TMS320F28377DPTPEP [TI]
具有 800MIPS、2xCPU、2xCLA、FPU、TMU、1MB 闪存、EMIF、16 位 ADC 的 C2000™ 增强型产品 32 位 MCU | PTP | 176 | -55 to 125;
| 型号： | TMS320F28377DPTPEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 800MIPS、2xCPU、2xCLA、FPU、TMU、1MB 闪存、EMIF、16 位 ADC 的 C2000™ 增强型产品 32 位 MCU | PTP | 176 | -55 to 125 闪存 |
| 文件： | 总210页 (文件大小：3302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMS320F28377D-EP
ZHCSHE0 –DECEMBER 2017
TMS320F28377D-EP 双核 Delfino™ 微控制器
1 器件概述
1.1 特性
1
– 两个多通道缓冲串行端口 (McBSP)
• 双核架构
– 四个串行通信接口 (SCI/UART)（引脚可引导）
– 两个 I2C 接口（引脚可引导）
• 模拟子系统
– 两个 TMS320C28x 32 位 CPU
– 200MHz
– IEEE-754 单精度浮点单元 (FPU)
– 三角法数学单元 (TMU)
– Viterbi / 复杂数学单元 (VCU-II)
• 两个可编程控制律加速器 (CLA)
– 200MHz
– IEEE 754 单精度浮点指令
– 独立于主 CPU 之外执行代码
• 片上存储器
– 多达四个模数转换器 (ADC)
– 16 位模式
–
每个转换器的吞吐量为 1.1MSPS（系统吞
吐量高达 4.4MSPS）
差分输入
–
–
多达 12 个外部通道
– 12 位模式
–
每个转换器的吞吐量为 3.5MSPS（系统吞
吐量高达 14MSPS）
单端输入
– 512KB (256KW) 或 1MB (512KW) 闪存（ECC
保护）
–
–
– 172KB (86KW) 或 204KB (102KW) RAM（ECC
保护或奇偶校验保护）
多达 24 个外部通道
– 每个 ADC 上有单个采样与保持 (S/H) 电路
– ADC 转换的硬件集成后置处理
– 支持第三方开发的双区安全
• 时钟和系统控制
–
–
–
–
饱和偏移校准
定点计算误差
– 两个内部零引脚 10MHz 振荡器
– 片上晶体振荡器
– 窗口化看门狗定时器模块
– 丢失时钟检测电路
具有中断功能的高、低和过零比较
触发至采样延迟捕捉
– 八个具有 12 位数模转换器 (DAC) 参考的窗口化
比较器
• 1.2V 内核，3.3V I/O 设计
• 系统外设
– 3 个 12 位缓冲 DAC 输出
• 增强型控制外设
– 两个支持 ASRAM 和 SDRAM 的外部存储器接口
(EMIF)
– 24 条具有增强功能的脉宽调制器 (PWM) 通道
– 16 条高分辨率脉宽调制器 (HRPWM) 通道
– 双 6 通道直接存储器存取 (DMA) 控制器
– 多达 169 个支持输入滤波的独立可编程、复用通
用输入/输出 (GPIO) 引脚
– 8 个 PWM 模块的 A 和 B 通道均可实现高分
辨率
– 扩展外设中断控制器 (ePIE)
– 死区支持（对于标准和高分辨率均支持）
– 6 个增强型捕捉 (eCAP) 模块
– 多个低功耗模式 (LPM)，支持通过外部器件唤醒
• 通信外设
– 3 个增强型正交编码器脉冲 (eQEP)模块
– USB 2.0 (MAC + PHY)
– 八条 Δ-Σ 滤波器模块 (SDFM) 输入通道，每条通
道 2 个并联滤波器
– 支持 12 引脚 3.3V 兼容通用并行端口 (uPP) 接口
– 两个控制器局域网 (CAN) 模块（引脚可引导）
– 三个高速（最高 50MHz）SPI 端口（引脚可引
导）
– 标准 SDFM 数据滤波
– 用于快速响应超范围情况的比较器滤波器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SPRSP19
TMS320F28377D-EP
ZHCSHE0 –DECEMBER 2017
www.ti.com.cn
• 封装选项：
– 一个制造场所
– 337 焊球全新细间距球栅阵列 (nFBGA) [后缀
– 在扩展温度范围（-55°C 至 125°C）内可用
– 延长的产品生命周期
GWT]
– 176 引脚 PowerPAD™散热增强型薄型四方扁平
封装 (HLQFP) [PTP 后缀]
• 支持国防、航天和医疗 应用：
– 受控基线
– 延长的产品变更通知
– 产品可追溯性
– 一个组装/测试场所
1.2 应用
•
•
•
•
•
•
高级驾驶员辅助系统 (ADAS)
楼宇自动化
•
•
•
•
•
•
工业运输
医疗、保健与健身
电机驱动器
电力输送
电子销售终端
电动汽车/混合动力电动汽车 (EV/HEV) 动力系统
工厂自动化
电信基础设施
测试和测量
电网基础设施
1.3 说明
Delfino™TMS320F28377D-EP 是一款强大的 32 位浮点微控制器单元 (MCU)，专为高级闭环控制 应用 而
设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。数
字电源和工业驱动器的完整开发包作为 powerSUITE 和 DesignDRIVE 方案的一部分提供。而 Delfino 产品
系列并不是 TMS320C2000™产品组合的新系列，但 F28377D 可支持新的双核 C28x 架构，进而显著提升
系统性能。此外，集成式模拟和控制外设还允许设计人员整合控制架构，并消除高端系统对多处理器的需
求。
双实时控制子系统基于 TI 的 32 位 C28x 浮点 CPU，每个内核均可提供 200MHz 的信号处理性能。C28x
CPU 的性能通过新型 TMU 加速器和 VCU 加速器得到了进一步提升，TMU 加速器可快速执行包含变换和转
矩环路计算中常见的三角运算的算法；VCU 加速器可缩短编码应用中常见的复杂数学运算的 时间中经常遇
到的特定频率下 OPAx189 的 EMIRR +IN 值。
F28377D 微控制器 具有 两个 CLA 实时控制协处理器。CLA 是一款独立的 32 位浮点处理器，运行速度与
主 CPU 相同。该 CLA 会对外设触发器作出响应，并与主 C28x CPU 同时执行代码。这种并行处理功能可
有效加倍实时控制系统的计算性能。通过利用 CLA 执行时间关键型功能，主 C28x CPU 可以得到释放，以
便用于执行通信和诊断等其他任务。双 C28x+CLA 架构可在各种系统任务之间实现智能分区。例如，一个
C28x+CLA 内核可用于跟踪速度和位置，而另一个 C28x+CLA 内核则可用于控制转矩和电流环路。
TMS320F28377D-EP 可支持 1MB (512KW) 的板载闪存内存，被配备错误校正代码 (ECC) 和 204KB
(102KW) 的 SRAM。每个 CPU 上还提供两个用于代码保护的 128 位安全区。
F28377D MCU 上集成了性能模拟和控制外设，以进一步支持系统整合。四个独立的 16 位 ADC 可准确、
高效地管理多个模拟信号，从而最终提高系统吞吐量。新型 Σ-Δ 滤波器模块 (SDFM) 与 Σ-Δ 调制器配合使
用可实现隔离分流测量。包含窗口化比较器的比较器子系统 (CMPSS) 可在超过或未满足电流限制条件的情
况下保护功率级。其他模拟和控制外设包括 DAC、PWM、eCAPs、eQEP 以及其他外设。
EMIF、CAN 模块（符合 ISO 11898-1/CAN 2.0B 标准）等外设以及新型 uPP 接口扩展了 F28377D 的连接
功能。uPP 接口是 C2000™MCU 的一个新特性，支持与 FPGA 之间或与具有类似 uPP 接口的其他处理器
之间的高速并行连接。最后，具有 MAC 和 PHY 的 USB 2.0 端口使用户能够轻松地将通用串行总线 (USB)
连接功能添加到其应用中。
Device Information(1)
PART NUMBER
PACKAGE
nFBGA (337)
HLQFP (176)
封装尺寸
16.0mm x 16.0mm
24.0mm × 24.0mm
TMS320F28377D-EP
(1) 有关这些器件的更多信息，请参阅机械封装和可订购信息。
器件概述
2
版权 © 2017, Texas Instruments Incorporated
TMS320F28377D-EP
www.ti.com.cn
ZHCSHE0 –DECEMBER 2017
1.4 功能框图
图 1-1 显示了 CPU 系统及相关外设。
User User
Configurable Configurable
PSWD
DCSM
OTP
1K x 16
DCSM
OTP
1K x 16
PSWD
Dual
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
FLASH
256K x 16
Secure
FLASH
256K x 16
Secure
Secure Memories
shown in Red
CPU2.CLA1
PUMP
OTP/Flash
Wrapper
OTP/Flash
Wrapper
MEMCPU1
MEMCPU2
Low-Power
Mode Control
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
GPIO MUX
INTOSC1
CPU2 to CPU2.CLA1
128x16 MSG RAM
CPU1.CLA1 to CPU1
128x16 MSG RAM
C28 CPU-1
FPU
VCU-II
C28 CPU-2
FPU
VCU-II
CPU1.CLA1
CPU1 to CPU1.CLA1
128x16 MSG RAM
CPU2.CLA1 to CPU2
128x16 MSG RAM
CPU2.M0 RAM 1Kx16
CPU2.M1 RAM 1Kx16
TMU
TMU
Watchdog 1/2
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
CPU2 Local Shared
6x 2Kx16
LS0-LS5 RAMs
Interprocessor
Communication
(IPC)
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
CPU2.D0 RAM 2Kx16
CPU2.D1 RAM 2Kx16
Main PLL
INTOSC2
Module
WD Timer
NMI-WDT
WD Timer
NMI-WDT
CPU1.CLA1 Data ROM
(4Kx16)
CPU2.CLA1 Data ROM
(4Kx16)
Global Shared
16x 4Kx16
GS0-GS15 RAMs
External Crystal or
Oscillator
CPU Timer 0
CPU Timer 1
CPU Timer 2
CPU Timer 0
CPU Timer 1
CPU Timer 2
Secure-ROM 32Kx16
Secure
Secure-ROM 32Kx16
Secure
A5:0
B5:0
C5:2
D5:0
16-/12-bit ADC
x4
Aux PLL
A
AUXCLKIN
CPU1 to CPU2
1Kx16 MSG RAM
B
C
D
Boot-ROM 32Kx16
Nonsecure
Boot-ROM 32Kx16
Nonsecure
ePIE
(up to 192
ePIE
(up to 192
ADC
Result
Regs
TRST
Analog
MUX
interrupts)
interrupts)
CPU2 to CPU1
1Kx16 MSG RAM
TCK
TDI
Config
JTAG
TMS
TDO
ADCIN14
ADCIN15
Data Bus
Bridge
CPU1.DMA
CPU2.DMA
Comparator
Subsystem
(CMPSS)
DAC
x3
CPU1 Buses
CPU2 Buses
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Peripheral Frame 1
Data Bus Bridge
Peripheral Frame 2
SCI-
A/B/C/D
(16L FIFO)
USB
Ctrl /
PHY
SPI-
A/B/C
(16L FIFO)
ePWM-1/../12
CAN-
A/B
(32-MBOX)
RAM
I2C-A/B
(16L FIFO)
McBSP-
A/B
eCAP-
1/../6
eQEP-1/2/3
SDFM-1/2
GPIO
EMIF1
EMIF2
uPP
HRPWM-1/../8
(CPU1 only)
GPIO MUX, Input X-BAR, Output X-BAR
Copyright © 2017, Texas Instruments Incorporated
图 1-1. 功能框图
版权 © 2017, Texas Instruments Incorporated
器件概述
3
TMS320F28377D-EP
ZHCSHE0 –DECEMBER 2017
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能框图 ............................................. 3
Revision History ......................................... 5
Terminal Configuration and Functions.............. 6
3.1 Pin Diagrams ......................................... 6
3.2 Signal Descriptions.................................. 13
3.3 Pins With Internal Pullup and Pulldown............. 36
3.4 Pin Multiplexing...................................... 37
3.5 Connections for Unused Pins ....................... 44
Specifications ........................................... 45
4.1 Absolute Maximum Ratings ........................ 45
4.2 ESD Ratings ........................................ 46
4.3 Recommended Operating Conditions............... 47
4.4 Power Consumption Summary...................... 48
4.5 Electrical Characteristics............................ 52
4.6 Thermal Resistance Characteristics ................ 53
4.7 System .............................................. 54
4.8 Analog Peripherals .................................. 90
4.9 Control Peripherals ................................ 116
4.10 Communications Peripherals ...................... 133
Detailed Description.................................. 169
5.1 Overview ........................................... 169
5.2 Functional Block Diagram ......................... 169
5.3 Memory ............................................ 171
5.4 Identification........................................ 178
5.5
Bus Architecture – Peripheral Connectivity........ 179
5.6 C28x Processor .................................... 180
5.7 Control Law Accelerator ........................... 183
5.8 Direct Memory Access............................. 184
2
3
5.9
Interprocessor Communication Module............ 186
5.10 Boot ROM and Peripheral Booting................. 187
5.11 Dual Code Security Module ....................... 190
5.12 Timers.............................................. 190
5.13 Nonmaskable Interrupt With Watchdog Timer
(NMIWD) ........................................... 190
5.14 Watchdog .......................................... 191
5.15 Configurable Logic Block (CLB) ................... 191
Applications, Implementation, and Layout ...... 192
6.1 TI Design or Reference Design.................... 192
器件和文档支持......................................... 193
7.1 器件和开发支持工具命名规则...................... 193
7.2 工具和软件 ......................................... 194
7.3 器件命名规则....................................... 195
7.4 文档支持 ........................................... 197
7.5 Community Resources............................. 197
7.6 商标 ................................................ 197
7.7 静电放电警告....................................... 198
7.8 出口管制提示....................................... 198
7.9 术语表.............................................. 198
机械封装和可订购信息................................. 199
8.1 Via Channel........................................ 199
8.2 封装信息 ........................................... 199
4
6
7
5
8
4
内容
版权 © 2017, Texas Instruments Incorporated
TMS320F28377D-EP
www.ti.com.cn
ZHCSHE0 –DECEMBER 2017
2 Revision History
注：之前版本的页码可能与当前版本有所不同。
DATE
REVISION
NOTES
2017 年 12 月
*
初始发行版
Copyright © 2017, Texas Instruments Incorporated
Revision History
5
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ZHCSHE0 –DECEMBER 2017
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3 Terminal Configuration and Functions
3.1 Pin Diagrams
Figure 3-1 to Figure 3-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid
Array. Each figure shows a quadrant of the terminal assignments. Figure 3-5 shows the pin assignments
on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack.
1
2
3
4
5
6
7
8
9
10
GPIO116
VSSA
VREFHIB
VREFLOD
VSS
VDDIO
W
ADCINB1
ADCINB3
ADCINB5
GPIO128
W
V
U
T
VREFHIA
ADCINA0
ADCINA1
VREFHIC
VSSA
VREFHID
ADCIND1
ADCIND0
VSSA
VREFLOB
ADCIND3
ADCIND2
VDDA
VSSA
ADCIND5
ADCIND4
VSS
V
ADCINB0
ADCINA2
ADCINA3
VREFLOA
VREFLOC
GPIO109
GPIO110
GPIO106
ADCINB2
ADCINA4
ADCINA5
ADCINC2
ADCINC3
GPIO114
GPIO112
GPIO107
ADCINB4
ADCIN15
ADCIN14
ADCINC4
ADCINC5
GPIO113
GPIO111
GPIO108
GPIO124
GPIO123
GPIO122
VSS
GPIO127
GPIO126
GPIO125
VDDIO
GPIO131
GPIO130
GPIO129
VDD
U
T
R
P
N
M
L
R
P
VSSA
VDDA
VSS
VSS
VDDIO
VDD
7
8
9
10
VSS
VSS
VSS
N
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
M
M
VSS
VSS
VSS
VSS
VSS
GPIO27
L
L
VDD
VDD
VSS
VSS
VSS
K
GPIO26
GPIO25
GPIO24
GPIO23
K
K
1
2
3
4
5
6
8
9
10
A. Only the GPIO function is shown on GPIO terminals. See Table 3-1 for the complete, muxed signal name.
Figure 3-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]
6
Terminal Configuration and Functions
Copyright © 2017, Texas Instruments Incorporated
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11
12
13
14
15
16
17
18
19
VSS
W
V
U
T
GPIO29
FLT1
TDI
TMS
TDO
GPIO121
GPIO39
GPIO132
GPIO134
GPIO135
GPIO137
GPIO50
GPIO54
GPIO57
GPIO141
VSS
W
V
U
T
VDDIO
ERRORSTS
GPIO138
GPIO51
GPIO28
GPIO31
GPIO30
VDD3VFL
GPIO115
GPIO117
GPIO118
VDD3VFL
FLT2
GPIO32
GPIO33
VDD
TCK
GPIO120
GPIO119
VSS
GPIO36
GPIO37
GPIO38
GPIO48
GPIO52
GPIO56
GPIO59
GPIO61
GPIO40
GPIO41
GPIO136
GPIO49
GPIO53
GPIO58
GPIO60
GPIO64
TRST
GPIO34
GPIO35
VSS
R
R
P
N
M
L
VSS
VSS
VDD
VSS
VSS
P
GPIO55
11
12
13
N
VDDIO
VDDIO
GPIO139
GPIO140
GPIO142
VSS
VSS
VSS
VSS
M
M
VSS
VSS
VDDIO
VDDIO
L
L
VSS
VSS
VSS
VSS
K
K
GPIO65
GPIO66
GPIO44
GPIO45
K
11
12
14
15
16
17
18
19
A. Only the GPIO function is shown on GPIO terminals. See Table 3-1 for the complete, muxed signal name.
Figure 3-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]
Copyright © 2017, Texas Instruments Incorporated
Terminal Configuration and Functions
7
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11
12
14
15
16
17
18
19
VSS
VSS
VDD
VDD
J
J
H
G
GPIO63
GPIO62
VREGENZ
X2
J
VSS
VSS
VSS
VSS
VDDOSC
VDDOSC
VSSOSC
GPIO133
GPIO143
GPIO47
GPIO146
GPIO68
GPIO69
VSSOSC
H
H
G
F
VDD
VDD
VSS
VSS
X1
11
12
13
VDD
VSS
VDDIO
VSS
VSS
VDDIO
F
E
D
C
B
A
GPIO144
GPIO145
GPIO147
GPIO74
GPIO71
XRS
VDD
VSS
VDDIO
VSS
VSS
VDDIO
GPIO46
GPIO42
GPIO43
GPIO67
E
D
C
B
A
GPIO87
GPIO86
GPIO85
GPIO156
GPIO155
GPIO154
GPIO152
GPIO151
GPIO150
GPIO148
GPIO83
GPIO82
GPIO80
GPIO79
GPIO78
GPIO75
GPIO76
GPIO72
VDDIO
VSS
GPIO84
GPIO153
GPIO149
GPIO81
GPIO77
GPIO73
GPIO70
11
12
13
14
15
16
17
18
19
A. Only the GPIO function is shown on GPIO terminals. See Table 3-1 for the complete, muxed signal name.
Figure 3-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]
8
Terminal Configuration and Functions
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ZHCSHE0 –DECEMBER 2017
1
2
3
4
5
6
8
9
10
VSS
VSS
VSS
VSS
VSS
J
H
G
F
GPIO103
GPIO100
GPIO99
GPIO98
GPIO16
GPIO13
GPIO11
VDDIO
GPIO104
GPIO105
GPIO22
J
J
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
VSS
GPIO101
GPIO102
NC
H
G
H
VDDIO
VDDIO
GPIO8
GPIO9
7
8
9
10
VDDIO
VSS
VDDIO
VSS
VDD
VDDIO
GPIO20
GPIO17
GPIO14
GPIO12
GPIO10
GPIO21
GPIO18
GPIO15
GPIO96
GPIO95
F
VSS
VSS
VDDIO
VSS
VDD
VDDIO
E
D
C
B
A
GPIO19
GPIO168
GPIO167
GPIO93
E
D
C
B
A
GPIO166
GPIO165
GPIO91
GPIO89
GPIO88
GPIO7
GPIO5
GPIO4
GPIO3
GPIO1
GPIO0
GPIO164
GPIO162
GPIO161
GPIO160
GPIO159
GPIO158
GPIO157
VSS
VDDIO
VSS
GPIO97
GPIO94
GPIO92
GPIO90
GPIO6
GPIO2
GPIO163
1
2
3
4
5
6
7
8
9
10
A. Only the GPIO function is shown on GPIO terminals. See Table 3-1 for the complete, muxed signal name.
Figure 3-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]
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V
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
GPIO68
GPIO69
GPIO70
GPIO71
DDIO
GPIO40
GPIO39
GPIO38
GPIO37
GPIO36
V
DD
V
DDIO
V
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
DDIO
TCK
TMS
TRST
TDO
TDI
V
DD
V
DDIO
V
DDIO
FLT2
FLT1
V
GPIO80
GPIO81
GPIO82
GPIO83
DD3VFL
GPIO35
GPIO34
GPIO33
V
DDIO
V
V
DDIO
DD
GPIO32
GPIO31
GPIO29
GPIO28
GPIO30
GPIO84
GPIO85
GPIO86
GPIO87
V
DD
V
V
DDIO
DDIO
V
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
DD
ADCIND4
ADCIND3
ADCIND2
ADCIND1
ADCIND0
V
REFHID
V
DDA
V
V
REFHIB
DDIO
V
V
SSA
DD
V
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
REFLOD
V
REFLOB
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCIN15
A. Only the GPIO function is shown on GPIO pins. See Table 3-1 for the complete, muxed signal name.
Figure 3-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)
10
Terminal Configuration and Functions
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NOTE
The exposed lead frame die pad of the PowerPAD™ package serves two functions: to
remove heat from the die and to provide ground path for the digital ground (analog ground is
provided through dedicated pins). Thus, the PowerPAD should be soldered to the ground
(GND) plane of the PCB because this will provide both the digital ground path and good
thermal conduction path. To make optimum use of the thermal efficiencies designed into the
PowerPAD package, the PCB must be designed with this technology in mind. A thermal land
is required on the surface of the PCB directly underneath the body of the PowerPAD. The
thermal land should be soldered to the exposed lead frame die pad of the PowerPAD
package; the thermal land should be as large as needed to dissipate the required heat. An
array of thermal vias should be used to connect the thermal pad to the internal GND plane of
the board. See PowerPAD™ Thermally Enhanced Package for more details on using the
PowerPAD package.
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NOTE
PCB footprints and schematic symbols are available for download in a vendor-neutral format,
which can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE
Symbols section in the product folder for each device, under the Packaging section. These
footprints and symbols can also be searched for at http://webench.ti.com/cad/.
12
Terminal Configuration and Functions
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3.2 Signal Descriptions
Table 3-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned.
The peripheral signals that are listed under them are alternate functions. Some peripheral functions may
not be available in all devices. All GPIO pins are I/O/Z and have an internal pullup, which can be
selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups
are not enabled at reset.
Table 3-1. Signal Descriptions
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
ADC, DAC, AND COMPARATOR SIGNALS
ADC-A high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should
be placed as close to the device as possible between
the VREFHIA and VREFLOA pins.
VREFHIA
VREFHIB
VREFHIC
V1
W5
R1
37
53
35
I
I
I
NOTE: Do not load this pin externally.
ADC-B high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should
be placed as close to the device as possible between
the VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
ADC-C high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should
be placed as close to the device as possible between
the VREFHIC and VREFLOC pins.
NOTE: Do not load this pin externally.
ADC-D high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should
be placed as close to the device as possible between
the VREFHID and VREFLOD pins.
VREFHID
V5
R2
55
33
I
I
NOTE: Do not load this pin externally.
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. On the PZP package, pin 17 must be
connected to VSSA on the system board.
VREFLOA
VREFLOB
VREFLOC
VREFLOD
ADCIN14
V6
P2
50
32
51
I
I
I
I
ADC-B low reference
ADC-C low reference
ADC-D low reference
W6
Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all
ADCs together (either single-ended or differential) from
an external reference.
T4
U4
44
45
CMPIN4P
ADCIN15
I
I
Comparator 4 positive input
Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all
ADCs together (either single-ended or differential) from
an external reference.
CMPIN4N
I
Comparator 4 negative input
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
ADCINA0
I
ADC-A input 0. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode which
cannot be disabled.
U1
T1
43
42
DACOUTA
ADCINA1
O
I
DAC-A output
ADC-A input 1. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTB
ADCINA2
CMPIN1P
ADCINA3
CMPIN1N
ADCINA4
CMPIN2P
ADCINA5
CMPIN2N
ADCINB0
O
I
DAC-B output
ADC-A input 2
U2
T2
U3
T3
41
40
39
38
I
Comparator 1 positive input
ADC-A input 3
I
I
Comparator 1 negative input
ADC-A input 4
I
I
Comparator 2 positive input
ADC-A input 5
I
I
Comparator 2 negative input
I
ADC-B input 0. There is a 100-pF capacitor to VSSA on
this pin in both ADC input or DAC reference mode which
cannot be disabled. If this pin is being used as a
reference for the on-chip DACs, place at least a 1-µF
capacitor on this pin.
V2
46
VDAC
I
Optional external reference voltage for on-chip DACs.
There is a 100-pF capacitor to VSSA on this pin in both
ADC input or DAC reference mode which cannot be
disabled. If this pin is being used as a reference for the
on-chip DACs, place at least a 1-µF capacitor on this
pin.
ADCINB1
I
ADC-B input 1. There is a 50-kΩ internal pulldown on
this pin in both an ADC input or DAC output mode which
cannot be disabled.
W2
47
DACOUTC
ADCINB2
CMPIN3P
ADCINB3
CMPIN3N
ADCINB4
ADCINB5
ADCINC2
CMPIN6P
ADCINC3
CMPIN6N
ADCINC4
CMPIN5P
ADCINC5
CMPIN5N
ADCIND0
CMPIN7P
ADCIND1
CMPIN7N
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DAC-C output
ADC-B input 2
V3
48
49
Comparator 3 positive input
ADC-B input 3
W3
Comparator 3 negative input
ADC-B input 4
V4
–
–
W4
ADC-B input 5
ADC-C input 2
R3
P3
R4
P4
T5
U5
31
30
29
–
Comparator 6 positive input
ADC-C input 3
Comparator 6 negative input
ADC-C input 4
Comparator 5 positive input
ADC-C input 5
Comparator 5 negative input
ADC-D input 0
56
57
Comparator 7 positive input
ADC-D input 1
Comparator 7 negative input
14
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
ADCIND2
CMPIN8P
ADCIND3
CMPIN8N
ADCIND4
ADCIND5
I
I
I
I
I
I
ADC-D input 2
T6
U6
58
59
Comparator 8 positive input
ADC-D input 3
Comparator 8 negative input
ADC-D input 4
T7
U7
60
—
ADC-D input 5
GPIO AND PERIPHERAL SIGNALS
GPIO0
0, 4, 8, 12
I/O
O
General-purpose input/output 0
Enhanced PWM1 output A (HRPWM-capable)
EPWM1A
SDAA
1
C8
D8
160
161
6
I/OD
I/O
O
I2C-A data open-drain bidirectional port
General-purpose input/output 1
Enhanced PWM1 output B (HRPWM-capable)
McBSP-B receive frame synch
I2C-A clock open-drain bidirectional port
General-purpose input/output 2
Enhanced PWM2 output A (HRPWM-capable)
Output 1 of the output XBAR
GPIO1
0, 4, 8, 12
EPWM1B
MFSRB
1
3
I/O
I/OD
I/O
O
SCLA
6
GPIO2
0, 4, 8, 12
EPWM2A
OUTPUTXBAR1
SDAB
1
A7
B7
162
163
5
O
6
I/OD
I/O
O
I2C-B data open-drain bidirectional port
General-purpose input/output 3
Enhanced PWM2 output B (HRPWM-capable)
Output 2 of the output XBAR
GPIO3
0, 4, 8, 12
EPWM2B
OUTPUTXBAR2
MCLKRB
OUTPUTXBAR2
SCLB
1
2
O
3
I/O
O
McBSP-B receive clock
5
Output 2 of the output XBAR
6
I/OD
I/O
O
I2C-B clock open-drain bidirectional port
General-purpose input/output 4
Enhanced PWM3 output A (HRPWM-capable)
Output 3 of the output XBAR
GPIO4
0, 4, 8, 12
EPWM3A
OUTPUTXBAR3
CANTXA
GPIO5
1
C7
D7
164
165
5
O
6
O
CAN-A transmit
0, 4, 8, 12
I/O
O
General-purpose input/output 5
Enhanced PWM3 output B (HRPWM-capable)
McBSP-A receive frame synch
Output 3 of the output XBAR
EPWM3B
MFSRA
1
2
I/O
O
OUTPUTXBAR3
CANRXA
GPIO6
3
6
I
CAN-A receive
0, 4, 8, 12
I/O
O
General-purpose input/output 6
Enhanced PWM4 output A (HRPWM-capable)
Output 4 of the output XBAR
EPWM4A
OUTPUTXBAR4
EXTSYNCOUT
EQEP3A
1
2
O
A6
B6
166
167
3
O
External ePWM synch pulse output
Enhanced QEP3 input A
5
I
CANTXB
GPIO7
6
O
CAN-B transmit
0, 4, 8, 12
I/O
O
General-purpose input/output 7
Enhanced PWM4 output B (HRPWM-capable)
McBSP-A receive clock
EPWM4B
MCLKRA
OUTPUTXBAR5
EQEP3B
1
2
3
5
6
I/O
O
Output 5 of the output XBAR
I
Enhanced QEP3 input B
CANRXB
I
CAN-B receive
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO8
0, 4, 8, 12
I/O
O
General-purpose input/output 8
EPWM5A
CANTXB
ADCSOCAO
EQEP3S
1
Enhanced PWM5 output A (HRPWM-capable)
CAN-B transmit
2
O
G2
G3
18
19
3
O
ADC start-of-conversion A output for external ADC
Enhanced QEP3 strobe
5
I/O
O
SCITXDA
GPIO9
6
SCI-A transmit data
0, 4, 8, 12
I/O
O
General-purpose input/output 9
Enhanced PWM5 output B (HRPWM-capable)
SCI-B transmit data
EPWM5B
SCITXDB
OUTPUTXBAR6
EQEP3I
1
2
O
3
O
Output 6 of the output XBAR
Enhanced QEP3 index
5
I/O
I
SCIRXDA
GPIO10
6
SCI-A receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 10
Enhanced PWM6 output A (HRPWM-capable)
CAN-B receive
EPWM6A
CANRXB
ADCSOCBO
EQEP1A
1
2
I
3
O
ADC start-of-conversion B output for external ADC
Enhanced QEP1 input A
B2
C1
C2
1
2
4
5
I
SCITXDB
UPP-WAIT
6
O
SCI-B transmit data
15
I/O
Universal parallel port wait. Receiver asserts to request
a pause in transfer.
GPIO11
0, 4, 8, 12
I/O
O
I
General-purpose input/output 11
Enhanced PWM6 output B (HRPWM-capable)
SCI-B receive data
EPWM6B
1
2, 6
3
SCIRXDB
OUTPUTXBAR7
EQEP1B
O
I
Output 7 of the output XBAR
Enhanced QEP1 input B
5
UPP-START
15
I/O
Universal parallel port start. Transmitter asserts at start
of DMA line.
GPIO12
EPWM7A
CANTXB
MDXB
0, 4, 8, 12
I/O
O
General-purpose input/output 12
Enhanced PWM7 output A (HRPWM-capable)
CAN-B transmit
1
2
O
3
O
McBSP-B transmit serial data
Enhanced QEP1 strobe
EQEP1S
SCITXDC
UPP-ENA
5
I/O
O
6
SCI-C transmit data
15
I/O
Universal parallel port enable. Transmitter asserts while
data bus is active.
GPIO13
EPWM7B
CANRXB
MDRB
0, 4, 8, 12
I/O
O
I
General-purpose input/output 13
Enhanced PWM7 output B (HRPWM-capable)
CAN-B receive
1
2
3
D1
5
I
McBSP-B receive serial data
Enhanced QEP1 index
EQEP1I
SCIRXDC
UPP-D7
5
I/O
I
6
SCI-C receive data
15
I/O
Universal parallel port data line 7
16
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO14
0, 4, 8, 12
I/O
O
General-purpose input/output 14
Enhanced PWM8 output A (HRPWM-capable)
SCI-B transmit data
EPWM8A
SCITXDB
MCLKXB
OUTPUTXBAR3
UPP-D6
1
2
O
D2
D3
6
7
3
I/O
O
McBSP-B transmit clock
6
Output 3 of the output XBAR
Universal parallel port data line 6
General-purpose input/output 15
Enhanced PWM8 output B (HRPWM-capable)
SCI-B receive data
15
I/O
I/O
O
GPIO15
0, 4, 8, 12
EPWM8B
SCIRXDB
MFSXB
1
2
I
3
I/O
O
McBSP-B transmit frame synch
Output 4 of the output XBAR
Universal parallel port data line 5
General-purpose input/output 16
SPI-A slave in, master out
CAN-B transmit
OUTPUTXBAR4
UPP-D5
6
15
I/O
I/O
I/O
O
GPIO16
0, 4, 8, 12
SPISIMOA
CANTXB
OUTPUTXBAR7
EPWM9A
SD1_D1
1
2
3
E1
E2
E3
E4
8
O
Output 7 of the output XBAR
Enhanced PWM9 output A
Sigma-Delta 1 channel 1 data input
Universal parallel port data line 4
General-purpose input/output 17
SPI-A slave out, master in
CAN-B receive
5
O
7
I
UPP-D4
15
I/O
I/O
I/O
I
GPIO17
0, 4, 8, 12
SPISOMIA
CANRXB
OUTPUTXBAR8
EPWM9B
SD1_C1
1
2
3
9
O
Output 8 of the output XBAR
Enhanced PWM9 output B
Sigma-Delta 1 channel 1 clock input
Universal parallel port data line 3
General-purpose input/output 18
SPI-A clock
5
O
7
I
UPP-D3
15
I/O
I/O
I/O
O
GPIO18
0, 4, 8, 12
SPICLKA
SCITXDB
CANRXA
EPWM10A
SD1_D2
1
2
SCI-B transmit data
3
10
I
CAN-A receive
5
O
Enhanced PWM10 output A
Sigma-Delta 1 channel 2 data input
Universal parallel port data line 2
General-purpose input/output 19
SPI-A slave transmit enable
SCI-B receive data
7
I
UPP-D2
15
I/O
I/O
I/O
I
GPIO19
0, 4, 8, 12
SPISTEA
SCIRXDB
CANTXA
EPWM10B
SD1_C2
1
2
3
12
O
CAN-A transmit
5
O
Enhanced PWM10 output B
Sigma-Delta 1 channel 2 clock input
Universal parallel port data line 1
7
I
UPP-D1
15
I/O
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO20
0, 4, 8, 12
I/O
I
General-purpose input/output 20
Enhanced QEP1 input A
EQEP1A
MDXA
1
2
O
O
O
I
McBSP-A transmit serial data
CAN-B transmit
CANTXB
EPWM11A
SD1_D3
UPP-D0
3
F2
F3
J4
K4
13
14
22
23
5
Enhanced PWM11 output A
Sigma-Delta 1 channel 3 data input
Universal parallel port data line 0
General-purpose input/output 21
Enhanced QEP1 input B
7
15
I/O
I/O
I
GPIO21
0, 4, 8, 12
EQEP1B
MDRA
1
2
I
McBSP-A receive serial data
CAN-B receive
CANRXB
EPWM11B
SD1_C3
UPP-CLK
GPIO22
3
I
5
O
I
Enhanced PWM11 output B
Sigma-Delta 1 channel 3 clock input
Universal parallel port transmit clock
General-purpose input/output 22
Enhanced QEP1 strobe
7
15
I/O
I/O
I/O
I/O
O
O
I/O
I
0, 4, 8, 12
EQEP1S
MCLKXA
SCITXDB
EPWM12A
SPICLKB
SD1_D4
GPIO23
1
2
McBSP-A transmit clock
3
SCI-B transmit data
5
Enhanced PWM12 output A
SPI-B clock
6
7
Sigma-Delta 1 channel 4 data input
General-purpose input/output 23
Enhanced QEP1 index
0, 4, 8, 12
I/O
I/O
I/O
I
EQEP1I
1
MFSXA
2
McBSP-A transmit frame synch
SCI-B receive data
SCIRXDB
EPWM12B
SPISTEB
SD1_C4
GPIO24
3
5
O
I/O
I
Enhanced PWM12 output B
SPI-B slave transmit enable
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 24
Output 1 of the output XBAR
Enhanced QEP2 input A
6
7
0, 4, 8, 12
I/O
O
I
OUTPUTXBAR1
EQEP2A
MDXB
1
2
K3
K2
24
25
3
O
I/O
I
McBSP-B transmit serial data
SPI-B slave in, master out
Sigma-Delta 2 channel 1 data input
General-purpose input/output 25
Output 2 of the output XBAR
Enhanced QEP2 input B
SPISIMOB
SD2_D1
GPIO25
6
7
0, 4, 8, 12
I/O
O
I
OUTPUTXBAR2
EQEP2B
MDRB
1
2
3
6
7
I
McBSP-B receive serial data
SPI-B slave out, master in
Sigma-Delta 2 channel 1 clock input
SPISOMIB
SD2_C1
I/O
I
18
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO26
0, 4, 8, 12
I/O
O
General-purpose input/output 26
Output 3 of the output XBAR
Enhanced QEP2 index
OUTPUTXBAR3
EQEP2I
1
2
I/O
I/O
O
MCLKXB
OUTPUTXBAR3
SPICLKB
SD2_D2
3
K1
27
McBSP-B transmit clock
5
Output 3 of the output XBAR
SPI-B clock
6
I/O
I
7
Sigma-Delta 2 channel 2 data input
General-purpose input/output 27
Output 4 of the output XBAR
Enhanced QEP2 strobe
GPIO27
0, 4, 8, 12
I/O
O
OUTPUTXBAR4
EQEP2S
1
2
I/O
I/O
O
MFSXB
3
L1
28
McBSP-B transmit frame synch
Output 4 of the output XBAR
SPI-B slave transmit enable
Sigma-Delta 2 channel 2 clock input
General-purpose input/output 28
SCI-A receive data
OUTPUTXBAR4
SPISTEB
SD2_C2
5
6
I/O
I
7
GPIO28
0, 4, 8, 12
I/O
I
SCIRXDA
EM1CS4
1
2
O
External memory interface 1 chip select 4
Output 5 of the output XBAR
Enhanced QEP3 input A
V11
W11
T11
U11
64
65
63
66
OUTPUTXBAR5
EQEP3A
5
O
6
I
SD2_D3
7
I
Sigma-Delta 2 channel 3 data input
General-purpose input/output 29
SCI-A transmit data
GPIO29
0, 4, 8, 12
I/O
O
SCITXDA
EM1SDCKE
OUTPUTXBAR6
EQEP3B
1
2
O
External memory interface 1 SDRAM clock enable
Output 6 of the output XBAR
Enhanced QEP3 input B
5
O
6
I
SD2_C3
7
I
Sigma-Delta 2 channel 3 clock input
General-purpose input/output 30
CAN-A receive
GPIO30
0, 4, 8, 12
I/O
I
CANRXA
EM1CLK
1
2
O
External memory interface 1 clock
Output 7 of the output XBAR
Enhanced QEP3 strobe
OUTPUTXBAR7
EQEP3S
5
O
6
I/O
I
SD2_D4
7
Sigma-Delta 2 channel 4 data input
General-purpose input/output 31
CAN-A transmit
GPIO31
0, 4, 8, 12
I/O
O
CANTXA
1
EM1WE
2
O
External memory interface 1 write enable
Output 8 of the output XBAR
Enhanced QEP3 index
OUTPUTXBAR8
EQEP3I
5
O
6
I/O
I
SD2_C4
7
Sigma-Delta 2 channel 4 clock input
General-purpose input/output 32
I2C-A data open-drain bidirectional port
External memory interface 1 chip select 0
General-purpose input/output 33
I2C-A clock open-drain bidirectional port
External memory interface 1 read not write
GPIO32
0, 4, 8, 12
I/O
I/OD
O
SDAA
1
U13
T13
67
69
EM1CS0
2
GPIO33
0, 4, 8, 12
I/O
I/OD
O
SCLA
1
2
EM1RNW
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO34
0, 4, 8, 12
I/O
O
General-purpose input/output 34
Output 1 of the output XBAR
OUTPUTXBAR1
EM1CS2
SDAB
1
U14
T14
V16
U16
T16
70
71
83
84
85
2
O
External memory interface 1 chip select 2
I2C-B data open-drain bidirectional port
General-purpose input/output 35
SCI-A receive data
6
I/OD
I/O
I
GPIO35
0, 4, 8, 12
SCIRXDA
EM1CS3
SCLB
1
2
O
External memory interface 1 chip select 3
I2C-B clock open-drain bidirectional port
General-purpose input/output 36
SCI-A transmit data
6
I/OD
I/O
O
GPIO36
0, 4, 8, 12
SCITXDA
EM1WAIT
CANRXA
GPIO37
1
2
I
External memory interface 1 Asynchronous SRAM WAIT
CAN-A receive
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 37
Output 2 of the output XBAR
External memory interface 1 output enable
CAN-A transmit
OUTPUTXBAR2
EM1OE
1
2
O
CANTXA
GPIO38
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 38
External memory interface 1 address line 0
SCI-C transmit data
EM1A0
2
SCITXDC
CANTXB
GPIO39
5
O
6
O
CAN-B transmit
0, 4, 8, 12
I/O
O
General-purpose input/output 39
External memory interface 1 address line 1
SCI-C receive data
EM1A1
2
W17
V17
86
87
SCIRXDC
CANRXB
GPIO40
5
I
6
I
CAN-B receive
0, 4, 8, 12
I/O
O
General-purpose input/output 40
External memory interface 1 address line 2
I2C-B data open-drain bidirectional port
EM1A2
2
6
SDAB
I/OD
I/O
GPIO41
0, 4, 8, 12
General-purpose input/output 41. For applications using
the Hibernate low-power mode, this pin serves as the
GPIOHIBWAKE signal. For details, see the Low Power
Modes section of the System Control chapter in the
TMS320F2837xD Dual-Core Delfino Microcontrollers
Technical Reference Manual.
U17
D19
89
EM1A3
SCLB
2
O
I/OD
I/O
I/OD
O
External memory interface 1 address line 3
I2C-B clock open-drain bidirectional port
General-purpose input/output 42
I2C-A data open-drain bidirectional port
SCI-A transmit data
6
GPIO42
SDAA
0, 4, 8, 12
6
15
130
SCITXDA
USB0DM
GPIO43
SCLA
Analog
0, 4, 8, 12
6
I/O
I/O
I/OD
I
USB PHY differential data
General-purpose input/output 43
I2C-A clock open-drain bidirectional port
SCI-A receive data
C19
K18
131
113
SCIRXDA
USB0DP
GPIO44
EM1A4
15
Analog
0, 4, 8, 12
2
I/O
I/O
O
USB PHY differential data
General-purpose input/output 44
External memory interface 1 address line 4
20
Terminal Configuration and Functions
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ZHCSHE0 –DECEMBER 2017
Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO45
0, 4, 8, 12
I/O
O
General-purpose input/output 45
External memory interface 1 address line 5
General-purpose input/output 46
External memory interface 1 address line 6
SCI-D receive data
K19
115
EM1A5
2
GPIO46
0, 4, 8, 12
I/O
O
EM1A6
2
E19
128
SCIRXDD
GPIO47
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 47
External memory interface 1 address line 7
SCI-D transmit data
EM1A7
2
E18
R16
129
90
SCITXDD
GPIO48
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 48
Output 3 of the output XBAR
OUTPUTXBAR3
EM1A8
1
2
O
External memory interface 1 address line 8
SCI-A transmit data
SCITXDA
SD1_D1
GPIO49
6
O
7
I
Sigma-Delta 1 channel 1 data input
General-purpose input/output 49
Output 4 of the output XBAR
0, 4, 8, 12
I/O
O
OUTPUTXBAR4
EM1A9
1
2
R17
R18
R19
P16
93
94
95
96
O
External memory interface 1 address line 9
SCI-A receive data
SCIRXDA
SD1_C1
GPIO50
6
I
7
I
Sigma-Delta 1 channel 1 clock input
General-purpose input/output 50
Enhanced QEP1 input A
0, 4, 8, 12
I/O
I
EQEP1A
EM1A10
SPISIMOC
SD1_D2
GPIO51
1
2
O
External memory interface 1 address line 10
SPI-C slave in, master out
6
I/O
I
7
Sigma-Delta 1 channel 2 data input
General-purpose input/output 51
Enhanced QEP1 input B
0, 4, 8, 12
I/O
I
EQEP1B
EM1A11
SPISOMIC
SD1_C2
GPIO52
1
2
O
External memory interface 1 address line 11
SPI-C slave out, master in
6
I/O
I
7
Sigma-Delta 1 channel 2 clock input
General-purpose input/output 52
Enhanced QEP1 strobe
0, 4, 8, 12
I/O
I/O
O
EQEP1S
EM1A12
SPICLKC
SD1_D3
GPIO53
1
2
External memory interface 1 address line 12
SPI-C clock
6
I/O
I
7
Sigma-Delta 1 channel 3 data input
General-purpose input/output 53
Enhanced QEP1 index
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I
EQEP1I
1
2
3
6
7
EM1D31
EM2D15
SPISTEC
SD1_C3
External memory interface 1 data line 31
External memory interface 2 data line 15
SPI-C slave transmit enable
P17
97
Sigma-Delta 1 channel 3 clock input
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO54
0, 4, 8, 12
I/O
I/O
I/O
I/O
I
General-purpose input/output 54
SPI-A slave in, master out
SPISIMOA
EM1D30
EM2D14
EQEP2A
SCITXDB
SD1_D4
GPIO55
1
2
External memory interface 1 data line 30
External memory interface 2 data line 14
Enhanced QEP2 input A
3
P18
P19
N16
N18
98
5
6
O
SCI-B transmit data
7
I
Sigma-Delta 1 channel 4 data input
General-purpose input/output 55
SPI-A slave out, master in
0, 4, 8, 12
I/O
I/O
I/O
I/O
I
SPISOMIA
EM1D29
EM2D13
EQEP2B
SCIRXDB
SD1_C4
GPIO56
1
2
External memory interface 1 data line 29
External memory interface 2 data line 13
Enhanced QEP2 input B
3
100
101
102
5
6
I
SCI-B receive data
7
I
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 56
SPI-A clock
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
O
SPICLKA
EM1D28
EM2D12
EQEP2S
SCITXDC
SD2_D1
GPIO57
1
2
External memory interface 1 data line 28
External memory interface 2 data line 12
Enhanced QEP2 strobe
3
5
6
SCI-C transmit data
7
I
Sigma-Delta 2 channel 1 data input
General-purpose input/output 57
SPI-A slave transmit enable
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I
SPISTEA
EM1D27
EM2D11
EQEP2I
1
2
External memory interface 1 data line 27
External memory interface 2 data line 11
Enhanced QEP2 index
3
5
SCIRXDC
SD2_C1
GPIO58
6
SCI-C receive data
7
I
Sigma-Delta 2 channel 1 clock input
General-purpose input/output 58
McBSP-A receive clock
0, 4, 8, 12
I/O
I/O
I/O
I/O
O
MCLKRA
EM1D26
EM2D10
OUTPUTXBAR1
SPICLKB
SD2_D2
SPISIMOA
GPIO59
1
2
External memory interface 1 data line 26
External memory interface 2 data line 10
Output 1 of the output XBAR
SPI-B clock
3
N17
103
5
6
I/O
I
7
Sigma-Delta 2 channel 2 data input
SPI-A slave in, master out(2)
15
I/O
I/O
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 59(3)
McBSP-A receive frame synch
External memory interface 1 data line 25
External memory interface 2 data line 9
Output 2 of the output XBAR
SPI-B slave transmit enable
MFSRA
1
2
EM1D25
EM2D9
3
M16
104
OUTPUTXBAR2
SPISTEB
SD2_C2
SPISOMIA
5
6
I/O
I
7
Sigma-Delta 2 channel 2 clock input
SPI-A slave out, master in(2)
15
I/O
22
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO60
0, 4, 8, 12
I/O
I/O
I/O
I/O
O
General-purpose input/output 60
McBSP-B receive clock
MCLKRB
EM1D24
EM2D8
1
2
External memory interface 1 data line 24
External memory interface 2 data line 8
Output 3 of the output XBAR
SPI-B slave in, master out
3
M17
105
OUTPUTXBAR3
SPISIMOB
SD2_D3
SPICLKA
GPIO61
5
6
I/O
I
7
Sigma-Delta 2 channel 3 data input
SPI-A clock(2)
15
I/O
I/O
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 61(3)
McBSP-B receive frame synch
External memory interface 1 data line 23
External memory interface 2 data line 7
Output 4 of the output XBAR
SPI-B slave out, master in
MFSRB
1
EM1D23
EM2D7
2
3
L16
J17
J16
107
108
109
OUTPUTXBAR4
SPISOMIB
SD2_C3
SPISTEA
GPIO62
5
6
I/O
I
7
Sigma-Delta 2 channel 3 clock input
SPI-A slave transmit enable(2)
General-purpose input/output 62
SCI-C receive data
15
I/O
I/O
I
0, 4, 8, 12
SCIRXDC
EM1D22
EM2D6
1
2
I/O
I/O
I
External memory interface 1 data line 22
External memory interface 2 data line 6
Enhanced QEP3 input A
3
EQEP3A
CANRXA
SD2_D4
GPIO63
5
6
I
CAN-A receive
7
I
Sigma-Delta 2 channel 4 data input
General-purpose input/output 63
SCI-C transmit data
0, 4, 8, 12
I/O
O
SCITXDC
EM1D21
EM2D5
1
2
I/O
I/O
I
External memory interface 1 data line 21
External memory interface 2 data line 5
Enhanced QEP3 input B
3
EQEP3B
CANTXA
SD2_C4
SPISIMOB
GPIO64
5
6
O
CAN-A transmit
7
I
Sigma-Delta 2 channel 4 clock input
SPI-B slave in, master out(2)
General-purpose input/output 64(3)
External memory interface 1 data line 20
External memory interface 2 data line 4
Enhanced QEP3 strobe
15
I/O
I/O
I/O
I/O
I/O
I
0, 4, 8, 12
EM1D20
EM2D4
2
3
L17
110
111
EQEP3S
SCIRXDA
SPISOMIB
GPIO65
5
6
SCI-A receive data
15
I/O
I/O
I/O
I/O
I/O
O
SPI-B slave out, master in(2)
General-purpose input/output 65
External memory interface 1 data line 19
External memory interface 2 data line 3
Enhanced QEP3 index
0, 4, 8, 12
EM1D19
EM2D3
2
3
K16
EQEP3I
5
SCITXDA
SPICLKB
6
SCI-A transmit data
SPI-B clock(2)
15
I/O
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO66
EM1D18
EM2D2
0, 4, 8, 12
I/O
I/O
I/O
I/OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OD
I/O
I/O
I/O
I
General-purpose input/output 66(3)
External memory interface 1 data line 18
External memory interface 2 data line 2
I2C-B data open-drain bidirectional port
SPI-B slave transmit enable(2)
General-purpose input/output 67
External memory interface 1 data line 17
External memory interface 2 data line 1
General-purpose input/output 68
External memory interface 1 data line 16
External memory interface 2 data line 0
General-purpose input/output 69
External memory interface 1 data line 15
I2C-B clock open-drain bidirectional port
SPI-C slave in, master out(2)
2
3
K17
112
SDAB
6
SPISTEB
GPIO67
EM1D17
EM2D1
15
0, 4, 8, 12
2
B19
C18
132
133
3
GPIO68
EM1D16
EM2D0
0, 4, 8, 12
2
3
GPIO69
EM1D15
SCLB
0, 4, 8, 12
2
B18
A17
134
135
6
SPISIMOC
GPIO70
EM1D14
CANRXA
SCITXDB
SPISOMIC
GPIO71
EM1D13
CANTXA
SCIRXDB
SPICLKC
GPIO72
15
0, 4, 8, 12
General-purpose input/output 70(3)
External memory interface 1 data line 14
CAN-A receive
2
5
6
O
SCI-B transmit data
SPI-C slave out, master in(2)
15
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 71
External memory interface 1 data line 13
CAN-A transmit
2
5
B17
B16
136
139
6
I
SCI-B receive data
SPI-C clock(2)
General-purpose input/output 72.(3) This is the factory
default boot mode select pin 1.
15
I/O
0, 4, 8, 12
I/O
EM1D12
CANTXB
SCITXDC
SPISTEC
GPIO73
2
I/O
O
External memory interface 1 data line 12
CAN-B transmit
5
6
O
SCI-C transmit data
15
I/O
I/O
I/O
O/Z
SPI-C slave transmit enable(2)
General-purpose input/output 73
External memory interface 1 data line 11
0, 4, 8, 12
EM1D11
XCLKOUT
2
3
External clock output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
The clock signal is chosen using the
CLKSRCCTL3.XCLKOUTSEL bit field while the divide
ratio is chosen using the
A16
140
XCLKOUTDIVSEL.XCLKOUTDIV bit field.
CANRXB
SCIRXDC
GPIO74
EM1D10
GPIO75
EM1D9
5
I
CAN-B receive
6
I
SCI-C receive
0, 4, 8, 12
I/O
I/O
I/O
I/O
General-purpose input/output 74
External memory interface 1 data line 10
General-purpose input/output 75
External memory interface 1 data line 9
C17
D16
141
142
2
0, 4, 8, 12
2
24
Terminal Configuration and Functions
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ZHCSHE0 –DECEMBER 2017
Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO76
EM1D8
SCITXDD
GPIO77
EM1D7
SCIRXDD
GPIO78
EM1D6
EQEP2A
GPIO79
EM1D5
EQEP2B
GPIO80
EM1D4
EQEP2S
GPIO81
EM1D3
EQEP2I
GPIO82
EM1D2
GPIO83
EM1D1
0, 4, 8, 12
I/O
I/O
O
General-purpose input/output 76
External memory interface 1 data line 8
SCI-D transmit data
2
C16
A15
B15
C15
D15
A14
143
144
145
146
148
149
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 77
External memory interface 1 data line 7
SCI-D receive data
2
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 78
External memory interface 1 data line 6
Enhanced QEP2 input A
2
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 79
External memory interface 1 data line 5
Enhanced QEP2 input B
2
6
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose input/output 80
External memory interface 1 data line 4
Enhanced QEP2 strobe
2
6
0, 4, 8, 12
General-purpose input/output 81
External memory interface 1 data line 3
Enhanced QEP2 index
2
6
0, 4, 8, 12
General-purpose input/output 82
External memory interface 1 data line 2
General-purpose input/output 83
External memory interface 1 data line 1
B14
C14
150
151
2
0, 4, 8, 12
2
General-purpose input/output 84. This is the factory
default boot mode select pin 0.
GPIO84
0, 4, 8, 12
I/O
SCITXDA
MDXB
5
O
O
SCI-A transmit data
A11
B11
154
155
6
McBSP-B transmit serial data
McBSP-A transmit serial data
General-purpose input/output 85
External memory interface 1 data line 0
SCI-A receive data
MDXA
15
O
GPIO85
EM1D0
0, 4, 8, 12
I/O
I/O
I
2
SCIRXDA
MDRB
5
6
I
McBSP-B receive serial data
McBSP-A receive serial data
General-purpose input/output 86
External memory interface 1 address line 13
External memory interface 1 column address strobe
SCI-B transmit data
MDRA
15
I
GPIO86
EM1A13
EM1CAS
SCITXDB
MCLKXB
MCLKXA
GPIO87
EM1A14
EM1RAS
SCIRXDB
MFSXB
MFSXA
0, 4, 8, 12
I/O
O
2
3
O
C11
D11
156
157
5
O
6
I/O
I/O
I/O
O
McBSP-B transmit clock
15
McBSP-A transmit clock
0, 4, 8, 12
General-purpose input/output 87
External memory interface 1 address line 14
External memory interface 1 row address strobe
SCI-B receive data
2
3
O
5
I
6
I/O
I/O
McBSP-B transmit frame synch
McBSP-A transmit frame synch
15
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO88
EM1A15
EM1DQM0
GPIO89
EM1A16
EM1DQM1
SCITXDC
GPIO90
EM1A17
EM1DQM2
SCIRXDC
GPIO91
EM1A18
EM1DQM3
SDAA
0, 4, 8, 12
I/O
O
General-purpose input/output 88
2
C6
170
External memory interface 1 address line 15
External memory interface 1 Input/output mask for byte 0
General-purpose input/output 89
3
O
0, 4, 8, 12
I/O
O
2
External memory interface 1 address line 16
External memory interface 1 Input/output mask for byte 1
SCI-C transmit data
D6
171
3
O
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 90
2
External memory interface 1 address line 17
External memory interface 1 Input/output mask for byte 2
SCI-C receive data
A5
B5
172
173
3
O
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 91
2
External memory interface 1 address line 18
External memory interface 1 Input/output mask for byte 3
I2C-A data open-drain bidirectional port
General-purpose input/output 92
3
O
6
I/OD
I/O
O
GPIO92
EM1A19
EM1BA1
SCLA
0, 4, 8, 12
2
External memory interface 1 address line 19
External memory interface 1 bank address 1
I2C-A clock open-drain bidirectional port
General-purpose input/output 93
A4
B4
174
175
3
O
6
I/OD
I/O
O
GPIO93
EM1BA0
SCITXDD
GPIO94
SCIRXDD
GPIO95
GPIO96
EM2DQM1
EQEP1A
GPIO97
EM2DQM0
EQEP1B
GPIO98
EM2A0
0, 4, 8, 12
3
External memory interface 1 bank address 0
SCI-D transmit data
6
O
0, 4, 8, 12
I/O
I
General-purpose input/output 94
A3
B3
176
—
6
SCI-D receive data
0, 4, 8, 12
I/O
I/O
O
General-purpose input/output 95
0, 4, 8, 12
General-purpose input/output 96
3
C3
A2
F1
G1
—
—
—
17
External memory interface 2 Input/output mask for byte 1
Enhanced QEP1 input A
5
I
0, 4, 8, 12
I/O
O
General-purpose input/output 97
3
External memory interface 2 Input/output mask for byte 0
Enhanced QEP1 input B
5
I
0, 4, 8, 12
I/O
O
General-purpose input/output 98
3
External memory interface 2 address line 0
Enhanced QEP1 strobe
EQEP1S
GPIO99
EM2A1
5
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 99
3
External memory interface 2 address line 1
Enhanced QEP1 index
EQEP1I
GPIO100
EM2A2
5
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 100
External memory interface 2 address line 2
Enhanced QEP2 input A
3
H1
H2
—
—
EQEP2A
SPISIMOC
GPIO101
EM2A3
5
I
6
I/O
I/O
O
SPI-C slave in, master out
0, 4, 8, 12
General-purpose input/output 101
External memory interface 2 address line 3
Enhanced QEP2 input B
3
5
6
EQEP2B
SPISOMIC
I
I/O
SPI-C slave out, master in
26
Terminal Configuration and Functions
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO102
EM2A4
0, 4, 8, 12
I/O
O
General-purpose input/output 102
External memory interface 2 address line 4
Enhanced QEP2 strobe
3
H3
J1
—
—
EQEP2S
SPICLKC
GPIO103
EM2A5
5
I/O
I/O
I/O
O
6
SPI-C clock
0, 4, 8, 12
General-purpose input/output 103
External memory interface 2 address line 5
Enhanced QEP2 index
3
EQEP2I
SPISTEC
GPIO104
SDAA
5
I/O
I/O
I/O
I/OD
O
6
SPI-C slave transmit enable
0, 4, 8, 12
General-purpose input/output 104
I2C-A data open-drain bidirectional port
External memory interface 2 address line 6
Enhanced QEP3 input A
1
EM2A6
3
J2
J3
—
—
EQEP3A
SCITXDD
GPIO105
SCLA
5
I
6
O
SCI-D transmit data
0, 4, 8, 12
I/O
I/OD
O
General-purpose input/output 105
I2C-A clock open-drain bidirectional port
External memory interface 2 address line 7
Enhanced QEP3 input B
1
EM2A7
3
EQEP3B
SCIRXDD
GPIO106
EM2A8
5
I
6
I
SCI-D receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 106
External memory interface 2 address line 8
Enhanced QEP3 strobe
3
L2
L3
—
—
EQEP3S
SCITXDC
GPIO107
EM2A9
5
I/O
O
6
SCI-C transmit data
0, 4, 8, 12
I/O
O
General-purpose input/output 107
External memory interface 2 address line 9
Enhanced QEP3 index
3
EQEP3I
SCIRXDC
GPIO108
EM2A10
GPIO109
EM2A11
GPIO110
EM2WAIT
GPIO111
EM2BA0
GPIO112
EM2BA1
GPIO113
EM2CAS
GPIO114
EM2RAS
GPIO115
EM2CS0
GPIO116
EM2CS2
5
I/O
I
6
SCI-C receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 108
External memory interface 2 address line 10
General-purpose input/output 109
External memory interface 2 address line 11
General-purpose input/output 110
External memory interface 2 Asynchronous SRAM WAIT
General-purpose input/output 111
External memory interface 2 bank address 0
General-purpose input/output 112
External memory interface 2 bank address 1
General-purpose input/output 113
External memory interface 2 column address strobe
General-purpose input/output 114
External memory interface 2 row address strobe
General-purpose input/output 115
External memory interface 2 chip select 0
General-purpose input/output 116
External memory interface 2 chip select 2
L4
N2
—
—
—
—
—
—
—
—
—
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
I
M2
M4
M3
N4
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
N3
3
0, 4, 8, 12
I/O
O
V12
W10
3
0, 4, 8, 12
3
I/O
O
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO117
EM2SDCKE
GPIO118
EM2CLK
GPIO119
EM2RNW
GPIO120
EM2WE
0, 4, 8, 12
I/O
O
General-purpose input/output 117
U12
T12
T15
—
—
—
3
External memory interface 2 SDRAM clock enable
General-purpose input/output 118
External memory interface 2 clock
General-purpose input/output 119
External memory interface 2 read not write
General-purpose input/output 120
External memory interface 2 write enable
USB external regulator power fault indicator
General-purpose input/output 121
External memory interface 2 output enable
USB external regulator enable
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
U15
W16
T8
—
—
—
—
—
—
USB0PFLT
GPIO121
EM2OE
15
I/O
I/O
O
0, 4, 8, 12
3
USB0EPEN
GPIO122
SPISIMOC
SD1_D1
15
I/O
I/O
I/O
I
0, 4, 8, 12
General-purpose input/output 122
SPI-C slave in, master out
6
7
Sigma-Delta 1 channel 1 data input
General-purpose input/output 123
SPI-C slave out, master in
GPIO123
SPISOMIC
SD1_C1
0, 4, 8, 12
I/O
I/O
I
6
U8
7
Sigma-Delta 1 channel 1 clock input
General-purpose input/output 124
SPI-C clock
GPIO124
SPICLKC
SD1_D2
0, 4, 8, 12
I/O
I/O
I
6
V8
7
Sigma-Delta 1 channel 2 data input
General-purpose input/output 125
SPI-C slave transmit enable
GPIO125
SPISTEC
SD1_C2
0, 4, 8, 12
I/O
I/O
I
6
T9
7
Sigma-Delta 1 channel 2 clock input
General-purpose input/output 126
Sigma-Delta 1 channel 3 data input
General-purpose input/output 127
Sigma-Delta 1 channel 3 clock input
General-purpose input/output 128
Sigma-Delta 1 channel 4 data input
General-purpose input/output 129
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 130
Sigma-Delta 2 channel 1 data input
General-purpose input/output 131
Sigma-Delta 2 channel 1 clock input
General-purpose input/output 132
Sigma-Delta 2 channel 2 data input
GPIO126
SD1_D3
0, 4, 8, 12
I/O
I
U9
V9
—
—
—
—
—
—
—
7
GPIO127
SD1_C3
0, 4, 8, 12
I/O
I
7
GPIO128
SD1_D4
0, 4, 8, 12
I/O
I
W9
7
GPIO129
SD1_C4
0, 4, 8, 12
I/O
I
T10
U10
V10
W18
7
GPIO130
SD2_D1
0, 4, 8, 12
I/O
I
7
GPIO131
SD2_C1
0, 4, 8, 12
7
I/O
I
GPIO132
SD2_D2
0, 4, 8, 12
7
I/O
I
GPIO133/AUXCLKIN
0, 4, 8, 12
I/O
General-purpose input/output 133. The AUXCLKIN
function of this GPIO pin could be used to provide a
single-ended 3.3-V level clock signal to the Auxiliary
Phase-Locked Loop (AUXPLL), whose output is used for
the USB module. The AUXCLKIN clock may also be
used for the CAN module.
G18
118
SD2_C2
7
I
Sigma-Delta 2 channel 2 clock input
28
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ZHCSHE0 –DECEMBER 2017
Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO134
SD2_D3
0, 4, 8, 12
I/O
I
General-purpose input/output 134
Sigma-Delta 2 channel 3 data input
General-purpose input/output 135
SCI-A transmit data
V18
—
7
GPIO135
SCITXDA
SD2_C3
0, 4, 8, 12
I/O
O
6
U18
—
7
I
Sigma-Delta 2 channel 3 clock input
General-purpose input/output 136
SCI-A receive data
GPIO136
SCIRXDA
SD2_D4
0, 4, 8, 12
I/O
I
6
T17
T18
—
—
7
I
Sigma-Delta 2 channel 4 data input
General-purpose input/output 137
SCI-B transmit data
GPIO137
SCITXDB
SD2_C4
0, 4, 8, 12
I/O
O
6
7
I
Sigma-Delta 2 channel 4 clock input
General-purpose input/output 138
SCI-B receive data
GPIO138
SCIRXDB
GPIO139
SCIRXDC
GPIO140
SCITXDC
GPIO141
SCIRXDD
GPIO142
SCITXDD
GPIO143
GPIO144
GPIO145
EPWM1A
GPIO146
EPWM1B
GPIO147
EPWM2A
GPIO148
EPWM2B
GPIO149
EPWM3A
GPIO150
EPWM3B
GPIO151
EPWM4A
GPIO152
EPWM4B
GPIO153
EPWM5A
GPIO154
EPWM5B
GPIO155
EPWM6A
0, 4, 8, 12
I/O
I
T19
N19
M19
M18
L19
—
—
—
—
—
6
0, 4, 8, 12
I/O
I
General-purpose input/output 139
SCI-C receive data
6
0, 4, 8, 12
I/O
O
General-purpose input/output 140
SCI-C transmit data
6
0, 4, 8, 12
I/O
I
General-purpose input/output 141
SCI-D receive data
6
0, 4, 8, 12
I/O
O
General-purpose input/output 142
SCI-D transmit data
6
0, 4, 8, 12
F18
F17
—
—
I/O
I/O
I/O
O
General-purpose input/output 143
General-purpose input/output 144
General-purpose input/output 145
Enhanced PWM1 output A (HRPWM-capable)
General-purpose input/output 146
Enhanced PWM1 output B (HRPWM-capable)
General-purpose input/output 147
Enhanced PWM2 output A (HRPWM-capable)
General-purpose input/output 148
Enhanced PWM2 output B (HRPWM-capable)
General-purpose input/output 149
Enhanced PWM3 output A (HRPWM-capable)
General-purpose input/output 150
Enhanced PWM3 output B (HRPWM-capable)
General-purpose input/output 151
Enhanced PWM4 output A (HRPWM-capable)
General-purpose input/output 152
Enhanced PWM4 output B (HRPWM-capable)
General-purpose input/output 153
Enhanced PWM5 output A (HRPWM-capable)
General-purpose input/output 154
Enhanced PWM5 output B (HRPWM-capable)
General-purpose input/output 155
Enhanced PWM6 output A (HRPWM-capable)
0, 4, 8, 12
0, 4, 8, 12
E17
D18
D17
D14
A13
B13
C13
D13
A12
B12
C12
—
—
—
—
—
—
—
—
—
—
—
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
1
I/O
O
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
GPIO156
EPWM6B
GPIO157
EPWM7A
GPIO158
EPWM7B
GPIO159
EPWM8A
GPIO160
EPWM8B
GPIO161
EPWM9A
GPIO162
EPWM9B
GPIO163
EPWM10A
GPIO164
EPWM10B
GPIO165
EPWM11A
GPIO166
EPWM11B
GPIO167
EPWM12A
GPIO168
EPWM12B
0, 4, 8, 12
I/O
O
General-purpose input/output 156
D12
B10
C10
D10
B9
—
—
—
—
—
—
—
—
—
—
—
—
—
1
Enhanced PWM6 output B (HRPWM-capable)
General-purpose input/output 157
Enhanced PWM7 output A (HRPWM-capable)
General-purpose input/output 158
Enhanced PWM7 output B (HRPWM-capable)
General-purpose input/output 159
Enhanced PWM8 output A (HRPWM-capable)
General-purpose input/output 160
Enhanced PWM8 output B (HRPWM-capable)
General-purpose input/output 161
Enhanced PWM9 output A
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
C9
1
0, 4, 8, 12
I/O
O
General-purpose input/output 162
Enhanced PWM9 output B
D9
1
0, 4, 8, 12
I/O
O
General-purpose input/output 163
Enhanced PWM10 output A
A8
1
0, 4, 8, 12
I/O
O
General-purpose input/output 164
Enhanced PWM10 output B
B8
1
0, 4, 8, 12
I/O
O
General-purpose input/output 165
Enhanced PWM11 output A
C5
1
0, 4, 8, 12
I/O
O
General-purpose input/output 166
Enhanced PWM11 output B
D5
1
0, 4, 8, 12
I/O
O
General-purpose input/output 167
Enhanced PWM12 output A
C4
1
0, 4, 8, 12
1
I/O
O
General-purpose input/output 168
Enhanced PWM12 output B
D4
RESET
Device Reset (in) and Watchdog Reset (out). The
devices have a built-in power-on reset (POR) circuit.
During a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset or NMI watchdog reset
occurs. During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK cycles.
A resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be
100 nF or smaller. These values will allow the watchdog
to properly drive the XRS pin to VOL within 512 OSCCLK
cycles when the watchdog reset is asserted. The output
buffer of this pin is an open drain with an internal pullup.
If this pin is driven by an external device, an open-drain
device is recommended.
XRS
F19
124
I/OD
30
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
CLOCKS
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
X1
X2
NC
G19
J19
H4
123
121
I
On-chip crystal-oscillator output. A quartz crystal may be
connected across X1 and X2. If X2 is not used, it must
be left unconnected.
O
NO CONNECT
No connect. BGA ball is electrically open and not
connected to the die.
—
JTAG
TCK
TDI
V15
81
77
I
I
JTAG test clock with internal pullup (see Section 4.5)
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on
a rising edge of TCK.
W13
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK.(3)
TDO
TMS
W15
W14
78
80
O/Z
I
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained
low at all times during normal device operation. An
external pulldown resistor is required on this pin. The
value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ
or smaller resistor generally offers adequate protection.
The value of the resistor is application-specific. TI
recommends that each target board be validated for
proper operation of the debugger and the application.
This pin has an internal 50-ns (nominal) glitch filter.
TRST
V14
79
I
INTERNAL VOLTAGE REGULATOR CONTROL
Internal voltage regulator enable with internal pulldown.
The internal VREG is not supported and must be
disabled. Connect VREGENZ to VDDIO
VREGENZ
J18
119
I
.
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
ANALOG, DIGITAL, AND I/O POWER
E9
E11
F9
16
21
61
F11
G14
G15
J14
J15
K5
76
117
126
137
153
158
169
—
1.2-V digital logic power pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 uF. The exact
value of the decoupling capacitance should be
VDD
determined by your system voltage regulation solution.
K6
P10
P13
R10
R13
R11
R12
P6
—
—
—
72
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin.
VDD3VFL
—
36
3.3-V analog power pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
VDDA
R6
54
32
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
A9
A18
B1
3
11
15
E7
20
E10
E13
E16
F4
26
62
68
75
F7
82
F10
F13
F16
G4
88
91
99
106
114
116
127
138
147
152
159
168
—
3.3-V digital I/O power pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. The exact value of the
decoupling capacitance should be determined by your
system voltage regulation solution.
G5
VDDIO
G6
H5
H6
L14
L15
M1
M5
M6
N14
N15
P9
—
—
—
R9
—
V19
W8
H16
—
—
120
Power pins for the 3.3-V on-chip crystal oscillator (X1
and X2) and the two zero-pin internal oscillators
(INTOSC). Place a 0.1-μF (minimum) decoupling
capacitor on each pin.
VDDOSC
H17
125
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
A1
A10
A19
E5
E6
E8
E12
E14
E15
F5
F6
F8
F12
F14
F15
G16
G17
H8
H9
H10
H11
H12
H14
H15
J5
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
PWR
PAD
VSS
J6
J8
J9
J10
J11
J12
K8
K9
K10
K11
K12
K14
K15
L5
L6
L8
L9
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
L10
L11
L12
L18
M8
M9
M10
M11
M12
M14
M15
N1
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
N5
PWR
PAD
VSS
N6
P7
P8
P11
P12
P14
P15
R7
R8
R14
R15
W7
W19
H18
122
—
Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of the
external crystal oscillator circuit.
If an external crystal is not used, this pin may be
connected to the board ground.
VSSOSC
H19
P1
P5
R5
V7
W1
34
52
—
—
—
Analog ground.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. This pin must be connect to VSSA
VSSA
.
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Table 3-1. Signal Descriptions (continued)
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
MUX
POSITION
NAME
SPECIAL FUNCTIONS
ERRORSTS
U19
92
O
Error status output. This pin has an internal pulldown.
TEST PINS
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT1
FLT2
W12
V13
73
74
I/O
I/O
Flash test pin 2. Reserved for TI. Must be left
unconnected.
(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance
(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in
SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system
PCB characteristics. If this is a concern, the user should take precautions such as adding a 39 Ω (10% tolerance) series termination
resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be performed
with the provided IBIS models. The termination is not required if this pin is used for input function.
3.3 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 3-2 lists the pull direction and when it
is active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order
to avoid any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are
not bonded out in a particular package. Other pins noted in Table 3-2 with pullups and pulldowns are
always on and cannot be disabled.
Table 3-2. Pins With Internal Pullup and Pulldown
RESET
(XRS = 0)
PIN
DEVICE BOOT
APPLICATION SOFTWARE
Pullup enable is application-
defined
GPIOx
Pullup disabled
Pullup disabled(1)
TRST
Pulldown active
Pullup active
TCK
TMS
Pullup active
TDI
Pullup active
XRS
Pullup active
VREGENZ
ERRORSTS
Other pins
Pulldown active
Pulldown active
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
36
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3.4 Pin Multiplexing
3.4.1 GPIO Muxed Pins
Table 3-3 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions
can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The
GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from
alternate mux selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 3-3. GPIO Muxed Pins(1)(2)
GPIO Mux Selection
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO0
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
SDAA (I/OD)
SCLA (I/OD)
GPIO1
MFSRB (I/O)
MCLKRB (I/O)
GPIO2
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
SDAB (I/OD)
SCLB (I/OD)
GPIO3
OUTPUTXBAR2 (O)
MFSRA (I/O)
GPIO4
CANTXA (O)
CANRXA (I)
GPIO5
OUTPUTXBAR3 (O)
GPIO6
OUTPUTXBAR4 (O) EXTSYNCOUT (O)
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
CANTXB (O)
CANRXB (I)
GPIO7
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
OUTPUTXBAR5 (O)
ADCSOCAO (O)
OUTPUTXBAR6 (O)
ADCSOCBO (O)
OUTPUTXBAR7 (O)
MDXB (O)
GPIO8
SCITXDA (O)
SCIRXDA (I)
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
SCITXDB (O)
SCIRXDB (I)
UPP-WAIT (I/O)
UPP-START (I/O)
UPP-ENA (I/O)
UPP-D7 (I/O)
UPP-D6 (I/O)
UPP-D5 (I/O)
UPP-D4 (I/O)
UPP-D3 (I/O)
UPP-D2 (I/O)
UPP-D1 (I/O)
UPP-D0 (I/O)
UPP-CLK (I/O)
SCITXDC (O)
SCIRXDC (I)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
OUTPUTXBAR7 (O)
OUTPUTXBAR8 (O)
CANRXA (I)
EPWM9A (O)
EPWM9B (O)
EPWM10A (O)
EPWM10B (O)
EPWM11A (O)
EPWM11B (O)
EPWM12A (O)
EPWM12B (O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
SD2_C2 (I)
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
CANTXA (O)
CANTXB (O)
EQEP1B (I)
MDRA (I)
CANRXB (I)
EQEP1S (I/O)
EQEP1I (I/O)
MCLKXA (I/O)
MFSXA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
EM1CS4 (O)
EM1SDCKE (O)
EM1CLK (O)
EM1WE (O)
EM1CS0 (O)
EM1RNW (O)
EM1CS2 (O)
EM1CS3 (O)
EM1WAIT (I)
EM1OE (O)
EM1A0 (O)
SCITXDB (O)
SCIRXDB (I)
SPICLKB (I/O)
SPISTEB (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
EQEP3A (I)
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
SCIRXDA (I)
MDXB (O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
OUTPUTXBAR5 (O)
OUTPUTXBAR6 (O)
OUTPUTXBAR7 (O)
OUTPUTXBAR8 (O)
SCITXDA (O)
CANRXA (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
CANTXA (O)
SDAA (I/OD)
SCLA (I/OD)
OUTPUTXBAR1 (O)
SCIRXDA (I)
SDAB (I/OD)
SCLB (I/OD)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDA (O)
OUTPUTXBAR2 (O)
SCITXDC (O)
SCIRXDC (I)
EM1A1 (O)
(1) I = Input, O = Output, OD = Open Drain
(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
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Table 3-3. GPIO Muxed Pins(1)(2) (continued)
GPIO Mux Selection
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO40
EM1A2 (O)
EM1A3 (O)
SDAB (I/OD)
SCLB (I/OD)
SDAA (I/OD)
SCLA (I/OD)
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
SCITXDA (O)
SCIRXDA (I)
EM1A4 (O)
EM1A5 (O)
EM1A6 (O)
SCIRXDD (I)
SCITXDD (O)
SCITXDA (O)
SCIRXDA (I)
EM1A7 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP1A (I)
EM1A8 (O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
SD2_C2 (I)
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
EM1A9 (O)
EM1A10 (O)
EM1A11 (O)
EM1A12 (O)
EM1D31 (I/O)
EM1D30 (I/O)
EM1D29 (I/O)
EM1D28 (I/O)
EM1D27 (I/O)
EM1D26 (I/O)
EM1D25 (I/O)
EM1D24 (I/O)
EM1D23 (I/O)
EM1D22 (I/O)
EM1D21 (I/O)
EM1D20 (I/O)
EM1D19 (I/O)
EM1D18 (I/O)
EM1D17 (I/O)
EM1D16 (I/O)
EM1D15 (I/O)
EM1D14 (I/O)
EM1D13 (I/O)
EM1D12 (I/O)
EM1D11 (I/O)
EM1D10 (I/O)
EM1D9 (I/O)
EM1D8 (I/O)
EM1D7 (I/O)
EM1D6 (I/O)
EM1D5 (I/O)
EM1D4 (I/O)
EM1D3 (I/O)
EM1D2 (I/O)
EM1D1 (I/O)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SCITXDB (O)
SCIRXDB (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
EM2D15 (I/O)
EM2D14 (I/O)
EM2D13 (I/O)
EM2D12 (I/O)
EM2D11 (I/O)
EM2D10 (I/O)
EM2D9 (I/O)
EM2D8 (I/O)
EM2D7 (I/O)
EM2D6 (I/O)
EM2D5 (I/O)
EM2D4 (I/O)
EM2D3 (I/O)
EM2D2 (I/O)
EM2D1 (I/O)
EM2D0 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
SCITXDC (O)
SCIRXDC (I)
SPICLKB (I/O)
SPISTEB (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
CANRXA (I)
EQEP2I (I/O)
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP3A (I)
SPISIMOA(3) (I/O)
SPISOMIA(3) (I/O)
SPICLKA(3) (I/O)
SPISTEA(3) (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
EQEP3B (I)
CANTXA (O)
SCIRXDA (I)
SPISIMOB(3) (I/O)
SPISOMIB(3) (I/O)
SPICLKB(3) (I/O)
SPISTEB(3) (I/O)
EQEP3S (I/O)
EQEP3I (I/O)
SCITXDA (O)
SDAB (I/OD)
SCLB (I/OD)
SCITXDB (O)
SCIRXDB (I)
SCITXDC (O)
SCIRXDC (I)
SPISIMOC(3) (I/O)
SPISOMIC(3) (I/O)
SPICLKC(3) (I/O)
SPISTEC(3) (I/O)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
XCLKOUT (O)
SCITXDD (O)
SCIRXDD (I)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
MDRB (I)
MDXA (O)
MDRA (I)
EM1D0 (I/O)
EM1A13 (O)
EM1A14 (O)
EM1A15 (O)
EM1A16 (O)
EM1CAS (O)
EM1RAS (O)
EM1DQM0 (O)
EM1DQM1 (O)
MCLKXB (I/O)
MFSXB (I/O)
MCLKXA (I/O)
MFSXA (I/O)
SCITXDC (O)
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in
SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
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Table 3-3. GPIO Muxed Pins(1)(2) (continued)
GPIO Mux Selection
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO90
EM1A17 (O)
EM1A18 (O)
EM1A19 (O)
EM1DQM2 (O)
EM1DQM3 (O)
EM1BA1 (O)
EM1BA0 (O)
SCIRXDC (I)
SDAA (I/OD)
SCLA (I/OD)
SCITXDD (O)
SCIRXDD (I)
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
EM2DQM1 (O)
EM2DQM0 (O)
EM2A0 (O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
GPIO97
GPIO98
GPIO99
EM2A1 (O)
GPIO100
GPIO101
GPIO102
GPIO103
GPIO104
GPIO105
GPIO106
GPIO107
GPIO108
GPIO109
GPIO110
GPIO111
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO118
GPIO119
GPIO120
GPIO121
GPIO122
GPIO123
GPIO124
GPIO125
GPIO126
GPIO127
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
EM2A2 (O)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SCITXDD (O)
SCIRXDD (I)
EM2A3 (O)
EM2A4 (O)
EM2A5 (O)
SDAA (I/OD)
SCLA (I/OD)
EM2A6 (O)
EM2A7 (O)
EM2A8 (O)
SCITXDC (O)
SCIRXDC (I)
EM2A9 (O)
EM2A10 (O)
EM2A11 (O)
EM2WAIT (I)
EM2BA0 (O)
EM2BA1 (O)
EM2CAS (O)
EM2RAS (O)
EM2CS0 (O)
EM2CS2 (O)
EM2SDCKE (O)
EM2CLK (O)
EM2RNW (O)
EM2WE (O)
EM2OE (O)
USB0PFLT
USB0EPEN
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
GPIO133/
AUXCLKIN
SD2_C2 (I)
GPIO134
GPIO135
GPIO136
GPIO137
GPIO138
GPIO139
GPIO140
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
SCIRXDC (I)
SCITXDC (O)
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Table 3-3. GPIO Muxed Pins(1)(2) (continued)
GPIO Mux Selection
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO141
GPIO142
GPIO143
GPIO144
GPIO145
GPIO146
GPIO147
GPIO148
GPIO149
GPIO150
GPIO151
GPIO152
GPIO153
GPIO154
GPIO155
GPIO156
GPIO157
GPIO158
GPIO159
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
GPIO166
GPIO167
GPIO168
SCIRXDD (I)
SCITXDD (O)
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
EPWM9A (O)
EPWM9B (O)
EPWM10A (O)
EPWM10B (O)
EPWM11A (O)
EPWM11B (O)
EPWM12A (O)
EPWM12B (O)
40
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3.4.2 Input X-BAR
The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 3-6). Table 3-4 shows the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core
Delfino Microcontrollers Technical Reference Manual.
INPUT7
INPUT8
INPUT9
INPUT10
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
GPIO0
GPIOx
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
INPUT11
INPUT12
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
XINT5
XINT4
XINT3
XINT2
XINT1
CPU PIE
CLA
TRIP4
TRIP5
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
TRIP6
ADCEXTSOC
ADC
EXTSYNCIN1
EXTSYNCIN2
ePWM and eCAP
Sync Chain
Output X-BAR
Figure 3-6. Input X-BAR
Table 3-4. Input X-BAR Destinations
INPUT
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
DESTINATIONS
EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR
EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR
EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR
XINT1, EPWM X-BAR, Output X-BAR
XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR
XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR
ECAP1
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
XINT4
XINT5
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3.4.3 Output X-BAR and ePWM X-BAR
The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The
ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for
both the Output X-BAR and ePWM X-BAR are shown in Figure 3-7. For details on the Output X-BAR and
ePWM X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xD Dual-Core Delfino
Microcontrollers Technical Reference Manual.
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)
ePWM and eCAP
Sync Chain
EXTSYNCOUT
OUTPUT1
OUTPUT2
ADCSOCAO
OUTPUT3
ADCSOCAO
OUTPUT4
Select Ckt
GPIO
Mux
Output
X-BAR
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
ADCSOCBO
Select Ckt
ADCSOCBO
ECAPxOUT
eCAPx
ADCx
EVT1
EVT2
EVT3
EVT4
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
ePWM
X-BAR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
Input X-Bar
OTHER DESTINATIONS
(see Input X-BAR)
X-BAR Flags
(shared)
FLT1.COMPH
FLT1.COMPL
SDFMx
FLT4.COMPH
FLT4.COMPL
Figure 3-7. Output X-BAR and ePWM X-BAR
42
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3.4.4 USB Pin Muxing
Table 3-5 shows assignment of the alternate USB function mapping. These can be configured with the
GPBAMSEL register.
Table 3-5. Alternate USB Function
GPIO
GPBAMSEL SETTING
GPBAMSEL[10] = 1b
GPBAMSEL[11] = 1b
USB FUNCTION
USB0DM
GPIO42
GPIO43
USB0DP
3.4.5 High-Speed SPI Pin Muxing
The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special
GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by
the SPI when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 3-6.
Table 3-6. GPIO Configuration for High-Speed SPI
GPIO
SPI SIGNAL
MUX CONFIGURATION
SPIA
SPIB
SPIC
GPIO58
GPIO59
GPIO60
GPIO61
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
GPBGMUX2[21:20]=11b
GPBMUX2[21:20]=11b
GPBMUX2[23:22]=11b
GPBMUX2[25:24]=11b
GPBMUX2[27:26]=11b
GPBGMUX2[23:22]=11b
GPBGMUX2[25:24]=11b
GPBGMUX2[27:26]=11b
GPIO63
GPIO64
GPIO65
GPIO66
SPISIMOB
SPISOMIB
SPICLKB
SPISTEB
GPBGMUX2[31:30]=11b
GPCGMUX1[1:0]=11b
GPCGMUX1[3:2]=11b
GPCGMUX1[5:4]=11b
GPBMUX2[31:30]=11b
GPCMUX1[1:0]=11b
GPCMUX1[3:2]=11b
GPCMUX1[5:4]=11b
GPIO69
GPIO70
GPIO71
GPIO72
SPISIMOC
SPISOMIC
SPICLKC
SPISTEC
GPCGMUX1[11:10]=11b
GPCGMUX1[13:12]=11b
GPCGMUX1[15:14]=11b
GPCGMUX1[17:16]=11b
GPCMUX1[11:10]=11b
GPCMUX1[13:12]=11b
GPCMUX1[15:14]=11b
GPCMUX1[17:16]=11b
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3.5 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 3-7 lists acceptable conditioning
for any unused pins. When multiple options are listed in Table 3-7, any are acceptable. Pins not listed in
Table 3-7 must be connected according to Table 3-1.
Table 3-7. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
Analog
VREFHIx
VREFLOx
Tie to VDDA
Tie to VSSA
•
•
No Connect
Tie to VSSA
ADCINx
Digital
•
•
•
Input mode with internal pullup enabled
GPIOx
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
X1
X2
Tie to VSS
No Connect
•
•
No Connect
TCK
TDI
Pullup resistor
•
•
No Connect
Pullup resistor
TDO
No Connect
TMS
No Connect
TRST
Pulldown resistor (2.2 kΩ or smaller)
Tie to VDDIO. VREG is not supported.
No Connect
VREGENZ
ERRORSTS
FLT1
No Connect
FLT2
No Connect
Power and Ground
VDD
All VDD pins must be connected per Table 3-1.
If a separate analog supply is not used, tie to VDDIO
All VDDIO pins must be connected per Table 3-1.
Must be tied to VDDIO
VDDA
.
VDDIO
VDD3VFL
VDDOSC
VSS
Must be tied to VDDIO
All VSS pins must be connected to board ground.
VSSA
If a separate analog ground is not used, tie to VSS
.
VSSOSC
If an external crystal is not used, this pin may be connected to the board ground.
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4 Specifications
4.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–20
MAX
4.6
4.6
4.6
1.5
4.6
4.6
4.6
20
UNIT
VDDIO with respect to VSS
VDD3VFL with respect to VSS
Supply voltage
V
VDDOSC with respect to VSS
VDD with respect to VSS
Analog voltage
Input voltage
Output voltage
VDDA with respect to VSSA
V
V
V
VIN (3.3 V)
VO
Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO
)
Analog input (per pin), IIKANALOG
–20
–20
20
20
Input clamp current
(VIN < VSSA or VIN > VDDA
)
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
)
Output current
Digital output (per pin), IOUT
–20
–55
–65
20
150
150
mA
°C
Operating junction temperature
Storage temperature(3)
TJ
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see Semiconductor and IC Package Thermal Metrics.
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4.2 ESD Ratings
VALUE
UNIT
TMS320F28377D in 337-ball ZWT package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
TMS320F28377D in 176-pin PTP package
V(ESD) Electrostatic discharge (ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
46
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4.3 Recommended Operating Conditions
MIN
3.14
1.14
NOM
3.3
1.2
0
MAX
3.47
1.26
UNIT
V
(1)
Device supply voltage, I/O, VDDIO
Device supply voltage, VDD
Supply ground, VSS
V
V
Analog supply voltage, VDDA
Analog ground, VSSA
3.14
–55
3.3
0
3.47
125
V
V
(2)
Junction temperature, TJ
°C
(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
1000000
100000
10000
1000
90
100
110
120
130
140
150
Temperature (èC)
D001
(1) Silicon operating life design goal is 100000 power-on hours (POH) at 105°C junction temperature (does not include package
interconnect life).
(2) The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant
failure mechanism affecting device wearout for the specific device process and design characteristics.
Figure 4-1. TMS320F28377D-EP Operating Life Derating Chart
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4.4 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Table 4-1 shows the device current consumption at 200-MHz SYSCLK.
Table 4-1. Device Current Consumption at 200-MHz SYSCLK
(1)
IDD
TYP(2)
IDDIO
TYP(2)
IDDA
TYP(2)
IDD3VFL
TYP(2)
MODE
TEST CONDITIONS
MAX(3)
MAX(3)
MAX(3)
MAX(3)
•
•
•
Code is running out of RAM.(4)
All I/O pins are left unconnected.
Operational
(RAM)
Peripherals not active have their
clocks disabled.
325 mA
440 mA
30 mA
13 mA
20 mA
33 mA
40 mA
•
•
FLASH is read and in active state.
XCLKOUT is enabled at SYSCLK/4.
•
Both CPU1 and CPU2 are in IDLE
mode.
IDLE
105 mA
30 mA
210 mA
135 mA
3 mA
3 mA
10 mA
10 mA
10 µA
5 µA
150 µA
150 µA
10 µA
10 µA
150 µA
150 µA
•
•
Flash is powered down.
XCLKOUT is turned off.
•
Both CPU1 and CPU2 are in
STANDBY mode.
STANDBY
•
•
Flash is powered down.
XCLKOUT is turned off.
•
•
•
CPU1 watchdog is running.
Flash is powered down.
XCLKOUT is turned off.
HALT(5)
1.5 mA
300 µA
110 mA
4 mA
750 µA
750 µA
2 mA
2 mA
5 µA
5 µA
150 µA
75 µA
10 µA
1 µA
150 µA
50 µA
•
•
CPU1.M0 and CPU1.M1 RAMs are in
low-power data retention mode.
HIBERNATE(6)
CPU2.M0 and CPU2.M1 RAMs are in
low-power data retention mode.
•
•
•
•
•
CPU1 is running from RAM.
CPU2 is running from Flash.
All I/O pins are left unconnected.
Peripheral clocks are disabled.
Flash
Erase/Program
242 mA
360 mA
3 mA
10 mA
10 µA
150 µA
53 mA
65 mA
CPU1 is performing Flash Erase and
Programming.
•
•
CPU2 is accessing Flash locations to
keep bank active.
XCLKOUT is turned off.
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) TYP: Vnom, 30°C
(3) MAX: Vmax, 125°C
(4) The following is executed in a loop on CPU1:
•
All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
SDFM1 to SDFM4 active
ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
CPU TIMERs active
•
•
•
•
•
•
•
•
DMA does 32-bit burst transfers
CLA1 does multiply-accumulate tasks
All ADCs perform continuous conversion
All DACs ramp voltage up/down at 150 kHz
CMPSS1 to CMPSS8 active
The following is executed in a loop on CPU2:
•
•
•
•
•
CPU TIMERs active
CLA1 does multiply-accumulate tasks
VCU does complex multiply/accumulate with parallel load
TMU calculates a cosine
FPU does multiply/accumulate with parallel load
(5) CPU2 must go into IDLE mode before CPU1 enters HALT mode.
(6) CPU2 must go into reset/IDLE/STANDBY mode before CPU1 enters HIBERNATE mode.
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4.4.1 Current Consumption Graphs
Figure 4-2 and Figure 4-3 are a typical representation of the relationship between frequency and current
consumption/power on the device. The operational test from Table 4-1 was run across frequency at Vmax
and high temperature. Actual results will vary based on the system implementation and conditions.
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
VDD
VDDIO
VDDA
VDD3VFL
Figure 4-2. Operational Current Versus Frequency
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
Power
Figure 4-3. Power Versus Frequency
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Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD
current between TYP and MAX conditions can be seen in Figure 4-4. The current consumption in HALT
mode is primarily leakage current as there is no active switching if the internal oscillator has been powered
down.
Figure 4-4 shows the typical leakage current across temperature. The device was placed into HALT mode
under nominal voltage conditions.
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120 130
Temperature (èC)
D002
Figure 4-4. IDD Leakage Current Versus Temperature
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4.4.2 Reducing Current Consumption
The F28377D provides some methods to reduce the device current consumption:
•
Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered
during idle periods in the application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 4-2
indicates the typical current reduction that may be achieved by disabling the clocks using the
PCLKCRx register.
Table 4-2. Current on VDD Supply by Various
Peripherals (at 200 MHz)(1)
PERIPHERAL
MODULE(2)
IDD CURRENT
REDUCTION (mA)
ADC(3)
3.3
3.3
1.4
1.4
0.3
0.6
2.9
0.6
2.9
2.6
4.5
1.7
1.7
1.3
1.6
0.9
2
CAN
CLA
CMPSS(3)
CPUTIMER
DAC(3)
DMA
eCAP
EMIF1
EMIF2
ePWM1 to ePWM4(4)
ePWM5 to ePWM12(4)
HRPWM(4)
I2C
McBSP
SCI
SDFM
SPI
uPP
0.5
7.3
23.8
USB and AUXPLL at 60 MHz
(1) At Vmax and 125°C.
(2) All peripherals are disabled upon reset. Use the PCLKCRx register
to individually enable peripherals. For peripherals with multiple
instances, the current quoted is for a single module.
(3) This number represents the current drawn by the digital portion of
the ADC, CMPSS, and DAC modules.
(4) The ePWM is at /2 of SYSCLK.
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4.5 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
VOH
High-level output voltage
Low-level output voltage
V
0.4
V
VOL
IOH
IOL
0.2
High-level output source current for all output
pins
–4
mA
Low-level output sink current for all output pins
GPIO0–GPIO7,
4
mA
GPIO42–GPIO43,
GPIO46–GPIO47
VDDIO * 0.7
VDDIO + 0.3
High-level input voltage
(3.3 V)
VIH
V
All other pins
2.0
VDDIO + 0.3
0.8
VIL
Low-level input voltage (3.3 V)
VSS – 0.3
V
Digital inputs with
VDDIO = 3.3 V
VIN = VDDIO
Ipulldown
Input current
Input current
120
150
µA
pulldown(1)
Digital inputs with
pullup enabled(1)
VDDIO = 3.3 V
VIN = 0 V
Ipullup
µA
Pullups disabled
0 V ≤ VIN ≤ VDDIO
Digital
2
Analog (except
ADCINB0 or
DACOUTx)
2
ILEAK
Pin leakage
µA
pF
0 V ≤ VIN ≤ VDDA
ADCINB0
DACOUTx
2
66
2
11(2)
CI
Input capacitance
(1) See Table 3-2 for a list of pins with a pullup or pulldown.
(2) The MAX input leakage shown on ADCINB0 is at high temperature.
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4.6 Thermal Resistance Characteristics
4.6.1 GWT Package
°C/W(1)
8.8
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
11.6
23.2
19.0
17.8
16.5
0.2
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.3
150
250
500
0
PsiJT
Junction-to-package top
0.4
0.5
11.4
11.3
11.2
11.0
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
4.6.2 PTP Package
°C/W(1)
10.2
7.9
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
N/A
N/A
0
RΘJB
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
RΘJA (High k PCB)
19.4
12.8
11.4
10.1
0.11
0.24
0.33
0.42
6.1
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
150
250
500
0
PsiJT
Junction-to-package top
5.5
150
250
500
PsiJB
Junction-to-board
5.4
5.3
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
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4.7 System
4.7.1 Power Sequencing
An external power supply must be used to supply 3.3 V to VDDIO, VDD3VFL, VDDOSC, and VDDA and to
provide 1.2 V to VDD. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high
to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 4-3 shows the supply ramp rate.
Table 4-3. Supply Ramp Rate
MIN
MAX
UNIT
Supply ramp rate
VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS
330
105
V/s
The voltage on VDDIO should be greater than VDD or no less than 0.3 V below VDD at all times. VDDIO
,
VDD3VFL, VDDOSC, and VDDA should be powered up together and be kept within 0.3 V of each other during
operation. Before powering the device, no voltage larger than 0.3 V above VDDIO should be applied to any
digital pin, and no voltage larger than 0.3 V above VDDA should be applied to any analog pin. The VREFHI
voltage should not exceed VDDA at any time.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance
state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on
the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.
4.7.2 Reset Timing
XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in
power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI
watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should
be placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These
values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the
watchdog reset is asserted. Figure 4-5 shows the recommended reset circuit.
VDDIO
2.2 kW – 10 kW
XRS
£100 nF
Figure 4-5. Reset Circuit
54
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4.7.2.1 Reset Sources
The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and
HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xD Dual-Core
Delfino Microcontrollers Technical Reference Manual.
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources
will drive XRS low. Use this to disable any other devices driving the boot pins.
The SCCRESET and debugger reset sources do not drive XRS; therefore, the
pins used for boot mode should not be actively driven by other devices in the
system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2837xD Dual-Core Delfino
Microcontrollers Technical Reference Manual.
4.7.2.2 Reset Electrical Data and Timing
Table 4-4 shows the reset (XRS) timing requirements. Table 4-5 shows the reset (XRS) switching
characteristics. Figure 4-6 shows the power-on reset. Figure 4-7 shows the warm reset.
Table 4-4. Reset (XRS) Timing Requirements
MIN
1.5
MAX
UNIT
ms
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRS low on warm reset
3.2
µs
Table 4-5. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
Pulse duration, XRS driven low by device after supplies are
tw(RSL1)
tw(WDRS)
µs
stable
Pulse duration, reset pulse generated by watchdog
512tc(OSCCLK)
cycles
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VDDIO, VDDA
(3.3 V)
VDD (1.2 V)
t
w(RSL1)
XRS(A)
Boot ROM
CPU
Execution
Phase
User-code
(B)
h(boot-mode)
t
User-code dependent
Boot-Mode
Pins
GPIO pins as input
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input (pullups are disabled)
I/O Pins
User-code dependent
A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Table 3-1. On-chip POR logic
will hold this pin low until the supplies are in a valid range.
B. After reset from any source (see Section 4.7.2.1), the boot ROM code samples Boot Mode pins. Based on the status
of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code
executes after power-on conditions (in debugger environment), the boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 4-6. Power-on Reset
t
w(RSL2)
XRS
User Code
CPU
Execution
Phase
User Code
Boot ROM
Boot-ROM execution starts
(initiated by any reset source)
(A)
t
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see Section 4.7.2.1), the Boot ROM code samples BOOT Mode pins. Based on the
status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code
executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLK speed. The SYSCLK will be based on user environment and could be with or without PLL enabled.
Figure 4-7. Warm Reset
56
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4.7.3 Clock Specifications
4.7.3.1 Clock Sources
表 4-6 lists four possible clock sources. 图 4-8 provides an overview of the device's clocking system.
表 4-6. Possible Reference Clock Sources
CLOCK SOURCE
MODULES CLOCKED
COMMENTS
INTOSC1
Can be used to provide clock for:
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Watchdog block
Main PLL
CPU-Timer 2
INTOSC2(1)
Can be used to provide clock for:
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
XTAL
Can be used to provide clock for:
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
AUXCLKIN
Can be used to provide clock for:
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
should be used to provide the input clock.
•
•
Auxiliary PLL
CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).
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INTOSC1
WDCLK
To watchdog timers
CLKSRCCTL1
SYSPLLCTL1
SYSCLKDIVSEL
INTOSC2
X1 (XTAL)
SYSCLK
Divider
To GS RAMs, GPIOs,
NMIWDs, and IPC
OSCCLK
PLLSYSCLK
CPU1.CPUCLK
CPU2.CPUCLK
System PLL
PLLRAWCLK
CPU1.SYSCLK
CPU2.SYSCLK
CPU1
CPU2
To local memories
To local memories
CPU1.SYSCLK
CPU2.SYSCLK
To ePIEs, LS RAMs,
CLA message RAMs,
and DCSMs
One per SYSCLK peripheral
CPUSELx
CPU1.PCLKCRx
To peripherals
PERx.SYSCLK
CPU2.PCLKCRx
One per LSPCLK peripheral
LOSPCP
CPUSELx
CPU1.PCLKCRx
CPU2.PCLKCRx
LSP
Divider
To SCIs, SPIs, and
McBSPs
PERx.LSPCLK
One per ePWM
EPWMCLKDIV
CPU1.PCLKCRx
CPUSELx
/1
/2
PLLSYSCLK
To ePWMs
EPWMCLK
CPU2.PCLKCRx
HRPWM
CPU1.PCLKCRx
To HRPWM Registers
HRPWMCLK
One per CAN module
CPUSELx
CLKSRCCTL2
CAN Bit Clock
To CANs
AUXCLKIN
CLKSRCCTL2
AUXPLLCTL1
AUXCLKDIVSEL
AUXCLK
Divider
AUXOSCCLK
AUXPLLCLK
To USB bit clock
Auxiliary PLL
AUXPLLRAWCLK
图 4-8. Clocking System
58
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4.7.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times,
frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.
4.7.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
表 4-7 shows the frequency requirements for the input clocks. 表 4-16 shows the crystal equivalent series
resistance requirements. 表 4-8 shows the X1 input level characteristics when using an external clock
source. 表 4-9 and 表 4-10 show the timing requirements for the input clocks. 表 4-11 shows the PLL lock
times for the Main PLL and the USB PLL.
表 4-7. Input Clock Frequency
MIN
10
2
MAX UNIT
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator (PLL enabled)
Frequency, X1, from external oscillator (PLL disabled)
Frequency, AUXCLKIN, from external oscillator
20
25
MHz
MHz
MHz
MHz
2
100
60
f(AUXI)
2
表 4-8. X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
MAX
0.3 * VDDIO
VDDIO + 0.3
UNIT
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
V
V
0.7 * VDDIO
表 4-9. X1 Timing Requirements
MIN
MAX UNIT
tf(X1)
Fall time, X1
Rise time, X1
6
6
ns
ns
tr(X1)
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
表 4-10. AUXCLKIN Timing Requirements
MIN
MAX UNIT
tf(AUXI)
Fall time, AUXCLKIN
6
6
ns
ns
tr(AUXI)
tw(AUXL)
tw(AUXH)
Rise time, AUXCLKIN
Pulse duration, AUXCLKIN low as a percentage of tc(XCI)
Pulse duration, AUXCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
表 4-11. PLL Lock Times
MIN
NOM
MAX UNIT
(1)
t(PLL)
t(USB)
Lock time, Main PLL (X1, from external oscillator)
50 µs + 2500 * tc(OSCCLK)
50 µs + 2500 * tc(OSCCLK)
µs
µs
(1)
Lock time, USB PLL (AUXCLKIN, from external oscillator)
(1) The PLL lock time here includes the two required PLL lock sequences. Cycle count includes code execution of the PLL initialization
routine, which could vary depending on compiler optimizations and flash wait states.
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4.7.3.2.2 Internal Clock Frequencies
表 4-12 provides the clock frequencies for the internal clocks.
表 4-12. Internal Clock Frequencies
MIN
NOM
MAX
200(1)
UNIT
MHz
ns
f(SYSCLK)
Frequency, device (system) clock
Period, device (system) clock
2
5(1)
tc(SYSCLK)
500
Frequency, system PLL output (before SYSCLK
divider)
f(PLLRAWCLK)
120
120
400
400
MHz
MHz
Frequency, auxiliary PLL output (before AUXCLK
divider)
f(AUXPLLRAWCLK)
f(AUXPLL)
f(PLL)
Frequency, AUXPLLCLK
Frequency, PLLSYSCLK
Frequency, LSPCLK(2)
Period, LSPCLK
2
2
60
60
200(1)
200(1)
500
MHz
MHz
MHz
ns
f(LSP)
2
5(1)
tc(LSPCLK)
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1)
f(OSCCLK)
See respective clock
MHz
f(EPWM)
Frequency, EPWMCLK(3)
100
100
MHz
MHz
f(HRPWM)
Frequency, HRPWMCLK
60
(1) Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and the
minimum period is 5.15 ns.
(2) Lower LSPCLK will reduce device power consumption. The default at reset is SYSCLK/4.
(3) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
4.7.3.2.3 Output Clock Frequency and Switching Characteristics
表 4-13 provides the frequency of the output clock. 表 4-14 shows the switching characteristics of the
output clock, XCLKOUT.
表 4-13. Output Clock Frequency
MIN
MAX UNIT
50 MHz
f(XCO)
Frequency, XCLKOUT
表 4-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
5
UNIT
tf(XCO)
Fall time, XCLKOUT
ns
ns
ns
ns
tr(XCO)
Rise time, XCLKOUT
5
tw(XCOL)
tw(XCOH)
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
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4.7.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, multiple external clock source options are available. 图 4-9
shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also
referred to as XTAL) and AUXCLKIN.
X1
X2
X1
X2
v
v
ssosc
ssosc
RESONATOR
CRYSTAL
R
C
C
L1
D
L2
X1
X2
GPIO133/AUXCLKIN
v
ssosc
NC
3.3V
VDD
CLK
3.3V
VDD
CLK
OUT
GND
OUT
GND
3.3V OSCILLATOR
3.3V OSCILLATOR
图 4-9. Connecting Input Clocks to a 2837xD Device
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4.7.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should
be as small as possible because the size of the resistance affects start-up time (smaller RD = faster start-
up time). TI recommends that the crystal manufacturer characterize the crystal with the application board.
表 4-15 shows the crystal oscillator parameters. 表 4-16 shows the crystal equivalent series resistance
(ESR) requirements. 表 4-17 shows the crystal oscillator electrical characteristics.
表 4-15. Crystal Oscillator Parameters
MIN
MAX UNIT
CL1, CL2
C0
Load capacitance
12
24
7
pF
pF
Crystal shunt capacitance
表 4-16. Crystal Equivalent Series Resistance (ESR) Requirements(1)(2)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
CRYSTAL FREQUENCY (MHz)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
表 4-17. Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ms
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
Start-up time(1)
2
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
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4.7.3.5 Internal Oscillators
To reduce production board costs and application development time, the F28377D contains two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are
enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and
INTOSC1 is set as the backup clock source. INTOSC1 can also be manually configured as the system
reference clock (OSCCLK). 表 4-18 provides the electrical characteristics of the internal oscillators to
determine if this module meets the clocking requirements of the application.
表 4-18 provides the electrical characteristics of the two internal oscillators.
注
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to
frequencies above 194 MHz.
表 4-18. Internal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.0
MAX
UNIT
f(INTOSC)
Frequency, INTOSC1 and INTOSC2
Frequency stability at room temperature
Frequency stability over VDD
Frequency stability
9.7
10.3
MHz
30ºC, Nominal VDD
30ºC
±0.1%
±0.2%
f(INTOSC-STABILITY)
–3.0%
3.0%
20
f(INTOSC-ST)
Start-up and settling time
µs
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4.7.4 Flash Parameters
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash
through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal
to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of
approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2×
improvement in performance when migrating from the previous generation Delfino MCUs.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module
(DCSM), which cannot be erased after it is programmed.
表 4-19 shows the minimum required flash wait states at different frequencies. 表 4-20 shows the flash
parameters.
表 4-19. Flash Wait States
CPUCLK (MHz)
(1)
MINIMUM WAIT STATES
EXTERNAL OSCILLATOR OR CRYSTAL
150 < CPUCLK ≤ 200
INTOSC1 OR INTOSC2
145 < CPUCLK ≤ 194
97 < CPUCLK ≤ 145
48 < CPUCLK ≤ 97
CPUCLK ≤ 48
3
2
1
0
100 < CPUCLK ≤ 150
50 < CPUCLK ≤ 100
CPUCLK ≤ 50
(1) Minimum required FRDCNTL[RWAIT].
表 4-20. Flash Parameters
PARAMETER
MIN
TYP
MAX
300
UNIT
µs
128 data bits + 16 ECC bits
40
90
Program Time(1)
8KW sector
32KW sector
8KW sector
32KW sector
8KW sector
32KW sector
180
ms
360
25
720
ms
50
Erase Time(2) at < 25 cycles
Erase Time(2) at 50k cycles
ms
ms
30
55
105
110
4000
4000
20000
Nwec
Write/erase cycles
cycles
years
tretention
Data retention duration at TJ = 85°C
20
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include the
time to transfer the following into RAM:
•
•
•
Code that uses flash API to program the flash
Flash API itself
Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the emulator used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
注
The Main Array flash programming must be aligned to 64-bit address boundaries and each
64-bit word may only be programmed once per write/erase cycle. For more details, see the
"Flash: Minimum Programming Word Size" advisory in the TMS320F2837xD Dual-Core
Delfino™ MCUs Silicon Errata.
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4.7.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always
be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0
and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should always
be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See 图 4-10 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. 图 4-11 shows
how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not
used and should be grounded.
The PD (Power Detect) terminal of the emulator header should be connected to the board 3.3-V supply.
Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should also
be connected to board ground. The JTAG clock should be looped from the header TCK output terminal
back to the RTCK input terminal of the header (to sense clock continuity by the emulator). Header terminal
RESET is an open-drain output from the emulator header that enables board components to be reset
through emulator commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the
JTAG header is smaller than 6 in (15.24 cm), and no other devices are present on the JTAG chain.
Otherwise, each signal should be buffered. Additionally, for most emulator operations at 10 MHz, no
series resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35
MHz or so), 22-Ω resistors should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and
Watchpoints for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
TRST
TMS
TDI
GND
2
1
3
TMS
TDI
TRST
TDIS
KEY
4
GND
100 W
MCU
5
6
3.3 V
PD
7
8
TDO
TCK
TDO
RTCK
TCK
GND
GND
GND
EMU1
9
10
12
14
11
13
4.7 kW
4.7 kW
3.3 V
EMU0
3.3 V
图 4-10. Connecting to the 14-Pin JTAG Header
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Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
TRST
TMS
TDI
GND
GND
2
1
3
TMS
TDI
TRST
TDIS
4
100 W
MCU
5
6
3.3V
PD
KEY
7
8
TDO
TCK
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
4.7 kW
4.7 kW
3.3 V
EMU0
RESET
EMU2
EMU4
3.3 V
open
drain
A low pulse from the emulator
can be tied with other reset
sources to reset the board.
GND
GND
图 4-11. Connecting to the 20-Pin JTAG Header
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4.7.5.1 JTAG Electrical Data and Timing
表 4-21 lists the JTAG timing requirements. 表 4-22 lists the JTAG switching characteristics. 图 4-12
shows the JTAG timing.
表 4-21. JTAG Timing Requirements
NO.
1
MIN
66.66
26.66
26.66
13
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
ns
3
4
13
ns
7
ns
7
ns
表 4-22. JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
25
ns
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
图 4-12. JTAG Timing
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4.7.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO
pins are configured as inputs. For specific inputs, the user can also select the number of input qualification
cycles to filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed
to a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an
Input X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADC(s),
eCAP(s), ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the
TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
4.7.6.1 GPIO - Output Timing
Table 4-23 shows the general-purpose output switching characteristics. Figure 4-13 shows the general-
purpose output timing.
Table 4-23. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Rise time, GPIO switching low to high
MIN
MAX
8(1)
8(1)
25
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
ns
MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPO)
tf(GPO)
Figure 4-13. General-Purpose Output Timing
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4.7.6.2 GPIO - Input Timing
Table 4-24 shows the general-purpose input timing requirements. Figure 4-14 shows the sampling mode.
Table 4-24. General-Purpose Input Timing Requirements
MIN
1tc(SYSCLK)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n",
the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be
sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide
pulse ensures reliable recognition.
Figure 4-14. Sampling Mode
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4.7.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 ´ QUALPRD), if QUALPRD ¹ 0
(1)
Sampling frequency = SYSCLK, if QUALPRD = 0
(2)
Sampling period = SYSCLK cycle ´ 2 ´ QUALPRD, if QUALPRD ¹ 0
(3)
In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 4-15 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 4-15. General-Purpose Input Timing
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4.7.7 Interrupts
图 4-16 provides a high-level view of the interrupt architecture.
As shown in 图 4-16, the devices support five external interrupts (XINT1 to XINT5) that can be mapped
onto any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU
interrupt groups, with 16 interrupts per group.
CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT
LPM Logic
CPU1.WAKEINT
NMI
CPU1.NMIWD
CPU1.WD
CPU1.WDINT
CPU1
INPUTXBAR4
CPU1.XINT1 Control
CPU1.XINT2 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT5 Control
GPIO0
GPIO1
...
...
GPIOx
INT1
to
INT12
CPU1.
ePIE
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
Input
X-BAR
CPU1.TINT1
CPU1.TINT2
CPU1.TIMER1
CPU1.TIMER2
INT13
INT14
IPC
4 Interrupts
Peripherals
NMI
CPU1.NMIWD
CPU2
CPU2.XINT1 Control
CPU2.XINT2 Control
CPU2.XINT3 Control
CPU2.XINT4 Control
CPU2.XINT5 Control
INT1
to
INT12
CPU2
ePIE
CPU2.TINT1
CPU2.TINT2
INT13
INT14
CPU2.TIMER1
CPU2.TIMER2
CPU2.LPMINT
LPM Logic
CPU2.WD
CPU2.WAKEINT
CPU2.TINT0
CPU2.WDINT
CPU2.TIMER0
图 4-16. External and ePIE Interrupt Sources
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4.7.7.1 External Interrupt (XINT) Electrical Data and Timing
Table 4-25 lists the external interrupt timing requirements. Table 4-26 lists the external interrupt switching
characteristics. Figure 4-17 shows the external interrupt timing.
Table 4-25. External Interrupt Timing Requirements(1)
MIN
2tc(SYSCLK)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
Table 4-26. External Interrupt Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(2)
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK)
cycles
(1) For an explanation of the input qualifier parameters, see Table 4-24.
(2) This assumes that the ISR is in a single-cycle memory.
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 4-17. External Interrupt Timing
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4.7.8 Low-Power Modes
This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the
Low Power Modes section of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical
Reference Manual.
4.7.8.1 Clock-Gating Low-Power Modes
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. 表 4-27
describes the effect on the system when any of the clock-gating low-power modes are entered.
表 4-27. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
CPU1 IDLE
CPU1 STANDBY
CPU2 IDLE
CPU2 STANDBY
HALT
CPU1.CLKIN
Active
Active
Gated
N/A
Gated
Gated
Gated
N/A
N/A
N/A
N/A
N/A
Gated
Gated
Gated
Gated
Gated
Gated
Gated
CPU1.SYSCLK
CPU1.CPUCLK
CPU2.CLKIN
N/A
N/A
Active
Active
Gated
Active
Gated
Gated
Gated
CPU2.SYSCLK
CPU2.CPUCLK
N/A
N/A
N/A
N/A
Clock to modules
Connected to
PERx.SYSCLK
Active
Gated if
CPUSEL.PERx =
CPU1
Gated if
CPUSEL.PERx =
CPU2
CPU1.WDCLK
Active
Active
N/A
N/A
Gated if
CLKSRCCTL1.WDHALTI = 0
CPU2.WDCLK
AUXPLLCLK
PLL
N/A
N/A
Active
Active
Active
Active
Gated
Gated
Active
Active
Powered
Powered
Powered
Powered
Software must power down PLL
before entering HALT
INTOSC1
INTOSC2
Flash
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered down if
CLKSRCCTL1.WDHALTI = 0
Powered down if
CLKSRCCTL1.WDHALTI = 0
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Software-Controlled
Powered-Down
X1/X2 Crystal
Oscillator
4.7.8.2 Power-Gating Low-Power Modes
HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the
supply voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote
wakeup capability, and can be used to save power during long periods of inactivity. 表 4-28 describes the
effects on the system when the HIBERNATE mode is entered.
表 4-28. Effect of Power-Gating Low-Power Mode on the Device
MODULES/POWER DOMAINS
HIBERNATE
M0 and M1 memories
●
●
Remain on with memory retention if LPMCR.M0M1MODE = 0x00
Are off when LPMCR.M0M1MODE = 0x01
CPU1, CPU2 digital peripherals
Dx, LSx, GSx memories
I/Os
Powered down
Power down, memory contents are lost
On with output state preserved
Enters Low-Power Mode
Oscillators, PLL, analog
peripherals, Flash
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4.7.8.3 Low-Power Mode Wakeup Timing
表 4-29 shows the IDLE mode timing requirements, 表 4-30 shows the switching characteristics, and 图 4-
18 shows the timing diagram for IDLE mode.
表 4-29. IDLE Mode Timing Requirements(1)
MIN
2tc(SYSCLK)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
表 4-30. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(2)
Delay time, external wake signal to program execution resume
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
40tc(SYSCLK)
•
Wakeup from Flash
Flash module in active state
–
40tc(SYSCLK) + tw(WAKE)
(3)
td(WAKE-IDLE)
6700tc(SYSCLK)
cycles
•
Wakeup from Flash
Flash module in sleep state
–
6700tc(SYSCLK)(3) + tw(WAKE)
25tc(SYSCLK)
•
Wakeup from RAM
25tc(SYSCLK) + tw(WAKE)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD
Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3,
and FPAC1[PSLEEP] is 0x860.
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK
cycles (minimum) is needed before the wake-up signal could be asserted.
图 4-18. IDLE Entry and Exit Timing Diagram
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表 4-31 shows the STANDBY mode timing requirements, 表 4-32 shows the switching characteristics, and
图 4-19 shows the timing diagram for STANDBY mode.
表 4-31. STANDBY Mode Timing Requirements
MIN
MAX
UNIT
QUALSTDBY = 0 | 2tc(OSCCLK)
QUALSTDBY > 0 |
(2 + QUALSTDBY)tc(OSCCLK)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
表 4-32. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction executed to
XCLKOUT stop
td(IDLE-XCOS)
16tc(INTOSC1)
cycles
Delay time, external wake signal to
program execution resume(1)
•
Wakeup from flash
Flash module in active state
175tc(SYSCLK) + tw(WAKE-INT)
–
td(WAKE-STBY)
cycles
•
Wakeup from flash
Flash module in sleep state
6700tc(SYSCLK)(2) + tw(WAKE-INT)
–
3tc(OSC) + 15tc(SYSCLK)
+
•
Wakeup from RAM
tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD
Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3,
and FPAC1[PSLEEP] is 0x860.
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(C)
(F)
(A)
(B)
(D)(E)
(G)
Normal Execution
Device
Status
STANDBY
STANDBY
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before
being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before
the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
图 4-19. STANDBY Entry and Exit Timing Diagram
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表 4-33 shows the HALT mode timing requirements, 表 4-34 shows the switching characteristics, and 图
4-20 shows the timing diagram for HALT mode.
表 4-33. HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal(1)
Pulse duration, XRS wake-up signal(1)
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See 表 4-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK, see
节 4.7.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is powered
externally to the device.
表 4-34. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(IDLE-XCOS)
Delay time, IDLE instruction executed to XCLKOUT stop
16tc(INTOSC1)
cycles
Delay time, external wake signal end to CPU1 program
execution resume
•
•
•
Wakeup from flash
Flash module in active state
75tc(OSCCLK)
–
td(WAKE-HALT)
cycles
Wakeup from flash
Flash module in sleep state
(1)
17500tc(OSCCLK)
–
75tc(OSCCLK)
Wakeup from RAM
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xD
Dual-Core Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3,
and FPAC1[PSLEEP] is 0x860.
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(C)
(F)
(A)
(B)
(D)(E)
HALT
(G)
Device
Status
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being
turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very
little power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in
HALT MODE. This is done by writing a 1 to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay
of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wakeup sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables
the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin
asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The
HALT mode is now exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
图 4-20. HALT Entry and Exit Timing Diagram
注
CPU2 should enter IDLE mode before CPU1 puts the device into HALT mode. CPU1 should
verify that CPU2 has entered IDLE mode using the LPMSTAT register before calling the
IDLE instruction to enter HALT.
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表 4-35 shows the HIBERNATE mode timing requirements, 表 4-36 shows the switching characteristics,
and 图 4-21 shows the timing diagram for HIBERNATE mode.
表 4-35. HIBERNATE Mode Timing Requirements
MIN
40
MAX
UNIT
µs
tw(HIBWAKE)
tw(WAKEXRS)
Pulse duration, HIBWAKE signal
Pulse duration, XRS wake-up signal
40
µs
表 4-36. HIBERNATE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
cycles
ms
td(IDLE-XCOS)
td(WAKE-HIB)
Delay time, IDLE instruction executed to XCLKOUT stop
Delay time, external wake signal to lORestore function start
30tc(SYSCLK)
1.5
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(C)
(D)
(A)
(B)
(F)
(G)(H)
(I)(J)
(E)
CPU1 IDLE
Instruction
CPU1 HIB
config
Device Status Device Active
IoRestore() or Application Specific Operation
CPU1 Boot ROM
HIBERNATE
Td(WAKE-HIB)
GPIOHIBWAKEn,
XRSn
tw(HIBWAKEn),
tw(XRSn)
I/O Isolation
Bypassed &
Powered-Down
Application SpecificOperation
PLLs
Enabled
INTOSC1,INTOSC2,
X1/X2
Powering up
On
Powered Down
On
XCLKCOUT
Inactive
Application Specific Operation
td(IDLE-XCOS)
A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if
using I/O Isolation. Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank,
USB-PHY, CMPSS, DAC, and ADC using their register configurations. The application should also power down the
PLL and peripheral clocks before entering HIBERNATE. In dual-core applications, CPU1 should confirm that CPU2
has entered IDLE/STANDBY using the LPMSTAT register.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained.
CPU1 and CPU2 are powered down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals,
and Flash are in their software-controlled Low-Power modes. Dx, LSx, and GSx memories are also powered down,
and their memory contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2,
and X1/X2 OSC. The wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of
these clock sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of
the remainder of the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the
CPU1.REC.HIBRESETn bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined
IoRestore function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O
isolation, reconfigure the PLL, restore peripheral configurations, or branch to application code. This is up to the
application requirements.
I.
If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will
disable I/O isolation automatically if it was not taken care of inside of IoRestore. CPU2 will be brought out of reset at
this point as well.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral
Booting chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more
information.
图 4-21. HIBERNATE Entry and Exit Timing Diagram
注
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue
its execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM
Code and Peripheral Booting chapter of the TMS320F2837xD Dual-Core Delfino
Microcontrollers Technical Reference Manual for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function.
Regardless if the user has disabled Isolation in the IoRestore function or if IoRestore is
not defined, the BootROM will automatically disable isolation before booting as
determined by the HIBBOOTMODE register.
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注
For applications using both CPU1 and CPU2, TI recommends that the application puts CPU2
in either IDLE or STANDBY before entering HIBERNATE mode. If any GPIOs are used and
the state is to be preserved, data can be stored in M0/M1 memory of CPU1 to be
reconfigured upon wakeup. This should be done before step A of 图 4-21.
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4.7.9 External Memory Interface (EMIF)
The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).
4.7.9.1 Asynchronous Memory Support
The EMIF supports asynchronous memories:
•
•
SRAMs
NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access.
The EMIF module supports up to three chip selects (EMIF_CS[4:2]). Each chip select has the following
individually programmable attributes:
•
•
•
•
•
•
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turnaround time
Extended wait option with programmable time-out
Select strobe option
4.7.9.2 Synchronous DRAM Support
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit
data bus. The EMIF has a single SDRAM chip select (EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of
the program address bus and can only be accessed through the data bus, which places a restriction on
the C compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the
user is advised to copy data (using the DMA) from external memory to RAM before working on it. See the
examples in controlSUITE™ (CONTROLSUITE) and the TMS320F2837xD Dual-Core Delfino
Microcontrollers Technical Reference Manual.
SDRAM configurations supported are:
•
•
•
•
•
One-bank, two-bank, and four-bank SDRAM devices
Devices with 8-, 9-, 10-, and 11-column addresses
CAS latency of two or three clock cycles
16-bit/32-bit data bus width
3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh
mode allows the SDRAM to be put in a low-power state while still retaining memory contents because the
SDRAM will continue to refresh itself even without clocks from the microcontroller. Power-down mode
achieves even lower power, except the microcontroller must periodically wake up and issue refreshes if
data retention is required. The EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every
access to an external SDRAM device will have CAS latency.
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4.7.9.3 EMIF Electrical Data and Timing
4.7.9.3.1 Asynchronous RAM
Table 4-37 shows the EMIF asynchronous memory timing requirements. Table 4-38 shows the EMIF
asynchronous memory switching characteristics. Figure 4-22 through Figure 4-25 show the EMIF
asynchronous memory timing diagrams.
Table 4-37. EMIF Asynchronous Memory Timing Requirements(1)
NO.
MIN
MAX
UNIT
Reads and Writes
E
EMIF clock period
tc(SYSCLK)
2E
ns
ns
Pulse duration, EMxWAIT assertion and
deassertion
2
tw(EM_WAIT)
Reads
12
13
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
Setup time, EMxD[y:0] valid before EMxOE high
Hold time, EMxD[y:0] valid after EMxOE high
15
0
ns
ns
Setup Time, EMxWAIT asserted before end of
Strobe Phase(2)
14
tsu(EMOEL-EMWAIT)
4E+20
ns
Writes
Setup Time, EMxWAIT asserted before end of
Strobe Phase(2)
28
tsu(EMWEL-EMWAIT)
4E+20
ns
(1) E = EMxCLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 4-23 and Figure 4-25 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 4-38. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO.
PARAMETER
MIN
MAX UNIT
Reads and Writes
1
td(TURNAROUND)
Turn around time
(TA)*E–3
(TA)*E+2
ns
Reads
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH+2)*E–3
(RS+RST+RH+2)*E+2
ns
ns
3
4
tc(EMRCYCLE)
(RS+RST+RH+2+
(EWC*16))*E–3
(RS+RST+RH+2+
(EWC*16))*E+2
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 0)
(RS)*E–3
–3
(RS)*E+2
2
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 1)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 0)
(RH)*E–3
–3
(RH)*E
0
5
th(EMOEH-EMCEH)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 1)
Output setup time, EMxBA[y:0]
valid to EMxOE low
6
7
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
(RS)*E–3
(RH)*E–3
(RS)*E+2
(RH)*E
Output hold time, EMxOE high to
EMxBA[y:0] invalid
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual
for more information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.
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MAX UNIT
Table 4-38. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO.
PARAMETER
MIN
Output setup time, EMxA[y:0] valid
to EMxOE low
8
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E–3
(RS)*E+2
ns
ns
Output hold time, EMxOE high to
EMxA[y:0] invalid
9
(RH)*E–3
(RH)*E
EMxOE active low width (EW = 0)
EMxOE active low width (EW = 1)
(RST)*E–1
(RST)*E+1
ns
ns
10
tw(EMOEL)
(RST+(EWC*16))*E–1
(RST+(EWC*16))*E+1
Delay time from EMxWAIT
deasserted to EMxOE high
11
29
30
td(EMWAITH-EMOEH)
tsu(EMDQMV-EMOEL)
th(EMOEH-EMDQMIV)
4E+10
(RS)*E–3
(RH)*E–3
5E+15
(RS)*E+2
(RH)*E
ns
ns
ns
Output setup time, EMxDQM[y:0]
valid to EMxOE low
Output hold time, EMxOE high to
EMxDQM[y:0] invalid
Writes
EMIF write cycle time (EW = 0)
(WS+WST+WH+2)*E–3
(WS+WST+WH+2)*E+1
ns
ns
15
16
tc(EMWCYCLE)
(WS+WST+WH+2+
(EWC*16))*E–3
(WS+WST+WH+2+
(EWC*16))*E+1
EMIF write cycle time (EW = 1)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 0)
(WS)*E–3
–3
(WS)*E+1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 1)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0)
(WH)*E–3
–3
(WH)*E
17
th(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1)
0
Output setup time, EMxDQM[y:0]
valid to EMxWE low
18
19
20
21
22
23
tsu(EMDQMV-EMWEL)
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WST)*E–1
(WST+(EWC*16))*E–1
4E+10
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0]
valid to EMxWE low
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
to EMxWE low
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxA[y:0] invalid
EMxWE active low width
(EW = 0)
(WST)*E+1
(WST+(EWC*16))*E+1
5E+15
24
tw(EMWEL)
EMxWE active low width
(EW = 1)
Delay time from EMxWAIT
deasserted to EMxWE high
25
26
27
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Output setup time, EMxD[y:0] valid
to EMxWE low
(WS)*E–3
(WH)*E–3
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxD[y:0] invalid
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3
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
4
8
5
9
6
7
29
30
10
EMxOE
13
12
EMxD[y:0]
EMxWE
Figure 4-22. Asynchronous Memory Read Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
14
11
EMxOE
2
2
EMxWAIT
Asserted
Deasserted
Figure 4-23. EMxWAIT Read Timing Requirements
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15
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
16
18
20
22
17
19
21
23
24
EMxWE
EMxD[y:0]
EMxOE
27
26
Figure 4-24. Asynchronous Memory Write Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
28
25
EMxWE
2
2
EMxWAIT
Asserted
Deasserted
Figure 4-25. EMxWAIT Write Timing Requirements
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4.7.9.3.2 Synchronous RAM
Table 4-39 shows the EMIF synchronous memory timing requirements. Table 4-40 shows the EMIF
synchronous memory switching characteristics. Figure 4-26 and Figure 4-27 show the synchronous
memory timing diagrams.
Table 4-39. EMIF Synchronous Memory Timing Requirements
NO.
19
MIN
2
MAX UNIT
tsu(EMIFDV-EM_CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMxD[y:0] before EMxCLK rising
Input hold time, read data valid on EMxD[y:0] after EMxCLK rising
ns
ns
20
1.5
Table 4-40. EMIF Synchronous Memory Switching Characteristics
NO.
1
PARAMETER
MIN
10
3
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMxCLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMxCLK high or low
Delay time, EMxCLK rising to EMxCS[y:2] valid
Output hold time, EMxCLK rising to EMxCS[y:2] invalid
Delay time, EMxCLK rising to EMxDQM[y:0] valid
Output hold time, EMxCLK rising to EMxDQM[y:0] invalid
Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid
Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid
Delay time, EMxCLK rising to EMxD[y:0] valid
Output hold time, EMxCLK rising to EMxD[y:0] invalid
Delay time, EMxCLK rising to EMxRAS valid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
8
8
8
8
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
1
1
1
1
1
1
1
1
5
6
7
8
toh(CLKH-AIV)
td(CLKH-DV)
9
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
td(CLKH-DHZ)
toh(CLKH-DLZ)
Output hold time, EMxCLK rising to EMxRAS invalid
Delay time, EMxCLK rising to EMxCAS valid
Output hold time, EMxCLK rising to EMxCAS invalid
Delay time, EMxCLK rising to EMxWE valid
Output hold time, EMxCLK rising to EMxWE invalid
Delay time, EMxCLK rising to EMxD[y:0] tri-stated
Output hold time, EMxCLK rising to EMxD[y:0] driving
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BASIC SDRAM
1
READ OPERATION
2
2
EMxCLK
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
4
3
5
7
7
6
8
8
19
20
2 EM_CLK Delay
18
17
EMxD[y:0]
EMxRAS
11
12
13
14
EMxCAS
EMxWE
Figure 4-26. Basic SDRAM Read Operation
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMxCLK
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
3
5
7
7
9
4
6
8
8
10
EMxD[y:0]
EMxRAS
EMxCAS
EMxWE
11
12
13
15
16
Figure 4-27. Basic SDRAM Write Operation
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4.8 Analog Peripherals
This analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
•
Flexible voltage references
–
VREFHIA and VREFLOA, VREFHIB and VREFLOB, VREFHIC and VREFLOC, and VREFHID and VREFLOD externally
supplied reference voltage pins
•
Selectable by ADCs and buffered DACs
–
VDAC externally supplied reference voltage pin
•
•
Selectable by buffered DACs and comparator subsystem DACs
Low reference is VSSA
•
•
Flexible pin usage
Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
Internal connection to VREFLO on all ADCs for offset self-calibration
–
图 4-28 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. 图 4-29 shows the
Analog Subsystem Block Diagram for the 176-pin PTP package. 图 4-30 shows the Analog Subsystem
Block Diagram for the 100-pin PZP package.
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VREFHIA
VREFHIA
VDAC
Comparator Subsystem 1
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
Digital
Filter
DACREFSEL
VDDA or VDAC
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA
VDAC
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DACREFSEL
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
VSSA
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADCINB5
ADC-B
16-bits
or
12-bits
(selectable)
CTRIP3L
Digital
Filter
12-bit
Buffered
DAC
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
VSSA
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
CMPIN5N/ADCINC5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
CMPIN5N
CMPIN6P
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADCIND5
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
图 4-28. Analog Subsystem Block Diagram (337-Ball ZWT)
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VREFHIA
VREFHIA VDAC
DACREFSEL
Comparator Subsystem 1
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
Digital
Filter
VDDA or VDAC
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
VSSA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA VDAC
DACREFSEL
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADC-B
16-bits
or
12-bits
(selectable)
12-bit
Buffered
DAC
CTRIP3L
Digital
Filter
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CMPIN6P
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
图 4-29. Analog Subsystem Block Diagram (176-Pin PTP)
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VREFHIA
VREFHIA VDAC
DACREFSEL
Comparator Subsystem 1
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
Digital
Filter
VDDA or VDAC
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA VDAC
DACREFSEL
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DAC12
DAC12
12-bit
Buffered
DAC
REFLO
REFHI
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
VSSA
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
0
1
2
3
4
5
6
7
8
VREFHIB VDAC
DACREFSEL
CTRIP3H
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADCINB5
ADC-B
16-bits
or
12-bits
(selectable)
12-bit
Buffered
DAC
CTRIP3L
Digital
Filter
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
VSSA
10
11
12
13
14
15
Comparator Subsystem 4
Digital
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP4L
VREFLOB
CMPIN4N
CTRIPOUT4L
图 4-30. Analog Subsystem Block Diagram (100-Pin PZP)
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4.8.1 Analog-to-Digital Converter (ADC)
The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of
either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC
wrapper is start-of-conversion (SOC) based [see the SOC Principle of Operation section of the
TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
Each ADC has the following features:
•
•
•
•
•
•
•
•
Selectable resolution of 16 bits or 12 bits
Ratiometric external reference set by VREFHI and VREFLO
Differential signal conversions (16-bit mode only)
Single-ended signal conversions (12-bit mode only)
Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
–
–
–
–
–
Software immediate start
All ePWMs
GPIO XINT2
CPU timers
ADCINT1 or 2
•
•
•
Four flexible PIE interrupts
Burst mode
Four post-processing blocks, each with:
–
–
–
–
Saturating offset calibration
Error from setpoint calculation
High, low, and zero-crossing compare, with interrupt and ePWM trip capability
Trigger-to-sample delay capture
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图 4-31 shows the ADC module block diagram.
Analog to Digital Core
Analog to Digital Wrapper Logic
SIGNALMODE
SIGNALMODE
RESOLUTION
ADCSOC
RESOLUTION
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC
Arbitration
& Control
ACQPS
CHSEL
0
1
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
2
3
4
5
ADCCOUNTER
6
TRIGGER[15:0]
VIN+
7
DOUT
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
S/H Circuit
Converter
RESULT
-
+
ADCPPBxOFFCAL
S
saturate
+
ADCPPBxOFFREF
ADCPPBxRESULT
-
S
ADCEVT
VREFHI
Event
Logic
CONFIG
ADCEVTINT
VREFLO
Reference Voltage Levels
Post Processing Block (1-4)
Interrupt Block (1-4)
ADCINT1-4
图 4-31. ADC Module Block Diagram
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4.8.1.1 ADC Electrical Data and Timing
Table 4-41 shows the ADC operating conditions for 16-bit differential mode. Table 4-42 shows the ADC
characteristics for 16-bit differential mode. Table 4-43 shows the ADC operating conditions for 12-bit
single-ended mode. Table 4-44 shows the ADC characteristics for 12-bit single-ended mode. Table 4-45
shows the ADCEXTSOC timing requirements.
Table 4-41. ADC Operating Conditions (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
ns
ADCCLK (derived from PERx.SYSCLK)
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)
5
320
50
VREFHI
2.4
2.5 or 3.0
0
VDDA
VSSA
V
VREFLO
VSSA
V
VREFHI – VREFLO
2.4
VDDA
V
ADC input conversion range
ADC input signal common mode voltage(2)(3)
VREFLO
VREFCM – 50
VREFHI
V
VREFCM
VREFCM + 50
mV
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) VREFCM = (VREFHI + VREFLO)/2
(3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO
.
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC or DAC inputs using the same VREF
.
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Table 4-42. ADC Characteristics (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC conversion cycles(2)
29.6
31 ADCCLKs
Power-up time (after setting
ADCPWDNZ to first conversion)
500
µs
Gain error
Offset error(3)
–64
–16
±9
±9
64
16
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
dB
Channel-to-channel gain error
Channel-to-channel offset error
ADC-to-ADC gain error
ADC-to-ADC offset error
DNL(4)
±6
±3
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±6
±3
> –1
–3
±0.5
±1.5
87.6
–93.5
95.4
86.6
1
3
INL
SNR(5)(6)
THD(5)(6)
SFDR(5)(6)
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
dB
dB
SINAD(5)(6)
dB
VREFHI = 2.5 V, fin = 10 kHz,
single ADC(7)
14.1
14.1
VREFHI = 2.5 V, fin = 10 kHz,
synchronous ADCs(8)
ENOB(5)(6)
bits
VREFHI = 2.5 V, fin = 10 kHz,
asynchronous ADCs(9)
Not
supported
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
PSRR
PSRR
77
74
dB
dB
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
CMRR
DC to 1 MHz
60
dB
µA
VREFHI input current
190
VREFHI = 2.5 V, synchronous ADCs(8)
VREFHI = 2.5 V, asynchronous ADCs(9)
–2
2
ADC-to-ADC isolation(6)(10)(11)
LSBs
Not
supported
(1) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(2) See 节 4.8.1.1.2.
(3) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM
(4) No missing codes.
.
(5) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(6) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(7) One ADC operating while all other ADCs are idle.
(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(10) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(11) Value based on characterization.
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Table 4-43. ADC Operating Conditions (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)
MIN
5
TYP
MAX
UNIT
MHz
ns
V
ADCCLK (derived from PERx.SYSCLK)
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)
50
75
VREFHI
2.4
2.5 or 3.0
0
VDDA
VSSA
VREFLO
VSSA
2.4
V
VREFHI – VREFLO
ADC input conversion range
VDDA
V
VREFLO
VREFHI
V
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC or DAC inputs using the same VREF
.
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Table 4-44. ADC Characteristics (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
ADC conversion cycles(2)
Power-up time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.1
11 ADCCLKs
500
µs
Gain error
–5
–4
±3
±2
5
4
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
dB
Offset error
Channel-to-channel gain error
Channel-to-channel offset error
ADC-to-ADC gain error
ADC-to-ADC offset error
DNL(3)
±4
±2
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±4
±2
> –1
–2
±0.5
±1.0
68.8
–78.4
79.2
68.4
1
2
INL
SNR(4)(5)
THD(4)(5)
SFDR(4)(5)
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
dB
dB
SINAD(4)(5)
dB
VREFHI = 2.5 V, fin = 100 kHz,
single ADC(6), all packages
11.1
11.1
VREFHI = 2.5 V, fin = 100 kHz,
synchronous ADCs(7), all packages
VREFHI = 2.5 V, fin = 100 kHz,
Not
supported
asynchronous ADCs(8)
100-pin PZP package
,
ENOB(4)(5)
bits
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8)
176-pin PTP package
,
9.7
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8)
337-ball ZWT package
,
10.9
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
PSRR
PSRR
60
57
dB
dB
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
VREFHI = 2.5 V, synchronous ADCs(7)
all packages
,
–1
1
VREFHI = 2.5 V, asynchronous ADCs(8)
100-pin PZP package
VREFHI = 2.5 V, asynchronous ADCs(8)
176-pin PTP package
VREFHI = 2.5 V, asynchronous ADCs(8)
337-ball ZWT package
,
,
,
Not
supported
ADC-to-ADC isolation(5)(9)(10)
LSBs
µA
–9
–2
9
2
VREFHI input current
130
(1) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(2) See 节 4.8.1.1.2.
(3) No missing codes.
(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(5) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(6) One ADC operating while all other ADCs are idle.
(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(9) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(10) Value based on characterization.
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Table 4-45. ADCEXTSOC Timing Requirements(1)
MIN
MAX
UNIT
cycles
cycles
Synchronous
2tc(SYSCLK)
tw(INT)
Pulse duration, INT input low/high
With qualifier
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
4.8.1.1.1 ADC Input Models
注
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA
.
For single-ended operation, the ADC input characteristics are given by 表 4-46 and 图 4-32.
表 4-46. Single-Ended Input Model Parameters
DESCRIPTION
Parasitic input capacitance
VALUE (12-BIT MODE)
Cp
Ron
Ch
Rs
See 表 4-48
425 Ω
Sampling switch resistance
Sampling capacitor
14.5 pF
50 Ω
Nominal source impedance
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
图 4-32. Single-Ended Input Model
For differential operation, the ADC input characteristics are given by 表 4-47 and 图 4-33.
表 4-47. Differential Input Model Parameters
DESCRIPTION
Parasitic input capacitance
VALUE (16-BIT MODE)
See 表 4-48
700 Ω
Cp
Ron
Ch
Rs
Sampling switch resistance
Sampling capacitor
16.5 pF
Nominal source impedance
50 Ω
ADC
ADCINxP
Rs
Cp
Cp
Ron
Switch
Switch
AC
Ch
VSSA
Ron
ADCINxN
Rs
图 4-33. Differential Input Model
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表 4-48 shows the parasitic capacitance on each channel. Also, enabling a comparator adds
approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative
comparator inputs.
表 4-48. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0
ADCINA1
ADCINA2
ADCINA3
ADCINA4
ADCINA5
ADCINB0(1)
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINC2
ADCINC3
ADCINC4
ADCINC5
ADCIND0
ADCIND1
ADCIND2
ADCIND3
ADCIND4
ADCIND5
ADCIN14
ADCIN15
12.9
10.3
5.9
6.3
5.9
6.3
117.0
10.6
5.9
6.2
5.2
5.1
5.5
5.8
5.0
5.3
5.3
5.7
5.3
5.6
4.3
4.3
8.6
9.0
N/A
N/A
7.3
8.8
7.3
8.8
N/A
N/A
7.3
8.7
N/A
N/A
6.9
8.3
6.4
7.8
6.7
8.2
6.7
8.1
N/A
N/A
10.0
11.5
(1) The increased capacitance is due to VDAC functionality.
These input models should be used along with actual signal source impedance to determine the
acquisition window duration. See the Choosing an Acquisition Window Duration section of the
TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will
require assuming that Ch could start the S+H window completely charged to VREFHI or completely
discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered
channel, or vice-versa, the actual initial voltage on Ch will be close to being completely discharged to
VREFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on Ch will be close to the
voltage of the previously converted channel.
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4.8.1.1.2 ADC Timing Diagrams
表 4-49 shows the ADC timings in 12-bit mode (SYSCLK cycles). 表 4-50 shows the ADC timings in 16-bit
mode. 图 4-34 and 图 4-35 show the ADC conversion timings for two SOCs given the following
assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE
module).
The following parameters are identified in the timing diagrams:
•
The parameter tSH is the duration of the S+H window. At the end of this window, the value on the S+H
capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS +
1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be
the same for different SOCs.
•
•
•
The parameter tLAT is the time from the end of the S+H window until the ADC conversion results latch
in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous
conversion results will be returned.
The parameter tEOC is the time from the end of the S+H window until the next ADC conversion S+H
window can begin. In 16-bit mode, this will coincide with the latching of the conversion results, while in
12-bit mode, the subsequent sample can start before the conversion results are latched.
The parameter tINT is the time from the end of the S+H window until an ADCINT flag is set (if
configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, this will coincide with the
conversion results being latched into the result register. If the bit is cleared, this will coincide with the
end of the S+H window.
102
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表 4-49. ADC Timings in 12-Bit Mode (SYSCLK Cycles)
ADCCLK
CYCLES
ADCCLK PRESCALE
SYSCLK CYCLES
tLAT tINT(EARLY)
13
ADCCTL2
RATIO
tEOC
tINT(LATE)
tEOC
[PRESCALE]
ADCCLK:SYSCLK
0
1
1
1.5
2
11
1
11
11.0
Invalid
2
21
26
31
36
41
46
51
56
61
66
71
76
81
86
23
28
34
39
44
49
55
60
65
70
76
81
86
91
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
26
31
36
41
46
51
56
61
66
71
76
81
86
10.5
10.4
10.3
10.3
10.3
10.2
10.2
10.2
10.2
10.2
10.1
10.1
10.1
10.1
3
2.5
3
4
5
3.5
4
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADC S+H
Sample n+1
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
Sample n
(old data)
(old data)
Sample n+1
ADCRESULT1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
图 4-34. ADC Timings for 12-Bit Mode
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表 4-50. ADC Timings in 16-Bit Mode
ADCCLK
CYCLES
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
0
1
1
1.5
2
31
32
1
31
31.0
Invalid
2
60
61
1
1
1
1
1
1
1
1
1
1
1
1
1
1
60
30.0
30.0
30.0
29.7
29.8
29.8
29.8
29.6
29.7
29.7
29.7
29.6
29.6
29.6
3
2.5
3
75
75
75
4
90
91
90
5
3.5
4
104
119
134
149
163
178
193
208
222
237
252
106
120
134
150
165
179
193
209
224
238
252
104
119
134
149
163
178
193
208
222
237
252
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
104
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Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADC S+H
Sample n+1
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
Sample n
(old data)
(old data)
Sample n+1
tSH
tLAT
tEOC
tINT
图 4-35. ADC Timings for 16-Bit Mode
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4.8.1.2 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature
sensor is sampled through an internal connection to the ADC and translated into a temperature through
TI-provided software. When sampling the temperature sensor, the ADC must meet the acquisition time in
Table 4-51.
Table 4-51. Temperature Sensor Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
±15
500
MAX
UNIT
°C
Temperature accuracy
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor)
ADC acquisition time
µs
700
ns
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4.8.2 Comparator Subsystem (CMPSS)
Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs),
two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of
these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the
positive input of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the
negative comparator inputs. There are two comparators, and therefore two outputs from the CMPSS
module, which are connected to the input of a digital filter module before being passed on to the
Comparator TRIP crossbar and either PWM modules or directly to a GPIO pin. 图 4-36 shows the CMPSS
connectivity on the 337-ball ZWT and 176-pin PTP packages. 图 4-37 shows CMPSS connectivity on the
100-pin PZP package.
Comparator Subsystem 1
CMPIN1P Pin
CTRIP1H
Digital
Filter
CTRIPOUT1H
VDDA or VDAC
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
DAC12
DAC12
CTRIP1L
Digital
Filter
CTRIPOUT1L
ePWMs
ePWM X-BAR
CMPIN1N Pin
CMPIN2P Pin
CTRIP8H
CTRIP8L
Comparator Subsystem 2
Digital
CTRIP2H
CTRIPOUT2H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP2L
Digital
Filter
CTRIPOUT2L
CMPIN2N Pin
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem 8
Digital
CMPIN8P Pin
CTRIP8H
Output X-BAR
GPIO Mux
CTRIPOUT8H
VDDA or VDAC
Filter
CTRIPOUT8H
CTRIPOUT8L
DAC12
DAC12
CTRIP8L
Digital
Filter
CTRIPOUT8L
CMPIN8N Pin
图 4-36. CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)
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Comparator Subsystem 1
Digital
CMPIN1P Pin
CTRIP1H
CTRIPOUT1H
VDDA or VDAC
Filter
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CTRIP3H
CTRIP3L
CTRIP4H
CTRIP4L
DAC12
DAC12
CTRIP1L
Digital
Filter
CTRIPOUT1L
ePWM X-BAR
ePWMs
CMPIN1N Pin
CMPIN2P Pin
Comparator Subsystem 2
Digital
CTRIP2H
CTRIPOUT2H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP2L
Digital
Filter
CTRIPOUT2L
CMPIN2N Pin
CMPIN3P Pin
Comparator Subsystem 3
Digital
CTRIP3H
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT3H
CTRIPOUT3L
CTRIPOUT4H
CTRIPOUT4L
CTRIPOUT3H
VDDA or VDAC
Filter
DAC12
DAC12
Output X-BAR
GPIO Mux
CTRIP3L
Digital
Filter
CTRIPOUT3L
CMPIN3N Pin
CMPIN4P Pin
Comparator Subsystem 4
Digital
CTRIP4H
CTRIPOUT4H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP4L
Digital
Filter
CTRIPOUT4L
CMPIN4N Pin
图 4-37. CMPSS Connectivity (100-Pin PZP)
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4.8.2.1 CMPSS Electrical Data and Timing
Table 4-52 shows the comparator electrical characteristics. Figure 4-38 shows the CMPSS comparator
input referred offset. Figure 4-39 shows the CMPSS comparator hysteresis.
Table 4-52. Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power-up time (from COMPCTL[COMPDACE] to
comparator ready)
10
µs
Comparator input (CMPINxx) range
Input referred offset error
0
VDDA
20
V
–20
mV
1x
2x
3x
4x
12
24
36
48
21
26
30
CMPSS
DAC LSB
Hysteresis(1)
Step response
60
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Ramp response (1.65 V/µs)
Ramp response (8.25 mV/µs)
ns
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the CMPSS
DAC reference voltage. Hysteresis is available for all comparator input source configurations.
NOTE
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If
a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal
comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V.
During this time, the internal comparator input will be floating and can decay below VDDA
within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect
result depending on the value of the other comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 4-38. CMPSS Comparator Input Referred Offset
Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 4-39. CMPSS Comparator Hysteresis
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Table 4-53 shows the CMPSS DAC static electrical characteristics. Figure 4-40 shows the CMPSS DAC
static offset. Figure 4-41 shows the CMPSS DAC static gain. Figure 4-42 shows the CMPSS DAC static
linearity.
Table 4-53. CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Internal reference
MIN
0
TYP
MAX
VDDA
VDAC
25
UNIT
CMPSS DAC output range
V
External reference
0
Static offset error(1)
Static gain error(1)
Static DNL
–25
–2
mV
% of FSR
LSB
2
Endpoint corrected
Endpoint corrected
>–1
–16
4
Static INL
16
LSB
Settling to 1 LSB after full-scale output
change
Settling time
Resolution
1
µs
12
bits
Error induced by comparator trip or
CMPSS DAC code change within the
same CMPSS module
CMPSS DAC output disturbance(2)
–100
2.4
100
LSB
CMPSS DAC disturbance time(2)
VDAC reference voltage
VDAC load(3)
200
2.5 or 3.0
6
ns
V
When VDAC is reference
When VDAC is reference
VDDA
kΩ
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
Offset Error
Figure 4-40. CMPSS DAC Static Offset
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Ideal Gain
Actual Gain
Figure 4-41. CMPSS DAC Static Gain
Linearity Error
Figure 4-42. CMPSS DAC Static Linearity
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4.8.3 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal reference DAC and an analog output buffer that is
capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a
known pin voltage when the output buffer is disabled. This pulldown resistor cannot be disabled and
remains as a passive component on the pin, even for other shared pin mux functions. Software writes to
the DAC value register can take effect immediately or can be synchronized with PWMSYNC events.
Each buffered DAC has the following features:
•
•
•
•
12-bit programmable internal DAC
Selectable reference voltage
Pulldown resistor on output
Ability to synchronize with PWMSYNC
The block diagram for the buffered DAC is shown in 图 4-43.
DACCTL[DACREFSEL]
VDAC
0
1
VREFHI
VDDA
DACCTL[LOADMODE]
0
SYSCLK
>
DACVALS
D Q
D Q
12-bit
DAC
DACVALA
Buffer
1
RPD
PWMSYNC1
0
>
VSSA
PWMSYNC2
PWMSYNC3
1
VSSA
2
...
PWMSYNCn
…
n-1
DACCTL[SYNCSEL]
图 4-43. DAC Module Block Diagram
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4.8.3.1 Buffered DAC Electrical Data and Timing
Table 4-54 shows the buffered DAC electrical characteristics. Figure 4-44 shows the buffered DAC offset.
Figure 4-45 shows the buffered DAC gain. Figure 4-46 shows the buffered DAC linearity.
Table 4-54. Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
µs
Power-up time (DACOUTEN to DAC
output valid)
Trimmed offset error
Gain error(2)
DNL(3)
Midpoint
–10
–2.5
> –1
–5
10
mV
2.5 % of FSR
Endpoint corrected
Endpoint corrected
1
5
LSB
LSB
INL
Settling to 2 LSBs after 0.3V-to-3V
transition
DACOUTx settling time
2
µs
Resolution
12
bits
Voltage output range(4)
Capacitive load
Resistive load
RPD
Reference voltage(5)
Reference load(6)
0.3
5
VDDA – 0.3
100
V
pF
Output drive capability
Output drive capability
kΩ
50
2.5 or 3.0
170
kΩ
VDAC or VREFHI
2.4
VDDA
V
VDAC or VREFHI
kΩ
Integrated noise from 100 Hz to 100 kHz
Noise density at 10 kHz
500
µVrms
nVrms/√Hz
V-ns
Output noise
Glitch energy
PSRR(7)
711
1.5
DC up to 1 kHz
70
dB
100 kHz
30
SNR
THD
1020 Hz
67
dB
dB
1020 Hz
–63
1020 Hz, including harmonics and spurs
1020 Hz, including only spurs
66
SFDR
dBc
104
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V unless otherwise noted. Minimum and Maximum values are tested
or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or VREFHI should be less than VDDA
.
(6) Per active Buffered DAC module.
(7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
NOTE
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC
may float to 0 V internally, giving improper DAC output.
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Offset Error
Code 2048
Figure 4-44. Buffered DAC Offset
Actual Gain
Ideal Gain
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 4-45. Buffered DAC Gain
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Linearity Error
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 4-46. Buffered DAC Linearity
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4.9 Control Peripherals
4.9.1 Enhanced Capture (eCAP)
The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall
sensors)
•
•
•
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to
GPIO pins through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 3.4.2 and
Section 3.4.3.
图 4-47 shows the block diagram of an eCAP module.
116
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CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Prescale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
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图 4-47. eCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually
(for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is
off.
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4.9.1.1 eCAP Electrical Data and Timing
Table 4-55 shows the eCAP timing requirement and Table 4-56 shows the eCAP switching characteristics.
Table 4-55. eCAP Timing Requirement(1)
MIN
2tc(SYSCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SYSCLK)
cycles
With input qualifier
1tc(SYSCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 4-24.
Table 4-56. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
118
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4.9.2 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme,
advanced trip-zone functionality, and global register reload capabilities.
图 4-48 shows the signal interconnections with the ePWM. 图 4-49 shows the ePWM trip input
connectivity.
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TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable
00
01
10
11
CTR=CMPC
TBPRD Shadow (24)
CTR=CMPD
Rsvd
CTR=ZERO
CTR=CMPB
TBPRDHR (8)
Sync
Out
Select
EPWMxSYNCO
TBPRD Active (24)
TBCTL[SWFSYNC]
EPWMxSYNCI
8
CTR=PRD
TBCTL[PHSEN]
TBCTL[SYNCOSEL]
DCAEVT1.sync(A)
DCBEVT1.sync(A)
Counter
Up/Down
(16 Bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
CTR=ZERO
EPWMxINT
TBPHSHR (8)
16
8
CTR=PRD or ZERO
CTR=CMPA
EPWMxSOCA
EPWMxSOCB
Phase
Control
On-chip
ADC
TBPHS Active (24)
Event
Trigger
and
CTR=CMPB
CTR=CMPC
Interrupt
(ET)
ADCSOCOUTSEL
CTR=CMPD
Counter Compare (CC)
CTR_Dir
Action
Qualifier
(AQ)
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Select and pulse stretch
for external ADC
CTR=CMPA
CMPAHR (8)
ADCSOCAO
ADCSOCBO
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
CMPBHR (8)
16
EPWMB
ePWMxB
CMPB Active (24)
CMPB Shadow (24)
CMPBHR (8)
CTR=CMPC
EPWMxTZINT
TZ1 to TZ3
TBCNT(16)
EMUSTOP
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
CLOCKFAIL
CMPC[15-0] 16
EQEPxERR
CMPC Active (16)
CMPC Shadow (16)
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
DCBEVT2.inter
TBCNT(16)
CTR=CMPD
CMPD[15-0] 16
CMPD Active (16)
CMPD Shadow (16)
Copyright © 2017, Texas Instruments Incorporated
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
图 4-48. ePWM Submodules and Critical Internal Signal Interconnects
120
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GPIO0
GPIOx
Async/
Sync/
Sync+Filter
XINT5
XINT4
PIE(s),
CLA(s)
INPUT14
INPUT13
Input X-Bar
eCAP6
eCAP5
eCAP4
eCAP3
eCAP2
eCAP1
XINT1
XINT2
XINT3
PIE(s),
CLA(s)
EXTSYNCIN1
ADC
Wrapper(s)
ePWM and eCAP
Sync Chain
EXTSYNCIN2
TZ1
TZ2
TZ3
PIE(s),
CLA(s)
EPWMINT
TZINT
TRIP1
TRIP2
TRIP3
TRIP6
EPWMx.EPWMCLK
EPWMENCLK
TBCLKSYNC
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ADCSOCAO Select Ckt
ADCSOCBO Select Ckt
ePWM
X-Bar
All
ePWM
Modules
SOCA
SOCB
ADC
Wrapper(s)
TRIP14
TRIP15
TZ4
TZ5
TZ6
ECCERR
CPU1.PIEVECTERROR
CPU2.PIEVECTERROR
SD1
Filter-Reset
Filter-Reset
EQEPERR
CLKFAIL
FLT1
FLT1
FLT1
FLT1
PWM11.CMPC
PWM11.CMPD
CPU1.EMUSTOP
CPU2.EMUSTOP
EPWMn.EMUSTOP
Filter-Reset
Filter-Reset
FLT1
FLT1
FLT1
PWM12.CMPC
PWM12.CMPD
FLT1
CPUSEL0.EPWMx
SD2
Copyright © 2017, Texas Instruments Incorporated
图 4-49. ePWM Trip Input Connectivity
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4.9.2.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization chain on the device provides flexibility in partitioning the ePWM
and eCAP modules between CPU1 and CPU2 and allows localized synchronization within the modules
belonging to the same CPU. Like the other peripherals, the partitioning of the ePWM and eCAP modules
needs to be done using the CPUSELx registers. 图 4-50 shows the synchronization chain architecture.
EXTSYNCIN1
EXTSYNCIN2
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM3
EPWM4
EXTSYNCOUT
Pulse-Stretched
EPWM4SYNCOUT
(8 PLLSYSCLK
Cycles)
EPWM5
EPWM6
SYNCSEL.EPWM4SYNCIN
EPWM7
EPWM8
EPWM9
EPWM7SYNCOUT
SYNCSEL.EPWM7SYNCIN
EPWM10
EPWM11
EPWM12
EPWM10SYNCOUT
SYNCSEL.EPWM10SYNCIN
ECAP1
ECAP2
ECAP1SYNCOUT
SYNCSEL.SYNCOUT
SYNCSEL.ECAP1SYNCIN
ECAP3
ECAP4
ECAP5
ECAP6
SYNCSEL.ECAP4SYNCIN
图 4-50. Synchronization Chain Architecture
122
Specifications
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4.9.2.2 ePWM Electrical Data and Timing
Table 4-57 shows the PWM timing requirements and Table 4-58 shows the PWM switching
characteristics.
Table 4-57. ePWM Timing Requirements(1)
MIN
2tc(EPWMCLK)
MAX
UNIT
cycles
cycles
cycles
Asynchronous
Synchronous
tw(SYNCIN)
Sync input pulse width
2tc(EPWMCLK)
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
Table 4-58. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
td(TZ-PWM)
25
ns
4.9.2.2.1 Trip-Zone Input Timing
Table 4-59 shows the trip-zone input timing requirements. Figure 4-51 shows the PWM Hi-Z
characteristics.
Table 4-59. Trip-Zone Input Timing Requirements(1)
MIN
1tc(EPWMCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 4-24.
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 4-51. PWM Hi-Z Characteristics
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4.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing
表 4-60 shows the external ADC start-of-conversion switching characteristics. 图 4-52 shows the
ADCSOCAO or ADCSOCBO timing.
表 4-60. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
图 4-52. ADCSOCAO or ADCSOCBO Timing
124
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4.9.3 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position,
direction, and speed information from rotating machines used in high-performance motion and position-
control systems.
Each eQEP peripheral comprises five major functional blocks:
•
•
•
•
•
Quadrature Capture Unit (QCAP)
Position Counter/Control Unit (PCCU)
Quadrature Decoder Unit (QDU)
Unit Time Base for speed and frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
The eQEP peripherals are clocked by PERx.SYSCLK. 图 4-53 shows the eQEP block diagram.
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System Control
Registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
PIE
16
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
eQEP Peripheral
Copyright © 2017, Texas Instruments Incorporated
图 4-53. eQEP Block Diagram
126
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4.9.3.1 eQEP Electrical Data and Timing
Table 4-61 lists the eQEP timing requirement and Table 4-62 lists the eQEP switching characteristics.
Table 4-61. eQEP Timing Requirements(1)
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK)
tw(QEPP)
QEP input period
2[1tc(SYSCLK) + tw(IQSW)
]
Asynchronous(2)/Synchronous
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
Asynchronous(2)/Synchronous
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 4-24.
(2) See the TMS320F2837xD Dual-Core Delfino™ MCUs Silicon Errata for limitations in the asynchronous mode.
Table 4-62. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
4tc(SYSCLK)
6tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
Delay time, QEP input edge to position compare sync output
td(PCS-OUT)QEP
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4.9.4 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
注
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
4.9.4.1 HRPWM Electrical Data and Timing
Table 4-63 lists the high-resolution PWM switching characteristics.
Table 4-63. High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
128
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4.9.5 Sigma-Delta Filter Module (SDFM)
The SDFM is a four-channel digital filter designed specifically for current measurement and resolver
position decoding in motor control applications. Each channel can receive an independent sigma-delta
(ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital
decimation filters. The filter set includes a fast comparator for immediate digital threshold comparisons for
overcurrent and undercurrent monitoring. 图 4-54 shows a block diagram of the SDFMs.
SDFM features include:
•
Eight external pins per SDFM module:
–
–
Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
•
Four different configurable modulator clock modes:
–
–
–
–
Modulator clock rate equals modulator data rate
Modulator clock rate running at half the modulator data rate
Modulator data is Manchester encoded. Modulator clock not required.
Modulator clock rate is double that of modulator data rate
•
•
Four independent configurable comparator units:
–
–
–
Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
Ability to detect over-value and under-value conditions
Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
Four independent configurable data filter units:
–
–
–
–
Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
Ability to enable or disable individual filter module
Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable
(MFE) bit or the PWM signals.
•
•
Filter data can be 16-bit or 32-bit representation
PWMs can be used to generate modulator clock for sigma-delta modulators
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{5Cꢀ- {igma 5elta Cilter ꢀodule
G4
{treams
Cilter /hannel 1
{51LꢂÇ
{52LꢂÇ
L9[
L9I
Comparator filter
Lnterrupt
Ünit
{51_51
{51_/1
Input
Ctrl
ꢁL9
Data filter
FILRES
ꢁíꢀ11ꢃ/ꢀꢁ/
Cilter /hannel 2
Cilter /hannel 3
Cilter /hannel 4
{51_52
{51_/2
CL[w9{
5ata bus
wegister
ꢀap
{51_53
{51_/3
CL[w9{
CL[w9{
ꢁíꢀ11ꢃ/ꢀꢁ5
{51_54
{51_/4
{51C[Ç1ꢃL9I
{51C[Ç1ꢃL9[
{51C[Ç2ꢃL9I
{51C[Ç2ꢃL9[
{51C[Ç3ꢃL9I
{51C[Ç3ꢃL9[
{51C[Ç4ꢃL9I
{51C[Ç4ꢃL9[
DꢁLh
ꢀÜó
{5Cꢀ- {igma 5elta Cilter ꢀodule
hutput
ó.ar
G4
{treams
Cilter /hannel 1
{52C[Ç1ꢃL9I
{52C[Ç1ꢃL9[
{52C[Ç2ꢃL9I
{52C[Ç2ꢃL9[
L9[
L9I
Comparator filter
Lnterrupt
Ünit
{52_51
{52_/1
Input
Ctrl
Data filter
FILRES
{52C[Ç3ꢃL9I
{52C[Ç3ꢃL9[
{52C[Ç4ꢃL9I
{52C[Ç4ꢃL9[
ꢁíꢀ12ꢃ/ꢀꢁ/
{52_52
{52_/2
Cilter /hannel 2
Cilter /hannel 3
Cilter /hannel 4
CL[w9{
5ata bus
wegister
ꢀap
{52_53
{52_/3
CL[w9{
CL[w9{
ꢁíꢀ12ꢃ/ꢀꢁ5
{52_54
{52_/4
图 4-54. SDFM Block Diagram
130
Specifications
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4.9.5.1 SDFM Electrical Data and Timing
Table 4-64 shows the SDFM timing requirements. Figure 4-55 through Figure 4-58 show the SDFM timing
diagrams.
Table 4-64. SDFM Timing Requirements
MIN
MAX UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
40
10
256 * SYSCLK period
ns
ns
tw(SDCH)M0
Pulse duration, SDx_Cy high
tc(SDC)M0 – 10
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
5
5
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 1
tc(SDC)M1
Cycle time, SDx_Cy
80
10
5
256 * SYSCLK period
tc(SDC)M1 – 10
ns
ns
ns
tw(SDCH)M1
Pulse duration, SDx_Cy high
Setup time, SDx_Dy valid before SDx_Cy goes low
tsu(SDDV-SDCL)M1
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M1
5
ns
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes low
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 2
5
5
ns
ns
tc(SDD)M2
Cycle time, SDx_Dy
8 * tc(SYSCLK)
10
20 * tc(SYSCLK)
ns
ns
tw(SDDH)M2
Pulse duration, SDx_Dy high
Mode 3
tc(SDC)M3
Cycle time, SDx_Cy
40
10
256 * SYSCLK period
tc(SDC)M3 – 5
ns
ns
tw(SDCH)M3
Pulse duration, SDx_Cy high
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
5
5
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 0
SDx_Cy
tw(SDCH)M0
tc(SDC)M0
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
SDx_Dy
Figure 4-55. SDFM Timing Diagram – Mode 0
Mode 1
SDx_Cy
tw(SDCH)M1
tc(SDC)M1
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
SDx_Dy
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Figure 4-56. SDFM Timing Diagram – Mode 1
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Mode 2
(Manchester-encoded bit stream)
tc(SDD)M2
Modulator
internal clock
tw(SDDH)M2
Modulator
internal data
0
0
0
1
1
1
1
1
1
SDx-Dy
Figure 4-57. SDFM Timing Diagram – Mode 2
(CLKx is driven externally)
tc(SDC)M3
Mode 3
SDx_Cy
tw(SDCH)M3
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
SDx_Dy
Figure 4-58. SDFM Timing Diagram – Mode 3
132
Specifications
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4.10 Communications Peripherals
4.10.1 Controller Area Network (CAN)
注
The CAN module uses the IP known as D_CAN. This document uses the names CAN and
D_CAN interchangeably to reference this peripheral.
The CAN module implements the following features:
•
•
•
•
Complies with ISO 11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects, each with the following properties:
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Programmable receive and identifier masks for each object
Supports data and remote frames
Holds 0 to 8 bytes of data
Parity-checked configuration and data RAM
•
•
•
•
•
•
•
•
•
Individual identifier mask for each message object
Programmable FIFO mode for receive message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM parity check mechanism
Two interrupt lines
Global power down and wakeup support
注
For a CANx Bit-CLK of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
注
The accuracy of the on-chip zero-pin oscillator is in 表 4-18, Internal Oscillator Electrical
Characteristics. Depending on parameters such as the CAN bit timing settings, bit rate, bus
length, and propagation delay, the accuracy of this oscillator may not meet the requirements
of the CAN protocol. In this situation, an external clock source must be used.
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4.10.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
•
•
One 16-byte receive FIFO and one 16-byte transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
134
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图 4-59 shows how the I2C peripheral module interfaces within the device.
I2C Module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
SDA
Peripheral Bus
I2CRSR
I2CDRR
Control/Status
Registers
CPU
Clock
Synchronizer
SCL
Prescaler
Noise Filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
图 4-59. I2C Peripheral Module Interfaces
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4.10.2.1 I2C Electrical Data and Timing
Table 4-65 shows the I2C timing requirements. Table 4-66 shows the I2C switching characteristics.
Table 4-65. I2C Timing Requirements
MIN
MAX
UNIT
Hold time, START condition, SCL fall delay
after SDA fall
th(SDA-SCL)START
tsu(SCL-SDA)START
0.6
µs
Setup time, Repeated START, SCL rise before
SDA fall delay
0.6
µs
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
Input tolerance
Input tolerance
Input tolerance
Input tolerance
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before
SDA rise delay
tsu(SCL-SDA)STOP
0.6
µs
Table 4-66. I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
fSCL
SCL clock frequency
0
1.3
0.6
400
kHz
µs
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
Pulse duration of spikes that will be
suppressed by the input filter
tw(SP)
tBUF
0
50
ns
µs
Bus free time between STOP and START
conditions
1.3
tv(SCL-DAT)
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
0.9
0.9
µs
µs
V
tv(SCL-ACK)
VIL
VIH
VOL
II
–0.3
0.7 * VDDIO
0
0.3 * VDDIO
VDDIO + 0.3
0.4
V
Sinking 3 mA
V
Input current on pins
0.1 Vbus < Vi < 0.9 Vbus
–10
10
µA
NOTE
To meet all of the I2C protocol timing specifications, the I2C module clock must be
configured between 7 MHz to 12 MHz.
136
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4.10.3 Multichannel Buffered Serial Port (McBSP)
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
8-bit data transfer mode can be configured to transmit with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
Supports AC97, I2S, and SPI protocols
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR.
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图 4-60 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
CPU
Peripheral Write Bus
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
DXR1 Transmit Buffer
16
PERx.LSPCLK
MFSXx
16
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
RSR1
16
RSR2
16
CPU
DMA Bus
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
Interrupt Select Logic
16
16
RX
Interrupt
RX Interrupt Logic
MRINT
CPU
Peripheral Read Bus
To CPU
图 4-60. McBSP Block Diagram
138
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4.10.3.1 McBSP Electrical Data and Timing
4.10.3.1.1 McBSP Transmit and Receive Timing
Table 4-67 shows the McBSP timing requirements. Table 4-68 shows the McBSP switching
characteristics. Figure 4-61 and Figure 4-62 show the McBSP timing diagrams.
Table 4-67. McBSP Timing Requirements(1) (2)
NO.
MIN
MAX UNIT
1
kHz
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
25
1
MHz
ns
40
ms
ns
M11
M12
M13
M14
tc(CKRX)
tw(CKRX)
tr(CKRX)
tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
P – 7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15
M16
M17
M18
M19
M20
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
18
5
0
Hold time, DR valid after CLKR low
3
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
0
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
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Table 4-68. McBSP Switching Characteristics(1) (2)
over recommended operating conditions (unless otherwise noted)
NO.
M1
M2
M3
PARAMETER
Cycle time, CLKR/X
MIN
MAX UNIT
tc(CKRX)
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
(3)
(3)
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5
D + 5
ns
ns
(3)
(3)
C – 5
C + 5
0
3
0
3
4
27
4
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
27
8
Disable time, CLKX high to DX high impedance
following last data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit
transmitted.
CLKX ext
28
CLKX int
CLKX ext
CLKX int
8
Delay time, CLKX high to DX
DXENA = 0
valid
M7
td(CKXH-DXV)
ns
14
Only applies to first bit
P + 8
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 14
or 10b) modes
CLKX int
CLKX ext
CLKX int
0
6
Enable time, CLKX high to
DXENA = 0
DX driven
Only applies to first bit
P
M8
M9
ten(CKXH-DX)
ns
ns
ns
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 6
or 10b) modes
FSX int
FSX ext
FSX int
8
14
Delay time, FSX high to DX
DXENA = 0
valid
Only applies to first bit
P + 8
td(FXH-DXV)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 14
mode.
FSX int
FSX ext
FSX int
0
6
Enable time, FSX high to DX
DXENA = 0
driven
Only applies to first bit
P
M10 ten(FXH-DX)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 6
mode
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
FSR (ext)
M15
M17
M16
M18
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−3)
M18
M17
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 4-61. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 4-62. McBSP Transmit Timing
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4.10.3.1.2 McBSP as SPI Master or Slave Timing
For CLKSTP = 10b and CLKXP = 0, Table 4-69 shows the timing requirements, Table 4-70 shows the
switching characteristics, and Figure 4-63 shows the timing diagram.
Table 4-69. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 4-70. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
M24
M25
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
2P(1)
P
ns
ns
Disable time, DX high impedance following
last data bit from FSX high
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M33
M32
MSB
LSB
CLKX
M25
M24
FSX
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 4-63. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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For CLKSTP = 11b and CLKXP = 0, Table 4-71 shows the timing requirements, Table 4-72 shows the
switching characteristics, and Figure 4-64 shows the timing diagram.
Table 4-71. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 4-72. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
P
2P(1)
MAX
M34
M35
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
Disable time, DX high impedance following last data bit
from CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M42
MSB
LSB
M41
CLKX
FSX
M35
M34
M37
M38
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M39
M40
Bit 0
(n-2)
(n-3)
(n-4)
Figure 4-64. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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For CLKSTP = 10b and CLKXP = 1, Table 4-73 shows the timing requirements, Table 4-74 shows the
switching characteristics, and Figure 4-65 shows the timing diagram.
Table 4-73. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M49
M50
M51
M52
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 4-74. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
M47 tdis(FXH-DXHZ)
6
6
6P + 6
ns
ns
M48 td(FXL-DXV)
(1) 2P = 1/CLKG
Delay time, FSX low to DX valid
4P + 6
M52
M51
MSB
LSB
CLKX
M43
M44
FSX
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
(n-4)
Figure 4-65. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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For CLKSTP = 11b and CLKXP = 1, Table 4-75 shows the timing requirements, Table 4-76 shows the
switching characteristics, and Figure 4-66 shows the timing diagram.
Table 4-75. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 4-76. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
MASTER(2)
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
P
2P(1)
MAX
MAX
M53
M54
M55
th(CKXH-FXL)
td(FXL-CKXL)
td(CLKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
ns
ns
ns
–2
0
3P + 6
7P + 6
4P + 6
5P + 20
Disable time, DX high impedance following last
data bit from CLKX high
M56
M57
tdis(CKXH-DXHZ)
td(FXL-DXV)
P + 6
6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
M53
FSX
M56
M55
M57
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
M58
M59
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 4-66. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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4.10.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard non-
return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register. 图 4-67 shows the SCI block diagram.
Features of the SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates
–
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from 1 to 8 bits
Optional even/odd/no parity bit
1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wakeup multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
注
All registers in this module are 8-bit registers. When a register is accessed, the register data
is in the lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the
upper byte has no effect.
146
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SCICTL1.1
Frame Format and Mode
Parity
SCITXD
SCITXD
TXSHF
Register
TXENA
TX EMPTY
SCICTL2.6
Even/Odd
Enable
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
SCICTL2.0
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
8
SCICTL1.3
1
TX FIFO _0
TX FIFO _1
−−−−−
TXINT
To CPU
TX Interrupt
Logic
TX FIFO Interrupt
TX FIFO _15
SCI TX Interrupt select logic
Auto baud detect logic
WUT
SCITXBUF.7−0
TX FIFO registers
SCIFFENA
SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
SCIRXD
Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
RXENA
SCICTL1.0
Baud Rate
LSbyte
8
SCICTL2.1
Register
RXRDY
RX/BK INT ENA
Receive Data
Buffer register
SCIRXST.6
SCIRXBUF.7−0
8
BRKDT
SCIRXST.5
RX FIFO _15
−−−−−
RX FIFO_1
RX Interrupt
Logic
RXINT
RX FIFO _0
RX FIFO Interrupt
To CPU
SCIRXBUF.7−0
RX FIFO registers
RXFFOVF
SCIRXST.7
RX Error
SCIRXST.4 – 2
FE OE PE
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
图 4-67. SCI Block Diagram
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The major elements used in full-duplex operation include:
•
•
A transmitter (TX) and its major registers:
–
SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
–
TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts
data onto the SCITXD pin, 1 bit at a time
A receiver (RX) and its major registers:
–
–
RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data
from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and
SCIRXEMU registers
•
•
A programmable baud generator
Data-memory-mapped control and status registers enable the CPU to access the I2C module registers
and FIFOs.
The SCI receiver and transmitter operate independently.
148
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4.10.5 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of
programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The SPI is normally used for communications between the microcontroller and external peripherals or
another controller. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI. The port supports 16-level receive and transmit FIFOs for reducing
CPU servicing overhead.
The SPI module features include:
•
•
•
•
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: master and slave
Baud rate: 125 different programmable rates
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
•
•
•
•
•
16-level transmit and receive FIFO
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
DMA support
High-speed mode for up to 50-MHz full-duplex communication
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The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK
signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the
SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit
(SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result,
both controllers send and receive data simultaneously. The application software determines whether the
data is meaningful or dummy data. There are three possible methods for data transmission:
•
•
•
Master sends data; slave sends dummy data
Master sends data; slave sends data
Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
图 4-68 shows the SPI CPU Interface.
PCLKCR8
Low-Speed
LSPCLK
SYSCLK
CPU
Prescaler
Bit
Clock
SYSRS
SPISIMO
SPISOMI
SPICLK
GPIO
MUX
SPI
SPIINT
SPITXINT
PIE
SPISTE
SPIRXDMA
SPITXDMA
DMA
图 4-68. SPI CPU Interface
150
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4.10.5.1 SPI Electrical Data and Timing
The following sections contain the SPI External Timings in Non-High-Speed Mode:
节 4.10.5.1.1
节 4.10.5.1.2
Non-High-Speed Master Mode Timings
Non-High-Speed Slave Mode Timings
The following sections contain the SPI External Timings in High-Speed Mode:
节 4.10.5.1.3
节 4.10.5.1.4
High-Speed Master Mode Timings
High-Speed Slave Mode Timings
注
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on
SPICLK, SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter
of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual.
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see
Section 3.4.5).
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4.10.5.1.1 Non-High-Speed Master Mode Timings
Table 4-77 lists the SPI master mode switching characteristics where the clock phase = 0. 图 4-69 shows
the SPI master mode external timing where the clock phase = 0.
Table 4-78 lists the SPI master mode switching characteristics where the clock phase = 1. 图 4-70 shows
the SPI master mode external timing where the clock phase = 1.
Table 4-79 lists the SPI master mode timing requirements.
Table 4-77. SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
2
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M
+
0.5tc(SPC)M +
Odd
Even
Odd
0.5tc(LSPCLK) – 3
0.5tc(LSPCLK) + 3
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK, second
pulse
3
4
5
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
ns
0.5tc(SPC)M
–
0.5tc(SPC)M
0.5tc(LSPCLK) + 3
–
0.5tc(LSPCLK) – 3
Delay time, SPICLK to SPISIMO
valid
Even, Odd
Even
Odd
3
0.5tc(SPC)M – 3
0.5tc(SPC)M
Valid time, SPISIMO valid after
SPICLK
–
0.5tc(LSPCLK) – 3
Even
Odd
tc(SPC)M – 3
Delay time, SPISTE active to
SPICLK
23 td(SPC)M
ns
ns
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 3
Even
Odd
0.5tc(SPC)M – 3
Delay time, SPICLK to SPISTE
inactive
24 td(STE)M
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 3
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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Table 4-78. SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
ns
1
tc(SPC)M
Cycle time, SPICLK
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
2
3
4
5
tw(SPC1)M
Pulse duration, SPICLK, first pulse
ns
ns
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
0.5tc(SPC)M –
0.5tc(LSPCLK) + 3
Odd
Even
Odd
Even
Odd
Even
Odd
0.5tc(SPC)M – 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK, second
pulse
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
+
0.5tc(SPC)M
+
0.5tc(LSPCLK) + 3
0.5tc(SPC)M – 3
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
+
0.5tc(SPC)M – 3
Valid time, SPISIMO valid after
SPICLK
ns
ns
ns
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
Delay time, SPISTE active to
SPICLK
23 td(SPC)M
Even, Odd
Even
tc(SPC)M – 3
0.5tc(SPC)M – 3
Delay time, SPICLK to
SPISTE inactive
24 td(STE)M
0.5tc(SPC)M
0.5tc(LSPCLK) – 3
–
Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Table 4-79. SPI Master Mode Timing Requirements
(BRR + 1)
NO.
8
MIN
20
0
MAX UNIT
CONDITION(1)
Setup time, SPISOMI valid before
SPICLK
tsu(SOMI)M
th(SOMI)M
Even, Odd
ns
ns
Hold time, SPISOMI valid after
SPICLK
9
Even, Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
图 4-69. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
图 4-70. SPI Master Mode External Timing (Clock Phase = 1)
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4.10.5.1.2 Non-High-Speed Slave Mode Timings
Table 4-80 lists the SPI slave mode switching characteristics. Table 4-81 lists the SPI slave mode timing
requirements.
图 4-71 shows the SPI slave mode external timing where the clock phase = 0. 图 4-72 shows the SPI
slave mode external timing where the clock phase = 1.
Table 4-80. SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
15
PARAMETER
MIN
MAX UNIT
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
20
ns
ns
16
0
Table 4-81. SPI Slave Mode Timing Requirements
NO.
12
13
14
19
20
25
26
MIN
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
ns
ns
ns
ns
ns
ns
ns
tw(SPC1)S
tw(SPC2)S
tsu(SIMO)S
th(SIMO)S
tsu(STE)S
th(STE)S
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
图 4-71. SPI Slave Mode External Timing (Clock Phase = 0)
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
图 4-72. SPI Slave Mode External Timing (Clock Phase = 1)
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4.10.5.1.3 High-Speed Master Mode Timings
Table 4-82 lists the SPI high-speed master mode switching characteristics where the clock phase = 0. 图
4-73 shows the high-speed SPI master mode external timing where the clock phase = 0.
Table 4-83 lists the SPI high-speed master mode switching characteristics where the clock phase = 1. 图
4-74 shows the high-speed SPI master mode external timing where the clock phase = 1.
Table 4-84 lists the SPI high-speed master mode timing requirements.
Table 4-82. SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
2
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M
+
0.5tc(SPC)M +
Odd
Even
Odd
0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
pulse
3
4
5
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
ns
0.5tc(SPC)M
–
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
–
0.5tc(LSPCLK) – 1
Delay time, SPICLK to SPISIMO
valid
Even, Odd
Even
Odd
1
0.5tc(SPC)M – 1
0.5tc(SPC)M
Valid time, SPISIMO valid after
SPICLK
–
0.5tc(LSPCLK) – 1
Even
Odd
tc(SPC)M – 1
Delay time, SPISTE active to
SPICLK
23 td(SPC)M
ns
ns
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 1
Even
Odd
0.5tc(SPC)M – 1
Delay time, SPICLK to SPISTE
inactive
24 td(STE)M
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 1
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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Table 4-83. SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
tc(SPC)M
Cycle time, SPICLK
ns
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
2
3
4
5
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M
–
0.5tc(SPC)M –
Odd
Even
Odd
Even
Odd
Even
Odd
0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
pulse
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
ns
ns
0.5tc(SPC)M
+
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
+
0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 1
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 1
Valid time, SPISIMO valid after
SPICLK
ns
ns
ns
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 1
Delay time, SPISTE active to
SPICLK
23 td(SPC)M
Even, Odd
tc(SPC)M – 1
Even
Odd
0.5tc(SPC)M – 1
Delay time, SPICLK to SPISTE
inactive
24 td(STE)M
0.5tc(SPC)M
–
0.5tc(LSPCLK) – 1
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Table 4-84. SPI High-Speed Master Mode Timing Requirements
(BRR + 1)
NO.
8
MIN
1
MAX UNIT
CONDITION(1)
Setup time, SPISOMI valid before
SPICLK
tsu(SOMI)M
th(SOMI)M
Even, Odd
ns
ns
Hold time, SPISOMI valid after
SPICLK
9
Even, Odd
5
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
158
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
图 4-73. High-Speed SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
图 4-74. High-Speed SPI Master Mode External Timing (Clock Phase = 1)
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4.10.5.1.4 High-Speed Slave Mode Timings
Table 4-85 lists the SPI high-speed slave mode switching characteristics. Table 4-86 lists the SPI high-
speed slave mode timing requirements.
图 4-75 shows the high-speed SPI slave mode external timing where the clock phase = 0. 图 4-76 shows
the high-speed SPI slave mode external timing where the clock phase = 1.
Table 4-85. SPI High-Speed Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
15
PARAMETER
MIN
MAX UNIT
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
9
ns
ns
16
0
Table 4-86. SPI High-Speed Slave Mode Timing Requirements
NO.
12
13
14
19
20
25
26
MIN
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
ns
ns
ns
ns
ns
ns
ns
tw(SPC1)S
tw(SPC2)S
tsu(SIMO)S
th(SIMO)S
tsu(STE)S
th(STE)S
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
图 4-75. High-Speed SPI Slave Mode External Timing (Clock Phase = 0)
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
图 4-76. High-Speed SPI Slave Mode External Timing (Clock Phase = 1)
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4.10.6 Universal Serial Bus (USB) Controller
The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
•
•
•
•
USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
Integrated PHY
Three transfer types: control, interrupt, and bulk
32 endpoints
–
–
One dedicated control IN endpoint and one dedicated control OUT endpoint
15 configurable IN endpoints and 15 configurable OUT endpoints
•
4KB of dedicated endpoint memory
图 4-77 shows the USB block diagram.
Endpoint Control
Transmit
Receive
EP0 –31
Control
CPU Interface
Interrupt
Control
Interrupts
CPU Bus
Host
Transaction
Scheduler
Combine
Endpoints
EP Reg.
Decoder
Common
Regs
UTM
Synchronization
Packet
Encode/Decode
FIFO RAM
Controller
USB PHY
Rx
Buff
Rx
Buff
Data Sync
Packet Encode
Packet Decode
CRC Gen/Check
Cycle
Control
Tx
Buff
Tx
Buff
HNP/SRP
USB FS/LS
PHY
FIFO
Decoder
Timers
Cycle Control
USB DataLines
D+ andD-
图 4-77. USB Block Diagram
注
The accuracy of the on-chip zero-pin oscillator (表 4-18, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external
clock source must be used for applications using USB. For applications using the USB boot
mode, see 节 5.10 (Boot ROM and Peripheral Booting) for clock frequency requirements.
162
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4.10.6.1 USB Electrical Data and Timing
Table 4-87 shows the USB input ports DP and DM timing requirements. Table 4-88 shows the USB output
ports DP and DM switching characteristics.
Table 4-87. USB Input Ports DP and DM Timing Requirements
MIN
0.8
MAX
UNIT
V
V(CM)
Z(IN)
VCRS
VIL
Differential input common mode range
Input impedance
2.5
300
1.3
kΩ
V
Crossover voltage
2.0
Static SE input logic-low level
Static SE input logic-high level
Differential input voltage
0.8
V
VIH
2.0
0.2
V
VDI
V
Table 4-88. USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
D+, D– single-ended
D+, D– single-ended
D+, D– impedance
TEST CONDITIONS
MIN
MAX
UNIT
V
VOH
USB 2.0 load conditions
USB 2.0 load conditions
2.8
0
3.6
0.3
44
VOL
V
Z(DRV)
28
Ω
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
tr
tf
Rise time
Fall time
4
4
20
20
ns
ns
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
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4.10.7 Universal Parallel Port (uPP) Interface
The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals.
The uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It
can also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve
high-speed digital data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU
overhead during high-speed data transmission. All uPP transactions use internal DMA to feed data to or
retrieve data from the I/O channels. Even though there is only one I/O channel, the DMA controller
includes two DMA channels to support data interleave mode, in which all DMA resources service a single
I/O channel.
On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1,
and CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG
RAMs) are tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to
store the bulk of data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have
access to these data RAMs. 图 4-78 shows the integration of the uPP on this device.
CPU1
RX-DATARAM
READ
Arbi
Arbiter Y
512 Byte
(Dual Port
t
Memory)
CPU1.CLA1
uPP DMA WRITE
CPU1
I/O Interface
Arbi
Arbiter X
uPP
(Universal
CPU1.CLA1
t
0
1
Parallel Port)
CPU1.DMA
uPP DMA READ
SECMSEL.PF2SEL
CPU1
TX-DATARAM
512 Byte
WRITE
Arbi
Arbiter Y
(Dual Port
Memory)
t
CPU1.CLA1
图 4-78. uPP Integration
注
On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI)
module.
164
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The uPP interface supports the following:
•
•
•
•
•
•
•
•
•
•
•
Mainstream high-speed data converters with parallel conversion interface.
Mainstream high-speed streaming interface with frame START indication.
Mainstream high-speed streaming interface with data ENABLE indication.
Mainstream high-speed streaming interface with synchronization WAIT signal.
SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
Multiplexing of interleaved data in SDR transmit case.
Demultiplexing and multiplexing of interleaved data in DDR case.
I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
Single-channel 8-bit input receive or output transmit mode.
Max throughput is 50MB/s for pure read or pure write.
Available as a DSP to FPGA general-purpose streaming interface.
图 4-79 shows the uPP functional block diagram.
uPP
Configuration
ENABLE OUT
G
P
I
ENABLE/GPIOx
MMR
I/F
Transmit Timing
and Control
START OUT
WAIT IN
O
CLK OUT
START/GPIOx
WAIT/GPIOx
CPU1.SYSCLK
CLKDIVIDER
M
U
X
CLK IN
ENABLE IN
Receive Timing
and Control
Control Mux
START IN
WAIT OUT
Interrupt/Trigger
and
I/O
CLK/GPIOx
Arbi
I-FIFO
t
C
O
N
T
64 Bit
MEM WR I/F
DATA OUT
DATA IN
DATA[7:0]/GPIOx
Internal
Data Interleaving
(TX/RX)
DMA
Arbit
R
O
L
64 Bit
MEM RD I/F
Arbi
Q-FIFO
图 4-79. uPP Functional Block Diagram
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4.10.7.1 uPP Electrical Data and Timing
Table 4-89 shows the uPP timing requirements. Table 4-90 shows the uPP switching characteristics.
Figure 4-80 through Figure 4-83 show the uPP timing diagrams.
Table 4-89. uPP Timing Requirements
NO.
MIN MAX UNIT
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
20
40
8
1
tc(CLK)
Cycle time, CLK
ns
ns
ns
2
3
tw(CLKH)
Pulse width, CLK high
Pulse width, CLK low
18
8
tw(CLKL)
18
4
4
5
tsu(STV-CLKH)
th(CLKH-STV)
tsu(ENV-CLKH)
th(CLKH-ENV)
tsu(DV-CLKH)
th(CLKH-DV)
Setup time, START valid before CLK high
Hold time, START valid after CLK high
Setup time, ENABLE valid before CLK high
Hold time, ENABLE valid after CLK high
Setup time, DATA valid before CLK high
Hold time, DATA valid after CLK high
Setup time, DATA valid before CLK low
Hold time, DATA valid after CLK low
Setup time, WAIT valid before CLK high
Hold time, WAIT valid after CLK high
Setup time, WAIT valid before CLK low
Hold time, WAIT valid after CLK low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
4
6
7
0.8
4
8
9
0.8
4
10
11
19
20
21
22
tsu(DV-CLKL)
th(CLKL-DV)
0.8
20
0
tsu(WTV-CLKH)
th(CLKH-WTV)
tsu(WTV-CLKL)
th(CLKL-WTV)
SDR mode
SDR mode
DDR mode
DDR mode
20
0
Table 4-90. uPP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN MAX UNIT
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
20
ns
40
12
tc(CLK)
Cycle time, CLK
8
ns
18
13
14
tw(CLKH)
Pulse width, CLK high
Pulse width, CLK low
8
ns
18
tw(CLKL)
15
16
17
18
td(CLKH-STV)
td(CLKH-ENV)
td(CLKH-DV)
td(CLKL-DV)
Delay time, START valid after CLK high
Delay time, ENABLE valid after CLK high
Delay time, DATA valid after CLK high
Delay time, DATA valid after CLK low
3
3
3
3
12
12
12
12
ns
ns
ns
ns
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1
2
3
CLK
START
ENABLE
WAIT
4
5
6
7
8
9
DATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 4-80. uPP Single Data Rate (SDR) Receive Timing
1
2
3
CLK
4
5
START
6
7
ENABLE
WAIT
10
8
11
9
DATA[n:0]
I1 Q1 I2 Q2 I3 Q3
I4 Q4
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
Figure 4-81. uPP Double Data Rate (DDR) Receive Timing
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12
13
14
CLK
START
15
16
ENABLE
WAIT
19
20
17
DATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 4-82. uPP Single Data Rate (SDR) Transmit Timing
12
13
14
CLK
START
ENABLE
WAIT
15
16
21
22
17
18
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
DATA[n:0]
I1 Q1 I2 Q2 I3 Q3
Q4
I4
Figure 4-83. uPP Double Data Rate (DDR) Transmit Timing
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5 Detailed Description
5.1 Overview
The Delfino TMS320F28377D-EP is a powerful 32-bit floating-point microcontroller unit (MCU) designed
for advanced closed-loop control applications such as industrial drives and servo motor control; solar
inverters and converters; digital power; transportation; and power line communications. Complete
development packages for digital power and industrial drives are available as part of the powerSUITE and
DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000 portfolio, the
F28377D supports a new dual-core C28x architecture that significantly boosts system performance. The
integrated analog and control peripherals also let designers consolidate control architectures and eliminate
multiprocessor use in high-end systems.
The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide
200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new
TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in
transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex
math operations common in encoded applications.
The F28377D microcontroller features two CLA real-time control coprocessors. The CLA is an
independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA
responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel
processing capability can effectively double the computational performance of a real-time control system.
By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such
as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning
between various system tasks. For example, one C28x+CLA core can be used to track speed and
position, while the other C28x+CLA core can be used to control torque and current loops.
The TMS320F28377D-EP supports 1MB (512KW) of onboard flash memory with error correction code
(ECC) and up to 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for
code protection.
Performance analog and control peripherals are also integrated on the F28377D MCU to further enable
system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple
analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM)
works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The
Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when
current limit conditions are exceeded or not met. Other analog and control peripherals include DACs,
PWMs, eCAPs, eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface
extend the connectivity of the F28377D. The uPP interface is a new feature of the C2000 MCUs and
supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly,
a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their
application.
5.2 Functional Block Diagram
图 5-1 shows the CPU system and associated peripherals.
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User User
Configurable Configurable
PSWD
DCSM
OTP
1K x 16
DCSM
OTP
1K x 16
PSWD
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
FLASH
256K x 16
Secure
FLASH
256K x 16
Secure
Secure Memories
shown in Red
CPU2.CLA1
PUMP
OTP/Flash
Wrapper
OTP/Flash
Wrapper
MEMCPU1
MEMCPU2
Low-Power
Mode Control
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
GPIO MUX
INTOSC1
CPU2 to CPU2.CLA1
128x16 MSG RAM
CPU1.CLA1 to CPU1
128x16 MSG RAM
C28 CPU-1
FPU
VCU-II
C28 CPU-2
FPU
VCU-II
CPU1.CLA1
CPU1 to CPU1.CLA1
128x16 MSG RAM
CPU2.CLA1 to CPU2
128x16 MSG RAM
CPU2.M0 RAM 1Kx16
CPU2.M1 RAM 1Kx16
TMU
TMU
Watchdog 1/2
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
CPU2 Local Shared
6x 2Kx16
LS0-LS5 RAMs
Interprocessor
Communication
(IPC)
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
CPU2.D0 RAM 2Kx16
CPU2.D1 RAM 2Kx16
Main PLL
INTOSC2
Module
WD Timer
NMI-WDT
WD Timer
NMI-WDT
CPU1.CLA1 Data ROM
(4Kx16)
CPU2.CLA1 Data ROM
(4Kx16)
Global Shared
16x 4Kx16
GS0-GS15 RAMs
External Crystal or
Oscillator
CPU Timer 0
CPU Timer 1
CPU Timer 2
CPU Timer 0
CPU Timer 1
CPU Timer 2
Secure-ROM 32Kx16
Secure
Secure-ROM 32Kx16
Secure
A5:0
B5:0
16-/12-bit ADC
x4
Aux PLL
A
AUXCLKIN
CPU1 to CPU2
1Kx16 MSG RAM
B
Boot-ROM 32Kx16
Nonsecure
Boot-ROM 32Kx16
Nonsecure
ePIE
(up to 192
ePIE
(up to 192
C
ADC
Result
Regs
TRST
Analog
MUX
interrupts)
interrupts)
CPU2 to CPU1
1Kx16 MSG RAM
C5:2
D5:0
D
TCK
TDI
Config
JTAG
TMS
TDO
ADCIN14
ADCIN15
Data Bus
Bridge
CPU1.DMA
CPU2.DMA
Comparator
Subsystem
(CMPSS)
DAC
x3
CPU1 Buses
CPU2 Buses
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Peripheral Frame 1
Data Bus Bridge
Peripheral Frame 2
SCI-
A/B/C/D
(16L FIFO)
USB
Ctrl /
PHY
SPI-
A/B/C
(16L FIFO)
ePWM-1/../12
CAN-
A/B
(32-MBOX)
RAM
I2C-A/B
(16L FIFO)
McBSP-
A/B
eCAP-
1/../6
eQEP-1/2/3
SDFM-1/2
GPIO
EMIF1
EMIF2
uPP
HRPWM-1/../8
(CPU1 only)
GPIO MUX, Input X-BAR, Output X-BAR
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图 5-1. Functional Block Diagram
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5.3 Memory
5.3.1 C28x Memory Map
Both C28x CPUs on the device have the same memory map except where noted in 表 5-1. The
GSx_RAM (Global Shared RAM) should be assigned to either CPU by the GSxMSEL register. Memories
accessible by the CLA or DMA (direct memory access) are noted as well.
表 5-1. C28x Memory Map
MEMORY
SIZE
1K × 16
1K × 16
512 × 16
128 × 16
128 × 16
512 × 16
512 × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
1K × 16
1K × 16
2K × 16
2K × 16
256K × 16
32K × 16
32K × 16
64 × 16
START ADDRESS
0x0000 0000
0x0000 0400
0x0000 0D00
0x0000 1480
0x0000 1500
0x0000 6C00
0x0000 6E00
0x0000 8000
0x0000 8800
0x0000 9000
0x0000 9800
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 C000
0x0000 D000
0x0000 E000
0x0000 F000
0x0001 0000
0x0001 1000
0x0001 2000
0x0001 3000
0x0001 4000
0x0001 5000
0x0001 6000
0x0001 7000
0x0001 8000
0x0001 9000
0x0001 A000
0x0001 B000
0x0003 F800
0x0003 FC00
0x0004 9000
0x0004 B000
0x0008 0000
0x003F 0000
0x003F 8000
0x003F FFC0
END ADDRESS
0x0000 03FF
0x0000 07FF
0x0000 0EFF
0x0000 14FF
0x0000 157F
0x0000 6DFF
0x0000 6FFF
0x0000 87FF
0x0000 8FFF
0x0000 97FF
0x0000 9FFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
0x0000 CFFF
0x0000 DFFF
0x0000 EFFF
0x0000 FFFF
0x0001 0FFF
0x0001 1FFF
0x0001 2FFF
0x0001 3FFF
0x0001 4FFF
0x0001 5FFF
0x0001 6FFF
0x0001 7FFF
0x0001 8FFF
0x0001 9FFF
0x0001 AFFF
0x0001 BFFF
0x0003 FBFF
0x0003 FFFF
0x0004 97FF
0x0004 B7FF
0x000B FFFF
0x003F 7FFF
0x003F FFBF
0x003F FFFF
CLA ACCESS
DMA ACCESS
M0 RAM
M1 RAM
PieVectTable
CPUx.CLA1 to CPUx MSGRAM
CPUx to CPUx.CLA1 MSGRAM
UPP TX MSG RAM
UPP RX MSG RAM
LS0 RAM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LS1 RAM
LS2 RAM
LS3 RAM
LS4 RAM
LS5 RAM
D0 RAM
D1 RAM
GS0 RAM(1)
GS1 RAM(1)
GS2 RAM(1)
GS3 RAM(1)
GS4 RAM(1)
GS5 RAM(1)
GS6 RAM(1)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GS7 RAM(1)
GS8 RAM(1)
GS9 RAM(1)
GS10 RAM(1)
GS11 RAM(1)
GS12 RAM(1)(2)
GS13 RAM(1)(2)
GS14 RAM(1)(2)
GS15 RAM(1)(2)
CPU2 to CPU1 MSGRAM(1)
CPU1 to CPU2 MSGRAM(1)
CAN A Message RAM(1)
CAN B Message RAM(1)
Flash
Secure ROM
Boot ROM
Vectors
(1) Shared between CPU subsystems.
(2) Available only on F28379D, F28378D, F28377D, and F28375D.
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5.3.2 Flash Memory Map
On the F28377D device, each CPU has its own flash bank [512KB (256KW)], the total flash for each
device is 1MB (512KW). Only one bank can be programmed or erased at a time and the code to program
the flash should be executed out of RAM. 表 5-2 shows the addresses of flash sectors on CPU1 and
CPU2 for F28377D.
表 5-2. Addresses of Flash Sectors on CPU1 and CPU2 for F28377D
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP Sectors
Sectors
TI OTP
1K × 16
1K × 16
0x0007 0000
0x0007 8000
0x0007 03FF
0x0007 83FF
User configurable DCSM OTP
Sector A
Sector B
Sector C
Sector D
Sector E
Sector F
Sector G
Sector H
Sector I
8K × 16
8K × 16
8K × 16
8K × 16
32K × 16
32K × 16
32K × 16
32K × 16
32K × 16
32K × 16
8K × 16
8K × 16
8K × 16
8K ×16
0x0008 0000
0x0008 2000
0x0008 4000
0x0008 6000
0x0008 8000
0x0009 0000
0x0009 8000
0x000A 0000
0x000A 8000
0x000B 0000
0x000B 8000
0x000B A000
0x000B C000
0x000B E000
0x0008 1FFF
0x0008 3FFF
0x0008 5FFF
0x0008 7FFF
0x0008 FFFF
0x0009 7FFF
0x0009 FFFF
0x000A 7FFF
0x000A FFFF
0x000B 7FFF
0x000B 9FFF
0x000B BFFF
0x000B DFFF
0x000B FFFF
Sector J
Sector K
Sector L
Sector M
Sector N
Flash ECC Locations
TI OTP ECC
128 × 16
128 × 16
32K × 16
0x0107 0000
0x0107 1000
0x0108 0000
0x0107 007F
0x0107 107F
0x0108 7FFF
User-configurable DCSM OTP
ECC
Flash ECC
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5.3.3 EMIF Chip Select Memory Map
The EMIF1 memory map is the same for both CPU subsystems. EMIF2 is available only on the CPU1
subsystem. The EMIF memory map is shown in 表 5-3.
表 5-3. EMIF Chip Select Memory Map
EMIF CHIP SELECT
EMIF1_CS0n - Data
EMIF1_CS2n - Program + Data(2)
EMIF1_CS3n - Program + Data
EMIF1_CS4n - Program + Data
EMIF2_CS0n - Data(3)
SIZE(1)
256M × 16
2M × 16
START ADDRESS
0x8000 0000
0x0010 0000
0x0030 0000
0x0038 0000
0x9000 0000
0x0000 2000
END ADDRESS
0x8FFF FFFF
0x002F FFFF
0x0037 FFFF
0x003D FFFF
0x91FF FFFF
0x0000 2FFF
CLA ACCESS DMA ACCESS
Yes
Yes
Yes
Yes
512K × 16
393K × 16
3M × 16
EMIF2_CS2n - Program + Data(3)
4K × 16
Yes (Data only)
(1) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory
sizes because of pin mux setting. See Section 3.4.1 to find the available address lines for your use case.
(2) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not used
(tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with
address pins (see Section 3.4.1). If 16-bit memory is used, then the maximum size is 1M × 16.
(3) Available only on the CPU1 subsystem.
5.3.4 Peripheral Registers Memory Map
The peripheral registers memory map can be found in 表 5-4. The peripheral registers can be assigned to
either the CPU1 or CPU2 subsystems except where noted in 表 5-4. Registers in the peripheral frames
share a secondary master (CLA or DMA) selection with all other registers within the same peripheral
frame. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for
details on the CPU subsystem and secondary master selection.
表 5-4. Peripheral Registers Memory Map
START
ADDRESS
END
ADDRESS
CLA
DMA
PROTECTED(1)
REGISTERS
STRUCTURE NAME
ACCESS ACCESS
AdcaResultRegs
AdcbResultRegs
AdccResultRegs
AdcdResultRegs
CpuTimer0Regs(2)
CpuTimer1Regs(2)
CpuTimer2Regs(2)
PieCtrlRegs(2)
ADC_RESULT_REGS
ADC_RESULT_REGS
ADC_RESULT_REGS
ADC_RESULT_REGS
CPUTIMER_REGS
CPUTIMER_REGS
CPUTIMER_REGS
PIE_CTRL_REGS
0x0000 0B00
0x0000 0B20
0x0000 0B40
0x0000 0B60
0x0000 0C00
0x0000 0C08
0x0000 0C10
0x0000 0CE0
0x0000 0B1F
0x0000 0B3F
0x0000 0B5F
0x0000 0B7F
0x0000 0C07
0x0000 0C0F
0x0000 0C17
0x0000 0CFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes –
CLA only,
no CPU
access
Cla1SoftIntRegs
CLA_SOFTINT_REGS
0x0000 0CE0
0x0000 0CFF
DmaRegs(2)
Cla1Regs(2)
DMA_REGS
CLA_REGS
0x0000 1000
0x0000 1400
0x0000 11FF
0x0000 147F
Peripheral Frame 1
EPwm1Regs
EPwm2Regs
EPwm3Regs
EPwm4Regs
EPwm5Regs
EPwm6Regs
EPwm7Regs
EPwm8Regs
EPwm9Regs
EPwm10Regs
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
0x0000 4000
0x0000 4100
0x0000 4200
0x0000 4300
0x0000 4400
0x0000 4500
0x0000 4600
0x0000 4700
0x0000 4800
0x0000 4900
0x0000 40FF
0x0000 41FF
0x0000 42FF
0x0000 43FF
0x0000 44FF
0x0000 45FF
0x0000 46FF
0x0000 47FF
0x0000 48FF
0x0000 49FF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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表 5-4. Peripheral Registers Memory Map (continued)
START
ADDRESS
END
ADDRESS
CLA
DMA
PROTECTED(1)
REGISTERS
STRUCTURE NAME
ACCESS ACCESS
EPwm11Regs
EPwm12Regs
ECap1Regs
ECap2Regs
ECap3Regs
ECap4Regs
ECap5Regs
ECap6Regs
EQep1Regs
EQep2Regs
EQep3Regs
DacaRegs
EPWM_REGS
EPWM_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
EQEP_REGS
EQEP_REGS
EQEP_REGS
DAC_REGS
0x0000 4A00
0x0000 4B00
0x0000 5000
0x0000 5020
0x0000 5040
0x0000 5060
0x0000 5080
0x0000 50A0
0x0000 5100
0x0000 5140
0x0000 5180
0x0000 5C00
0x0000 5C10
0x0000 5C20
0x0000 5C80
0x0000 5CA0
0x0000 5CC0
0x0000 5CE0
0x0000 5D00
0x0000 5D20
0x0000 5D40
0x0000 5D60
0x0000 5E00
0x0000 5E80
0x0000 4AFF
0x0000 4BFF
0x0000 501F
0x0000 503F
0x0000 505F
0x0000 507F
0x0000 509F
0x0000 50BF
0x0000 513F
0x0000 517F
0x0000 51BF
0x0000 5C0F
0x0000 5C1F
0x0000 5C2F
0x0000 5C9F
0x0000 5CBF
0x0000 5CDF
0x0000 5CFF
0x0000 5D1F
0x0000 5D3F
0x0000 5D5F
0x0000 5D7F
0x0000 5E7F
0x0000 5EFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DacbRegs
DAC_REGS
DaccRegs
DAC_REGS
Cmpss1Regs
Cmpss2Regs
Cmpss3Regs
Cmpss4Regs
Cmpss5Regs
Cmpss6Regs
Cmpss7Regs
Cmpss8Regs
Sdfm1Regs
Sdfm2Regs
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
SDFM_REGS
SDFM_REGS
Peripheral Frame 2
McbspaRegs
McbspbRegs
SpiaRegs
MCBSP_REGS
MCBSP_REGS
SPI_REGS
0x0000 6000
0x0000 6040
0x0000 6100
0x0000 6110
0x0000 6120
0x0000 6200
0x0000 603F
0x0000 607F
0x0000 610F
0x0000 611F
0x0000 612F
0x0000 62FF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SpibRegs
SPI_REGS
SpicRegs
SPI_REGS
UppRegs(3)
UPP_REGS
WdRegs(2)
NmiIntruptRegs(2)
XintRegs(2)
WD_REGS
NMI_INTRUPT_REGS
XINT_REGS
0x0000 7000
0x0000 7060
0x0000 7070
0x0000 7200
0x0000 7210
0x0000 7220
0x0000 7230
0x0000 7300
0x0000 7340
0x0000 7400
0x0000 7480
0x0000 7500
0x0000 7580
0x0000 7900
0x0000 7920
0x0000 7940
0x0000 7980
0x0000 7A00
0x0000 703F
0x0000 706F
0x0000 707F
0x0000 720F
0x0000 721F
0x0000 722F
0x0000 723F
0x0000 733F
0x0000 737F
0x0000 747F
0x0000 74FF
0x0000 757F
0x0000 75FF
0x0000 791F
0x0000 793F
0x0000 794F
0x0000 798F
0x0000 7A3F
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SciaRegs
SCI_REGS
ScibRegs
SCI_REGS
ScicRegs
SCI_REGS
ScidRegs
SCI_REGS
I2caRegs
I2C_REGS
I2cbRegs
I2C_REGS
AdcaRegs
ADC_REGS
Yes
Yes
Yes
Yes
AdcbRegs
ADC_REGS
AdccRegs
ADC_REGS
AdcdRegs
ADC_REGS
InputXbarRegs(3)
XbarRegs(3)
TrigRegs(3)
INPUT_XBAR_REGS
XBAR_REGS
TRIG_REGS
DmaClaSrcSelRegs(2)
EPwmXbarRegs(3)
DMA_CLA_SRC_SEL_REGS
EPWM_XBAR_REGS
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表 5-4. Peripheral Registers Memory Map (continued)
START
ADDRESS
END
ADDRESS
CLA
DMA
PROTECTED(1)
REGISTERS
STRUCTURE NAME
ACCESS ACCESS
OutputXbarRegs(3)
GpioCtrlRegs(3)
GpioDataRegs(2)
UsbaRegs(3)
Emif1Regs
OUTPUT_XBAR_REGS
GPIO_CTRL_REGS
GPIO_DATA_REGS
USB_REGS
0x0000 7A80
0x0000 7C00
0x0000 7F00
0x0004 0000
0x0004 7000
0x0004 7800
0x0004 8000
0x0004 A000
0x0000 7ABF
0x0000 7D7F
0x0000 7F2F
0x0004 0FFF
0x0004 77FF
0x0004 7FFF
0x0004 87FF
0x0004 A7FF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EMIF_REGS
Emif2Regs(3)
CanaRegs
EMIF_REGS
CAN_REGS
CanbRegs
CAN_REGS
IPC_REGS_CPU1
IPC_REGS_CPU2
IpcRegs(2)
0x0005 0000
0x0005 0023
Yes
FlashPumpSemaphoreRegs(2)
DevCfgRegs(3)
FLASH_PUMP_SEMAPHORE_REGS
DEV_CFG_REGS
0x0005 0024
0x0005 D000
0x0005 D180
0x0005 D200
0x0005 D300
0x0005 E608
0x0005 F000
0x0005 F040
0x0005 F070
0x0005 F400
0x0005 F480
0x0005 F4A0
0x0005 F4C0
0x0005 F500
0x0005 F540
0x0005 F800
0x0005 FB00
0x0005 0025
0x0005 D17F
0x0005 D1FF
0x0005 D2FF
0x0005 D3FF
0x0005 E60B
0x0005 F02F
0x0005 F05F
0x0005 F07F
0x0005 F47F
0x0005 F49F
0x0005 F4BF
0x0005 F4FF
0x0005 F53F
0x0005 F541
0x0005 FAFF
0x0005 FB3F
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
AnalogSubsysRegs(3)
ClkCfgRegs(4)
ANALOG_SUBSYS_REGS
CLK_CFG_REGS
CpuSysRegs(2)
CPU_SYS_REGS
RomPrefetchRegs(3)
DcsmZ1Regs(2)
ROM_PREFETCH_REGS
DCSM_Z1_REGS
DcsmZ2Regs(2)
DCSM_Z2_REGS
DcsmCommonRegs(2)
MemCfgRegs(2)
DCSM_COMMON_REGS
MEM_CFG_REGS
Emif1ConfigRegs(2)
Emif2ConfigRegs(3)
AccessProtectionRegs(2)
MemoryErrorRegs(2)
RomWaitStateRegs(3)
Flash0CtrlRegs(2)
Flash0EccRegs(2)
EMIF1_CONFIG_REGS
EMIF2_CONFIG_REGS
ACCESS_PROTECTION_REGS
MEMORY_ERROR_REGS
ROM_WAIT_STATE_REGS
FLASH_CTRL_REGS
FLASH_ECC_REGS
(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.
(2) A unique copy of these registers exist on each CPU subsystem.
(3) These registers are available only on the CPU1 subsystem.
(4) These registers are mapped to either CPU1 or CPU2 based on a semaphore.
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5.3.5 Memory Types
表 5-5 provides more information about each memory type.
表 5-5. Memory Types
HIBERNATE
RETENTION
ACCESS
PROTECTION
MEMORY TYPE
ECC-CAPABLE
PARITY
SECURITY
M0, M1
D0, D1
LSx
Yes
Yes
–
–
–
–
Yes
–
–
Yes
Yes
–
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
–
–
GSx
–
–
CPU/CLA MSGRAM
Boot ROM
–
Yes
–
–
–
N/A
N/A
N/A
N/A
Secure ROM
–
–
Yes
Yes
Yes
–
Flash
Yes
Yes
–
N/A
N/A
User-configurable DCSM OTP
–
5.3.5.1 Dedicated RAM (Mx and Dx RAM)
The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1
memories are small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has
access to them). D0/D1 memories are secure blocks and also have the access-protection feature (CPU
write/CPU fetch protection).
5.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU
write/CPU fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
表 5-6 shows the master access for the LSx RAM.
表 5-6. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
CPU ALLOWED
ACCESS
CLA ALLOWED
ACCESS
MSEL_LSx
CLAPGM_LSx
COMMENT
LSx memory is configured
as CPU dedicated RAM.
00
01
01
X
0
1
All
All
–
Data Read
Data Write
LSx memory is shared
between CPU and CLA1.
Emulation Read
Emulation Write
LSx memory is CLA1
program memory.
Fetch Only
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5.3.5.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx
RAMs). Each shared RAM block can be owned by either CPU subsystem based on the configuration of
respective bits in the GSxMSEL register. Both the CPU and DMA have full read and write access to these
memories.
All GSx RAM blocks have parity.
When a GSx RAM block is owned by a CPU subsystem, the CPUx and CPUx.DMA will have full access to
that RAM block whereas the other CPUy and CPUy.DMA will only have read access (no fetch/write
access).
表 5-7 shows the master access for the GSx RAM.
表 5-7. Master Access for GSx RAM
(With Assumption That all Other Access Protections are Disabled)
INSTRUCTION
FETCH
CPUx.DMA
READ
CPUx.DMA
WRITE
GSxMSEL
CPU
READ
WRITE
CPU1
CPU2
CPU1
CPU2
Yes
–
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
Yes
Yes
–
0
–
–
–
1
Yes
Yes
Yes
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
5.3.5.4 CPU Message RAM (CPU MSGRAM)
These RAM blocks can be used to share data between CPU1 and CPU2. Since these RAMs are used for
interprocessor communication, they are also called IPC RAMs. The CPU MSGRAMs have CPU/DMA
read/write access from its own CPU subsystem, and CPU/DMA read only access from the other
subsystem.
This RAM has parity.
5.3.5.5 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write
access to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA
MSGRAM." The CPU and CLA both have read access to both MSGRAMs.
This RAM has parity.
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5.4 Identification
表 5-8 shows the Device Identification Registers.
表 5-8. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
PARTIDH (CPU1)
0x0005 D00A
0x0007 0202
2
TMS320F28377D
0x00FF 0300
PARTIDH (CPU2)
REVID
Silicon revision number
Revision 0
0x0000 0000
0x0000 0000
0x0000 0002
0x0000 0003
0x0005 D00C
0x0007 03C0
2
2
Revision A
Revision B
Revision C
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
a serial number in the application. This number is present only
on TMS Revision C devices.
UID_UNIQUE
CPU identification number
CPU ID
0x0007 026D
N/A
1
CPU1
0xXX01
CPU2
0xXX02
JTAG ID
N/A
JTAG Device ID
0x0B99 C02F
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5.5 Bus Architecture – Peripheral Connectivity
表 5-9 shows a broad view of the peripheral and configuration register accessibility from each bus master.
Peripherals can be individually assigned to the CPU1 or CPU2 subsystem (for example, ePWM can be
assigned to CPU1 and eQEP assigned to CPU2). Peripherals within peripheral frames 1 or 2 will all be
mapped to the respective secondary master as a group (if SPI is assigned to CPUx.DMA, then McBSP is
also assigned to CPUx.DMA).
表 5-9. Bus Master Peripheral Access
PERIPHERALS
CPU1.DMA
CPU1.CLA1
CPU1
CPU2
CPU2.CLA1
CPU2.DMA
(BY BUS ACCESS TYPE)
Peripherals that can be assigned to CPU1 or CPU2 and have common selectable Secondary Masters
Peripheral Frame 1:
•
•
•
•
•
•
ePWM
SDFM
eCAP(1)
eQEP(1)
CMPSS(1)
DAC(1)
Y
Y
Y
Y
Y
Y
Peripheral Frame 1:
HRPWM
Peripheral Frame 2:
Y
Y
Y
Y
Y
Y
Y
Y
Y
•
•
•
SPI
Y
Y
Y
McBSP
Peripheral Frame 2:
•
uPP Configuration(1)
Peripherals that can be assigned to CPU1 or CPU2 subsystems
SCI
I2C
Y
Y
Y
Y
Y
Y
Y
Y
CAN
ADC Configuration
EMIF1
Y
Y
Y
Y
Y
Y
Peripherals and Device Configuration Registers only on CPU1 subsystem
EMIF2
USB
Y
Y
Y
Device Capability, Peripheral Reset, Peripheral CPU
Select
Y
GPIO Pin Mapping and Configuration
Analog System Control
uPP Message RAMs
Y
Y
Y
Y
Y
Reset Configuration
Accessible by only one CPU at a time with Semaphore
Clock and PLL Configuration
Y
Y
Peripherals and Registers with Unique Copies of Registers for each CPU and CLA Master(2)
System Configuration
(WD, NMIWD, LPM, Peripheral Clock Gating)
Y
Y
Flash Configuration(3)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CPU Timers
DMA and CLA Trigger Source Select
GPIO Data(4)
Y
Y
Y
Y
ADC Results
Y
Y
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) Each CPUx and CPUx.CLA1 can only access its own copy of these registers.
(3) At any given time, only one CPU can perform program or erase operations on the Flash.
(4) The GPIO Data Registers are unique for each CPUx and CPUx.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual for more details.
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5.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal
processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and
tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and
unpacking, and bit manipulation. The modified Harvard architecture of the CPU enables instruction and
data fetches to be performed in parallel. The CPU can read instructions and data while it writes data
simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this
over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction
Set Reference Guide.
5.6.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU
by adding registers and instructions to support IEEE single-precision floating point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point
unit registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be
used in high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
5.6.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in 表 5-
10.
表 5-10. TMU Supported Instructions
INSTRUCTIONS
MPY2PIF32 RaH,RbH
C EQUIVALENT OPERATION
PIPELINE CYCLES
a = b * 2pi
a = b / 2pi
a = b / c
2/3
2/3
5
DIV2PIF32 RaH,RbH
DIVF32 RaH,RbH,RcH
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
COSPUF32 RaH,RbH
ATANPUF32 RaH,RbH
QUADF32 RaH,RbH,RcH,RdH
a = sin(b * 2pi)
4
a = cos(b * 2pi)
4
a = atan(b) / 2pi
4
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU
instructions use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed
explanation of the workings of the FPU can be found in the TMS320C28x Extended Instruction Sets
Technical Reference Manual.
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5.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The
VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the
performance of FFTs and communications-based algorithms. The C28x+VCU-II supports the following
algorithm types:
•
Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode
algorithm consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly),
and a traceback operation. 表 5-11 shows a summary of the VCU performance for each of these
operations.
表 5-11. Viterbi Decode Performance
VITERBI OPERATION
Branch Metric Calculation (code rate = 1/2)
Branch Metric Calculation (code rate = 1/3)
Viterbi Butterfly (add-compare-select)
Traceback per Stage
VCU CYCLES
1
2p
2(1)
3(2)
(1) C28x CPU takes 15 cycles per butterfly.
(2) C28x CPU takes 22 cycles per stage.
•
•
Cyclic Redundancy Check
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity
over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit,
16-bit, 24-bit, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10
bytes in 10 cycles. A CRC result register contains the current CRC, which is updated whenever a CRC
instruction is executed.
Complex Math
Complex math is used in many applications, a few of which are:
–
Fast Fourier Transform (FFT)
The complex FFT is used in spread spectrum communications, as well as in many signal
processing algorithms.
–
Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The
C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single
cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data
to memory in a single cycle.
表 5-12 shows a summary of the VCU operations enabled by the VCU.
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表 5-12. Complex Math Performance
COMPLEX MATH OPERATION
Add or Subtract
VCU CYCLES
NOTES
1
1
32 +/- 32 = 32-bit (Useful for filters)
16 +/- 32 = 15-bit (Useful for FFT)
16 x 16 = 32-bit
Add or Subtract
Multiply
2p
Multiply and Accumulate (MAC)
RPT MAC
2p
32 + 32 = 32-bit, 16 x 16 = 32-bit
2p+N
Repeat MAC. Single cycle after the first operation.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
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5.7 Control Law Accelerator
The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch
mechanism, and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or
a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a
time to completion. When a task completes, the main CPU is notified by an interrupt to the PIE and the
CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC
Result registers, ePWM, eCAP, eQEP, Comparator and DAC registers. Dedicated message RAMs provide
a method to pass additional data between the main CPU and the CLA.
图 5-2 shows the CLA block diagram.
CLA Control
Register Set
CLA_INT1
MIFR(16)
From
Shared
Peripherals
MPERINT1
to
MPERINT8
to
CLA_INT8
MIOVF(16)
MICLR(16)
MICLROVF(16)
MIFRC(16)
MIER(16)
C28x
CPU
INT11
INT12
PIE
MIRUN(16)
LVF
LUF
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
SYSCLK
CLA Clock Enable
SYSRSn
CPU Read/Write Data Bus
CLA Program
Memory (LSx)
CLA Program Bus
MCTL(16)
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
CLA Data
Memory (LSx)
CLA Execution
Register Set
MPC(16)
CLA Message
RAMs
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
Shared
Peripherals
MEALLOW
MAR0(16)
MAR1(16)
CPU Read Data Bus
图 5-2. CLA Block Diagram
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5.8 Direct Memory Access
Each CPU has its own 6-channel DMA module. The DMA module provides a hardware method of
transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing
up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally
rearrange the data as it is transferred as well as “ping-pong” data between buffers. These features are
useful for structuring data into blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start
a DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the
interrupt trigger source, there is no mechanism within the module itself to start memory transfers
periodically. The interrupt trigger source for each of the six DMA channels can be configured separately
and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer
has either started or completed. Five of the six channels are exactly the same, while Channel 1 has the
ability to be configured at a higher priority than the others.
DMA features include:
•
•
Six channels with independent PIE interrupts
Peripheral interrupt trigger sources
–
–
–
–
–
–
–
–
ADC interrupts and EVT signals
Multichannel buffered serial port transmit and receive
External interrupts
CPU timers
EPWMxSOC signals
SPIx transmit and receive
SDFM
Software trigger
•
Data sources and destinations:
–
–
–
–
–
–
–
GSx RAM
CPU message RAM (IPC RAM)
ADC result registers
ePWMx
SPI
McBSP
EMIF
•
•
Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
Throughput: four cycles/word (without arbitration)
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图 5-3 shows a device-level block diagram of the DMA.
CPU1
XINT
(5)
CPU1
TIMER
(3)
ADC
WRAPPER
(4)
ADC
RESULTS
(4)
Global Shared
16x 4Kx16
GS0-15 RAMs
MSG RAM
1Kx16
CPU2 to CPU1
MSG RAM
1Kx16
CPU1 to CPU2
C28x CPU1 Bus
CPU1.DMA Bus
DMA Trigger
Source Selection
TINT (0-2)
XINT (1-5)
ADC INT (A-D) (1-4), EVT (A-D)
SDxFLTy (x = 1 to 2, y = 1 to 4)
SOCA (1-12), SOCB (1-12)
MXEVT (A-B), MREVT (A-B)
SPITX (A-C), SPIRX (A-C)
DMA
CPU1
C28x
CPU1
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
PIE
DMA Trigger
Source Selection
DMA
CPU2
C28x
CPU2
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
XINT (1-5)
TINT (0-2)
PIE
CPU2.DMA Bus
C28x CPU2 Bus
DMA Trigger Source
CPU and DMA Data Path
CPU2
XINT
(5)
CPU2
TIMER
(3)
SDFM
(8)
EPWM
(12)
McBSP
(2)
SPI
(3)
EMIF1
图 5-3. DMA Block Diagram
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5.9 Interprocessor Communication Module
The IPC module supports several methods of interprocessor communication:
•
Thirty-two IPC flags per CPU, which can be used to signal events or indicate status through software
polling. Four flags per CPU can generate interrupts.
•
Shared data registers, which can be used to send commands or other small pieces of information
between CPUs. Although the register names were chosen to support a command/response system,
they can be used for any purpose as defined in software.
•
•
•
Boot mode and status registers, which allow CPU1 to control the CPU2 boot process.
A general-purpose free-running 64-bit counter.
Two shared message RAMs, which can be used to transfer bulk data. Each RAM can be read by both
CPUs. CPU1 can write to one RAM and CPU2 can write to the other.
图 5-4 shows the IPC architecture.
SET31
CLR31
ACK31
FLG31
R=0/W=1
R=0/W=1
IPCSET[31:0]
IPCCLR[31:0]
SET0
CLR0
ACK0
IPCACK[31:0]
R=0/W=1
FLG0
Gen Int Pulse
(on FLG 0->1)
CPU2.
ePIE
C1TOC2IPCINT1/2/3/4
IPCSTS[31:0]
IPCFLG[31:0]
R
R
IPCSENDCOM[31:0]
IPCSENDADDR[31:0]
IPCSENDDATA[31:0]
IPCREMOTEREPLY[31:0]
IPCRECVCOM[31:0]
IPCRECVADDR[31:0]
IPCRECVDATA[31:0]
IPCLOCALREPLY[31:0]
R/W
R/W
R/W
R
C1TOC2IPCCOM[31:0]
C1TOC2IPCADDR[31:0]
C1TOC2IPCDATAW[31:0]
C1TOC2IPCDATAR[31:0]
R
R
R
R/W
R/W
R
IPCBOOTMODE[31:0]
IPCBOOTSTS[31:0]
R
R/W
CPU2.EmulationHalt
CPU1.EmulationHalt
R
64-bit Free Run Counter
PLLSYSCLK
R
CPU2
CPU1
IPCCOUNTERH/L[31:0]
SET31
ACK31
CLR31
FLG31
IPCSET[31:0]
IPCCLR[31:0]
R=0/W=1
R=0/W=1
SET0
CLR0
R=0/W=1
IPCACK[31:0]
ACK0
FLG0
Gen Int Pulse
(on FLG 0->1)
CPU1.
ePIE
C2TOC1IPCINT1/2/3/4
IPCSTS[31:0]
R
IPCFLG[31:0]
R
IPCRECVCOM[31:0]
IPCRECVADDR[31:0]
IPCRECVDATA[31:0]
IPCLOCALREPLY[31:0]
C2TOC1IPCCOM[31:0]
C2TOC1IPCADDR[31:0]
C2TOC1IPCDATAW[31:0]
C2TOC1IPCDATAR[31:0]
IPCSENDCOM[31:0]
IPCSENDADDR[31:0]
IPCSENDDATA[31:0]
IPCREMOTEREPLY[31:0]
R
R
R/W
R/W
R/W
R
R
R/W
图 5-4. IPC Architecture
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5.10 Boot ROM and Peripheral Booting
The device boot ROM (on both the CPUs) contains bootloading software. The CPU1 boot ROM does the
system initialization before bringing CPU2 out of reset. The device boot ROM is executed each time the
device comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to
boot the device through one of the bootable peripherals by configuring the boot mode GPIO pins.
The CPU1 boot ROM, being master, owns the boot mode GPIO and boot configurations. The CPU2 boot
ROM either boots to flash (if configured to do so through user configurable DCSM OTP) or enters a WAIT
BOOT mode if no OTP is programmed. In WAIT BOOT mode, the CPU1 application instructs the CPU2
boot ROM on how to boot further using boot mode IPC commands supported by CPU2 boot ROM.
表 5-13 shows the possible boot modes supported on the device. The default boot mode pins are GPIO72
(boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for boot
mode pins if they use a peripheral on these pins as well, so the pullups can be overdriven. On this device,
customers can change the factory default boot mode pins by programming user configurable DCSM OTP
locations. This is recommended only for cases in which the factory default boot mode pins do not fit into
the customer design. More details on the locations to be programmed is available in the TMS320F2837xD
Dual-Core Delfino Microcontrollers Technical Reference Manual.
表 5-13. Device Boot Mode
GPIO72
(BOOT
MODE
PIN 1)
GPIO84
(BOOT
MODE
PIN 0)
MODE
NO.
CPU1 BOOT MODE
CPU2 BOOT MODE
TRST
0
1
Parallel I/O
SCI Mode
Boot from Master
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Boot from Master
Boot from master
Boot from Master
Boot from Master
2
Wait Boot Mode
3
Get Mode
4-7
EMU Boot Mode (Emulator Connected)
注
The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get
mode will result in repeated watchdog resets, which may prevent proper JTAG connection
and device initialization. Use Wait mode or another boot mode for unprogrammed devices.
CAUTION
Some reset sources are internally driven by the device. The user must ensure
the pins used for boot mode are not actively driven by other devices in the
system for these cases. The boot configuration has a provision for changing the
boot pins in OTP. For more details, see the TMS320F2837xD Dual-Core
Delfino Microcontrollers Technical Reference Manual.
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5.10.1 EMU Boot or Emulation Boot
The CPU enters this boot when it detects that TRST is HIGH (in other words, when an emulator/debugger
is connected). In this mode, the user can program the EMUBOOTCTRL register (at location 0xD00) to
instruct the device on how to boot. If the contents of the EMUBOOTCTRL locations are invalid, then the
device would default into WAIT Boot mode. The emulation boot allows users to verify the device boot
before programming the boot mode into OTP.
5.10.2 WAIT Boot Mode
The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a
debugger on a secure device or if users do not want the device to execute an application in flash yet.
5.10.3 Get Mode
The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-
OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this
device is divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a
valid OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the
Z1-OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-
OTPBOOTCTRL is invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed,
then the device defaults to factory default operation, which is to use factory default boot mode pins to boot
to flash if the boot mode pins are set to GET MODE. Users can choose the device through which to
boot—SPI, I2C, CAN, and USB—by programming proper values into the user configurable DCSM OTP.
More details on this can be found in the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical
Reference Manual.
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5.10.4 Peripheral Pins Used by Bootloaders
表 5-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs
for each mode, as shown in 表 5-14.
表 5-14. GPIO Pins Used by Each Peripheral Bootloader
BOOTLOADER
GPIO PINS
SCITXDA: GPIO84
SCIRXDA: GPIO85
NOTES
SCIA Boot I/O option 1 (default SCI option
when chosen through Boot Mode GPIOs)
SCI-Boot0
SCI-Boot1
SCITXDA: GPIO28
SCIRXDA: GPIO29
SCIA Boot option 2 – with alternate I/Os.
D0 – GPIO65
D1 – GPIO64
D2 – GPIO58
D3 – GPIO59
D4 – GPIO60
D5 – GPIO61
Parallel Boot
D6 – GPIO62
D7 – GPIO63
HOST_CTRL – GPIO70
DSP_CTRL – GPIO69
CANRXA: GPIO70
CANTXA: GPIO71
CAN-Boot0
CAN-Boot1
I2C-Boot0
I2C-Boot1
CAN-A Boot – I/O option 1
CAN-A Boot – I/O option 2
I2CA Boot – I/O option 1
I2CA Boot – I/O option 2
CANRXA: GPIO62
CANTXA: GPIO63
SDAA: GPIO91
SCLA: GPIO92
SDAA: GPIO32
SCLA: GPIO33
SPISIMOA - GPIO58
SPISOMIA - GPIO59
SPICLKA - GPIO60
SPISTEA - GPIO61
SPI-Boot0
SPI-Boot1
SPIA Boot – I/O option 1
SPIA Boot – I/O option 2
SPISIMOA – GPIO16
SPISOMIA – GPIO17
SPICLKA – GPIO18
SPISTEA – GPIO19
The USB Bootloader will switch the clock
source to the external crystal oscillator (X1
and X2 pins). A 20-MHz crystal should be
present on the board if this boot mode is
selected.
USB0DM - GPIO42
USB0DP - GPIO43
USB Boot
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5.11 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure”
means access to secure memories and resources is blocked. The term “unsecure” means access is
allowed; for example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP
memory and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for
each zone is stored in an OTP memory location based on a zone-specific link pointer. The link pointer
value can be changed to program a different set of security settings (including passwords) in OTP.
5.12 Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register that generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and is connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of
the CPU. If TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
•
SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
AUXPLLCLK
5.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
The NMIWD module is used to handle system-level errors. There is an NMIWD module for each CPU.
The conditions monitored are:
•
•
•
•
•
Missing system clock due to oscillator failure
Uncorrectable ECC error on CPU access to flash memory
Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
Vector fetch error on the other CPU
CPU1 only: Watchdog or NMI watchdog reset on CPU2
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after
a programmable time interval. The default time is 65536 SYSCLK cycles.
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5.14 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional
lower limit on the time between software resets of the counter. This windowed countdown is disabled by
default, so the watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a
selectable frequency divider.
图 5-5 shows the various functional blocks within the watchdog module.
WDCR(WDPS(2:0))
WDCR(WDDIS)
WDCNTR(7:0)
1 WDCLK
delay
Watchdog
Prescaler
8-bit
Watchdog
Counter
OSCCLK
/512
WDCLK
Overflow
SYSRSn
Clear
Count
WDWCR(MIN(7:0))
WDKEY(7:0)
Watchdog
Window
Detector
In Window
Watchdog
Key Detector
55 + AA
Good Key
Bad Key
Out of Window
Generate
512-OSCCLK
Output Pulse
WDRSn
WDINTn
Watchdog Time-out
SCSR(WDENINT)
图 5-5. Windowed Watchdog
5.15 Configurable Logic Block (CLB)
TI uses the CLB to offer additional interfacing and control features for select C2000 devices. Functions
that would otherwise be accomplished using external logic devices are now provided by on-chip TI
solutions. For example, absolute encoder master protocol interfaces such as EnDat and BiSS are now
provided as Position Manager solutions. Configuration files, application programmer’s interface (API), and
use examples for such solutions are provided with the C2000 controlSUITE software package. In some
solutions, the TI-configured CLB is used with other on-chip resources, such as the SPI port or the C28x
CPU, to perform more complex functionality. In some cases, external communications transceivers may
need to be added.
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6 Applications, Implementation, and Layout
注
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download designs at TIDesigns.
Industrial Servo Drive and AC Inverter Drive Reference Design
The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly
connecting to a three-phase ACI or PMSM motor. Many drive topologies can be created from the
combined control, power, and communications technologies included on this single platform. This platform
includes multiple position sensor interfaces, diverse current sensing techniques, hot-side partitioning
options, and expansion for safety and industrial Ethernet.
Isolated Current Shunt and Voltage Measurement Reference Design for Motor Drives
This evaluation kit and reference design implement the AMC130x reinforced isolated delta-sigma
modulators along with integrated Sinc filters in the C2000 TMS320F28377D Delfino microcontroller. The
design provides an ability to evaluate the performance of these measurements: three motor currents, three
inverter voltages, and the DC Link voltage. Provided in the kit is firmware to configure the Sinc filters, set
the PLL frequency, and receive data from Sinc filters. A versatile run-time GUI is also provided to help the
user validate the AMC130x performance and supports configuration changes to Sinc filter parameters in
the Delfino controller.
Isolated, Shunt-Based Current Sensing Reference Design
This Verified TI Design implements an isolated current sensing data acqusition solution based on the
AMC1304M25 isolated delta-sigma (ΔΣ) modulator and a TMS320F28377D microcontroller. This circuit
was designed for shunt-based current measurement applications, which require excellent galvanic
isolation and accuracy, such as industrial motor drives, photovoltaic inverters, and energy metering. It is
capable of measuring load currents from –10 A to +10 A with better than 0.3% uncalibrated accuracy, and
it also provides dual functionality of a high-resolution channel and an additional overcurrent or short-circuit
detection channel. The design’s functionality and performance were verified against the circuit design
goals by fabricating three PCBs and measuring results for dc and ac input signals.
Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for differential ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative
measurement circuit with external differential SAR ADCs as well as circuits for high-speed overcurrent and
earth fault detection. Proper differential signal conditioning improves noise immunity on critical current
measurements in motor drives. This reference design can help increase the effective resolution of the
analog-to-digital conversion, improving motor drive efficiency.
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7 器件和文档支持
TI 提供大量的开发工具。下面列出了用于评估器件性能、生成代码和开发解决方案的工具和软件。
7.1 器件和开发支持工具命名规则
为了标明产品开发周期的阶段，TI 为所有 TMS320™MCU 器件和支持工具的部件号指定前缀。每个
TMS320 MCU 商用系列成员都具有以下三个前缀中的一个：TMX、TMP TMS（例如
TMS320F28379D）。德州仪器 (TI) 建议为其支持的工具使用三个可用前缀指示符中的两个：TMDX
或
和
TMDS。这些前缀代表了产品从工程原型机（其中 TMX 针对器件，而 TMDX 针对工具）直到完全合格的生
产器件和工具（其中 TMS 针对器件，而 TMDS 针对工具）的产品开发进化阶段。
器件开发进化流程：
TMX
TMP
TMS
试验器件不一定代表最终器件的电气规范标准。
最终的芯片模型符合器件的电气规范标准，但是未经完整的质量和可靠性验证。
完全合格的生产器件
支持工具开发发展流程：
TMDX 还未经完整的德州仪器 (TI) 内部质量测试的开发支持工具
TMDS 完全合格的开发支持产品
TMX 和 TMP 器件和 TMDX 开发支持工具出货时带有如下的免责声明：
“开发产品用于内部评估用途。”
TMS 器件和 TMDS 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准
保修证书适用。
预测显示原型器件（TMX 或者 TMP）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未
定义，德州仪器建议不要将这些器件用于任何生产系统。只有合格的产品器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀包括封装类型（例如 PTP）和温度范围
（如 T）。图 7-1 提供了解读任一系列产品成员完整器件名称的图例。
要获取器件部件号以及更多订购信息，请访问 TI 网站 (www.ti.com) 或者联系您的 TI 销售代表。
有关裸片器件命名规则标记 的 详细说明，请参阅《TMS320F2837xD 双核 Delfino™ MCUs 器件勘误
表》。
TMS 320
F
28377D PTP
EP
PREFIX
TEMPERATURE RANGE
EP
experimental device
prototype device
qualified device
TMX =
TMP =
TMS =
−55°C to 125°C (TJ)
=
DEVICE FAMILY
320 = TMS320 MCU Family
PACKAGE TYPE
337-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (HLQFP)
TECHNOLOGY
F = Flash
DEVICE
28377D
图 7-1. 器件命名规则
7.2 工具和软件
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TI 提供大量的开发工具。下面列出了部分用于评估器件性能、生成代码和开发解决方案的工具和软件。要查
看 C2000™ 实时控制 MCU 的所有可用工具和软件，请访问 C2000™ MCU 工具和软件页面。
开发工具
用于 C2000 实时控制开发套件的 F28379D controlCARD
德州仪器 (TI) 提供的 Delfino F28379D controlCARD 支持位置管理器，是用于初期软件开发以及短期内构
建系统原型、试验台和许多其他需要轻松获得高性能控制器的项目的理想产品。所有 C2000 controlCARD
均是使用 HSEC180 或 DIMM100 外形尺寸来提供薄型单板控制器解决方案的完整板级模块。主机系统只需
为 controlCARD 提供单个 5V 电源轨，即可使其运行全部功能。
F28379D Delfino 实验套件
C2000™ MCU 实验套件提供了一个使用德州仪器 (TI) C2000 32 位微控制器系列进行实时、闭环控制开发
的强大硬件原型设计平台。此平台作为一种非常出色的工具，可定制和验证众多常见电力电子 应用的解决方
案，这些应用包括电机控制、数字电源、光伏逆变器、数字 LED 照明、精密传感等等。
软件工具
用于 C2000 MCU 的 C2000Ware
用于 C2000 微控制器的 C2000Ware 是一系列联系密切的开发软件和文档，旨在最大限度地缩短软件开发
时间。从特定于器件的驱动程序和库到器件外设示例，C2000Ware 能够为开始进行开发和评估提供坚实的
基础。相较于 controlSUITE™，目前推荐使用 C2000Ware 作为内容交付工具。
controlSUITE™ 软件套件
用于 C2000 微控制器的 controlSUITE™ 是一系列联系密切的软件基础设施和软件工具，旨在最大限度地缩
短软件开发时间。
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用于 C2000 微控制器的 Code Composer Studio™ (CCS) 集成开发环境 (IDE)
Code Composer Studio 是支持 TI 的微控制器和嵌入式处理器产品系列的集成开发环境 (IDE)。Code
Composer Studio 包含一整套用于开发和调试嵌入式应用 的工具。它包含了优化的 C/C++ 编译器、源代码
编辑器、项目构建环境、调试器、描述器以及其他多种 功能。直观的 IDE 提供了单一用户界面，可帮助用
户完成应用开发流程的每个步骤。熟悉的工具和界面使用户能够比以前更快地入手。Code
Composer
Studio 将 Eclipse 软件框架的优点和 TI 先进的嵌入式调试功能相结合，为嵌入式开发人员提供了一种功能
丰富的优异开发环境。
引脚多路复用工具
引脚多路复用实用程序是一款软件工具，可提供图形用户界面，用于配置引脚多路复用设置、解决冲突并指
定 TI MPU 的 I/O 电池特性。
F021 闪存应用编程接口 (API)
F021 闪存应用编程接口 (API) 提供的软件函数库可用于对 F021 片上闪存执行编程、擦除和验证操作。
培训
为了帮助设计工程师充分利用 C2000 微控制器 特性 和性能，TI 开发了各种培训资源。通过利用在线培训资
料和可下载的实际操作技术讲座，可方便地获得 C2000 微控制器系列的全方位实际知识。这些培训资源旨
在简化学习过程，同时缩短开发时间并加快产品上市速度。有关各种培训资源的更多信息，请访问 C2000™
实时控制 MCU 的支持和培训站点。
可从以下站点找到具体的 F2837xD/F2837xS/F2807x 实际操作培训资源：
•
•
C2000 多日技术讲座
C2000 一日技术讲座
7.3 器件命名规则
为了指出产品开发周期所处的阶段，TI 为所有微处理器 (MPU) 和支持工具的产品型号分配了前缀。每个器
件都具有以下三个前缀中的一个：X、P 或无（无前缀）（例如，您的器件）。德州仪器 (TI) 建议为其支持
的工具使用三个可用前缀指示符中的两个：TMDX 和 TMDS。这些前缀代表了产品开发的发展阶段，即从工
程原型 (TMDX) 直到完全合格的生产器件和工具 (TMDS)。
器件开发进化流程：
X
试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。
原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。
完全合格的芯片模型的生产版本。
P
无
支持工具开发进化流程：
TMDX
TMDS
还未经德州仪器 (TI) 完整内部质量测试的开发支持产品.
完全合格的开发支持产品。
X 和 P 器件和 TMDX 开发支持工具在供货时附带如下免责条款：
为了指出产品开发周期的阶段，TI 为所有数字信号处理 (DSP) 器件和支持工具的部件号指定了前缀。每一
个 DSP 商用系列成员产品具有以下三个前缀中的一个：TMX、TMP、或者 TMS（例如，您的器件）。德州
仪器 (TI) 建议为其支持的工具使用三个可用前缀指示符中的两个：TMDX 和 TMDS。这些前缀代表了产品
开发的发展阶段，即从工程原型（TMX 和 TMDX）直到完全合格的生产器件和工具（TMS 和 TMDS）。
器件开发进化流程：
TMX
TMP
TMS
试验器件不一定代表最终器件的电气规范标准并且不可使用生产组装流程。
原型器件不一定是最终芯片模型并且不一定符合最终电气标准规范。
完全合格的芯片模型的生产版本。
支持工具开发进化流程：
TMDX
TMDS
还未经德州仪器 (TI) 完整内部质量测试的开发支持产品.
完全合格的开发支持产品。
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TMX 和 TMP 器件和 TMDX 开发支持工具在供货时附带如下免责条款：
“开发的产品用于内部评估用途。”
生产器件和 TMDS 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准
保修证书适用。
预测显示原型器件（X 或者 P）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定义，
德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的产品器件将被使用。
TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如，您的封装），温度
范围（例如，“空白”是默认的商业级温度范围）以及以 MHz 为单位的器件速度范围（例如，您的器件的速度
范围）。图 7-2 提供了解读任一您的器件器件完整器件名称的图例。
有关采用您的封装
封装类型的您的器件
器件的可订购部件号，请参阅本文档的封装选项附录、访问
ti.com.cn 或联系您的 TI 销售代表。
有关裸片器件命名规则标记 的 其他说明，请参阅《器件勘误表》。
图 7-2. 器件命名规则
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7.4 文档支持
如需接收文档更新通知，请访问 ti.com.cn 上的器件产品文件夹。In the upper right corner, click on Alert me
to register and receive a weekly digest of any product information that has changed. For change details,
review the revision history included in any revised document.
下面列出了介绍处理器、相关外设以及其他配套技术资料的最新文档。
勘误表
《TMS320F2837xD 双核 Delfino™ MCU 芯片勘误表》 介绍了器件的已知问题并提供了权变措施。
技术参考手册
《TMS320F2837xD 双核 Delfino 微控制器技术参考手册》 介绍了 2837xD 微控制器的每个外设和子系统的
集成、环境、功能 说明和编程模型。
CPU 用户指南
《TMS320C28x CPU 和指令集参考指南》 介绍了 TMS320C28x 定点数字信号处理器 (DSP) 的中央处理器
(CPU) 和汇编语言指令。此参考指南还介绍了上述 DSP 所 提供 的仿真特性。
《TMS320C28x 扩展指令集技术参考手册》 介绍了 TMU、VCU-II 和 FPU 加速器的架构、流水线和指令
集。
外设指南
《C2000 实时控制外设参考指南》 介绍了 28x DSP 的外设参考指南。
工具指南
《TMS320C28x 汇编语言工具 v17.6.0.STS 用户指南》 介绍了用于 TMS320C28x 器件的汇编语言工具
（用于开发汇编语言代码的汇编器和其他工具）、汇编器指令、宏、通用目标文件格式和符号调试指令。
《TMS320C28x 优化 C/C++ 编译器 v17.6.0.STS 用户指南》 介绍了 TMS320C28x C/C++ 编译器。此编译
器接受 ANSI 标准 C/C++ 源代码，并为 TMS320C28x 器件生成 TMS320 DSP 汇编语言源代码。
《TMS320C28x 指令集仿真器技术概述》 介绍了用于 TMS320C2000 IDE 的 Code Composer Studio 内提
供的仿真器，该仿真器可以对 C28x 内核的指令集进行仿真。
应用报告
《半导体封装方法》 介绍了准备向最终用户运输半导体器件时所用的封装方法。
《计算嵌入式处理器的有效使用寿命》 介绍了如何计算 TI 嵌入式处理器 (EP) 在电子系统中运行时的有效使
用寿命。本文档的目标读者为希望确定 TI EP 的可靠性是否符合终端系统可靠性要求的总工程师。
《TMS320C28x 数字信号控制器使用入门》 介绍了如何开始使用 TMS320C28x DSP 软件和硬件开发来辅
助实现初始设计和调试目的。
7.5 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区为了促进工程师之间的合作，我们创建了 TI 工程师对工程师 (E2E) 社区。在 e2e.ti.com
中，您可以提问、分享知识、拓展思路并与同行工程师一道帮助解决问题。
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.6 商标
PowerPAD, Delfino, TMS320C2000, C2000, controlSUITE, Code Composer Studio, TMS320, 用于 C2000
微控制器的 Code Composer Studio, E2E are trademarks of Texas Instruments.
Bosch is a registered trademark of Robert Bosch GmbH Corporation.
All other trademarks are the property of their respective owners.
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7.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.8 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
7.9 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
198
器件和文档支持
版权 © 2017, Texas Instruments Incorporated
提交文档反馈意见
产品主页链接: TMS320F28377D-EP
TMS320F28377D-EP
www.ti.com.cn
ZHCSHE0 –DECEMBER 2017
8 机械封装和可订购信息
8.1 Via Channel
您的封装已经采用“过孔通道”技术进行了特殊设计。这使得 PCB 设计中能够采用 0.65mm 间距封装，实现
比正常尺寸更大的 PCB 过孔和布线，从而减小 PCB 信号层数，并大幅降低 PCB 成本。由于 Via Channel
BGA 技术提升了分层效率，因此该器件允许仅在两个信号层（共四层）中进行 PCB 布线。
利用 [所用封装] 封装中实施的 Via Channel 技术可构建基于 [所用器件] 的产品，该产品采用 4 层 PCB 设
计，但这可能达不到系统性能目标要求。因此，产品设计期间必须对采用 4 层 PCB 设计的系统的性能进行
评估。
8.2 封装信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
对于具有散热焊盘的封装，“机械数据”图显示了通用散热焊盘（无尺寸）。有关适用于该器件的实际散热焊
盘尺寸，请参阅“散热焊盘机械数据”图。
版权 © 2017, Texas Instruments Incorporated
机械封装和可订购信息
199
提交文档反馈意见
产品主页链接: TMS320F28377D-EP
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
GWT
PTP
Qty
90
40
90
40
(1)
(2)
(3)
(4/5)
(6)
TMS320F28377DGWTEP
TMS320F28377DPTPEP
V62/18601-01XF
ACTIVE
NFBGA
HLQFP
NFBGA
HLQFP
337
176
337
176
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
Level-3-260C-168 HR
Level-3-220C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
TMS320
F28377DGWTEP
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
ACTIVE
RoHS & Green
NIPDAU
SNPB
TMS320
F28377DPTPEP
GWT
PTP
Non-RoHS
& Green
TMS320
F28377DGWTEP
V62/18601-01YE
RoHS & Green
NIPDAU
TMS320
F28377DPTPEP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F28377D-EP :
Catalog : TMS320F28377D
•
Automotive : TMS320F28377D-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
TMS320F28377DGWTE
P
GWT
NFBGA
337
90
6 X 15
150
315 135.9 7620
20
17.5 15.45
TMS320F28377DPTPEP
V62/18601-01XF
PTP
GWT
PTP
HLQFP
NFBGA
HLQFP
176
337
176
40
90
40
4x10
6 X 15
4x10
150
150
150
315 135.9 7620 20.7
315 135.9 7620 20
315 135.9 7620 20.7
30.4
17.5 15.45
30.4 20.7
20.7
V62/18601-01YE
Pack Materials-Page 1
GENERIC PACKAGE VIEW
PTP 176
24 x 24, 0.5 mm pitch
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226435/A
www.ti.com
PACKAGE OUTLINE
PTP0176F
PowerPADTM HLQFP - 1.6 mm max height
SCALE 0.550
PLASTIC QUAD FLATPACK
24.2
23.8
NOTE 3
B
PIN 1 ID
133
176
1
132
24.2
23.8
26.2
TYP
25.8
NOTE 3
44
89
45
88
0.27
0.17
176X
C
A
172X 0.5
0.08
C A B
4X 21.5
SEATING PLANE
1.6 MAX
SEE DETAIL A
(0.13)
TYP
45
88
89
44
0.25
GAGE PLANE
(1.4)
4X 0.78 MAX
NOTE 4
4X
0.54 MAX
NOTE 4
0.15
0.05
0.08 C
7.33
6.78
0 -7
177
0.75
0.45
DETAIL A
TYPICAL
4X
0.2 MAX
NOTE 4
EXPOSED
THERMAL PAD
1
132
133
176
8.07
7.53
4223382/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features my not present.
5. Reference JEDEC registration MS-026.
www.ti.com
DETAIL
SCALE: 12
A
EXAMPLE BOARD LAYOUT
PTP0176F
PowerPADTM HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
(8.07)
SYMM
SOLDER MASK
DEFINED PAD
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
177
SYMM
(7.33)
(1.5 TYP)
(
(25.5)
22)
NOTE 10
(R0.05) TYP
(
0.2) TYP
VIA
89
44
SEE DETAILS
45
88
METAL COVERED
BY SOLDER MASK
(1.5 TYP)
(25.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223382/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PTP0176F
PowerPADTM HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
(8.07)
BASED ON
0.125 THICK STENCIL
SYMM
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
(25.5)
(7.33)
BASED ON
SYMM
177
0.125 THICK
STENCIL
(R0.05) TYP
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
44
89
METAL COVERED
BY SOLDER MASK
45
88
(25.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:4X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
9.02 X 8.2
8.07 X 7.33 (SHOWN)
7.37 X 6.69
0.125
0.150
0.175
6.82 X 6.2
4223382/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
GWT0337A
NFBGA - 1.4 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC BALL GRID ARRAY
16.1
15.9
A
B
BALL A1
CORNER
16.1
15.9
0.95
0.84
0.23
0.15
C
SEATING PLANE
0.12 C
1.40
1.19
14.4 TYP
SYMM
0.45
0.35
(0.8)
W
V
U
T
(0.8)
R
P
N
M
L
SYMM
K
14.4 TYP
J
H
G
F
E
D
C
0.55
337X
0.45
0.15
0.05
C A B
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
0.8 TYP
0.8 TYP
4229175/A 11/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
GWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
(0.8) TYP
9
10
11
12 13
14
15
16
17
18
19
7
8
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 7X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4229175/A 11/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
GWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
(0.8) TYP
9
10
11
12 13
14
15
16
17
18
19
7
8
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 7X
4229175/A 11/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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