TMS320F28377SPZPQ [TI]
具有 400MIPS、1xCPU、1xCLA、FPU、TMU、1024KB 闪存、EMIF、16 位 ADC 的汽车类 C2000™ 32 位 MCU | PZP | 100 | -40 to 125;
| 型号： | TMS320F28377SPZPQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 400MIPS、1xCPU、1xCLA、FPU、TMU、1024KB 闪存、EMIF、16 位 ADC 的汽车类 C2000™ 32 位 MCU | PZP | 100 | -40 to 125 闪存 |
| 文件： | 总225页 (文件大小：5419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TMS320F2837xS Microcontrollers
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Four Serial Communications Interfaces (SCI/
UART) (pin-bootable)
1 Features
•
TMS320C28x 32-bit CPU
– 200 MHz
– IEEE 754 single-precision Floating-Point Unit
(FPU)
– Two I2C interfaces (pin-bootable)
Analog subsystem
•
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
Programmable Control Law Accelerator (CLA)
– 200 MHz
– IEEE 754 single-precision floating-point
instructions
– Executes code independently of main CPU
On-chip memory
– 512KB (256KW) or 1MB (512KW) of flash
(ECC-protected)
– Up to four Analog-to-Digital Converters (ADCs)
•
16-bit mode
•
•
– 1.1 MSPS each (up to 4.4-MSPS system
throughput)
– Differential inputs
– Up to 12 external channels
12-bit mode
•
– 3.5 MSPS each (up to 14-MSPS system
throughput)
– Single-ended inputs
– 132KB (66KW) or 164KB (82KW) of RAM
(ECC-protected or parity-protected)
– Dual-zone security supporting third-party
development
– Unique identification number
Clock and system control
– Up to 24 external channels
Single Sample-and-Hold (S/H) on each ADC
Hardware-integrated post-processing of
ADC conversions
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare,
with interrupt capability
•
•
•
– Two internal zero-pin 10-MHz oscillators
– On-chip crystal oscillator
– Windowed watchdog timer module
– Missing clock detection circuitry
1.2-V core, 3.3-V I/O design
System peripherals
– Two External Memory Interfaces (EMIFs) with
ASRAM and SDRAM support
– Trigger-to-sample delay capture
– Eight windowed comparators with 12-bit Digital-
to-Analog Converter (DAC) references
– Three 12-bit buffered DAC outputs
Enhanced control peripherals
– 24 PWM channels with enhanced features
– 16 High-Resolution Pulse Width Modulator
(HRPWM) channels
•
•
•
– 6-channel Direct Memory Access (DMA)
controller
– Up to 169 individually programmable,
multiplexed General-Purpose Input/Output
(GPIO) pins with input filtering
– Expanded Peripheral Interrupt controller (ePIE)
– Multiple Low-Power Mode (LPM) support with
external wakeup
Communications peripherals
– USB 2.0 (MAC + PHY)
– Support for 12-pin 3.3 V-compatible Universal
Parallel Port (uPP) interface
– Two Controller Area Network (CAN) modules
(pin-bootable)
•
High resolution on both A and B channels of
8 PWM modules
Dead-band support (on both standard and
high resolution)
•
– Six Enhanced Capture (eCAP) modules
– Three Enhanced Quadrature Encoder Pulse
(eQEP) modules
– Eight Sigma-Delta Filter Module (SDFM) input
channels, 2 parallel filters per channel
•
•
•
Standard SDFM data filtering
Comparator filter for fast action for out of
range
– Three high-speed (up to 50-MHz) SPI ports
(pin-bootable)
•
•
Configurable Logic Block (CLB)
– Augments existing peripheral capability
– Supports position manager solutions
Functional Safety-Compliant
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
– Developed for functional safety applications
2 Applications
– Documentation available to aid ISO 26262
system design up to ASIL D; IEC 61508 up to
SIL 3; IEC 60730 up to Class C; and UL 1998
up to Class 2
– Hardware integrity up to ASIL B, SIL 2
Safety-related certification
– ISO 26262 certified up to ASIL B and IEC
61508 certified up to SIL 2 by TUV SUD
Package options:
– Lead-free, green packaging
– 337-ball New Fine Pitch Ball Grid Array
(nFBGA) [ZWT suffix]
– 176-pin PowerPAD™ Thermally Enhanced Low-
Profile Quad Flatpack (HLQFP)
[PTP suffix]
– 100-pin PowerPAD Thermally Enhanced Thin
Quad Flatpack (HTQFP) [PZP suffix]
Temperature options:
– T: –40°C to 105°C junction
– S: –40°C to 125°C junction
– Q: –40°C to 125°C free-air
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Medium/short range radar
Traction inverter motor control
HVAC large commercial motor control
Automated sorting equipment
CNC control
AC charging (pile) station
DC charging (pile) station
EV charging station power module
•
•
Energy storage power conversion system (PCS)
Central inverter
Solar power optimizer
String inverter
Inverter & motor control
On-board (OBC) & wireless charger
Linear motor segment controller
Servo drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
Industrial AC-DC
•
Three phase UPS
(AEC Q100 qualification for automotive
applications)
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced
closed-loop control applications such as industrial motor drives; solar inverters and digital power; electrical
vehicles and transportation; and sensing and signal processing. To accelerate application development, the
DigitalPower software development kit (SDK) for C2000 MCUs and the MotorControl software development kit
(SDK) for C2000™ MCUs are available.
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz of
signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables
fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations;
and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.
The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent
32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC)
and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system
consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in
conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit
conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs,
eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend
the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs and supports high-
speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with
MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information
PART NUMBER(1)
TMS320F28379SZWT
TMS320F28377SZWT
TMS320F28376SZWT
TMS320F28375SZWT
TMS320F28374SZWT
TMS320F28379SPTP
TMS320F28378SPTP
TMS320F28377SPTP
TMS320F28376SPTP
TMS320F28375SPTP
TMS320F28374SPTP
TMS320F28379SPZP
TMS320F28378SPZP
TMS320F28377SPZP
TMS320F28376SPZP
TMS320F28375SPZP
TMS320F28374SPZP
PACKAGE
nFBGA (337)
nFBGA (337)
nFBGA (337)
nFBGA (337)
nFBGA (337)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
HTQFP (100)
HTQFP (100)
HTQFP (100)
HTQFP (100)
HTQFP (100)
HTQFP (100)
BODY SIZE
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
16.0 mm × 16.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Functional Block Diagram
Figure 4-1 shows the CPU system and associated peripherals.
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
MEMCPU1
Low-Power
Mode Control
CPU1.CLA1 to CPU1
C28 CPU-1
GPIO MUX
INTOSC1
CPU1.CLA1
User-Configurable
128x16 MSG RAM
DCSM
OTP
1K x 16
CPU1 to CPU1.CLA1
128x16 MSG RAM
PSWD
FPU
VCU-II
TMU
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
Watchdog
Main PLL
Aux PLL
Flash Bank 0
256K x 16
Secure
Flash Bank 1
256K x 16
Secure
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
Secure Memories
shown in Red
PUMP
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
Flash Wrapper for
Bank 0
Flash Wrapper for
Bank 1
INTOSC2
WD Timer
NMI-WDT
External Crystal or
Oscillator
CPU Timer 0
CPU Timer 1
CPU Timer 2
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
A5:0
B5:0
C5:2
D5:0
16-/12-bit ADC
x4
A
B
C
D
Global Shared
16x 4Kx16
GS0-GS15 RAMs
ePIE
(up to 192
AUXCLKIN
ADC
Result
Regs
Secure-ROM 32Kx16
Secure
Analog
MUX
interrupts)
TRST
TCK
TDI
Config
Boot-ROM 32Kx16
Nonsecure
JTAG
ADCIN14
ADCIN15
Data Bus
Bridge
TMS
TDO
CPU1.CLA1 Data ROM
(4Kx16)
CPU1.DMA
Comparator
Subsystem
(CMPSS)
DAC
x3
CPU1 Buses
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Peripheral Frame 1
Data Bus Bridge
Peripheral Frame 2
McBSP-A/B
SCI-
USB
Ctrl /
PHY
SPI-
A/B/C
(16L FIFO)
ePWM-1/../12
HRPWM-1/../8
CAN-
A/B
(32-MBOX)
RAM
I2C-A/B
A/B/C/D
(16L FIFO)
(16L FIFO)
eCAP-
1/../6
eQEP-1/2/3
SDFM-1/2
uPP
EMIF1
EMIF2
GPIO
GPIO MUX, Input X-BAR, Output X-BAR
Figure 4-1. Functional Block Diagram
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagrams.............................................................. 9
6.2 Signal Descriptions................................................... 16
6.3 Pins With Internal Pullup and Pulldown.................... 39
6.4 Pin Multiplexing.........................................................40
6.5 Connections for Unused Pins................................... 47
7 Specifications................................................................ 48
7.1 Absolute Maximum Ratings...................................... 48
7.2 ESD Ratings – Commercial...................................... 49
7.3 ESD Ratings – Automotive....................................... 49
7.4 Recommended Operating Conditions.......................50
7.5 Power Consumption Summary................................. 51
7.6 Electrical Characteristics...........................................55
7.7 Thermal Resistance Characteristics......................... 56
7.8 Thermal Design Considerations................................57
7.9 System......................................................................58
7.10 Analog Peripherals..................................................93
7.11 Control Peripherals............................................... 123
7.12 Communications Peripherals................................142
8 Detailed Description....................................................175
8.1 Overview.................................................................175
8.2 Functional Block Diagram.......................................175
8.3 Memory...................................................................177
8.4 Identification............................................................186
8.5 Bus Architecture – Peripheral Connectivity.............187
8.6 C28x Processor...................................................... 187
8.7 Control Law Accelerator..........................................191
8.8 Direct Memory Access............................................192
8.9 Boot ROM and Peripheral Booting..........................194
8.10 Dual Code Security Module.................................. 197
8.11 Timers................................................................... 198
8.12 Nonmaskable Interrupt With Watchdog Timer
(NMIWD)................................................................... 198
8.13 Watchdog..............................................................199
8.14 Configurable Logic Block (CLB)............................200
8.15 Functional Safety.................................................. 202
9 Applications, Implementation, and Layout............... 204
9.1 TI Reference Design...............................................204
10 Device and Documentation Support........................205
10.1 Device and Development Support Tool
Nomenclature............................................................205
10.2 Markings............................................................... 206
10.3 Tools and Software............................................... 207
10.4 Documentation Support........................................ 209
10.5 Support Resources............................................... 209
10.6 Trademarks...........................................................210
10.7 Electrostatic Discharge Caution............................210
10.8 Glossary................................................................210
11 Mechanical, Packaging, and Orderable
Information.................................................................. 211
11.1 Packaging Information...........................................211
4 Revision History
Changes from June 25, 2020 to January 31, 2021 (from Revision I (June 2020) to Revision J
(January 2021))
Page
•
•
•
•
Device Comparison: Updated part numbers.......................................................................................................6
ESD Ratings – Commercial: Updated part numbers........................................................................................ 49
ESD Ratings – Automotive: Updated part numbers......................................................................................... 49
Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................205
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
5 Device Comparison
Table 5-1 lists the features of each 2837xS device.
Table 5-1. Device Comparison
28377S
28375S
28375S-Q1
FEATURE(1)
Package Type
(ZWT is an nFBGA package.
PTP is an HLQFP package.
PZP is an HTQFP package.)
28379S
28378S
28376S
28374S
28377S-Q1
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
Processor and Accelerators
Number
1
Frequency (MHz)
200
Floating-Point Unit
(FPU)
C28x
Yes
VCU-II
Yes
Yes
1
TMU – Type 0
Number
CLA – Type 1
Frequency (MHz)
200
1
6-Channel DMA – Type 0
Memory
Flash (16-bit words)
1MB (512KW)
1MB (512KW)
128KB (64KW)
1MB (512KW)
512KB (256KW)
36KB (18KW)
1MB (512KW)
512KB (256KW)
Dedicated and Local
Shared RAM
RAM
Global Shared RAM
(16-bit words)
128KB (64KW)
128KB (64KW)
96KB (48KW)
128KB (64KW)
96KB (48KW)
164KB
(82KW)
Total RAM
164KB (82KW)
164KB (82KW)
132KB (66KW)
164KB (82KW)
132KB (66KW)
Code security for on-chip flash, RAM,
and OTP blocks
Yes
Boot ROM
Yes
System
Configurable Logic Block (CLB)
32-bit CPU timers
4 tiles
No
3
1
Watchdog timers
Nonmaskable Interrupt Watchdog
(NMIWD) timers
1
Crystal oscillator/External clock input
0-pin internal oscillator
1
2
I/O pins
GPIO
169
97
–
41
97
41
169
97
–
41
169
5
97
–
41
169
97
–
41
169
97
–
41
(shared)
External interrupts
EMIF1 (16-bit or 32-bit)
1
–
–
1
–
–
–
1
–
–
1
–
–
1
–
–
1
–
–
EMIF
EMIF2 (16-bit)
1
1
1
1
1
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table 5-1. Device Comparison (continued)
28377S
28375S
28375S-Q1
FEATURE(1)
28379S
28378S
28376S
28374S
28377S-Q1
Package Type
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
337-
Ball
ZWT
176-
Pin
PTP
100-
Pin
PZP
(ZWT is an nFBGA package.
PTP is an HLQFP package.
PZP is an HTQFP package.)
Analog Peripherals
MSPS
1.1
915
20
9
–
–
–
–
1.1
–
–
–
–
Conversion Time (ns)(2)
915
ADC 16-bit
mode
Input pins
24
12
14
7
24
12
20
9
14
7
24
12
20
9
14
7
Channels (differential)
MSPS
3.5
280
24
Conversion Time (ns)(2)
Input pins
ADC 12-bit
mode
24
24
20
20
14
14
2
20
20
14
14
24
24
20
20
14
14
2
20
20
14
14
2
24
24
20
20
14
14
24
24
20
20
14
14
Channels
(single-ended)
24
Number of 16-bit or 12-bit ADCs
Number of 12-bit only ADCs
Temperature sensor
4
–
4
8
4
–
–
4
8
2
4
–
4
8
2
4
4
2
4
1
CMPSS (each CMPSS has two
comparators and two internal DACs)
8
4
4
8
4
8
Buffered DAC
3
6
Control Peripherals (3)
eCAP inputs – Type 0
Enhanced Pulse Width Modulator
(ePWM) channels – Type 4
24
3
15
2
24
3
15
24
3
15
24
3
15
2
24
3
15
2
24
3
15
2
eQEP modules – Type 0
2
9
6
2
9
6
High-resolution ePWM channels –
Type 4
16
8
9
16
8
16
8
16
8
9
16
8
9
16
8
9
SDFM channels – Type 0
6
6
6
6
Communication Peripherals (3)
Controller Area Network (CAN) –
Type 0(4)
2
2
2
Inter-Integrated Circuit (I2C) – Type 0
Multichannel Buffered Serial Port
(McBSP) – Type 1
Serial Communications Interface (SCI) –
Type 0
4
3
4
3
4
3
4
3
4
3
4
3
Serial Peripheral Interface (SPI) –
Type 2
3
Universal Serial Bus (USB) – Type 0
uPP – Type 0
1
1
Temperature and Qualification
T: –40°C to 105°C
Junction
Yes
No
Yes
Temperature ( S: –40°C to 125°C
Yes
TJ)
Q: –40°C to 150°C(5)
No
No
No
No
Yes
Yes
No
No
No
No
Yes
Yes
No
No
Free-Air
Temperature ( Q: –40°C to 125°C(5)
TA)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time
Control Peripherals Reference Guide.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to
the largest package offered within a part number. See Section 6 to identify which peripheral instances are accessible on pins in the
smaller package.
(4) The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this
peripheral.
(5) The letter Q refers to AEC Q100 qualification for automotive applications.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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5.1 Related Products
For information about similar products, see the following links:
TMS320F2837xD Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the TMS320F2807x series.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
6 Terminal Configuration and Functions
6.1 Pin Diagrams
Figure 6-1 to Figure 6-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array.
Each figure shows a quadrant of the terminal assignments. Figure 6-5 shows the pin assignments on the 176-pin
PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 6-6 shows the pin assignments on the
100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.
1
2
3
4
5
6
7
8
9
10
GPIO116
VSSA
VREFHIB
VREFLOD
VSS
VDDIO
W
ADCINB1
ADCINB3
ADCINB5
GPIO128
W
V
U
T
VREFHIA
ADCINA0
ADCINA1
VREFHIC
VSSA
VREFHID
ADCIND1
ADCIND0
VSSA
VREFLOB
ADCIND3
ADCIND2
VDDA
VSSA
ADCIND5
ADCIND4
VSS
V
ADCINB0
ADCINA2
ADCINA3
VREFLOA
VREFLOC
GPIO109
GPIO110
GPIO106
ADCINB2
ADCINA4
ADCINA5
ADCINC2
ADCINC3
GPIO114
GPIO112
GPIO107
ADCINB4
ADCIN15
ADCIN14
ADCINC4
ADCINC5
GPIO113
GPIO111
GPIO108
GPIO124
GPIO123
GPIO122
VSS
GPIO127
GPIO126
GPIO125
VDDIO
GPIO131
GPIO130
GPIO129
VDD
U
T
R
P
N
M
L
R
P
VSSA
VDDA
VSS
VSS
VDDIO
VDD
7
8
9
10
VSS
VSS
VSS
N
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
M
M
VSS
VSS
VSS
VSS
VSS
GPIO27
L
L
VDD
VDD
VSS
VSS
VSS
K
GPIO26
GPIO25
GPIO24
GPIO23
K
K
1
2
3
4
5
6
8
9
10
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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11
12
13
14
15
16
17
18
19
VSS
W
V
U
T
GPIO29
FLT1
TDI
TMS
TDO
GPIO121
GPIO39
GPIO132
W
VDDIO
GPIO28
GPIO31
GPIO30
VDD3VFL
GPIO115
GPIO117
GPIO118
VDD3VFL
FLT2
GPIO32
GPIO33
VDD
TCK
GPIO120
GPIO119
VSS
GPIO36
GPIO37
GPIO38
GPIO48
GPIO52
GPIO56
GPIO59
GPIO61
GPIO40
GPIO41
GPIO136
GPIO49
GPIO53
GPIO58
GPIO60
GPIO64
GPIO134
GPIO135
GPIO137
GPIO50
GPIO54
GPIO57
GPIO141
VSS
V
TRST
GPIO34
GPIO35
VSS
ERRORSTS
GPIO138
GPIO51
U
T
R
R
P
N
M
L
VSS
VSS
VDD
VSS
VSS
P
GPIO55
11
12
13
N
VDDIO
VDDIO
GPIO139
GPIO140
GPIO142
VSS
VSS
VSS
VSS
M
M
VSS
VSS
VDDIO
VDDIO
L
L
VSS
VSS
VSS
VSS
K
K
GPIO65
GPIO66
GPIO44
GPIO45
K
11
12
14
15
16
17
18
19
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-2. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
11
12
14
15
16
17
18
19
X2
VSS
VSS
VDD
VDD
J
J
H
G
GPIO63
GPIO62
VREGENZ
J
VSS
VSS
VSS
VSS
VDDOSC
VDDOSC
VSSOSC
GPIO133
GPIO143
GPIO47
GPIO146
GPIO68
GPIO69
VSSOSC
H
H
G
F
VDD
VDD
VSS
VSS
X1
11
12
13
VDD
VSS
VDDIO
VSS
VSS
VDDIO
F
E
D
C
B
A
GPIO144
GPIO145
GPIO147
GPIO74
GPIO71
XRS
VDD
VSS
VDDIO
VSS
VSS
VDDIO
GPIO46
GPIO42
GPIO43
GPIO67
E
D
C
B
A
GPIO87
GPIO86
GPIO85
GPIO156
GPIO155
GPIO154
GPIO152
GPIO151
GPIO150
GPIO148
GPIO83
GPIO82
GPIO80
GPIO79
GPIO78
GPIO75
GPIO76
GPIO72
VDDIO
VSS
GPIO84
GPIO153
GPIO149
GPIO81
GPIO77
GPIO73
GPIO70
11
12
13
14
15
16
17
18
19
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-3. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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1
2
3
4
5
6
8
9
10
VSS
VSS
VSS
VSS
VSS
J
H
G
F
GPIO103
GPIO104
GPIO105
GPIO22
J
J
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
VSS
GPIO100
GPIO99
GPIO98
GPIO16
GPIO13
GPIO11
VDDIO
GPIO101
GPIO102
NC
H
G
H
VDDIO
VDDIO
GPIO8
GPIO9
7
8
9
10
VDDIO
VSS
VDDIO
VSS
VDD
VDDIO
GPIO20
GPIO17
GPIO14
GPIO12
GPIO10
GPIO21
GPIO18
GPIO15
GPIO96
GPIO95
F
VSS
VSS
VDDIO
VSS
VDD
VDDIO
E
D
C
B
A
GPIO19
GPIO168
GPIO167
GPIO93
E
D
C
B
A
GPIO166
GPIO165
GPIO91
GPIO89
GPIO88
GPIO7
GPIO5
GPIO4
GPIO3
GPIO1
GPIO0
GPIO164
GPIO162
GPIO161
GPIO160
GPIO159
GPIO158
GPIO157
VSS
VDDIO
VSS
GPIO97
GPIO94
GPIO92
GPIO90
GPIO6
GPIO2
GPIO163
1
2
3
4
5
6
7
8
9
10
A. Only the GPIO function is shown on GPIO terminals. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-4. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
V
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
GPIO68
GPIO69
GPIO70
GPIO71
DDIO
GPIO40
GPIO39
GPIO38
GPIO37
GPIO36
V
DD
V
DDIO
V
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
DDIO
TCK
TMS
TRST
TDO
TDI
V
DD
V
DDIO
V
DDIO
FLT2
FLT1
V
GPIO80
GPIO81
GPIO82
GPIO83
DD3VFL
GPIO35
GPIO34
GPIO33
V
DDIO
V
V
DDIO
DD
GPIO32
GPIO31
GPIO29
GPIO28
GPIO30
GPIO84
GPIO85
GPIO86
GPIO87
V
DD
V
V
DDIO
DDIO
V
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
DD
ADCIND4
ADCIND3
ADCIND2
ADCIND1
ADCIND0
V
REFHID
V
DDA
V
V
REFHIB
DDIO
V
V
SSA
DD
V
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
REFLOD
V
REFLOB
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCIN15
A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-5. 176-Pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack (Top View)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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GPIO70
GPIO71
VDD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TCK
TMS
TRST
TDO
TDI
VDDIO
GPIO72
GPIO73
VDD
VDDIO
GPIO78
VDDIO
FLT2
VDD
GPIO84
GPIO85
GPIO86
FLT1
VDD3VFL
VDDIO
VDD
VDDA
GPIO87
VDD
VREFHIB
VSSA
VDDIO
VSSA
GPIO2
GPIO3
VREFLOB
GPIO4
VDDIO
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCIN15
ADCIN14
VDD
GPIO89
GPIO90
GPIO91
GPIO92
GPIO10
A. Only the GPIO function is shown on GPIO pins. See Section 6.2.1 for the complete, muxed signal name.
Figure 6-6. 100-Pin PZP PowerPAD HTQFP (Top View)
Note
The exposed lead frame die pad of the PowerPAD™ package serves two functions: to remove heat
from the die and to provide ground path for the digital ground (analog ground is provided through
dedicated pins). Thus, the PowerPAD should be soldered to the ground (GND) plane of the PCB
because this will provide both the digital ground path and good thermal conduction path. To make
optimum use of the thermal efficiencies designed into the PowerPAD package, the PCB must be
designed with this technology in mind. A thermal land is required on the surface of the PCB directly
underneath the body of the PowerPAD. The thermal land should be soldered to the exposed lead
frame die pad of the PowerPAD package; the thermal land should be as large as needed to dissipate
the required heat. An array of thermal vias should be used to connect the thermal pad to the internal
GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details on using
the PowerPAD package.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Note
PCB footprints and schematic symbols are available for download in a vendor-neutral format, which
can be exported to the leading EDA CAD/CAE design tools. See the CAD/CAE Symbols section in the
product folder for each device, under the Packaging section. These footprints and symbols can also
be searched for at http://webench.ti.com/cad/.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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6.2 Signal Descriptions
Section 6.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The
peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be
available in all devices. See Table 5-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can
be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are
not enabled at reset.
6.2.1 Signal Descriptions
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
ADC, DAC, AND COMPARATOR SIGNALS
ADC-A high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIA and VREFLOA pins.
VREFHIA
VREFHIB
VREFHIC
V1
W5
R1
37
53
35
19
37
–
I
I
I
NOTE: Do not load this pin externally.
ADC-B high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
ADC-C high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHIC and VREFLOC pins.
NOTE: Do not load this pin externally.
ADC-D high reference. This voltage must be driven into
the pin from external circuitry. Place at least a 1-µF
capacitor on this pin for the 12-bit mode, or at least a 22-
µF capacitor for the 16-bit mode. This capacitor should be
placed as close to the device as possible between the
VREFHID and VREFLOD pins.
VREFHID
V5
R2
55
33
–
I
I
NOTE: Do not load this pin externally.
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. On the PZP package, pin 17 must be
connected to VSSA on the system board.
VREFLOA
17
VREFLOB
VREFLOC
VREFLOD
ADCIN14
V6
P2
50
32
51
34
–
I
I
I
I
ADC-B low reference
ADC-C low reference
ADC-D low reference
W6
–
Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference.
T4
U4
44
45
26
27
CMPIN4P
ADCIN15
I
I
Comparator 4 positive input
Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together (either single-ended or differential) from an
external reference.
CMPIN4N
I
Comparator 4 negative input
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
ADCINA0
I
ADC-A input 0. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
U1
T1
43
42
25
24
DACOUTA
ADCINA1
O
I
DAC-A output
ADC-A input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
DACOUTB
ADCINA2
CMPIN1P
ADCINA3
CMPIN1N
ADCINA4
CMPIN2P
ADCINA5
CMPIN2N
ADCINB0
O
I
DAC-B output
ADC-A input 2
U2
T2
U3
T3
41
40
39
38
23
22
21
20
I
Comparator 1 positive input
ADC-A input 3
I
I
Comparator 1 negative input
ADC-A input 4
I
I
Comparator 2 positive input
ADC-A input 5
I
I
Comparator 2 negative input
I
ADC-B input 0. There is a 100-pF capacitor to VSSA on
this pin in both ADC input or DAC reference mode which
cannot be disabled. If this pin is being used as a
reference for the on-chip DACs, place at least a 1-µF
capacitor on this pin.
V2
46
28
VDAC
I
I
Optional external reference voltage for on-chip DACs.
There is a 100-pF capacitor to VSSA on this pin in both
ADC input or DAC reference mode which cannot be
disabled. If this pin is being used as a reference for the
on-chip DACs, place at least a 1-µF capacitor on this pin.
ADCINB1
ADC-B input 1. There is a 50-kΩ internal pulldown on this
pin in both an ADC input or DAC output mode which
cannot be disabled.
W2
47
29
DACOUTC
ADCINB2
CMPIN3P
ADCINB3
CMPIN3N
ADCINB4
ADCINB5
ADCINC2
CMPIN6P
ADCINC3
CMPIN6N
ADCINC4
CMPIN5P
ADCINC5
CMPIN5N
ADCIND0
CMPIN7P
ADCIND1
CMPIN7N
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DAC-C output
ADC-B input 2
V3
48
49
30
31
Comparator 3 positive input
ADC-B input 3
W3
Comparator 3 negative input
ADC-B input 4
V4
–
–
32
33
W4
ADC-B input 5
ADC-C input 2
R3
P3
R4
P4
T5
U5
31
30
29
–
–
–
–
–
–
–
Comparator 6 positive input
ADC-C input 3
Comparator 6 negative input
ADC-C input 4
Comparator 5 positive input
ADC-C input 5
Comparator 5 negative input
ADC-D input 0
56
57
Comparator 7 positive input
ADC-D input 1
Comparator 7 negative input
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
ADCIND2
CMPIN8P
ADCIND3
CMPIN8N
ADCIND4
ADCIND5
I
I
I
I
I
I
ADC-D input 2
T6
U6
58
59
–
–
Comparator 8 positive input
ADC-D input 3
Comparator 8 negative input
ADC-D input 4
T7
U7
60
–
–
–
ADC-D input 5
GPIO AND PERIPHERAL SIGNALS
GPIO0
0, 4, 8, 12
I/O
O
General-purpose input/output 0
EPWM1A
SDAA
1
C8
D8
160
161
–
–
Enhanced PWM1 output A (HRPWM-capable)
I2C-A data open-drain bidirectional port
General-purpose input/output 1
Enhanced PWM1 output B (HRPWM-capable)
McBSP-B receive frame synch
I2C-A clock open-drain bidirectional port
General-purpose input/output 2
Enhanced PWM2 output A (HRPWM-capable)
Output 1 of the output XBAR
6
I/OD
I/O
O
GPIO1
0, 4, 8, 12
EPWM1B
MFSRB
SCLA
1
3
I/O
I/OD
I/O
O
6
GPIO2
0, 4, 8, 12
EPWM2A
1
A7
B7
162
163
91
92
OUTPUTXBAR1
SDAB
5
O
6
I/OD
I/O
O
I2C-B data open-drain bidirectional port
General-purpose input/output 3
Enhanced PWM2 output B (HRPWM-capable)
Output 2 of the output XBAR
GPIO3
0, 4, 8, 12
EPWM2B
OUTPUTXBAR2
MCLKRB
1
2
O
3
I/O
O
McBSP-B receive clock
OUTPUTXBAR2
SCLB
5
Output 2 of the output XBAR
6
I/OD
I/O
O
I2C-B clock open-drain bidirectional port
General-purpose input/output 4
Enhanced PWM3 output A (HRPWM-capable)
Output 3 of the output XBAR
GPIO4
0, 4, 8, 12
EPWM3A
OUTPUTXBAR3
CANTXA
1
C7
D7
164
165
93
5
O
6
O
CAN-A transmit
GPIO5
0, 4, 8, 12
I/O
O
General-purpose input/output 5
Enhanced PWM3 output B (HRPWM-capable)
McBSP-A receive frame synch
Output 3 of the output XBAR
EPWM3B
MFSRA
1
2
–
I/O
O
OUTPUTXBAR3
CANRXA
3
6
I
CAN-A receive
GPIO6
0, 4, 8, 12
I/O
O
General-purpose input/output 6
Enhanced PWM4 output A (HRPWM-capable)
Output 4 of the output XBAR
EPWM4A
OUTPUTXBAR4
EXTSYNCOUT
EQEP3A
1
2
O
A6
166
–
3
O
External ePWM synch pulse output
Enhanced QEP3 input A
5
I
CANTXB
6
O
CAN-B transmit
GPIO7
0, 4, 8, 12
I/O
O
General-purpose input/output 7
Enhanced PWM4 output B (HRPWM-capable)
McBSP-A receive clock
EPWM4B
MCLKRA
1
2
3
5
6
I/O
O
B6
167
–
OUTPUTXBAR5
EQEP3B
Output 5 of the output XBAR
I
Enhanced QEP3 input B
CANRXB
I
CAN-B receive
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO8
0, 4, 8, 12
I/O
O
General-purpose input/output 8
EPWM5A
CANTXB
ADCSOCAO
EQEP3S
1
Enhanced PWM5 output A (HRPWM-capable)
CAN-B transmit
2
O
G2
18
–
3
O
ADC start-of-conversion A output for external ADC
Enhanced QEP3 strobe
5
I/O
O
SCITXDA
GPIO9
6
SCI-A transmit data
0, 4, 8, 12
I/O
O
General-purpose input/output 9
Enhanced PWM5 output B (HRPWM-capable)
SCI-B transmit data
EPWM5B
SCITXDB
OUTPUTXBAR6
EQEP3I
1
2
O
G3
19
–
3
O
Output 6 of the output XBAR
Enhanced QEP3 index
5
I/O
I
SCIRXDA
GPIO10
6
SCI-A receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 10
Enhanced PWM6 output A (HRPWM-capable)
CAN-B receive
EPWM6A
CANRXB
ADCSOCBO
EQEP1A
1
2
I
3
O
ADC start-of-conversion B output for external ADC
Enhanced QEP1 input A
B2
C1
C2
1
2
4
100
5
I
SCITXDB
UPP-WAIT
6
O
SCI-B transmit data
15
I/O
Universal parallel port wait. Receiver asserts to request a
pause in transfer.
GPIO11
0, 4, 8, 12
I/O
O
I
General-purpose input/output 11
Enhanced PWM6 output B (HRPWM-capable)
SCI-B receive data
EPWM6B
1
2, 6
3
SCIRXDB
OUTPUTXBAR7
EQEP1B
1
O
I
Output 7 of the output XBAR
Enhanced QEP1 input B
5
UPP-START
15
I/O
Universal parallel port start. Transmitter asserts at start of
DMA line.
GPIO12
EPWM7A
CANTXB
MDXB
0, 4, 8, 12
I/O
O
General-purpose input/output 12
Enhanced PWM7 output A (HRPWM-capable)
CAN-B transmit
1
2
O
3
O
McBSP-B transmit serial data
Enhanced QEP1 strobe
3
EQEP1S
SCITXDC
UPP-ENA
5
I/O
O
6
SCI-C transmit data
15
I/O
Universal parallel port enable. Transmitter asserts while
data bus is active.
GPIO13
EPWM7B
CANRXB
MDRB
0, 4, 8, 12
I/O
O
I
General-purpose input/output 13
Enhanced PWM7 output B (HRPWM-capable)
CAN-B receive
1
2
3
D1
5
4
I
McBSP-B receive serial data
Enhanced QEP1 index
EQEP1I
SCIRXDC
UPP-D7
5
I/O
I
6
SCI-C receive data
15
I/O
Universal parallel port data line 7
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO14
0, 4, 8, 12
I/O
O
General-purpose input/output 14
EPWM8A
SCITXDB
MCLKXB
1
Enhanced PWM8 output A (HRPWM-capable)
SCI-B transmit data
2
O
D2
6
5
3
I/O
O
McBSP-B transmit clock
OUTPUTXBAR3
UPP-D6
6
Output 3 of the output XBAR
Universal parallel port data line 6
General-purpose input/output 15
Enhanced PWM8 output B (HRPWM-capable)
SCI-B receive data
15
I/O
I/O
O
GPIO15
0, 4, 8, 12
EPWM8B
SCIRXDB
MFSXB
1
2
I
D3
7
6
3
I/O
O
McBSP-B transmit frame synch
Output 4 of the output XBAR
Universal parallel port data line 5
General-purpose input/output 16
SPI-A slave in, master out
CAN-B transmit
OUTPUTXBAR4
UPP-D5
6
15
I/O
I/O
I/O
O
GPIO16
0, 4, 8, 12
SPISIMOA
CANTXB
OUTPUTXBAR7
EPWM9A
SD1_D1
1
2
3
E1
E2
E3
E4
8
7
O
Output 7 of the output XBAR
Enhanced PWM9 output A
Sigma-Delta 1 channel 1 data input
Universal parallel port data line 4
General-purpose input/output 17
SPI-A slave out, master in
CAN-B receive
5
O
7
I
UPP-D4
15
I/O
I/O
I/O
I
GPIO17
0, 4, 8, 12
SPISOMIA
CANRXB
OUTPUTXBAR8
EPWM9B
SD1_C1
1
2
3
9
8
O
Output 8 of the output XBAR
Enhanced PWM9 output B
Sigma-Delta 1 channel 1 clock input
Universal parallel port data line 3
General-purpose input/output 18
SPI-A clock
5
O
7
I
UPP-D3
15
I/O
I/O
I/O
O
GPIO18
0, 4, 8, 12
SPICLKA
SCITXDB
CANRXA
EPWM10A
SD1_D2
1
2
SCI-B transmit data
3
10
9
I
CAN-A receive
5
O
Enhanced PWM10 output A
Sigma-Delta 1 channel 2 data input
Universal parallel port data line 2
General-purpose input/output 19
SPI-A slave transmit enable
SCI-B receive data
7
I
UPP-D2
15
I/O
I/O
I/O
I
GPIO19
0, 4, 8, 12
SPISTEA
SCIRXDB
CANTXA
EPWM10B
SD1_C2
1
2
3
12
11
O
CAN-A transmit
5
O
Enhanced PWM10 output B
Sigma-Delta 1 channel 2 clock input
Universal parallel port data line 1
7
I
UPP-D1
15
I/O
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO20
0, 4, 8, 12
I/O
I
General-purpose input/output 20
EQEP1A
MDXA
1
Enhanced QEP1 input A
2
O
O
O
I
McBSP-A transmit serial data
CAN-B transmit
CANTXB
EPWM11A
SD1_D3
UPP-D0
3
F2
F3
J4
K4
13
14
22
23
12
13
–
5
Enhanced PWM11 output A
Sigma-Delta 1 channel 3 data input
Universal parallel port data line 0
General-purpose input/output 21
Enhanced QEP1 input B
7
15
I/O
I/O
I
GPIO21
0, 4, 8, 12
EQEP1B
MDRA
1
2
I
McBSP-A receive serial data
CAN-B receive
CANRXB
EPWM11B
SD1_C3
UPP-CLK
GPIO22
3
I
5
O
I
Enhanced PWM11 output B
Sigma-Delta 1 channel 3 clock input
Universal parallel port transmit clock
General-purpose input/output 22
Enhanced QEP1 strobe
7
15
I/O
I/O
I/O
I/O
O
O
I/O
I
0, 4, 8, 12
EQEP1S
MCLKXA
SCITXDB
EPWM12A
SPICLKB
SD1_D4
GPIO23
1
2
McBSP-A transmit clock
3
SCI-B transmit data
5
Enhanced PWM12 output A
SPI-B clock
6
7
Sigma-Delta 1 channel 4 data input
General-purpose input/output 23
Enhanced QEP1 index
0, 4, 8, 12
I/O
I/O
I/O
I
EQEP1I
1
MFSXA
2
McBSP-A transmit frame synch
SCI-B receive data
SCIRXDB
EPWM12B
SPISTEB
SD1_C4
GPIO24
3
–
5
O
I/O
I
Enhanced PWM12 output B
SPI-B slave transmit enable
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 24
Output 1 of the output XBAR
Enhanced QEP2 input A
6
7
0, 4, 8, 12
I/O
O
I
OUTPUTXBAR1
EQEP2A
MDXB
1
2
K3
24
–
3
O
I/O
I
McBSP-B transmit serial data
SPI-B slave in, master out
Sigma-Delta 2 channel 1 data input
General-purpose input/output 25
Output 2 of the output XBAR
Enhanced QEP2 input B
SPISIMOB
SD2_D1
GPIO25
6
7
0, 4, 8, 12
I/O
O
I
OUTPUTXBAR2
EQEP2B
MDRB
1
2
3
6
7
K2
25
–
I
McBSP-B receive serial data
SPI-B slave out, master in
Sigma-Delta 2 channel 1 clock input
SPISOMIB
SD2_C1
I/O
I
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO26
0, 4, 8, 12
I/O
O
General-purpose input/output 26
OUTPUTXBAR3
EQEP2I
1
Output 3 of the output XBAR
Enhanced QEP2 index
2
I/O
I/O
O
MCLKXB
OUTPUTXBAR3
SPICLKB
SD2_D2
3
K1
27
–
McBSP-B transmit clock
5
Output 3 of the output XBAR
SPI-B clock
6
I/O
I
7
Sigma-Delta 2 channel 2 data input
General-purpose input/output 27
Output 4 of the output XBAR
Enhanced QEP2 strobe
GPIO27
0, 4, 8, 12
I/O
O
OUTPUTXBAR4
EQEP2S
1
2
I/O
I/O
O
MFSXB
3
L1
28
–
McBSP-B transmit frame synch
Output 4 of the output XBAR
SPI-B slave transmit enable
Sigma-Delta 2 channel 2 clock input
General-purpose input/output 28
SCI-A receive data
OUTPUTXBAR4
SPISTEB
SD2_C2
5
6
I/O
I
7
GPIO28
0, 4, 8, 12
I/O
I
SCIRXDA
EM1CS4
1
2
O
External memory interface 1 chip select 4
Output 5 of the output XBAR
Enhanced QEP3 input A
V11
W11
T11
U11
64
65
63
66
–
–
–
–
OUTPUTXBAR5
EQEP3A
5
O
6
I
SD2_D3
7
I
Sigma-Delta 2 channel 3 data input
General-purpose input/output 29
SCI-A transmit data
GPIO29
0, 4, 8, 12
I/O
O
SCITXDA
EM1SDCKE
OUTPUTXBAR6
EQEP3B
1
2
O
External memory interface 1 SDRAM clock enable
Output 6 of the output XBAR
5
O
6
I
Enhanced QEP3 input B
SD2_C3
7
I
Sigma-Delta 2 channel 3 clock input
General-purpose input/output 30
CAN-A receive
GPIO30
0, 4, 8, 12
I/O
I
CANRXA
EM1CLK
1
2
O
External memory interface 1 clock
Output 7 of the output XBAR
OUTPUTXBAR7
EQEP3S
5
O
6
I/O
I
Enhanced QEP3 strobe
SD2_D4
7
Sigma-Delta 2 channel 4 data input
General-purpose input/output 31
CAN-A transmit
GPIO31
0, 4, 8, 12
I/O
O
CANTXA
1
EM1WE
2
O
External memory interface 1 write enable
Output 8 of the output XBAR
OUTPUTXBAR8
EQEP3I
5
O
6
I/O
I
Enhanced QEP3 index
SD2_C4
7
Sigma-Delta 2 channel 4 clock input
General-purpose input/output 32
I2C-A data open-drain bidirectional port
External memory interface 1 chip select 0
General-purpose input/output 33
I2C-A clock open-drain bidirectional port
External memory interface 1 read not write
GPIO32
0, 4, 8, 12
I/O
I/OD
O
SDAA
1
U13
T13
67
69
–
–
EM1CS0
2
GPIO33
0, 4, 8, 12
I/O
I/OD
O
SCLA
1
2
EM1RNW
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO34
0, 4, 8, 12
I/O
O
General-purpose input/output 34
OUTPUTXBAR1
EM1CS2
SDAB
1
Output 1 of the output XBAR
U14
T14
V16
U16
T16
70
71
83
84
85
–
–
–
–
–
2
O
External memory interface 1 chip select 2
I2C-B data open-drain bidirectional port
General-purpose input/output 35
SCI-A receive data
6
I/OD
I/O
I
GPIO35
0, 4, 8, 12
SCIRXDA
EM1CS3
SCLB
1
2
O
External memory interface 1 chip select 3
I2C-B clock open-drain bidirectional port
General-purpose input/output 36
SCI-A transmit data
6
I/OD
I/O
O
GPIO36
0, 4, 8, 12
SCITXDA
EM1WAIT
CANRXA
GPIO37
1
2
I
External memory interface 1 Asynchronous SRAM WAIT
CAN-A receive
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 37
Output 2 of the output XBAR
OUTPUTXBAR2
EM1OE
1
2
O
External memory interface 1 output enable
CAN-A transmit
CANTXA
GPIO38
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 38
External memory interface 1 address line 0
SCI-C transmit data
EM1A0
2
SCITXDC
CANTXB
GPIO39
5
O
6
O
CAN-B transmit
0, 4, 8, 12
I/O
O
General-purpose input/output 39
External memory interface 1 address line 1
SCI-C receive data
EM1A1
2
W17
V17
86
87
–
–
SCIRXDC
CANRXB
GPIO40
5
I
6
I
CAN-B receive
0, 4, 8, 12
I/O
O
General-purpose input/output 40
External memory interface 1 address line 2
I2C-B data open-drain bidirectional port
EM1A2
2
6
SDAB
I/OD
I/O
GPIO41
0, 4, 8, 12
General-purpose input/output 41. For applications using
the Hibernate low-power mode, this pin serves as the
GPIOHIBWAKE signal. For details, see the Low Power
Modes section of the System Control chapter in the
TMS320F2837xS Microcontrollers Technical Reference
Manual .
U17
D19
89
51
73
EM1A3
SCLB
2
O
I/OD
I/O
I/OD
O
External memory interface 1 address line 3
I2C-B clock open-drain bidirectional port
General-purpose input/output 42
I2C-A data open-drain bidirectional port
SCI-A transmit data
6
GPIO42
SDAA
0, 4, 8, 12
6
15
130
SCITXDA
USB0DM
GPIO43
SCLA
Analog
0, 4, 8, 12
6
I/O
I/O
I/OD
I
USB PHY differential data
General-purpose input/output 43
I2C-A clock open-drain bidirectional port
SCI-A receive data
C19
K18
131
113
74
–
SCIRXDA
USB0DP
GPIO44
EM1A4
15
Analog
0, 4, 8, 12
2
I/O
I/O
O
USB PHY differential data
General-purpose input/output 44
External memory interface 1 address line 4
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO45
EM1A5
0, 4, 8, 12
I/O
O
General-purpose input/output 45
K19
115
–
2
External memory interface 1 address line 5
General-purpose input/output 46
External memory interface 1 address line 6
SCI-D receive data
GPIO46
EM1A6
0, 4, 8, 12
I/O
O
2
E19
128
–
SCIRXDD
GPIO47
EM1A7
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 47
External memory interface 1 address line 7
SCI-D transmit data
2
E18
R16
129
90
–
–
SCITXDD
GPIO48
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 48
Output 3 of the output XBAR
OUTPUTXBAR3
EM1A8
1
2
O
External memory interface 1 address line 8
SCI-A transmit data
SCITXDA
SD1_D1
GPIO49
6
O
7
I
Sigma-Delta 1 channel 1 data input
General-purpose input/output 49
Output 4 of the output XBAR
0, 4, 8, 12
I/O
O
OUTPUTXBAR4
EM1A9
1
2
R17
R18
R19
P16
93
94
95
96
–
–
–
–
O
External memory interface 1 address line 9
SCI-A receive data
SCIRXDA
SD1_C1
GPIO50
6
I
7
I
Sigma-Delta 1 channel 1 clock input
General-purpose input/output 50
Enhanced QEP1 input A
0, 4, 8, 12
I/O
I
EQEP1A
EM1A10
SPISIMOC
SD1_D2
GPIO51
1
2
O
External memory interface 1 address line 10
SPI-C slave in, master out
6
I/O
I
7
Sigma-Delta 1 channel 2 data input
General-purpose input/output 51
Enhanced QEP1 input B
0, 4, 8, 12
I/O
I
EQEP1B
EM1A11
SPISOMIC
SD1_C2
GPIO52
1
2
O
External memory interface 1 address line 11
SPI-C slave out, master in
6
I/O
I
7
Sigma-Delta 1 channel 2 clock input
General-purpose input/output 52
Enhanced QEP1 strobe
0, 4, 8, 12
I/O
I/O
O
EQEP1S
EM1A12
SPICLKC
SD1_D3
GPIO53
1
2
External memory interface 1 address line 12
SPI-C clock
6
I/O
I
7
Sigma-Delta 1 channel 3 data input
General-purpose input/output 53
Enhanced QEP1 index
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I
EQEP1I
1
2
3
6
7
EM1D31
EM2D15
SPISTEC
SD1_C3
External memory interface 1 data line 31
External memory interface 2 data line 15
SPI-C slave transmit enable
P17
97
–
Sigma-Delta 1 channel 3 clock input
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO54
0, 4, 8, 12
I/O
I/O
I/O
I/O
I
General-purpose input/output 54
SPISIMOA
EM1D30
EM2D14
EQEP2A
SCITXDB
SD1_D4
GPIO55
1
SPI-A slave in, master out
2
External memory interface 1 data line 30
External memory interface 2 data line 14
Enhanced QEP2 input A
3
P18
P19
N16
N18
98
–
–
–
–
5
6
O
SCI-B transmit data
7
I
Sigma-Delta 1 channel 4 data input
General-purpose input/output 55
SPI-A slave out, master in
0, 4, 8, 12
I/O
I/O
I/O
I/O
I
SPISOMIA
EM1D29
EM2D13
EQEP2B
SCIRXDB
SD1_C4
GPIO56
1
2
External memory interface 1 data line 29
External memory interface 2 data line 13
Enhanced QEP2 input B
3
100
101
102
5
6
I
SCI-B receive data
7
I
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 56
SPI-A clock
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
O
SPICLKA
EM1D28
EM2D12
EQEP2S
SCITXDC
SD2_D1
GPIO57
1
2
External memory interface 1 data line 28
External memory interface 2 data line 12
Enhanced QEP2 strobe
3
5
6
SCI-C transmit data
7
I
Sigma-Delta 2 channel 1 data input
General-purpose input/output 57
SPI-A slave transmit enable
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I
SPISTEA
EM1D27
EM2D11
EQEP2I
1
2
External memory interface 1 data line 27
External memory interface 2 data line 11
Enhanced QEP2 index
3
5
SCIRXDC
SD2_C1
GPIO58
6
SCI-C receive data
7
I
Sigma-Delta 2 channel 1 clock input
General-purpose input/output 58
McBSP-A receive clock
0, 4, 8, 12
I/O
I/O
I/O
I/O
O
MCLKRA
EM1D26
EM2D10
OUTPUTXBAR1
SPICLKB
SD2_D2
SPISIMOA
GPIO59
1
2
External memory interface 1 data line 26
External memory interface 2 data line 10
Output 1 of the output XBAR
SPI-B clock
3
N17
103
52
5
6
I/O
I
7
Sigma-Delta 2 channel 2 data input
SPI-A slave in, master out(2)
15
I/O
I/O
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 59(3)
McBSP-A receive frame synch
External memory interface 1 data line 25
External memory interface 2 data line 9
Output 2 of the output XBAR
SPI-B slave transmit enable
MFSRA
1
2
EM1D25
EM2D9
3
M16
104
53
OUTPUTXBAR2
SPISTEB
SD2_C2
SPISOMIA
5
6
I/O
I
7
Sigma-Delta 2 channel 2 clock input
SPI-A slave out, master in(2)
15
I/O
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO60
MCLKRB
EM1D24
EM2D8
0, 4, 8, 12
I/O
I/O
I/O
I/O
O
General-purpose input/output 60
1
McBSP-B receive clock
2
External memory interface 1 data line 24
External memory interface 2 data line 8
Output 3 of the output XBAR
SPI-B slave in, master out
3
M17
105
54
OUTPUTXBAR3
SPISIMOB
SD2_D3
SPICLKA
GPIO61
5
6
I/O
I
7
Sigma-Delta 2 channel 3 data input
SPI-A clock(2)
15
I/O
I/O
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 61(3)
McBSP-B receive frame synch
External memory interface 1 data line 23
External memory interface 2 data line 7
Output 4 of the output XBAR
SPI-B slave out, master in
MFSRB
1
EM1D23
EM2D7
2
3
L16
J17
J16
107
108
109
56
57
58
OUTPUTXBAR4
SPISOMIB
SD2_C3
SPISTEA
GPIO62
5
6
I/O
I
7
Sigma-Delta 2 channel 3 clock input
SPI-A slave transmit enable(2)
General-purpose input/output 62
SCI-C receive data
15
I/O
I/O
I
0, 4, 8, 12
SCIRXDC
EM1D22
EM2D6
1
2
I/O
I/O
I
External memory interface 1 data line 22
External memory interface 2 data line 6
Enhanced QEP3 input A
3
EQEP3A
CANRXA
SD2_D4
GPIO63
5
6
I
CAN-A receive
7
I
Sigma-Delta 2 channel 4 data input
General-purpose input/output 63
SCI-C transmit data
0, 4, 8, 12
I/O
O
SCITXDC
EM1D21
EM2D5
1
2
I/O
I/O
I
External memory interface 1 data line 21
External memory interface 2 data line 5
Enhanced QEP3 input B
3
EQEP3B
CANTXA
SD2_C4
SPISIMOB
GPIO64
5
6
O
CAN-A transmit
7
I
Sigma-Delta 2 channel 4 clock input
SPI-B slave in, master out(2)
General-purpose input/output 64(3)
External memory interface 1 data line 20
External memory interface 2 data line 4
Enhanced QEP3 strobe
15
I/O
I/O
I/O
I/O
I/O
I
0, 4, 8, 12
EM1D20
EM2D4
2
3
L17
110
111
59
EQEP3S
SCIRXDA
SPISOMIB
GPIO65
5
6
SCI-A receive data
15
I/O
I/O
I/O
I/O
I/O
O
SPI-B slave out, master in(2)
General-purpose input/output 65
External memory interface 1 data line 19
External memory interface 2 data line 3
Enhanced QEP3 index
0, 4, 8, 12
EM1D19
EM2D3
2
3
K16
60
EQEP3I
5
SCITXDA
SPICLKB
6
SCI-A transmit data
SPI-B clock(2)
15
I/O
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO66
EM1D18
EM2D2
0, 4, 8, 12
I/O
I/O
I/O
I/OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OD
I/O
I/O
I/O
I
General-purpose input/output 66(3)
External memory interface 1 data line 18
External memory interface 2 data line 2
I2C-B data open-drain bidirectional port
SPI-B slave transmit enable(2)
General-purpose input/output 67
External memory interface 1 data line 17
External memory interface 2 data line 1
General-purpose input/output 68
External memory interface 1 data line 16
External memory interface 2 data line 0
General-purpose input/output 69
External memory interface 1 data line 15
I2C-B clock open-drain bidirectional port
SPI-C slave in, master out(2)
2
3
K17
112
61
SDAB
6
SPISTEB
GPIO67
EM1D17
EM2D1
15
0, 4, 8, 12
2
B19
C18
132
133
–
–
3
GPIO68
EM1D16
EM2D0
0, 4, 8, 12
2
3
GPIO69
EM1D15
SCLB
0, 4, 8, 12
2
B18
A17
134
135
75
76
6
SPISIMOC
GPIO70
EM1D14
CANRXA
SCITXDB
SPISOMIC
GPIO71
EM1D13
CANTXA
SCIRXDB
SPICLKC
GPIO72
15
0, 4, 8, 12
General-purpose input/output 70(3)
External memory interface 1 data line 14
CAN-A receive
2
5
6
O
SCI-B transmit data
SPI-C slave out, master in(2)
15
I/O
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 71
External memory interface 1 data line 13
CAN-A transmit
2
5
B17
B16
136
139
77
80
6
I
SCI-B receive data
SPI-C clock(2)
General-purpose input/output 72.(3) This is the factory
default boot mode select pin 1.
15
I/O
0, 4, 8, 12
I/O
EM1D12
CANTXB
SCITXDC
SPISTEC
GPIO73
2
I/O
O
External memory interface 1 data line 12
CAN-B transmit
5
6
O
SCI-C transmit data
15
I/O
I/O
I/O
O/Z
SPI-C slave transmit enable(2)
General-purpose input/output 73
External memory interface 1 data line 11
0, 4, 8, 12
EM1D11
XCLKOUT
2
3
External clock output. This pin outputs a divided-down
version of a chosen clock signal from within the device.
The clock signal is chosen using the
CLKSRCCTL3.XCLKOUTSEL bit field while the divide
ratio is chosen using the
A16
140
81
XCLKOUTDIVSEL.XCLKOUTDIV bit field.
CANRXB
SCIRXDC
GPIO74
EM1D10
GPIO75
EM1D9
5
I
CAN-B receive
6
I
SCI-C receive
0, 4, 8, 12
I/O
I/O
I/O
I/O
General-purpose input/output 74
External memory interface 1 data line 10
General-purpose input/output 75
External memory interface 1 data line 9
C17
D16
141
142
–
–
2
0, 4, 8, 12
2
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO76
EM1D8
SCITXDD
GPIO77
EM1D7
SCIRXDD
GPIO78
EM1D6
EQEP2A
GPIO79
EM1D5
EQEP2B
GPIO80
EM1D4
EQEP2S
GPIO81
EM1D3
EQEP2I
GPIO82
EM1D2
GPIO83
EM1D1
0, 4, 8, 12
I/O
I/O
O
General-purpose input/output 76
2
C16
A15
B15
C15
D15
A14
143
144
145
146
148
149
–
–
External memory interface 1 data line 8
SCI-D transmit data
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 77
External memory interface 1 data line 7
SCI-D receive data
2
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 78
External memory interface 1 data line 6
Enhanced QEP2 input A
2
82
–
6
0, 4, 8, 12
I/O
I/O
I
General-purpose input/output 79
External memory interface 1 data line 5
Enhanced QEP2 input B
2
6
0, 4, 8, 12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose input/output 80
External memory interface 1 data line 4
Enhanced QEP2 strobe
2
–
6
0, 4, 8, 12
General-purpose input/output 81
External memory interface 1 data line 3
Enhanced QEP2 index
2
–
6
0, 4, 8, 12
General-purpose input/output 82
External memory interface 1 data line 2
General-purpose input/output 83
External memory interface 1 data line 1
B14
C14
150
151
–
–
2
0, 4, 8, 12
2
General-purpose input/output 84. This is the factory
default boot mode select pin 0.
GPIO84
0, 4, 8, 12
I/O
SCITXDA
MDXB
5
O
O
SCI-A transmit data
A11
B11
154
155
85
86
6
McBSP-B transmit serial data
McBSP-A transmit serial data
General-purpose input/output 85
External memory interface 1 data line 0
SCI-A receive data
MDXA
15
O
GPIO85
EM1D0
0, 4, 8, 12
I/O
I/O
I
2
SCIRXDA
MDRB
5
6
I
McBSP-B receive serial data
McBSP-A receive serial data
General-purpose input/output 86
External memory interface 1 address line 13
External memory interface 1 column address strobe
SCI-B transmit data
MDRA
15
I
GPIO86
EM1A13
EM1CAS
SCITXDB
MCLKXB
MCLKXA
GPIO87
EM1A14
EM1RAS
SCIRXDB
MFSXB
MFSXA
0, 4, 8, 12
I/O
O
2
3
O
C11
D11
156
87
5
O
6
I/O
I/O
I/O
O
McBSP-B transmit clock
15
McBSP-A transmit clock
0, 4, 8, 12
General-purpose input/output 87
External memory interface 1 address line 14
External memory interface 1 row address strobe
SCI-B receive data
2
3
O
157
88
5
I
6
I/O
I/O
McBSP-B transmit frame synch
McBSP-A transmit frame synch
15
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO88
EM1A15
EM1DQM0
GPIO89
EM1A16
EM1DQM1
SCITXDC
GPIO90
EM1A17
EM1DQM2
SCIRXDC
GPIO91
EM1A18
EM1DQM3
SDAA
0, 4, 8, 12
I/O
O
General-purpose input/output 88
2
C6
170
–
External memory interface 1 address line 15
External memory interface 1 Input/output mask for byte 0
General-purpose input/output 89
3
O
0, 4, 8, 12
I/O
O
2
External memory interface 1 address line 16
External memory interface 1 Input/output mask for byte 1
SCI-C transmit data
D6
171
96
3
O
6
O
0, 4, 8, 12
I/O
O
General-purpose input/output 90
2
External memory interface 1 address line 17
External memory interface 1 Input/output mask for byte 2
SCI-C receive data
A5
B5
172
173
97
98
3
O
6
I
0, 4, 8, 12
I/O
O
General-purpose input/output 91
2
External memory interface 1 address line 18
External memory interface 1 Input/output mask for byte 3
I2C-A data open-drain bidirectional port
General-purpose input/output 92
3
O
6
I/OD
I/O
O
GPIO92
EM1A19
EM1BA1
SCLA
0, 4, 8, 12
2
External memory interface 1 address line 19
External memory interface 1 bank address 1
I2C-A clock open-drain bidirectional port
General-purpose input/output 93
A4
B4
174
175
99
–
3
O
6
I/OD
I/O
O
GPIO93
EM1BA0
SCITXDD
GPIO94
SCIRXDD
GPIO95
GPIO96
EM2DQM1
EQEP1A
GPIO97
EM2DQM0
EQEP1B
GPIO98
EM2A0
0, 4, 8, 12
3
External memory interface 1 bank address 0
SCI-D transmit data
6
O
0, 4, 8, 12
I/O
I
General-purpose input/output 94
A3
B3
176
–
–
–
6
SCI-D receive data
0, 4, 8, 12
I/O
I/O
O
General-purpose input/output 95
0, 4, 8, 12
General-purpose input/output 96
3
C3
A2
F1
G1
–
–
–
–
External memory interface 2 Input/output mask for byte 1
Enhanced QEP1 input A
5
I
0, 4, 8, 12
I/O
O
General-purpose input/output 97
3
External memory interface 2 Input/output mask for byte 0
Enhanced QEP1 input B
5
I
0, 4, 8, 12
I/O
O
General-purpose input/output 98
3
–
–
External memory interface 2 address line 0
Enhanced QEP1 strobe
EQEP1S
GPIO99
EM2A1
5
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 99
3
17
14
External memory interface 2 address line 1
Enhanced QEP1 index
EQEP1I
GPIO100
EM2A2
5
I/O
I/O
O
0, 4, 8, 12
General-purpose input/output 100
External memory interface 2 address line 2
Enhanced QEP2 input A
3
H1
H2
–
–
–
–
EQEP2A
SPISIMOC
GPIO101
EM2A3
5
I
6
I/O
I/O
O
SPI-C slave in, master out
0, 4, 8, 12
General-purpose input/output 101
External memory interface 2 address line 3
Enhanced QEP2 input B
3
5
6
EQEP2B
SPISOMIC
I
I/O
SPI-C slave out, master in
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO102
EM2A4
0, 4, 8, 12
I/O
O
General-purpose input/output 102
External memory interface 2 address line 4
Enhanced QEP2 strobe
3
H3
J1
–
–
–
–
EQEP2S
SPICLKC
GPIO103
EM2A5
5
I/O
I/O
I/O
O
6
SPI-C clock
0, 4, 8, 12
General-purpose input/output 103
External memory interface 2 address line 5
Enhanced QEP2 index
3
EQEP2I
SPISTEC
GPIO104
SDAA
5
I/O
I/O
I/O
I/OD
O
6
SPI-C slave transmit enable
0, 4, 8, 12
General-purpose input/output 104
I2C-A data open-drain bidirectional port
External memory interface 2 address line 6
Enhanced QEP3 input A
1
EM2A6
3
J2
J3
–
–
–
–
EQEP3A
SCITXDD
GPIO105
SCLA
5
I
6
O
SCI-D transmit data
0, 4, 8, 12
I/O
I/OD
O
General-purpose input/output 105
I2C-A clock open-drain bidirectional port
External memory interface 2 address line 7
Enhanced QEP3 input B
1
EM2A7
3
EQEP3B
SCIRXDD
GPIO106
EM2A8
5
I
6
I
SCI-D receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 106
External memory interface 2 address line 8
Enhanced QEP3 strobe
3
L2
L3
–
–
–
–
EQEP3S
SCITXDC
GPIO107
EM2A9
5
I/O
O
6
SCI-C transmit data
0, 4, 8, 12
I/O
O
General-purpose input/output 107
External memory interface 2 address line 9
Enhanced QEP3 index
3
EQEP3I
SCIRXDC
GPIO108
EM2A10
GPIO109
EM2A11
GPIO110
EM2WAIT
GPIO111
EM2BA0
GPIO112
EM2BA1
GPIO113
EM2CAS
GPIO114
EM2RAS
GPIO115
EM2CS0
GPIO116
EM2CS2
5
I/O
I
6
SCI-C receive data
0, 4, 8, 12
I/O
O
General-purpose input/output 108
External memory interface 2 address line 10
General-purpose input/output 109
External memory interface 2 address line 11
General-purpose input/output 110
L4
N2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
I
M2
M4
M3
N4
3
External memory interface 2 Asynchronous SRAM WAIT
General-purpose input/output 111
0, 4, 8, 12
I/O
O
3
External memory interface 2 bank address 0
General-purpose input/output 112
0, 4, 8, 12
I/O
O
3
External memory interface 2 bank address 1
General-purpose input/output 113
0, 4, 8, 12
I/O
O
3
External memory interface 2 column address strobe
General-purpose input/output 114
0, 4, 8, 12
I/O
O
N3
3
External memory interface 2 row address strobe
General-purpose input/output 115
0, 4, 8, 12
I/O
O
V12
W10
3
0, 4, 8, 12
3
External memory interface 2 chip select 0
General-purpose input/output 116
I/O
O
External memory interface 2 chip select 2
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO117
EM2SDCKE
GPIO118
EM2CLK
GPIO119
EM2RNW
GPIO120
EM2WE
0, 4, 8, 12
I/O
O
General-purpose input/output 117
External memory interface 2 SDRAM clock enable
General-purpose input/output 118
External memory interface 2 clock
General-purpose input/output 119
External memory interface 2 read not write
General-purpose input/output 120
External memory interface 2 write enable
USB external regulator power fault indicator
General-purpose input/output 121
External memory interface 2 output enable
USB external regulator enable
U12
T12
T15
–
–
–
–
–
–
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
0, 4, 8, 12
I/O
O
3
U15
W16
T8
–
–
–
–
–
–
–
–
–
–
–
–
USB0PFLT
GPIO121
EM2OE
15
I/O
I/O
O
0, 4, 8, 12
3
USB0EPEN
GPIO122
SPISIMOC
SD1_D1
15
I/O
I/O
I/O
I
0, 4, 8, 12
General-purpose input/output 122
SPI-C slave in, master out
6
7
Sigma-Delta 1 channel 1 data input
General-purpose input/output 123
SPI-C slave out, master in
GPIO123
SPISOMIC
SD1_C1
0, 4, 8, 12
I/O
I/O
I
6
U8
7
Sigma-Delta 1 channel 1 clock input
General-purpose input/output 124
SPI-C clock
GPIO124
SPICLKC
SD1_D2
0, 4, 8, 12
I/O
I/O
I
6
V8
7
Sigma-Delta 1 channel 2 data input
General-purpose input/output 125
SPI-C slave transmit enable
GPIO125
SPISTEC
SD1_C2
0, 4, 8, 12
I/O
I/O
I
6
T9
7
Sigma-Delta 1 channel 2 clock input
General-purpose input/output 126
Sigma-Delta 1 channel 3 data input
General-purpose input/output 127
Sigma-Delta 1 channel 3 clock input
General-purpose input/output 128
Sigma-Delta 1 channel 4 data input
General-purpose input/output 129
Sigma-Delta 1 channel 4 clock input
General-purpose input/output 130
Sigma-Delta 2 channel 1 data input
General-purpose input/output 131
Sigma-Delta 2 channel 1 clock input
General-purpose input/output 132
Sigma-Delta 2 channel 2 data input
GPIO126
SD1_D3
0, 4, 8, 12
I/O
I
U9
V9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
7
GPIO127
SD1_C3
0, 4, 8, 12
I/O
I
7
GPIO128
SD1_D4
0, 4, 8, 12
I/O
I
W9
7
GPIO129
SD1_C4
0, 4, 8, 12
I/O
I
T10
U10
V10
W18
7
GPIO130
SD2_D1
0, 4, 8, 12
I/O
I
7
GPIO131
SD2_C1
0, 4, 8, 12
7
I/O
I
GPIO132
SD2_D2
0, 4, 8, 12
7
I/O
I
GPIO133/AUXCLKIN
0, 4, 8, 12
I/O
General-purpose input/output 133. The AUXCLKIN
function of this GPIO pin could be used to provide a
single-ended 3.3-V level clock signal to the Auxiliary
Phase-Locked Loop (AUXPLL), whose output is used for
the USB module. The AUXCLKIN clock may also be used
for the CAN module.
G18
118
–
SD2_C2
7
I
Sigma-Delta 2 channel 2 clock input
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO134
SD2_D3
0, 4, 8, 12
I/O
I
General-purpose input/output 134
Sigma-Delta 2 channel 3 data input
General-purpose input/output 135
SCI-A transmit data
V18
–
–
7
GPIO135
SCITXDA
SD2_C3
0, 4, 8, 12
I/O
O
6
U18
–
–
7
I
Sigma-Delta 2 channel 3 clock input
General-purpose input/output 136
SCI-A receive data
GPIO136
SCIRXDA
SD2_D4
0, 4, 8, 12
I/O
I
6
T17
T18
–
–
–
–
7
I
Sigma-Delta 2 channel 4 data input
General-purpose input/output 137
SCI-B transmit data
GPIO137
SCITXDB
SD2_C4
0, 4, 8, 12
I/O
O
6
7
I
Sigma-Delta 2 channel 4 clock input
General-purpose input/output 138
SCI-B receive data
GPIO138
SCIRXDB
GPIO139
SCIRXDC
GPIO140
SCITXDC
GPIO141
SCIRXDD
GPIO142
SCITXDD
GPIO143
GPIO144
GPIO145
EPWM1A
GPIO146
EPWM1B
GPIO147
EPWM2A
GPIO148
EPWM2B
GPIO149
EPWM3A
GPIO150
EPWM3B
GPIO151
EPWM4A
GPIO152
EPWM4B
GPIO153
EPWM5A
GPIO154
EPWM5B
0, 4, 8, 12
I/O
I
T19
N19
M19
M18
L19
–
–
–
–
–
–
–
–
–
–
6
0, 4, 8, 12
I/O
I
General-purpose input/output 139
SCI-C receive data
6
0, 4, 8, 12
I/O
O
General-purpose input/output 140
SCI-C transmit data
6
0, 4, 8, 12
I/O
I
General-purpose input/output 141
SCI-D receive data
6
0, 4, 8, 12
I/O
O
General-purpose input/output 142
SCI-D transmit data
6
0, 4, 8, 12
F18
F17
–
–
–
–
I/O
I/O
I/O
O
General-purpose input/output 143
General-purpose input/output 144
General-purpose input/output 145
Enhanced PWM1 output A (HRPWM-capable)
General-purpose input/output 146
Enhanced PWM1 output B (HRPWM-capable)
General-purpose input/output 147
Enhanced PWM2 output A (HRPWM-capable)
General-purpose input/output 148
Enhanced PWM2 output B (HRPWM-capable)
General-purpose input/output 149
Enhanced PWM3 output A (HRPWM-capable)
General-purpose input/output 150
Enhanced PWM3 output B (HRPWM-capable)
General-purpose input/output 151
Enhanced PWM4 output A (HRPWM-capable)
General-purpose input/output 152
Enhanced PWM4 output B (HRPWM-capable)
General-purpose input/output 153
Enhanced PWM5 output A (HRPWM-capable)
General-purpose input/output 154
Enhanced PWM5 output B (HRPWM-capable)
0, 4, 8, 12
0, 4, 8, 12
E17
D18
D17
D14
A13
B13
C13
D13
A12
B12
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
1
I/O
O
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
GPIO155
EPWM6A
GPIO156
EPWM6B
GPIO157
EPWM7A
GPIO158
EPWM7B
GPIO159
EPWM8A
GPIO160
EPWM8B
GPIO161
EPWM9A
GPIO162
EPWM9B
GPIO163
EPWM10A
GPIO164
EPWM10B
GPIO165
EPWM11A
GPIO166
EPWM11B
GPIO167
EPWM12A
GPIO168
EPWM12B
0, 4, 8, 12
I/O
O
General-purpose input/output 155
Enhanced PWM6 output A (HRPWM-capable)
General-purpose input/output 156
Enhanced PWM6 output B (HRPWM-capable)
General-purpose input/output 157
Enhanced PWM7 output A (HRPWM-capable)
General-purpose input/output 158
Enhanced PWM7 output B (HRPWM-capable)
General-purpose input/output 159
Enhanced PWM8 output A (HRPWM-capable)
General-purpose input/output 160
Enhanced PWM8 output B (HRPWM-capable)
General-purpose input/output 161
Enhanced PWM9 output A
C12
D12
B10
C10
D10
B9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
1
0, 4, 8, 12
I/O
O
C9
1
0, 4, 8, 12
I/O
O
General-purpose input/output 162
Enhanced PWM9 output B
D9
1
0, 4, 8, 12
I/O
O
General-purpose input/output 163
Enhanced PWM10 output A
A8
1
0, 4, 8, 12
I/O
O
General-purpose input/output 164
Enhanced PWM10 output B
B8
1
0, 4, 8, 12
I/O
O
General-purpose input/output 165
Enhanced PWM11 output A
C5
1
0, 4, 8, 12
I/O
O
General-purpose input/output 166
Enhanced PWM11 output B
D5
1
0, 4, 8, 12
I/O
O
General-purpose input/output 167
Enhanced PWM12 output A
C4
1
0, 4, 8, 12
1
I/O
O
General-purpose input/output 168
Enhanced PWM12 output B
D4
RESET
Device Reset (in) and Watchdog Reset (out). The devices
have a built-in power-on reset (POR) circuit. During a
power-on condition, this pin is driven low by the device.
An external circuit may also drive this pin to assert a
device reset. This pin is also driven low by the MCU when
a watchdog reset or NMI watchdog reset occurs. During
watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. A
resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and VDDIO. If a capacitor is placed
between XRS and VSS for noise filtering, it should be
100 nF or smaller. These values will allow the watchdog
to properly drive the XRS pin to VOL within 512 OSCCLK
cycles when the watchdog reset is asserted. The output
buffer of this pin is an open drain with an internal pullup. If
this pin is driven by an external device, it should be done
using an open-drain device.
XRS
F19
124
69
I/OD
CLOCKS
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
X1
X2
NC
G19
J19
H4
123
121
–
68
66
I
On-chip crystal-oscillator output. A quartz crystal may be
connected across X1 and X2. If X2 is not used, it must be
left unconnected.
O
NO CONNECT
No connect. BGA ball is electrically open and not
connected to the die.
–
JTAG
TCK
TDI
V15
81
77
50
46
I
I
JTAG test clock with internal pullup (see Section 7.6)
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on a
rising edge of TCK.
W13
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) are shifted out of
TDO on the falling edge of TCK.(3)
TDO
TMS
W15
W14
78
80
47
49
O/Z
I
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained low
at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this
resistor should be based on drive strength of the
debugger pods applicable to the design. A 2.2-kΩ or
smaller resistor generally offers adequate protection. The
value of the resistor is application-specific. TI
TRST
V14
79
48
I
recommends that each target board be validated for
proper operation of the debugger and the application. This
pin has an internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
Internal voltage regulator enable with internal pulldown.
The internal VREG is not supported and must be
VREGENZ
J18
119
64
I
disabled. Connect VREGENZ to VDDIO
.
ANALOG, DIGITAL, AND I/O POWER
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
E9
E11
F9
16
21
61
76
117
126
137
153
158
169
–
16
39
45
63
71
78
84
89
95
–
F11
G14
G15
J14
J15
K5
1.2-V digital logic power pins. TI recommends placing a
decoupling capacitor near each VDD pin with a minimum
total capacitance of approximately 20 uF. The exact value
of the decoupling capacitance should be determined by
your system voltage regulation solution.
VDD
K6
P10
P13
R10
R13
R11
R12
P6
–
–
–
–
–
–
–
72
–
41
–
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin.
VDD3VFL
36
54
18
38
3.3-V analog power pins. Place a minimum 2.2-µF
decoupling capacitor to VSSA on each pin.
VDDA
R6
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
A9
A18
B1
3
11
2
10
15
40
44
55
62
72
79
83
90
94
–
15
20
26
62
68
75
82
88
91
99
106
114
116
127
138
147
152
159
168
–
E7
E10
E13
E16
F4
F7
F10
F13
F16
G4
3.3-V digital I/O power pins. Place a minimum 0.1-µF
decoupling capacitor on each pin. The exact value of the
decoupling capacitance should be determined by your
system voltage regulation solution.
G5
–
VDDIO
G6
–
H5
–
H6
–
L14
L15
M1
M5
M6
N14
N15
P9
–
–
–
–
–
–
–
–
–
–
–
R9
–
–
V19
W8
H16
–
–
–
–
120
65
Power pins for the 3.3-V on-chip crystal oscillator (X1 and
X2) and the two zero-pin internal oscillators (INTOSC).
Place a 0.1-μF (minimum) decoupling capacitor on each
pin.
VDDOSC
H17
125
70
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
A1
A10
A19
E5
E6
E8
E12
E14
E15
F5
F6
F8
F12
F14
F15
G16
G17
H8
H9
H10
H11
H12
H14
H15
J5
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
PWR
PAD
PWR
PAD
VSS
J6
J8
J9
J10
J11
J12
K8
K9
K10
K11
K12
K14
K15
L5
L6
L8
L9
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
TERMINAL
I/O/Z(1)
DESCRIPTION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
MUX
POSITION
NAME
L10
L11
L12
L18
M8
M9
M10
M11
M12
M14
M15
N1
Device ground. For Quad Flatpacks (QFPs), the
PowerPAD on the bottom of the package must be
soldered to the ground plane of the PCB.
N5
PWR
PAD
PWR
PAD
VSS
N6
P7
P8
P11
P12
P14
P15
R7
R8
R14
R15
W7
W19
H18
122
–
67
–
Crystal oscillator (X1 and X2) ground pin. When using an
external crystal, do not connect this pin to the board
ground. Instead, connect it to the ground reference of the
external crystal oscillator circuit.
If an external crystal is not used, this pin may be
connected to the board ground.
VSSOSC
H19
P1
P5
R5
V7
W1
34
52
–
17
35
36
–
Analog ground.
On the PZP package, pin 17 is double-bonded to VSSA
and VREFLOA. This pin must be connect to VSSA
VSSA
.
–
–
–
SPECIAL FUNCTIONS
ERRORSTS
U19
92
–
O
Error status output. This pin has an internal pulldown.
TEST PINS
Flash test pin 1. Reserved for TI. Must be left
unconnected.
FLT1
FLT2
W12
V13
73
74
42
43
I/O
I/O
Flash test pin 2. Reserved for TI. Must be left
unconnected.
(1) I = Input, O = Output, OD = Open Drain, Z = High Impedance
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
(2) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
(3) This pin has output impedance that can be as low as 22 Ω. This output could have fast edges and ringing depending on the system
PCB characteristics. If this is a concern, the user should take precautions such as adding a 39Ω (10% tolerance) series termination
resistor or implement some other termination scheme. It is also recommended that a system-level signal integrity analysis be
performed with the provided IBIS models. The termination is not required if this pin is used for input function.
6.3 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 6-1 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. In order to avoid
any floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 6-1 with pullups and pulldowns are always on and cannot be
disabled.
Table 6-1. Pins With Internal Pullup and Pulldown
RESET
( XRS = 0)
PIN
DEVICE BOOT
APPLICATION SOFTWARE
Pullup enable is application-
defined
GPIOx
Pullup disabled
Pullup disabled(1)
TRST
Pulldown active
Pullup active
TCK
TMS
Pullup active
TDI
Pullup active
XRS
Pullup active
VREGENZ
ERRORSTS
Other pins
Pulldown active
Pulldown active
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
6.4 Pin Multiplexing
6.4.1 GPIO Muxed Pins
Table 6-2 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can
be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn
register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux
selections. Columns not shown and blank cells are reserved GPIO Mux settings.
Table 6-2. GPIO Muxed Pins
GPIO Mux Selection(1) (2)
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO0
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
SDAA (I/OD)
SCLA (I/OD)
SDAB (I/OD)
SCLB (I/OD)
CANTXA (O)
CANRXA (I)
CANTXB (O)
CANRXB (I)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
SCITXDC (O)
SCIRXDC (I)
GPIO1
MFSRB (I/O)
MCLKRB (I/O)
GPIO2
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
GPIO3
OUTPUTXBAR2 (O)
MFSRA (I/O)
GPIO4
GPIO5
OUTPUTXBAR3 (O)
GPIO6
OUTPUTXBAR4 (O) EXTSYNCOUT (O)
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
GPIO7
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
OUTPUTXBAR5 (O)
ADCSOCAO (O)
OUTPUTXBAR6 (O)
ADCSOCBO (O)
OUTPUTXBAR7 (O)
MDXB (O)
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
UPP-WAIT (I/O)
UPP-START (I/O)
UPP-ENA (I/O)
UPP-D7 (I/O)
UPP-D6 (I/O)
UPP-D5 (I/O)
UPP-D4 (I/O)
UPP-D3 (I/O)
UPP-D2 (I/O)
UPP-D1 (I/O)
UPP-D0 (I/O)
UPP-CLK (I/O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
OUTPUTXBAR7 (O)
OUTPUTXBAR8 (O)
CANRXA (I)
EPWM9A (O)
EPWM9B (O)
EPWM10A (O)
EPWM10B (O)
EPWM11A (O)
EPWM11B (O)
EPWM12A (O)
EPWM12B (O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
SD2_C2 (I)
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
CANTXA (O)
CANTXB (O)
EQEP1B (I)
MDRA (I)
CANRXB (I)
EQEP1S (I/O)
EQEP1I (I/O)
MCLKXA (I/O)
MFSXA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
EM1CS4 (O)
EM1SDCKE (O)
EM1CLK (O)
EM1WE (O)
EM1CS0 (O)
EM1RNW (O)
EM1CS2 (O)
EM1CS3 (O)
EM1WAIT (I)
EM1OE (O)
EM1A0 (O)
SCITXDB (O)
SCIRXDB (I)
SPICLKB (I/O)
SPISTEB (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
EQEP3A (I)
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
SCIRXDA (I)
MDXB (O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
OUTPUTXBAR5 (O)
OUTPUTXBAR6 (O)
OUTPUTXBAR7 (O)
OUTPUTXBAR8 (O)
SCITXDA (O)
CANRXA (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
CANTXA (O)
SDAA (I/OD)
SCLA (I/OD)
OUTPUTXBAR1 (O)
SCIRXDA (I)
SDAB (I/OD)
SCLB (I/OD)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SDAB (I/OD)
SCLB (I/OD)
SDAA (I/OD)
SCITXDA (O)
OUTPUTXBAR2 (O)
SCITXDC (O)
SCIRXDC (I)
EM1A1 (O)
EM1A2 (O)
EM1A3 (O)
SCITXDA (O)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO90
GPIO91
GPIO92
GPIO93
SCLA (I/OD)
SCIRXDA (I)
EM1A4 (O)
EM1A5 (O)
EM1A6 (O)
SCIRXDD (I)
SCITXDD (O)
SCITXDA (O)
SCIRXDA (I)
EM1A7 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP1A (I)
EM1A8 (O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
SD2_C2 (I)
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
EM1A9 (O)
EM1A10 (O)
EM1A11 (O)
EM1A12 (O)
EM1D31 (I/O)
EM1D30 (I/O)
EM1D29 (I/O)
EM1D28 (I/O)
EM1D27 (I/O)
EM1D26 (I/O)
EM1D25 (I/O)
EM1D24 (I/O)
EM1D23 (I/O)
EM1D22 (I/O)
EM1D21 (I/O)
EM1D20 (I/O)
EM1D19 (I/O)
EM1D18 (I/O)
EM1D17 (I/O)
EM1D16 (I/O)
EM1D15 (I/O)
EM1D14 (I/O)
EM1D13 (I/O)
EM1D12 (I/O)
EM1D11 (I/O)
EM1D10 (I/O)
EM1D9 (I/O)
EM1D8 (I/O)
EM1D7 (I/O)
EM1D6 (I/O)
EM1D5 (I/O)
EM1D4 (I/O)
EM1D3 (I/O)
EM1D2 (I/O)
EM1D1 (I/O)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SCITXDB (O)
SCIRXDB (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
EM2D15 (I/O)
EM2D14 (I/O)
EM2D13 (I/O)
EM2D12 (I/O)
EM2D11 (I/O)
EM2D10 (I/O)
EM2D9 (I/O)
EM2D8 (I/O)
EM2D7 (I/O)
EM2D6 (I/O)
EM2D5 (I/O)
EM2D4 (I/O)
EM2D3 (I/O)
EM2D2 (I/O)
EM2D1 (I/O)
EM2D0 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
SCITXDC (O)
SCIRXDC (I)
SPICLKB (I/O)
SPISTEB (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
CANRXA (I)
EQEP2I (I/O)
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP3A (I)
SPISIMOA(3) (I/O)
SPISOMIA(3) (I/O)
SPICLKA(3) (I/O)
SPISTEA (3) (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
EQEP3B (I)
CANTXA (O)
SCIRXDA (I)
SPISIMOB(3) (I/O)
SPISOMIB(3) (I/O)
SPICLKB(3) (I/O)
SPISTEB (3) (I/O)
EQEP3S (I/O)
EQEP3I (I/O)
SCITXDA (O)
SDAB (I/OD)
SCLB (I/OD)
SCITXDB (O)
SCIRXDB (I)
SCITXDC (O)
SCIRXDC (I)
SPISIMOC(3) (I/O)
SPISOMIC(3) (I/O)
SPICLKC(3) (I/O)
SPISTEC (3) (I/O)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
XCLKOUT (O)
SCITXDD (O)
SCIRXDD (I)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
MDRB (I)
MDXA (O)
MDRA (I)
EM1D0 (I/O)
EM1A13 (O)
EM1A14 (O)
EM1A15 (O)
EM1A16 (O)
EM1A17 (O)
EM1A18 (O)
EM1A19 (O)
EM1CAS (O)
EM1RAS (O)
EM1DQM0 (O)
EM1DQM1 (O)
EM1DQM2 (O)
EM1DQM3 (O)
EM1BA1 (O)
MCLKXB (I/O)
MFSXB (I/O)
MCLKXA (I/O)
MFSXA (I/O)
SCITXDC (O)
SCIRXDC (I)
SDAA (I/OD)
SCLA (I/OD)
SCITXDD (O)
EM1BA0 (O)
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO94
SCIRXDD (I)
GPIO95
GPIO96
EM2DQM1 (O)
EM2DQM0 (O)
EM2A0 (O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
GPIO97
GPIO98
GPIO99
EM2A1 (O)
GPIO100
GPIO101
GPIO102
GPIO103
GPIO104
GPIO105
GPIO106
GPIO107
GPIO108
GPIO109
GPIO110
GPIO111
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO118
GPIO119
GPIO120
GPIO121
GPIO122
GPIO123
GPIO124
GPIO125
GPIO126
GPIO127
GPIO128
GPIO129
GPIO130
GPIO131
GPIO132
EM2A2 (O)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SCITXDD (O)
SCIRXDD (I)
EM2A3 (O)
EM2A4 (O)
EM2A5 (O)
SDAA (I/OD)
SCLA (I/OD)
EM2A6 (O)
EM2A7 (O)
EM2A8 (O)
SCITXDC (O)
SCIRXDC (I)
EM2A9 (O)
EM2A10 (O)
EM2A11 (O)
EM2WAIT (I)
EM2BA0 (O)
EM2BA1 (O)
EM2CAS (O)
EM2RAS (O)
EM2CS0 (O)
EM2CS2 (O)
EM2SDCKE (O)
EM2CLK (O)
EM2RNW (O)
EM2WE (O)
EM2OE (O)
USB0PFLT
USB0EPEN
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
GPIO133/
AUXCLKIN
SD2_C2 (I)
GPIO134
GPIO135
GPIO136
GPIO137
GPIO138
GPIO139
GPIO140
GPIO141
GPIO142
GPIO143
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
SCIRXDC (I)
SCITXDC (O)
SCIRXDD (I)
SCITXDD (O)
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table 6-2. GPIO Muxed Pins (continued)
GPIO Mux Selection(1) (2)
GPIO Index
0, 4, 8, 12
1
2
3
5
6
7
15
GPyGMUXn.
GPIOz =
00b, 01b,
10b, 11b
00b
01b
11b
GPyMUXn.
GPIOz =
00b
01b
10b
11b
01b
10b
11b
11b
GPIO144
GPIO145
GPIO146
GPIO147
GPIO148
GPIO149
GPIO150
GPIO151
GPIO152
GPIO153
GPIO154
GPIO155
GPIO156
GPIO157
GPIO158
GPIO159
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
GPIO166
GPIO167
GPIO168
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
EPWM9A (O)
EPWM9B (O)
EPWM10A (O)
EPWM10B (O)
EPWM11A (O)
EPWM11B (O)
EPWM12A (O)
EPWM12B (O)
(1) I = Input, O = Output, OD = Open Drain
(2) GPIO Index settings of 9, 10, 11, 13, and 14 are reserved.
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1
in SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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6.4.2 Input X-BAR
The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to
external interrupts (XINT) (see Figure 6-7). Table 6-3 shows the input X-BAR destinations. For details on
configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xS Microcontrollers
Technical Reference Manual .
INPUT7
INPUT8
INPUT9
INPUT10
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
GPIO0
GPIOx
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
INPUT11
INPUT12
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
XINT5
XINT4
XINT3
XINT2
XINT1
CPU PIE
CLA
TRIP4
TRIP5
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
TRIP6
ADCEXTSOC
ADC
EXTSYNCIN1
EXTSYNCIN2
ePWM and eCAP
Sync Chain
Output X-BAR
Figure 6-7. Input X-BAR
Table 6-3. Input X-BAR Destinations
INPUT
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
DESTINATIONS
EPWM[TZ1,TRIP1], EPWM X-BAR, Output X-BAR
EPWM[TZ2,TRIP2], EPWM X-BAR, Output X-BAR
EPWM[TZ3,TRIP3], EPWM X-BAR, Output X-BAR
XINT1, EPWM X-BAR, Output X-BAR
XINT2, ADCEXTSOC, EXTSYNCIN1, EPWM X-BAR, Output X-BAR
XINT3, EPWM[TRIP6], EXTSYNCIN2, EPWM X-BAR, Output X-BAR
ECAP1
ECAP2
ECAP3
ECAP4
ECAP5
ECAP6
XINT4
XINT5
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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6.4.3 Output X-BAR and ePWM X-BAR
The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM
X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the
Output X-BAR and ePWM X-BAR are shown in Figure 6-8. For details on the Output X-BAR and ePWM X-BAR,
see the Crossbar (X-BAR) chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual .
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
CMPSSx
CTRIPH
CTRIPL
(ePWM X-BAR only)
ePWM and eCAP
Sync
EXTSYNCOUT
OUTPUT1
OUTPUT2
ADCSOCAO
Select Ckt
OUTPUT3
OUTPUT4
ADCSOCAO
GPIO
Mux
Output
X-BAR
OUTPUT5
OUTPUT6
OUTPUT7
OUTPUT8
ADCSOCBO
Select Ckt
ADCSOCBO
ECAPxOUT
eCAPx
ADCx
EVT1
EVT2
EVT3
EVT4
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
All
ePWM
Modules
ePWM
X-BAR
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
Input X-Bar
OTHER DESTINATIONS
(see Input X-BAR)
X-BAR Flags
(shared)
FLT1.COMPH
FLT1.COMPL
SDFMx
FLT4.COMPH
FLT4.COMPL
Figure 6-8. Output X-BAR and ePWM X-BAR
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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6.4.4 USB Pin Muxing
Table 6-4 shows assignment of the alternate USB function mapping. These can be configured with the
GPBAMSEL register.
Table 6-4. Alternate USB Function
GPIO
GPBAMSEL SETTING
GPBAMSEL[10] = 1b
GPBAMSEL[11] = 1b
USB FUNCTION
USB0DM
GPIO42
GPIO43
USB0DP
6.4.5 High-Speed SPI Pin Muxing
The SPI module on this device has a high-speed mode. To achieve the highest possible speed, a special GPIO
configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI
when not in high-speed mode (HS_MODE = 0).
To select the mux options that enable the SPI high-speed mode, configure the GPyGMUX and GPyMUX
registers as shown in Table 6-5.
Table 6-5. GPIO Configuration for High-Speed SPI
GPIO
SPI SIGNAL
MUX CONFIGURATION
SPIA
SPIB
SPIC
GPIO58
GPIO59
GPIO60
GPIO61
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
GPBGMUX2[21:20]=11b
GPBMUX2[21:20]=11b
GPBMUX2[23:22]=11b
GPBMUX2[25:24]=11b
GPBMUX2[27:26]=11b
GPBGMUX2[23:22]=11b
GPBGMUX2[25:24]=11b
GPBGMUX2[27:26]=11b
GPIO63
GPIO64
GPIO65
GPIO66
SPISIMOB
SPISOMIB
SPICLKB
SPISTEB
GPBGMUX2[31:30]=11b
GPCGMUX1[1:0]=11b
GPCGMUX1[3:2]=11b
GPCGMUX1[5:4]=11b
GPBMUX2[31:30]=11b
GPCMUX1[1:0]=11b
GPCMUX1[3:2]=11b
GPCMUX1[5:4]=11b
GPIO69
GPIO70
GPIO71
GPIO72
SPISIMOC
SPISOMIC
SPICLKC
SPISTEC
GPCGMUX1[11:10]=11b
GPCGMUX1[13:12]=11b
GPCGMUX1[15:14]=11b
GPCGMUX1[17:16]=11b
GPCMUX1[11:10]=11b
GPCMUX1[13:12]=11b
GPCMUX1[15:14]=11b
GPCMUX1[17:16]=11b
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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6.5 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 6-6 lists acceptable conditioning for any
unused pins. When multiple options are listed in Table 6-6, any are acceptable. Pins not listed in Table 6-6 must
be connected according to Section 6.2.1.
Table 6-6. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
Analog
VREFHIx
Tie to VDDA
Tie to VSSA
VREFLOx
•
•
No Connect
Tie to VSSA
ADCINx
Digital
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
GPIOx
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
X1
X2
Tie to VSS
No Connect
•
•
No Connect
TCK
TDI
Pullup resistor
•
•
No Connect
Pullup resistor
TDO
No Connect
TMS
No Connect
TRST
Pulldown resistor (2.2 kΩ or smaller)
Tie to VDDIO. VREG is not supported.
No Connect
VREGENZ
ERRORSTS
FLT1
No Connect
FLT2
No Connect
Power and Ground
VDD
All VDD pins must be connected per Section 6.2.1.
If a dedicated analog supply is not used, tie to VDDIO
All VDDIO pins must be connected per Section 6.2.1.
Must be tied to VDDIO
VDDA
.
VDDIO
VDD3VFL
VDDOSC
VSS
Must be tied to VDDIO
All VSS pins must be connected to board ground.
VSSA
If a dedicated analog ground is not used, tie to VSS
.
VSSOSC
If an external crystal is not used, this pin may be connected to the board ground.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX(1) (2)
4.6
UNIT
VDDIO with respect to VSS
VDD3VFL with respect to VSS
Supply voltage
4.6
V
VDDOSC with respect to VSS
4.6
VDD with respect to VSS
1.5
Analog voltage
Input voltage
Output voltage
VDDA with respect to VSSA
4.6
V
V
V
VIN (3.3 V)
VO
4.6
4.6
Digital/analog input (per pin), IIK
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
–20
–20
20
20
(3)
)
Input clamp current
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
)
Output current
Digital output (per pin), IOUT
–20
–40
–40
–65
20
125
150
150
mA
°C
°C
°C
Free-Air temperature
Operating junction temperature
Storage temperature(4)
TA
TJ
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.2 ESD Ratings – Commercial
VALUE
TMS320F28379S, TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, and TMS320F23874S in 337-ball ZWT package
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
TMS320F28379S, TMS320F28378S, TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, and
TMS320F23874S in 176-pin PTP package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
TMS320F28379S, TMS320F28378S, TMS320F28376S, and TMS320F23874S in 100-pin PZP package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE
UNIT
TMS320F28377S and TMS320F28377S-Q1 in 337-ball ZWT package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner balls on 337-ball ZWT:
A1, A19, W1, W19
TMS320F28377S and TMS320F28377S-Q1 in 176-pin PTP package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
V
Corner pins on 176-pin PTP:
1, 44, 45, 88, 89, 132, 133, 176
TMS320F28377S and TMS320F28377S-Q1 and TMS320F28375S in 100-pin PZP package
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
All pins
±500
±750
Corner pins on 100-pin PZP:
1, 25, 26, 50, 51, 75, 76, 100
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.4 Recommended Operating Conditions
MIN
3.14
1.14
NOM
3.3
1.2
0
MAX
3.47
1.26
UNIT
(1)
Device supply voltage, I/O, VDDIO
V
V
V
V
V
Device supply voltage, VDD
Supply ground, VSS
Analog supply voltage, VDDA
Analog ground, VSSA
T version
3.14
3.3
0
3.47
–40
–40
–40
–40
105
125
150
125
Junction temperature, TJ
S version(2)
°C
°C
Q version (AEC Q100 qualification)(2)
Free-Air temperature, TA
Q version (AEC Q100 qualification)
(1) VDDIO, VDD3VFL, and VDDOSC should be maintained within 0.3 V of each other.
(2) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 7.5.1 shows the device current consumption at 200-MHz SYSCLK.
7.5.1 Device Current Consumption at 200-MHz SYSCLK
(1)
IDD
TYP(3)
IDDIO
TYP(3)
IDDA
TYP(3)
IDD3VFL
TYP(3)
MODE
TEST CONDITIONS
MAX(2)
MAX(2)
MAX(2)
MAX(2)
•
•
•
Code is running out of RAM.(4)
All I/O pins are left unconnected.
Peripherals not active have their
clocks disabled.
Operational
245 mA
400 mA
30 mA
13 mA
20 mA
33 mA
40 mA
•
•
FLASH is read and in active state.
XCLKOUT is enabled at SYSCLK/4.
•
•
•
CPU1 is in IDLE mode.
Flash is powered down.
XCLKOUT is turned off.
IDLE
80 mA
30 mA
215 mA
170 mA
3 mA
3 mA
10 mA
10 mA
10 µA
5 µA
150 µA
150 µA
10 µA
10 µA
150 µA
150 µA
•
•
•
CPU1 is in STANDBY mode.
Flash is powered down.
XCLKOUT is turned off.
STANDBY
•
•
•
CPU1 watchdog is running.
Flash is powered down.
XCLKOUT is turned off.
HALT
1.5 mA
300 µA
120 mA
5 mA
750 µA
750 µA
2 mA
2 mA
5 µA
5 µA
150 µA
75 µA
10 µA
1 µA
150 µA
50 µA
•
CPU1.M0 and CPU1.M1 RAMs are
in low-power data retention mode.
HIBERNATE
•
•
•
•
CPU1 is running from RAM.
All I/O pins are left unconnected.
Peripheral clocks are disabled.
Flash
154 mA
230 mA
3 mA
10 mA
10 µA
150 µA
45 mA
55 mA
Erase/Program(5)
CPU1 is performing Flash Erase and
Programming.
•
XCLKOUT is turned off.
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) MAX: Vmax, 125°C
(3) TYP: Vnom, 30°C
(4) The following is executed in a loop on CPU1:
•
All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to
I2C-B; McBSP-A to McBSP-B; USB
•
•
•
•
•
•
•
•
•
•
•
SDFM1 to SDFM4 active
ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
CPU TIMERs active
DMA does 32-bit burst transfers
CLA1 does multiply-accumulate tasks
All ADCs perform continuous conversion
All DACs ramp voltage up/down at 150 kHz
CMPSS1 to CMPSS8 active
VCU does complex multiply/accumulate with parallel load
TMU calculates a cosine
FPU does multiply/accumulate with parallel load
(5) Brownout events during flash programming can corrupt flash data. Programming environments using alternate power sources (such as
a USB programmer) must be capable of supplying the rated current for the device and other system components with sufficient margin
to avoid supply brownout conditions.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.5.2 Current Consumption Graphs
Figure 7-1 and Figure 7-2 are a typical representation of the relationship between frequency and current
consumption/power on the device. The operational test from Section 7.5.1 was run across frequency at Vmax and
high temperature. Actual results will vary based on the system implementation and conditions.
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
VDD
VDDIO
VDDA
VDD3VFL
Figure 7-1. Operational Current Versus Frequency
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
SYSCLK (MHz)
Power
Figure 7-2. Power Versus Frequency
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current
between TYP and MAX conditions can be seen in Figure 7-3. The current consumption in HALT mode is
primarily leakage current as there is no active switching if the internal oscillator has been powered down.
Figure 7-3 shows the typical leakage current across temperature. The device was placed into HALT mode under
nominal voltage conditions.
Figure 7-3. IDD Leakage Current Versus Temperature
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.5.3 Reducing Current Consumption
The F2837xS devices provide some methods to reduce the device current consumption:
•
Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during
idle periods in the application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Table 7-1 indicates
the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320F2837xS Microcontrollers Technical Reference Manual to ensure each module is powered down
as well.
•
Table 7-1. Current on VDD Supply by Various
Peripherals (at 200 MHz)
PERIPHERAL
MODULE(1) (2)
IDD CURRENT
REDUCTION (mA)
ADC(3)
3.3
3.3
1.4
1.4
0.3
0.6
2.9
0.6
2.9
2.6
4.5
1.7
1.7
1.3
1.6
0.9
2
CAN
CLA
CMPSS(3)
CPUTIMER
DAC(3)
DMA
eCAP
EMIF1
EMIF2
ePWM1 to ePWM4(4)
ePWM5 to ePWM12(4)
HRPWM(4)
I2C
McBSP
SCI
SDFM
SPI
uPP
0.5
7.3
23.8
USB and AUXPLL at 60 MHz
(1) At Vmax and 125°C.
(2) All peripherals are disabled upon reset. Use the PCLKCRx
register to individually enable peripherals. For peripherals with
multiple instances, the current quoted is for a single module.
(3) This number represents the current drawn by the digital portion
of the ADC, CMPSS, and DAC modules.
(4) The ePWM is at /2 of SYSCLK.
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7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
VOH
High-level output voltage
Low-level output voltage
V
0.4
V
0.2
VOL
IOH
IOL
High-level output source current for all output pins
Low-level output sink current for all output pins
GPIO0–GPIO7,
–4
mA
4
mA
GPIO42–GPIO43,
GPIO46–GPIO47
VDDIO * 0.7
VDDIO + 0.3
High-level input voltage
(3.3 V)
VIH
V
All other pins
2.0
VDDIO + 0.3
0.8
VIL
Low-level input voltage (3.3 V)
Input hysteresis
VSS – 0.3
V
VHYSTERESIS
150
120
mV
Digital inputs with
pulldown(1)
VDDIO = 3.3 V
VIN = VDDIO
Ipulldown
Ipullup
Input current
Input current
µA
µA
Digital inputs with pullup VDDIO = 3.3 V
150
enabled(1)
VIN = 0 V
Pullups disabled
0 V ≤ VIN ≤ VDDIO
Digital
2
Analog (except
ADCINB0 or DACOUTx)
2
ILEAK
Pin leakage
µA
0 V ≤ VIN ≤ VDDA
ADCINB0
DACOUTx
2
66
2
11(2)
CI
Input capacitance
pF
V
VDDIO-POR
VDDIO power-on reset voltage
2.3
(1) See Table 6-1 for a list of pins with a pullup or pulldown.
(2) The MAX input leakage shown on ADCINB0 is at high temperature.
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7.7 Thermal Resistance Characteristics
7.7.1 ZWT Package
°C/W(1)
8.3
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
11.6
21.5
19.0
17.8
16.5
0.2
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.3
150
250
500
0
PsiJT
Junction-to-package top
0.4
0.5
11.4
11.3
11.2
11.0
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.7.2 PTP Package
°C/W(1)
6.97
6.05
17.8
12.8
11.4
10.1
0.11
0.24
0.33
0.42
6.1
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
N/A
N/A
0
RΘJB
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
150
250
500
0
PsiJT
Junction-to-package top
5.5
150
250
500
PsiJB
Junction-to-board
5.4
5.3
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
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(2) lfm = linear feet per minute
7.7.3 PZP Package
°C/W(1)
4.3
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
N/A
N/A
0
RΘJB
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
5.9
RΘJA (High k PCB)
19.1
14.3
12.8
11.4
0.03
0.09
0.12
0.20
6.0
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
150
250
500
0
PsiJT
Junction-to-package top
5.5
150
250
500
PsiJB
Junction-to-board
5.5
5.3
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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7.9 System
7.9.1 Power Sequencing
7.9.1.1 Signal Pin Requirements
Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no
voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).
7.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
The 3.3-V supplies should be powered up together and kept within 0.3 V of each other during functional
operation.
7.9.1.3 VDD Requirements
The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to
supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO
.
VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is
off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered
Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xS MCUs Silicon Errata .
There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When the
flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal
current source can cause VDD to rise to approximately 1.3 V. There will be zero current load to the external
system VDD regulator while in this condition. This is not an issue for most regulators; however, if the system
voltage regulator requires a minimum load for proper operation, then an external 82Ω resistor can be added to
the board to ensure a minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain
Minimum Device Activity" advisory in the TMS320F2837xS MCUs Silicon Errata .
7.9.1.4 Supply Ramp Rate
The supplies should ramp to full rail within 10 ms. Section 7.9.1.4.1 shows the supply ramp rate.
7.9.1.4.1 Supply Ramp Rate
MIN
MAX
UNIT
Supply ramp rate
VDDIO, VDD, VDDA, VDD3VFL, VDDOSC with respect to VSS
330
105
V/s
7.9.1.5 Supply Supervision
An internal power-on-reset (POR) circuit keeps the I/Os in a high-impedance state during power up. External
supply voltage supervisors (SVS) can be used to monitor the voltage on the 3.3-V and 1.2-V rails and drive XRS
low when supplies are outside operational specifications.
Note
If the supply voltage is held near the POR threshold, then the device may drive periodic resets onto
the XRS pin.
7.9.2 Reset Timing
XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI watchdog reset also
drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. A capacitor should be
placed between XRS and VSS for noise filtering; the capacitance should be 100 nF or smaller. These values will
allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 7-4 shows the recommended reset circuit.
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VDDIO
2.2 kW – 10 kW
XRS
£100 nF
Figure 7-4. Reset Circuit
7.9.2.1 Reset Sources
The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and
HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xS Microcontrollers
Technical Reference Manual .
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRS low.
Use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRS; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP; for more details, see the TMS320F2837xS Microcontrollers Technical Reference Manual .
7.9.2.2 Reset Electrical Data and Timing
Section 7.9.2.2.1 shows the reset ( XRS) timing requirements. Section 7.9.2.2.2 shows the reset ( XRS)
switching characteristics. Figure 7-5 shows the power-on reset. Figure 7-6 shows the warm reset.
7.9.2.2.1 Reset ( XRS) Timing Requirements
MIN
1.5
MAX
UNIT
th(boot-mode)
Hold time for boot-mode pins
ms
All cases
3.2
Pulse duration, XRS low on
warm reset
tw(RSL2)
µs
Low-power modes used in
application and SYSCLKDIV > 16
3.2 * (SYSCLKDIV/16)
7.9.2.2.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
Pulse duration, XRS driven low by device after supplies are
tw(RSL1)
tw(WDRS)
µs
stable
Pulse duration, reset pulse generated by watchdog
512tc(OSCCLK)
cycles
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VDDIO, VDDA
(3.3 V)
VDD (1.2 V)
t
w(RSL1)
XRS(A)
Boot ROM
CPU
Execution
Phase
User-code
(B)
h(boot-mode)
t
User-code dependent
Boot-Mode
Pins
GPIO pins as input
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
GPIO pins as input (pullups are disabled)
I/O Pins
User-code dependent
A. The XRS pin can be driven externally by a supervisor or an external pullup resistor, see Section 6.2.1.
B. After reset from any source (see Section 7.9.2.1), the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-5. Power-on Reset
t
w(RSL2)
XRS
User Code
CPU
Execution
Phase
User Code
Boot ROM
Boot-ROM execution starts
(initiated by any reset source)
(A)
t
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
A. After reset from any source (see Section 7.9.2.1), the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode
pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based on user
environment and could be with or without PLL enabled.
Figure 7-6. Warm Reset
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7.9.3 Clock Specifications
7.9.3.1 Clock Sources
Table 7-2 lists four possible clock sources. Figure 7-7 provides an overview of the device's clocking system.
Table 7-2. Possible Reference Clock Sources
CLOCK SOURCE
MODULES CLOCKED
COMMENTS
INTOSC1
Can be used to provide clock for:
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Watchdog block
Main PLL
CPU-Timer 2
INTOSC2(1)
Can be used to provide clock for:
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
XTAL
Can be used to provide clock for:
External crystal or resonator connected between the X1 and X2 pins
or single-ended clock connected to the X1 pin.
•
•
•
Main PLL
Auxiliary PLL
CPU-Timer 2
AUXCLKIN
Can be used to provide clock for:
Single-ended 3.3-V level clock source. GPIO133/AUXCLKIN pin
should be used to provide the input clock.
•
•
Auxiliary PLL
CPU-Timer 2
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for both system PLL (OSCCLK) and auxiliary PLL (AUXOSCCLK).
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INTOSC1
WDCLK
To watchdog timer
CLKSRCCTL1
SYSPLLCTL1
SYSCLKDIVSEL
INTOSC2
X1(XTAL)
SYSCLK
Divider
To GS RAMs, GPIOs,
and NMIWDs
OSCCLK
PLLSYSCLK
System PLL
PLLRAWCLK
SYSCLK
CPU
CPU1.CPUCLK
CPU1.SYSCLK
To local memories
To ePIEs, LS RAMs,
CLA message RAMs,
and DCSMs
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
To peripherals
One per LSPCLK peripheral
PCLKCRx
LOSPCP
To SCIs, SPIs, and
McBSPs
PERx.LSPCLK
LSP
Divider
LSPCLK
One per ePWM
PCLKCRx
EPWMCLKDIV
/1
To ePWMs
EPWMCLK
PLLSYSCLK
/2
HRPWM
PCLKCRx
To HRPWMs
HRPWMCLK
One per CAN module
CLKSRCCTL2
CAN Bit Clock
To CANs
AUXCLKIN
CLKSRCCTL2
AUXPLLCTL1
AUXCLKDIVSEL
AUXCLK
Divider
AUXOSCCLK
AUXPLLCLK
To USB bit clock
Auxiliary PLL
AUXPLLRAWCLK
Figure 7-7. Clocking System
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7.9.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
7.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Section 7.9.3.2.1.1 shows the frequency requirements for the input clocks. Table 7-3 shows the crystal
equivalent series resistance requirements. Section 7.9.3.2.1.2 shows the X1 input level characteristics when
using an external clock source. Section 7.9.3.2.1.3 and Section 7.9.3.2.1.4 show the timing requirements for the
input clocks. Section 7.9.3.2.1.5 shows the PLL lock times for the Main PLL and the USB PLL.
7.9.3.2.1.1 Input Clock Frequency
MIN
10
2
MAX UNIT
20 MHz
25 MHz
60 MHz
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator
f(AUXI)
Frequency, AUXCLKIN, from external oscillator
2
7.9.3.2.1.2 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER
Valid low-level input voltage
Valid high-level input voltage
MIN
–0.3
MAX
UNIT
V
X1 VIL
X1 VIH
0.3 * VDDIO
VDDIO + 0.3
0.7 * VDDIO
V
7.9.3.2.1.3 X1 Timing Requirements
MIN
MAX UNIT
tf(X1)
Fall time, X1
6
6
ns
ns
tr(X1)
Rise time, X1
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
7.9.3.2.1.4 AUXCLKIN Timing Requirements
MIN
MAX UNIT
tf(AUXI)
Fall time, AUXCLKIN
6
6
ns
ns
tr(AUXI)
tw(AUXL)
tw(AUXH)
Rise time, AUXCLKIN
Pulse duration, AUXCLKIN low as a percentage of tc(XCI)
Pulse duration, AUXCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
7.9.3.2.1.5 PLL Lock Times
MIN
NOM
MAX UNIT
(1)
t(PLL)
t(USB)
Lock time, Main PLL (X1, from external oscillator)
Lock time, USB PLL (AUXCLKIN, from external oscillator)
50 µs + 2500 * tc(OSCCLK)
50 µs + 2500 * tc(OSCCLK)
µs
µs
(1)
(1) The PLL lock time here defines the typical time of execution for the PLL workaround as defined in the TMS320F2837xS MCUs Silicon
Errata . Cycle count includes code execution of the PLL initialization routine, which could vary depending on compiler optimizations
and flash wait states. TI recommends using the latest example software from C2000Ware for initializing the PLLs. For the system PLL,
see InitSysPll() or SysCtl_setClock(). For the auxillary PLL, see InitAuxPll() or SysCtl_setAuxClock().
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.9.3.2.2 Internal Clock Frequencies
Section 7.9.3.2.2.1 provides the clock frequencies for the internal clocks.
7.9.3.2.2.1 Internal Clock Frequencies
MIN
NOM
MAX
200(2)
500
UNIT
MHz
ns
f(SYSCLK)
Frequency, device (system) clock
Period, device (system) clock
2
tc(SYSCLK)
5(2)
Frequency, system PLL output (before SYSCLK
divider)
f(PLLRAWCLK)
120
120
400
400
MHz
MHz
Frequency, auxiliary PLL output (before AUXCLK
divider)
f(AUXPLLRAWCLK)
f(AUXPLL)
f(PLL)
Frequency, AUXPLLCLK
Frequency, PLLSYSCLK
Frequency, LSPCLK
Period, LSPCLK
2
2
60
60
200(2)
200(2)
500
MHz
MHz
MHz
ns
f(LSP)
2
tc(LSPCLK)
5(2)
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1)
f(OSCCLK)
See respective clock
MHz
f(EPWM)
Frequency, EPWMCLK(1)
100
100
MHz
MHz
f(HRPWM)
Frequency, HRPWMCLK
60
(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
(2) Using an external clock source. If INTOSC1 or INTOSC2 is used as the clock source, then the maximum frequency is 194 MHz and
the minimum period is 5.15 ns.
7.9.3.2.3 Output Clock Frequency and Switching Characteristics
Section 7.9.3.2.3.1 provides the frequency of the output clock. Section 7.9.3.2.3.2 shows the switching
characteristics of the output clock, XCLKOUT.
7.9.3.2.3.1 Output Clock Frequency
MIN
MAX UNIT
f(XCO)
Frequency, XCLKOUT
50 MHz
7.9.3.2.3.2 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1) (2)
MIN
MAX
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
5
5
tr(XCO)
Rise time, XCLKOUT
ns
tw(XCOL)
tw(XCOH)
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
ns
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
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7.9.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 7-8 shows
the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as
XTAL) and AUXCLKIN.
X1
X2
X1
X2
v
v
ssosc
ssosc
RESONATOR
CRYSTAL
R
C
C
L1
D
L2
X1
X2
GPIO133/AUXCLKIN
v
ssosc
NC
3.3V
VDD
CLK
3.3V
VDD
CLK
OUT
GND
OUT
GND
3.3V OSCILLATOR
3.3V OSCILLATOR
Figure 7-8. Connecting Input Clocks to a 2837xS Device
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.9.3.4 Crystal Oscillator
When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to
prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency
applications (10 MHz or greater), RD is generally not required. If a damping resistor is required, RD should be as
small as possible because the size of the resistance affects start-up time (smaller RD = faster start-up time). TI
recommends that the crystal manufacturer characterize the crystal with the application board. Section 7.9.3.4.1
shows the crystal oscillator parameters. Table 7-3 shows the crystal equivalent series resistance (ESR)
requirements. Section 7.9.3.4.2 shows the crystal oscillator electrical characteristics.
7.9.3.4.1 Crystal Oscillator Parameters
MIN
MAX UNIT
CL1, CL2
C0
Load capacitance
12
24
7
pF
pF
Crystal shunt capacitance
Table 7-3. Crystal Equivalent Series Resistance (ESR) Requirements
CRYSTAL FREQUENCY (MHz)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
(1) (2)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
(1) Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
(2) ESR = Negative Resistance/3
7.9.3.4.2 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ms
f = 20 MHz
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
Start-up time(1)
2
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
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7.9.3.5 Internal Oscillators
To reduce production board costs and application development time, all F2837xS devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled
at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the
backup clock source. INTOSC1 can also be manually configured as the system reference clock (OSCCLK).
Section 7.9.3.5.1 provides the electrical characteristics of the internal oscillators to determine if this module
meets the clocking requirements of the application.
Section 7.9.3.5.1 provides the electrical characteristics of the two internal oscillators.
Note
This oscillator cannot be used as the PLL source if the PLLSYSCLK is configured to frequencies
above 194 MHz.
7.9.3.5.1 Internal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10.0
MAX UNIT
f(INTOSC)
Frequency, INTOSC1 and INTOSC2
Frequency stability at room temperature
Frequency stability over VDD
Frequency stability
9.7
10.3
MHz
µs
30°C, Nominal VDD
30°C
±0.1%
±0.2%
f(INTOSC-STABILITY)
–3.0%
3.0%
20
f(INTOSC-ST)
Start-up and settling time
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7.9.4 Flash Parameters
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through
128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution
from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative
to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when
migrating from the previous generation of MCUs. Note that an extra wait state is automatically added when code
is fetched or data is read from Bank 1 (compared to that of Bank 0), even for prefetched data.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM),
which cannot be erased after it is programmed.
Table 7-4 shows the minimum required flash wait states at different frequencies. Section 7.9.4.1 shows the flash
parameters.
Table 7-4. Flash Wait States
CPUCLK (MHz)
MINIMUM WAIT STATES (1)
EXTERNAL OSCILLATOR OR CRYSTAL
150 < CPUCLK ≤ 200
INTOSC1 OR INTOSC2
145 < CPUCLK ≤ 194
97 < CPUCLK ≤ 145
48 < CPUCLK ≤ 97
CPUCLK ≤ 48
3
2
1
0
100 < CPUCLK ≤ 150
50 < CPUCLK ≤ 100
CPUCLK ≤ 50
(1) Minimum required FRDCNTL[RWAIT].
7.9.4.1 Flash Parameters
PARAMETER
MIN
TYP
MAX
300
UNIT
µs
128 data bits + 16 ECC bits
40
90
Program Time(1)
8KW sector
32KW sector
8KW sector
32KW sector
8KW sector
32KW sector
180
ms
360
25
720
ms
50
Erase Time(2) at < 25 cycles
Erase Time(2) at 20k cycles
ms
ms
30
55
105
110
4000
4000
20000
Nwec
Write/erase cycles
cycles
years
tretention
Data retention duration at TJ = 85°C
20
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
•
•
•
Code that uses flash API to program the flash
Flash API itself
Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum
Programming Word Size" advisory in the TMS320F2837xS MCUs Silicon Errata .
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7.9.5 Emulation/JTAG
The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be
pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1
signals that are present on 14-pin and 20-pin emulation headers. These signals should always be pulled up at
the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
See Figure 7-9 to see how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 7-10 shows
how to connect to the 20-pin header. The 20-pin JTAG header terminals EMU2, EMU3, and EMU4 are not used
and should be grounded.
The PD (Power Detect) terminal of the JTAG debug probe header should be connected to the board 3.3-V
supply. Header GND terminals should be connected to board ground. TDIS (Cable Disconnect Sense) should
also be connected to board ground. The JTAG clock should be looped from the header TCK output terminal back
to the RTCK input terminal of the header (to sense clock continuity by the JTAG debug probe). Header terminal
RESET is an open-drain output from the JTAG debug probe header that enables board components to be reset
through JTAG debug probe commands (available only through the 20-pin header).
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
for C28x in CCS.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
TRST
TMS
TDI
GND
2
1
3
TMS
TDI
TRST
TDIS
KEY
4
GND
100 W
MCU
5
6
3.3 V
PD
7
8
TDO
TCK
TDO
RTCK
TCK
GND
GND
GND
EMU1
9
10
12
14
11
13
4.7 kW
4.7 kW
3.3 V
EMU0
3.3 V
Figure 7-9. Connecting to the 14-Pin JTAG Header
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Distance between the header and the target
should be less than 6 inches (15.24 cm).
2.2 kW
TRST
GND
GND
2
1
TMS
TMS
TDI
TRST
TDIS
3
4
TDI
100 W
MCU
5
7
6
3.3V
PD
KEY
8
TDO
TCK
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
4.7 kW
4.7 kW
3.3 V
EMU0
RESET
EMU2
EMU4
3.3 V
open
drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
GND
Figure 7-10. Connecting to the 20-Pin JTAG Header
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7.9.5.1 JTAG Electrical Data and Timing
Section 7.9.5.1.1 lists the JTAG timing requirements. Section 7.9.5.1.2 lists the JTAG switching characteristics.
Figure 7-11 shows the JTAG timing.
7.9.5.1.1 JTAG Timing Requirements
NO.
1
MIN
66.66
26.66
26.66
13
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
ns
3
4
13
ns
7
ns
7
ns
7.9.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
25
ns
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
Figure 7-11. JTAG Timing
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7.9.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to a
GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input X-BAR
which is used to route signals from any GPIO input to different IP blocks such as the ADC(s), eCAP(s),
ePWM(s), and external interrupts. For more details, see the X-BAR chapter in the TMS320F2837xS
Microcontrollers Technical Reference Manual .
7.9.6.1 GPIO - Output Timing
Section 7.9.6.1.1 shows the general-purpose output switching characteristics. Figure 7-12 shows the general-
purpose output timing.
7.9.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
8(1)
8(1)
25
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
All GPIOs
All GPIOs
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
ns
MHz
(1) Rise time and fall time vary with load. These values assume a 40-pF load.
GPIO
tr(GPO)
tf(GPO)
Figure 7-12. General-Purpose Output Timing
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7.9.6.2 GPIO - Input Timing
Section 7.9.6.2.1 shows the general-purpose input timing requirements. Figure 7-13 shows the sampling mode.
7.9.6.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SYSCLK)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
tw(SP)
Sampling period
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 7-13. Sampling Mode
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7.9.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 ´ QUALPRD), if QUALPRD ¹ 0
(1)
Sampling frequency = SYSCLK, if QUALPRD = 0
(2)
Sampling period = SYSCLK cycle ´ 2 ´ QUALPRD, if QUALPRD ¹ 0
(3)
In Equation 1, Equation 2, and Equation 3, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
Figure 7-14 shows the general-purpose input timing.
SYSCLK
GPIOxn
tw(GPI)
Figure 7-14. General-Purpose Input Timing
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7.9.7 Interrupts
Figure 7-15 provides a high-level view of the interrupt architecture.
As shown in Figure 7-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto
any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt
groups, with 16 interrupts per group.
CPU1.TINT0
CPU1.TIMER0
CPU1.LPMINT
LPM Logic
CPU1.WAKEINT
CPU1.WD
NMI
CPU1.NMIWD
CPU1.WDINT
CPU1
INPUTXBAR4
CPU1.XINT1 Control
CPU1.XINT2 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT5 Control
GPIO0
GPIO1
...
...
GPIOx
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
INT1
to
INT12
Input
X-BAR
CPU1.
ePIE
CPU1.TINT1
CPU1.TINT2
CPU1.TIMER1
CPU1.TIMER2
INT13
INT14
Peripherals
Figure 7-15. External and ePIE Interrupt Sources
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7.9.7.1 External Interrupt (XINT) Electrical Data and Timing
Section 7.9.7.1.1 lists the external interrupt timing requirements. Section 7.9.7.1.2 lists the external interrupt
switching characteristics. Figure 7-16 shows the external interrupt timing.
7.9.7.1.1 External Interrupt Timing Requirements
MIN
2tc(SYSCLK)
MAX UNIT(1)
cycles
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(2)
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This assumes that the ISR is in a single-cycle memory.
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-16. External Interrupt Timing
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7.9.8 Low-Power Modes
This device has three clock-gating low-power modes and a special power-gating mode.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F2837xS Microcontrollers Technical Reference Manual .
7.9.8.1 Clock-Gating Low-Power Modes
IDLE, STANDBY, and HALT modes on this device are similar to those on other C28x devices. Table 7-5
describes the effect on the system when any of the clock-gating low-power modes are entered.
Table 7-5. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
CPU1 IDLE
CPU1 STANDBY
HALT
CPU1.CLKIN
Active
Active
Gated
Active
Gated
Gated
Gated
Gated
Gated
Gated
Gated
Gated
CPU1.SYSCLK
CPU1.CPUCLK
Clock to modules Connected to
PERx.SYSCLK
CPU1.WDCLK
AUXPLLCLK
PLL
Active
Active
Active
Active
Gated if CLKSRCCTL1.WDHALTI = 0
Gated
Powered
Powered
Software must power down PLL before entering
HALT
INTOSC1
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered down if CLKSRCCTL1.WDHALTI = 0
Software-Controlled
INTOSC2
Flash
X1/X2 Crystal Oscillator
Powered-Down
7.9.8.2 Power-Gating Low-Power Modes
HIBERNATE mode is the lowest power mode on this device. It is a global low-power mode that gates the supply
voltages to most of the system. HIBERNATE is essentially a controlled power-down with remote wakeup
capability, and can be used to save power during long periods of inactivity. Table 7-6 describes the effects on the
system when the HIBERNATE mode is entered.
Table 7-6. Effect of Power-Gating Low-Power Mode on the Device
MODULES/POWER DOMAINS
HIBERNATE
M0 and M1 memories
●
●
Remain on with memory retention if LPMCR.M0M1MODE = 0x00
Are off when LPMCR.M0M1MODE = 0x01
CPU1 digital peripherals
Dx, LSx, GSx memories
I/Os
Powered down
Power down, memory contents are lost
On with output state preserved
Enters Low-Power Mode
Oscillators, PLL, analog
peripherals, Flash
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7.9.8.3 Low-Power Mode Wakeup Timing
Section 7.9.8.3.1 shows the IDLE mode timing requirements, Section 7.9.8.3.2 shows the switching
characteristics, and Figure 7-17 shows the timing diagram for IDLE mode.
7.9.8.3.1 IDLE Mode Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT(1)
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.9.8.3.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume (2)
•
Wakeup from Flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
40tc(SYSCLK)
–
40tc(SYSCLK) + tw(WAKE)
(3)
td(WAKE-IDLE)
•
Wakeup from Flash
Flash module in sleep state
6700tc(SYSCLK)
cycles
–
6700tc(SYSCLK) (3) + tw(WAKE)
25tc(SYSCLK)
•
Wakeup from RAM
25tc(SYSCLK) + tw(WAKE)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is
needed before the wake-up signal could be asserted.
Figure 7-17. IDLE Entry and Exit Timing Diagram
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Section 7.9.8.3.3 shows the STANDBY mode timing requirements, Section 7.9.8.3.4 shows the switching
characteristics, and Figure 7-18 shows the timing diagram for STANDBY mode.
7.9.8.3.3 STANDBY Mode Timing Requirements
MIN
MAX
UNIT
QUALSTDBY = 0 | 2tc(OSCCLK)
QUALSTDBY > 0 |
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1)
(2 + QUALSTDBY)tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
7.9.8.3.4 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction executed to
XCLKOUT stop
td(IDLE-XCOS)
16tc(INTOSC1)
cycles
Delay time, external wake signal to
program execution resume(1)
•
Wakeup from flash
Flash module in active state
175tc(SYSCLK) + tw(WAKE-INT)
–
td(WAKE-STBY)
cycles
•
Wakeup from flash
Flash module in sleep state
6700tc(SYSCLK) (2) + tw(WAKE-
–
INT)
3tc(OSC) + 15tc(SYSCLK)
+
•
Wakeup from RAM
tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
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(C)
(F)
(A)
(B)
(D)(E)
(G)
Normal Execution
Device
Status
STANDBY
STANDBY
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-18. STANDBY Entry and Exit Timing Diagram
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Section 7.9.8.3.5 shows the HALT mode timing requirements, Section 7.9.8.3.6 shows the switching
characteristics, and Figure 7-19 shows the timing diagram for HALT mode.
7.9.8.3.5 HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal(1)
Pulse duration, XRS wake-up signal(1)
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on circuit/
layout external to the device. See Section 7.9.3.4.2 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 7.9.3.5 for toscst. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
7.9.8.3.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(IDLE-XCOS)
Delay time, IDLE instruction executed to XCLKOUT stop
16tc(INTOSC1)
cycles
Delay time, external wake signal end to CPU1 program
execution resume
•
•
•
Wakeup from flash
Flash module in active state
75tc(OSCCLK)
–
td(WAKE-HALT)
cycles
Wakeup from flash
Flash module in sleep state
(1)
17500tc(OSCCLK)
–
Wakeup from RAM
75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Microcontrollers Technical Reference Manual . This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
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(C)
(F)
(A)
(B)
(D)(E)
HALT
(G)
Device
Status
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible to keep the
zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing a 1 to
CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-
up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wakeup sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 7-19. HALT Entry and Exit Timing Diagram
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Section 7.9.8.3.7 shows the HIBERNATE mode timing requirements, Section 7.9.8.3.8 shows the switching
characteristics, and Figure 7-20 shows the timing diagram for HIBERNATE mode.
7.9.8.3.7 HIBERNATE Mode Timing Requirements
MIN
40
MAX
UNIT
µs
tw(HIBWAKE)
tw(WAKEXRS)
Pulse duration, HIBWAKE signal
Pulse duration, XRS wake-up signal
40
µs
7.9.8.3.8 HIBERNATE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
30tc(SYSCLK)
1.5
UNIT
cycles
ms
td(IDLE-XCOS)
td(WAKE-HIB)
Delay time, IDLE instruction executed to XCLKOUT stop
Delay time, external wake signal to lORestore function start
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(C)
(D)
(A)
(B)
(F)
(G)(H)
(I)(J)
(E)
CPU1 IDLE
Instruction
CPU1 HIB
config
Device Status Device Active
IoRestore() or Application Specific Operation
CPU1 Boot ROM
HIBERNATE
Td(WAKE-HIB)
GPIOHIBWAKEn,
XRSn
tw(HIBWAKEn),
tw(XRSn)
I/O Isolation
Bypassed &
Powered-Down
Application SpecificOperation
PLLs
Enabled
INTOSC1,INTOSC2,
X1/X2
Powering up
On
Powered Down
On
XCLKCOUT
Inactive
Application Specific Operation
td(IDLE-XCOS)
A. CPU1 does necessary application-specific context save to M0/M1 memories if required. This includes GPIO state if using I/O Isolation.
Configures the LPMCR register of CPU1 for HIBERNATE mode. Powers down Flash Pump/Bank, USB-PHY, CMPSS, DAC, and ADC
using their register configurations. The application should also power down the PLL and peripheral clocks before entering HIBERNATE.
B. IDLE instruction is executed to put the device into HIBERNATE mode.
C. The device is now in HIBERNATE mode. If configured, I/O isolation is turned on, M0 and M1 memories are retained. CPU1 is powered
down. Digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and Flash are in their software-controlled Low-
Power modes. Dx, LSx, and GSx memories are also powered down, and their memory contents lost.
D. A falling edge on the GPIOHIBWAKEn pin will drive the wakeup of the devices clock sources INTOSC1, INTOSC2, and X1/X2 OSC. The
wakeup source must keep the GPIOHIBWAKEn pin low long enough to ensure full power-up of these clock sources.
E. After the clock sources are powered up, the GPIOHIBWAKEn must be driven high to trigger the wakeup sequence of the remainder of
the device.
F. The BootROM will then begin to execute. The BootROM can distinguish a HIBERNATE wakeup by reading the CPU1.REC.HIBRESETn
bit. After the TI OTP trims are loaded, the BootROM code will branch to the user-defined IoRestore function if it has been configured.
G. At this point, the device is out of HIBERNATE mode, and the application may continue.
H. The IoRestore function is a user-defined function where the application may reconfigure GPIO states, disable I/O isolation, reconfigure
the PLL, restore peripheral configurations, or branch to application code. This is up to the application requirements.
I. If the application has not branched to application code, the BootROM will continue after completing IoRestore. It will disable I/O isolation
automatically if it was not taken care of inside of IoRestore.
J. BootROM will then boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and Peripheral Booting chapter of the
TMS320F2837xS Microcontrollers Technical Reference Manual for more information.
Figure 7-20. HIBERNATE Entry and Exit Timing Diagram
Note
1. If the IORESTOREADDR is configured as the default value, the BootROM will continue its
execution to boot as determined by the HIBBOOTMODE register. Refer to the ROM Code and
Peripheral Booting chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual
for more information.
2. The user may choose to disable I/O Isolation at any point in the IoRestore function. Regardless if
the user has disabled Isolation in the IoRestore function or if IoRestore is not defined, the
BootROM will automatically disable isolation before booting as determined by the HIBBOOTMODE
register.
7.9.9 External Memory Interface (EMIF)
The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous
memories (SRAM, NOR flash) or synchronous memory (SDRAM).
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7.9.9.1 Asynchronous Memory Support
The EMIF supports asynchronous memories:
•
•
SRAMs
NOR Flash memories
There is an external wait input that allows slower asynchronous memories to extend the memory access. The
EMIF module supports up to three chip selects ( EMIF_CS[4:2]). Each chip select has the following individually
programmable attributes:
•
•
•
•
•
•
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turnaround time
Extended wait option with programmable time-out
Select strobe option
7.9.9.2 Synchronous DRAM Support
The EMIF memory controller is compliant with the JESD21-C SDR SDRAMs that use a 32-bit or 16-bit data bus.
The EMIF has a single SDRAM chip select ( EMIF_CS[0]).
The address space of the EMIF, for the synchronous memory (SDRAM), lies beyond the 22-bit range of the
program address bus and can only be accessed through the data bus, which places a restriction on the C
compiler being able to work effectively on data in this space. Therefore, when using SDRAM, the user is advised
to copy data (using the DMA) from external memory to RAM before working on it. See the examples in
C2000Ware (C2000Ware for C2000 MCUs ) and the TMS320F2837xS Microcontrollers Technical Reference
Manual .
SDRAM configurations supported are:
•
•
•
•
•
One-bank, two-bank, and four-bank SDRAM devices
Devices with 8-, 9-, 10-, and 11-column addresses
CAS latency of two or three clock cycles
16-bit/32-bit data bus width
3.3-V LVCMOS interface
Additionally, the EMIF supports placing the SDRAM in self-refresh and power-down modes. Self-refresh mode
allows the SDRAM to be put in a low-power state while still retaining memory contents because the SDRAM will
continue to refresh itself even without clocks from the microcontroller. Power-down mode achieves even lower
power, except the microcontroller must periodically wake up and issue refreshes if data retention is required. The
EMIF module does not support mobile SDRAM devices.
On this device, the EMIF does not support burst access for SDRAM configurations. This means every access to
an external SDRAM device will have CAS latency.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.9.9.3 EMIF Electrical Data and Timing
7.9.9.3.1 Asynchronous RAM
Section 7.9.9.3.1.1 shows the EMIF asynchronous memory timing requirements. Section 7.9.9.3.1.2 shows the
EMIF asynchronous memory switching characteristics. Figure 7-21 through Figure 7-24 show the EMIF
asynchronous memory timing diagrams.
7.9.9.3.1.1 EMIF Asynchronous Memory Timing Requirements
NO.(1)
MIN
MAX
UNIT
Reads and Writes
E
EMIF clock period
tc(SYSCLK)
2E
ns
ns
Pulse duration, EMxWAIT assertion and
deassertion
2
tw(EM_WAIT)
Reads
12
13
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
Setup time, EMxD[y:0] valid before EMxOE high
Hold time, EMxD[y:0] valid after EMxOE high
15
0
ns
ns
Setup Time, EMxWAIT asserted before end of
Strobe Phase(2)
14
tsu(EMOEL-EMWAIT)
4E+20
ns
Writes
Setup Time, EMxWAIT asserted before end of
Strobe Phase(2)
28
tsu(EMWEL-EMWAIT)
4E+20
ns
(1) E = EMxCLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 7-22 and Figure 7-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
7.9.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics
NO.(1)
PARAMETER
MIN
MAX UNIT
(2) (3)
Reads and Writes
Reads
1
td(TURNAROUND)
Turn around time
(TA)*E–3
(TA)*E+2
ns
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E–3
(RS+RST+RH)*E+2
ns
ns
3
4
tc(EMRCYCLE)
(RS+RST+RH+
(EWC*16))*E–3
(RS+RST+RH+
(EWC*16))*E+2
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 0)
(RS)*E–3
–3
(RS)*E+2
2
ns
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 1)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 0)
(RH)*E–3
–3
(RH)*E
0
5
th(EMOEH-EMCEH)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 1)
Output setup time, EMxBA[y:0]
valid to EMxOE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E–3
(RH)*E–3
(RS)*E–3
(RH)*E–3
(RS)*E+2
(RH)*E
(RS)*E+2
(RH)*E
Output hold time, EMxOE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
to EMxOE low
Output hold time, EMxOE high to
EMxA[y:0] invalid
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NO.(1)
PARAMETER
MIN
MAX UNIT
(2) (3)
EMxOE active low width (EW = 0)
EMxOE active low width (EW = 1)
(RST)*E–1
(RST)*E+1
ns
ns
10
tw(EMOEL)
(RST+(EWC*16))*E–1
(RST+(EWC*16))*E+1
5E+15
Delay time from EMxWAIT
deasserted to EMxOE high
11
29
30
td(EMWAITH-EMOEH)
tsu(EMDQMV-EMOEL)
th(EMOEH-EMDQMIV)
4E+10
(RS)*E–3
(RH)*E–3
ns
ns
ns
Output setup time, EMxDQM[y:0]
valid to EMxOE low
(RS)*E+2
(RH)*E
Output hold time, EMxOE high to
EMxDQM[y:0] invalid
Writes
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E–3
(WS+WST+WH)*E+1
ns
ns
15
16
tc(EMWCYCLE)
(WS+WST+WH+
(EWC*16))*E–3
(WS+WST+WH+
(EWC*16))*E+1
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 0)
(WS)*E–3
–3
(WS)*E+1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 1)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0)
(WH)*E–3
–3
(WH)*E
17
th(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1)
0
Output setup time, EMxDQM[y:0]
valid to EMxWE low
18
19
20
21
22
23
tsu(EMDQMV-EMWEL)
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WS)*E–3
(WH)*E–3
(WST)*E–1
(WST+(EWC*16))*E–1
4E+10
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxDQM[y:0] invalid
Output setup time, EMxBA[y:0]
valid to EMxWE low
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxBA[y:0] invalid
Output setup time, EMxA[y:0] valid
to EMxWE low
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxA[y:0] invalid
EMxWE active low width
(EW = 0)
(WST)*E+1
(WST+(EWC*16))*E+1
5E+15
24
tw(EMWEL)
EMxWE active low width
(EW = 1)
Delay time from EMxWAIT
deasserted to EMxWE high
25
26
27
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Output setup time, EMxD[y:0] valid
to EMxWE low
(WS)*E–3
(WH)*E–3
(WS)*E+1
(WH)*E
Output hold time, EMxWE high to
EMxD[y:0] invalid
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xS Microcontrollers Technical Reference Manual for more
information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xS Microcontrollers Technical Reference Manual for more information.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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3
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
4
8
5
9
6
7
29
30
10
EMxOE
13
12
EMxD[y:0]
EMxWE
Figure 7-21. Asynchronous Memory Read Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
14
11
EMxOE
2
2
EMxWAIT
Asserted
Deasserted
Figure 7-22. EMxWAIT Read Timing Requirements
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
15
1
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxDQM[y:0]
16
18
20
22
17
19
21
24
23
EMxWE
EMxD[y:0]
EMxOE
27
26
Figure 7-23. Asynchronous Memory Write Timing
Extended Due to EMxWAIT
SETUP
STROBE
STROBE HOLD
EMxCS[y:2]
EMxBA[y:0]
EMxA[y:0]
EMxD[y:0]
28
25
EMxWE
2
2
EMxWAIT
Asserted
Deasserted
Figure 7-24. EMxWAIT Write Timing Requirements
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.9.9.3.2 Synchronous RAM
Section 7.9.9.3.2.1 shows the EMIF synchronous memory timing requirements. Section 7.9.9.3.2.2 shows the
EMIF synchronous memory switching characteristics. Figure 7-25 and Figure 7-26 show the synchronous
memory timing diagrams.
7.9.9.3.2.1 EMIF Synchronous Memory Timing Requirements
NO.
19
MIN
2
MAX UNIT
tsu(EMIFDV-EM_CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMxD[y:0] before EMxCLK rising
Input hold time, read data valid on EMxD[y:0] after EMxCLK rising
ns
ns
20
1.5
7.9.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
NO.
1
PARAMETER
MIN
10
3
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMxCLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMxCLK high or low
Delay time, EMxCLK rising to EMxCS[y:2] valid
Output hold time, EMxCLK rising to EMxCS[y:2] invalid
Delay time, EMxCLK rising to EMxDQM[y:0] valid
Output hold time, EMxCLK rising to EMxDQM[y:0] invalid
Delay time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] valid
Output hold time, EMxCLK rising to EMxA[y:0] and EMxBA[y:0] invalid
Delay time, EMxCLK rising to EMxD[y:0] valid
Output hold time, EMxCLK rising to EMxD[y:0] invalid
Delay time, EMxCLK rising to EMxRAS valid
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
8
8
8
8
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
1
1
1
1
1
1
1
1
5
6
7
8
toh(CLKH-AIV)
td(CLKH-DV)
9
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
td(CLKH-DHZ)
toh(CLKH-DLZ)
Output hold time, EMxCLK rising to EMxRAS invalid
Delay time, EMxCLK rising to EMxCAS valid
Output hold time, EMxCLK rising to EMxCAS invalid
Delay time, EMxCLK rising to EMxWE valid
Output hold time, EMxCLK rising to EMxWE invalid
Delay time, EMxCLK rising to EMxD[y:0] tri-stated
Output hold time, EMxCLK rising to EMxD[y:0] driving
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
BASIC SDRAM
1
READ OPERATION
2
2
EMxCLK
4
3
5
7
7
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
6
8
8
19
20
2 EM_CLK Delay
18
17
EMxD[y:0]
EMxRAS
11
12
13
14
EMxCAS
EMxWE
Figure 7-25. Basic SDRAM Read Operation
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMxCLK
EMxCS[y:2]
EMxDQM[y:0]
EMxBA[y:0]
EMxA[y:0]
3
5
7
7
4
6
8
8
9
10
EMxD[y:0]
EMxRAS
EMxCAS
EMxWE
11
12
13
15
16
Figure 7-26. Basic SDRAM Write Operation
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
7.10 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
The analog subsystem has the following features:
•
Flexible voltage references
– The ADCs are referenced to VREFHIx and VREFLOx pins.
•
VREFHIx pin voltage must be driven in externally.
The buffered DACs are referenced to VREFHIx and VSSA
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
The comparator DACs are referenced to VDDA and VSSA
– Alternately, these DACs can be referenced to the VDAC pin and VSSA
Flexible pin usage
•
•
•
•
.
.
.
.
– Buffered DAC and comparator subsystem functions multiplexed with ADC inputs
Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 7-27 shows the Analog Subsystem Block Diagram for the 337-ball ZWT package. Figure 7-28 shows the
Analog Subsystem Block Diagram for the 176-pin PTP package. Figure 7-29 shows the Analog Subsystem
Block Diagram for the 100-pin PZP package.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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VREFHIA
VREFHIA
VDAC
Comparator Subsystem 1
Digital
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA
VDAC
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DACREFSEL
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
VSSA
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADCINB5
ADC-B
16-bits
or
12-bits
(selectable)
CTRIP3L
Digital
Filter
12-bit
Buffered
DAC
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
VSSA
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
CMPIN5N/ADCINC5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
CMPIN5N
CMPIN6P
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADCIND5
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
Figure 7-27. Analog Subsystem Block Diagram (337-Ball ZWT)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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VREFHIA
VREFHIA VDAC
Comparator Subsystem 1
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
REFHI
CMPIN1P
CTRIP1H
Digital
Filter
DACREFSEL
VDDA or VDAC
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
ADC-A
16-bits
or
12-bits
(selectable)
CTRIP1L
Digital
Filter
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
VSSA
VSSA
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA VDAC
DACREFSEL
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DAC12
DAC12
REFLO
REFHI
12-bit
Buffered
DAC
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CMPIN2N
CMPIN3P
CTRIPOUT2L
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
0
1
2
3
4
5
6
7
8
CTRIP3H
VREFHIB VDAC
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT3H
DAC12
DAC12
ADC-B
16-bits
or
12-bits
(selectable)
12-bit
Buffered
DAC
CTRIP3L
Digital
Filter
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
9
10
11
12
13
14
15
Comparator Subsystem 4
Digital
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP4L
VREFLOB
VREFHIC
CMPIN4N
CMPIN5P
CTRIPOUT4L
Comparator Subsystem 5
Digital
0
1
CTRIP5H
CMPIN6P/ADCINC2
CMPIN6N/ADCINC3
CMPIN5P/ADCINC4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDDA or VDAC
Filter
CTRIPOUT5H
DAC12
DAC12
ADC-C
16-bits
or
12-bits
(selectable)
CTRIP5L
Digital
Filter
CTRIPOUT5L
VREFLOC
VREFLOC
Comparator Subsystem 6
Digital
CMPIN6P
CTRIP6H
VDDA or VDAC
Filter
CTRIPOUT6H
DAC12
DAC12
REFLO
REFHI
Digital
Filter
CTRIP6L
VREFLOC
VREFHID
CTRIPOUT6L
CMPIN6N
CMPIN7P
Comparator Subsystem 7
Digital
CMPIN7P/ADCIND0
CMPIN7N/ADCIND1
CMPIN8P/ADCIND2
CMPIN8N/ADCIND3
ADCIND4
0
1
2
3
4
5
6
7
8
CTRIP7H
VDDA or VDAC
Filter
CTRIPOUT7H
DAC12
DAC12
ADC-D
16-bits
or
12-bits
(selectable)
CTRIP7L
Digital
Filter
CTRIPOUT7L
CMPIN7N
CMPIN8P
VREFLOD
VREFLOD
9
10
11
12
13
14
15
Comparator Subsystem 8
Digital
CTRIP8H
VDDA or VDAC
Filter
CTRIPOUT8H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP8L
VREFLOD
CTRIPOUT8L
CMPIN8N
Figure 7-28. Analog Subsystem Block Diagram (176-Pin PTP)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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VREFHIA
VREFHIA VDAC
Comparator Subsystem 1
Digital
REFHI
DACOUTA/ADCINA0
DACOUTB/ADCINA1
CMPIN1P/ADCINA2
CMPIN1N/ADCINA3
CMPIN2P/ADCINA4
CMPIN2N/ADCINA5
0
1
2
3
4
5
6
7
8
CMPIN1P
CTRIP1H
DACREFSEL
VDDA or VDAC
Filter
CTRIPOUT1H
12-bit
Buffered
DAC
DAC12
DAC12
CTRIP1L
Digital
Filter
ADC-A
CMPIN1N
CMPIN2P
CTRIPOUT1L
VREFLOA
VREFLOA
VSSA
12-bits
9
10
11
12
13
14
15
Comparator Subsystem 2
Digital
VREFHIA VDAC
DACREFSEL
CTRIP2H
VDDA or VDAC
Filter
CTRIPOUT2H
TEMP SENSOR
CMPIN4P/ADCIN14
CMPIN4N/ADCIN15
DAC12
DAC12
12-bit
Buffered
DAC
REFLO
REFHI
CTRIP2L
Digital
Filter
VREFLOA
VREFHIB
CTRIPOUT2L
CMPIN2N
CMPIN3P
VSSA
Comparator Subsystem 3
Digital
VDAC/ADCINB0
DACOUTC/ADCINB1
CMPIN3P/ADCINB2
CMPIN3N/ADCINB3
ADCINB4
0
1
2
3
4
5
6
7
8
VREFHIB
VDAC
CTRIP3H
VDDA or VDAC
Filter
CTRIPOUT3H
DACREFSEL
DAC12
DAC12
ADCINB5
12-bit
Buffered
DAC
CTRIP3L
Digital
Filter
ADC-B
CMPIN3N
CMPIN4P
CTRIPOUT3L
VREFLOB
VREFLOB
12-bits
9
VSSA
10
11
12
13
14
15
Comparator Subsystem 4
Digital
CTRIP4H
VDDA or VDAC
Filter
CTRIPOUT4H
DAC12
DAC12
REFLO
Digital
Filter
CTRIP4L
VREFLOB
CTRIPOUT4L
CMPIN4N
Figure 7-29. Analog Subsystem Block Diagram (100-Pin PZP)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.1 Analog-to-Digital Converter (ADC)
The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either
16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling. The ADC wrapper is
start-of-conversion (SOC) based [see the SOC Principle of Operation section of the TMS320F2837xS
Microcontrollers Technical Reference Manual .
Each ADC has the following features:
•
•
•
•
•
•
•
•
Selectable resolution of 16 bits or 12 bits
Ratiometric external reference set by VREFHI and VREFLO
Differential signal conversions (16-bit mode only)
Single-ended signal conversions (12-bit mode only)
Input multiplexer with up to 16 channels (single-ended) or 8 channels (differential)
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
– Software immediate start
– All ePWMs
– GPIO XINT2
– CPU timers
– ADCINT1 or 2
•
•
•
Four flexible PIE interrupts
Burst mode
Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Figure 7-30 shows the ADC module block diagram.
Analog to Digital Core
Analog to Digital Wrapper Logic
SIGNALMODE
SIGNALMODE
RESOLUTION
RESOLUTION
ADCSOC
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC
Arbitration
& Control
ACQPS
CHSEL
0
1
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
2
3
4
5
ADCCOUNTER
6
TRIGGER[15:0]
VIN+
7
DOUT
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
S/H Circuit
Converter
RESULT
-
+
ADCPPBxOFFCAL
S
saturate
+
ADCPPBxOFFREF
ADCPPBxRESULT
-
S
ADCEVT
VREFHI
Event
Logic
CONFIG
ADCEVTINT
VREFLO
Reference Voltage Levels
Post Processing Block (1-4)
Interrupt Block (1-4)
ADCINT1-4
Figure 7-30. ADC Module Block Diagram
7.10.1.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are controlled by each ADC
module. Table 7-7 summarizes the basic ADC options and their level of configurability.
Table 7-7. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
By the module(1)
Clock
Resolution
Signal mode
By the module(1)
By the module
Reference voltage source
Trigger source
Not configurable (external reference only)
By the SOC(1)
Converted channel
Acquisition window duration
EOC location
By the SOC
By the SOC(1)
By the module
Burst mode
By the module(1)
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F2837xS Microcontrollers Technical Reference Manual .
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.1.1.1 Signal Mode
The ADC supports two signal modes: single-ended and differential. In single-ended mode, the input voltage to
the converter is sampled through a single pin (ADCINx), referenced to VREFLO. In differential signaling mode,
the input voltage to the converter is sampled through a pair of input pins, one of which is the positive input
(ADCINxP) and the other is the negative input (ADCINxN). The actual input voltage is the difference between the
two (ADCINxP – ADCINxN). Figure 7-31 shows the differential signaling mode. Figure 7-32 shows the single-
ended signaling mode.
Pin Voltages
VREFHI
VREFHI
ADCINxP
VREFHI/2
ADCINxN
ADCINxP
ADCINxN
ADC
VREFLO
VREFLO
(VSSA)
Input Common Mode
Effective Input Voltage
Digital Output
VREFHI
Vin Common Mode
VREFHI/2 50mV
VREFLO
(VSSA)
+VREFHI
ADC Vin
0
-VREFHI
2n - 1
ADC Vin
0
Figure 7-31. Differential Signaling Mode
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 7-32. Single-ended Signaling Mode
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.10.1.2 ADC Electrical Data and Timing
Section 7.10.1.2.1 shows the ADC operating conditions for 16-bit differential mode. Section 7.10.1.2.2 shows the
ADC characteristics for 16-bit differential mode. Section 7.10.1.2.3 shows the ADC operating conditions for 12-
bit single-ended mode. Section 7.10.1.2.4 shows the ADC characteristics for 12-bit single-ended mode. Section
7.10.1.2.5 shows the ADCEXTSOC timing requirements.
7.10.1.2.1 ADC Operating Conditions (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
ns
ADCCLK (derived from PERx.SYSCLK)
5
320
50
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)
VREFHI
2.4
2.5 or 3.0
0
VDDA
VSSA
V
VREFLO
VSSA
V
VREFHI – VREFLO
2.4
VDDA
V
ADC input conversion range
ADC input signal common mode voltage(2) (3)
VREFLO
VREFCM – 50
VREFHI
V
VREFCM
VREFCM + 50
mV
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) VREFCM = (VREFHI + VREFLO)/2
(3) The VREFCM requirements will not be met if the negative ADC input pin is connected to VSSA or VREFLO
.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF
.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
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UNIT
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
7.10.1.2.2 ADC Characteristics (16-Bit Differential Mode)
over recommended operating conditions (unless otherwise noted)(6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ADC conversion cycles(1)
29.6
31 ADCCLKs
Power-up time (after setting
ADCPWDNZ to first conversion)
500
µs
Gain error
–64
–16
±9
±9
64
16
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
dB
Offset error(2)
Channel-to-channel gain error
Channel-to-channel offset error
ADC-to-ADC gain error
ADC-to-ADC offset error
DNL(3)
±6
±3
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±6
±3
> –1
–3
±0.5
±1.5
87.6
–93.5
95.4
86.6
1
3
INL
SNR(4) (11)
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
VREFHI = 2.5 V, fin = 10 kHz
THD(4) (11)
dB
SFDR(4) (11)
dB
SINAD(4) (11)
dB
VREFHI = 2.5 V, fin = 10 kHz,
single ADC(7)
14.1
14.1
VREFHI = 2.5 V, fin = 10 kHz,
synchronous ADCs(8)
ENOB(4) (11)
bits
VREFHI = 2.5 V, fin = 10 kHz,
asynchronous ADCs(9)
Not
supported
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
PSRR
PSRR
77
74
dB
dB
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
CMRR
DC to 1 MHz
60
dB
µA
VREFHI input current
190
VREFHI = 2.5 V, synchronous ADCs(8)
VREFHI = 2.5 V, asynchronous ADCs(9)
–2
2
ADC-to-ADC isolation(11) (5) (10)
LSBs
Not
supported
(1) See Section 7.10.1.2.7.
(2) Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM
.
(3) No missing codes.
(4) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(5) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(6) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(7) One ADC operating while all other ADCs are idle.
(8) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
(9) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(10) Value based on characterization.
(11) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
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7.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)
MIN
5
TYP
MAX
UNIT
MHz
ns
V
ADCCLK (derived from PERx.SYSCLK)
50
Sample window duration (set by ACQPS and PERx.SYSCLK)(1)
75
VREFHI
2.4
2.5 or 3.0
0
VDDA
VSSA
VREFLO
VSSA
2.4
V
VREFHI – VREFLO
ADC input conversion range
VDDA
V
VREFLO
VREFHI
V
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC or
DAC inputs using the same VREF
.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
7.10.1.2.4 ADC Characteristics (12-Bit Single-Ended Mode)
over recommended operating conditions (unless otherwise noted)(5)
PARAMETER
ADC conversion cycles(1)
Power-up time
TEST CONDITIONS
MIN
TYP
MAX
10.1
11 ADCCLKs
500
µs
Gain error
–5
–4
±3
±2
5
4
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
dB
Offset error
Channel-to-channel gain error
Channel-to-channel offset error
ADC-to-ADC gain error
ADC-to-ADC offset error
DNL(2)
±4
±2
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
±4
±2
> –1
–2
±0.5
±1.0
68.8
–78.4
79.2
68.4
1
2
INL
SNR(3) (10)
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
VREFHI = 2.5 V, fin = 100 kHz
THD(3) (10)
dB
SFDR(3) (10)
dB
SINAD(3) (10)
dB
VREFHI = 2.5 V, fin = 100 kHz,
single ADC(6), all packages
11.1
11.1
VREFHI = 2.5 V, fin = 100 kHz,
synchronous ADCs(7), all packages
VREFHI = 2.5 V, fin = 100 kHz,
Not
supported
asynchronous ADCs(8)
100-pin PZP package
,
ENOB(3) (10)
bits
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8)
176-pin PTP package
,
9.7
VREFHI = 2.5 V, fin = 100 kHz,
asynchronous ADCs(8)
,
10.9
337-ball ZWT package
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
PSRR
PSRR
60
57
dB
dB
VDDA = 3.3-V DC + 200 mV
Sine at 800 kHz
VREFHI = 2.5 V, synchronous ADCs(7), all
packages
–1
1
VREFHI = 2.5 V, asynchronous ADCs(8)
100-pin PZP package
,
,
,
Not
supported
ADC-to-ADC isolation(10) (4) (9)
LSBs
µA
VREFHI = 2.5 V, asynchronous ADCs(8)
176-pin PTP package
–9
–2
9
2
VREFHI = 2.5 V, asynchronous ADCs(8)
337-ball ZWT package
VREFHI input current
130
(1) See Section 7.10.1.2.7.
(2) No missing codes.
(3) AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source
for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip
Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.
(4) Maximum DC code deviation due to operation of multiple ADCs simultaneously.
(5) Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with
VREFHI = 2.5 V and VREFLO = 0 V.
(6) One ADC operating while all other ADCs are idle.
(7) All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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(8) Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.
(9) Value based on characterization.
(10) I/O activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
7.10.1.2.5 ADCEXTSOC Timing Requirements
MIN(1)
2tc(SYSCLK)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.10.1.2.6 ADC Input Models
Note
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA
.
For differential operation, the ADC input characteristics are given by Section 7.10.1.2.6.1 and Figure 7-33.
7.10.1.2.6.1 Differential Input Model Parameters
DESCRIPTION
Parasitic input capacitance
VALUE (16-BIT MODE)
See Table 7-8
700 Ω
Cp
Ron
Ch
Rs
Sampling switch resistance
Sampling capacitor
16.5 pF
Nominal source impedance
50 Ω
ADC
ADCINxP
Rs
Cp
Cp
Ron
Switch
Switch
AC
Ch
VSSA
Ron
ADCINxN
Rs
Figure 7-33. Differential Input Model
For single-ended operation, the ADC input characteristics are given by Section 7.10.1.2.6.2 Figure 7-34and .
7.10.1.2.6.2 Single-Ended Input Model Parameters
DESCRIPTION
Parasitic input capacitance
VALUE (12-BIT MODE)
See Table 7-8
425 Ω
Cp
Ron
Ch
Rs
Sampling switch resistance
Sampling capacitor
14.5 pF
Nominal source impedance
50 Ω
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
Figure 7-34. Single-Ended Input Model
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Table 7-8shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately
1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs.
Table 7-8. Per-Channel Parasitic Capacitance
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
ADCINA0
ADCINA1
ADCINA2
ADCINA3
ADCINA4
ADCINA5
ADCINB01
ADCINB1
ADCINB2
ADCINB3
ADCINB4
ADCINB5
ADCINC2
ADCINC3
ADCINC4
ADCINC5
ADCIND0
ADCIND1
ADCIND2
ADCIND3
ADCIND4
ADCIND5
ADCIN14
ADCIN15
12.9
10.3
5.9
6.3
5.9
6.3
117.0
10.6
5.9
6.2
5.2
5.1
5.5
5.8
5.0
5.3
5.3
5.7
5.3
5.6
4.3
4.3
8.6
9.0
N/A
N/A
7.3
8.8
7.3
8.8
N/A
N/A
7.3
8.7
N/A
N/A
6.9
8.3
6.4
7.8
6.7
8.2
6.7
8.1
N/A
N/A
10.0
11.5
1. The increased capacitance is due to VDAC functionality.
These input models should be used along with actual signal source impedance to determine the acquisition
window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2837xS
Microcontrollers Technical Reference Manual for more information.
The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will require
assuming that Ch could start the S+H window completely charged to VREFHI or completely discharged to VREFLO
.
When the ADC transitions from an odd-numbered channel to an even-numbered channel, or vice-versa, the
actual initial voltage on Ch will be close to being completely discharged to VREFLO. For even-to-even or odd-to-
odd channel transitions, the initial voltage on Ch will be close to the voltage of the previously converted channel.
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7.10.1.2.7 ADC Timing Diagrams
Section 7.10.1.2.7.1 lists the ADC timings in 12-bit mode (SYSCLK cycles). Section 7.10.1.2.7.2 lists the ADC
timings in 16-bit mode. Figure 7-35 and Figure 7-36 show the ADC conversion timings for two SOCs given the
following assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 7-9 lists the descriptions of the ADC timing parameters that are in Figure 7-35 and Figure 7-36 .
Table 7-9. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the next ADC conversion S+H window can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
tINT
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
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7.10.1.2.7.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
ADCCLK
CYCLES
ADCCLK PRESCALE
ADCCTL2
SYSCLK CYCLES
RATIO
(1)
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
[PRESCALE]
ADCCLK:SYSCLK
0
1
1
1.5
2
11
13
1
11
11.0
Invalid
2
21
26
31
36
41
46
51
56
61
66
71
76
81
86
23
28
34
39
44
49
55
60
65
70
76
81
86
91
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21
26
31
36
41
46
51
56
61
66
71
76
81
86
10.5
10.4
10.3
10.3
10.3
10.2
10.2
10.2
10.2
10.2
10.1
10.1
10.1
10.1
3
2.5
3
4
5
3.5
4
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xS MCUs Silicon Errata .
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADC S+H
Sample n+1
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
Sample n
(old data)
(old data)
Sample n+1
tSH
tLAT
tEOC
tINT
Figure 7-35. ADC Timings for 12-Bit Mode
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.1.2.7.2 ADC Timings in 16-Bit Mode
ADCCLK
CYCLES
ADCCLK PRESCALE
ADCCTL2
SYSCLK CYCLES
RATIO
(1)
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
[PRESCALE]
ADCCLK:SYSCLK
0
1
1
1.5
2
31
32
1
31
31.0
Invalid
2
60
61
75
91
1
1
1
1
1
1
1
1
1
1
1
1
1
1
60
30.0
30.0
30.0
29.7
29.8
29.8
29.8
29.6
29.7
29.7
29.7
29.6
29.6
29.6
3
2.5
3
75
75
4
90
90
5
3.5
4
104
119
134
149
163
178
193
208
222
237
252
106
120
134
150
165
179
193
209
224
238
252
104
119
134
149
163
178
193
208
222
237
252
6
7
4.5
5
8
9
5.5
6
10
11
12
13
14
15
6.5
7
7.5
8
8.5
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F2837xS MCUs Silicon Errata .
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Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
ADC S+H
Sample n+1
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
ADCRESULT1
ADCINTFLG.ADCINTx
Sample n
(old data)
(old data)
Sample n+1
tSH
tLAT
tEOC
tINT
Figure 7-36. ADC Timings for 16-Bit Mode
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.1.3 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor is
sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in Section 7.10.1.3.1.
7.10.1.3.1 Temperature Sensor Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
±15
500
MAX
UNIT
°C
Temperature accuracy
Start-up time (TSNSCTL[ENABLE] to sampling temperature sensor)
ADC acquisition time
µs
700
ns
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7.10.2 Comparator Subsystem (CMPSS)
Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two
digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these
inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input
of the CMPSS comparators. CMPINxN can be used instead of the DAC output to drive the negative comparator
inputs. There are two comparators, and therefore two outputs from the CMPSS module, which are connected to
the input of a digital filter module before being passed on to the Comparator TRIP crossbar and either PWM
modules or directly to a GPIO pin. Figure 7-37 shows the CMPSS connectivity on the 337-ball ZWT and 176-pin
PTP packages. Figure 7-38 shows CMPSS connectivity on the 100-pin PZP package.
Comparator Subsystem 1
CMPIN1P Pin
CTRIP1H
Digital
Filter
CTRIPOUT1H
VDDA or VDAC
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
DAC12
DAC12
CTRIP1L
Digital
Filter
CTRIPOUT1L
ePWMs
ePWM X-BAR
CMPIN1N Pin
CMPIN2P Pin
CTRIP8H
CTRIP8L
Comparator Subsystem 2
Digital
CTRIP2H
CTRIPOUT2H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP2L
Digital
Filter
CTRIPOUT2L
CMPIN2N Pin
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem 8
Digital
CMPIN8P Pin
CTRIP8H
Output X-BAR
GPIO Mux
CTRIPOUT8H
VDDA or VDAC
Filter
CTRIPOUT8H
CTRIPOUT8L
DAC12
DAC12
CTRIP8L
Digital
Filter
CTRIPOUT8L
CMPIN8N Pin
Figure 7-37. CMPSS Connectivity (337-Ball ZWT and 176-Pin PTP)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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Comparator Subsystem 1
CMPIN1P Pin
CTRIP1H
Digital
Filter
CTRIPOUT1H
VDDA or VDAC
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CTRIP3H
CTRIP3L
CTRIP4H
CTRIP4L
DAC12
DAC12
CTRIP1L
Digital
Filter
CTRIPOUT1L
ePWM X-BAR
ePWMs
CMPIN1N Pin
CMPIN2P Pin
Comparator Subsystem 2
Digital
CTRIP2H
CTRIPOUT2H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP2L
Digital
Filter
CTRIPOUT2L
CMPIN2N Pin
CMPIN3P Pin
Comparator Subsystem 3
Digital
CTRIP3H
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
CTRIPOUT3H
CTRIPOUT3L
CTRIPOUT4H
CTRIPOUT4L
CTRIPOUT3H
VDDA or VDAC
Filter
DAC12
DAC12
Output X-BAR
GPIO Mux
CTRIP3L
Digital
Filter
CTRIPOUT3L
CMPIN3N Pin
CMPIN4P Pin
Comparator Subsystem 4
Digital
CTRIP4H
CTRIPOUT4H
VDDA or VDAC
Filter
DAC12
DAC12
CTRIP4L
Digital
Filter
CTRIPOUT4L
CMPIN4N Pin
Figure 7-38. CMPSS Connectivity (100-Pin PZP)
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.2.1 CMPSS Electrical Data and Timing
Section 7.10.2.1.1 shows the comparator electrical characteristics. Figure 7-39 shows the CMPSS comparator
input referred offset. Figure 7-40 shows the CMPSS comparator hysteresis.
7.10.2.1.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500(2)
VDDA
UNIT
µs
Power-up time
Comparator input (CMPINxx) range
Input referred offset error
0
V
Low common mode, inverting input set
to 50 mV
–20
20
mV
1x
12
24
36
48
21
26
30
2x
CMPSS
DAC LSB
Hysteresis(1)
3x
4x
Step response
60
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Ramp response (1.65 V/µs)
Ramp response (8.25 mV/µs)
ns
Common Mode Rejection Ratio (CMRR)
40
dB
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
(2) See the "Analog Bandgap References" advisory of the TMS320F2837xS MCUs Silicon Errata .
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from
the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal
comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this
time, the comparator could begin to output an incorrect result depending on the value of the other
comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-39. CMPSS Comparator Input Referred Offset
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 7-40. CMPSS Comparator Hysteresis
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Section 7.10.2.1.2 shows the CMPSS DAC static electrical characteristics. Figure 7-41 shows the CMPSS DAC
static offset. Figure 7-42 shows the CMPSS DAC static gain. Figure 7-43 shows the CMPSS DAC static linearity.
7.10.2.1.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
(1)
Internal reference
VDDA
CMPSS DAC output range
V
External reference
0
VDAC
Static offset error(2)
Static gain error(2)
Static DNL
–25
–2
25
2
mV
% of FSR
LSB
Endpoint corrected
Endpoint corrected
>–1
–16
4
Static INL
16
LSB
Settling to 1 LSB after full-scale output
change
Settling time
Resolution
1
µs
12
bits
Error induced by comparator trip or
CMPSS DAC code change within the
same CMPSS module
CMPSS DAC output disturbance(3)
–100
2.4
100
LSB
CMPSS DAC disturbance time(3)
VDAC reference voltage
VDAC load(4)
200
2.5 or 3.0
6
ns
V
When VDAC is reference
When VDAC is reference
VDDA
kΩ
(1) The maximum output voltage is VDDA when VDAC > VDDA
(2) Includes comparator input referred errors.
.
(3) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(4) Per active CMPSS module.
Offset Error
Figure 7-41. CMPSS DAC Static Offset
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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Ideal Gain
Actual Gain
Figure 7-42. CMPSS DAC Static Gain
Linearity Error
Figure 7-43. CMPSS DAC Static Linearity
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.10.3 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that is capable of
driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage
when the output buffer is disabled. This pulldown resistor cannot be disabled and remains as a passive
component on the pin, even for other shared pin mux functions. Software writes to the DAC value register can
take effect immediately or can be synchronized with EPWMSYNCPER events.
Each buffered DAC has the following features:
•
•
•
•
12-bit programmable internal DAC
Selectable reference voltage
Pulldown resistor on output
Ability to synchronize with EPWMSYNCPER
The block diagram for the buffered DAC is shown in Figure 7-44.
DACCTL[DACREFSEL]
VDAC
0
1
DACREF
VREFHI
VDDA
DACCTL[LOADMODE]
SYSCLK
>
Q
Q
0
1
DACVALS
D
12-bit
DAC
DACOUT
DACVALA
Buffer
D
RPD
EPWM1SYNCPER
EPWM2SYNCPER
EPWM3SYNCPER
0
1
2
EN
VSSA
VSSA
...
EPWMnSYNCPER
Y
n-1
DACCTL[SYNCSEL]
Figure 7-44. DAC Module Block Diagram
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7.10.3.1 Buffered DAC Electrical Data and Timing
Section 7.10.3.1.1 shows the buffered DAC electrical characteristics. Figure 7-45 shows the buffered DAC offset.
Figure 7-46 shows the buffered DAC gain. Figure 7-47 shows the buffered DAC linearity.
7.10.3.1.1 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500(8)
10
UNIT
µs
Power-up time
Offset error
Gain error(2)
DNL(3)
Midpoint
–10
–2.5
> –1
–5
mV
2.5 % of FSR
Endpoint corrected
Endpoint corrected
±0.4
±2
1
5
LSB
LSB
INL
Settling to 2 LSBs after 0.3V-to-3V
transition
DACOUTx settling time
2
µs
Resolution
12
bits
Voltage output range(4)
0.3
5
VDDA – 0.3
100
V
pF
Capacitive load
Output drive capability
Output drive capability
Resistive load
kΩ
RPD pulldown resistor
Reference voltage(5)
Reference input resistance(6)
50
2.5 or 3.0
170
kΩ
VDAC or VREFHI
2.4
VDDA
V
VDAC or VREFHI
kΩ
Integrated noise from 100 Hz to 100 kHz
Noise density at 10 kHz
500
µVrms
nVrms/√Hz
V-ns
Output noise
Glitch energy
PSRR(7)
711
1.5
DC up to 1 kHz
70
dB
100 kHz
30
SNR
THD
1020 Hz
67
dB
dB
1020 Hz
–63
1020 Hz, including harmonics and spurs
1020 Hz, including only spurs
66
SFDR
dBc
104
(1) Typical values are measured with VREFHI = 3.3 V unless otherwise noted. Minimum and Maximum values are tested or characterized
with VREFHI = 2.5 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or VREFHI should be less than VDDA
(6) Per active Buffered DAC module.
.
(7) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
(8) See the "Analog Bandgap References" advisory of the TMS320F2837xS MCUs Silicon Errata .
Note
The VDAC pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VDAC
pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC may float to 0 V
internally, giving improper DAC output.
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Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the VREFHI
pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may float to 0 V
internally, giving improper ADC conversion or DAC output.
Offset Error
Code 2048
Figure 7-45. Buffered DAC Offset
Actual Gain
Ideal Gain
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-46. Buffered DAC Gain
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Linearity Error
Code 3722
Code 373
Linear Range
(3.3-V Reference)
Figure 7-47. Buffered DAC Linearity
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7.11 Control Peripherals
Note
For the actual number of each peripheral on a specific device, see Table 5-1.
7.11.1 Enhanced Capture (eCAP)
The eCAP module can be used in systems where accurate timing of external events is important.
Applications for eCAP include:
•
•
•
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See Section 6.4.2 and Section 6.4.3.
Figure 7-48 shows the block diagram of an eCAP module.
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CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR [0−31]
PRD [0−31]
CTR=CMP
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Prescale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Figure 7-48. eCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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7.11.1.1 eCAP Electrical Data and Timing
Section 7.11.1.1.1 shows the eCAP timing requirement and Section 7.11.1.1.2 shows the eCAP switching
characteristics.
7.11.1.1.1 eCAP Timing Requirement
MIN(1)
2tc(SYSCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SYSCLK)
cycles
With input qualifier
1tc(SYSCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
7.11.1.1.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
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7.11.2 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced trip-
zone functionality, and global register reload capabilities.
Figure 7-49 shows the signal interconnections with the ePWM. Figure 7-50 shows the ePWM trip input
connectivity.
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TBCTL2[SYNCOSELX]
Time-Base (TB)
Disable
00
01
10
11
CTR=CMPC
TBPRD Shadow (24)
TBPRD Active (24)
CTR=CMPD
Rsvd
CTR=ZERO
CTR=CMPB
TBPRDHR (8)
Sync
Out
Select
EPWMxSYNCO
TBCTL[SWFSYNC]
EPWMxSYNCI
8
CTR=PRD
TBCTL[PHSEN]
TBCTL[SYNCOSEL]
DCAEVT1.sync(A)
DCBEVT1.sync(A)
Counter
Up/Down
(16 Bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
CTR=ZERO
EPWMx_INT
TBPHSHR (8)
16
8
CTR=PRD or ZERO
CTR=CMPA
EPWMxSOCA
EPWMxSOCB
Phase
Control
On-chip
ADC
TBPHS Active (24)
Event
Trigger
and
CTR=CMPB
CTR=CMPC
Interrupt
(ET)
ADCSOCOUTSELECT
CTR=CMPD
Counter Compare (CC)
CTR_Dir
Action
Qualifier
(AQ)
DCAEVT1.soc(A)
DCBEVT1.soc(A)
Select and pulse stretch
for external ADC
CTR=CMPA
CMPAHR (8)
ADCSOCAO
ADCSOCBO
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
CMPBHR (8)
16
EPWMB
ePWMxB
CMPB Active (24)
CMPB Shadow (24)
CMPBHR (8)
CTR=CMPC
EPWMx_TZ_INT
TZ1 to TZ3
TBCNT(16)
EMUSTOP
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
CLOCKFAIL
CMPC[15-0] 16
EQEPxERR
CMPC Active (16)
CMPC Shadow (16)
DCAEVT1.force(A)
DCAEVT2.force(A)
DCBEVT1.force(A)
DCBEVT2.force(A)
DCBEVT2.inter
TBCNT(16)
CTR=CMPD
CMPD[15-0] 16
CMPD Active (16)
CMPD Shadow (16)
Copyright © 2017, Texas Instruments Incorporated
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 7-49. ePWM Submodules and Critical Internal Signal Interconnects
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GPIO0
Async/
Sync/
XINT5
XINT4
PIE(s),
CLA(s)
INPUT14
INPUT13
Input X-Bar
Sync+Filter
GPIOx
eCAP6
eCAP5
eCAP4
eCAP3
eCAP2
eCAP1
XINT1
XINT2
XINT3
PIE(s),
CLA(s)
EXTSYNCIN1
ADC
Wrapper(s)
ePWM and eCAP
Sync Chain
EXTSYNCIN2
TZ1
TZ2
TZ3
PIE(s),
CLA(s)
EPWMINT
TZINT
TRIP1
TRIP2
TRIP3
TRIP6
EPWMx.EPWMCLK
EPWMENCLK
TBCLKSYNC
TRIP4
TRIP5
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ADCSOCAO Select Ckt
ADCSOCBO Select Ckt
ePWM
X-Bar
All
ePWM
Modules
SOCA
SOCB
ADC
Wrapper(s)
Reserved
ECCERR
TRIP13
TRIP14
TRIP15
TZ4
TZ5
TZ6
CPU1.PIEVECTERROR
SD1
Filter-Reset
Filter-Reset
EQEPERR
CLKFAIL
FLT1
FLT1
FLT1
FLT1
PWM11.CMPC
PWM11.CMPD
CPU1.EMUSTOP
EPWMn.EMUSTOP
Filter-Reset
Filter-Reset
FLT1
FLT1
FLT1
PWM12.CMPC
PWM12.CMPD
FLT1
SD2
EPWMSYNCPER
CMPSS
DAC
Figure 7-50. ePWM Trip Input Connectivity
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7.11.2.1 Control Peripherals Synchronization
The ePWM and eCAP synchronization chain allows synchronization between multiple modules for the system.
Figure 7-51 shows the synchronization chain architecture.
EXTSYNCIN1
EXTSYNCIN2
EPWM1
EPWM1SYNCOUT
EPWM2
EPWM3
EPWM4
EPWM4SYNCOUT
EPWM5
EPWM6
SYNCSEL.EPWM4SYNCIN
EXTSYNCOUT
Pulse-Stretched
(8 PLLSYSCLK
Cycles)
EPWM7
EPWM8
EPWM9
EPWM7SYNCOUT
SYNCSEL.EPWM7SYNCIN
EPWM10
EPWM11
EPWM12
EPWM10SYNCOUT
SYNCSEL.EPWM10SYNCIN
ECAP1
ECAP2
ECAP1SYNCOUT
SYNCSEL.ECAP1SYNCIN
ECAP3
ECAP4
ECAP5
ECAP6
SYNCSEL.ECAP4SYNCIN
SYNCSEL.SYNCOUT
Figure 7-51. Synchronization Chain Architecture
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7.11.2.2 ePWM Electrical Data and Timing
Section 7.11.2.2.1 shows the PWM timing requirements and Section 7.11.2.2.2 shows the PWM switching
characteristics.
7.11.2.2.1 ePWM Timing Requirements
MIN(1)
MAX
UNIT
MHz
f(EPWM)
Frequency, EPWMCLK(2)
Sync input pulse width
100
Asynchronous
Synchronous
2tc(EPWMCLK)
2tc(EPWMCLK)
cycles
cycles
cycles
tw(SYNCIN)
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
7.11.2.2.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
td(TZ-PWM)
25
ns
7.11.2.2.3 Trip-Zone Input Timing
Section 7.11.2.2.3.1 shows the trip-zone input timing requirements. Figure 7-52 shows the PWM Hi-Z
characteristics.
7.11.2.2.3.1 Trip-Zone Input Timing Requirements
MIN(1)
1tc(EPWMCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-52. PWM Hi-Z Characteristics
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7.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
Section 7.11.2.3.1 shows the external ADC start-of-conversion switching characteristics. Figure 7-53 shows the
ADCSOCAO or ADCSOCBO timing.
7.11.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-53. ADCSOCAO or ADCSOCBO Timing
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and
speed information from rotating machines used in high-performance motion and position-control systems.
Each eQEP peripheral comprises five major functional blocks:
•
•
•
•
•
Quadrature Capture Unit (QCAP)
Position Counter/Control Unit (PCCU)
Quadrature Decoder Unit (QDU)
Unit Time Base for speed and frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
The eQEP peripherals are clocked by PERx.SYSCLK. Figure 7-54 shows the eQEP block diagram.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
System Control
Registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
Capture
Unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
eQEP Peripheral
Figure 7-54. eQEP Block Diagram
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.11.3.1 eQEP Electrical Data and Timing
Section 7.11.3.1.1 lists the eQEP timing requirement and Section 7.11.3.1.2 lists the eQEP switching
characteristics.
7.11.3.1.1 eQEP Timing Requirements
MIN(1)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK)
tw(QEPP)
QEP input period
2[1tc(SYSCLK) + tw(IQSW)
]
Asynchronous(2)/Synchronous
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
Asynchronous(2)/Synchronous
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.6.2.1.
(2) See the TMS320F2837xS MCUs Silicon Errata for limitations in the asynchronous mode.
7.11.3.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
4tc(SYSCLK)
6tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.11.4 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
Note
The minimum HRPWMCLK frequency allowed for HRPWM is 60 MHz.
7.11.4.1 HRPWM Electrical Data and Timing
Section 7.11.4.1.1 lists the high-resolution PWM timing requirements. Section 7.11.4.1.2 lists the high-resolution
PWM switching characteristics.
7.11.4.1.1 High-Resolution PWM Timing Requirements
MIN
MAX
100
UNIT
MHz
MHz
f(EPWM)
Frequency, EPWMCLK(1)
Frequency, HRPWMCLK
f(HRPWM)
60
100
(1) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
7.11.4.1.2 High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
150
MAX UNIT
Micro Edge Positioning (MEP) step size(1)
310
ps
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.11.5 Sigma-Delta Filter Module (SDFM)
The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position
decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated
bit stream. The bit streams are processed by four individually programmable digital decimation filters. The filter
set includes a fast comparator for immediate digital threshold comparisons for overcurrent and undercurrent
monitoring. Figure 7-55 shows a block diagram of the SDFMs.
SDFM features include:
•
Eight external pins per SDFM module:
– Four sigma-delta data input pins per SDFM module (SDx_Dy, where x = 1 to 2 and y = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SDx_Cy, where x = 1 to 2 and y = 1 to 4)
Four different configurable modulator clock modes:
•
– Modulator clock rate equals modulator data rate
– Modulator clock rate running at half the modulator data rate
– Modulator data is Manchester encoded. Modulator clock not required.
– Modulator clock rate is double that of modulator data rate
•
•
Four independent configurable comparator units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Ability to detect over-value and under-value conditions
– Comparator Over-Sampling Ratio (COSR) value for comparator programmable from 1 to 32
Four independent configurable data filter units:
– Four different filter type selection (Sinc1/Sinc2/Sincfast/Sinc3) options available
– Data filter Over-Sampling Ratio (DOSR) value for data filter unit programmable from 1 to 256
– Ability to enable or disable individual filter module
– Ability to synchronize all four independent filters of a SDFM module using the Master Filter Enable (MFE)
bit or the PWM signals.
•
•
Filter data can be 16-bit or 32-bit representation
PWMs can be used to generate modulator clock for sigma-delta modulators
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SDFM- Sigma Delta Filter Module
Filter Channel 1
G4
Streams
SD1INT
IEL
IEH
Comparator filter
Interrupt
Unit
SD2INT
SD1_D1
SD1_C1
Input
Ctrl
PIE
Data filter
FILRES
PWM11.CMPC
Filter Channel 2
Filter Channel 3
Filter Channel 4
SD1_D2
SD1_C2
FILRES
Data bus
Register
Map
SD1_D3
SD1_C3
FILRES
FILRES
PWM11.CMPD
SD1_D4
SD1_C4
SD1FLT1.IEH
SD1FLT1.IEL
SD1FLT2.IEH
SD1FLT2.IEL
SD1FLT3.IEH
SD1FLT3.IEL
SD1FLT4.IEH
SD1FLT4.IEL
GPIO
MUX
SDFM- Sigma Delta Filter Module
Output
XBar
G4
Streams
Filter Channel 1
SD2FLT1.IEH
SD2FLT1.IEL
SD2FLT2.IEH
SD2FLT2.IEL
IEL
IEH
Comparator filter
Interrupt
Unit
SD2_D1
SD2_C1
Input
Ctrl
Data filter
FILRES
SD2FLT3.IEH
SD2FLT3.IEL
SD2FLT4.IEH
SD2FLT4.IEL
PWM12.CMPC
SD2_D2
SD2_C2
Filter Channel 2
Filter Channel 3
Filter Channel 4
FILRES
Data bus
Register
Map
SD2_D3
SD2_C3
FILRES
FILRES
PWM12.CMPD
SD2_D4
SD2_C4
Figure 7-55. SDFM Block Diagram
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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7.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
SDFM operation with asynchronous GPIO is defined by setting GPyQSELn = 0b11. Section 7.11.5.1.1 lists the
SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 7-56 through Figure
7-59 show the SDFM timing diagrams.
7.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
MIN
MAX UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
40
10
256 * SYSCLK period
ns
ns
tw(SDCH)M0
Pulse duration, SDx_Cy high
tc(SDC)M0 – 10
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
5
5
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 1
tc(SDC)M1
Cycle time, SDx_Cy
80
10
256 * SYSCLK period
tc(SDC)M1 – 10
ns
ns
tw(SDCH)M1
Pulse duration, SDx_Cy high
Setup time, SDx_Dy valid before SDx_Cy goes
low
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
5
5
ns
ns
Setup time, SDx_Dy valid before SDx_Cy goes
high
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes low
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 2
5
5
ns
ns
tc(SDD)M2
Cycle time, SDx_Dy
8 * tc(SYSCLK)
10
20 * tc(SYSCLK)
ns
ns
tw(SDDH)M2
Pulse duration, SDx_Dy high
SDx_Dy long pulse duration keepout, where the
long pulse must not fall within the MIN or MAX
values listed.
Long pulse is defined as the high or low pulse
which is the full width of the Manchester bit-clock
period.
This requirement must be satisfied for any integer
between 8 and 20.
tw(SDD_LONG_KEEPOUT)M2
(N * tc(SYSCLK)) – 0.5
(N * tc(SYSCLK)) + 0.5
ns
ns
SDx_Dy Short pulse duration for a high or low
pulse (SDD_SHORT_H or SDD_SHORT_L).
Short pulse is defined as the high or low pulse
which is half the width of the Manchester bit-clock
period.
tw(SDD_LONG) / 2 –
tc(SYSCLK)
tw(SDD_LONG) / 2 +
tc(SYSCLK)
tw(SDD_SHORT)M2
SDx_Dy Long pulse variation (SDD_LONG_H –
SDD_LONG_L)
tw(SDD_LONG_DUTY)M2
tw(SDD_SHORT_DUTY)M2
– tc(SYSCLK)
– tc(SYSCLK)
tc(SYSCLK)
tc(SYSCLK)
ns
ns
SDx_Dy Short pulse variation (SDD_SHORT_H –
SDD_SHORT_L)
Mode 3
Cycle time, SDx_Cy
tc(SDC)M3
40
10
256 * SYSCLK period
tc(SDC)M3 – 5
ns
ns
tw(SDCH)M3
Pulse duration, SDx_Cy high
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
5
5
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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WARNING
The SDFM clock inputs (SDx_Cy pins) directly clock the SDFM module when there is no GPIO input
synchronization. Any glitches or ringing noise on these inputs can corrupt the SDFM module
operation. Special precautions should be taken on these signals to ensure a clean and noise-free
signal that meets SDFM timing requirements. Precautions such as series termination for ringing due
to any impedance mismatch of the clock driver and spacing of traces from other noisy signals are
recommended.
WARNING
Mode 2 (Manchester Mode) is not recommended for new applications. See the "SDFM: Manchester
Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions" advisory in the
TMS320F2837xS MCUs Silicon Errata .
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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Mode 0
tw(SDCH)M0
tc(SDC)M0
SDx_Cy
SDx_Dy
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
Figure 7-56. SDFM Timing Diagram – Mode 0
Mode 1
SDx_Cy
tw(SDCH)M1
tc(SDC)M1
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
SDx_Dy
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Figure 7-57. SDFM Timing Diagram – Mode 1
Mode 2
(Manchester-encoded-bit stream)
tc(SDD)M2
Modulator
Internal clock
tw(SDDH)M2
Modulator
Internal data
1
1
0
1
1
0
0
1
1
tw(SDD_LONG_KEEPOUT)
SDx-Dy
tw(SDD_LONG_L)
tw(SDD_LONG_H)
tw(SDD_SHORT_L)
tw(SDD_SHORT_H)
N x tc(SYSCLK) + 0.5
N x SYSCLK
SYSCLK
N x tc(SYSCLK) œ0.5
œ
Figure 7-58. SDFM Timing Diagram – Mode 2
(CLKx is driven externally)
tc(SDC)M3
Mode 3
tw(SDCH)M3
SDx_Cy
SDx_Dy
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
Figure 7-59. SDFM Timing Diagram – Mode 3
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
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7.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
SDFM operation with qualified GPIO (3-sample window) is defined by setting GPyQSELn = 0b01. When using
this qualified GPIO (3-sample window) mode, the timing requirement for the tw(GPI) pulse duration of 2tc(SYSCLK)
must be met. It is important for both SD-Cx and SD-Dx pairs to be configured with the same GPIO qualification
option. Section 7.11.5.2.1 lists the SDFM timing requirements when using the GPIO input qualification (3-sample
window) option. Figure 7-56 through Figure 7-59 show the SDFM timing diagrams.
7.11.5.2.1 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
MIN(1)
MAX UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
10 * SYSCLK period
4 * SYSCLK period
4 * SYSCLK period
256 * SYSCLK period
ns
ns
ns
tw(SDCHL)M0
tw(SDDHL)M0
Pulse duration, SDx_Cy high/low
Pulse duration, SDx_Dy high/low
6 * SYSCLK period
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 1
tc(SDC)M1
Cycle time, SDx_Cy
20 * SYSCLK period
4 * SYSCLK period
4 * SYSCLK period
256 * SYSCLK period
6 * SYSCLK period
ns
ns
ns
tw(SDCH)M1
tw(SDDHL)M1
Pulse duration, SDx_Cy high
Pulse duration, SDx_Dy high/low
Setup time, SDx_Dy valid before SDx_Cy goes
low
tsu(SDDV-SDCL)M1
tsu(SDDV-SDCH)M1
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Setup time, SDx_Dy valid before SDx_Cy goes
high
th(SDCL-SDD)M1
th(SDCH-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes low
Hold time, SDx_Dy wait after SDx_Cy goes high
Mode 2
2 * SYSCLK period
2 * SYSCLK period
ns
ns
tc(SDD)M2
Cycle time, SDx_Dy
Option unavailable
tw(SDDH)M2
Pulse duration, SDx_Dy high
Mode 3
tc(SDC)M3
Cycle time, SDx_Cy
10 * SYSCLK period
4 * SYSCLK period
4 * SYSCLK period
256 * SYSCLK period
6 * SYSCLK period
ns
ns
ns
tw(SDCHL)M3
tw(SDDHL)M3
Pulse duration, SDx_Cy high
Pulse duration, SDx_Dy high/low
Setup time, SDx_Dy valid before SDx_Cy goes
high
tsu(SDDV-SDCH)M3
th(SDCH-SDD)M3
2 * SYSCLK period
2 * SYSCLK period
ns
ns
Hold time, SDx_Dy wait after SDx_Cy goes high
(1) SDFM timing requirements apply only when the GPIO input qualification type is the 3-sample window (GPyQSELx = 1; QUALPRD = 0)
option. It is important that both the SD-Cx and SD-Dx pairs be configured with the 3-sample window option.
Note
The SDFM Qualified GPIO (3-sample) mode provides protection against SDFM module corruption due
to occasional random noise glitches on the SDx_Cy pin that may result in a false comparator trip and
filter output. For more details, refer to the "SDFM: Use Caution While Using SDFM Under Noisy
Conditions" usage note in the TMS320F2837xS MCUs Silicon Errata .
The SDFM Qualified GPIO (3-sample) mode does not provide protection against persistent violations
of the above timing requirements. Timing violations will result in data corruption proportional to the
number of bits which violate the requirements.
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7.12 Communications Peripherals
Note
For the actual number of each peripheral on a specific device, see Table 5-1.
7.12.1 Controller Area Network (CAN)
The CAN module performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN
protocol specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbps. A CAN transceiver chip
is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message objects and
identifier masks are stored in the Message RAM.
All functions concerning the handling of messages are implemented in the message handler. These functions
are: acceptance filtering; the transfer of messages between the CAN Core and the Message RAM; and the
handling of transmission requests.
The register set of the CAN may be accessed directly by the CPU through the module interface. These registers
are used to control and configure the CAN core and the message handler, and to access the message RAM.
The CAN module implements the following features:
•
•
•
•
Complies with ISO11898-1 (Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (“message objects” are also referred to as “mailboxes” in this document; the two terms
are used interchangeably), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
•
•
•
•
•
•
•
•
Software module reset
Automatic bus-on, after bus-off state by a programmable 32-bit timer
Message-RAM parity-check mechanism
Two interrupt lines
Note
For a CAN bit clock of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
Note
Depending on the timing settings used, the accuracy of the on-chip zero-pin oscillator (specified in the
data manual) may not meet the requirements of the CAN protocol. In this situation, an external clock
source must be used.
Figure 7-60 shows the CAN block diagram.
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CAN_H
CAN_L
CAN Bus
3.3V CAN Transceiver
External connections
Device
CANx RX pin
CANx TX pin
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Register and Message
Object Access (IFx)
32
Message
Objects
(Mailboxes)
Test Modes
Only
Module Interface
CANINT0 CANINT1
(to ePIE)
CPU Bus
Figure 7-60. CAN Block Diagram
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7.12.2 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 16-byte receive FIFO and one 16-byte transmit FIFO
•
•
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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Figure 7-61 shows how the I2C peripheral module interfaces within the device.
I2C Module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
SDA
Peripheral Bus
I2CRSR
I2CDRR
Control/Status
Registers
CPU
Clock
Synchronizer
SCL
Prescaler
Noise Filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
Figure 7-61. I2C Peripheral Module Interfaces
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7.12.2.1 I2C Electrical Data and Timing
Section 7.12.2.1.1 lists the I2C timing requirements. Section 7.12.2.1.2 lists the I2C switching characteristics.
Figure 7-62 shows the I2C timing diagram.
7.12.2.1.1 I2C Timing Requirements
NO.
MIN
MAX
UNIT
Standard mode
T0
T1
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
th(SDA-SCL)START
4.0
Setup time, Repeated START, SCL rise before SDA
fall delay
T2
tsu(SCL-SDA)START
4.7
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
250
1000
1000
300
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
4.0
0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
tw(SP)
Cb
50
ns
T11
capacitance load on each bus line
400
pF
Fast mode
T0
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
0.6
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
0.6
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.6
0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
50
ns
capacitance load on each bus line
400
pF
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7.12.2.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
0.1 Vbus < Vi < 0.9 Vbus
0.1 Vbus < Vi < 0.9 Vbus
MIN
MAX UNIT
Standard mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
10
100
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
4.7
4.0
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
4.7
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
3.45
3.45
10
µs
µs
µA
–10
Fast mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
2.5
1.3
0.6
400
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
1.3
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.9
0.9
10
µs
µs
µA
–10
7.12.2.1.3
Note
To meet all of the I2C protocol timing specifications, the I2C module clock (Fmod) must be configured
from 7 MHz to 12 MHz.
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STOP
START
SDA
SCL
ACK
Contd...
Contd...
S7
S6
T10
T5
T7
S3
S4
9th
clock
T6
T8
S2
Repeated
START
STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 7-62. I2C Timing Diagram
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7.12.3 Multichannel Buffered Serial Port (McBSP)
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
8-bit data transfer mode can be configured to transmit with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
•
•
Supports AC97, I2S, and SPI protocols
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR.
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Figure 7-63 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
CPU
Peripheral Write Bus
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
DXR1 Transmit Buffer
16
PERx.LSPCLK
MFSXx
16
MCLKXx
MDXx
Compand Logic
XSR2
XSR1
MDRx
RSR1
16
RSR2
16
CPU
DMA Bus
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
Interrupt Select Logic
16
16
RX
Interrupt
RX Interrupt Logic
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 7-63. McBSP Block Diagram
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7.12.3.1 McBSP Electrical Data and Timing
7.12.3.1.1 McBSP Transmit and Receive Timing
Section 7.12.3.1.1.1 shows the McBSP timing requirements. Section 7.12.3.1.1.2 shows the McBSP switching
characteristics. Figure 7-64 and Figure 7-65 show the McBSP timing diagrams.
7.12.3.1.1.1 McBSP Timing Requirements
NO.(1)
MIN
MAX UNIT
(2)
1
kHz
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
25
1
MHz
ns
40
ms
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
P – 7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
18
5
0
Hold time, DR valid after CLKR low
3
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
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7.12.3.1.1.2 McBSP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.(1)
PARAMETER
MIN
MAX UNIT
(2)
M1
M2
M3
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5 (3)
D + 5 (3)
ns
ns
C – 5 (3)
C + 5 (3)
-7
3
7.5
27
6
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
-5
3
27
8
–8
3
Disable time, CLKX high to DX high impedance
following last data bit
15
9
Delay time, CLKX high to DX valid.
–3
This applies to all bits except the first bit
transmitted.
CLKX ext
5
25
CLKX int
CLKX ext
CLKX int
–3
5
8
20
Delay time, CLKX high to DX
DXENA = 0
valid
M7
td(CKXH-DXV)
ns
Only applies to first bit
P – 3
P + 8
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 5
P + 20
or 10b) modes
CLKX int
CLKX ext
CLKX int
-6
4
Enable time, CLKX high to
DXENA = 0
DX driven
Only applies to first bit
P - 6
M8
M9
ten(CKXH-DX)
ns
ns
ns
transmitted when in Data
Delay 1 or 2 (XDATDLY=01b
DXENA = 1
CLKX ext
P + 4
or 10b) modes
FSX int
FSX ext
FSX int
8
17
Delay time, FSX high to DX
DXENA = 0
valid
Only applies to first bit
P + 8
td(FXH-DXV)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 17
mode.
FSX int
FSX ext
FSX int
-3
6
Enable time, FSX high to DX
DXENA = 0
driven
Only applies to first bit
P - 3
M10 ten(FXH-DX)
transmitted when in Data
Delay 0 (XDATDLY=00b)
DXENA = 1
FSX ext
P + 6
mode
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
FSR (ext)
M15
M17
M16
M18
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(n−2)
M18
DR
(RDATDLY=01b)
Bit (n−1)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
Figure 7-64. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 7-65. McBSP Transmit Timing
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7.12.3.1.2 McBSP as SPI Master or Slave Timing
Section 7.12.3.1.2.1 lists the McBSP as SPI master timing requirements. Section 7.12.3.1.2.2 lists the McBSP as
SPI master switching characteristics. Section 7.12.3.1.2.3 lists the McBSP as SPI slave timing requirements.
Section 7.12.3.1.2.4 lists the McBSP as SPI slave switching characteristics.
Figure 7-66 through Figure 7-69 show the McBSP as SPI master or slave timing diagrams.
7.12.3.1.2.1 McBSP as SPI Master Timing Requirements
NO.
MIN
MAX
UNIT
CLOCK
tc(CLKG)
P
Cycle time, CLKG(1)
2 * tc(LSPCLK)
tc(LSPCLK)
ns
ns
Cycle time, LSPCLK(1)
M33,
M42,
M52,
M61
tc(CKX)
Cycle time, CLKX
2P
ns
CLKSTP = 10b, CLKXP = 0
M30
M31
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
30
1
ns
ns
CLKSTP = 11b, CLKXP = 0
M39
M40
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
30
1
ns
ns
CLKSTP = 10b, CLKXP = 1
M49
M50
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
30
1
ns
ns
CLKSTP = 11b, CLKXP = 1
M58
M59
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
30
1
ns
ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
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7.12.3.1.2.2 McBSP as SPI Master Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
CLOCK
M33
PARAMETER
MIN
TYP
MAX
UNIT
tc(CLKG)
Cycle time, CLKG(1) (n * tc(LSPCLK)
Half CLKG cycle; 0.5 * tc(CLKG)
LSPCLK to CLKG divider
)
40
20
2
ns
ns
ns
P
n
CLKSTP = 10b, CLKXP = 0
M24
M25
M26
th(CKXL-FXL)
td(FXL-CKXH)
td(CLKXH-DXV)
Hold time, FSX high after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
2P – 6
P – 6
–4
ns
ns
ns
6
Disable time, DX high impedance following last data bit from
CLKX low
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
P – 8
P – 3
ns
ns
Delay time, FSX low to DX valid
P + 6
CLKSTP = 11b, CLKXP = 0
M34
M35
M36
th(CKXL-FXH)
td(FXL-CKXH)
td(CLKXL-DXV)
Hold time, FSX high after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
P – 6
P – 6
–4
ns
ns
ns
6
1
Disable time, DX high impedance following last data bit from
CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
P – 6
–2
ns
ns
Delay time, FSX low to DX valid
CLKSTP = 10b, CLKXP = 1
M43
M44
M45
th(CKXH-FXH)
td(FXL-CKXL)
td(CLKXL-DXV)
Hold time, FSX high after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
2P – 6
P – 6
–4
ns
ns
ns
6
1
Disable time, DX high impedance following last data bit from
CLKX low
M47
M48
tdis(FXH-DXHZ)
td(FXL-DXV)
P – 6
–2
ns
ns
Delay time, FSX low to DX valid
CLKSTP = 11b, CLKXP = 1
M53
M54
M55
th(CKXH-FXH)
td(FXL-CKXL)
td(CLKXH-DXV)
Hold time, FSX high after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
P – 6
2P – 6
–4
ns
ns
ns
6
1
Disable time, DX high impedance following last data bit from
CLKX high
M56
M57
tdis(CKXH-DXHZ)
td(FXL-DXV)
P – 8
–2
ns
ns
Delay time, FSX low to DX valid
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1.
7.12.3.1.2.3 McBSP as SPI Slave Timing Requirements
NO.
MIN
MAX
UNIT
CLOCK
tc(CLKG)
P
Cycle time, CLKG(1)
2 * tc(LSPCLK)
tc(LSPCLK)
ns
ns
Cycle time, LSPCLK(1)
M33,
M42,
M52,
M61
tc(CKX)
Cycle time, CLKX(2)
16P
ns
CLKSTP = 10b, CLKXP = 0
M30
M31
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
8P – 10
8P – 10
ns
ns
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NO.
MIN
MAX
UNIT
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
CLKSTP = 11b, CLKXP = 0
M39
M40
M41
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
8P – 10
8P – 10
16P+10
ns
ns
ns
CLKSTP = 10b, CLKXP = 1
M49
M50
M51
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
8P – 10
8P – 10
8P+10
ns
ns
ns
CLKSTP = 11b, CLKXP = 1
M58
M59
M60
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(FXL-CKXL)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
8P – 10
8P – 10
16P+10
ns
ns
ns
(1) CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1
(2) For SPI slave modes CLKX must be a minimum of 8 CLKG cycles
7.12.3.1.2.4 McBSP as SPI Slave Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
CLOCK
2P
CLKSTP = 10b, CLKXP = 0
Cycle time, CLKG
ns
M26
M28
M29
td(CLKXH-DXV)
tdis(FXH-DXHZ)
td(FXL-DXV)
Delay time, CLKX high to DX valid
3P + 6
6P + 6
4P + 6
5P + 20
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
Delay time, FSX low to DX valid
CLKSTP = 11b, CLKXP = 0
M36
M37
M38
td(CLKXL-DXV)
tdis(CKXL-DXHZ)
td(FXL-DXV)
Delay time, CLKX low to DX valid
3P + 6
7P + 6
4P + 6
5P + 20
5P + 20
5P + 20
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX low
Delay time, FSX low to DX valid
CLKSTP = 10b, CLKXP = 1
M45
M47
M48
td(CLKXL-DXV)
tdis(FXH-DXHZ)
td(FXL-DXV)
Delay time, CLKX low to DX valid
3P + 6
6P + 6
4P + 6
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
Delay time, FSX low to DX valid
CLKSTP = 11b, CLKXP = 1
M55
M56
M57
td(CLKXH-DXV)
tdis(CKXH-DXHZ)
td(FXL-DXV)
Delay time, CLKX high to DX valid
3P + 6
7P + 6
4P + 6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX high
Delay time, FSX low to DX valid
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M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M26
M29
M28
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M31
(n-2)
(n-3)
(n-4)
M30
Bit 0
(n-3)
(n-4)
Figure 7-66. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M36
(n-2)
M40
(n-2)
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M39
DR
Bit 0
(n-3)
(n-4)
Figure 7-67. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
M45
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
(n-4)
Figure 7-68. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M56
M55
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 7-69. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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7.12.4 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register. Figure 7-70 shows the SCI block diagram.
Features of the SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
Data-word format
•
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wakeup multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
•
•
•
•
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
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TXENA
SCICTL1.1
TXSHF
SCITXD
Register
Frame
Format and Mode
8
Parity
Even/Odd
TXEMPTY
1
SCICTL2.6
0
SCICCR.6
8
Enable
TX FIFO_0
TXINT
To CPU
SCICCR.5
TX FIFO_1
TX Interrupt
Logic
TX FIFO Interrupts
8
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCIFFTX.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
Figure 7-70. SCI Block Diagram
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The major elements used in full-duplex operation include:
•
•
A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts data onto
the SCITXD pin, 1 bit at a time
A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into the RXSHF register and then into the SCIRXBUF and SCIRXEMU
registers
•
•
A programmable baud generator
Data-memory-mapped control and status registers enable the CPU to access the I2C module registers and
FIFOs.
The SCI receiver and transmitter operate independently.
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7.12.5 Serial Peripheral Interface (SPI)
The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communications between the microcontroller and external peripherals or another controller.
Typical applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The
port supports 16-level receive and transmit FIFOs for reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: master and slave
Baud rate: 125 different programmable rates
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
16-level transmit and receive FIFO
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
DMA support
High-speed mode for up to 50-MHz full-duplex communication
•
•
•
•
•
•
•
•
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The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For
both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched
into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.3) is high, data is
transmitted and received a half-cycle before the SPICLK transition. As a result, both controllers send and receive
data simultaneously. The application software determines whether the data is meaningful or dummy data. There
are three possible methods for data transmission:
•
•
•
Master sends data; slave sends dummy data
Master sends data; slave sends data
Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
Figure 7-71 shows the SPI CPU Interface.
PCLKCR8
Low-Speed
LSPCLK
SYSCLK
CPU
Prescaler
Bit
Clock
SYSRS
SPISIMO
SPISOMI
SPICLK
GPIO
MUX
SPI
SPIINT
SPITXINT
PIE
SPISTE
SPIRXDMA
SPITXDMA
DMA
Figure 7-71. SPI CPU Interface
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7.12.5.1 SPI Electrical Data and Timing
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
For more information about the SPI in High-Speed mode, see the Serial Peripheral Interface (SPI) chapter of the
TMS320F2837xS Microcontrollers Technical Reference Manual .
To use the SPI in High-Speed mode, the application must use the high-speed enabled GPIOs (see Section
6.4.5).
7.12.5.1.1 SPI Master Mode Timings
Section 7.12.5.1.1.1 lists the SPI master mode timing requirements. Section 7.12.5.1.1.2 lists the SPI master
mode switching characteristics (clock phase = 0). Section 7.12.5.1.1.3 lists the SPI master mode switching
characteristics (clock phase = 1). Figure 7-72 shows the SPI master mode external timing where the clock phase
= 0. Figure 7-73 shows the SPI master mode external timing where the clock phase = 1.
7.12.5.1.1.1 SPI Master Mode Timing Requirements
(BRR + 1)
NO.
MIN
MAX UNIT
CONDITION(1)
High Speed Mode
Setup time, SPISOMI valid before
SPICLK
8
9
tsu(SOMI)M
th(SOMI)M
Even, Odd
1
5
ns
ns
Hold time, SPISOMI valid after
SPICLK
Even, Odd
Normal Mode
Even, Odd
Setup time, SPISOMI valid before
SPICLK
8
9
tsu(SOMI)M
th(SOMI)M
20
0
ns
ns
Hold time, SPISOMI valid after
SPICLK
Even, Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
General
Even
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
Odd
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
tw(SPC1)M
Pulse duration, SPICLK, first pulse
0.5tc(SPC)M +0.5tc(LSPCLK)
– 1
0.5tc(SPC)M +0.5tc(LSPCLK)
+ 1
Odd
Even
Odd
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, second
pulse
3
tw(SPC2)M
ns
ns
ns
0.5tc(SPC)M –0.5tc(LSPCLK)
1.5tc(SPC)M - 3tc(SYSCLK)
1.5tc(SPC)M - 4tc(SYSCLK)
–
1
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 1
–
7
1.5tc(SPC)M - 3tc(SYSCLK)
+
5
Even
23 td(SPC)M
Delay time, SPISTE active to SPICLK
–
7
1.5tc(SPC)M - 4tc(SYSCLK)
+
5
Odd
Even
Odd
0.5tc(SPC)M – 7
0.5tc(SPC)M + 5
Valid time, SPICLK to SPISTE
inactive
24 tv(STE)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
7
0.5tc(SPC)M –0.5tc(LSPCLK)
+ 5
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MAX UNIT
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over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
CONDITION(1)
High Speed Mode
4
5
td(SIMO)M
Delay time, SPICLK to SPISIMO valid Even, Odd
1
ns
ns
Even
0.5tc(SPC)M – 2
Valid time, SPISIMO valid after
tv(SIMO)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
2
SPICLK
Odd
Normal Mode
4
5
td(SIMO)M
Delay time, SPICLK to SPISIMO valid Even, Odd
6
ns
ns
Even
0.5tc(SPC)M – 5
Valid time, SPISIMO valid after
tv(SIMO)M
0.5tc(SPC)M –0.5tc(LSPCLK)
–
5
SPICLK
Odd
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
7.12.5.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
(BRR + 1)
NO.
PARAMETER
MIN
MAX UNIT
CONDITION(1)
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
0.5tc(SPC)M – 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK, first
pulse
tw(SPCH)M
0.5tc(SPC)M
–
Odd
Even
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 1
0.5tc(LSPCLK) + 1
0.5tc(SPC)M + 1
Pulse duration, SPICLK,
second pulse
3
tw(SPC2)M
ns
0.5tc(SPC)M
+
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(LSPCLK) + 1
Delay time, SPISTE valid to
SPICLK
2tc(SPC)M –
3tc(SYSCLK) + 5
23 td(SPC)M
Even, Odd
2tc(SPC)M – 3tc(SYSCLK) – 7
ns
ns
Even
Odd
– 7
– 7
+5
+5
Valid time, SPICLK to SPISTE
invalid
24 tv(STE)M
High Speed Mode
Even
Odd
0.5tc(SPC)M – 1
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
0.5tc(SPC)M – 2
Delay time, SPISIMO valid to
SPICLK
4
5
td(SIMO)M
ns
ns
Even
Odd
Valid time, SPISIMO valid after
SPICLK
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 2
Normal Mode
Even
Odd
0.5tc(SPC)M – 5
0.5tc(SPC)M + 0.5tc(LSPCLK) – 5
0.5tc(SPC)M – 5
Delay time, SPISIMO valid to
SPICLK
4
5
td(SIMO)M
ns
ns
Even
Odd
Valid time, SPISIMO valid after
SPICLK
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 5
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-72. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 7-73. SPI Master Mode External Timing (Clock Phase = 1)
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7.12.5.1.2 SPI Slave Mode Timings
Section 7.12.5.1.2.1 lists the SPI slave mode timing requirements. Section 7.12.5.1.2.2 lists the SPI slave mode
switching characteristics. Figure 7-74 shows the SPI slave mode external timing where the clock phase = 0.
Figure 7-75 shows the SPI slave mode external timing where the clock phase = 1.
7.12.5.1.2.1 SPI Slave Mode Timing Requirements
NO.
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
19 tsu(SIMO)S
20 th(SIMO)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
Setup time, SPISTE valid before
SPICLK (Clock Phase = 0)
2tc(SYSCLK) + 4
ns
25 tsu(STE)S
Setup time, SPISTE valid before
SPICLK (Clock Phase = 1)
2tc(SYSCLK) + 14
1.5tc(SYSCLK)
ns
ns
26 th(STE)S
Hold time, SPISTE invalid after SPICLK
7.12.5.1.2.2 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
0
MAX UNIT
High Speed Mode
15 td(SOMI)S
16 tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
9
ns
ns
Normal Mode
15 td(SOMI)S
16 tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
20
ns
ns
0
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-74. SPI Slave Mode External Timing (Clock Phase = 0)
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-75. SPI Slave Mode External Timing (Clock Phase = 1)
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7.12.6 Universal Serial Bus (USB) Controller
The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
•
•
•
•
USB 2.0 full-speed and low-speed operation
Integrated PHY
Three transfer types: control, interrupt, and bulk
32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
4KB of dedicated endpoint memory
•
Figure 7-76 shows the USB block diagram.
Endpoint Control
Transmit
Receive
EP0 –31
Control
CPU Interface
Interrupt
Control
Interrupts
CPU Bus
Host
Transaction
Scheduler
Combine
Endpoints
EP Reg.
Decoder
Common
Regs
UTM
Synchronization
Packet
Encode/Decode
FIFO RAM
Controller
Rx
Buff
Rx
Buff
Data Sync
Packet Encode
Packet Decode
CRC Gen/Check
Cycle
Control
Tx
Buff
Tx
Buff
HNP/SRP
USB FS/LS
PHY
FIFO
Decoder
Timers
Cycle Control
USB DataLines
D+ andD-
Figure 7-76. USB Block Diagram
Note
The accuracy of the on-chip zero-pin oscillator (Section 7.9.3.5.1, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external clock source
must be used for applications using USB. For applications using the USB boot mode, see Section 8.9
(Boot ROM and Peripheral Booting) for clock frequency requirements.
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7.12.6.1 USB Electrical Data and Timing
Section 7.12.6.1.1 shows the USB input ports DP and DM timing requirements. Section 7.12.6.1.2 shows the
USB output ports DP and DM switching characteristics.
7.12.6.1.1 USB Input Ports DP and DM Timing Requirements
MIN
0.8
MAX
UNIT
V
V(CM)
Z(IN)
VCRS
VIL
Differential input common mode range
Input impedance
2.5
300
1.3
kΩ
V
Crossover voltage
2.0
Static SE input logic-low level
Static SE input logic-high level
Differential input voltage
0.8
V
VIH
2.0
0.2
V
VDI
V
7.12.6.1.2 USB Output Ports DP and DM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
D+, D– single-ended
D+, D– single-ended
D+, D– impedance
TEST CONDITIONS
MIN
MAX
UNIT
V
VOH
USB 2.0 load conditions
USB 2.0 load conditions
2.8
0
3.6
0.3
44
VOL
V
Z(DRV)
28
Ω
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
tr
tf
Rise time
Fall time
4
4
20
20
ns
ns
Full speed, differential, CL = 50 pF, 10%/90%,
Rpu on D+
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7.12.7 Universal Parallel Port (uPP) Interface
The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals. The
uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width. It can also be
interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital
data transfer. It can operate in receive mode or transmit mode (simplex mode).
The uPP interface includes an internal DMA controller to maximize throughput and minimize CPU overhead
during high-speed data transmission. All uPP transactions use internal DMA to feed data to or retrieve data from
the I/O channels. Even though there is only one I/O channel, the DMA controller includes two DMA channels to
support data interleave mode, in which all DMA resources service a single I/O channel.
On this device, the uPP interface is the dedicated resource for the CPU1 subsystem. CPU1, CPU1.CLA1, and
CPU1.DMA have access to this module. Two dedicated 512-byte data RAMs (also known as MSG RAMs) are
tightly coupled with the uPP module (one for each, TX and RX). These data RAMs are used to store the bulk of
data to avoid frequent interruptions to the CPU. Only CPU1 and CPU1.CLA1 have access to these data RAMs.
Figure 7-77 shows the integration of the uPP on this device.
CPU1
RX-DATARAM
READ
Arbi
Arbiter Y
512 Byte
(Dual Port
t
Memory)
CPU1.CLA1
uPP DMA WRITE
CPU1
I/O Interface
Arbi
Arbiter X
uPP
(Universal
CPU1.CLA1
t
0
1
Parallel Port)
CPU1.DMA
uPP DMA READ
SECMSEL.PF2SEL
CPU1
TX-DATARAM
512 Byte
WRITE
Arbi
Arbiter Y
(Dual Port
Memory)
t
CPU1.CLA1
Figure 7-77. uPP Integration
Note
On some TI devices, the uPP module is also called the Radio Peripheral Interface (RPI) module.
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The uPP interface supports the following:
•
•
•
•
•
•
•
•
•
•
•
Mainstream high-speed data converters with parallel conversion interface.
Mainstream high-speed streaming interface with frame START indication.
Mainstream high-speed streaming interface with data ENABLE indication.
Mainstream high-speed streaming interface with synchronization WAIT signal.
SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
Multiplexing of interleaved data in SDR transmit case.
Demultiplexing and multiplexing of interleaved data in DDR case.
I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
Single-channel 8-bit input receive or output transmit mode.
Max throughput is 50MB/s for pure read or pure write.
Available as a DSP to FPGA general-purpose streaming interface.
Figure 7-78 shows the uPP functional block diagram.
uPP
Configuration
MMR
I/F
ENABLE OUT
G
P
I
ENABLE/GPIOx
Transmit Timing
and Control
START OUT
WAIT IN
O
CLK OUT
START/GPIOx
WAIT/GPIOx
CPU1.SYSCLK
Interrupt/Trigger
CLKDIVIDER
M
U
X
CLK IN
ENABLE IN
Receive Timing
and Control
Control Mux
START IN
WAIT OUT
and
I/O
CLK/GPIOx
Arbi
I-FIFO
t
C
O
N
T
64 Bit
MEM WR I/F
DATA OUT
DATA IN
DATA[7:0]/GPIOx
Internal
Data Interleaving
(TX/RX)
DMA
Arbit
R
O
L
64 Bit
MEM RD I/F
Arbi
Q-FIFO
Figure 7-78. uPP Functional Block Diagram
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7.12.7.1 uPP Electrical Data and Timing
Section 7.12.7.1.1 shows the uPP timing requirements. Section 7.12.7.1.2 shows the uPP switching
characteristics. Figure 7-79 through Figure 7-82 show the uPP timing diagrams.
7.12.7.1.1 uPP Timing Requirements
NO.
MIN MAX UNIT
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
20
ns
40
1
tc(CLK)
Cycle time, CLK
8
ns
18
2
3
tw(CLKH)
Pulse width, CLK high
Pulse width, CLK low
8
ns
18
tw(CLKL)
4
5
6
7
8
9
tsu(STV-CLKH)
th(CLKH-STV)
tsu(ENV-CLKH)
th(CLKH-ENV)
tsu(DV-CLKH)
th(CLKH-DV)
Setup time, START valid before CLK high
Hold time, START valid after CLK high
Setup time, ENABLE valid before CLK high
Hold time, ENABLE valid after CLK high
Setup time, DATA valid before CLK high
Hold time, DATA valid after CLK high
Setup time, DATA valid before CLK low
Hold time, DATA valid after CLK low
Setup time, WAIT valid before CLK high
Hold time, WAIT valid after CLK high
Setup time, WAIT valid before CLK low
Hold time, WAIT valid after CLK low
4
0.8
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
4
0.8
4
10 tsu(DV-CLKL)
11 th(CLKL-DV)
0.8
20
0
19 tsu(WTV-CLKH)
20 th(CLKH-WTV)
21 tsu(WTV-CLKL)
22 th(CLKL-WTV)
SDR mode
SDR mode
DDR mode
DDR mode
20
0
7.12.7.1.2 uPP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN MAX UNIT
SDR mode
DDR mode
SDR mode
DDR mode
SDR mode
DDR mode
20
ns
40
12 tc(CLK)
Cycle time, CLK
8
ns
18
13 tw(CLKH)
Pulse width, CLK high
Pulse width, CLK low
8
ns
18
14 tw(CLKL)
15 td(CLKH-STV)
16 td(CLKH-ENV)
17 td(CLKH-DV)
18 td(CLKL-DV)
Delay time, START valid after CLK high
Delay time, ENABLE valid after CLK high
Delay time, DATA valid after CLK high
Delay time, DATA valid after CLK low
3
3
3
3
12
12
12
12
ns
ns
ns
ns
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CLK
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1
2
3
4
5
START
ENABLE
WAIT
6
7
8
9
DATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 7-79. uPP Single Data Rate (SDR) Receive Timing
1
2
3
CLK
4
5
START
6
7
ENABLE
WAIT
10
8
11
9
DATA[n:0]
I1 Q1 I2 Q2 I3 Q3
I4 Q4
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
Figure 7-80. uPP Double Data Rate (DDR) Receive Timing
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12
13
14
CLK
START
15
16
ENABLE
WAIT
19
20
17
DATA[n:0]
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Figure 7-81. uPP Single Data Rate (SDR) Transmit Timing
12
13
14
CLK
START
15
16
ENABLE
WAIT
21
22
17
18
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9
DATA[n:0]
I1 Q1 I2 Q2 I3 Q3
Q4
I4
Figure 7-82. uPP Double Data Rate (DDR) Transmit Timing
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8 Detailed Description
8.1 Overview
The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced
closed-loop control applications such as industrial motor drives; solar inverters and digital power; electrical
vehicles and transportation; and sensing and signal processing. Complete development packages for digital
power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives.
The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200 MHz of
signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables
fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations;
and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.
The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent
32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral
triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can
effectively double the computational performance of a real-time control system. By using the CLA to service
time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and
diagnostics.
The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC)
and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection.
Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system
consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog
signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in
conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator
Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit
conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs,
eQEPs, and other peripherals.
Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend
the connectivity of the F2837xS. The uPP interface is a new feature of the C2000 MCUs and supports high-
speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with
MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.
8.2 Functional Block Diagram
Figure 8-1 shows the CPU system and associated peripherals.
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MEMCPU1
Low-Power
Mode Control
CPU1.CLA1 to CPU1
C28 CPU-1
GPIO MUX
INTOSC1
CPU1.CLA1
User-Configurable
128x16 MSG RAM
DCSM
OTP
1K x 16
CPU1 to CPU1.CLA1
128x16 MSG RAM
PSWD
FPU
VCU-II
TMU
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
Watchdog
Main PLL
Aux PLL
Flash Bank 0
256K x 16
Secure
Flash Bank 1
256K x 16
Secure
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
Secure Memories
shown in Red
PUMP
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
Flash Wrapper for
Bank 0
Flash Wrapper for
Bank 1
INTOSC2
WD Timer
NMI-WDT
External Crystal or
Oscillator
CPU Timer 0
CPU Timer 1
CPU Timer 2
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
A5:0
B5:0
C5:2
D5:0
16-/12-bit ADC
x4
A
B
C
D
Global Shared
16x 4Kx16
GS0-GS15 RAMs
ePIE
(up to 192
AUXCLKIN
ADC
Result
Regs
Secure-ROM 32Kx16
Secure
Analog
MUX
interrupts)
TRST
Config
Boot-ROM 32Kx16
Nonsecure
TCK
TDI
JTAG
ADCIN14
ADCIN15
Data Bus
Bridge
TMS
TDO
CPU1.CLA1 Data ROM
(4Kx16)
CPU1.DMA
Comparator
Subsystem
(CMPSS)
DAC
x3
CPU1 Buses
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Data Bus
Bridge
Peripheral Frame 1
Data Bus Bridge
Peripheral Frame 2
McBSP-A/B
SCI-
USB
Ctrl /
PHY
SPI-
A/B/C
(16L FIFO)
ePWM-1/../12
HRPWM-1/../8
CAN-
A/B
(32-MBOX)
RAM
I2C-A/B
A/B/C/D
(16L FIFO)
(16L FIFO)
eCAP-
1/../6
eQEP-1/2/3
SDFM-1/2
uPP
EMIF1
EMIF2
GPIO
GPIO MUX, Input X-BAR, Output X-BAR
Figure 8-1. Functional Block Diagram
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
8.3 Memory
8.3.1 C28x Memory Map
The C28x memory map is described in Table 8-1. Memories accessible by the CLA or DMA (direct memory
access) are noted as well.
Table 8-1. C28x Memory Map
MEMORY
SIZE
1K × 16
1K × 16
512 × 16
128 × 16
128 × 16
512 × 16
512 × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
2K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
4K × 16
2K × 16
2K × 16
256K × 16
256K × 16
32K × 16
32K × 16
64 × 16
START ADDRESS
0x0000 0000
0x0000 0400
0x0000 0D00
0x0000 1480
0x0000 1500
0x0000 6C00
0x0000 6E00
0x0000 8000
0x0000 8800
0x0000 9000
0x0000 9800
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 C000
0x0000 D000
0x0000 E000
0x0000 F000
0x0001 0000
0x0001 1000
0x0001 2000
0x0001 3000
0x0001 4000
0x0001 5000
0x0001 6000
0x0001 7000
0x0001 8000
0x0001 9000
0x0001 A000
0x0001 B000
0x0004 9000
0x0004 B000
0x0008 0000
0x000C 0000
0x003F 0000
0x003F 8000
0x003F FFC0
END ADDRESS
0x0000 03FF
0x0000 07FF
0x0000 0EFF
0x0000 14FF
0x0000 157F
0x0000 6DFF
0x0000 6FFF
0x0000 87FF
0x0000 8FFF
0x0000 97FF
0x0000 9FFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
0x0000 CFFF
0x0000 DFFF
0x0000 EFFF
0x0000 FFFF
0x0001 0FFF
0x0001 1FFF
0x0001 2FFF
0x0001 3FFF
0x0001 4FFF
0x0001 5FFF
0x0001 6FFF
0x0001 7FFF
0x0001 8FFF
0x0001 9FFF
0x0001 AFFF
0x0001 BFFF
0x0004 97FF
0x0004 B7FF
0x000B FFFF
0x000F FFFF
0x003F 7FFF
0x003F FFBF
0x003F FFFF
CLA ACCESS
DMA ACCESS
M0 RAM
M1 RAM
PieVectTable
CLA to CPU MSGRAM
CPU to CLA MSGRAM
UPP TX MSG RAM
UPP RX MSG RAM
LS0 RAM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LS1 RAM
LS2 RAM
LS3 RAM
LS4 RAM
LS5 RAM
D0 RAM
D1 RAM
GS0 RAM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
GS1 RAM
GS2 RAM
GS3 RAM
GS4 RAM
GS5 RAM
GS6 RAM
GS7 RAM
GS8 RAM
GS9 RAM
GS10 RAM
GS11 RAM
GS12 RAM(1)
GS13 RAM(1)
GS14 RAM(1)
GS15 RAM(1)
CAN A Message RAM
CAN B Message RAM
Flash Bank 0
Flash Bank 1
Secure ROM
Boot ROM
Vectors
(1) Available only on F28379S, F28378S, F28377S, and F28375S.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
8.3.2 Flash Memory Map
The F28379S, F28378S, F28377S, and F28375S devices have two flash banks [512KB (256KW) each] for a
total of 1MB (512KW). Only one bank can be programmed or erased at a time. The Flash API can be executed
from RAM, or since there are two Flash banks for one CPU, the Flash API code can be executed from one bank
to erase/program the other bank. Note that an extra wait state is automatically added when code is fetched or
data is read from Bank 1 (compared to that of Bank 0), even for prefetched data. See Section 7.9.4 for details on
flash wait states. Table 1-1 shows the addresses of flash sectors on F28379S, F28378S, F28377S, and
F28375S.
Table 8-2. Addresses of Flash Sectors on F28379S, F28378S, F28377S, and F28375S
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP Sectors
TI OTP
1K x 16
1K x 16
0x0007 0000
0x0007 0800
0x0007 03FF
0x0007 0BFF
Reserved(1)
User configurable DCSM OTP
Bank 0
1K x 16
1K x 16
0x0007 8000
0x0007 8800
0x0007 83FF
0x0007 8BFF
Reserved
Bank 0 Sectors
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
8K x 16
8K x 16
8K x 16
8K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
8K x 16
8K x 16
8K x 16
8K x 16
0x0008 0000
0x0008 2000
0x0008 4000
0x0008 6000
0x0008 8000
0x0009 0000
0x0009 8000
0x000A 0000
0x000A 8000
0x000B 0000
0x000B 8000
0x000B A000
0x000B C000
0x000B E000
0x0008 1FFF
0x0008 3FFF
0x0008 5FFF
0x0008 7FFF
0x0008 FFFF
0x0009 7FFF
0x0009 FFFF
0x000A 7FFF
0x000A FFFF
0x000B 7FFF
0x000B 9FFF
0x000B BFFF
0x000B DFFF
0x000B FFFF
Bank 1 Sectors
Sector 14
Sector 15
Sector 16
Sector 17
Sector 18
Sector 19
Sector 20
Sector 21
Sector 22
Sector 23
Sector 24
Sector 25
Sector 26
Sector 27
8K x 16
8K x 16
8K x 16
8K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
8K x 16
8K x 16
8K x 16
8K x 16
0x000C 0000
0x000C 2000
0x000C 4000
0x000C 6000
0x000C 8000
0x000D 0000
0x000D 8000
0x000E 0000
0x000E 8000
0x000F 0000
0x000F 8000
0x000F A000
0x000F C000
0x000F E000
0x000C 1FFF
0x000C 3FFF
0x000C 5FFF
0x000C 7FFF
0x000C FFFF
0x000D 7FFF
0x000D FFFF
0x000E 7FFF
0x000E FFFF
0x000F 7FFF
0x000F 9FFF
0x000F BFFF
0x000F DFFF
0x000F FFFF
Flash ECC Locations
0x0107 0000
TI OTP ECC
128 x 16
0x0107 007F
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table 8-2. Addresses of Flash Sectors on F28379S, F28378S, F28377S, and F28375S (continued)
SECTOR
SIZE
START ADDRESS
END ADDRESS
Reserved
128 x 16
0x0107 0200
0x0107 027F
User-configurable DCSM OTP
ECC Bank 0
128 x 16
0x0107 1000
0x0107 107F
Reserved
128 x 16
1K x 16
1K x 16
1K x 16
1K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
1K x 16
1K x 16
1K x 16
1K x 16
1K x 16
1K x 16
1K x 16
1K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
1K x 16
1K x 16
1K x 16
1K x 16
0x0107 1200
0x0108 0000
0x0108 0400
0x0108 0800
0x0108 0C00
0x0108 1000
0x0108 2000
0x0108 3000
0x0108 4000
0x0108 5000
0x0108 6000
0x0108 7000
0x0108 7400
0x0108 7800
0x0108 7C00
0x0108 8000
0x0108 8400
0x0108 8800
0x0108 8C00
0x0108 9000
0x0108 A000
0x0108 B000
0x0108 C000
0x0108 D000
0x0108 E000
0x0108 F000
0x0108 F400
0x0108 F800
0x0108 FC00
0x0107 127F
0x0108 03FF
0x0108 07FF
0x0108 0BFF
0x0108 0FFF
0x0108 1FFF
0x0108 2FFF
0x0108 3FFF
0x0108 4FFF
0x0108 5FFF
0x0108 6FFF
0x0108 73FF
0x0108 77FF
0x0108 7BFF
0x0108 7FFF
0x0108 83FF
0x0108 87FF
0x0108 8BFF
0x0108 8FFF
0x0108 9FFF
0x0108 AFFF
0x0108 BFFF
0x0108 CFFF
0x0108 DFFF
0x0108 EFFF
0x0108 F3FF
0x0108 F7FF
0x0108 FBFF
0x0108 FFFF
Flash ECC (Sector 0)
Flash ECC (Sector 1)
Flash ECC (Sector 2)
Flash ECC (Sector 3)
Flash ECC (Sector 4)
Flash ECC (Sector 5)
Flash ECC (Sector 6)
Flash ECC (Sector 7)
Flash ECC (Sector 8)
Flash ECC (Sector 9)
Flash ECC (Sector 10)
Flash ECC (Sector 11)
Flash ECC (Sector 12)
Flash ECC (Sector 13)
Flash ECC (Sector 14)
Flash ECC (Sector 15)
Flash ECC (Sector 16)
Flash ECC (Sector 17)
Flash ECC (Sector 18)
Flash ECC (Sector 19)
Flash ECC (Sector 20)
Flash ECC (Sector 21)
Flash ECC (Sector 22)
Flash ECC (Sector 23)
Flash ECC (Sector 24)
Flash ECC (Sector 25)
Flash ECC (Sector 26)
Flash ECC (Sector 27)
(1) Any kind of access to this region may result in a spurious ECC error event.
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
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The F28376S and F28374S devices have one flash bank of 512KB (256KW) and the code to program the flash
should be executed out of RAM. See Section 7.9.4 for details on flash wait states. Table 1-1 shows the
addresses of flash sectors on F28376S and F28374S.
Table 8-3. Addresses of Flash Sectors on F28376S and F28374S
SECTOR
SIZE
START ADDRESS
END ADDRESS
OTP Sectors
Sectors
TI OTP Bank 0
1K x 16
1K x 16
0x0007 0000
0x0007 8000
0x0007 03FF
0x0007 83FF
User configurable DCSM OTP
Bank 0
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
8K x 16
8K x 16
8K x 16
8K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
32K x 16
8K x 16
8K x 16
8K x 16
8K x 16
0x0008 0000
0x0008 2000
0x0008 4000
0x0008 6000
0x0008 8000
0x0009 0000
0x0009 8000
0x000A 0000
0x000A 8000
0x000B 0000
0x000B 8000
0x000B A000
0x000B C000
0x000B E000
0x0008 1FFF
0x0008 3FFF
0x0008 5FFF
0x0008 7FFF
0x0008 FFFF
0x0009 7FFF
0x0009 FFFF
0x000A 7FFF
0x000A FFFF
0x000B 7FFF
0x000B 9FFF
0x000B BFFF
0x000B DFFF
0x000B FFFF
Flash ECC Locations
TI OTP ECC Bank 0
128 x 16
128 x 16
0x0107 0000
0x0107 1000
0x0107 007F
0x0107 107F
User-configurable DCSM OTP
ECC Bank 0
Flash ECC (Sector 0)
Flash ECC (Sector 1)
Flash ECC (Sector 2)
Flash ECC (Sector 3)
Flash ECC (Sector 4)
Flash ECC (Sector 5)
Flash ECC (Sector 6)
Flash ECC (Sector 7)
Flash ECC (Sector 8)
Flash ECC (Sector 9)
Flash ECC (Sector 10)
Flash ECC (Sector 11)
Flash ECC (Sector 12)
Flash ECC (Sector 13)
1K x 16
1K x 16
1K x 16
1K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
1K x 16
1K x 16
1K x 16
1K x 16
0x0108 0000
0x0108 0400
0x0108 0800
0x0108 0C00
0x0108 1000
0x0108 2000
0x0108 3000
0x0108 4000
0x0108 5000
0x0108 6000
0x0108 7000
0x0108 7400
0x0108 7800
0x0108 7C00
0x0108 03FF
0x0108 07FF
0x0108 0BFF
0x0108 0FFF
0x0108 1FFF
0x0108 2FFF
0x0108 3FFF
0x0108 4FFF
0x0108 5FFF
0x0108 6FFF
0x0108 73FF
0x0108 77FF
0x0108 7BFF
0x0108 7FFF
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
8.3.3 EMIF Chip Select Memory Map
The EMIF memory map is shown in Table 8-4.
Table 8-4. EMIF Chip Select Memory Map
EMIF CHIP SELECT
EMIF1_CS0n - Data
SIZE(1)
256M × 16
2M × 16
START ADDRESS
0x8000 0000
0x0010 0000
0x0030 0000
0x0038 0000
0x9000 0000
0x0000 2000
END ADDRESS
0x8FFF FFFF
0x002F FFFF
0x0037 FFFF
0x003D FFFF
0x91FF FFFF
0x0000 2FFF
CLA ACCESS DMA ACCESS
Yes
Yes
Yes
Yes
EMIF1_CS2n - Program + Data(2)
EMIF1_CS3n - Program + Data
EMIF1_CS4n - Program + Data
EMIF2_CS0n - Data
512K × 16
393K × 16
3M × 16
EMIF2_CS2n - Program + Data
4K × 16
Yes (Data only)
(1) Available memory size listed in this table is the maximum possible size assuming 32-bit memory. This may not apply to other memory
sizes because of pin mux setting. See Section 6.4.1 to find the available address lines for your use case.
(2) The 2M × 16 size is for a 32-bit interface with the assumption that 16-bit accesses are not performed; hence, byte enables are not
used (tied to active value on board). If byte enables are used, then the maximum size is smaller because byte enables are muxed with
address pins (see Section 6.4.1) . If 16-bit memory is used, then the maximum size is 1M × 16.
8.3.4 Peripheral Registers Memory Map
The peripheral registers memory map can be found in Table 8-5. Registers in the peripheral frames share a
secondary master (CLA or DMA) selection with all other registers within the same peripheral frame. See the
TMS320F2837xS Microcontrollers Technical Reference Manual for details on the CPU subsystem and
secondary master selection.
Table 8-5. Peripheral Registers Memory Map
START
ADDRESS
END
ADDRESS
CLA
DMA
REGISTERS
STRUCTURE NAME
PROTECTED(1)
ACCESS ACCESS
AdcaResultRegs
AdcbResultRegs
AdccResultRegs
AdcdResultRegs
CpuTimer0Regs
CpuTimer1Regs
CpuTimer2Regs
PieCtrlRegs (2)
ADC_RESULT_REGS
ADC_RESULT_REGS
ADC_RESULT_REGS
ADC_RESULT_REGS
CPUTIMER_REGS
CPUTIMER_REGS
CPUTIMER_REGS
PIE_CTRL_REGS
0x0000 0B00
0x0000 0B20
0x0000 0B40
0x0000 0B60
0x0000 0C00
0x0000 0C08
0x0000 0C10
0x0000 0CE0
0x0000 0B1F
0x0000 0B3F
0x0000 0B5F
0x0000 0B7F
0x0000 0C07
0x0000 0C0F
0x0000 0C17
0x0000 0CFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes – CLA
only, no
CPU
Cla1SoftIntRegs(2)
CLA_SOFTINT_REGS
0x0000 0CE0
0x0000 0CFF
access
DmaRegs
Cla1Regs
DMA_REGS
CLA_REGS
0x0000 1000
0x0000 1400
0x0000 11FF
0x0000 147F
Peripheral Frame 1
EPwm1Regs
EPwm2Regs
EPwm3Regs
EPwm4Regs
EPwm5Regs
EPwm6Regs
EPwm7Regs
EPwm8Regs
EPwm9Regs
EPwm10Regs
EPwm11Regs
EPwm12Regs
ECap1Regs
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
ECAP_REGS
0x0000 4000
0x0000 4100
0x0000 4200
0x0000 4300
0x0000 4400
0x0000 4500
0x0000 4600
0x0000 4700
0x0000 4800
0x0000 4900
0x0000 4A00
0x0000 4B00
0x0000 5000
0x0000 40FF
0x0000 41FF
0x0000 42FF
0x0000 43FF
0x0000 44FF
0x0000 45FF
0x0000 46FF
0x0000 47FF
0x0000 48FF
0x0000 49FF
0x0000 4AFF
0x0000 4BFF
0x0000 501F
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
DMA
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
Table 8-5. Peripheral Registers Memory Map (continued)
START
ADDRESS
END
ADDRESS
CLA
REGISTERS
STRUCTURE NAME
PROTECTED(1)
ACCESS ACCESS
ECap2Regs
ECap3Regs
ECap4Regs
ECap5Regs
ECap6Regs
EQep1Regs
EQep2Regs
EQep3Regs
DacaRegs
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
EQEP_REGS
EQEP_REGS
EQEP_REGS
DAC_REGS
0x0000 5020
0x0000 5040
0x0000 5060
0x0000 5080
0x0000 50A0
0x0000 5100
0x0000 5140
0x0000 5180
0x0000 5C00
0x0000 5C10
0x0000 5C20
0x0000 5C80
0x0000 5CA0
0x0000 5CC0
0x0000 5CE0
0x0000 5D00
0x0000 5D20
0x0000 5D40
0x0000 5D60
0x0000 5E00
0x0000 5E80
0x0000 503F
0x0000 505F
0x0000 507F
0x0000 509F
0x0000 50BF
0x0000 513F
0x0000 517F
0x0000 51BF
0x0000 5C0F
0x0000 5C1F
0x0000 5C2F
0x0000 5C9F
0x0000 5CBF
0x0000 5CDF
0x0000 5CFF
0x0000 5D1F
0x0000 5D3F
0x0000 5D5F
0x0000 5D7F
0x0000 5E7F
0x0000 5EFF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DacbRegs
DAC_REGS
DaccRegs
DAC_REGS
Cmpss1Regs
Cmpss2Regs
Cmpss3Regs
Cmpss4Regs
Cmpss5Regs
Cmpss6Regs
Cmpss7Regs
Cmpss8Regs
Sdfm1Regs
Sdfm2Regs
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
SDFM_REGS
SDFM_REGS
Peripheral Frame 2
McbspaRegs
McbspbRegs
SpiaRegs
MCBSP_REGS
MCBSP_REGS
SPI_REGS
0x0000 6000
0x0000 6040
0x0000 6100
0x0000 6110
0x0000 6120
0x0000 6200
0x0000 603F
0x0000 607F
0x0000 610F
0x0000 611F
0x0000 612F
0x0000 62FF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SpibRegs
SPI_REGS
SpicRegs
SPI_REGS
UppRegs
UPP_REGS
WdRegs
NmiIntruptRegs
XintRegs
WD_REGS
NMI_INTRUPT_REGS
XINT_REGS
0x0000 7000
0x0000 7060
0x0000 7070
0x0000 7200
0x0000 7210
0x0000 7220
0x0000 7230
0x0000 7300
0x0000 7340
0x0000 7400
0x0000 7480
0x0000 7500
0x0000 7580
0x0000 7900
0x0000 7920
0x0000 7940
0x0000 7980
0x0000 7A00
0x0000 7A80
0x0000 7C00
0x0000 703F
0x0000 706F
0x0000 707F
0x0000 720F
0x0000 721F
0x0000 722F
0x0000 723F
0x0000 733F
0x0000 737F
0x0000 747F
0x0000 74FF
0x0000 757F
0x0000 75FF
0x0000 791F
0x0000 793F
0x0000 794F
0x0000 798F
0x0000 7A3F
0x0000 7ABF
0x0000 7D7F
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SciaRegs
SCI_REGS
ScibRegs
SCI_REGS
ScicRegs
SCI_REGS
ScidRegs
SCI_REGS
I2caRegs
I2C_REGS
I2cbRegs
I2C_REGS
AdcaRegs
ADC_REGS
Yes
Yes
Yes
Yes
AdcbRegs
ADC_REGS
AdccRegs
ADC_REGS
AdcdRegs
ADC_REGS
InputXbarRegs
XbarRegs
INPUT_XBAR_REGS
XBAR_REGS
TrigRegs
TRIG_REGS
DmaClaSrcSelRegs
EPwmXbarRegs
OutputXbarRegs
GpioCtrlRegs
DMA_CLA_SRC_SEL_REGS
EPWM_XBAR_REGS
OUTPUT_XBAR_REGS
GPIO_CTRL_REGS
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Table 8-5. Peripheral Registers Memory Map (continued)
START
END
CLA
DMA
REGISTERS
STRUCTURE NAME
PROTECTED(1)
ADDRESS
0x0000 7F00
0x0004 0000
0x0004 7000
0x0004 7800
0x0004 8000
0x0004 A000
0x0005 0024
0x0005 D000
0x0005 D180
0x0005 D200
0x0005 D300
0x0005 E608
0x0005 F000
0x0005 F040
0x0005 F070
0x0005 F400
0x0005 F480
0x0005 F4A0
0x0005 F4C0
0x0005 F500
0x0005 F540
0x0005 F800
0x0005 FB00
0x0005 FC00
0x0005 FF00
ADDRESS
0x0000 7F2F
0x0004 0FFF
0x0004 77FF
0x0004 7FFF
0x0004 87FF
0x0004 A7FF
0x0005 0025
0x0005 D17F
0x0005 D1FF
0x0005 D2FF
0x0005 D3FF
0x0005 E60B
0x0005 F02F
0x0005 F05F
0x0005 F07F
0x0005 F47F
0x0005 F49F
0x0005 F4BF
0x0005 F4FF
0x0005 F53F
0x0005 F541
0x0005 FAFF
0x0005 FB3F
0x0005 FEFF
0x0005 FF3F
ACCESS ACCESS
GpioDataRegs
UsbaRegs
GPIO_DATA_REGS
USB_REGS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Emif1Regs
EMIF_REGS
Emif2Regs
EMIF_REGS
CanaRegs
CAN_REGS
CanbRegs
CAN_REGS
FlashPumpSemaphoreRegs
DevCfgRegs
FLASH_PUMP_SEMAPHORE_REGS
DEV_CFG_REGS
AnalogSubsysRegs
ClkCfgRegs
ANALOG_SUBSYS_REGS
CLK_CFG_REGS
CpuSysRegs
CPU_SYS_REGS
RomPrefetchRegs
DcsmZ1Regs
ROM_PREFETCH_REGS
DCSM_Z1_REGS
DcsmZ2Regs
DCSM_Z2_REGS
DcsmCommonRegs
MemCfgRegs
DCSM_COMMON_REGS
MEM_CFG_REGS
Emif1ConfigRegs
Emif2ConfigRegs
AccessProtectionRegs
MemoryErrorRegs
RomWaitStateRegs
Flash0CtrlRegs
Flash0EccRegs
Flash1CtrlRegs
Flash1EccRegs
EMIF1_CONFIG_REGS
EMIF2_CONFIG_REGS
ACCESS_PROTECTION_REGS
MEMORY_ERROR_REGS
ROM_WAIT_STATE_REGS
FLASH_CTRL_REGS
FLASH_ECC_REGS
FLASH_CTRL_REGS
FLASH_ECC_REGS
(1) The CPU (not applicable for CLA or DMA) contains a write followed by read protection mode to ensure that any read operation that
follows a write operation within a protected address range is executed as written by delaying the read operation until the write is
initiated.
(2) The address overlap of PieCtrlRegs and Cla1SoftIntRegs is correct. Each CPU, C28x and CLA, only has access to one of the register
sets.
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8.3.5 Memory Types
Table 8-6 provides more information about each memory type.
Table 8-6. Memory Types
HIBERNATE
RETENTION
ACCESS
PROTECTION
MEMORY TYPE
ECC-CAPABLE
PARITY
SECURITY
M0, M1
D0, D1
LSx
Yes
Yes
–
–
–
–
Yes
–
–
Yes
Yes
–
Yes
Yes
Yes
Yes
–
Yes
Yes
Yes
–
–
GSx
–
–
CPU/CLA MSGRAM
Boot ROM
–
Yes
–
–
–
N/A
N/A
N/A
N/A
Secure ROM
–
–
Yes
Yes
Yes
–
Flash
Yes
Yes
–
N/A
N/A
User-configurable DCSM OTP
–
8.3.5.1 Dedicated RAM (Mx and Dx RAM)
The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are
small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1
memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).
8.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called
local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU
fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these memories
with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 8-7 shows the master access for the LSx RAM.
Table 8-7. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
MSEL_LSx
CLAPGM_LSx
CPU ALLOWED ACCESS CLA ALLOWED ACCESS
COMMENT
LSx memory is configured
as CPU dedicated RAM.
00
X
All
All
–
Data Read
Data Write
LSx memory is shared
between CPU and CLA1.
01
01
0
1
Emulation Read
Emulation Write
LSx memory is CLA1
program memory.
Fetch Only
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8.3.5.3 Global Shared RAM (GSx RAM)
RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs).
Both the CPU and DMA have full read and write access to these memories.
All GSx RAM blocks have parity.
The GSx RAMs have access protection (CPU write/CPU fetch/DMA write).
8.3.5.4 CLA Message RAM (CLA MSGRAM)
These RAM blocks can be used to share data between the CPU and CLA. The CLA has read and write access
to the "CLA to CPU MSGRAM." The CPU has read and write access to the "CPU to CLA MSGRAM." The CPU
and CLA both have read access to both MSGRAMs.
This RAM has parity.
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8.4 Identification
Table 8-8 shows the Device Identification Registers.
Table 8-8. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number(1)
TMS320F28379S
TMS320F28378S
TMS320F28377S
TMS320F28376S
TMS320F28375S
TMS320F28374S
Silicon revision number
Revision B
0x**F9 0400
0x**FA 0400
0x**FF 0400
0x**FE 0400
0x**FD 0400
0x**FC 0400
PARTIDH
REVID
0x0005 D00A
2
0x0005 D00C
2
0x0000 0002
0x0000 0003
Revision C
Unique identification number. This number is different on each
individual device with the same PARTIDH. This can be used as
a serial number in the application. This number is present only
on TMS Revision C devices.
UID_UNIQUE
JTAG ID
0x0007 03CC
N/A
2
N/A
JTAG Device ID
0x0B99 C02F
(1) PARTIDH may have one of two values for each part number, with the eight most significant bits identified with '**' above being 0x00 or
0x02.
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8.5 Bus Architecture – Peripheral Connectivity
Table 8-9 shows a broad view of the peripheral and configuration register accessibility from each bus master.
Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if
SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA).
Table 8-9. Bus Master Peripheral Access
PERIPHERALS
(BY BUS ACCESS TYPE)
CPU1.DMA
CPU1.CLA1
CPU1
Peripheral Frame 1:
•
•
•
•
•
•
ePWM/HRPWM
SDFM
eCAP(1)
eQEP(1)
CMPSS(1)
DAC(1)
Y
Y
Y
Peripheral Frame 2:
•
•
•
SPI
Y
Y
Y
McBSP
uPP(1)
SCI
I2C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CAN
ADC Configuration
EMIF1
Y
Y
Y
EMIF2
USB
Device Capability, Peripheral Reset, Peripheral CPU Select
GPIO Pin Mapping and Configuration
Analog System Control
uPP Message RAMs
Y
Reset Configuration
Clock and PLL Configuration
System Configuration
(WD, NMIWD, LPM, Peripheral Clock Gating)
Y
Flash Configuration
CPU Timers
Y
Y
Y
Y
Y
DMA and CLA Trigger Source Select
GPIO Data(2)
Y
Y
ADC Results
Y
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for each CPU1 and CPU1.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2837xS Microcontrollers Technical Reference Manual for more details.
8.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features are
single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and
bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
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performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
8.6.1 Floating-Point Unit
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB)
All of the floating-point registers, except the repeat block register, are shadowed. This shadowing can be used in
high-priority interrupts for fast context save and restore of the floating-point registers.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
8.6.2 Trigonometric Math Unit
The TMU extends the capabilities of a C28x+FPU by adding instructions and leveraging existing FPU
instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-10.
Table 8-10. TMU Supported Instructions
INSTRUCTIONS
MPY2PIF32 RaH,RbH
C EQUIVALENT OPERATION
PIPELINE CYCLES
a = b * 2pi
a = b / 2pi
a = b/c
2/3
2/3
5
DIV2PIF32 RaH,RbH
DIVF32 RaH,RbH,RcH
SQRTF32 RaH,RbH
a = sqrt(b)
5
SINPUF32 RaH,RbH
COSPUF32 RaH,RbH
ATANPUF32 RaH,RbH
QUADF32 RaH,RbH,RcH,RdH
a = sin(b*2pi)
4
a = cos(b*2pi)
4
a = atan(b)/2pi
4
Operation to assist in calculating ATANPU2
5
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations. A detailed explanation of the
workings of the FPU can be found in the TMS320C28x Extended Instruction Sets Technical Reference Manual.
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8.6.3 Viterbi, Complex Math, and CRC Unit II
The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The VCU-II
extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the performance of
Fast Fourier Transforms (FFTs) and communications-based algorithms. The C28x+VCU-II supports the following
algorithm types:
•
Viterbi Decoding
Viterbi decoding is commonly used in baseband communications applications. The Viterbi decode algorithm
consists of three main parts: branch metric calculations, compare-select (Viterbi butterfly), and a traceback
operation. Table 8-11 shows a summary of the VCU performance for each of these operations.
Table 8-11. Viterbi Decode Performance
VITERBI OPERATION
Branch Metric Calculation (code rate = 1/2)
Branch Metric Calculation (code rate = 1/3)
Viterbi Butterfly (add-compare-select)
Traceback per Stage
VCU CYCLES
1
2p
2(1)
3(2)
(1) C28x CPU takes 15 cycles per butterfly.
(2) C28x CPU takes 22 cycles per stage.
•
•
Cyclic Redundancy Check
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
Complex Math
Complex math is used in many applications, a few of which are:
– Fast Fourier Transform
The complex FFT is used in spread spectrum communications, as well as in many signal processing
algorithms.
– Complex filters
Complex filters improve data reliability, transmission distance, and power efficiency. The C28x+VCU can
perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In addition, the C28x
+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a single cycle.
Table 8-12 shows a summary of the VCU operations enabled by the VCU.
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Table 8-12. Complex Math Performance
COMPLEX MATH OPERATION
Add or Subtract
VCU CYCLES
NOTES
32 +/- 32 = 32-bit (Useful for filters)
16 +/- 32 = 15-bit (Useful for FFT)
16 x 16 = 32-bit
1
1
Add or Subtract
Multiply
2p
Multiply and Accumulate (MAC)
RPT MAC
2p
32 + 32 = 32-bit, 16 x 16 = 32-bit
2p+N
Repeat MAC. Single cycle after the first operation.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
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8.7 Control Law Accelerator
The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism,
and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such
as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion. When a
task completes, the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next
highest-priority pending task. The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP,
Comparator and DAC registers. Dedicated message RAMs provide a method to pass additional data between
the main CPU and the CLA.
Figure 8-2 shows the CLA block diagram.
CLA Control
Register Set
CLA_INT1
MIFR(16)
From
Shared
Peripherals
MPERINT1
to
MPERINT8
to
CLA_INT8
MIOVF(16)
MICLR(16)
MICLROVF(16)
MIFRC(16)
MIER(16)
C28x
CPU
INT11
INT12
PIE
MIRUN(16)
LVF
LUF
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
SYSCLK
CLA Clock Enable
SYSRSn
CPU Read/Write Data Bus
CLA Program
Memory (LSx)
CLA Program Bus
MCTL(16)
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
CLA Data
Memory (LSx)
CLA Execution
Register Set
MPC(16)
CLA Message
RAMs
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
Shared
Peripherals
MEALLOW
MAR0(16)
MAR1(16)
CPU Read Data Bus
Figure 8-2. CLA Block Diagram
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8.8 Direct Memory Access
The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring
data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for
other system functions. Additionally, the DMA has the capability to orthogonally rearrange the data as it is
transferred as well as “ping-pong” data between buffers. These features are useful for structuring data into
blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start a DMA
transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the interrupt
trigger source, there is no mechanism within the module itself to start memory transfers periodically. The
interrupt trigger source for each of the six DMA channels can be configured separately and each channel
contains its own independent PIE interrupt to let the CPU know when a DMA transfer has either started or
completed. Five of the six channels are exactly the same, while Channel 1 has the ability to be configured at a
higher priority than the others.
DMA features include:
•
•
Six channels with independent PIE interrupts
Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– Multichannel buffered serial port transmit and receive
– External interrupts
– CPU timers
– EPWMxSOC signals
– SPIx transmit and receive
– SDFM
– Software trigger
•
Data sources and destinations:
– GSx RAM
– ADC result registers
– ePWMx
– SPI
– McBSP
– EMIF
•
•
Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
Throughput: four cycles/word (without arbitration)
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Figure 8-3 shows a device-level block diagram of the DMA.
ADC
WRAPPER
(4)
ADC
RESULTS
(4)
Global Shared
16x 4Kx16
GS0-15 RAMs
XINT
(5)
TIMER
(3)
C28x Bus
DMA Bus
TINT (0-2)
XINT (1-5)
DMA Trigger
Source Selection
ADC INT (A-D) (1-4), EVT (A-D)
SDxFLTy (x = 1 to 2, y = 1 to 4)
SOCA (1-12), SOCB (1-12)
MXEVT (A-B), MREVT (A-B)
SPITX (A-C), SPIRX (A-C)
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA
C28x
PIE
DMA Trigger Source
CPU and DMA Data Path
SDFM
(8)
EPWM McBSP
(12)
(2)
SPI
EMIF1
(3)
Figure 8-3. DMA Block Diagram
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8.9 Boot ROM and Peripheral Booting
The device boot ROM contains bootloading software. The device boot ROM is executed each time the device
comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to boot the
device through one of the bootable peripherals by configuring the boot mode GPIO pins.
Table 8-13 shows the possible boot modes supported on the device. The default boot mode pins are GPIO72
(boot mode pin 1) and GPIO 84 (boot mode pin 0). Users may choose to have weak pullups for boot mode pins if
they use a peripheral on these pins as well, so the pullups can be overdriven. On this device, customers can
change the factory default boot mode pins by programming user-configurable Dual Code Security Module
(DCSM) OTP locations. This is recommended only for cases in which the factory default boot mode pins do not
fit into the customer design. More details on the locations to be programmed is available in the TMS320F2837xS
Microcontrollers Technical Reference Manual .
Table 8-13. Device Boot Mode
GPIO72
(BOOT
MODE
PIN 1)
GPIO84
(BOOT
MODE
PIN 0)
MODE NO.
CPU1 BOOT MODE
TRST
0
1
Parallel I/O
SCI Mode
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
2
Wait Boot Mode
Get Mode
3
4-7
EMU Boot Mode (JTAG debug probe connected)
Note
The default behavior of Get mode is boot-to-flash. On unprogrammed devices, using Get mode will
result in repeated watchdog resets, which may prevent proper JTAG connection and device
initialization. Use Wait mode or another boot mode for unprogrammed devices.
CAUTION
Some reset sources are internally driven by the device. The user must ensure the pins used for boot
mode are not actively driven by other devices in the system for these cases. The boot configuration
has a provision for changing the boot pins in OTP. For more details, see the TMS320F2837xS
Microcontrollers Technical Reference Manual .
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8.9.1 EMU Boot or Emulation Boot
The CPU enters this boot when it detects that TRST is HIGH (that is, when a JTAG debug probe/debugger is
connected). In this mode, the user can program the EMU_BOOTCTRL control-word (at location 0xD00) to
instruct the device on how to boot. If the contents of the EMU_BOOTCTRL location are invalid, then the device
would default to WAIT Boot mode. The emulation boot allows users to verify the device boot before
programming the boot mode into OTP. Note that EMU_BOOTCTRL is not actually a register, but refers to a
location in RAM (PIE RAM). PIE RAM starts at 0xD00, but the first few locations are reserved (when initializing
the PIE vector table in application code) for these boot ROM variables.
8.9.2 WAIT Boot Mode
The device in this boot mode loops in the boot ROM. This mode is useful if users want to connect a debugger on
a secure device or if users do not want the device to execute an application in flash yet.
8.9.3 Get Mode
The default behavior of Get mode is boot-to-flash. This behavior can be changed by programming the Zx-
OTPBOOTCTRL locations in user configurable DCSM OTP. The user configurable DCSM OTP on this device is
divided in to two secure zones: Z1 and Z2. The Get mode function in boot ROM first checks if a valid
OTPBOOTCTRL value is programmed in Z1. If the answer is yes, then the device boots as per the Z1-
OTPBOOTCTRL location. The Z2-OTPBOOTCTRL location is read and decodes only if Z1-OTPBOOTCTRL is
invalid or not programmed. If either Zx-OTPBOOTCTRL location is not programmed, then the device defaults to
factory default operation, which is to use factory default boot mode pins to boot to flash if the boot mode pins are
set to GET MODE. Users can choose the device through which to boot—SPI, I2C, CAN, and USB—by
programming proper values into the user configurable DCSM OTP. More details on this can be found in the
TMS320F2837xS Microcontrollers Technical Reference Manual .
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8.9.4 Peripheral Pins Used by Bootloaders
Table 8-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs for
each mode, as shown in Table 8-14.
Table 8-14. GPIO Pins Used by Each Peripheral Bootloader
BOOTLOADER
GPIO PINS
NOTES
SCITXDA: GPIO84
SCIRXDA: GPIO85
SCIA Boot I/O option 1 (default SCI option
when chosen through Boot Mode GPIOs)
SCI-Boot0
SCI-Boot1
SCIRXDA: GPIO28
SCITXDA: GPIO29
SCIA Boot option 2 – with alternate I/Os.
D0 – GPIO65
D1 – GPIO64
D2 – GPIO58
D3 – GPIO59
D4 – GPIO60
D5 – GPIO61
Parallel Boot
D6 – GPIO62
D7 – GPIO63
HOST_CTRL – GPIO70
DSP_CTRL – GPIO69
CANRXA: GPIO70
CANTXA: GPIO71
CAN-Boot0
CAN-Boot1
I2C-Boot0
I2C-Boot1
CAN-A Boot – I/O option 1
CAN-A Boot – I/O option 2
I2CA Boot – I/O option 1
I2CA Boot – I/O option 2
CANRXA: GPIO62
CANTXA: GPIO63
SDAA: GPIO91
SCLA: GPIO92
SDAA: GPIO32
SCLA: GPIO33
SPISIMOA - GPIO58
SPISOMIA - GPIO59
SPICLKA - GPIO60
SPISTEA - GPIO61
SPI-Boot0
SPI-Boot1
SPIA Boot – I/O option 1
SPIA Boot – I/O option 2
SPISIMOA – GPIO16
SPISOMIA – GPIO17
SPICLKA – GPIO18
SPISTEA – GPIO19
The USB Bootloader will switch the clock
source to the external crystal oscillator (X1
and X2 pins). A 20-MHz crystal should be
present on the board if this boot mode is
selected.
USB0DM - GPIO42
USB0DP - GPIO43
USB Boot
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8.10 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CSS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (CLA, LSx RAM, and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each zone
is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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8.11 Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
•
SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
AUXPLLCLK
8.12 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
The NMIWD module is used to handle system-level errors. The conditions monitored are:
•
•
•
Missing system clock due to oscillator failure
Uncorrectable ECC error on CPU access to flash memory
Uncorrectable ECC error on CPU, CLA, or DMA access to RAM
If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a
programmable time interval. The default time is 65536 SYSCLK cycles.
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8.13 Watchdog
The watchdog module is the same as the one on previous TMS320C2000™ MCUs, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backwards-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 8-4 shows the various functional blocks within the watchdog module.
WDCR(WDPS(2:0))
WDCR(WDDIS)
WDCNTR(7:0)
Watchdog
Prescaler
1-count
delay
WDCLK
(INTOSC1)
8-bit
Watchdog
Counter
Overflow
/512
SYSRSn
Clear
Count
WDWCR(MIN(7:0))
WDKEY(7:0)
Watchdog
Window
Detector
Watchdog
Key Detector
55 + AA
Good Key
Bad Key
Out of Window
Generate
512-WDCLK
Output Pulse
WDRSTn
WDINTn
Watchdog Time-out
SCSR(WDENINT)
Figure 8-4. Windowed Watchdog
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8.14 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware package
(C2000Ware_2_00_00_03 and higher):
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User Guide
How to Design with the C2000™ CLB Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ CLB Application Report
The CLB module and its interconnects are shown in Figure 8-5.
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Figure 8-5. CLB Overview
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality. See
Table 5-1 for the devices that support the CLB feature.
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8.15 Functional Safety
TMS320C2000™ MCUs are equipped with a TI release validation-based C28x and CLA Compiler Qualification
Kit (CQ-Kit), which is available for free and may be requested at the Compiler Qualification Kit web page.
Additionally, C2000™ MCUs are supported by the TI C2000 Support from Embedded Coder from MathWorks® to
generate C2000-optimized code from a Simulink® model. Simulink® enables Model-Based Design to ease the
systematic compliance process with certified tools, including Embedded Coder®, Simulink® model verification
tools, Polyspace® code verification tools, and the IEC Certification Kit for ISO 26262 and IEC 61508 compliance.
For more information, see the How to Use Simulink for ISO 26262 Projects article.
The Error Detection in SRAM Application Report provides technical information about the nature of the SRAM bit
cell and bit array, as well as the sources of SRAM failures. It then presents methods for managing memory
failures in electronic systems. This discussion is intended for electronic system developers or integrators who
are interested in improving the robustness of the embedded SRAM.
Functional Safety-Compliant products are developed using an ISO 26262/IEC 61508-compliant hardware
development process that is independently assessed and certified to meet ASIL D/SIL 3 systematic capability
(see certificate). The TMS320F2837D, TMS320F2837xS, and TMS320F2807x MCUs have been certified to
meet a component-level random hardware capability of ASIL B/SIL 2 (see certificate).
The Functional Safety-Compliant enablers include:
•
•
•
•
A Functional Safety Manual
A detailed, tunable, quantitative Failure Modes, Effects, and Diagnostics Analysis (FMEDA)
A software diagnostic library that will help shorten the time to implement various software safety mechanisms
A collection of application reports to help in the development of functionally safe systems.
A functional safety manual that describes all of the hardware and software functional safety mechanisms is
available. See the Safety Manual for TMS320F2837xD, TMS320F2837xS, and TMS320F2807x.
A detailed, tunable, fault-injected, quantitative FMEDA that enables the calculation of random hardware metrics
—as outlined in the International Organization for Standardization ISO 26262 and the International
Electrotechnical Commission IEC 61508 for automotive and industrial applications, respectively—is also
available. This tunable FMEDA must be requested; see the C2000™ Package for Automotive and Industrial
MCUs User's Guide.
•
A white paper outlining the value (or benefit) of a tunable FMEDA is available. See the Functional Safety: A
tunable FMEDA for C2000™ MCUs publication.
•
Parts 1 and 2 of a five-part FMEDA tuning training are available. See the C2000™ Tunable FMEDA Training
page.
Parts 3, 4, and 5 are packaged with the tunable FMEDA, and must be requested.
The C2000 Diagnostic Software Library is a collection of different safety mechanisms designed to detect faults.
These safety mechanisms target different device components, including the C28x core, the control law
accelerator (CLA), system control, static random access memory (SRAM), flash, and communications and
control peripherals. The software safety mechanisms leverage available hardware safety features such as the
C28x hardware built-in self-test (HWBIST); error detection and correction functionality on memories; parallel
signature analysis circuitry; missing clock detection logic; watchdog counters; and hardware redundancy.
Also included are software functional safety manual, user guides, example projects, and source code to help
users shorten system integration time. The library package includes a compliance support package (CSP), a
series of documents that TI used to develop and test the diagnostic software library. The CSP provides the
necessary documentation and reports to assist users with compliance to functional safety standards: software
safety requirements specifications; a software architecture document; software module design documents;
software module unit test plans; software module unit test documents; static analysis reports; unit test reports;
dynamic analysis reports; functional test reports; and traceability documents. Users can use these documents to
comply with route 1s (as described in IEC 61508-3, section 7.4.2.12) to reuse a preexisting software element to
implement all or part of a safety function. The contents of the CSP could also help users make important
decisions for overall system safety compliance.
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Two application reports offer details about how to develop functionally safe systems with C2000 real-time control
devices:
•
C2000™ Hardware Built-In Self-Test discusses the HWBIST safety mechanism, along with its functions and
features, in the F2807x/F2837xS/F2837xD series of C2000 devices. The report also addresses some
system-level considerations when using the HWBIST feature and explains how customers can use the
diagnostic library on their system.
•
C2000™ CPU Memory Built-In Self-Test describes embedded memory validation using the C28x central
processing unit (CPU) during an active control loop. It discusses system challenges to memory validation as
well as the different solutions provided by C2000 devices and software. Finally, it presents the Diagnostic
Library implementations for memory testing.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Industrial Servo Drive and AC Inverter Drive Reference Design
The DesignDRIVE Development Kit is a reference design for a complete industrial drive directly connecting to a
three-phase ACI or PMSM motor. Many drive topologies can be created from the combined control, power, and
communications technologies included on this single platform. This platform includes multiple position sensor
interfaces, diverse current sensing techniques, hot-side partitioning options, and expansion for safety and
industrial Ethernet.
Differential Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors
This design provides a 4-channel signal conditioning solution for differential ADCs integrated into a
microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative measurement
circuit with external differential SAR ADCs as well as circuits for high-speed overcurrent and earth fault
detection. Proper differential signal conditioning improves noise immunity on critical current measurements in
motor drives. This reference design can help increase the effective resolution of the analog-to-digital conversion,
improving motor drive efficiency.
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10 Device and Documentation Support
10.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28379S). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PTP) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2837xS MCUs
Silicon Errata .
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
Figure 10-1. Device Nomenclature
10.2 Markings
Figure 10-2 provides an example of the 2837xS device markings and defines each of the markings. The device
revision can be determined by the symbols marked on the top of the package as shown in Figure 10-2. Some
prototype devices may have markings different from those illustrated.
=
YMLLLLS
Lot Trace Code
=
=
=
=
=
YM
LLLL
S
$$
#
2-Digit Year/Month Code
Assembly Lot
Assembly Site Code
Wafer Fab Code as applicable
Silicon Revision Code
TMS320
F28379SPTPT
$$#-YMLLLLS
G4
=
G4
Green (Low Halogen and RoHS-compliant)
Package
Pin 1
Figure 10-2. Example of Device Markings
Table 10-1. Determining Silicon Revision From Lot Trace Code
REVID(1)
Address: 0x5D00C
SILICON REVISION CODE
SILICON REVISION
COMMENTS
B
C
B
C
0x0002
This silicon revision is available as TMX.
This silicon revision is available as TMS.
0x0003
(1) Silicon Revision ID
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
F28379D controlCARD for C2000 Real time control development kits
The F28379D controlCARD from Texas Instruments is Position Manager-ready and an ideal product for initial
software development and short run builds for system prototypes, test stands, and many other projects that
require easy access to high-performance controllers. All C2000 controlCARDs are complete board-level modules
that utilize a HSEC180 or DIMM100 form factor to provide a low-profile single-board controller solution. The host
system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional.
F28379D Experimenter Kit
C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop
control development with Texas Instruments C2000 32-bit microcontroller family. This platform is a great tool to
customize and prove-out solutions for many common power electronics applications, including motor control,
digital power supplies, solar inverters, digital LED lighting, precision sensing, and more.
Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is now the
recommended content delivery tool versus controlSUITE™.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
F021 Flash Application Programming Interface (API)
The F021 Flash Application Programming Interface (API) provides a software library of functions to program,
erase, and verify F021 on-chip Flash memory.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific F2837xD/F2837xS/F2807x hands-on training resources can be found at C2000™ MCU Device
Workshops.
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2837xS MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F2837xS Microcontrollers Technical Reference Manual details the integration, the environment, the
functional description, and the programming models for each peripheral and subsystem in the 2837xS
microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 209
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
10.6 Trademarks
PowerPAD™, C2000™, Code Composer Studio™, TMS320C2000™, TMS320™, controlSUITE™, TI E2E™ are
trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
MathWorks®, Simulink®, Embedded Coder®, Polyspace® are registered trademarks of The MathWorks, Inc.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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211
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
PACKAGE OUTLINE
PZP0100N
PowerPADTM TQFP - 1.2 mm max height
SCALE 1.000
PLASTIC QUAD FLATPACK
14.2
13.8
NOTE 3
B
PIN 1 ID
100
76
1
75
14.2
13.8
NOTE 3
16.2
TYP
15.8
25
51
26
50
A
0.27
0.17
100X
96X 0.5
0.08
C A B
4X 12
C
SEATING PLANE
1.2 MAX
SEE DETAIL A
(0.127)
TYP
26
50
25
51
0.25
GAGE PLANE
(1)
0.15
0.05
8.64
7.45
101
0.08 C
0 -7
0.75
0.45
DETAIL A
TYPICAL
4X (0.3)
NOTE 4
4X (0.3)
NOTE 4
1
75
100
76
4223383/A 04/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features may not be present.
5. Reference JEDEC registration MS-026.
DETAIL
A
S
C
A
L
E
:
1
4
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
EXAMPLE BOARD LAYOUT
PZP0100N
PowerPADTM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
( 12)
NOTE 10
(
8.64)
SYMM
SOLDER MASK
DEFINED PAD
100
76
100X (1.5)
1
75
100X (0.3)
96X (0.5)
SYMM
101
(1) TYP
(15.4)
(R0.05) TYP
51
25
(
0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
26
50
SEE DETAILS
(1) TYP
(15.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:5X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223383/A 04/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,
plugged or tented.
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 213
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
EXAMPLE STENCIL DESIGN
PZP0100N
PowerPADTM TQFP - 1.2 mm max height
PLASTIC QUAD FLATPACK
(
8.64)
BASED ON
0.125 THICK STENCIL
SYMM
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
100
76
100X (1.5)
1
75
100X (0.3)
96X (0.5)
SYMM
101
(15.4)
(R0.05) TYP
25
51
METAL COVERED
BY SOLDER MASK
26
50
(15.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
9.66 X 9.66
8.64 X 8.64 (SHOWN)
7.89 X 7.89
0.125
0.150
0.175
7.3 X 7.3
4223383/A 04/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
PACKAGE OUTLINE
TM
PowerPAD HLQFP - 1.6 mm max height
PTP0176F
SCALE 0.550
PLASTIC QUAD FLATPACK
24.2
23.8
NOTE 3
B
PIN 1 ID
133
176
1
132
24.2
23.8
NOTE 3
26.2
25.8
TYP
44
89
88
45
0.27
0.17
176X
C
A
172X 0.5
0.08
C A B
4X 21.5
SEATING PLANE
1.6 MAX
SEE DETAIL A
(0.13)
TYP
45
88
89
44
0.25
GAGE PLANE
(1.4)
4X 0.78 MAX
NOTE 4
4X
0.54 MAX
NOTE 4
0.15
0.05
0.08 C
7.33
6.78
0 -7
177
0.75
0.45
DETAIL A
TYPICAL
4X
0.2 MAX
NOTE 4
EXPOSED
THERMAL PAD
1
132
176
133
8.07
7.53
4223382/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Strap features my not present.
5. Reference JEDEC registration MS-026.
www.ti.com
DETAIL
A
S
C
A
L
E
:
1
2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 215
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
www.ti.com
EXAMPLE BOARD LAYOUT
PowerPADTM HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
(8.07)
SYMM
SOLDER MASK
DEFINED PAD
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
177
SYMM
(7.33)
(1.5 TYP)
(25.5)
( 22)
NOTE 10
(R0.05) TYP
(
0.2) TYP
VIA
89
44
SEE DETAILS
45
88
METAL COVERED
BY SOLDER MASK
(1.5 TYP)
(25.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223382/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,
Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
10. Size of metal pad may vary due to creepage requirement.
Copyright © 2021 Texas Instruments Incorporated
216 Submit Document Feedback
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
TMS320F28379S, TMS320F28378S, TMS320F28377S, TMS320F28377S-Q1
TMS320F28376S, TMS320F28375S, TMS320F28375S-Q1, TMS320F28374S
www.ti.com
SPRS881J – AUGUST 2014 – REVISED FEBRUARY 2021
EXAMPLE STENCIL DESIGN
PowerPADTM HLQFP - 1.6 mm max height
PTP0176F
PLASTIC QUAD FLATPACK
(8.07)
BASED ON
0.125 THICK STENCIL
SYMM
176
133
176X (1.45)
1
132
176X (0.3)
172X (0.5)
(25.5)
(7.33)
BASED ON
SYMM
177
0.125 THICK
STENCIL
(R0.05) TYP
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
44
89
METAL COVERED
BY SOLDER MASK
45
88
(25.5)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:4X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
9.02 X 8.2
8.07 X 7.33 (SHOWN)
7.37 X 6.69
0.125
0.150
0.175
6.82 X 6.2
4223382/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 217
Product Folder Links: TMS320F28379S TMS320F28378S TMS320F28377S TMS320F28377S-Q1
TMS320F28376S TMS320F28375S TMS320F28375S-Q1 TMS320F28374S
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
PTP
PTP
PTP
PZP
PZP
ZWT
ZWT
ZWT
PTP
PTP
PZP
PZP
PZP
PZP
ZWT
ZWT
PTP
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F28374SPTPS
TMS320F28374SPTPSR
TMS320F28374SPTPT
TMS320F28374SPZPS
TMS320F28374SPZPT
TMS320F28374SZWTS
TMS320F28374SZWTT
TMS320F28374SZWTTR
TMS320F28375SPTPS
TMS320F28375SPTPT
TMS320F28375SPZPQ
TMS320F28375SPZPQR
TMS320F28375SPZPS
TMS320F28375SPZPT
TMS320F28375SZWTS
TMS320F28375SZWTT
TMS320F28376SPTPS
ACTIVE
HLQFP
HLQFP
HLQFP
HTQFP
HTQFP
NFBGA
NFBGA
NFBGA
HLQFP
HLQFP
HTQFP
HTQFP
HTQFP
HTQFP
NFBGA
NFBGA
HLQFP
176
176
176
100
100
337
337
337
176
176
100
100
100
100
337
337
176
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
TMS320
F28374SPTPS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
200
40
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
TMS320
F28374SPTPS
TMS320
F28374SPTPT
90
TMS320
F28374SPZPS
90
TMS320
F28374SPZPT
90
TMS320
F28374SZWTS
90
TMS320
F28374SZWTT
1000 RoHS & Green
TMS320
F28374SZWTT
40
40
90
RoHS & Green
RoHS & Green
RoHS & Green
TMS320
F28375SPTPS
TMS320
F28375SPTPT
TMS320
F28375SPZPQ
1000 RoHS & Green
TMS320
F28375SPZPQ
90
90
90
90
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
TMS320
F28375SPZPS
TMS320
F28375SPZPT
TMS320
F28375SZWTS
TMS320
F28375SZWTT
TMS320
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F28376SPTPS
TMS320F28376SPTPT
TMS320F28376SPZPS
TMS320F28376SPZPT
TMS320F28376SZWTS
TMS320F28376SZWTT
TMS320F28377SPTPQ
TMS320F28377SPTPS
TMS320F28377SPTPT
TMS320F28377SPZPQ
TMS320F28377SPZPS
TMS320F28377SPZPT
TMS320F28377SZWTQ
TMS320F28377SZWTS
TMS320F28377SZWTT
TMS320F28378SPTPS
TMS320F28378SPZPS
TMS320F28379SPTPS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HLQFP
HTQFP
HTQFP
NFBGA
NFBGA
HLQFP
HLQFP
HLQFP
HTQFP
HTQFP
HTQFP
NFBGA
NFBGA
NFBGA
HLQFP
HTQFP
HLQFP
PTP
PZP
PZP
ZWT
ZWT
PTP
PTP
PTP
PZP
PZP
PZP
ZWT
ZWT
ZWT
PTP
PZP
PTP
176
100
100
337
337
176
176
176
100
100
100
337
337
337
176
100
176
40
90
90
90
90
40
40
40
90
90
90
90
90
90
40
90
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 125
TMS320
F28376SPTPT
TMS320
F28376SPZPS
TMS320
F28376SPZPT
TMS320
F28376SZWTS
TMS320
F28376SZWTT
TMS320
F28377SPTPQ
TMS320
F28377SPTPS
TMS320
F28377SPTPT
TMS320
F28377SPZPQ
TMS320
F28377SPZPS
TMS320
F28377SPZPT
TMS320
F28377SZWTQ
TMS320
F28377SZWTS
TMS320
F28377SZWTT
TMS320
F28378SPTPS
TMS320
F28378SPZPS
TMS320
F28379SPTPS
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
40
90
90
90
90
(1)
(2)
(3)
(4/5)
(6)
TMS320F28379SPTPT
TMS320F28379SPZPS
TMS320F28379SPZPT
TMS320F28379SZWTS
TMS320F28379SZWTT
ACTIVE
HLQFP
HTQFP
HTQFP
NFBGA
NFBGA
PTP
176
100
100
337
337
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
TMS320
F28379SPTPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PZP
NIPDAU
NIPDAU
SNAGCU
SNAGCU
TMS320
F28379SPZPS
PZP
TMS320
F28379SPZPT
ZWT
ZWT
TMS320
F28379SZWTS
TMS320
F28379SZWTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE OUTLINE
ZWT0337A
NFBGA - 1.4 mm max height
SCALE 0.950
PLASTIC BALL GRID ARRAY
16.1
15.9
A
B
BALL A1 CORNER
16.1
15.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
TYP
14.4 TYP
SYMM
(0.8) TYP
(0.8) TYP
W
V
U
T
R
P
N
M
L
14.4
TYP
SYMM
K
J
H
G
F
0.55
337X
0.45
E
D
C
0.15
0.05
C A B
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
0.8 TYP
0.8 TYP
BALL A1 CORNER
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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