TMS320LC2401A [TI]
DSP CONTROLLERS; DSP控制器
| 型号： | TMS320LC2401A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DSP CONTROLLERS |
| 文件： | 总88页 (文件大小：1319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
D
D
High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
D
Small Foot-Print (7 mm × 7 mm) Ideally
Suited for Space-Constrained Applications
D
Watchdog (WD) Timer Module
− Low-Power 3.3-V Design
D
10-Bit Analog-to-Digital Converter (ADC)
− 5 Multiplexed Input Channels
− 500 ns Minimum Conversion Time
− Selectable Twin 8-State Sequencers
Triggered by Event Manager
Based on TMS320C2xx DSP CPU Core
− Code-Compatible With 240x and
F243/F241/C242
− Instruction Set Compatible With
F240/C240
D
D
D
Serial Communications Interface (SCI)
D
On-Chip Memory
Phase-Locked-Loop (PLL)-Based Clock
Generation
− Up to 8K Words x 16 Bits of Flash
EEPROM (2 Sectors) (LF2401A)
− 8K Words x 16 Bits of ROM (LC2401A)
− Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
− Up to 1K Words x 16 Bits of
Data/Program RAM
Up to 13 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
D
D
User-Selectable Dual External Interrupts
(XINT1 and XINT2)
− 544 Words of Dual-Access RAM
− Up to 512 Words of Single-Access
RAM
Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral
Independently
D
D
Boot ROM
− SCI Bootloader
D
D
Real-Time JTAG-Compliant Scan-Based
Event-Manager (EV) Module (EVA), Which
Includes:
†
Emulation, IEEE Standard 1149.1 (JTAG)
Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
− Two 16-Bit General-Purpose Timers
− Seven 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM
Channels
− Emergency PWM Channel Shutdown
With External PDPINTA Pin
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
− One Capture Unit for Time-Stamping of
External Events
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control
Support
D
D
32-Pin VF Low-Profile Quad Flatpack
(LQFP)
Temperature Range: − 40°C to 85°C
− Input Qualifier for Select Pins
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.
ꢎꢑ ꢏ ꢍꢓ ꢌ ꢀꢔ ꢏ ꢐ ꢍ ꢊꢀꢊ ꢕꢖ ꢗ ꢘꢙ ꢚ ꢛꢜ ꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜ ꢕꢘꢖ ꢤꢛ ꢜꢠ ꢥ
ꢎꢙ ꢘ ꢤꢟꢞ ꢜ ꢝ ꢞ ꢘꢖ ꢗꢘ ꢙ ꢚ ꢜ ꢘ ꢝ ꢡꢠ ꢞ ꢕꢗ ꢕꢞꢛ ꢜꢕ ꢘꢖꢝ ꢡꢠ ꢙ ꢜꢦ ꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢀꢠꢧ ꢛꢝ ꢔꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ
ꢝ ꢜ ꢛ ꢖꢤ ꢛ ꢙꢤ ꢨ ꢛ ꢙꢙ ꢛ ꢖ ꢜꢩꢥ ꢎꢙ ꢘ ꢤꢟꢞ ꢜꢕꢘꢖ ꢡꢙ ꢘꢞ ꢠꢝ ꢝꢕ ꢖꢪ ꢤꢘꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢩ ꢕꢖꢞ ꢣꢟꢤ ꢠ
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
Copyright 2004, Texas Instruments Incorporated
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240xA device summary . . . . . . . . . . . . . . . .
functional block diagram of the LF2401A DSP
controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block diagram of the LC2401A DSP
controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
constraints while emulating with JTAG port pins and
3
4
clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
watchdog (WD) timer module . . . . . . . . . . . . . . . . . . . 48
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
device and development support tool nomenclature 52
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . 54
LF2401A AND LC2401A electrical
5
6
8
specifications data . . . . . . . . . . . . . . . . . . . . . . . . . 56
absolute maximum ratings over operating
case temperature range . . . . . . . . . . . . . . . . . . . 56
recommended operating conditions . . . . . . . . . . . . . . 56
electrical characteristics over recommended
operating case temperature range . . . . . . . . . . 57
current consumption graphs . . . . . . . . . . . . . . . . . . . . 59
reducing current consumption . . . . . . . . . . . . . . . . . . . 59
PARAMETER MEASUREMENT INFORMATION . . 60
external reference crystal/clock with PLL circuit
GPIO functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
in-circuit emulation options . . . . . . . . . . . . . . . . . . . . . 17
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . 20
device reset and interrupts . . . . . . . . . . . . . . . . . . . . . . 21
DSP CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TMS320Lx2401A instruction set . . . . . . . . . . . . . . . . . 24
scan-based emulation . . . . . . . . . . . . . . . . . . . . . . . . . . 25
functional block diagram of the 2401A DSP CPU . . 26
2401A legend for the internal hardware . . . . . . . . . . 27
status and control registers . . . . . . . . . . . . . . . . . . . . . 28
central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . 29
internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
dual-access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . 33
single-access RAM (SARAM) . . . . . . . . . . . . . . . . . . . 33
ROM (LC2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash EEPROM (LF2401A) . . . . . . . . . . . . . . . . . . . . . 33
boot ROM† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Flash/ROM security . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
event manager module (EVA) . . . . . . . . . . . . . . . . . . . 36
enhanced analog-to-digital converter (ADC) module 40
serial communications interface (SCI) module . . . . . 42
PLL-based clock module . . . . . . . . . . . . . . . . . . . . . . . 44
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
timing with the PLL circuit enabled . . . . . . . . . . . . . . . 62
switching characteristics over recommended
operating conditions [H = 0.5 tc(CO)] . . . . . . . . . 62
timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
RS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
low-power mode timing . . . . . . . . . . . . . . . . . . . . . . . . . 66
LPM2 wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PWM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
capture timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
general-purpose input/output timing . . . . . . . . . . . . . . 72
10-bit analog-to-digital converter (ADC) . . . . . . . . . . . 73
migrating from other 240xA devices to Lx2401A . . . 75
peripheral register description . . . . . . . . . . . . . . . . . . . 77
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
description
†
The TMS320Lx2401A device, a new member of the TMS320C24x generation of digital signal processor
(DSP) controllers, is part of the TMS320C2000 platform of fixed-point DSPs. The Lx2401A device offers the
enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and
high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and
motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing 240x and C24x DSP controller devices, the Lx2401A offers increased
processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device
Summary section for device-specific features.
The Lx2401A device offers a peripheral suite tailored to meet the specific price/performance points required
by various applications. The Lx2401A also offers a cost-effective reprogrammable solution for volume
production. A password-based “code security” feature on the device is useful in preventing unauthorized
duplication of proprietary code stored in on-chip Flash/ROM. Note that the LF2401A contains a 256-word boot
ROM to facilitate in-circuit programming. The boot ROM on LC2401A is used for test purposes.
The Lx2401A offers an event manager module which has been optimized for digital motor control and power
conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation,
programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion.
Select EV pins have been provided with an “input-qualifier” circuitry, which minimizes inadvertent pin-triggering
by glitches.
The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and
offers up to 5 channels of analog input. The autosequencing capability of the ADC allows a maximum of
16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication
to other devices in the system. To maximize device flexibility, functional pins are also configurable as
general-purpose inputs/outputs (GPIOs).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices.
This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite
of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger
supports this family. Numerous third-party developers not only offer device-level development tools, but also
system-level design and development support.
NOTE: The Lx2401A device has reduced peripheral functionality compared to other 24x/240x devices. While
peripherals such as SPI and CAN are absent on the Lx2401A, peripherals such as EV and ADC have reduced
functionality. For example, in the case of EV, there is no QEP unit and the Capture unit has only one capture
pin (as opposed to three or six pins in other devices). The ADC has only five input channels (as opposed to eight
or sixteen channels in other devices). For these reasons, some bits that are valid in other 24x/240x devices are
not applicable in the Lx2401A. The registers and their valid bits are described in Table 16, Lx2401A DSP
Peripheral Register Description. For a description of those registers and bits that are valid, refer to the
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357). Any exceptions to SPRU357 has been described in the respective peripheral sections in this data
sheet.
TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments.
†
Throughout this document, TMS320Lx2401A is used as a generic name for the TMS320LF2401A and TMS320LC2401A devices. An
abbreviated name, Lx2401A, denotes both devices as well.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
TMS320x240xA device summary
Table 1. Device Feature Comparison Between Lx2401A and Lx2402A
FEATURE
LF2401A
Yes
LC2401A
Yes
LF2402A
Yes
LC2402A
Yes
C2xx DSP Core
Instruction Cycle
MIPS (40 MHz)
25 ns
25 ns
25 ns
25 ns
40 MIPS
40 MIPS
40 MIPS
40 MIPS
Dual-Access
RAM (DARAM)
544
512
544
512
544
512
544
—
RAM (16-bit word)
Single-Access
RAM (SARAM)
3.3-V Flash (Program Space, 16-bit word)
Flash Sectors
8K
4K/4K
—
—
—
8K
4K/4K
—
—
—
On-chip ROM (Program Space, 16-bit word)
Code Security for On-Chip Flash/ROM
Boot ROM
8K
Yes
Yes
—
6K
Yes
—
Yes
Yes
—
Yes
Yes
—
External Memory Interface
Event Manager A (EVA)
—
EVA
2
EVA
2
EVA
2
EVA
2
S
S
S
S
General-Purpose (GP) Timers
Compare (CMP)/PWM
Capture (CAP)/QEP
7
7
8
8
1
1
3/2
3/2
Input qualifier circuitry on
PDPINTx, CAPn, XINT1/2, and
ADCSOC pins
†
Yes
†
Yes
Yes
Yes
Watchdog Timer
10-Bit ADC
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
S
S
Channels
Conversion Time (minimum)
5
5
8
8
500 ns
—
500 ns
—
375 ns
—
425 ns
—
SPI
SCI
CAN
Yes
Yes
Yes
Yes
—
—
—
—
Digital I/O Pins (Shared)
External Interrupts
13
13
21
21
2
2
3
3
Core
I/O
3.3 V
3.3 V
32-pin VF
3.3 V
3.3 V
32-pin VF
3.3 V
3.3 V
64-pin PG
3.3 V
3.3 V
64-pin PG
Supply Voltage
Packaging
‡
Product Status :
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD
PD
PD
PD
†
‡
Some pins may not be applicable to Lx2401A.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
4
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
functional block diagram of the LF2401A DSP controller
XTAL1/CLKIN
XTAL2
V
DD
(3.3 V)
DARAM (B0)
256 Words
PLL Clock
V
SS
RS
C2xx
DSP
Core
XF
†
DARAM (B1)
256 Words
ADCIN00−ADCIN04
XINT1
V
V
10-Bit ADC
(With Twin
Autosequencer)
CCA
‡
XINT2
CLKOUT
SSA
‡
DARAM (B2)
32 Words
‡
ADCSOC
SCITXD/IOPB3
SCIRXD/IOPB4
SARAM (512 Words)
SCI
WD
Flash
V
CCP
(5V)
(8K Words −
4K/4K Sectors)
‡
†
Port A(0−7) IOPA[0:7]
Port B(0−5) IOPB[0:5]
Digital I/O
(Shared With
Other Pins)
PDPINTA/IOPA0
PWM1/IOPA1
PWM2/IOPA2
PWM3/IOPA3
Event Manager A
TRST
TDO/IOPB2
PWM4/IOPA4
PWM5/IOPA5
PWM6/IOPA6
D 1 × Capture Input
D 7 × Compare/PWM
Output
D 2 × GP Timers/PWM
TDI/OPB5
TMS/XF
JTAG Port
‡
CAP1
TCK/IOPB1
†
T2PWM
†
‡
T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0.
XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.
5
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
functional block diagram of the LC2401A DSP controller
XTAL1/CLKIN
XTAL2
V
DD
(3.3 V)
DARAM (B0)
256 Words
PLL Clock
V
SS
RS
C2xx
DSP
Core
XF
†
DARAM (B1)
256 Words
ADCIN00−ADCIN04
XINT1
V
V
10-Bit ADC
(With Twin
Autosequencer)
CCA
‡
XINT2
CLKOUT
SSA
‡
DARAM (B2)
32 Words
‡
ADCSOC
SCITXD/IOPB3
SCIRXD/IOPB4
SARAM (512 Words)
SCI
WD
ROM
(8K Words)
‡
†
Port A(0−7) IOPA[0:7]
Port B(0−5) IOPB[0:5]
Digital I/O
(Shared With
Other Pins)
PDPINTA/IOPA0
PWM1/IOPA1
PWM2/IOPA2
PWM3/IOPA3
Event Manager A
TRST
TDO/IOPB2
PWM4/IOPA4
PWM5/IOPA5
PWM6/IOPA6
D 1 × Capture Input
D 7 × Compare/PWM
Output
D 2 × GP Timers/PWM
TDI/OPB5
TMS/XF
JTAG Port
‡
CAP1
TCK/IOPB1
†
T2PWM
†
‡
T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0.
XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT.
6
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
32-PIN VF PACKAGE
(TOP VIEW)
24
23
22
21
20
19
18
17
25
26
27
28
29
30
31
16
15
14
13
12
11
10
ADCIN01
ADCIN02
ADCIN03
ADCIN04
PWM6/IOPA6
PWM5/IOPA5
PWM4/IOPA4
RS
V
DD
†
V
CCP
PWM1/IOPA1
PWM2/IOPA2
PWM3/IOPA3
V
SS
T2PWM/XINT1/IOPB0
PDPINTA/IOPA0
32
9
1
2
3
4
5
6
7
8
†
Pin 26 is V
on LF2401A and is a No Connect (NC) on LC2401A.
NOTE A: Bold face type indicates function of the device pin after reset.
CCP
7
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions
†
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
Device Reset (in) and Watchdog Reset (out).
Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to
a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP
when a watchdog reset occurs. During watchdog reset, the RS pin will be driven low for the watchdog
reset duration of 128 CLKIN cycles.
RS
9
The output buffer of this pin is an open-drain with an internal pullup (20 µA, typical). It is recommended
that this pin be driven by an open-drain device. (↑)
Power drive protection input. When this pin is pulled low by an external event, an interrupt is generated
and all PWM outputs go to high-impedance state. PDPINTA will keep PWM outputs in high-impedance
state even when the DSP is not executing. (↑)
NOTES:
1) Upon reset, the PDPINTA function is active, in addition to the GPIO function. If the IOPA0 function
is desired, the PDPINTA function must be disabled. (This can be done by writing to bit 0 of the
EVAIMRA register.) Otherwise, the PWM outputs could inadvertently be put into a high-impedance
state when the IOPA0 pin is driven low.
PDPINTA/IOPA0
32
2) When PDPINTA is used to “wake up” the DSP from LPM2, the pin should be held low for
(98304 CLKIN + 12 CLKOUT) cycles.
3) This pin must be held high when on-chip boot ROM is invoked.
PWM1/IOPA1
PWM2/IOPA2
PWM3/IOPA3
PWM4/IOPA4
PWM5/IOPA5
PWM6/IOPA6
27
28
29
10
11
12
Compare/PWM output 1 or GPIO (↑)
Compare/PWM output 2 or GPIO (↑)
Compare/PWM output 3 or GPIO (↑)
Compare/PWM output 4 or GPIO (↑)
Compare/PWM output 5 or GPIO (↑)
Compare/PWM output 6 or GPIO (↑)
Upon reset, this pin comes up as XINT1/IOPB0 pin. To enable the XINT1 function, the appropriate bit
in the XINT1CR register must be set. No special configuration sequence is needed to use this pin as
a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a
general-purpose output. Configuration of this pin as T2PWM is achieved by writing a one to bit 8 of the
MCRA register. Note that the value of bit 8 in the MCRA register does not affect the XINT1 functionality
of this pin. The XINT1 function is enabled/disabled by the value written into the XINT1CR register and
is independent of the value written in bit 8 in the MCRA register. (↑)
T2PWM/XINT1/IOPB0
31
Upon reset, this pin can be configured as any one of the following: XINT2, ADCSOC, CAP1, or IOPA7.
To configure this pin for XINT2 function, the appropriate bit in the XINT2CR register must be set. To
configure this pin for ADCSOC function, the appropriate bit in the ADCTRL2 register must be set. To
configure this pin for CAP1 function, the appropriate bits in the CAPCONA register must be configured.
To summarize, the XINT2, ADCSOC, and CAP1 functions are enabled at the respective peripheral level.
No special configuration sequence is needed to use this pin as a GPIO. However, a write to the
PADATDIR register is necessary to configure this pin as a general-purpose output. This pin can also
function as the CPU clock output. This is achieved by writing a one to bit 7 of the MCRA register. When
CLKOUT is chosen, the internal logic for the XINT2, ADCSOC, and CAP1 sees the pin as a “1”. (↑)
XINT2/ADCSOC/CAP1/
IOPA7/CLKOUT
22
†
‡
Bold face type indicates function of the device pin after reset.
It is highly recommended that V be isolated from the digital supply voltage (and V
from digital ground) to maintain the specified accuracy
CCA SSA
and improve the noise immunity of the ADC.
TDI is MUXed with digital output, not digital I/O.
§
¶
Pin 26 is V
on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 20 µA.)
CCP
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.
8
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
†
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME
NO.
17
16
15
14
13
19
18
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04
Analog input channel 0
Analog input channel 1
Analog input channel 2
Analog input channel 3
Analog input channel 4
‡
V
Analog supply voltage for ADC (3.3 V) Internally connected to V
REFHI
CCA
SSA
V
Analog ground reference for ADC. Internally connected to V
.
REFLO
SCITXD/IOPB3
SCIRXD/IOPB4
3
2
SCI asynchronous serial port transmit data or GPIO (↑)
SCI asynchronous serial port receive data or GPIO (↑)
JTAG test clock or GPIO (↑)
TCK/IOPB1
4
24
23
1
Function when TRST = 0: IOPB1
Function when TRST = 1: TCK
JTAG test data input or GPO. When TRST is low (i.e., when the JTAG connector is not connected to the
DSP), the TDI/OPB5 pin acts as an output. When RS is low, the OPB5 pin is asynchronously forced into
a high-impedance state and when RS subsequently rises, it will remain in high-impedance state until
software configures this pin as an output. The B5DIR bit (bit 13 of the PBDATDIR register) controls the
enable to this output buffer. Bit 13 of the MCRA register will have no effect on this pin. (↑)
§
TDI/OPB5
This pin must be held low during a reset to invoke the on-chip boot ROM.
Function when TRST = 0: OPB5
Function when TRST = 1: TDI
JTAG scan out, test data output or GPIO (↓)
TDO/IOPB2
Function when TRST = 0: IOPB2
Function when TRST = 1: TDO
JTAG test mode select or GPO. External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XFinstruction. This pin is configured
as an external flag output by all device resets. (↑)
Function when TRST = 0: XF
Function when TRST = 1: TMS
TMS/XF
NOTE: The enabling/disabling of the XF pin is controlled by Bit 0 of the SCSR4 register at address
0x701B (in addition to the TRST pin). Upon reset, this bit is zero, disabling the XF pin. This bit must be
set by user code before it can be used. This bit is not readable; hence, its status cannot be determined.
†
‡
Bold face type indicates function of the device pin after reset.
It is highly recommended that V be isolated from the digital supply voltage (and V
from digital ground) to maintain the specified accuracy
CCA SSA
and improve the noise immunity of the ADC.
TDI is MUXed with digital output, not digital I/O.
§
¶
Pin 26 is V
on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 20 µA.)
CCP
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.
9
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
†
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME
NO.
JTAG test reset. The function of the TCK, TDI, TDO, and TMS pins depend on the state of the TRST
pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO
function of these pins is not available). If TRST = 0 (Functional mode), these pins function as GPIO. (↓)
NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. In a low-noise
environment, TRST can be left unconnected. In a high-noise environment, an additional pulldown
resistor may be needed. The value of this resistor should be based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of the
debugger and the application.
TRST
20
XTAL1/CLKIN
XTAL2
6
7
Crystal/Clock input to PLL
Crystal output
Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The
Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e.,
during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied
to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series
with the 5-V supply on this pin. This pin is a “no connect” (NC) on ROM parts (i.e., this pin is not connected
to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference
on ROM parts.
¶
V
CCP
26
V
DD
V
DD
V
SS
V
SS
V
SS
5
Core supply (3.3 V)
Core supply (3.3 V)
Core ground
25
8
21
30
Core ground
Core ground
†
‡
Bold face type indicates function of the device pin after reset.
It is highly recommended that V be isolated from the digital supply voltage (and V
and improve the noise immunity of the ADC.
TDI is MUXed with digital output, not digital I/O.
from digital ground) to maintain the specified accuracy
CCA SSA
§
¶
Pin 26 is V
on LF2401A and is a No Connect (NC) on LC2401A.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is 20 µA.)
CCP
NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high.
NOTE:
The I/O pins that are MUXed with the JTAG function cannot be used while debugging, since the
emulator needs complete control of the JTAG pins. While debugging, there should not be any
circuitry connected on these MUXed pins that could disturb the JTAG debug process.
10
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
NOTE: The multiplexing diagrams are functional representations of the multiplexing scheme. They do not
represent the actual circuit elements within the silicon.
PADATDIR.n
[IOPAn − input data]
PADATDIR.m
0
(Direction)
Pullup
PWMn/IOPAn Pin
FCOMPOE
1
[COMCONA.9]
MCRA.k
PADATDIR.n
[IOPAn − Output Data]
0
1
PWMn
MCRA.k
MCRA.1
MCRA.2
MCRA.3
MCRA.4
MCRA.5
MCRA.6
PWMn/IOPAn
DIRECTION BIT
DATA BIT
PWM1/IOPA1
PWM2/IOPA2
PWM3/IOPA3
PWM4/IOPA4
PWM5/IOPA5
PWM6/IOPA6
PADATDIR.9
PADATDIR.10
PADATDIR.11
PADATDIR.12
PADATDIR.13
PADATDIR.14
PADATDIR.1
PADATDIR.2
PADATDIR.3
PADATDIR.4
PADATDIR.5
PADATDIR.6
Figure 1. PWMn/IOPAn Pin Multiplexing Functional Block Diagram
PADATDIR.0
[IOPA0 − Input Data]
PADATDIR.0
[IOPA0 − Output Data]
Pullup
PDPINTA/IOPA0 Pin
MCRA.0
PADATDIR.8
Input
Qualifier
Circuit
PDPINTA
EVAIMRA.0
Figure 2. PDPINTA/IOPA0 Pin Multiplexing Functional Block Diagram
11
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
1
1
0
PADATDIR.7
[IOPA7 − Input Data]
XINT2 and XINT2
LPM1 Wakeup Logic
Input
Qualifier
Circuit
XINT2CR.0
CAP1
CAPCONA[14,13]
ADSOC
Pullup
XINT2/ADCSOC/
CAP1/IOPA7/
CLKOUT Pin
ADCTRL2.7
MCRA.7
PADATDIR.15
(Direction)
CLKOUT
1
PADATDIR.7
[IOPA7 − Output Data]
0
Figure 3. XINT2/ADCSOC/CAP1/IOPA7/CLKOUT Pin Multiplexing Functional Block Diagram
12
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
PBDATDIR.0
[IOPB0 − Input Data]
XINT1CR.0
XINT1 and
XINT1 LPM1
Wakeup Logic
Input
Qualifier
Circuit
Pullup
T2PWM/XINT1/IOPB0 Pin
PBDATDIR.8
(Direction Bit)
0
TCOMPOE
[GPTCONA.6]
1
MCRA.8
PBDATDIR.0
[IOPB0 − Output Data]
0
1
T2PWM
[PWM Signal]
Figure 4. T2PWM/XINT1/IOPB0 Pin Multiplexing Functional Block Diagram
PBDATDIR.3
[IOPB3 − Input Data]
PBDATDIR.11
(Direction Bit)
Pullup
SCITXD/
MCRA.11
IOPB3 Pin
PBDATDIR.3
[IOPB3 − Output Data]
0
1
SCITXD
Figure 5. SCITXD/IOPB3 Pin Multiplexing Functional Block Diagram
13
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
SCIRXD
PBDATDIR.4
[IOPB4 − Input Data]
Pullup
PBDATDIR.12
(Direction Bit)
SCIRXD/IOPB4 Pin
MCRA.12
PBDATDIR.4
[IOPB4 − Output Data]
Figure 6. SCIRXD/IOPB4 Pin Multiplexing Functional Block Diagram
14
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
terminal functions (continued)
TCK
Pullup
PBDATDIR.1
[IOPB1 − Input Data]
TCK/IOPB1 Pin
PBDATDIR.1
[IOPB1 − Output Data]
TRST
To CPU
RS
PBDATDIR.9
(Direction Bit)
Pullup
TDI
TDI/OPB5 Pin
PBDATDIR.5
[OPB5 − Output Data]
TRST
RS
PBDATDIR.13
(Direction Bit)
IOPBDATDIR.2
[IOPB2 − Input Data]
TDO/IOPB2 Pin
Pulldown
PBDATDIR.2
[IOPB2 − Output Data]
0
1
TDO
TRST
RS
PBDATDIR.10
(Direction Bit)
Pullup
TMS
TMS/XF Pin
XF
TRST
†
Bit 0 of SCSR4
TRST Pin
Pulldown
†
This bit is a write-only bit.
Figure 7. JTAG/GPIO Pins Multiplexing Functional Block Diagram
15
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
constraints while emulating with JTAG port pins and GPIO functions
This section highlights the constraints that are encountered if the emulation/debugging tool attempts to use the
multiplexed JTAG/GPIO pins in their JTAG configuration while the application attempts to use them in the GPIO
configuration at the same time:
1. Since the emulation/debugging tools need complete control of the JTAG port pins, the GPIO functions that
are multiplexed with the JTAG port pins cannot be used when the JTAG pod is connected to the JTAG
header.
2. Applications using the JTAG port pins for its GPIO function must provide some isolation mechanism (such
as jumpers) to isolate the external circuitry associated with the GPIO circuits. This will ensure that the GPIO
circuit does not conflict with the signals from the JTAG pod. To reiterate, the circuitry associated with the
GPIO pins must be isolated from the DSP before the JTAG pod is connected to the JTAG header.
3. It is recommended that the Lx2401A application software does not enable GPIO function for the multiplexed
JTAG/GPIO pins if emulation tools are ever planned to be used concurrently. This will avoid drive conflicts
between JTAG pod signals and GPIO signals—particularly on TCK, TDI and TMS pins. Table 2 shows the
configuration of the multiplexed JTAG/GPIO pins depending on the status of the TRST pin.
Table 2. Configuration of Multiplexed JTAG/GPIO Pins
TRST = 1
TRST = 0
TCK (signal from the JTAG pod)
TDI (signal from the JTAG pod)
TMS (signal from the JTAG pod)
Can be configured as IOPB1
Can be configured as IOPB5
Can be configured as XF
4. TRST pin is internally pulled down. When this pin is left unconnected, it puts the multiplexed JTAG/GPIO
pins in their GPIO configuration. If TRST is driven high, it puts the multiplexed JTAG/GPIO pins in their JTAG
configuration and the device enters emulation mode. All the emulation and flash programming tools use the
JTAG port and will drive this pin high. TRST pin controls the functionality of the multiplexed JTAG/GPIO pins.
16
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
in-circuit emulation options
The GPIO functionality of the JTAG/GPIO pins cannot be used when the JTAG function is used for debugging.
In applications which require full emulation, it is easy to build an in-circuit emulation system using a 2407A EVM
(or any TMS320LF240x target board). This requires some additional planning in the Lx2401A target board
design. The following suggestions may be used as a guideline while planning the board layout:
1. Make provisions for a connector (port) which will bring out all the Lx2401A signals.
2. Map these signals (such as PWM, SCI, ADC, GPIO) through a cable to the 2407A EVM connector signals.
3. Using the 2407A EVM emulation device, there are two options to build your software:
a. Use assembler directives to enable 2407A register mapping.
−
−
−
Build your application using 2407A emulation board with the 2401A target board connected using
the harness suggested above.
After software development is complete, rebuild the code using the assembler directive to use
2401A registers.
Map and flash the code in Lx2401A. The end application should now run seamlessly on the 2401A
target with Lx2401A device.
b. Use the device IDs of 2407A and 2401A devices to select the required pin-mapping for your application.
−
−
The Device ID for these devices is a unique number located at 701Ch.
Build your application using the 2407A emulation board with the 2401A target board connected
using the harness suggested above.
−
After software development is complete, flash the code in Lx2401A. The end application will select
the map and the registers based on the device ID and should now run seamlessly on the 2401A
target with Lx2401A device.
Lx2401A Target
Lx2401A/EVM Harness
JTAG Link
LF2407A EVM as
In-Circuit Emulator
Code Composer for
LF2407A EVM
Figure 8. Lx2401A Emulation Using LF2407A EVM as In-Circuit Emulator (Optional)
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
memory map
Hex
Hex
Data
Hex
I/O
Program
0000
0000
FLASH SECTOR 0 (4K)
0000
Memory-Mapped
Interrupt Vectors (0000−003Fh)
Reserved (0040−0043h)
User code begins at 0044h
Registers/Reserved Addresses
005F
0060
007F
0080
00FF
0100
01FF
0200
†
On-Chip DARAM B2
Illegal
0FFF
1000
1FFF
2000
FLASH SECTOR 1 (4K)
Reserved
§
On-Chip DARAM (B0) (CNF = 0)
Reserved (CNF = 1)
02FF
0300
03FF
0400
04FF
0500
¶
On-Chip DARAM (B1)
Reserved
Reserved
Illegal
07FF
0800
Reserved
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
7FFF
8000
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
09FF
0A00
Reserved
Illegal
0FFF
1000
81FF
8200
Reserved
6FFF
7000
87FF
8800
Peripheral Memory-Mapped
Registers (System, WD, ADC,
EV, SCI, I/O)
7FFF
8000
Reserved
FEFF
FF00
Reserved
Flash Control Mode Register
Reserved
FF0E
FDFF
FE00
FF0F
Illegal
‡
FF10
FFFE
Reserved
FEFF
FF00
‡
On-Chip DARAM (B0) (CNF = 1)
Reserved
Reserved (CNF = 0)
FFFF
FFFF
FFFF
On-Chip Flash Memory (Sectored)
SARAM (See Table 1 for details.)
Reserved or Illegal
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
‡
Addresses 0040h−0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
§
¶
Figure 9. TMS320LF2401A Memory Map
18
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
memory map (continued)
Hex
Data
Hex
I/O
Hex
Program
0000
0000
0000
Memory-Mapped
ROM (8K)
Registers/Reserved Addresses
On-Chip DARAM B2
Illegal
005F
0060
007F
0080
00FF
0100
01FF
0200
Interrupt Vectors (0000−003Fh)
†
Reserved (0040−0043h)
User code begins at 0044h
1FFF
2000
Reserved
§
On-Chip DARAM (B0) (CNF = 0)
Reserved (CNF = 1)
02FF
0300
03FF
0400
04FF
0500
¶
On-Chip DARAM (B1)
Reserved
Reserved
Illegal
07FF
0800
Reserved
SARAM (512 words)
Internal (DON = 1)
Reserved (DON = 0)
7FFF
8000
SARAM (512 words)
Internal (PON = 1)
Reserved (PON = 0)
09FF
0A00
Reserved
Illegal
0FFF
1000
81FF
8200
Reserved
6FFF
7000
87FF
8800
Peripheral Memory-Mapped
Registers (System, WD, ADC,
EV, SCI, I/O)
7FFF
8000
Reserved
FEFF
FF00
Reserved
FDFF
FE00
Illegal
‡
FF10
FFFE
Reserved
Reserved
Reserved
FEFF
FF00
‡
On-Chip DARAM (B0) (CNF = 1)
Reserved (CNF = 0)
FFFF
FFFF
FFFF
SARAM (See Table 1 for details.)
Reserved or Illegal
NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000−00FF in the program space will be occupied by boot ROM.
†
‡
Addresses 0040h−0043h in program memory are reserved for code security passwords.
When CNF = 1, addresses FE00h−FEFFh and FF00h−FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h−FEFFh are referred to as reserved.
When CNF = 0, addresses 0100h−01FFh and 0200h−02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h−01FFh are referred to as reserved.
Addresses 0300h−03FFh and 0400h−04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity, addresses 0400h−04FFh are referred to as reserved.
§
¶
Figure 10. TMS320LC2401A Memory Map
19
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peripheral memory map
Hex
0000
0003
0004
Reserved
Interrupt-Mask Register
Reserved
0005
Interrupt Flag Register
0006
0007
Emulation Registers
and Reserved
005F
Hex
0000
Memory-Mapped Registers
and Reserved
Illegal
7000−700F
7010−701F
005F
0060
System Configuration and
Control Registers
On-Chip DARAM B2
Illegal
007F
0080
Watchdog Timer Registers
Illegal
7020−702F
7030−703F
00FF
0100
Reserved
01FF
0200
On-Chip DARAM B0
7040−704F
7050−705F
Reserved
SCI
02FF
0300
On-Chip DARAM B1
Reserved
03FF
0400
Illegal
7060−708F
04FF
0500
Illegal
SARAM (512 words)
Illegal
07FF
0800
Digital I/O Control Registers
ADC Control Registers
Illegal
7090−709F
70A0−70BF
09FF
0A00
70C0−70FF
7100−710E
710F−71FF
7200−722F
7230−73FF
6FFF
7000
Peripheral Frame 1 (PF1)
Peripheral Frame 2 (PF2)
Reserved
Illegal
73FF
7400
743F
7440
Illegal
Reserved
Illegal
74FF
7500
Reserved
753F
7540
Illegal
77EF
77F0
77F3
77F4
Event Manager − EVA
Code Security Passwords
Reserved
General-Purpose
Timer Registers
7400−7408
Compare, PWM, and
Deadband Registers
77FF
7800
7411−7419
7420−7429
Illegal
Capture Registers
FFFF
Interrupt Mask, Vector and
Flag Registers
742C−7431
7432−743F
“Illegal” indicates that access to
these addresses causes a
nonmaskable interrupt (NMI).
Illegal
Illegal
“Reserved” indicates addresses that
are reserved for test.
Reserved
Figure 11. Peripheral Memory Map
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device reset and interrupts
The TMS320Lx2401A software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The Lx2401A recognizes three types
of interrupt sources.
D
Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The Lx2401A devices have two sources of reset: an external reset pin and a watchdog timer time-out
(reset).
D
Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
−
External interrupts are generated by one of three external pins corresponding to the interrupts XINT1,
XINT2, and PDPINTA. These three can be masked both by dedicated enable bits and by the CPU
interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
−
Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A,
SCI, and ADC. They can be masked both by enable bits for each event in each peripheral and by the
CPU IMR, which can mask each maskable interrupt line at the DSP core.
D
Software-generated interrupts for the Lx2401A devices include:
−
−
−
The INTR instruction. This instruction allows initialization of any Lx2401A interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. Lx2401A devices do not have the NMI hardware signal, only
software activation is provided.
The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
−
An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1−INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the Lx2401A peripherals and are grouped
to share the six core level interrupts. Figure 12 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 12) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. Lx2401A devices have interrupts identical to those of the F24x devices. See Table 3 for details.
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device reset and interrupts (continued)
PIE
IMR
IFR
PDPINTA
ADCINT
RXINT
Level 1
IRQ GEN
TXINT
INT1
INT2
XINT1
XINT2
CMP1INT
CMP2INT
CMP3INT
T1PINT
Level 2
IRQ GEN
T1CINT
T1UFINT
T1OFINT
CPU
INT3
T2PINT
T2CINT
Level 3
IRQ GEN
T2UFINT
T2OFINT
INT4
Level 4
IRQ GEN
CAP1INT
INT5
RXINT
TXINT
Level 5
IRQ GEN
ADCINT
INT6
Level 6
IRQ GEN
XINT1
IACK
XINT2
PIVR & Logic
PIRQR#
PIACK#
Data Bus
Addr Bus
Interrupt from external interrupt pin. The remaining interrupts are internal to the peripherals.
Figure 12. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts
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interrupt request structure
Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
PERIPHERAL
INTERRUPT
VECTOR
SOURCE
PERIPHERAL
MODULE
INTERRUPT OVERALL
MASK-
ABLE?
POSITION IN
PIRQRx AND
PIACKRx
DESCRIPTION
NAME
PRIORITY
(PIV)
RSN
0000h
RS pin,
Watchdog
Reset from pin, watchdog
timeout
Reset
1
2
N/A
N
N
N
Y
Y
Y
Y
Y
Y
−
Reserved
NMI
N/A
CPU
Emulator trap
0026h
NMI
0024h
Nonmaskable Nonmaskable interrupt,
Interrupt
3
N/A
software interrupt only
Power device protection
interrupt pin
PDPINTA
ADCINT
XINT1
4
0.0
0.1
0.2
0.3
0.5
0.6
0020h
0004h
0001h
0011h
0006h
0007h
EVA
ADC interrupt in
high-priority mode
6
ADC
External
Interrupt Logic
7
INT1
0002h
External interrupt pins in high
priority
External
Interrupt Logic
XINT2
8
SCI receiver interrupt in
high-priority mode
RXINT
TXINT
10
11
SCI
SCI
SCI transmitter interrupt in
high-priority mode
CMP1INT
CMP2INT
CMP3INT
T1PINT
14
15
16
17
18
19
20
28
29
30
31
0.9
0.10
0.11
0.12
0.13
0.14
0.15
1.0
0021h
0022h
0023h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
EVA
EVA
EVA
EVA
EVA
EVA
EVA
EVA
EVA
EVA
EVA
Compare 1 interrupt
Compare 2 interrupt
Compare 3 interrupt
INT2
0004h
Timer 1 period interrupt
Timer 1 compare interrupt
Timer 1 underflow interrupt
Timer 1 overflow interrupt
Timer 2 period interrupt
Timer 2 compare interrupt
Timer 2 underflow interrupt
Timer 2 overflow interrupt
T1CINT
T1UFINT
T1OFINT
T2PINT
T2CINT
1.1
INT3
0006h
T2UFINT
T2OFINT
1.2
1.3
INT4
0008h
CAP1INT
RXINT
36
43
44
1.4
1.8
1.9
0033h
0006h
0007h
Y
Y
Y
EVA
SCI
SCI
Capture 1 interrupt
SCI receiver interrupt
(low-priority mode)
INT5
000Ah
SCI transmitter interrupt
(low-priority mode)
TXINT
†
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
23
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interrupt request structure (continued)
Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors (Continued)
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
PERIPHERAL
INTERRUPT
VECTOR
SOURCE
PERIPHERAL
MODULE
INTERRUPT OVERALL
MASK-
ABLE?
POSITION IN
PIRQRx AND
PIACKRx
DESCRIPTION
NAME
PRIORITY
(PIV)
ADC interrupt
(low priority)
ADCINT
47
48
49
1.12
1.13
1.14
0004h
0001h
0011h
Y
Y
Y
ADC
External
Interrupt Logic
INT6
000Ch
XINT1
XINT2
External interrupt pins
(low-priority mode)
External
Interrupt Logic
Reserved
TRAP
000Eh
0022h
N/A
N/A
Y
CPU
CPU
Analysis interrupt
TRAP instruction
N/A
N/A
N/A
Phantom
Interrupt
Vector
N/A
0000h
N/A
CPU
Phantom interrupt vector
Software interrupt vectors
INT8−INT16
N/A
N/A
0010h−0020h
N/A
N/A
N/A
N/A
CPU
CPU
†
INT20−INT31
00028h−0603Fh
†
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information.
NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details.
DSP CPU core
The TMS320Lx2401A device uses an advanced Harvard-type architecture that maximizes processing power
by maintaining two separate memory bus structures — program and data — for full-speed execution. This
multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers
between program memory and data memory. This architecture permits coefficients that are stored in program
memory to be read in RAM. This, coupled with a four-deep pipeline, allows the Lx2401A device to execute most
instructions in a single cycle. See the functional block diagram of the 2401A DSP CPU for more information.
TMS320Lx2401A instruction set
The 2401A DSP implements a comprehensive instruction set that supports both numeric-intensive
signal-processing operations and general-purpose applications, such as multiprocessing and high-speed
control.
For maximum throughput, the next instruction is prefetched while the current one is being executed.
addressing modes
The TMS320Lx2401A instruction set provides four basic memory-addressing modes: direct, indirect,
immediate, and register.
In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field
is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address.
Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each
page containing 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address
of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers
(AR0−AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary
register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
24
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scan-based emulation
TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardware-
development support. Scan-based emulation allows the emulator to control the processor in the system without
the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx
by way of the IEEE 1149.1-compatible (JTAG) interface. The Lx2401A DSP does not include boundary scan.
The scan chain of the device is useful for emulation function only.
25
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functional block diagram of the 2401A DSP CPU
Program Bus
MUX
XTAL1
CLKOUT
NPAR
PAR
XTAL2
XF
RS
16
PC
MSTACK
MUX
Stack 8 × 16
XINT[1−2]
2
FLASH EEPROM
Program Control
(PCTRL)
16
16
16
Data Bus
16
16
16
16
16
3
9
7
16
16
LSB
from
IR
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
DP(9)
16
MUX
MUX
16
ARP(3)
3
3
9
TREG0(16)
ARB(3)
Multiplier
3
ISCALE (0−16)
PREG(32)
32
16
PSCALE (−6,ā 0,ā 1,ā 4)
32
32
16
MUX
ARAU(16)
MUX
32
CALU(32)
32
32
16
Memory Map
Register
MUX
MUX
IMR (16)
IFR (16)
Data/Prog
DARAM
Data
C
ACCH(16)
ACCL(16)
32
GREG (16)
DARAM
B0 (256 × 16)
B2 (32 × 16)
B1 (256 × 16)
OSCALE (0−7)
16
MUX
16
16
16
NOTES: A. See Table 4 for symbol descriptions.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.
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2401A legend for the internal hardware
Table 4. Legend for the 2401A DSP CPU Internal Hardware
SYMBOL
NAME
DESCRIPTION
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
ACC
Accumulator
Auxiliary Register
Arithmetic Unit
An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs
ARAU
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
AUX
REGS
Auxiliary Registers
0−7
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
C
Carry
32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
Central Arithmetic
Logic Unit
CALU
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300−03FF and 0060−007F, respectively. Blocks 0
and 1 contain 256 words, while block 2 contains 32 words.
DARAM
Dual-Access RAM
Data Memory
Page Pointer
The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to
form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
DP
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space. Since the global memory space is not used in
the 240x devices, this register is reserved.
GREG
IMR
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
Interrupt Flag
Register
The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
interrupts.
IFR
INT#
Interrupt Traps
A total of 32 interrupts by way of hardware and/or software are available.
Input Data-Scaling 16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
ISCALE
Shifter
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MPY
Multiplier
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
MSTACK
MUX
Micro Stack
Multiplexer
Multiplexes buses to a common input
Next Program
Address Register
NPAR
NPAR holds the program address to be driven out on the PAB in the next cycle.
Output
Data-Scaling
Shifter
16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data
bus (DWEB).
OSCALE
Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PAR
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PC
Program Counter
Program
Controller
PCTRL
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
27
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2401A legend for the internal hardware (continued)
Table 4. Legend for the 2401A DSP CPU Internal Hardware (Continued)
SYMBOL
NAME
DESCRIPTION
32-bit register holds results of 16 × 16 multiply
PREG
Product Register
0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle
overhead.
Product-Scaling
Shifter
PSCALE
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep.
STACK
TREG
Stack
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
status and control registers
Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can
be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved
and restored for subroutines.
The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST)
instruction is used to read from ST0 and ST1 — except for the INTM bit, which is not affected by the LST
instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC
instructions. Figure 13 shows the organization of status registers ST0 and ST1, indicating all status bits
contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status
register field definitions.
15
13
12
11
10
1
9
8
0
ST0
ST1
ARP
ARB
OV
OVM
INTM
DP
15
13
12
11
10
9
8
1
7
1
6
1
5
1
4
3
1
2
1
1
0
CNF
TC
SXM
C
XF
PM
Figure 13. Organization of Status Registers ST0 and ST1
Table 5. Status Register Field Definitions
FIELD
FUNCTION
Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST
instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP.
ARB
Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value
is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the
LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed.
ARP
Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow.
Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these
cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate
instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch
on the status of C. C is set to 1 on a reset.
C
On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data
space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1
instructions. RS sets the CNF to 0.
CNF
28
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status and control registers (continued)
Table 5. Status Register Field Definitions (Continued)
FIELD
DP
FUNCTION
Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory
address of 16 bits. DP can be modified by the LST and LDP instructions.
Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.
INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable
RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when
a maskable interrupt trap is taken.
INTM
Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an
overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV.
OV
Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator
is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset
this bit, respectively. LST can also be used to modify the OVM.
OVM
Product shift mode. If these two bits are 00, the multiplier’s 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG
output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits
and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG
contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the
SPM and LST #1 instructions. PM is cleared by RS.
PM
Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter.
SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction
suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction
and can be loaded by the LST #1 instruction. SXM is set to 1 by reset.
SXM
Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT
or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most
significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return
instructions can execute based on the condition of TC.
TC
XF
XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset
by the CLRC XF instruction. XF is set to 1 by reset.
central processing unit
The TMS320Lx2401A central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel
multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the
outputs of both the accumulator and the multiplier. This section describes the CPU components and their
functions. The functional block diagram shows the components of the CPU.
input scaling shifter
The TMS320Lx2401A provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output
connected to the CALU. This shifter operates as part of the path of data coming from program or data space
to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit
CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations.
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.
29
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multiplier
The TMS320Lx2401A device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or
an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply
unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated
as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers
associated with the multiplier, as follow:
D
D
16-bit temporary register (TREG) that holds one of the operands for the multiplier
32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.
Table 6. PSCALE Product-Shift Modes
PM
00
SHIFT
No shift
Left 1
DESCRIPTION
Product feed to CALU or data bus with no shift
01
Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when
using the multiply-by-a-13-bit constant
10
11
Left 4
Right 6
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.
30
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multiplier (continued)
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits
to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This
is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot
be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product
register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high
half, then, is loaded using the LPH instruction.
central arithmetic logic unit
The TMS320Lx2401A central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate
it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU).
Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional
operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming
from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from
immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean
operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320Lx2401A device supports floating-point operations for applications requiring a large dynamic
range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the
accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter
for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions.
These instructions are useful in floating-point arithmetic where a number must be denormalized — that is,
floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC)
going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based
on the value contained in the four LSBs of TREG.
The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result
in overflow.)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and the
accumulator. These instructions can be executed conditionally based on any meaningful combination of these
status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
31
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
central arithmetic logic unit (continued)
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use
the previous value of carry in their addition/subtraction operation.
The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.
Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing,
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.
accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16−31), the
MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0−15). When the postscaling
shifter is used on the low word, the LSBs are zero-filled.
The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions can be used with the shift and rotate instructions for multiple-bit shifts.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The 2401A provides a register file containing eight auxiliary registers (AR0−AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers also can be stored in data memory or used as inputs to the CALU.
The auxiliary register file (AR0−AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary
register while the data memory location is being addressed. Indexing either by 1 or by the contents of the AR0
register can be performed. As a result, accessing tables of information does not require the CALU for address
manipulation; therefore, the CALU is free for other operations in parallel.
32
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
internal memory
The TMS320Lx2401A device is configured with the following memory modules:
D
D
D
D
D
Dual-access random-access memory (DARAM)
Single-access random-access memory (SARAM)
ROM (LC2401A)
Flash (LF2401A)
Boot ROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 2401A runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 2401A architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle.
single-access RAM (SARAM)
There are 512 words × 16 bits of SARAM on the Lx2401A. The PON and DON bits select SARAM (512 words)
mapping in program space, data space, or both. See Table 16 for details on the SCSR2 register and the PON
and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data
spaces.
ROM (LC2401A)
There are 8K words × 16 bits of ROM on the LC2401A.
Flash EEPROM (LF2401A)
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2401A incorporates one 8K ꢀ 16-bit
Flash EEPROM module in program space. The Flash module has two sectors that can be individually protected
while erasing or programming. The sector size is partitioned as 4K/4K sectors.
Unlike most discrete Flash memory, the LF2401A Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
†
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at V
at zero wait state while the device is powered at 3.3 V.
pin only) the array. The Flash runs
CCP
†
IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.
33
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
†
boot ROM
Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the
BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the
TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when:
TRST
RS
=
=
=
0
0
0
TDI
(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the
execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG
connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is
low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected
(TRST = 1), it can be achieved by writing a “0” into bit 3 of the SCSR2 register.
The boot ROM has a generic bootloader to transfer code through the SCI port. The incoming code should
disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not
be enabled.
The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The
SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows:
D
D
D
If the SCITXD pin is pulled low, the PLL multiplier is set to 2.
If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default)
If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4.
Care should be taken such that a combination of CLKIN and the PLL multiplication factor does not result in a
CPU clock speed of greater than 40 MHz, the maximum rated speed. For restrictions concerning the maximum
frequency of CLKIN, see the latest revision of the TMS320LF2401A DSP Controller Silicon Errata (literature
number SPRZ013).
Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI.
Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature
number SPRU357) for more details about the bootloader operation.
†
The boot ROM on LC2401A is used for test purposes.
34
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
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Flash/ROM security
The 2401A device has a security feature that prevents external access to Flash/ROM memory. This feature is
useful in preventing unauthorized duplication of proprietary code resident on the Flash/ROM memory.
If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken:
1. A “dummy” read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word
“dummy” indicates that the destination address of this read is not relevant. If 40h−43h contain all zeros or
ones, then Step 2 is not required.
2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h,
77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h,
41h, 42h, and 43h (of program memory space), respectively. The device becomes “unsecured” one cycle
after the last instruction that unsecures the part.
Code Security Module Disclaimer
The Code Security Module (“CSM”) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
35
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
PERIPHERALS
The integrated peripherals of the TMS320Lx2401A are described in the following subsections:
D
D
D
D
D
D
Event-manager module (EVA)
Enhanced analog-to-digital converter (ADC) module
Serial communications interface (SCI) module
PLL-based clock module
Digital I/O and shared pin functions
Watchdog (WD) timer module
event manager module (EVA)
The event-manager module includes general-purpose (GP) timers, full-compare/PWM units, and a capture unit.
Table 7 shows the module and signal names used. Table 7 also shows the features and functionality available
for the event-manager module.
The EVA peripheral register set starts at 7400h. The paragraphs in this section describe the function of the GP
timers, the compare units, and the capture unit.
Table 7. Module and Signal Names for EVA
EVENT MANAGER MODULES
MODULE
SIGNAL
Timer 1
Timer 2
—
GP Timers
T2PWM/T2CMP
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare Units
Capture Unit
Capture 1
CAP1
36
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
event manager module (EVA) (continued)
2401A DSP Core
Data Bus
16
ADDR Bus Reset
16
Clock
INT2,3,4
3
16
EV Control Registers
and Control Logic
ADC Start of
Conversion
16
16
GP Timer 1
Compare
CLKOUT
(Internal)
GP Timer 1
Prescaler
T1CON[8,9,10]
16
16
PWM1
SVPWM
State
Machine
3
3
3
Full-Compare
Units
Deadband
Units
Output
Logic
PWM6
16
16
Output
Logic
GP Timer 2
Compare
T2PWM
GP Timer 2
CLKOUT
(Internal)
Prescaler
T2CON[8,9,10]
16
16
MUX
16
Capture Unit
CAP1
16
Figure 14. Event Manager A Block Diagram
37
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
general-purpose (GP) timers
There are two GP timers. GP timer x (x = 1 or 2) includes:
D
D
D
D
D
D
D
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Internal input clock
A programmable prescaler for internal clock input
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
The GP timers can be operated independently or synchronized with each other. The compare register
associated with GP timer 2 can be used for compare function and PWM-waveform generation. There are three
continuous modes of operations for each GP timer in up- or up/down-counting operations. An internal input
clock with programmable prescaler is used for each GP timer. GP timers also provide the time base for the other
event-manager submodules: GP timer 1 for all the compares and PWM circuits, and GP timer 2/1 for the capture
unit. Double-buffering of the period and compare registers allows programmable change of the timer (PWM)
period and the compare/PWM pulse width as needed.
full-compare units
There are three full-compare units on the event manager (EVA). These compare units use GP timer1 as the
time base and generate six outputs for compare and PWM-waveform generation using programmable
deadband circuit. The state of each of the six outputs is configured independently. The compare registers of
the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as
needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values (from 0 to 16 µs) can be programmed into the compare register for the outputs of the three compare units.
The deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output
signal. The output states of the deadband generator are configurable and changeable as needed by way of the
double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by EVA: three independent pairs (six
outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the
GP-timer compares.
38
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
PWM characteristics
Characteristics of the PWMs are as follows:
D
D
D
D
D
D
D
16-bit registers
Programmable deadband for the PWM output pairs, from 0 to 12 µs
Minimum deadband width of 25 ns
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
D
Minimized CPU overhead using auto-reload of the compare and period registers
D
The PWM pins are driven to a high-impedance state when the PDPINTA pin is driven low and after
PDPINTA signal qualification. The status of the PDPINTA pin (after qualification) is reflected in bit 8 of the
COMCONA register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stack when selected transitions are detected
on the capture input pin, CAP1. The capture unit consists of three capture circuits.
The capture unit includes the following features:
D
D
D
D
D
One 16-bit capture control register, CAPCONA (R/W)
One 16-bit capture FIFO status register, CAPFIFOA
Selection of GP timer 1/2 as the time base
One 16-bit 2-level-deep FIFO stack
One capture input pin (CAP1). [The input is synchronized with the device (CPU) clock. In order for a
transition to be captured, the input must hold at its current level to meet two rising edges of the device clock.]
D
D
User-specified transition (rising edge, falling edge, or both edges) detection
One maskable interrupt flag
input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1, XINT1/2, ADCSOC, and PDPINTA pins in the
2401A device. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal
input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller
than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low
for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether
6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches.
39
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
D
D
D
D
10-bit ADC core with built-in S/H
Fast conversion time (S/H + Conversion) of 500 ns
5-channel, MUXed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 5 input channels
D
D
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
−
The digital value of the input analog voltage is derived by:
Input Analog Voltage * VREFLO
Digital Value + 1023
VREFHI * VREFLO
NOTE: V
is internally tied to V
; V
is internally tied to V
.
CCA
REFLO
SSA REFHI
D
Multiple triggers as sources for the start-of-conversion (SOC) sequence
−
−
−
S/W − software immediate start
EVA − Event manager A (multiple event sources within EVA)
Ext − External pin (ADCSOC)
D
D
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
D
EVA triggers can operate independently in dual-sequencer mode
D
Sample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The 2401A ADC module is identical to the LF2407A ADC module. However, only channels ADCIN00
through ADCIN04 are bonded out of the device. For this reason, the valid values for the CONVnn bit fields in
the CHSELSEQn registers are from 0 to 4. Attempting to convert channels 5 through 15 would yield
indeterminate results.
40
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the 2401A has been enhanced to provide flexible interface to the event manager (EVA).
The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H +
conversion). The ADC module has 5 channels to service EVA. Although there are multiple input channels and
two sequencers, there is only one converter in the ADC module. Figure 15 shows the block diagram of the
2401A ADC module.
Result Registers
Analog MUX
70A8h
Result Reg 0
Result Reg 1
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04
10-Bit
ADC
Module
(500 ns)
Result Reg 7
Result Reg 8
70AFh
70B0h
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
SOC
SOC
Sequencer 1
Sequencer 2
Figure 15. Block Diagram of the 2401A ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (such as V
and V
) from the digital supply.
CCA
SSA
41
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
serial communications interface (SCI) module
The 2401A device includes a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D
Two external pins:
−
−
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D
D
Baud rate programmable to 64K different rates
†
−
Up to 2500 Kbps at 40-MHz CPUCLK
Data-word format
−
−
−
−
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
D
D
D
D
D
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
−
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
−
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D
D
D
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing to the upper byte has no effect.
Figure 16 shows the SCI module block diagram.
†
SCI speed will be limited by the I/O buffer speed and external transceiver performance.
42
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
serial communications interface (SCI) module (continued)
SCI TX Interrupt
TXRDY
SCITXBUF.7−0
TXWAKE
TX INT ENA
TXINT
Transmitter-Data
Buffer Register
Frame Format and Mode
SCICTL1.3
External
SCICTL2.7
Connections
1
SCICTL2.0
Parity
TX EMPTY
8
Even/Odd Enable
SCICTL2.6
SCICCR.6 SCICCR.5
WUT
TXENA
TXSHF
Register
SCITXD
SCITXD
SCICTL1.1
SCIHBAUD. 15−8
SCI Priority Level
1
Baud Rate
MSbyte
Register
Level 5 Int.
0
Level 1 Int.
Internal
Clock
SCI TX
Priority
SCILBAUD. 7−0
SCIPRI.6
Baud Rate
LSbyte
Register
1
Level 5 Int.
0
Level 1 Int.
SCI RX
Priority
SCIPRI.5
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
SCIRXST.1
RXENA
RX ERR INT ENA
SCICTL1.0
SCICTL1.6
SCI RX Interrupt
8
RXRDY
RX/BK INT ENA
Receiver-Data
Buffer
SCIRXST.6
RX Error
Register
SCICTL2.1
BRKDT
SCIRXST.5
SCIRXBUF.7−0
SCIRXST.7
RX Error
SCIRXST.4−2
FE OE PE
Figure 16. Serial Communications Interface (SCI) Module Block Diagram
43
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
PLL-based clock module
The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 17 for the PLL Clock Module Block Diagram and Table 8 for clock rates.
The PLL-based clock module provides two modes of operation:
D
D
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
XTAL1/CLKIN
F
in
PLL
C
CLKOUT
b1
XTAL
OSC
RESONATOR/
CRYSTAL
3-bit
PLL Select
(SCSR1.[11:9])
XTAL2
C
b2
Figure 17. PLL Clock Module Block Diagram
Table 8. PLL Clock Selection Through Bits (11−9) in SCSR1 Register
CLK PS2
CLK PS1
CLK PS0
CLKOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 × F
2 × F
in
in
1.33 × F
in
1 × F
in
0.8 × F
in
0.66 × F
0.57 × F
in
in
0.5 × F
in
Default multiplication factor after reset is (1,1,1), i.e., 0.5 × F .
in
CAUTION:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN
used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot
ROM” section for more details.
44
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
external reference crystal clock option
The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown
in Figure 18a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 Ω−150 Ω and a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF.
external reference oscillator clock option
The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input
pin unconnected as shown in Figure 18b.
XTAL1/CLKIN
XTAL2
XTAL1/CLKIN
XTAL2
NC
External Clock Signal
(Toggling 0−3.3 V)
C
C
b1
b2
(see Note A)
(see Note A)
Crystal
(a)
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 18. Recommended Crystal/Clock Connection
low-power modes
The 2401A has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.
clock domains
All 2401A-based devices have two clock domains:
1. CPU clock domain − consists of the clock for most of the CPU logic
2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 2401A CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 2401A CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 9). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
45
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
clock domains (continued)
Table 9. Low-Power Modes Summary
LPMx BITS
SCSR1
[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
FLASH
POWER
EXIT
CONDITION
LOW-POWER MODE
CPU running normally
XX
00
On
Off
On
On
On
On
On
On
On
On
—
Peripheral
Interrupt,
External Interrupt,
Reset,
IDLE1 − (LPM0)
IDLE2 − (LPM1)
On
On
PDPINTA
Wakeup
Interrupts,
External Interrupt,
Reset,
01
1X
Off
Off
Off
Off
On
Off
On
Off
On
Off
On
PDPINTA
HALT − (LPM2)
[PLL/OSC power down]
Reset,
PDPINTA
†
Off
†
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357).
other power-down options
2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these
peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
Refer to the SCSR1 register for details on the peripheral clock enable bits.
46
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
digital I/O and shared pin functions
The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared
between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
D
D
Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.
Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
description of shared I/O pins
Each shared I/O pin has three bits that define its operation:
D
D
MUX control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.
I/O direction bit — if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).
D
I/O data bit — if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.
The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers.
A summary of shared pin configurations and associated bits is shown in Table 10.
Table 10. Shared Pin Configurations
†
PIN FUNCTION SELECTED
I/O PORT DATA AND DIRECTION
MUX
MUX CONTROL
VALUE AT
RESET
CONTROL
REGISTER
(name.bit #)
(MCRA.n = 0)
Secondary
Function
(MCRA.n = 1)
‡
§
REGISTER
DATA BIT NO.
DIR BIT NO.
Primary Function
(MCRx.n)
PORT A
¶
PDPINTA
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
IOPA0
MCRA.0
MCRA.1
MCRA.2
MCRA.3
MCRA.4
MCRA.5
MCRA.6
0
0
0
0
0
0
0
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PADATDIR
0
1
2
3
4
5
6
8
IOPA1
IOPA2
IOPA3
IOPA4
IOPA5
IOPA6
9
10
11
12
13
14
XINT2/ADCSOC/
CAP1/IOPA7
CLKOUT
MCRA.7
0
PADATDIR
7
15
PORT B
T2PWM
IOPB1
IOPB2
SCITXD
SCIRXD
OPB5
−
XINT1/IOPB0
IOPB1
MCRA.8
MCRA.9
0
0
0
0
0
0
0
0
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
0
1
2
3
4
5
6
7
8
9
IOPB2
MCRA.10
MCRA.11
MCRA.12
MCRA.13
MCRA.14
MCRA.15
10
11
12
13
14
15
IOPB3
IOPB4
OPB5
−
†
‡
§
¶
Valid only if the I/O function is selected on the pin
If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.
If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.
Even when MCRA.0 = 0, the PDPINT circuitry is still active.
47
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
digital I/O control registers
Table 11 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers
are memory-mapped to the data space.
Table 11. Addresses of Digital I/O Control Registers
ADDRESS
7090h
REGISTER
MCRA
NAME
I/O MUX control register A
7098h
PADATDIR
PBDATDIR
I/O port A data and direction register
I/O port B data and direction register
709Ah
CAUTION:
The bit definitions of the MCRA, PADATDIR, and PBDATDIR registers are not compatible
with those of other 24x/240x/240xA devices.
watchdog (WD) timer module
The 2401A device includes a watchdog (WD) timer module. The WD function of this module monitors software
and hardware operation by generating a system reset if it is not periodically serviced by software by having the
correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization
to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK
signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer
begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up
sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following:
D
WD Timer
−
−
Seven different WD overflow rates
A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and
generates a system reset if an incorrect value is written to the register
−
WD check bits that initiate a system reset if an incorrect value is written to the WD control register
(WDCR)
D
Automatic activation of the WD timer, once system reset is released
Three WD control registers located in control register frame beginning at address 7020h.
−
NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte
is read as zeros. Writing to the upper byte has no effect.
Table 12 shows the different WD overflow (time-out) selections. Figure 19 shows the WD block diagram.
The watchdog can be disabled in software by writing ‘1’ to bit 6 of the WDCR register (WDCR.6) while bit 5 of
the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent
to the WDDIS pin of the TMS320F243/241 devices.
48
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
watchdog (WD) timer module (continued)
Table 12. WD Overflow (Time-out) Selections
WATCHDOG
CLOCK RATE
WD PRESCALE SELECT BITS
†
WDCLK DIVIDER
WDPS2
WDPS1
WDPS0
FREQUENCY (Hz)
WDCLK/1
‡
X
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
2
0
WDCLK/2
1
0
1
0
1
4
WDCLK/4
8
WDCLK/8
16
32
64
WDCLK/16
WDCLK/32
WDCLK/64
†
‡
WDCLK = CLKOUT/512
X = Don’t care
49
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
watchdog (WD) timer module (continued)
CLKOUT
CLKIN
3-bit
Prescaler
÷ 512
PLL
6-Bit
Free-
Running
Counter
/64
/32
On-Chip
Oscillator or
External
Clock
/16
/8
WDCLK
/4
/2
System
Reset
CLR
000
001
010
011
100
101
WDPS
WDCR.2−
0
2 1 0
110
111
WDFLAG
WDCR.7
WDCR.6
WDDIS
Reset Flag
WDCNTR.7−0
8-Bit Watchdog
Counter
Internal
Pullup
One-Cycle
Delay
PS/257
CLR
RS pin
System
Reset
Request
WDKEY.7−0
Bad Key
Watchdog
Reset Key
Register
55 + AA
Detector
Good Key
WDCHK2−0
†
WDCR.5−3
Bad WDCR Key
3
3
System
Reset
1 0 1
(Constant
Value)
†
Writing to bits WDCR.5−3 with anything but the correct pattern (101) generates a system reset.
Figure 19. Block Diagram of the WD Module
50
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
development support
Texas Instruments (TI) offers an extensive line of development tools for the 240x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of 240x-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 (supports x24x multiprocessor system debug)
TMS320LF2407 EVM (Evaluation module for 2407 DSP)
See Table 13 and Table 14 for complete listings of development support tools for the 240x. For information on
pricing and availability, contact the nearest TI field sales office or authorized distributor.
Table 13. Development Support Tools
DEVELOPMENT TOOL
PLATFORM
Software
PART NUMBER
TMDSCCS2000-1
TMDS3P701014
Code Composer Studio v.2.2
PC
Hardware − Emulation Debug Tools
PC
XDS510PP Pod (Parallel Port) with JTAG cable
Table 14. TMS320x24x-Specific Development Tools
DEVELOPMENT TOOL
PLATFORM
PART NUMBER
Hardware − Evaluation/Starter Kits
2401A eZdsp
F2407A EVM
PC
PC
TMDSeZD2401
TMDS3P701016A
XDS510, Code Composer Studio, and XDS510PP are trademarks of Texas Instruments.
PC is a trademark of International Business Machines Corp.
51
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320 is a trademark of Texas Instruments.
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
device and development support tool nomenclature (continued)
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, VF) and temperature range (for example, A). Figure 20 provides a legend for reading the complete
TMS320Lx2401A device name.
TMS 320 LF 2401A
VF
A
PREFIX
TMX = experimental device
TMP = prototype device
TMS = qualified device
TEMPERATURE RANGE
−40°C to 85°C
A
=
†
PACKAGE TYPE
VF
DEVICE FAMILY
320 = TMS320 DSP Family
= 32-pin LQFP
DEVICE
2401A
TECHNOLOGY
LC = Low-voltage CMOS (3.3 V)
LF = Flash EEPROM (3.3 V)
†
LQFP = Low-Profile Quad Flatpack
Figure 20. TMS320Lx2401A Device Nomenclature
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s guides for all devices and development
support tools; and hardware and software applications. Useful reference documentation includes:
D
Silicon Errata
TMS320LF2401A, TMS320LC2401A DSP Controller Silicon Errata (literature number SPRZ013)
describes the known advisories of various revisions of the silicon.
User’s Guides
−
D
−
−
TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number
SPRU160) describes the TMS320C24x 16−bit fixed−point digital signal processor controller. Covered
are its architecture, internal register structure, data and program addressing, and instruction set. Also
includes instruction set comparisons and design considerations for using the XDS510 emulator.
TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number
SPRU357). This reference guide describes the architecture, system hardware, peripherals, and
general operation of the TMS320Lx2407A/x2406A/x2404A/x2403A/x2402A/x2401A digital signal
processor (DSP) controllers. This book is also applicable to TMS320Lx2407/2406/2402 and future
derivatives of the 240x family.
D
Application Reports
−
Getting Started in C and Assembly Code with the TMS320LF240x DSP (literature number SPRA755)
This application report presents basic code for initializing and operating the TMS320LF240x DSP
devices. Two functionally equivalent example programs are presented: one written in assembly
language and the other in C language. Detailed discussions of each program are provided that explain
numerous compiler and assembler directives, code requirements, and hardware-related requirements.
The programs are ready to run on either the TMS320LF2407 Evaluation Module (EVM) or the eZdspo.si
LF2407 development kit. However, they are also intended for use as a code template for any
TMS320LF240x (LF240x) or TMS320LF240xA (LF240xA) DSP target system.
−
Motor Speed Measurement Considerations Using TMS320C24x DSPs (literature number SPRA771)
The TMS320C24x generation of DSPs provide appropriate internal hardware for interfacing with
low−cost, external−speed sensors for motor speed measurement applications. The periodic output
signal from the speed sensor is applied to the capture input pin of the DSP and the signal’s period is
measured. This information is then used to calculate the motor speed. However, this calculation of
motor speed depends on several system parameters. These parameters affect the scaling and
normalization factors that must be used in the speed calculation routine for accurate measurements.
This application report, therefore, gives an analysis of the speed measurement system to show the
effect of system parameters on the calculated speed. The choice of appropriate scaling and
normalization factors for a given system is also discussed. Finally, code examples are given to show the
software implementation of the speed calculation routine.
−
3.3 V DSP for Digital Motor Control (literature number SPRA550) New generations of motor control
digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher
performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce
no additional system cost and no significant complication in interfacing with TTL and CMOS compatible
components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like
5-V-based designs, good engineering practice should be exercised to minimize noise and EMI effects
by proper component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a
mixed signal environment, with high and low voltage analog and switching signals, such as a motor
control system. In addition, software techniques such as Random PWM method can be used by special
54
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
features of the Texas Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise
effects caused by EMI radiation.
This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control
applications. The application report first describes a scenario of a 3.3-V-only motor controller indicating
that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists.
Cost−effective 3.3-V − 5-V interfacing techniques are then discussed for the situations where such
interfacing is needed. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also
discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are addressed. Guidelines
for component layout and printed circuit board (PCB) design that can reduce system noise and EMI
effects are summarized in the last section.
To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding the TMS320LF2401A/TMS320LC2401A data sheet (literature number
SPRS161), use the comments@books.sc.ti.com email address, which is a repository for feedback. For
questions
and
support,
contact
the
Product
Information
Center
listed
at
the
http://www.ti.com/sc/docs/pic/home.htm site.
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
LF2401A AND LC2401A ELECTRICAL SPECIFICATIONS DATA
This document contains information on products in more than one phase of development. The electrical
specifications for the TMS320LF2401A device are Production Data (PD) and those for the TMS320LC2401A
device are Product Preview (PP). These electrical specifications are subject to change.
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, V , V
, and V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
DD DDO
CCA
V
range (LF2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 5.5 V
CCP
Input voltage range, V
Output voltage range, V
Input clamp current, I (V < 0 or V > V
Output clamp current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
IN
O
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK IN
OK
IN
CC
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O O CC
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
stg
†
Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
‡
recommended operating conditions
MIN
NOM
3.3
0
MAX
3.6
0
UNIT
V
V
V
V
V
/V
Supply voltage
V
= V
0.3 V
3
0
DD DDO
DDO DD
Supply ground
V
SS
§
ADC supply voltage
3
3.3
5
3.6
5.25
40
V
CCA
Flash programming supply voltage (LF2401A)
Device clock frequency (system clock)
High-level input voltage
4.75
2
V
CCP
f
MHz
CLKOUT
V
All inputs
All inputs
2
V
V
IH
IL
V
Low-level input voltage
0.8
− 2
− 4
− 8
2
¶
¶
¶
¶
¶
¶
Output pins Group 1
Output pins Group 2
Output pins Group 3
Output pins Group 1
Output pins Group 2
Output pins Group 3
mA
mA
mA
mA
mA
mA
°C
I
I
High-level output source current, V
= 2.4 V
OH
OH
4
Low-level output sink current, V
Case temperature (A version)
= V
MAX
OL
OL
OL
8
T
C
− 40
85
N
Flash endurance for the array (Write/erase cycles)
− 40°C to 85°C
10K
cycles
f
‡
§
¶
Refer to the mechanical data package page for thermal resistance values, Θ (junction-to-ambient) and Θ (junction-to-case).
JA JC
V
CCA
should not exceed V
by 0.3 V.
DD
Primary signals and their groupings:
Group 1: PDPINTA/IOPA0, T2PWM, PWM1−PWM6 (IOPA1−IOPA6), IOPB0, IOPB1, OPB5, TMS/XF, RS, TCK, TDI
Group 2: SCITXD/IOPB3, SCIRXD/IOPB4, TDO/IOPB2
Group 3: CAP1, IOPA7, CLKOUT
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 3.0 V, I = I MAX
2.4
DD
OH OH
All outputs at 50 µA
= I MAX
V
V
High-level output voltage
V
OH
V
− 0.2
DDO
Low-level output voltage
Input current (low level)
I
0.4
−30
2
V
OL
OL OL
With pullup
−10
10
−16
16
I
IL
V
= 3.3 V, V = 0 V
IN
µA
DD
DD
With pulldown
With pullup
2
I
I
Input current (high level)
V
V
= 3.3 V, V = V
IN DD
µA
IH
With pulldown
30
2
Output current, high-impedance state (off-state)
Input capacitance
= V
O DD
or 0 V
µA
pF
pF
OZ
C
C
2
3
i
Output capacitance
o
current consumption by power-supply pins over recommended operating case temperature range
†
at 40-MHz CLOCKOUT (LF2401A)
‡
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
A test code running in Flash does the
following:
1. Enables clock to all peripherals
2. Toggles all PWM outputs at
20 kHz
I
I
3. Performs a continuous
conversion of all ADC channels
4. An infinite loop which transmits a
character out of SCI and
executes MACD instructions
NOTE: All I/O pins are floating.
75
10
90
22
mA
Operational Current
DD
ADC module current
mA
CCA
†
‡
I
is the current flowing into the V
and V
pins. I
current includes the current drawn by the PLL module.
DD
DD
DDO
DD
The MAX numbers are at maximum temperature and voltage.
current consumption by power-supply pins over recommended operating case temperature range
†
at 40-MHz CLOCKOUT (LC2401A)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
A test code running in Flash does the
following:
1. Enables clock to all peripherals
2. Toggles all PWM outputs at
20 kHz
I
I
3. Performs a continuous
conversion of all ADC channels
4. An infinite loop which transmits a
character out of SCI and
executes MACD instructions
NOTE: All I/O pins are floating.
55
70
mA
Operational Current
DD
ADC module current
11
25
mA
CCA
†
I
is the current flowing into the V
DD
and V
DDO
pins. I current includes the current drawn by the PLL module.
DD
DD
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
current consumption by power-supply pins over recommended operating case temperature range
†
during low-power modes at 40-MHz CLOCKOUT (LF2401A)
PARAMETER
Operational Current
ADC module current
Operational Current
ADC module current
Operational Current
ADC module current
MODE
OPERATING CONDITIONS
MIN
TYP
60
MAX
70
UNIT
mA
mA
mA
µA
I
I
I
I
I
I
DD
Clock to all peripherals is enabled.
No I/O pins are switching.
LPM0
12
35
5
18
40
CCA
DD
Clock to all peripherals is disabled.
No I/O pins are switching.
LPM1
LPM2
10
CCA
DD
80
5
100
10
µA
Clock to all peripherals is disabled.
Flash is powered down.
µA
CCA
†
I
is the current flowing into the V
DD
and V pins.
DDO
DD
current consumption by power-supply pins over recommended operating case temperature range
†
during low-power modes at 40-MHz CLOCKOUT (LC2401A)
PARAMETER
Operational Current
ADC module current
Operational Current
ADC module current
Operational Current
ADC module current
MODE
OPERATING CONDITIONS
MIN
TYP
40
MAX
50
UNIT
mA
mA
mA
µA
I
I
I
I
I
I
DD
Clock to all peripherals is enabled.
No I/O pins are switching.
LPM0
12
15
5
18
22
10
70
10
CCA
DD
Clock to all peripherals is disabled.
No I/O pins are switching.
LPM1
LPM2
CCA
DD
50
5
µA
Clock to all peripherals is disabled.
µA
CCA
†
I
is the current flowing into the V
DD
and V pins.
DDO
DD
58
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
current consumption graphs
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
45
CLKOUT Frequency (MHz)
Figure 21. LF2401A Typical Current Consumption (With Peripheral Clocks Enabled)
reducing current consumption
240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 15 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and
Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals.
Table 15. Typical Current Consumption by Various Peripherals (at 40 MHz)
PERIPHERAL MODULE
CURRENT REDUCTION (mA)
EVA
6.1
†
†
ADC
2.8
1.9
SCI
†
ADC current shown is at 30 MHz.
59
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
LOAD
C
T
I
OH
Where:
I
V
C
=
=
=
−2 mA (all outputs)
1.5 V
50-pF typical load-circuit capacitance
OH
LOAD
T
Figure 22. Test Load Circuit
signal transition levels
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.8 V.
Figure 23 shows output levels.
2.4 V (V
80%
)
OH
20%
0.4 V (V
)
OL
Figure 23. Output Levels
Output transition times are specified as follows:
D
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
D
For alow-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 24 shows the input levels.
2.0 V (V
90%
)
IH
10%
0.8 V (V
)
IL
Figure 24. Input Levels
Input transition times are specified as follows:
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
D
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
60
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
CI
XTAL1
CO
RS
INT
CLKOUT
RESET pin RS
XINT1, XINT2
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don’t care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
general notes on timing parameters
All output signals from the 2401A device (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.
61
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
external reference crystal/clock with PLL circuit enabled
timing with the PLL circuit enabled
PARAMETER
MIN
MAX
13
UNIT
Resonator
Crystal
4
†
4
4
20
f
x
Input clock frequency
MHz
CLKIN
20
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 t
] (see Figure 25)
c(CO)
PARAMETER
PLL MODE
MIN
TYP
MAX
UNIT
ns
†
t
t
t
t
t
t
t
X4 mode
25
Cycle time, CLKOUT
Fall time, CLKOUT
c(CO)
4
4
ns
f(CO)
Rise time, CLKOUT
ns
r(CO)
†
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
LF2401A
LF2401A
LC2401A
LC2401A
X4 mode @ 2 mA load
H−3
H −3
H−5
H −5
H
H
H
H
H+3
ns
w(COL)
w(COH)
w(COL)
w(COH)
†
X4 mode @ 2 mA load
H+3
H+5
H+5
ns
†
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
X4 mode @ 2 mA load
ns
†
X4 mode @ 2 mA load
ns
†
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum.
timing requirements (see Figure 25)
MIN
MAX
250
5
UNIT
ns
t
t
t
t
t
Cycle time, XTAL1/CLKIN
c(Cl)
Fall time, XTAL1/CLKIN
ns
f(Cl)
Rise time, XTAL1/CLKIN
5
ns
r(Cl)
Pulse duration, XTAL1/CLKIN low as a percentage of t
40
40
60
60
%
w(CIL)
w(CIH)
c(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of t
c(Cl)
%
t
c(CI)
t
w(CIH)
t
t
r(Cl)
f(Cl)
t
w(CIL)
XTAL1/CLKIN
CLKOUT
t
w(COH)
t
t
w(COL)
f(CO)
t
t
c(CO)
r(CO)
Figure 25. CLKIN-to-CLKOUT Timing With PLL and External Clock in ×4 Mode
62
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
RS timing
timing requirements for a reset [H = 0.5t
] (see Figure 26 and Figure 27)
c(CO)
MIN NOM
MAX
UNIT
†
t
t
8t
cycles
Pulse duration, stable CLKIN to RS high
Pulse duration, RS low
w(RSL)
c(CI)
8t
cycles
w(RSL2)
c(CI)
t
PLL lock-up time
98304t
cycles
cycles
p
c(CI)
t
36H
Delay time, reset vector executed after PLL lock time
d(EX)
†
During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles.
V
/V
DD DDO
t
d(EX)
t
p
t
w(RSL)
RS
CLKIN
XTAL1
(See
Note B)
t
OSCST
(See Note C)
TDI
(See
Note D)
TDI/OPB5
BOOT_EN
CLKOUT
(See
Note E)
I/Os
Code-Dependent
Hi-Z
NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before
the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New
generation emulators such as SPI515 and XDS510 USB emulators have a built-in protection mechanism to take care of this
requirement.
B. XTAL1 refers to the internal oscillator clock if an on-chip oscillator is used.
C.
t
is the oscillator start-up time, which is dependent on crystal/resonator and board design.
OSCST
D. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase,
this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low).
E. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The
CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal
to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 26. Power-On Reset
XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital.
XDS510 and XDS510PP, are trademarks of Texas Instruments.
63
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
RS timing (continued)
t
d(EX)
t
p
t
w(RSL2)
RS
CLKIN
†
XTAL1
TDI
‡
TDI/OPB5
BOOT_EN
§
CLKOUT
I/Os
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin
functions as TDI (if TRST is high) or OPB5 (if TRST is low).
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Hi-Z
Code-Dependent
†
‡
§
NOTE A: During warm resets, if the watchdog module is enabled and issues a reset, then the RS pin will be an output and driven low for the WD
pulse duration − 128 CLKIN cycles.
Figure 27. Warm Reset
64
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
RS timing (continued)
switching characteristics over recommended operating conditions for a reset [H = 0.5t
(see Figure 28)
]
c(CO)
PARAMETER
Watchdog reset pulse width
MIN
MAX
UNIT
ns
t
t
t
128t
w(RSL1)
d(EX)
p
c(CI)
36H
ns
Delay time, reset vector executed after PLL lock time
PLL lock time (input cycles)
98304t
c(CI)
ns
t
d(EX)
t
p
t
w(RSL1)
RS
CLKIN
†
XTAL1
TDI
‡
TDI/OPB5
BOOT_EN
§
CLKOUT
I/Os
XTAL1 refers to internal oscillator clock if on-chip oscillator is used.
The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the “TDI/OPB5” phase, this pin
functions as TDI (if TRST is high) or OPB5 (if TRST is low).
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Code-Dependent
Hi-Z
†
‡
§
Figure 28. Watchdog Initiated Reset
65
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
low-power mode timing
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 29, Figure 30, and Figure 31)
]
c(CO)
PARAMETER
LOW-POWER MODES
MIN
TYP
MAX
UNIT
IDLE1
LPM0
LPM1
12 × t
15 × t
c(CO)
Delay time, CLKOUT switching to
program execution resume
t
t
ns
d(WAKE-A)
IDLE2
c(CO)
Delay time, Idle instruction executed to
CLKOUT high
IDLE2
LPM1
4t
c(CO)
ns
d(IDLE-COH)
OSC start-up
and PLL lock
time
Delay time, wake-up interrupt
asserted to oscillator running
t
ms
d(WAKE-OSC)
HALT
LPM2
{PLL/OSC power down}
Delay time, Idle instruction executed to
oscillator power off
t
t
4t
c(CO)
ns
ns
d(IDLE-OSC)
36H
Delay time, reset vector executed after RS high
d(EX)
t
d(WAKE−A)
A0−A15
†‡
CLKOUT
§
WAKE INT
†
‡
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
WAKE INT can be any valid interrupt or RESET.
§
Figure 29. IDLE1 Entry and Exit Timing − LPM0
t
d(IDLE−COH)
A0−A15
†‡
CLKOUT
§
WAKE INT
t
d(WAKE−A)
†
‡
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
WAKE INT can be any valid interrupt or RESET.
§
Figure 30. IDLE2 Entry and Exit Timing − LPM1
66
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
low-power mode timing (continued)
t
d(EX)
t
p
A0−A15
t
d(IDLE−OSC)
t
d(IDLE−COH)
CLKOUT
RESET
t
d(WAKE−OSC)
t
w(RSL)
†
‡
In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software.
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform
depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
Figure 31. HALT Mode − LPM2
67
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
LPM2 wake-up timing
switching characteristics over recommended operating conditions (see Figure 32)
PARAMETER
MIN
MAX
UNIT
ns
†
†
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
(6 + 1)t
+ 12
c(CO)
Delay time, PDPINTA low to PWM
high-impedance state
t
d(PDP-PWM)HZ
(12+ 1)t
c(CO)
+ 12
ns
Delay time, INT low/high to interrupt-vector
fetch
t
10t
c(CO)
+ t (PDP−WAKE)
w
ns
d(INT)
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 32)
MIN
MAX
UNIT
ns
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
6t
c(CO)
t
t
Pulse duration, PDPINTA input low
PLL lock-up time
w(PDP−WAKE)
12t
c(CO)
98304t
c(CI)
cycles
p
Oscillator Disabled
XTAL1
†
t
OSC
t
p
CLKIN
‡§
CLKOUT
t
w(PDP−WAKE)
PDPINTA
t
d(PDP-PWM)HZ
PWM
t
d(INT)
Interrupt Vector or
¶
CPU IDLE State (LPM2)
CPU Status
#
Next Instruction
†
‡
§
t
is the oscillator start-up time.
OSC
CLKOUT frequency after LPM2 wake-up will be the same as that upon entering LPM2 (x4 shown as an example).
Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT
waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the
XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately.
PDPINTA interrupt vector, if PDPINTA interrupt is enabled.
¶
#
If PDPINTA interrupt is disabled.
Figure 32. LPM2 Wakeup Using PDPINTA
68
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
TIMING EVENT MANAGER INTERFACE
PWM timing
PWM refers to all PWM outputs on EVA.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t ] (see Figure 33)
c(CO)
PARAMETER
MIN
2H+5
13
MAX
UNIT
ns
†
t
t
Pulse duration, PWMx output high/low
w(PWM)
d(PWM)CO
21
ns
Delay time, CLKOUT low to PWMx output switching
†
PWM outputs may be 100%, 0%, or increments of t
with respect to the PWM period.
c(CO)
CLKOUT
t
d(PWM)CO
t
w(PWM)
PWMx
Figure 33. PWM Output Timing
69
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
capture timing
timing requirements (see Figure 34)
MIN
c(CO)
c(CO)
MAX
UNIT
6t
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
t
Pulse duration, CAP1 input low/high
ns
w(CAP)
12t
CLKOUT
t
w(CAP)
CAP1
Figure 34. Capture Input Timing
70
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
interrupt timing
INT refers to XINT1, XINT2, and PDPINTA.
switching characteristics over recommended operating conditions (see Figure 35)
PARAMETER
MIN
MAX
UNIT
ns
†
†
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
(6 + 1)t
+ 12
c(CO)
Delay time, PDPINTA low to PWM
high-impedance state
t
d(PDP-PWM)HZ
(12+ 1)t
+ 12
ns
c(CO)
Delay time, INT low/high to interrupt-vector
fetch
t
10t
+t
ns
d(INT)
c(CO) w(INT)
†
Includes i/p qualifier cycles plus synchronization plus propagation delay
timing requirements (see Figure 35)
MIN
c(CO)
c(CO)
c(CO)
c(CO)
MAX
UNIT
6t
12t
6t
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
t
t
Pulse duration, INT input low/high
Pulse duration, PDPINTA input low
ns
w(INT)
ns
w(PDP)
12t
CLKOUT
t
w(PDP)
PDPINTA
t
d(PDP-PWM)HZ
†
PWM
t
w(INT)
XINT1, XINT2
t
d(INT)
A0−A15
(Internal Bus)
Interrupt Vector
†
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA is taken
high depends on the state of the FCOMPOE bit.
Figure 35. External Interrupts Timing
71
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
general-purpose input/output timing
switching characteristics over recommended operating conditions (see Figure 36)
PARAMETER
MIN
MAX
UNIT
t
t
t
Delay time, CLKOUT low to GPIO low/high
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
All GPIOs
All GPIOs
All GPIOs
13
21
12
15
ns
ns
ns
d(GPO)CO
r(GPO)
f(GPO)
timing requirements [H = 0.5t
] (see Figure 37)
c(CO)
MIN
MAX
UNIT
t
2H+15
ns
Pulse duration, GPI high/low
w(GPI)
CLKOUT
t
d(GPO)CO
GPIO
t
r(GPO)
t
f(GPO)
Figure 36. General-Purpose Output Timing
CLKOUT
GPIO
t
w(GPI)
Figure 37. General-Purpose Input Timing
72
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V
and V
.
CCA
SSA
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V and V from coupling into the ADC analog stage. All ADC specifications
SS
CC
are given with respect to V
unless otherwise noted.
SSA
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for V ≤ V
; 3FFh for V ≥ V
)
I
SSA
I
CCA
Conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
recommended operating conditions
MIN
NOM
3.3
0
MAX
UNIT
†
V
V
Analog supply voltage
3.0
3.6
V
V
V
CCA
†
Analog ground
SSA
V
AI
Analog input voltage, ADCIN00−ADCIN04
V
V
REFHI
REFLO
†
V
CCA
and V must be stable, within 1/2 LSB of the required resolution, during the entire conversion time.
SSA
ADC operating frequency
MIN
MAX
UNIT
ADC operating frequency
2
30
MHz
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
TYP
MAX UNIT
I
Analog input leakage
1
mA
ADCIN
Non-sampling
Sampling
10
30
Typical capacitive load on
analog input pin
C
Analog input capacitance
pF
ai
Difference between the actual step width and the
ideal value
E
Differential nonlinearity error
2
2
LSB
LSB
ms
DNL
Maximum deviation from the best straight line
through the ADC transfer characteristics, excluding
the quantization error
E
INL
Integral nonlinearity error
Delay time, power-up to ADC
valid
t
Time to stabilize analog stage after power-up
10
d(PU)
Analog input source impedance needed for
Z
AI
Analog input source impedance
Zero-offset error
conversions to remain within specifications at min
10
Ω
t
w(SH)
8
10 LSB
73
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
†
internal ADC module timing (see Figure 38)
MIN
MAX
33.3
500
UNIT
ns
t
t
t
t
t
t
t
Cycle time, ADC prescaled clock
c(AD)
‡
Pulse duration, total sample/hold and conversion time
Pulse duration, sample and hold time
Pulse duration, total conversion time
ns
w(SHC)
w(SH)
§
2t
c(AD)
32t
ns
c(AD)
10t
ns
w(C)
c(AD)
c(CO)
c(CO)
c(CO)
Delay time, start of conversion to beginning of sample and hold
Delay time, end of conversion to data loaded into result register
Delay time, ADC flag to ADC interrupt
2t
2t
2t
ns
d(SOC-SH)
d(EOC)
d(ADCINT)
ns
ns
†
The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals (literature number SPRU357) for more details.
‡
§
The total sample/hold and conversion time is determined by the summation of t
Can be varied by ACQ Prescaler bits in the ADCCTRL1 register
, t
, t
, and t .
d(EOC)
d(SOC-SH) w(SH) w(C)
t
c(AD)
9
Bit Converted
ADC Clock
8
7
6
5
4
3
2
1
0
Analog Input
EOC/Convert
t
w(C)
t
w(SH)
Internal Start/
Sample Hold
t
d(SOC−SH)
Start of Convert
t
d(EOC)
t
w(SHC)
XFR to RESULTn
ADC Interrupt
t
d(ADCINT)
Figure 38. Analog-to-Digital Internal Module Timing
74
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
Flash parameters @40 MHz CLOCKOUT (LF2401A)
PARAMETER
MIN
TYP
30
MAX UNIT
Time/Word (16-bit)
µs
ms
ms
†
Clear/Programming time
Time/4K Sector
Time/4K Sector
130
350
†
Erase time
Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle
I
(V
pin current)
5
15
mA
CCP CCP
†
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when V = 3.3 V and V = 5 V, and any deviation from these values could affect the timing parameters. Aging and process
variance could also impact the timing parameters.
DD CCP
migrating from other 240xA devices to Lx2401A
This section outlines some of the issues to be considered while migrating a design from the 240xA family to the
Lx2401A. The Lx2401A shares the same CPU core (and hence, the same instruction set) as the 240xA.
Furthermore, the peripherals implemented on the Lx2401A are a subset of those found in the 240xA family.
However, some features of a particular peripheral may not be present on the 2401A. This must be taken into
consideration while porting code to the Lx2401A. Other issues to be considered for migration are as follows.
PLL
The PLL used in the Lx2401A is different than the one used in the 240xA family. The Lx2401A PLL does not
need the external loop-filter components. The PLL is bypassed when the TMS and TRST pins are sensed low
at reset.
NOTE: The device may come up in PLL bypass mode if the TMS and TRST pins are sensed low when the
emulator/debugger is brought up (with the XDS510/XDS510PP/XDS510PP+ pod connected to the target
hardware). If this happens, the device reset pin (RS) must be activated once (after the emulator is up and
running) to bring it out of PLL bypass mode. Note that this is a concern only when the JTAG connector is
connected for debug and does not have an impact when the code is free-run without the JTAG connector—i.e.,
there are no issues when the target hardware is powered up without the JTAG connector. Before attempting
to program flash through JTAG, it must be ensured that the PLL is not in bypass mode.
on-chip bootloader
Boot ROM is a 256-word ROM mapped in program space 0000h−00FFh. This ROM will be enabled if the
BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the
TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when:
TRST
RS
=
=
=
0
0
0
TDI
(In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the
execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG
connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is
low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected
(TRST = 1), it can be achieved by writing a “0” into bit 3 of the SCSR2 register.
GPIO
The multiplexing scheme of the GPIO pins with other functional pins is different in the Lx2401A. Because of this,
the bit assignments for the MCRA, PADATDIR, and PBDATDIR registers of the Lx2401A is not compatible with
the bit assignments of the 240xA family.
75
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
EV
The Event Manager of the Lx2401A has reduced functionality when compared to that of the 240xA family.
Following are the important differences:
D
D
D
D
D
There is no QEP unit.
There is only one “Capture” input (CAP1).
Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM).
There is no provision to feed an external clock to the timers.
There is no external direction control pin for the timers.
Due to these differences, some of the bits in the EV registers are not applicable in the Lx2401A and are shaded
gray. Refer to Table 16, Lx2401A DSP Peripheral Register Description, for more details.
ADC
pins
The Lx2401A ADC has only five input channels as compared to eight or sixteen channels in the 240xA family.
Therefore, the 4-bit fields in the CHSELSEQn registers should be programmed with values from 0−4 only.
The Lx2401A ADC does not have dedicated V
the necessary reference.
and V
pins. Instead, the V
and V
pins provide
REFHI
REFLO
CCA
SSA
The following pins, which are available in other 240xA devices, have been internally tied as indicated:
CAP2, CAP3 − low
TDIRA
TCLKINA
BIO
− low
− low
− high
DINR
The device ID contained in the DINR register is 0810h.
XF pin
The XF pin has to be enabled by writing a 1 to Bit 0 of the SCSR4 register before it can be used.
76
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ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description
Table 16 is a collection of all the programmable registers of the Lx2401A and is provided as a quick reference.
Table 16. Lx2401A DSP Peripheral Register Description
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
DATA MEMORY SPACE
CPU STATUS REGISTERS
ARP
DP(6)
ARB
1
OV
DP(4)
CNF
XF
OVM
DP(3)
TC
1
DP(2)
SXM
1
INTM
DP(1)
C
DP(8)
DP(0)
1
ST0
ST1
DP(7)
1
DP(5)
1
1
PM
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
—
—
—
—
—
—
—
—
—
—
00004h
00005h
00006h
IMR
INT6 MASK
INT5 MASK
INT4 MASK
INT3 MASK
INT2 MASK
INT1 MASK
Reserved
GREG
IFR
—
—
—
—
—
—
—
—
—
—
INT6 FLAG
INT5 FLAG
INT4 FLAG
INT3 FLAG
INT2 FLAG
INT1 FLAG
SYSTEM REGISTERS
IRQ0.15
IRQ0.7
IRQ1.15
IRQ1.7
IRQ2.15
IRQ2.7
IRQ0.14
IRQ0.6
IRQ1.14
IRQ1.6
IRQ2.14
IRQ2.6
IRQ0.13
IRQ0.5
IRQ1.13
IRQ1.5
IRQ2.13
IRQ2.5
IRQ0.12
IRQ0.11
IRQ0.3
IRQ1.11
IRQ1.3
IRQ2.11
IRQ2.3
IRQ0.10
IRQ0.2
IRQ1.10
IRQ1.2
IRQ2.10
IRQ2.2
IRQ0.9
IRQ0.1
IRQ1.9
IRQ1.1
IRQ2.9
IRQ2.1
IRQ0.8
IRQ0.0
IRQ1.8
IRQ1.0
IRQ2.8
IRQ2.0
07010h
07011h
PIRQR0
PIRQR1
PIRQR2
IRQ0.4
IRQ1.12
IRQ1.4
IRQ2.12
IRQ2.4
07012h
07013h
Illegal
IAK0.15
IAK0.7
IAK1.15
IAK1.7
IAK2.15
IAK2.7
IAK0.14
IAK0.6
IAK1.14
IAK1.6
IAK2.14
IAK2.6
IAK0.13
IAK0.5
IAK1.13
IAK1.5
IAK2.13
IAK2.5
IAK0.12
IAK0.4
IAK1.12
IAK1.4
IAK2.12
IAK2.4
IAK0.11
IAK0.3
IAK1.11
IAK1.3
IAK2.11
IAK2.3
IAK0.10
IAK0.2
IAK1.10
IAK1.2
IAK2.10
IAK2.2
IAK0.9
IAK0.1
IAK1.9
IAK1.1
IAK2.9
IAK2.1
IAK0.8
IAK0.0
IAK1.8
IAK1.0
IAK2.8
IAK2.0
07014h
07015h
PIACKR0
PIACKR1
PIACKR2
07016h
07017h
Illegal
—
ADC CLKEN
—
CLKSRC
SCI CLKEN
—
LPM1
SPI CLKEN
—
LPM0
CAN CLKEN
—
CLK PS2
EVB CLKEN
—
CLK PS1
EVA CLKEN
—
CLK PS0
—
ILLADR
—
07018h
SCSR1
SCSR2
—
—
I/P
07019h
WD
OVERRIDE
QUALIFIER
CLOCKS
—
—
BOOT_EN
—
DON
PON
0701Ah
0701Bh
Illegal
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XF ENABLE
DIN8
SCSR4
DINR
DIN15
DIN7
DIN14
DIN6
DIN13
DIN5
DIN12
DIN4
DIN11
DIN3
DIN10
DIN2
DIN9
DIN1
0701Ch
0701Dh
DIN0
Illegal
Illegal
V15
V7
V14
V6
V13
V5
V12
V4
V11
V3
V10
V2
V9
V1
V8
V0
0701Eh
0701Fh
PIVR
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
77
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ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
WD CONTROL REGISTERS
07020h
to
Illegal
07022h
07023h
07024h
07025h
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
WDCNTR
WDKEY
Illegal
Illegal
07026h
to
07028h
07029h
WDFLAG
WDDIS
WDCHK2
WDCHK1
WDCHK0
Illegal
WDPS2
WDPS1
WDPS0
WDCR
0702Ah
to
0703Fh
07040h
to
0704Fh
Reserved
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
STOP
BITS
EVEN/ODD
PARITY
PARITY
ENABLE
LOOP BACK
ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
SCI
CHAR0
07050h
07051h
07052h
07053h
07054h
SCICCR
RX ERR
INT ENA
—
SW RESET
BAUD13
BAUD5
—
—
BAUD12
BAUD4
—
TXWAKE
BAUD11
BAUD3
—
SLEEP
BAUD10
BAUD2
—
TXENA
BAUD9
BAUD1
RXENA
BAUD8
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
BAUD15
(MSB)
BAUD14
BAUD6
BAUD0
(LSB)
BAUD7
TXRDY
RX/BK
INT ENA
TX
INT ENA
TX EMPTY
07055h
07056h
07057h
07058h
07059h
RX ERROR
ERXDT7
RXDT7
RXRDY
ERXDT6
RXDT6
BRKDT
ERXDT5
RXDT5
FE
OE
PE
RXWAKE
ERXDT1
RXDT1
—
SCIRXST
ERXDT4
RXDT4
ERXDT3
RXDT3
ERXDT2
RXDT2
ERXDT0
RXDT0
SCIRXEMU
SCIRXBUF
Illegal
TXDT7
TXDT6
TXDT5
TXDT4
TXDT3
TXDT2
TXDT1
TXDT0
SCITXBUF
0705Ah
to
0705Eh
Illegal
Illegal
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
SOFT
SCI
FREE
0705Fh
—
—
—
—
SCIPRI
07060h
to
0706Fh
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
78
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
EXTERNAL INTERRUPT CONTROL REGISTERS
XINT1
FLAG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07070h
07071h
XINT1CR
XINT2CR
XINT1
POLARITY
XINT1
PRIORITY
XINT1
ENA
—
XINT2
FLAG
—
—
—
XINT2
POLARITY
XINT2
PRIORITY
XINT2
ENA
—
07072h
to
0708Fh
Illegal
DIGITAL I/O CONTROL REGISTERS
MCRA.15
MCRA.7
MCRA.14
MCRA.6
MCRA.13
MCRA.5
MCRA.12
MCRA.4
MCRA.11
MCRA.3
MCRA.10
MCRA.2
MCRA.9
MCRA.1
MCRA.8
MCRA.0
07090h
07091h
07092h
07093h
07094h
MCRA
MCRB
Illegal
MCRB.15
MCRB.7
MCRB.14
MCRB.6
MCRB.13
MCRB.5
MCRB.12
MCRB.4
MCRB.11
MCRB.3
MCRB.10
MCRB.2
MCRB.9
MCRB.1
MCRB.8
MCRB.0
Illegal
MCRC.15
MCRC.7
E7DIR
IOPE7
—
MCRC.14
MCRC.6
E6DIR
MCRC.13
MCRC.5
E5DIR
MCRC.12
MCRC.4
E4DIR
MCRC.11
MCRC.3
E3DIR
MCRC.10
MCRC.2
E2DIR
MCRC.9
MCRC.1
E1DIR
IOPE1
F1DIR
MCRC.8
MCRC.0
E0DIR
IOPE0
F0DIR
MCRC
07095h
PEDATDIR
PFDATDIR
IOPE6
IOPE5
IOPE4
IOPE3
IOPE2
F6DIR
F5DIR
F4DIR
F3DIR
F2DIR
07096h
07097h
07098h
07099h
0709Ah
0709Bh
0709Ch
0709Dh
0709Eh
0709Fh
—
IOPF6
IOPF5
IOPF4
IOPF3
IOPF2
IOPF1
IOPF0
Illegal
A7DIR
IOPA7
A6DIR
IOPA6
A5DIR
IOPA5
A4DIR
IOPA4
A3DIR
IOPA3
A2DIR
IOPA2
A1DIR
IOPA1
A0DIR
IOPA0
PADATDIR
PBDATDIR
PCDATDIR
PDDATDIR
Illegal
Illegal
Illegal
Illegal
B7DIR
IOPB7
B6DIR
IOPB6
B5DIR
IOPB5
B4DIR
IOPB4
B3DIR
IOPB3
B2DIR
IOPB2
B1DIR
IOPB1
B0DIR
IOPB0
C7DIR
IOPC7
C6DIR
IOPC6
C5DIR
IOPC5
C4DIR
IOPC4
C3DIR
IOPC3
C2DIR
IOPC2
C1DIR
IOPC1
C0DIR
IOPC0
D7DIR
IOPD7
D6DIR
IOPD6
D5DIR
IOPD5
D4DIR
IOPD4
D3DIR
IOPD3
D2DIR
IOPD2
D1DIR
IOPD1
D0DIR
IOPD0
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS
ADC
S/W RESET
ACQ
ACQ
ACQ
ACQ
—
SOFT
FREE
PRESCALE3 PRESCALE2 PRESCALE1 PRESCALE0
070A0h
ADCCTRL1
CONV PRE-
SCALE (CPS) UOUS RUN
CONTIN-
INT
PRIORITY
SEQ1/2
CASCADE
—
—
—
—
EVB SOC
Reset SEQ1
EN SEQ1
INT ENA
INT ENA
INT FLAG
SEQ1
EVA SOC
EN SEQ1
SOC SEQ1
SEQ1 BUSY
SEQ1 Mode1 SEQ1 Mode0
INT ENA INT ENA
SEQ2 Mode1 SEQ2 Mode0
070A1h
070A2h
ADCCTRL2
MAXCONV
EXT SOC
Reset SEQ2
EN SEQ1
INT FLAG
SEQ2
EVB SOC
EN SEQ2
SOC SEQ2
—
SEQ2 BUSY
—
—
—
—
—
—
—
—
MAXCONV2
2
MAXCONV2
1
MAXCONV2
0
MAXCONV1
3
MAXCONV1
2
MAXCONV1
1
MAXCONV1
0
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
CONV 2
CONV 0
CONV 2
CONV 0
CONV 2
CONV 0
CONV 6
CONV 4
CONV 10
CONV 8
CONV 14
CONV 12
CONV 2
CONV 0
CONV 6
CONV 4
CONV 10
CONV 8
CONV 14
CONV 12
070A3h
070A4h
070A5h
070A6h
CHSELSEQ1
CHSELSEQ2
CHSELSEQ3
CHSELSEQ4
CONV 6
CONV 6
CONV 4
CONV 4
CONV 10
CONV 8
CONV 10
CONV 8
CONV 14
CONV 12
SEQ CNTR3
CONV 14
CONV 12
SEQ CNTR2
SEQ CNTR1 SEQ CNTR0
070A7h
AUTO_SEQ_SR
SEQ2
SEQ2
SEQ2
SEQ2
SEQ1
SEQ1
SEQ1
SEQ1
STATE 3
STATE 2
STATE 1
STATE 0
STATE 3
STATE 2
STATE 1
STATE 0
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070A8h
070A9h
070AAh
070ABh
070ACh
070ADh
070AEh
070AFh
RESULT0
RESULT1
RESULT2
RESULT3
RESULT4
RESULT5
RESULT6
RESULT7
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
00
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D2
0
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the cor-
responding pins have not been bonded out of the device.
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED)
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D8
D0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070B0h
070B1h
070B2h
070B3h
070B4h
070B5h
070B6h
RESULT8
RESULT9
RESULT10
RESULT11
RESULT12
RESULT13
RESULT14
RESULT15
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
070B7h
070B8h
Reserved
Illegal
070B9h
to
070FFh
07100h
to
Reserved
073FFh
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVA
—
T1TOADC(0)
D15
T2STAT
TCOMPOE
D14
T1STAT
—
T2TOADC
T1TOADC(1)
07400h
07401h
07402h
07403h
07404h
GPTCONA
T1CNT
—
T2PIN
T1PIN
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
D7
D6
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
T1CMPR
T1PR
D7
D6
D4
D3
D1
D0
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
FREE
—
SOFT
TENABLE
—
TMODE1
TCLKS0
TMODE0
TCLD1
TPS2
TPS1
TECMPR
TPS0
—
T1CON
TCLKS1
TCLD0
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS − EVA (CONTINUED)
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D8
D0
07405h
07406h
07407h
07408h
T2CNT
T2CMPR
T2PR
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
D15
D14
D13
D5
D12
D11
D10
D2
D9
D8
D7
D6
D4
D3
D1
D0
FREE
T2SWT1
SOFT
TENABLE
—
TMODE1
TCLKS0
TMODE0
TCLD1
TPS2
TCLD0
TPS1
TECMPR
TPS0
SELT1PR
T2CON
TCLKS1
07409h
to
07410h
Illegal
FULL AND SIMPLE COMPARE UNIT REGISTERS − EVA
PDPINTA
STATUS
CENABLE
—
CLD1
—
CLD0
—
SVENABLE
—
ACTRLD1
—
ACTRLD0
—
FCOMPOE
—
07411h
COMCONA
—
07412h
07413h
07414h
07415h
07416h
07417h
Illegal
SVRDIR
D2
D1
D0
CMP6ACT1
CMP2ACT1
CMP6ACT0
CMP2ACT0
CMP5ACT1
CMP1ACT1
CMP5ACT0
CMP1ACT0
ACTRA
CMP4ACT1
CMP4ACT0
CMP3ACT1
CMP3ACT0
Illegal
—
—
—
—
DBT3
DBT2
DBT1
—
DBT0
—
DBTCONA
EDBT3
EDBT2
EDBT1
DBTPS2
DBTPS1
DBTPS0
Illegal
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CMPR1
CMPR2
CMPR3
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07418h
07419h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0741Ah
to
Illegal
0741Fh
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
82
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
CAPTURE UNIT REGISTERS − EVA
CAPRES
CAPQEPN
CAP3EN
CAP2EDGE
—
CAP3TSEL
CAP3EDGE
CAP12TSEL
CAP3TOADC
07420h
07421h
07422h
CAPCONA
CAP1EDGE
—
Illegal
—
CAP3FIFO
CAP2FIFO
CAP1FIFO
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
—
D15
D7
—
D14
D6
—
D13
D5
—
D12
D4
—
D11
D3
—
D10
D2
—
—
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
07423h
07424h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07425h
07426h
07427h
Illegal
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0
CAP1FBOT
CAP2FBOT
CAP3FBOT
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
07428h
07429h
D15
D7
D14
D6
D13
D5
D12
D4
D11
D3
D10
D2
0742Ah
to
Illegal
0742Bh
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS
T1OFINT
ENA
T1UFINT
ENA
T1CINT
ENA
—
—
—
—
—
0742Ch
EVAIMRA
T1PINT
ENA
CMP3INT
ENA
CMP2INT
ENA
CMP1INT
ENA
PDPINTA
ENA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0742Dh
0742Eh
EVAIMRB
EVAIMRC
T2OFINT
ENA
T2UFINT
ENA
T2CINT
ENA
T2PINT
ENA
—
—
—
—
—
CAP3INT
ENA
CAP2INT
ENA
CAP1INT
ENA
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
peripheral register description (continued)
Table 16. Lx2401A DSP Peripheral Register Description (Continued)
BIT 15
BIT 7
BIT 14
BIT 6
BIT 13
BIT 5
BIT 12
BIT 4
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
ADDR
REG
EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS (CONTINUED)
T1OFINT
FLAG
T1UFINT
FLAG
T1CINT
FLAG
—
—
—
—
—
0742Fh
EVAIFRA
T1PINT
FLAG
CMP3INT
FLAG
CMP2INT
FLAG
CMP1INT
FLAG
PDPINTA
FLAG
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07430h
07431h
EVAIFRB
EVAIFRC
T2OFINT
FLAG
T2UFINT
FLAG
T2CINT
FLAG
T2PINT
FLAG
—
—
—
—
—
CAP3INT
FLAG
CAP2INT
FLAG
CAP1INT
FLAG
07432h
to
Illegal
074FFh
07500h
to
0753Fh
Reserved
I/O MEMORY SPACE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0FF0Fh
0FFFFh
FCMR
WSGR
WAIT-STATE GENERATOR CONTROL REGISTER
—
—
—
—
—
BVIS.1
BVIS.0
ISWS.2
ISWS.1
ISWS.0
DSWS.2
DSWS.1
DSWS.0
PSWS.2
PSWS.1
PSWS.0
These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corre-
sponding pins have not been bonded out of the device.
84
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
MECHANICAL DATA
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
0,45
0,25
0,20
M
0,80
24
17
25
16
32
9
0,13 NOM
1
8
5,60 TYP
7,20
SQ
6,80
Gage Plane
9,20
8,80
SQ
0,25
0,05 MIN
0°−ā7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040172/D 04/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Typical Thermal Resistance Characteristics
PARAMETER
DESCRIPTION
°C/W
Θ
JA
Θ
JC
ψ
JT
Junction-to-ambient
55.61
Junction-to-case
13.89
2.5
Junction-to-top of package
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄ ꢈꢅꢉ ꢊꢋ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢌꢄ ꢈꢅ ꢉ ꢊ
ꢍ ꢂꢎ ꢌ ꢏꢐ ꢀꢑ ꢏꢆ ꢆꢒ ꢑꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS161G device-specific data
sheet to make it an SPRS161H revision.
Scope: Changed status of TMS320LC2401A from Advance Information to Production Data.
PAGE
HIGHLIGHTS
Changed the maximum values in the current consumption by power-supply pins over recommended operating case
temperature range at 40-MHz CLOCKOUT (LC2401A) table
57
†
Changed the ADC Module current values in the current consumption by power-supply pins over recommended
operating case temperature range during low-power modes at 40-MHz CLOCKOUT (LF2401A) table
58
58
62
†
Changed all but the first two TYP values in the current consumption by power-supply pins over recommended
†
operating case temperature range during low-power modes at 40-MHz CLOCKOUT (LC2401A) table
Changed the PLL mode for Pulse duration, CLKOUT low and high in the switching characteristics over
recommended operating conditions [H = 0.5 t ] table and changed the minimum value in the note.
c(CO)
63
73
Changed the unit for delay time in the timing requirements for a reset [H = 0.5t
] table
c(CO)
Changed ADCIN07 to ADCIN04 in the recommended operating conditions table
86
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈ ꢅ ꢉꢊ ꢋ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢌ ꢄꢈ ꢅꢉꢊ
ꢍꢂ ꢎ ꢌꢏ ꢐꢀꢑ ꢏ ꢆꢆ ꢒꢑ ꢂ
SPRS161H − MARCH 2001 − REVISED MARCH 2004
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