TMS320LC541PZ-80_技术文档

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

Fast Return From Interrupt

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

– Full-Duplex Serial Port to Support 8- or

16-Bit Transfers (’541, ’LC545, and

’LC546 Only)

– Time-Division Multiplexed (TDM) Serial

Port (’542, ’543, ’548, and ’549 Only)

– Buffered Serial Port (BSP) (’542, ’543,

’LC545, ’LC546, ’548, and ’549 Only)

– 8-Bit Parallel Host Port Interface (HPI)

(’542, ’LC545, ’548, and ’549)

40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

– One 16-Bit Timer

– External-Input/Output (XIO) Off Control

to Disable the External Data Bus,

Address Bus and Control Signals

Data Bus With a Bus Holder Feature

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

Address Bus With a Bus Holder Feature

(’548 and ’549 Only)

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space (’548 and ’549 Only)

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

†

IEEE Std 1149.1 (JTAG) Boundary Scan

192K × 16-Bit Maximum Addressable

Memory Space (64K Words Program,

64K Words Data, and 64K Words I/O)

Logic

25-ns Single-Cycle Fixed-Point Instruction

Execution Time [40 MIPS] for 5-V Power

Supply (’C541 and ’C542 Only)

On-Chip ROM with Some Configurable to

Program/Data Memory

20-ns and 25-ns Single-Cycle Fixed-Point

Instruction Execution Time (50 MIPS and

40 MIPS) for 3.3-V Power Supply (’LC54x)

Dual-Access On-Chip RAM

Single-Access On-Chip RAM (’548/’549)

Single-Instruction Repeat and

Block-Repeat Operations for Program Code

15-ns Single-Cycle Fixed-Point Instruction

Execution Time (66 MIPS) for 3.3-V Power

Supply (’LC54xA, ’548, ’LC549)

Block-Memory-Move Instructions for Better

Program and Data Management

12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS) for

3.3-V Power Supply (’LC549)

Instructions With a 32-Bit Long Word

Operand

Instructions With Two- or Three-Operand

Reads

10-ns Single-Cycle Fixed-Point Instruction

Execution Time (100 MIPS) for 3.3-V Power

Supply (2.5-V Core) (’VC549)

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

UNLESS OTHERWISE NOTED this document contains ADVANCE

INFORMATION on new products in the sampling or preproduction phase

of development. Characteristic data and other specifications are subject

to change without notice.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

description

The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families

(hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard

architecture that has one program memory bus and three data memory buses. These processors also provide

an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip

memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction

set, which is the basis of the operational flexibility and speed of these DSPs.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the

high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions

with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’C54x,

’LC54x, and ’VC54x versions include the control mechanisms to manage interrupts, repeated operations, and

function calls.

Table 1 provides an overview of the ’54x generation of DSPs. The table shows significant features of each

device including the capacity of on-chip RAM and ROM memories, the peripherals, the execution time of one

machine cycle, and the type of package with its total pin count.

Table 1. Characteristics of the ’54x Processors

ON-CHIP

PERIPHERALS

MEMORY

NOMINAL

VOLTAGE (V)

CYCLE

TIME (ns)

DSP TYPE

PACKAGE TYPE

†

RAM

ROM

SERIAL

PORT

TIMER

HPI

(Word) (Word)

‡

§

2

§

2

¶

2

¶

2

¶

2

||

2

||

2

||

2

||

2

TMS320C541

TMS320LC541

TMS320C542

TMS320LC542

TMS320LC543

TMS320LC545

TMS320LC545A

TMS320LC546

TMS320LC546A

5.0

3.3

5.0

3.3

5K

28K

2K

1

No

25

100-pin TQFP

20/25

25

100-pin TQFP

10K

6K

Yes

No

144-pin TQFP

2K

20/25

128-pin TQFP/144-pin TQFP

100-pin TQFP

2K

#

48K

Yes

No

128-pin TQFP

6K

15/20/25 128-pin TQFP

20/25 100-pin TQFP

15/20/25 100-pin TQFP

6K

No

144-pin TQFP/144-pin star

BGA

TMS320LC548

TMS320LC549

3.3

32K

2K

3

1

Yes

15/20

3.3

32K

16K

3

1

Yes

12.5/15

10

144-pin TQFP/144-pin star BGA

TMS320VC549

Legend:

3.3 (2.5 core)

TQFP = Thin Quad Flatpack

BGA = Ball Grid Array

†

‡

§

¶

#

||

The dual-access RAM (single access RAM on ’548 and ’549 devices) can be configured as data memory or program/data memory.

For ’C541/’LC541, 8K words of ROM can be configured as program memory or program/data memory.

Two standard (general purpose) serial ports

One TDM and one BSP

For ’LC545/’LC546, 16K words of ROM can be configured as program memory or program/data memory.

One standard and one BSP

One TDM and two BSPs

star is a trademark of Texas Instruments Incorporated.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320C541, TMS320LC541

†

PZ PACKAGE

(TOP VIEW)

V

1

D5

D4

D3

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SS

A10

2

A11

3

A12

A13

D2

4

5

D1

D0

A14

A15

6

RS

7

CV

X2/CLKIN

X1

8

DD

V

9

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CLKOUT

SS

DD

V

CV

SS

CV

DD

READY

PS

V

SS

TMS

TCK

TRST

TDI

DS

IS

R/W

MSTRB

IOSTRB

MSC

XF

TDO

EMU1/OFF

EMU0

HOLDA

IAQ

TOUT

CNT

HOLD

BIO

CLKMD3

CLKMD2

CLKMD1

MP/MC

†

DV

is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320C541PZ/TMS320LC541PZ (100-pin TQFP packages).

For the ’C541/’LC541 (100-pin packages), no letter in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin

names denotes standard serial port (where n = 0 or 1 port).

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320C542/TMS320LC542

†‡

PGE PACKAGE

(TOP VIEW)

1

108

107

106

105

104

103

102

101

100

99

V

SS

NC

SS

NC

2

3

V

SS

DD

SS

4

DV

D5

D4

D3

D2

D1

D0

RS

DD

5

A10

HD7

A11

A12

A13

A14

A15

6

7

8

9

10

11

12

13

14

15

16

98

CV

HAS

97

X2/CLKIN

X1

HD3

DD

96

V

95

SS

DD

94

CLKOUT

CV

93

V

SS

HPIENA

CV

HCS 17

HR/W 18

READY 19

PS 20

92

91

DD

90

V

TMS

SS

89

DS 21

88

TCK

IS 22

87

TRST

R/W 23

MSTRB 24

IOSTRB 25

MSC 26

XF 27

86

TDI

TDO

EMU1/OFF

EMU0

TOUT

HD2

85

84

83

82

HOLDA 28

IAQ 29

81

80

CNT

HOLD 30

BIO 31

MP/MC 32

79

CLKMD3

CLKMD2

CLKMD1

78

77

DV

V

NC 35

33

V

DV

NC

76

DD

SS

DD

34

75

74

V

36

73

SS

†

‡

NC = No connection

DV is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320C542PGE/’LC542PGE (144-pin TQFP packages).

For the ’C542/’LC542 (144-pin TQFP packages), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX

pin names denotes buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin

names denotes time-division multiplexed (TDM) serial port.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC542

PBK PACKAGE

(TOP VIEW)

†

128127126125124123122121 120119 118 117 116 115 114 113 112 111 110 109108107106105104103102101100 99 98 97

96

1

V

SS

2

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

DV

D5

D4

D3

D2

D1

D0

RS

DD

3

A10

HD7

A11

A12

A13

A14

A15

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CV

X2/CLKIN

X1

DD

HAS

V

HD3

SS

DD

CLKOUT

CV

V

SS

HPIENA

CV

HCS

HR/W

READY

PS

DD

V

SS

TMS

DS

TCK

IS

TRST

R/W

TDI

TDO

MSTRB

IOSTRB

MSC

EMU1/OFF

EMU0

TOUT

HD2

XF

HOLDA

IAQ

CNT

HOLD

BIO

CLKMD3

CLKMD2

CLKMD1

MP/MC

DV

DD

V

SS

DV

SS

DD

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

†

DV

is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320LC542PBK (128-pin TQFP package).

For the ’LC542 (128-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names

denotes buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names

denotes time-division multiplexed (TDM) serial port.

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC543

†

PZ PACKAGE

(TOP VIEW)

V

1

D5

D4

D3

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SS

A10

2

A11

3

A12

A13

D2

4

5

D1

D0

A14

A15

6

RS

7

CV

X2/CLKIN

X1

8

DD

V

9

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CLKOUT

SS

DD

V

CV

SS

CV

DD

READY

PS

V

SS

TMS

TCK

TRST

TDI

DS

IS

R/W

MSTRB

IOSTRB

MSC

XF

TDO

EMU1/OFF

EMU0

HOLDA

IAQ

TOUT

CNT

HOLD

BIO

CLKMD3

CLKMD2

CLKMD1

MP/MC

†

DV

is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320LC543PZ (100-pin TQFP package).

For the ’LC543 (100-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX denotes

buffered serial port (BSP). The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX denotes time-division

multiplexed (TDM) serial port.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC545

PBK PACKAGE

(TOP VIEW)

†

128127126125124123122121 120119 118 117 116 115 114 113 112 111 110 109108107106105104103102101100 99 98 97

96

1

V

SS

2

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

DV

D5

D4

D3

D2

D1

D0

RS

DD

3

A10

HD7

A11

A12

A13

A14

A15

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CV

X2/CLKIN

X1

DD

HAS

V

HD3

SS

DD

CLKOUT

CV

V

SS

HPIENA

CV

HCS

HR/W

READY

PS

DD

V

SS

TMS

DS

TCK

IS

TRST

R/W

TDI

TDO

MSTRB

IOSTRB

MSC

EMU1/OFF

EMU0

TOUT

HD2

XF

HOLDA

IAQ

CNT

HOLD

BIO

CLKMD3

CLKMD2

CLKMD1

MP/MC

DV

DD

V

SS

DV

SS

DD

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

†

DV

is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the for the

TMS320LC545PBK (128-pin TQFP package).

For the ’LC545 (128-pin TQFP package), the letter B in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names

denotes buffered serial port (BSP). No letter in front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes

standard serial port.

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC546

†

PZ PACKAGE

(TOP VIEW)

V

1

D5

D4

D3

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SS

A10

2

A11

3

A12

A13

D2

4

5

D1

D0

A14

A15

6

RS

7

CV

X2/CLKIN

X1

8

DD

V

9

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

CLKOUT

V

CV

SS

DD

CV

DD

READY

V

PS

DS

SS

TMS

TCK

TRST

TDI

IS

R/W

MSTRB

IOSTRB

MSC

XF

TDO

EMU1/OFF

EMU0

HOLDA

IAQ

TOUT

CNT

HOLD

BIO

CLKMD3

CLKMD2

CLKMD1

MP/MC

†

DV

is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the for the

TMS320LC546PZ (100-pin TQFP package).

For the ’LC546 (100-pin TQFP package), the letter B in front of CLKR, FSR, DR, FSX, and DX denotes buffered

serial port (BSP). No letter in front of CLKR, FSR, DR, FSX, and DX denotes standard serial port.

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC548, TMS320LC549, and TMS320VC549

†‡

PGE PACKAGE

(TOP VIEW)

1

108

107

106

105

104

103

102

101

100

99

V

A18

A17

SS

A22

2

3

V

SS

DD

SS

4

DV

A16

D5

5

A10

HD7

A11

A12

A13

A14

A15

6

D4

D3

D2

D1

D0

RS

X2/CLKIN

X1

HD3

CLKOUT

7

8

9

10

11

12

13

14

15

16

98

CV

HAS

97

DD

96

V

95

SS

DD

94

CV

93

V

SS

HPIENA

CV

HCS 17

HR/W 18

READY 19

PS 20

92

91

DD

SS

TMS

90

V

89

DS 21

88

TCK

IS 22

87

TRST

R/W 23

MSTRB 24

IOSTRB 25

MSC 26

XF 27

HOLDA 28

IAQ 29

HOLD 30

BIO 31

86

TDI

TDO

85

84

EMU1/OFF

EMU0

TOUT

HD2

TEST1

CLKMD3

CLKMD2

CLKMD1

83

82

81

80

79

78

MP/MC 32

77

DV

V

BDR1 35

BFSR1

33

V

DV

BDX1

BFSX1

76

DD

SS

DD

34

75

74

36

73

†

‡

NC = No connection

DV is the power supply for the I/O pins while CV

is the power supply for the core CPU, and V is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320LC548PGE (144-pin TQFP package).

For the ’LC548, ’LC549 and ’VC549 (144-pin TQFP package), the letter B in front of CLKRn, FSRn, DRn,

CLKXn, FSXn, and DXn pin names denotes buffered serial port (BSP), where n = 0 or 1 port. The letter T in

front of CLKR, FSR, DR, CLKX, FSX, and DX pin names denotes time-division multiplexed (TDM) serial port.

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

TMS320LC548, TMS320LC549, TMS320VC549

GGU PACKAGE

(BOTTOM VIEW)

13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the TMS320LC548,

TMS320LC549, and TMS320VC549 (144-pin BGA package).

The ’54x signal descriptions table lists each terminal name, function, and operating mode(s) for the

TMS320LC548GGU, TMS320LC549GGU, and TMS320VC549GGU.

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

Pin Assignments for the TMS320LC548GGU, TMS320LC549GGU, and TMS320VC549GGU

†

(144-Pin BGA Package)

SIGNAL

QUADRANT 1

SIGNAL

QUADRANT 2

SIGNAL

QUADRANT 3

SIGNAL

QUADRANT 4

BGA BALL #

V

A1

B1

C2

C1

D4

D3

D2

D1

E4

E3

E2

E1

F4

F3

F2

F1

G2

G1

G3

G4

H1

H2

H3

H4

J1

BFSX1

BDX1

N13

M13

L12

L13

K10

K11

K12

K13

J10

J11

V

N1

N2

M3

N3

K4

A19

A20

A13

A12

B11

A11

D10

C10

B10

A10

D9

C9

B9

SS

A22

SS

BCLKR1

HCNTL0

V

DV

V

SS

DV

DD

SS

DV

V

SS

V

SS

DD

A10

DD

D6

CLKMD1

CLKMD2

CLKMD3

TEST1

HD2

BCLKR0

TCLKR

BFSR0

HD7

A11

A12

A13

A14

A15

L4

D7

D8

M4

N4

K5

TFSR/TADD

BDR0

D9

D10

D11

D12

HD4

D13

D14

D15

HD5

TOUT

HCNTL1

TDR

L5

EMU0

EMU1/OFF

TDO

J12

J13

H10

H11

H12

H13

G12

G13

G11

G10

F13

F12

F11

F10

E13

E12

E11

E10

D13

D12

D11

C13

C12

C11

B13

B12

M5

N5

K6

CV

DD

HAS

BCLKX0

TCLKX

A9

D8

C8

B8

V

TDI

V

SS

L6

SS

TRST

HINT

CVDD

M6

N6

M7

N7

L7

SS

CV

DD

HCS

TCK

A8

TMS

BFSX0

CV

B7

DD

HR/W

READY

PS

V

TFSX/TFRM

HRDY

V

SS

HDS1

A7

SS

CV

C7

D7

A6

DD

HPIENA

DV

K7

V

DD

SS

HDS2

DV

DS

V

SS

V

SS

N8

M8

L8

IS

CLKOUT

HD3

X1

HD0

BDX0

TDX

IACK

HBIL

NMI

B6

DD

A0

R/W

C6

D6

A5

MSTRB

IOSTRB

MSC

XF

K8

A1

A2

A3

HD6

A4

A5

A6

A7

A8

A9

X2/CLKIN

RS

N9

M9

L9

J2

B5

J3

D0

C5

D5

A4

HOLDA

IAQ

J4

D1

INT0

INT1

INT2

INT3

K9

K1

K2

K3

L1

D2

N10

M10

L10

N11

M11

L11

N12

M12

HOLD

BIO

D3

B4

D4

C4

A3

MP/MC

D5

CV

DD

DV

L2

A16

HD1

B3

DD

V

SS

L3

V

SS

V

SS

CV

DD

A21

C3

A2

BDR1

M1

M2

A17

A18

BCLKX1

BFSR1

V

SS

B2

SS

is the power supply for the core CPU, and V

†

DV

is the power supply for the I/O pins while CV

is the ground for both the I/O pins and the

SS

DD

core CPU.

DD

11

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

’54x Signal Descriptions

TERMINAL

DESCRIPTION

DATA SIGNALS

†

NAME

TYPE

A22 (MSB)

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address

externaldata/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0

also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for

extended program memory addressing (’548 and ’549 only).

On the ’548 and ’549 devices, the address bus have a feature called bus holder that eliminates passive

components and the power dissipation associated with it. The bus holder keeps the address bus at the previous

logic level when the bus goes into a high-impedance state.

O/Z

A8

A7

A6

A5

A4

A3

A2

A1

A0

(LSB)

D15 (MSB)

D14

D13

D12

D11

D10

D9

Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core

CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when

not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF

is low.

The data bus has a feature called bus holder that eliminates passive components and the power dissipation

associated with it. The bus holder keeps the data bus at the previous logic level when the bus goes into a

high-impedance state.

D8

D7

I/O/Z

D6

D5

D4

D3

D2

D1

D0

(LSB)

INITIALIZATION, INTERRUPT AND RESET OPERATIONS

Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching

the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when

EMU1/OFF is low.

IACK

O/Z

I

INT0

INT1

INT2

INT3

External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the

interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.

†

I = Input, O = Output, Z = High impedance

12

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SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

’54x Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)

Nonmaskableinterrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

NMI

RS

I

Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS

is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various

registers and status bits.

Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes

the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode,

off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP.

MP/MC

CNT

I

I/O level select. For 5-V operation, all input and output voltage levels are TTL-compatible when CNT is pulled

down to a low level. For 3-V operation with CMOS-compatible I/O interface levels, CNT is pulled to a high level.

MULTIPROCESSING SIGNALS

Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes

the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC

instruction, and all other instructions sample BIO during the read phase of the pipeline.

BIO

XF

I

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low

by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in

multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when

OFF is low, and is set high at reset.

O/Z

MEMORY CONTROL SIGNALS

Data, program, andI/Ospaceselectsignals. DS, PS, andISarealwayshighunlessdrivenlowforcommunicating

to a particular external space. Active period corresponds to valid address information. Placed into a

high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is

low.

DS

PS

IS

O/Z

I

Memorystrobesignal. MSTRBisalwayshighunlesslow-levelassertedtoindicateanexternalbusaccesstodata

or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance

state when OFF is low.

MSTRB

READY

R/W

Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.

If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

processor performs ready-detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device and is normally

high(inreadmode), unlessassertedlowwhentheDSPperformsawriteoperation. Placedinthehigh-impedance

state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.

O/Z

I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O

device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when

EMU1/OFF is low.

IOSTRB

HOLD

O/Z

I

Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by

the ’54x, these lines go into high-impedance state.

Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that

the address, data, and control lines are in a high-impedance state, allowing them to be available to the external

circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.

HOLDA

O/Z

Microstate complete signal. MSC goes low when the last wait state of two or more internal software wait states

programmed are executed. If connected to the READY line, MSC forces one external wait state after the last

internal wait state has been completed. MSC also goes into the high-impedance state when EMU1/OFF is low.

MSC

O/Z

†

I = Input, O = Output, Z = High impedance

13

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

’54x Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

MEMORY CONTROL SIGNALS (CONTINUED)

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus and goes into the high-impedance state when EMU1/OFF is low.

IAQ

O/Z

OSCILLATOR/TIMER SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

isboundedbythefallingedgesofthissignal. CLKOUTalsogoesintothehigh-impedancestatewhenEMU1/OFF

is low.

CLKOUT

O/Z

CLKMD1

CLKMD2

CLKMD3

Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure

different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed

functional description of these pins.

I

Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can

become input to the device using this pin. The internal machine cycle time is determined by the clock

operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).

X2/CLKIN

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.

X1

O

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle

wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.

TOUT

O/Z

BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS

Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port

receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is

not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.

BCLKR0

BCLKR1

I

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven

by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the

buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0

and BCLKX1 go into the high-impedance state when OFF is low.

BCLKX0

BCLKX1

I/O/Z

BDR0

BDR1

I

O/Z

I

Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.

BDX0

BDX1

Bufferedserial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are

placed in the high-impedance state when not transmitting and when EMU1/OFF is low.

BFSR0

BFSR1

Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive

process, beginning the clocking of the RSR.

Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the

data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of

BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control

register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low.

BFSX0

BFSX1

I/O/Z

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS

Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive

shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and

CLKR1 can be sampled as an input via IN0 bit of the SPC register.

CLKR0

CLKR1

I

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by

the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled

as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF

is low.

CLKX0

CLKX1

I/O/Z

I

DR0

DR1

Serial-data-receive input. Serial data is received in the RSR by DR.

†

I = Input, O = Output, Z = High impedance

14

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

’54x Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED)

DX0

DX1

Serialporttransmitoutput. SerialdataistransmittedfromtheXSRviaDX. DX0andDX1areplacedinthehigh-im-

pedance state when not transmitting and when EMU1/OFF is low.

O/Z

I

FSR0

FSR1

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive pro-

cess, beginning the clocking of the RSR.

Framesynchronizationpulsefortransmitinput/output.ThefallingedgeoftheFSXpulseinitiatesthedatatransmit

process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input.

FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1.

This pin goes into the high-impedance state when EMU1/OFF is low.

FSX0

FSX1

I/O/Z

TDM SERIAL PORT SIGNALS

TDM receive clock input

TCLKR

I

TDR

I

TDM serial data-receive input

TFSR/TADD

TCLKX

I/O

TDM receive frame synchronization or TDM address

TDM transmit clock

I/O/Z

O/Z

I/O/Z

TDX

TDM serial data-transmit output

TFSX/TFRM

TDM transmit frame synchronization

HOST PORT INTERFACE SIGNALS

Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The

signals go into the high-impedance state when EMU1/OFF is low.

HD0–HD7

I/O/Z

I

HCNTL0

HCNTL1

Control inputs

HBIL

HCS

I

Byte-identification input

Chip-select input

HDS1

HDS2

I

Data strobe inputs

HAS

I

Address strobe input

HR/W

HRDY

Read/write input

O/Z

Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.

Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance

HINT

O/Z

I

state when EMU1/OFF is low.

HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open

or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,

and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active

only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the

Electrical Characteristics section for the input current requirements for this pin.

HPIENA

SUPPLY PINS

CV

DV

Supply

+V . CV

DD

is the dedicated power supply for the core CPU.

is the dedicated power supply for I/O pins.

is the dedicated power ground for the device.

DD

SS

+V . DV

DD

V

†

Ground. V

SS

I = Input, O = Output, Z = High impedance

15

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

’54x Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

IEEE1149.1 TEST PINS

†

IEEE standard 1149.1 test clock. This is normally a free-running clock signal with a 50% duty cycle. The changes

onthetest-accessport(TAP)ofinputsignalsTMSandTDIareclockedintotheTAPcontroller,instructionregister,

or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the

falling edge of TCK.

TCK

I

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDI

I

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when EMU1/OFF is low.

TDO

TMS

TRST

O/Z

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF

condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined

as input/output by way of IEEE standard 1149.1 scan system.

EMU0

I/O/Z

Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or

from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When

TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output

drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not

for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:

TRST = low,

EMU1/OFF

I/O/Z

EMU0 = high

EMU1/OFF = low

DEVICE TEST PIN

Test1 – Reserved for internal use only (’LC548, ’LC549, and ’VC549 only). This pin must not be connected

(NC).

TEST1

I

†

I = Input, O = Output, Z = High impedance

architecture

The ’54x DSPs use an advanced, modified Harvard architecture that maximizes processing power by

maintaining three separate bus structures for data memory and one for program memory. Separate program

and data spaces allow simultaneous access to program instructions and data, providing a high degree of

parallelism. For example, two read and one write operations can be performed in a single cycle. Instructions

with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’54x include

the control mechanisms to manage interrupts, repeated operations, and function calls.

The functional block diagram includes the principal blocks and bus structure in the ’54x devices.

16

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

functional block diagram of the ’54x internal hardware

Program Address Generation

Logic (PAGEN)

Data Address Generation

Logic (DAGEN)

System Control

Interface

ARAU0, ARAU1,

AR0–AR7

ARP, BK, DP, SP

PC, IPTR, RC,

BRC, RSA, REA

PAB

PB

Memory

And

External

Interface

CAB

CB

DAB

DB

Peripherals

(Serial Ports,

HPI, etc.)

EAB

EB

EXP Encoder

X

D

A

B

MUX

T Register

B A C D

T

D

A

P C D

T

A B C

D

S

A

Sign Ctr

A(40)

B(40)

Sign Ctr

MUX

Multiplier (17 × 17)

Barrel Shifter

0

ALU(40)

B

A

M U B

A

B

Fractional

MUX

Legend:

S

A Accumulator A

B Accumulator B

C CB Data Bus

D DB Data Bus

MSW/LSW

Select

Adder(40)

COMP

E

EB Data Bus

M MAC Unit

E

P

S

T

PB Program Bus

Barrel Shifter

T Register

TRN

TC

ZERO

SAT

ROUND

U ALU

17

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

central processing unit (CPU)

The CPU of the ’54x devices contains:

A 40-bit arithmetic logic unit (ALU)

Two 40-bit accumulators

A barrel shifter

A 17 × 17-bit multiplier/adder

A compare, select and store unit (CSSU)

arithmetic logic unit (ALU)

The ’54x devices perform 2s-complement arithmetic using: a 40-bit arithmetic logic unit (ALU) and two 40-bit

accumulators (ACCA and ACCB). The ALU also can perform Boolean operations.

The ALU can function as two 16-bit ALUs and perform two 16-bit operations simultaneously when the C16 bit

in status register 1 (ST1) is set.

accumulators

The accumulators, ACCA and ACCB, store the output from the ALU or the multiplier / adder block; the

accumulators can also provide a second input to the ALU or the multiplier / adder. The accumulators are divided

into three parts:

Guard bits (bits 32–39)

A high-order word (bits 16–31)

A low-order word (bits 0–15)

Instructions are provided for storing the guard bits, the high- and the low-order accumulator words in data

memory, and for manipulating 32-bit accumulator words in or out of data memory. Also, any of the accumulators

can be used as temporary storage for the other.

barrel shifter

The ’54x’s barrel shifter has a 40-bit input connected to the accumulator, or data memory

(CB, DB) and a 40-bit output connected to the ALU, or data memory (EB). The barrel shifter produces a left shift

of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift-count

field (ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift-count register.

This shifter and the exponent detector normalize the values in an accumulator in a single cycle. The least

significantbits (LSBs) of the output are filled with 0s and the most significant bits (MSBs) can be either zero-filled

or sign-extended, depending on the state of the sign-extended mode bit (SXM) of ST1. Additional shift

capabilitiesenable the processor to perform numerical scaling, bit extraction, extended arithmetic, and overflow

prevention operations.

multiplier/adder

The multiplier / adder performs 17 × 17-bit 2s-complement multiplication with a 40-bit accumulation in a single

instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed / unsigned

input control, fractional control, a zero detector, a rounder (2s-complement), overflow / saturation logic, and

TREG. The multiplier has two inputs: one input is selected from the TREG, a data-memory operand, or an

accumulator; the other is selected from the program memory, the data memory, an accumulator, or an

immediate value. The fast on-chip multiplier allows the ’54x to perform operations such as convolution,

correlation, and filtering efficiently.

In addition, the multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU

operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and

in implementing symmetrical and least mean square (LMS) filters, which are required for complex DSP

algorithms.

18

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

compare, select and store unit (CSSU)

The compare, select and store unit (CSSU) performs maximum comparisons between the accumulator’s high

and low word, allows the test/control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register

to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory.

The CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware.

program control

Program control is provided by several hardware and software mechanisms:

The program controller decodes instructions, manages the pipeline, stores the status of operations, and

decodes conditional operations. Some of the hardware elements included in the program controller are the

program counter, the status and control register, the stack, and the address-generation logic.

Some of the software mechanisms used for program control include branches, calls, conditional

instructions, a repeat instruction, reset, and interrupts.

power-down modes

There are three power-down modes, activated by the IDLE1, IDLE2, and IDLE3 instructions. In these modes,

the ’54x devices enter a dormant state and dissipate considerably less power than in normal operation. The

IDLE1instructionisusedtoshutdowntheCPU. TheIDLE2instructionisusedtoshutdowntheCPUandon-chip

peripherals. The IDLE3 instruction is used to shut down the ’54x processor completely. This instruction stops

the PLL circuitry as well as the CPU and peripherals.

bus structure

The ’54x device architecture is built around eight major 16-bit buses:

One program-read bus (PB), which carries the instruction code and immediate operands from program

memory

Two data-read buses (CB, DB) and one data-write bus (EB), which interconnect to various elements, such

as the CPU, data-address generation logic, program-address generation logic, on-chip peripherals, and

data memory

–

The CB and DB carry the operands read from data memory.

The EB carries the data to be written to memory.

Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction

execution

The ’54x devices have the capability to generate up to two data-memory addresses per cycle, which are stored

into two auxiliary register arithmetic units (ARAU0 and ARAU1).

The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier for

multiply/accumulate operations or to a destination in data space for the data move instruction. This capability

allows implementation of single-cycle three-operand instructions such as FIRS.

The ’54x devices also have an on-chip bidirectional bus for accessing on-chip peripherals; this bus is connected

to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus can require more than

two cycles for reads and writes depending on the peripheral’s structure.

The ’54x devices can have bus keepers connected to the data bus. Bus keepers ensure that the data bus does

not float. When bus keepers are enabled, the data bus maintains its previous level. Setting bit 1 of the bank

switching control register (BSCR) enables bus keepers and clearing bit 1 disables the bus keepers. A reset

automatically disables the bus keepers.

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bus structure (continued)

The ’548 and ’549 devices also have equivalent bus keepers connected to the address bus. The bus keepers

ensure the address bus does not float when in high-impedance. For the ’548 and ’549 devices, the bus keepers

are always enabled.

Table 2 summarizes the buses used by various types of accesses.

Table 2. Bus Usage for Accesses

PROGRAM

ADDRESS BUS

DATA BUS

DB

BUS

PB

√

ACCESS TYPE

PAB

CAB

DAB

EAB

CB

EB

Program read

√

Program write

√

Data single read

Data dual read

√

Data long (32-bit) read

Data single write

Data read/data write

Dual read/coefficient read

Peripheral read

√(hw)

√(lw)

√(hw)

√(lw)

√

Peripheral write

√

Legend:

hw = high 16-bit word

lw = low 16-bit word

memory

The total memory address range for the host of ’54x devices is 192K 16-bit words. The ’548 and ’549 devices

have 8M-word program memory. The memory space is divided into three specific memory segments: 64K-word

program, 64K-word data, and 64K-word I/O. The program memory space contains the instructions to be

executed as well as tables used in execution. The data memory space stores data used by the instructions. The

I/O memory space interfaces to external memory-mapped peripherals and can also serve as extra data storage

space.

The parallel nature of the architecture of these DSPs allows them to perform four concurrent memory operations

in any given machine cycle: fetching an instruction, reading two operands, and writing an operand. The four

parallel buses are the program-read bus (PB), the data-write bus (EB) and the two data-read buses (CB and

DB). Each bus accesses different memory spaces for different aspects of the DSP’s operation. Additionally, this

architecture allows dual-operand reads, 32-bit-long word accesses, and a single read with a parallel store.

The ’54x DSPs include on-chip memory to aid in system performance and integration.

on-chip ROM

The ’C541 and ’LC541 feature a 28K-word × 16-bit on-chip maskable ROM. 8K words of the ’C541 and ’LC541

ROM can be mapped into program and data memory space if the data ROM (DROM) bit in the processor mode

status (PMST) register is set. This allows an instruction to use data stored in the ROM as an operand.

The ’LC545/’LC546 all feature a 48K-word × 16-bit on-chip maskable ROM. 16K words of the ROM on these

devices can be mapped into program and data memory space if the DROM bit in the PMST register is set.

The ’C542/’LC542/’LC543/ ’LC548 all feature 2K-word × 16-bit on-chip ROM.

The ’LC549 and ’VC549 feature 16K-word x 16-bit on-chip ROM.

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on-chip ROM (continued)

Customers can arrange to have the ROM of the ’54x programmed with contents unique to any particular

application.

on-chip dual-access RAM (DARAM)

The ’541 devices have a 5K-word × 16-bit on-chip DARAM (5 blocks of 1K-word each).

The ’542 and ’543 devices have a 10K-word × 16-bit on-chip DARAM (5 blocks of 2K-word each).

The ’545 and ’546 devices have a 6K-word × 16-bit on-chip DARAM (3 blocks of 2K-word each).

The ’548 and ’549 devices have a 8K-word × 16-bit on-chip DARAM (4 blocks of 2K-word each).

Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store

data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory

space. DARAM can be mapped into program/data memory space by setting the OVLY bit in the PMST register.

on-chip single-access RAM (SARAM)

The ’548 and ’549 devices have a 24K word × 16 bit on-chip SARAM (three blocks of 8K words each).

EachoftheseSARAMblocksisasingle-accessmemory. Thismemoryisintendedprimarilytostoredatavalues;

however, it can be used to store program as well. At reset, the SARAM is mapped into data memory space

(2000h–7FFFh). SARAMcanbemappedintoprogram/datamemoryspacebysettingtheOVLYbitinthePMST

register.

on-chip memory security

The ’54x devices have a maskable option to protect the contents of on-chip memories. When the related bit is

set, no externally originating instruction can access the on-chip memory spaces.

21

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FIXED-POINT DIGITAL SIGNAL PROCESSORS

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memory (continued)

Program

Data

Hex

0000

Memory-Mapped

Registers

Reserved

(OVLY=1)

or

External

(OVLY=0)

Reserved

(OVLY=1)

or

External

(OVLY=0)

005F

0060

Scratch-Pad RAM

007F

0080

007F

0080

007F

0080

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(5K Words)

On-Chip DARAM

(OVLY=1)

or

External

(OVLY=0)

External

(OVLY=0)

13FF

1400

External

13FF

1400

13FF

1400

DFFF

E000

External

8FFF

9000

On-Chip ROM

(DROM=1)

External

or

On-Chip ROM

(28K Words)

External (DROM=0)

FEFF

FF00

FF7F

FF80

FF7F

FF80

Reserved (DROM=1)

or

External (DROM= 0)

Interrupts and

Reserved

(External)

Interrupts and

Reserved

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 1. Memory Map (’541 only)

Program

Data

Hex

0000

Memory-Mapped

Registers

Reserved (OVLY=1)

or

External (OVLY=0)

Reserved (OVLY=1)

or

External (OVLY=0)

005F

0060

Scratch-Pad RAM

007F

0080

007F

0080

007F

0080

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(10K Words)

On-Chip DARAM

(OVLY=1)

or

External (OVLY=0)

27FF

2800

External (OVLY=0)

External

27FF

2800

27FF

2800

EFFF

F000

Reserved

F7FF

F800

External

On-Chip ROM

(2K Words)

FF7F

FF80

FF7F

FF80

Interrupts and

Reserved

(External)

Interrupts and

Reserved

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 2. Memory Map (’542 and ’543 only)

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memory (continued)

Program

Data

Hex

0000

Hex

0000

Hex

0000

Memory-Mapped Registers

Reserved

(OVLY=1)

or

Reserved

(OVLY=1)

or

005F

0060

Scratch-Pad RAM

External (OVLY=0)

007F

0080

007F

0080

007F

0080

On-Chip DARAM

(6K Words)

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(OVLY=1)

or

17FF

1800

External (OVLY=0)

External

17FF

1800

17FF

1800

BFFF

C000

External

3FFF

4000

On-Chip ROM (DROM=1)

or

External

On-Chip ROM

(48K Words)

External (DROM=0)

FEFF

FF00

FF7F

FF80

FF7F

FF80

Reserved (DROM=1)

or

External (DROM= 0)

Interrupts and

Reserved

(External)

Interrupts and

Reserved

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 3. Memory Map (’545 and ’546 only)

23

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memory (continued)

Program

Data

Hex

0000

Memory-Mapped

Registers

Reserved

(OVLY=1)

or

Reserved

(OVLY=1)

or

005F

0060

Scratch-Pad RAM

External (OVLY=0)

007F

0080

007F

0080

007F

0080

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(8K Words)

External (OVLY=0)

1FFF

2000

1FFF

2000

1FFF

2000

On-Chip SARAM

(OVLY=1)

or

On-Chip SARAM

(OVLY=1)

or

On-Chip SARAM

(24K Words)

External (OVLY=0)

7FFF

8000

7FFF

8000

7FFF

8000

External

EFFF

F000

Reserved

External

F7FF

F800

On-Chip ROM

(2K Words)

FF7F

FF80

FF7F

FF80

Interrupts and

Reserved

(External)

Interrupts and

Reserved

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 4. Memory Map (’548 only)

(In the case of a 64K Program Word Address Reach)

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memory (continued)

Program

Hex

Program

Data

Hex

0000

Memory-Mapped

Registers

Reserved

(OVLY=1)

or

Reserved

(OVLY=1)

or

005F

0060

Scratch-Pad RAM

External (OVLY=0)

007F

External (OVLY=0)

007F

0080

007F

0080

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(OVLY=1)

or

On-Chip DARAM

(8K Words)

External (OVLY=0)

1FFF

2000

1FFF

2000

1FFF

2000

On-Chip SARAM

(OVLY=1)

or

(OVLY=1)

or

On-Chip SARAM

(24K Words)

External (OVLY=0)

7FFF

8000

7FFF

8000

7FFF

8000

External

BFFF

C000

BFFF

C000

External

On-Chip ROM (DROM=1)

or

On-Chip ROM

(16K Words)

External (DROM=0)

FEFF

FF00

FEFF

FF00

Reserved (DROM=1)

or

External (DROM= 0)

FF7F

Interrupts and

Reserved

(On-Chip)

FF80

Interrupts and

Reserved

(External)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 5. Memory Map (’549 only)

xx 0000

01 0000

02 0000

7F 0000

Page 0

32K

Page 1

32K

Page 2

32K

Page 127

32K

†

‡

Words

xx 7FFF

01 FFFF

01 8000

02 FFFF

02 8000

7F FFFF

7F 8000

00 8000

00 FFFF

Page 0

Page 1

Page 2

Page 127

32K

Words

32K

Words

32K

Words

32K

Words

01 FFFF

02 FFFF

7F FFFF

XPC = 0

XPC = 1

XPC = 2

XPC = 127

†

‡

See Figure 4 and Figure 5 for more information about this on-chip memory region.

These pages available when OVLY = 0 when on–chip RAM is not mapped in program space or data space. When OVLY = 1 the first 32K words

are all on page 0 when on–chip RAM is mapped in program space or data space.

NOTE A: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 – xx 7FFF, regardless of page number, are

mapped to the on-chip RAM at 00 0000 – 00 7FFF.

Figure 6. Extended Program Memory (’548 and ’549 only)

25

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program memory

The external program memory space on the ’54x devices addresses up to 64K 16-bit words. Software can

configure their memory cells to reside inside or outside of the program address map. When the cells aremapped

into program space, the device automatically accesses them when their addresses are within bounds. When

the program-address generation (PAGEN) logic generates an address outside its bounds, the device

automatically generates an external access. The advantages of operating from on-chip memory are as follows:

Higher performance because no wait states are required

Lower cost than external memory

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

program memory address map

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, and either two 1-word instructions or one 2-word instruction, which allows branching to the

appropriate interrupt service routine without the overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate

128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new

128-word page. For example:

STM

#05800h,PMST

;Remapped vectors to start at 5800h.

This example moves the interrupt vectors to program space at address 05800h. Any subsequent interrupt

(except for a device reset) fetches its interrupt vector from that new location. For example, if, after loading the

IPTR, an INT2 occurs, the interrupt service routine vector is fetched from location 5848h in program space as

opposed to location FFC8h. This feature facilitates moving the desired vectors out of the boot ROM and then

removing the ROM from the memory map. Once the system code is booted into the system from the boot-loader

code resident in ROM, the application reloads the IPTR with a value pointing to the new vectors. In the previous

example, the STM instruction is used to modify the PMST. Note that the STM instruction modifies not only the

IPTR but other status/control bits in the PMST register.

NOTE: The hardware reset (RS) vector cannot be remapped, because the hardware reset loads the IPTR with

1s. Therefore, the reset vector is always fetched at location FF80h in program space. In addition, for the ’54x,

128 words are reserved in the on-chip ROM for device-testing purposes. Application code written to be

implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.

extended program memory (’548 and ’549 only)

The ’548 and ’549 devices use a paged extended memory scheme in program space to allow access of up to

8M of program memory. This extended program memory is organized into 128 pages (0–127), each 64K in

length. To implement the extended program memory scheme, the ’548 and ’549 device includes the following

additional features:

Seven additional address lines (for a total of 23)

An extra memory-mapped register [program counter extension register (XPC)]

26

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extended program memory (’548 and ’549 only) (continued)

Six new instructions for addressing extended program memory space:

–

FB[D] — Far branch

FBACC[D] — Far branch to the location specified by the value in accumulator A or accumulator B

FCALA[D] — Far call to the location specified by the value in accumulator A or accumulator B

FCALL[D] — Far call

FRET[D] — Far return

FRETE[D] — Far return with interrupts enabled

Two ’54x instructions are extended to use the 23 bits in the ’548 and ’549 devices:

–

READA — Read program memory addressed by accumulator A and store in data memory

WRITA — Write data to program memory addressed by accumulator A

For more information on these six new instructions and the two extended instructions, refer to the instruction

set summary table in this data sheet and to the TMS320C54x DSP Reference Set, Volume 2, Mnemonic

Instruction Set, literature number SPRU172. And for more information on extended program memory, refer to

the TMS320C54x DSP Reference Set, Volume 1, CPU and Peripherals, literature number SPRU131.

data memory

The data memory space on the ’54x device addresses contains up to 64K of 16-bit words. The ’devices

automatically access the on-chip RAM when addressing within its bounds. When an address is generated

outside the RAM bounds, the device automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

Higher performance because no wait states are required

Higher performance because of better flow within the pipeline of the CALU

Lower cost than external memory

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

bootloader

A bootloader is available in the standard ’54x on-chip ROM. This bootloader can be used to transfer user code

from an external source to anywhere in the program memory at power up automatically. If MP/MC of the device

is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location

contains a branch instruction to the start of the boot-loader program. The standard ’54x devices provide different

ways to download the code to accommodate various system requirements:

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space 8-bit or 16-bit mode

Serial boot from serial ports 8-bit or 16-bit mode

Host port interface boot (’542, ’545, ’548, and ’549 devices only)

Warm boot

27

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bootloader (continued)

The bootloader provided in the on-chip ROM of the ’548 and ’549 devices implements several enhanced

features. These include the addition of BSP and TDM boot modes. To accommodate these new boot modes,

the encoding of the boot-mode selection word has been modified.

For a detailed description of bootloader functionality, refer to the TMS320C54x DSP Reference Set, Volume 4:

Applications Guide (literature number SPRU173). For a detailed description of the enhanced bootloader

functionality, refer to the TMS320x548/’549 Bootloader Technical Reference.

on-chip peripherals

All the ’54x devices have the same CPU structure; however, they have different on-chip peripherals connected

to their CPUs. The on-chip peripheral options provided are:

Software-programmable wait-state generator

Programmable bank switching

Parallel I/O ports

Serial ports (standard, TDM, and BSP)

A hardware timer

A clock generator [with a multiple phase-locked loop (PLL) on ’549 devices]

software-programmable wait-state generators

Software-programmable wait-state generators can be used to extend external bus cycles up to seven machine

cycles to interface with slower off-chip memory and I/O devices. The software wait-state generators are

incorporated without any external hardware. For off-chip memory access, a number of wait states can be

specified for every 32K-word block of program and data memory space, and for one 64K-word block of I/O

space within the software wait-state (SWWSR) register.

programmable bank-switching

Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank

boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from

program-memory space to data-memory space (’54x) or one program memory page to another program

memory page (’548 and ’549 only). This extra cycle allows memory devices to release the bus before other

devices start driving the bus; thereby avoiding bus contention. The size of memory bank for the bank-switching

is defined by the bank-switching control register (BSCR).

parallel I/O ports

Each ’54x device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the

PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The devices can

interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding

circuits.

host-port interface (’542, ’545, ’548, and ’549 only)

The host-port interface (HPI) is an 8-bit parallel port used to interface a host processor to the DSP device.

Information is exchanged between the DSP device and the host processor through on-chip memory that is

accessible by both the host and the DSP device. The DSP devices have access to the HPI control (HPIC)

register and the host can address the HPI memory through the HPI address register (HPIA). HPI memory is a

2K-word DARAM block that resides at 1000h to 17FFh in data memory and can also be used as

general-purpose on-chip data or program DARAM.

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host-port interface (’542, ’545, ’548, and ’549 only) (continued)

Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether

the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the

HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the DSP

device by writing to HPIC. The DSP device can interrupt the host with a dedicated HINT pin that the host can

acknowledge and clear.

The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the

normal mode of operation, both the DSP device and the host can access HPI memory. In this mode,

asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority

and the DSP device waits one cycle. The HOM capability allows the host to access HPI memory while the DSP

device is in IDLE2 (all internal clocks stopped) or in reset mode. The host can therefore access the HPI RAM

while the DSP device is in its optimal configuration in terms of power consumption.

The HPI control register has two data strobes, HDS1 and HDS2, a read/write strobe HR/W, and an address

strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is interfaced

easily to hosts with multiplexed address/data bus, separate address and data buses, one data strobe and a

read/write strobe, or two separate strobes for read and write.

The HPI supports high-speed back-to-back accesses.

In the SAM, the HPI can handle one byte every five DSP device periods—that is, 64 MBps with a 40-MIPS

DSP, or 160 MBps with a 100-MIPS DSP. The HPI is designed so that the host can take advantage of this

high bandwidth and run at frequencies up to (f n) ÷ 5, where n is the number of host cycles for an external

access and f is the DSP device frequency.

In HOM, the HPI supports high-speed back-to-back host accesses at 1 byte every 50 ns—that is, 160 MBps

with a -40 or faster DSP.

serial ports

The ’54x devices provide high-speed full-duplex serial ports that allow direct interface to other ’54x devices,

codecs, and other devices in a system. There is a standard serial port, a time-division-multiplexed (TDM) serial

port, and a buffered serial port (BSP). The ’549 devices provides a misalignment detection feature to that allows

the device to detect when a word or words are lost in the serial data line.

The general-purpose serial port utilizes two memory-mapped registers for data transfer: the data-transmit

register (DXR) and the data-receive register (DRR). Both of these registers can be accessed in the same

mannerasanyothermemorylocation. Thetransmitandreceivesectionsoftheserialporteachhaveassociated

clocks, frame-synchronization pulses, and serial-shift registers; and serial data can be transferred either in

bytes or in 16-bit words. Serial port receive and transmit operations can generate their own maskable transmit

andreceiveinterrupts(XINTandRINT), allowingserial-porttransferstobemanagedthroughsoftware. The’54x

serial ports are double-buffered and fully static.

The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’54x

devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals

with each subinterval representing a prespecified communications channel. The TDM port serially transmits

16-bit words on a single data line (TDAT) and destination addresses on a single address line (TADD). Each

device can transmit data on a single channel and receive data from one or more of the eight channels, providing

a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once

every 128 clock cycles, corresponding to the transmission of one 16-bit word on each of the eight channels. Like

the general-purpose serial port, the TDM port is double-buffered on both input and output data.

The buffered serial port (BSP) consists of a full-duplex double-buffered serial-port interface and an

auto-buffering unit (ABU). The serial port block of the BSP is an enhanced version of the standard serial port.

The ABU allows the serial port to read/write directly to the ’54x internal memory using a dedicated bus

independent of the CPU. This results in minimal overhead for serial port transactions and faster data rates.

29

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serial ports (continued)

When auto-buffering capability is disabled (standard mode), serial port transfers are performed under software

control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and

WRINT) provided by the serial port are sent to the CPU as transmit interrupt (XINT) and receive interrupt

(RINT). When auto buffering is enabled, word transfers are done directly between the serial port and the ’54x

internal memory using ABU-embedded address generators.

The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory

for the buffers resides in 2K words of the ’54x internal memory. The length and starting addresses of the buffers

are user-programmable. A buffer-empty/buffer-full interrupt can be posted to the CPU. Buffering is easily halted

by an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and receive

sections. When auto buffering is disabled, operation is similar to that of the general-purpose serial port.

The BSP allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a

frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs

when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency-

and polarity-programmable. The BSP is fully static and operates at arbitrarily low clock frequencies. The

maximum operating frequency for ’54x devices up to 50 MIPs is CLKOUT. For higher-speed ’54x devices, the

maximum operating frequency is 50 MBps at 20 ns.

buffer misalignment (BMINT) interrupt (’549 only)

The BMINT interrupt is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is

not at the top of the buffer address. This is useful for detecting several potential error conditions on the serial

interface, including extraneous and missed clocks and frame sync pulses. A BMINT interrupt, therefore,

indicates that one or more words may have been lost on the serial interface.

BMINT is useful for detecting buffer misalignment only when the buffer pointer(s) are initially loaded with the

top of buffer address, and a frame of data contains the same number of words as the buffer length. These are

theonlyconditionsunderwhichaframesyncoccurringatabufferaddress, otherthanthetopofbuffer, constitute

an error condition. In cases where these conditions are met, a frame sync always occurs when the buffer pointer

is at the top of buffer address, if the interface is functioning properly.

If BMINT is enabled under conditions other than those stated above, interrupts may be generated under

circumstances other than actual buffer misalignment. In these cases, BMINT should generally be masked in

the IMR register so that the processor will ignore this interrupt.

BMINT is available when operating auto-buffering mode with continuous transfers, the FIG bit cleared to 0, and

external serial clocks or frames.

TheBSP0andBSP1BMINTbitsintheIMRandIFRregistersarebits12and13, respectively, (bit15istheMSB),

and their interrupt vector locations are 070h and 074h, respectively.

30

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serial ports (continued)

Table 3 provides a comparison of the serial ports available in the ’54x devices.

Table 3. Serial Port Configurations for the ’54x

NO. OF STANDARD

SERIAL PORTS

NO. OF BSPs

(BSP ADDRESS RANGES)

NO. OF TDM

SERIAL PORTS

DEVICE

TMS320C541

2

–

TMS320LC541

TMS320C542

TMS320LC542

–

1

1 (0800h–0FFFh)

1

–

TMS320LC543

TMS320LC545

TMS320LC545A

TMS320LC546

TMS320LC546A

1

–

1 (0800h–0FFFh)

–

1

2 (0800h–0FFFh

and 1800h–1FFFh)

TMS320LC548

TMS320LC549

TMS320VC549

2 (0800h–0FFFh

and 1800h–1FFFh)

hardware timer

The ’54x devices feature a 16-bit timing circuit with a four-bit prescaler. The timer counter is decremented by

one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is generated. The timer

can be stopped, restarted, reset, or disabled by specific status bits.

clock generator

The clock generator provides clocks to the ’54x device, and consists of an internal oscillator and a phase-locked

loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal

resonator with the internal oscillator, or from an external clock source. The reference clock input is then either

divided by two (or by four on the ’545A, ’546A, ’548, and ’549) to generate clocks for the ’54x device, or the PLL

circuit can be used to generate the device clock by multiplying the reference clock frequency by a scale factor,

allowing use of a clock source with a lower frequency than that of the CPU.

The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the

PLLisinitiallystarted, itentersatransitionalmodeduringwhichthePLLacquireslockwiththeinputsignal. Once

the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal

clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’54x device.

Two types of PLL are available: a hardware-programmable PLL and a software-programmable PLL. All ’54x

devices have the hardware-programmable PLL except the ’545A, ’546A, ’548, and ’549, which have the

software-programmable PLL. On the hardware-programmable PLL, an external delay must be provided before

the device is released from reset in order for the PLL to achieve lock. With the software-programmable PLL,

a lock timer is provided to implement this delay automatically. Note that both the hardware- and the

software-programmable PLLs require the device to be reset after power up to begin functioning properly.

hardware-programmable PLL

The ’54x can use either the internal oscillator or an external frequency source for an input clock. The clock

generation mode is determined by the CLKMD1, CLKMD2 and CLKMD3 clock mode pins except on the ’545A,

the ’546A, the ’548, and the ’549 (see software-programmable PLL description below). Table 4 outlines the

selection of the clock mode by these pins. Note that both the hardware- and the software-programmable PLLs

require the device to be reset after power up to begin functioning properly.

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hardware-programmable PLL (continued)

Table 4. Clock Mode Configurations

MODE-SELECT PINS

CLOCK MODE

†

OPTION 2

CLKMD1

CLKMD2

CLKMD3

OPTION 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PLL × 3 with external source

PLL × 2 with external source

PLL × 5 with external source

PLL × 4 with external source

PLL × 3, internal oscillator enabled

PLL × 1.5 with external source

Divide-by-two with external source

PLL × 5, internal oscillator enabled

PLL × 4.5 with external source

Divide-by-two with external source

‡

Stop mode

PLL × 1 with external source

Divide-by-two, internal oscillator enabled

PLL × 1 with external source

Divide-by-two, internal oscillator enabled

†

‡

Option: Option 1 or option 2 is selected when ordering the device.

Stopmode:Thefunctionofthestopmodeisequivalenttothatofthepower-downmodeofIDLE3;however, theIDLE3instructionisrecommended

rather than stop mode to realize full power saving, since IDLE3 stops clocks synchronously and can be exited with an interrupt.

software-programmable PLL (’545A, ’546A, ’548, and ’549)

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved.

Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. The

CLKMD register fields are shown in Figure 7 and described below. Note that upon reset, the CLKMD register

is initialized with a predetermined value dependent only upon the state of the CLKMD1 – CLKMD3 pins (see

Table 6).

Bit #

15–12

11

10–3

2

1

0

PLLSTATUS

R

PLLMUL

PLLDIV

PLLCOUNT

PLLON/OFF

PLLNDIV

R/W

†

R/W

†

R/W

R = read, W = write

R/W

†

When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are

indeterminate.

Figure 7. Clock Mode Control Register (CLKMD)

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software-programmable PLL (’545A, ’546A, ’548, and ’549) (continued)

Bits 15–12 PLLMUL. PLL multiplier. Defines the frequency multiplier in conjunction with PLLDIV and

PLLNDIV, as shown in Table 5.

Bit 11

PLLDIV. PLL divider. Defines the frequency multiplier in conjunction with PLLMUL and PLLNDIV,

as shown in Table 5.

0 = an integer multiply factor is used.

1 = a non-integer multiply factor is used.

Bits 10–3 PLLCOUNT. PLL counter value. Specifies the number of input clock cycles (in increments of

16 cycles) for the PLL lock timer to count before the PLL begins clocking the processor after the

PLL is started. The PLL counter is a down-counter, which is driven by the input clock divided

by 16; therefore, for every 16 input clocks, the PLL counter decrements by one.

The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked,

so that only valid clock signals are sent to the device.

Bit 2

PLLON/OFF. PLL on/off. Enables or disables the PLL part of the clock generator in conjunction

with the PLLNDIV bit. Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when

PLLON/OFF is high, the PLL runs independently of the state of PLLNDIV.

PLLON/OFF

PLLNDIV

PLL STATE

0

1

0

1

0

1

Off

On

Bit 1

Bit 0

PLLNDIV. PLL clock generator select. Determines whether the clock generator works in PLL

mode or in divider (DIV) mode, thereby defining the frequency multiplier in conjunction with

PLLMUL and PLLDIV.

0 = Divider mode is used

1 = PLL mode is used

PLLSTATUS. PLL status. Indicates the mode in which the clock generator is operating.

0 = DIV mode

1 = PLL mode

Table 5. PLL Multiplier Ratio as a Function of PLLNDIV, PLLDIV, and PLLMUL

†

PLLNDIV

PLLDIV

PLLMUL

0–14

15

MULTIPLIER

0

x

0

1

0.5

0

0.25

1

0–14

15

PLLMUL + 1

1

0 or even

odd

(PLLMUL + 1)

2

1

PLLMUL

4

†

CLKOUT = CLKIN x multiplier

33

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software-programmable PLL (’545A, ’546A, ’548, and ’549) (continued)

Immediately following reset, the clock mode is determined by the values of the three external pins: CLKMD1,

CLKMD2, and CLKMD3. The modes corresponding to the CLKMD pins are shown in Table 6.

Table 6. Clock Mode Settings at Reset

CLKMD REGISTER

CLKMD1

CLKMD2

CLKMD3

CLOCK MODE

RESET VALUE

0000h

1000h

2000h

4000h

6000h

7000h

0007h

—

0

1

0

1

0

1

0

1

0

1

0

1

Divide-by-two, with external source

Divide-by-two, internal oscillator enabled

Divide-by-two, with external source

†

Divide-by-two, internal oscillator enabled

PLL × 1 with external source

Stop mode

†

Reserved mode (’549 only). Do not use in normal operation.

Following reset, the software-programmable PLL can be programmed to any configuration desired, as

described above. Note that when the PLL × 1 with external source option (CLKMD[1–3]=101) is selected during

reset, the internal PLL lock-count timer is not active; therefore, the system must delay releasing reset in order

to allow for the PLL lock-time delay. Also, note that both the hardware- and the software-programmable PLLs

require the device to be reset after power up to begin functioning properly.

programming considerations when using the software-programmable PLL

The software-programmable PLL offers many different options in startup configurations, operating modes, and

power-saving features. Programming considerations and several software examples are presented here to

illustrate the proper use of the software-programmable PLL at start-up, when switching between different

clocking modes, and before and after IDLE1/IDLE2/IDLE3 instruction execution.

use of the PLLCOUNT programmable lock timer

During the lockup period, the PLL should not be used to clock the ’54x. The PLLCOUNT programmable lock

timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is

achieved.

The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from

its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided

by 16. The resulting lockup delay can therefore be set from 0 to 255

16 CLKIN cycles.

The lock timer is activated when the clock generator operating mode is switched from DIV to PLL (see the

section describing switching from DIV mode to PLL mode). During the lockup period, the clock generator

continues to operate in DIV mode; after the PLL lock timer has decremented to zero, the PLL begins clocking

the ’54x.

Accordingly, the value loaded into PLLCOUNT is chosen based on the following relationship:

PLLCOUNT > Lockup Time / (16

t

)

CLKIN

where t

Figure 8.

is the input reference clock period and lockup time is the required PLL lockup time as shown in

CLKIN

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use of the PLLCOUNT programmable lock timer (continued)

60

55

50

45

40

35

30

25

20

15

10

5

59

44

35

’549 Only

29

23

22

24

17

16

19

0

2.5

10

20

30

40

50

60

70

80

100

CLKOUT Frequency (MHz)

Figure 8. PLL Lockup Time Versus CLKOUT Frequency

switching from DIV mode to PLL mode

Several circumstances may require switching from DIV mode to PLL mode; however, note that if the PLL is not

locked when switching from DIV mode to PLL mode, the PLL lockup time delay must be observed before the

mode switch occurs to ensure that only proper clock signals are sent to the device. It is, therefore, important

to know whether or not the PLL is locked when switching operating modes.

The PLL is unlocked on power-up, after changing the PLLMUL or PLLDIV values, after turning off the PLL

(PLLON/OFF = 0), or after loss of input reference clock. Once locked, the PLL remains locked even in DIV mode

as long as the PLL had been previously locked and has not been turned off (PLLON/OFF stays 1), and the

PLLMUL and PLLDIV values have not been changed since the PLL was locked.

Switching from DIV mode to PLL mode (setting PLLNDIV to 1) activates the PLLCOUNT programmable lock

timer (when PLLCOUNT is preloaded with a non-zero value), and this can be used to provide a convenient

method for implementing the lockup time delay. The PLLCOUNT lock timer feature should be used in the

situations described above, where the PLL is unlocked unless a reset delay is used to implement the lockup

delay, or the PLL is not used.

SwitchingfromDIVmodetoPLLmodeisaccomplishedbyloadingtheCLKMDregister. Thefollowingprocedure

describes switching from DIV mode to PLL mode when the PLL is not locked. When performing this mode switch

with the PLL already locked, the effect is the same as when switching from PLL to DIV mode, but in the reverse

order. In this case, the delays of when the new clock mode takes effect are the same.

When switching from DIV to PLL mode with the PLL unlocked, or when the mode change will result in unlocked

operation, the PLLMUL[3–0], PLLDIV, and PLLNDIV bits are set to select the desired frequency multiplier as

described in Table 5, and the PLLCOUNT[7–0] bits are set to select the required lockup time delay. Note that

PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF can only be modified when in DIV mode.

35

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switching from DIV mode to PLL mode (continued)

Once the PLLNDIV bit is set, the PLLCOUNT timer begins being decremented from its preset value. When the

PLLCOUNT timer reaches zero, the switch to PLL mode takes effect after six CLKIN cycles plus 3.5 PLL cycles

(CLKOUT frequency). When the switch to PLL mode is completed, the PLLSTATUS bit in the CLKMD register

is read as 1. Note that during the PLL lockup period, the ’54x continues operating in DIV mode.

The following software example shows an instruction that can be used to switch from DIV mode to PLL

with a CLKIN frequency of 13 MHz and PLLCOUNT = 41 (decimal).

3,

STM

#0010000101001111b, CLKMD

switching clock mode from PLL to DIV

When switching from PLL mode to DIV mode, the PLLCOUNT delay does not occur, and the switch between

the two modes takes place after a short transition delay.

The switch from PLL mode to DIV mode is also accomplished by loading the CLKMD register. The PLLNDIV

bit is set to 0, selecting DIV mode, and the PLLMUL bits are set to select the desired frequency multiplier as

shown in Table 5.

The switch to DIV mode takes effect in 6 CLKIN cycles plus 3.5 PLL cycles (CLKOUT frequency) for all PLLMUL

values except 1111b. With a PLLMUL value of 1111b, the switch to DIV mode takes effect in 12 CLKIN cycles

plus 3.5 PLL cycles (CLKOUT frequency). When the switch to DIV mode is completed, the PLLSTATUS bit in

the CLKMD register is read as 0.

The following software example shows a code sequence that can be used to switch from PLL × 3 to

divide-by-two mode. Note that the PLLSTATUS bit is polled to determine when the switch to DIV mode has taken

effect, and then the STM instruction is used to turn off the PLL at this point.

STM

LDM

AND

BC

#0b, CLKMD

CLKMD, A

#01b, A

TstStatu, ANEQ

#0b, CLKMD

;switch to DIV mode

;poll STATUS bit

TstStatu:

STM

;reset PLLON_OFF when STATUS

;is DIV mode

switching mode from one PLL multiplier to another

When switching from one PLL multiplier ratio to another is required, the clock generator must be switched from

PLL mode to DIV mode before selecting the new multiplier ratio; switching directly from one PLL multiplier ratio

to another is not supported.

In order to switch from one PLL multiplier ratio to another, the following steps must be followed:

1. Set the PLLNDIV bit to 0, selecting DIV mode.

2. Pollthe PLLSTATUS bit until a 0 is obtained, indicating that DIV mode is enabled and that PLLMUL, PLLDIV,

and PLLCOUNT can be updated.

3. Modify the CLKMD register to set the PLLMUL[3–0], PLLDIV, and PLLNDIV bits to the desired frequency

multiplier as defined in Table 5, and the PLLCOUNT[7–0] bits to the required lock-up time.

When the PLLNDIV bit is set to one in step three, the PLLCOUNT timer begins decrementing from its preset

value. Once the PLLCOUNT timer reaches zero, the new PLL mode takes effect after six CLKIN cycles plus

3.5 PLL cycles (CLKOUT frequency).

36

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switching mode from one PLL multiplier to another (continued)

Also, note that a direct switch between divide-by-two mode and divide-by-four mode is not possible. To switch

between these two modes, the clock generator must first be set to PLL mode with an integer-only

(non-fractional) multiplier ratio, and then set back to DIV mode in the desired divider configuration (see previous

sections for details on switching between DIV and PLL modes).

The following software example shows a code sequence that can be used to switch clock mode from PLL × X

to PLL × 1.

STM

LDM

AND

BC

#0b, CLKMD

CLKMD, A

#01b, A

TstStatu, ANEQ

#0000001111101111b, CLKMD

;switch to DIV mode

;poll STATUS bit

TstStatu:

STM

;switch to PLL

1 mode

programmable clock generator operation immediately following reset

Immediately following reset, the operating mode of the clock generator is determined only on the basis of the

CLKMD1/2/3 pin state as described in Table 6. All but two of these operating modes are ’divide-by-two with

external source’. Switching from divide-by-two to a PLL mode can easily be accomplished by changing the

CLKMD register contents. Note that if use of the internal oscillator is desired, either the 100 or the 111 state of

the CLKMD1–CLKMD3 pins must be selected at reset (as shown in Table 6) since the internal oscillator cannot

be programmed through software.

The following software example shows an instruction that can be used to switch from divide-by-two mode to

the PLL

3 mode.

STM

#0010000101001111b, CLKMD

considerations when using IDLE1/IDLE2/IDLE3

When using one of the IDLE instructions to reduce power requirements, proper management of the PLL is

important. The clock generator consumes the least power when operating in DIV mode with the PLL disabled.

Therefore, if power dissipation is a significant consideration, it is desirable to switch from PLL to DIV mode, and

disable the PLL, before executing the IDLE1/IDLE2/IDLE3 instructions. This is accomplished as explained

above in the section describing switching clock mode from PLL to DIV. After waking up from

IDLE1/IDLE2/IDLE3, the clock generator can be reprogrammed to PLL mode as explained above in the section

describing switching clock mode from DIV to PLL.

Note that when the PLL is stopped during an IDLE state, and the ’54x device is restarted and the clock generator

is switched back to PLL mode, the PLL lockup delay occurs in the same manner as in a normal device startup.

Therefore, in this case, the lockup delay must also be accounted for, either externally or by using the PLL lockup

counter timer.

The following software example illustrates a code sequence that switches the clock generator from PLL

3

mode to divide-by-two mode, turns off the PLL, and enters IDLE3. After waking up from IDLE3, the clock

generator is switched back from DIV mode to PLL 3 mode using a single STM instruction, with a PLLCOUNT

of 64 (decimal) used for the lock timer value.

37

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considerations when using IDLE1/IDLE2/IDLE3 (continued)

STM

LDM

AND

BC

#0b, CLKMD

CLKMD, A

#01b, A

TstStatu, ANEQ

#0b, CLKMD

;switch to DIV mode

;poll STATUS bit

TstStatu:

STM

;reset PLLON_OFF when STATUS

;is DIV mode

IDLE3

(After IDLE3 wake-up – switch the PLL from DIV mode to PLL

3 mode)

STM

#0010001000000111b, CLKMD

;PLLCOUNT = 64 (decimal)

PLL considerations when using the bootloader

The ROM on the ’545A and ’546A contains a bootloader program that can be used to load programs into RAM

for execution following reset. When using this bootloader with the software-programmable PLL, several

considerations are important for proper system operation.

On the ’545A and ’546A, for compatibility, the bootloader configures the PLL to the same mode as would have

resulted if the same CLKMD1–3 input bits had been provided to the option-1 or option-2

hardware-programmable PLL (see Table 4), according to whether the ’545A or ’546A is an option-1 or option-2

device. Once the bootloader program has finished executing, and control is transferred to the user’s program,

the PLL can be reprogrammed to any desired configuration.

38

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memory-mapped registers

Most ’54x devices have 26 (except ’548 and ’549 have 27) memory-mapped CPU registers, which are mapped

into data memory located at addresses 0h to 1Fh. Each of these devices also has a set of memory-mapped

registers associated with peripherals. Table 7 gives a list of CPU memory-mapped registers (MMR) common

to all ’54x devices. Table 8 shows additional peripheral MMRs associated with the ’541 devices, Table 9 shows

those associated with the ’545/’546 devices, Table 10 shows those associated with the ’542/’543 devices, and

Table 11 shows those associated with the ’548/’549 devices.

Table 7. Core Processor Memory-Mapped Registers

ADDRESS

NAME

DESCRIPTION

Interrupt mask register

DEC

0

HEX

0

IMR

IFR

–

1

Interrupt flag register

2–5

6

2–5

6

Reserved for testing

ST0

ST1

AL

Status register 0

7

Status register 1

8

Accumulator A low word (15–0)

Accumulator A high word (31–16)

Accumulator A guard bits (39–32)

Accumulator B low word (15–0)

Accumulator B high word (31–16)

Accumulator B guard bits (39–32)

Temporary register

AH

9

AG

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

BL

B

BH

C

BG

D

TREG

TRN

AR0

AR1

AR2

AR3

AR4

AR5

AR6

AR7

SP

E

F

Transition register

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Auxiliary register 0

Auxiliary register 1

Auxiliary register 2

Auxiliary register 3

Auxiliary register 4

Auxiliary register 5

Auxiliary register 6

Auxiliary register 7

Stack pointer register

BK

Circular buffer size register

Block-repeat counter

BRC

RSA

REA

PMST

XPC

–

Block-repeat start address

Block-repeat end address

Processor mode status (PMST) register

Extended program counter (’548 and ’549 only)

Reserved

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memory-mapped registers (continued)

Table 8. Peripheral Memory-Mapped Registers (’541 Only)

ADDRESS

NAME

DRR0

DESCRIPTION

DEC

32

HEX

20

21

22

23

24

25

26

27

28

29

Serial port 0 data-receive register

Serial port 0 data-transmit register

Serial port 0 control register

Reserved

DXR0

SPC0

—

33

34

35

TIM

36

Timer register

PRD

TCR

—

37

Timer period register

Timer control register

Reserved

38

39

SWWSR

BSCR

—

40

S/W wait-state register

Bank-switching control register

Reserved

41

42–47

48

2A–2F

30

DRR1

DXR1

SPC1

—

Serial port 1 data-receive register

Serial port 1 data-transmit register

Serial port 1 control register

Reserved

49

31

50

32

51

33

—

52–95

34–5F

Reserved

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memory-mapped registers (continued)

†

Table 9. Peripheral Memory-Mapped Registers (’545 and ’546 Only)

ADDRESS

NAME

BDRR

DESCRIPTION

DEC

32

33

34

35

36

37

38

39

40

41

HEX

20

BSP data-receive register

BSP data-transmit register

BSP serial-port control register

BSP control extension register

Timer register

BDXR

BSPC

BSPCE

TIM

21

22

23

24

PRD

TCR

—

25

Timer period counter

26

Timer control register

27

Reserved

SWWSR

BSCR

—

28

External bus S/W wait-state register

External bus bank-switching control register

Reserved

29

42 – 43

44

2A – 2B

2C

‡

HPIC

—

HPI control register

45 – 47

48

2D – 2F

30

Reserved

DRR

DXR

SPC

—

Data-receive register

49

31

Data-transmit register

50

32

Serial-port control register

Reserved

51 – 55

56

33 – 37

38

AXR

BKX

ARR

BKR

BSP ABU transmit-address register

BSP ABU transmit-buffer-size register

BSP ABU receive-address register

BSP ABU receive-buffer-size register

57

39

58

3A

59

3B

†

BSP = Buffered serial port

ABU = Auto-buffering unit

Host port interface (HPI) on ’LC545 only

‡

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memory-mapped registers (continued)

†

Table 10. Peripheral Memory-Mapped Registers (’542 and ’543 Only)

ADDRESS

NAME

BDRR

DESCRIPTION

BSP data-receive register

DEC

32

33

34

35

36

37

38

39

40

41

HEX

20

BDXR

BSPC

BSPCE

TIM

21

BSP data-transmit register

BSP serial-port control register

BSP control extension register

Timer register

22

23

24

PRD

TCR

25

Timer period counter

26

Timer control register

—

27

Reserved

SWWSR

BSCR

—

28

External bus S/W wait-state register

29

External bus bank-switching control register

Reserved

42 – 43

44

2A – 2B

2C

‡

HPIC

—

HPI control register

45 – 47

48

2D – 2F

30

Reserved

TRCV

TDXR

TSPC

TCSR

TRTA

TRAD

—

TDM data-receive register

49

31

TDM data-transmit register

50

32

TDM serial-port control register

TDM channel-select register

TDM receive/transmit register

TDM receive address register

Reserved

51

33

52

34

53

35

54 – 55

56

36 – 37

38

AXR

BSP ABU transmit-address register

BSP ABU transmit-buffer-size register

BSP ABU receive-address register

BSP ABU receive-buffer-size register

BKX

57

39

ARR

BKR

58

3A

59

3B

†

‡

BSP = Buffered serial port

TDM = Time-division multiplexed

ABU = Auto-buffering unit

Host port interface (HPI) on ’542 only

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memory-mapped registers (continued)

†

Table 11. Peripheral Memory-Mapped Registers (’548 and ’549 Only)

ADDRESS

NAME

BDRR0

DESCRIPTION

DEC

32

33

34

35

36

37

38

39

40

41

42

43

44

HEX

20

BSP 0 data-receive register

BSP 0 data-transmit register

BSP 0 control register

BDXR0

BSPC0

BSPCE0

TIM

21

22

23

BSP 0 control extension register

Timer count register

24

PRD

25

Timer period register

TCR

26

Timer control register

—

27

Reserved

SWWSR

BSCR

—

28

External interface software wait-state register

External interface bank-switching control register

Reserved

29

2A

—

2B

Reserved

HPIC

—

2C

2D–2F

30

HPI control register

45–47

48

Reserved

TRCV

TDXR

TSPC

TCSR

TRTA

TRAD

—

TDM port data-receive register

TDM port data-transmit register

TDM serial port control register

TDM channel-select register

TDM receive/transmit register

TDM receive/address register

Reserved

49

31

50

32

51

33

52

34

53

35

54–55

56

36–37

38

AXR0

BKX0

ARR0

BKR0

AXR1

BKX1

ARR1

BKR1

BDRR1

BDXR1

BSPC1

BSPCE1

—

ABU 0 transmit-address register

ABU 0 transmit-buffer-size register

ABU 0 receive-address register

ABU 0 receive-buffer-size register

ABU 1 transmit-address register

ABU 1 transmit-buffer-size register

ABU 1 receive-address register

ABU 1 receive-buffer-size register

BSP 1 data-receive register

BSP 1 data-transmit register

BSP 1 control register

57

39

58

3A

59

3B

60

3C

3D

3E

61

62

63

3F

64

40

65

41

66

42

67

43

BSP 1 control extension register

Reserved

68–87

88

44–57

58

CLKMD

—

Clock mode register

89–95

59–5F

Reserved

†

BSP = Buffered serial port

ABU = Auto-buffering unit

HPI = Host-port interface

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status registers (ST0, ST1)

The status registers, ST0 and ST1, contain the status of the various conditions and modes for the ’54x devices.

ST0 contains the flags (OV, C, and TC) produced by arithmetic operations and bit manipulations in addition to

the data page pointer (DP) and the auxiliary register pointer (ARP) fields. ST1 contains the various modes and

instructions that the processor operates on and executes.

accumulators (AL, AH, AG, and BL, BH, BG)

The ’54x devices have two 40-bit accumulators: accumulator A and accumulator B. Each accumulator is

memory-mapped and partitioned into accumulator low-word (AL, BL), accumulator high-word (AH, BH), and

accumulator guard bits (AG, BG).

39

AG (BG)

32 31

16 15

0

AH (BH)

AL (BL)

auxiliary registers (AR0–AR7)

The eight 16-bit auxiliary registers (AR0–AR7) can be accessed by the CALU and modified by the auxiliary

register arithmetic units (ARAUs). The primary function of the auxiliary registers is generating 16-bit addresses

for data space. However, these registers also can act as general-purpose registers or counters.

temporary register (TREG)

The TREG is used to hold one of the multiplicands for multiply and multiply/accumulate instructions. It can hold

a dynamic (execution-time programmable) shift count for instructions with shift operation such as ADD, LD, and

SUB instructions. It also can hold a dynamic bit address for the BITT instruction. The EXP instruction stores the

exponent value computed into the TREG, while the NORM instruction uses the TREG value to normalize the

number. For ACS operation of Viterbi decoding, TREG holds branch metrics used by the DADST and DSADT

instructions.

transition register (TRN)

The TRN is a 16-bit register that is used to hold the transition decision for the path to new metrics to perform

the Viterbi algorithm. The CMPS (compare, select, max, and store) instruction updates the contents of the TRN

based on the comparison between the accumulator high word and the accumulator low word.

stack-pointer register (SP)

The SP is a 16-bit register that contains the address at the top of the system. The SP always points to the last

element pushed onto the stack. The stack is manipulated by interrupts, traps, calls, returns, and the PUSHD,

PSHM, POPD, and POPM instructions. Pushes and pops of the stack predecrement and postincrement,

respectively, all 16 bits of the SP.

circular-buffer-size register (BK)

The 16-bit BK is used by the ARAUs in circular addressing to specify the data block size.

block repeat registers (BRC, RSA, REA)

The block-repeat counter (BRC) is a 16-bit register used to specify the number of times a block of code is to

be repeated when performing a block repeat. The block-repeat start address (RSA) is a 16-bit register

containing the starting address of the block of program memory to be repeated when operating in the repeat

mode. The 16-bit block repeat-end address (REA) contains the ending address if the block of program memory

is to be repeated when operating in the repeat mode.

interrupt registers (IMR, IFR)

The interrupt-mask register (IMR) is used to mask off specific interrupts individually at required times. The

interrupt-flag register (IFR) indicates the current status of the interrupts.

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processor-mode status register (PMST)

The processor-mode status register (PMST) controls memory configurations of the ’54x devices.

interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 12.

Table 12. ’54x Interrupt Locations and Priorities

LOCATION

NAME

PRIORITY

FUNCTION

DECIMAL

0

HEX

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

RS, SINTR

NMI, SINT16

SINT17

1

2

Reset (Hardware and software reset)

Nonmaskable interrupt

Software interrupt #17

Software interrupt #18

Software interrupt #19

Software interrupt #20

Software interrupt #21

Software interrupt #22

Software interrupt #23

Software interrupt #24

Software interrupt #25

Software interrupt #26

Software interrupt #27

Software interrupt #28

Software interrupt #29

Software interrupt #30

External user interrupt #0

External user interrupt #1

External user interrupt #2

External timer interrupt

4

8

–

SINT18

12

–

SINT19

16

–

SINT20

20

–

SINT21

24

–

SINT22

28

–

SINT23

32

–

SINT24

36

–

SINT25

40

–

SINT26

44

–

SINT27

48

–

SINT28

52

–

SINT29

56

–

SINT30

60

–

INT0, SINT0

INT1, SINT1

INT2, SINT2

TINT, SINT3

64

3

68

4

72

5

76

6

†

BSP #0 receive interrupt

BRINT0, SINT4

BXINT0, SINT5

TRINT, SINT6

TRINT, SINT7

INT3, SINT8

80

7

†

BSP #0 transmit interrupt

84

8

‡

TDM receive interrupt

88

9

‡

TDM transmit interrupt

92

10

11

12

13

14

15

16

–

96

External user interrupt #3

§

HINT, SINT9

100

104

108

112

116

120–127

64

68

6C

HPI interrupt (’542, ’545, ’548, ’549 only)

BSP #1 receive interrupt (’548, ’549 only)

BSP #1 transmit interrupt (’548, ’549 only)

BSP #0 misalignment detection interrupt (’549 only)

BSP #1 misalignment detection interrupt (’549 only)

Reserved

§

BRINT1, SINT10

BXINT1, SINT11

BMINT0, SINT12

BMINT1, SINT13

—

§

70

74

§

78–7F

†

‡

§

On ’541 devices, these interrupt locations are serial port 0 interrupts (RINT0/XINT0).

On ’541, ’545, and ’546 devices, these interrupt locations are serial port 1 interrupts (RINT1/XINT1).

On ’541, ’543, and ’546 devices, interrupt locations 64h – 7Fh are reserved. On ’542 and ’545 devices, interrupt locations 68h – 7Fh are reserved.

On ’548 devices, interrupt locations 70h – 7Fh are reserved.

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interrupts (continued)

The IFR and IMR registers are laid out as shown in Figure 9.

15–14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RESERVED

BMINT1

BMINT0

BXINT1

BRINT1

HINT

INT3

TXNT

TRNT

BXINT0

TRINT0

TINT

INT2

INT1

INT0

Figure 9. IFR and IMR Registers

instruction set summary

This section summarizes the syntax used by the mnemonic assembler and the associated instruction set

opcodes for the ’54x DSP devices (see Table 13). For detailed information on instruction operation, see the

TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set (literature number SPRU172); and for

detailed information on the algebraic assembler, see the TMS320C54x DSP Reference Set, Volume 3:

Algebraic Instruction Set (literature number SPRU179).

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instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes

OPCODE

WORDS/

CYCLES

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

ARITHMETIC INSTRUCTIONS

ABDST Xmem, Ymem

ABS src [, dst ]

Absolute distance

Absolute value of ACC

1/1

1110

1111

0000

0011

01SD

000S

010S

11SD

XXXX YYYY

1000

IAAA

0101

AAAA

ADD Smem, src

Add operand to ACC

ADD Smem, TS, src

ADD Smem, 16, src [, dst ]

Add (shifted by TREG[5:0]) operand to ACC

Add (shifted by 16 bits) operand to ACC

0110

0000

1111

11SD

IAAA

000S

AAAA

HIFT

ADD Smem [, SHIFT], src [, dst ]

Add shifted operand to ACC (2-word opcode)

2/2

ADD Xmem, SHFT, src

ADD Xmem, Ymem, dst

ADD #lk [, SHFT], src [, dst ]

ADD #lk, 16, src [, dst ]

ADD src [, SHIFT], [, dst ]

ADD src, ASM [, dst ]

ADDC Smem, src

Add shifted operand to ACC

1/1

2/2

1/1

2/2

1/1

2/3

1/1

2/2

1/1

2/3

1/1

1001

1010

1111

0000

0110

0000

000S

XXXX SHFT

Add dual operands, shift result by 16

Add shifted long-immediate value to ACC

Add (shifted by 16 bits) long-immediate to ACC

Add ACC(s) (A/B), then shift result

000D XXXX YYYY

00SD

01SD

011S

1011

0000

0110

000S

1000

IAAA

1000

SHFT

0000

HIFT

Add ACC(s) (A/B), then shift result by ASM value

Add to accumulator with carry

0000

AAAA

1110

ADDM #lk, Smem

Add long-immediate value to memory

Add to ACC with sign-extension suppressed

Double/dual add to accumulator

ADDS Smem, src

001S

DADD Lmem, src [, dst ]

DADST Lmem, dst

0101 00SD

Double/dual add/subtract of T, long operand

Memory delay

0101

0100

0101

1111

1110

101D

1101

100S

111D

010S

110D

010S

0000

0001

DELAY Smem

DRSUB Lmem, src

Double/dual 16-bit subtract from long word

Double/dual, subtract/add of T, long operand

Double-precision/dual 16-bit subtract from ACC

Double/dual, subtract/subtract of T, long operand

Accumulator exponent

DSADT Lmem, dst

DSUB Lmem, src

DSUBT Lmem, dst

EXP src

FIRS Xmem, Ymem, pmad

LMS Xmem, Ymem

MAC[R] Smem, src

Symmetrical finite impulse response filter

Least mean square

XXXX YYYY

Multiply by TREG, add to ACC, round if specified

Multiply dual, add to ACC, round if specified

Multiply TREG by long-immediate, add to ACC

Multiply by long-immediate value, add to ACC

Multiply by ACCA, add to ACCB [round]

Multiply TREG by ACCA, add to ACC [round]

Multiply by program memory, accumulate/delay

Multiply by program memory, then accumulate

Multiply signed by unsigned, then accumulate

Multiply by T, subtract from ACC [round]

0010 10RS

IAAA

AAAA

MAC[R] Xmem, Ymem, src [, dst ]

MAC #lk, src [, dst ]

MAC Smem, #lk, src [, dst ]

MACA[R] Smem [, B ]

MACA[R] T, src [, dst ]

MACD Smem, pmad, src

MACP Smem, pmad, src

MACSU Xmem, Ymem, src

MAS[R] Smem, src

1011 0RSD XXXX YYYY

1111

0110

0011

1111

0111

1010

0010

00SD

01SD

01R1

01SD

101S

100S

011S

11RS

0110

IAAA

1000

IAAA

0111

AAAA

100R

AAAA

XXXX YYYY

IAAA AAAA

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

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instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes (Continued)

WORDS/

CYCLES

OPCODE

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

ARITHMETIC INSTRUCTIONS (CONTINUED)

Multiply dual, subtract from ACC [round]

Multiply operand by ACCA, subtract from ACCB

Multiply ACCA by T, subtract from ACC [round]

Accumulator maximum

MAS[R] Xmem, Ymem, src [, dst ]

MASA Smem [, B ]

MASA[R] T, src [, dst ]

MAX dst

1/1

2/2

1/1

1011 1RSD XXXX YYYY

0011

1111

0011

01SD

010D

IAAA

1000

IAAA

AAAA

101R

0110

MIN dst

Accumulator minimum

0111

MPY[R] Smem, dst

MPY Xmem, Ymem, dst

MPY Smem, #lk, dst

MPY #lk, dst

Multiply TREG by operand, round if specified

Multiply dual data-memory operands

Multiply operand by long-immediate operand

Multiply TREG value by long-immediate operand

Multiply single data-memory operand by ACCA

Multiply TREG value by ACCA

Multiply unsigned

0010 00RD

AAAA

1010

0110

1111

0011

1111

0010

1111

0011

1111

1110

0010

1111

0011

0000

010D XXXX YYYY

001D

000D

0001

010D

01SD

0110

01SD

010S

0010

011D

010D

100S

101S

100S

110S

IAAA

0110

IAAA

1000

IAAA

1000

IAAA

1001

1000

AAAA

0110

AAAA

1100

AAAA

0100

1111

MPYA Smem

MPYA dst

MPYU Smem, dst

NEG src [, dst ]

Negate accumulator

NORM src [, dst ]

POLY Smem

Normalize

Evaluate polynomial

AAAA

1111

RND src [, dst ]

Round accumulator

SAT src

Saturate accumulator

0011

SQDST Xmem, Ymem

SQUR Smem, dst

SQUR A, dst

Square distance

XXXX YYYY

Square single data-memory operand

Square ACCA high

IAAA

1000

IAAA

AAAA

1101

SQURA Smem, src

SQURS Smem, src

SUB Smem, src

SUB Smem, TS, src

SUB Smem, 16, src [, dst ]

Square and accumulate

AAAA

Square and subtract

Subtract operand from accumulator

Shift by TREG[5:0], then subtract from ACC

Shift operand 16 bits, then subtract from ACC

0100 00SD

Shift operand, then subtract from ACC

(2-word opcode)

0110

0000

1111

11SD

IAAA

001S

AAAA

HIFT

SUB Smem [, SHIFT ], src [, dst ]

2/2

SUB Xmem, SHFT, src

SUB Xmem, Ymem, dst

SUB #lk [, SHFT ], src [, dst ]

SUB #lk, 16, src [, dst ]

SUB src [, SHIFT ], [, dst ]

SUB src, ASM [, dst ]

SUBB Smem, src

Shift operand, then subtract from ACC

Shift dual operands by 16, then subtract

Shift long-immediate, then subtract from ACC

Shift long-immediate 16 bits, subtract from ACC

Subtract shifted ACC from ACC

1/1

2/2

1/1

1001

1010

1111

0000

0001

0000

001S

XXXX SHFT

001D XXXX YYYY

00SD

01SD

111D

111S

101S

0001

0110

001S

1000

IAAA

SHFT

0001

HIFT

Subtract ACC shifted by ASM from ACC

Subtract from accumulator with borrow

Subtract conditionally

0001

AAAA

SUBC Smem, src

SUBS Smem, src

Subtract from ACC, sign-extension suppressed

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

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instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes (Continued)

WORDS/

CYCLES

OPCODE

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

CONTROL INSTRUCTIONS

Branch unconditionally with optional delay

Branch to address in ACC, optional delay

Branch on AR(ARP) not zero, optional delay

Branch conditionally, optional delay

Call subroutine at address in ACC, optional delay

Call unconditionally, optional delay

Call conditionally, optional delay

Far branch unconditionally (optional delay)

Far branch to address in ACC, optional delay

Far call to address in ACC, optional delay

Far call unconditionally, optional delay

Stack pointer immediate offset

‡

B[D] pmad

2/4,2

1111

0110

1111

1110

1111

0110

1111

1000

0100

1111

0100

1110

1111

00Z0

0111

1110

IAAA

0011

0010

AAAA

BACC[D] src

BANZ[D] pmad, Sind

BC[D] pmad, cond [, cond [, cond ]]

CALA[D] src

CALL[D] pmad

CC[D] pmad, cond [, cond [, cond ]]

FB[D] extpmad

FBACC[D] src

FCALA[D] src

FCALL[D] extpmad

FRAME K

1/6,4

01ZS

11Z0

§

¶

‡

2/4 ,2 ,2

§

¶

2/5 ,3 ,3

10Z0 CCCC CCCC

‡

1/6,4

01ZS

00Z0

1110

0111

0011

0100

¶

2/4,2

§

¶

‡

2/5 ,3 ,3

10Z1 CCCC CCCC

1KKK KKKK

‡

2/4,2

1/6,4

2/4,2

1/1

10Z0

01ZS

10Z1

1110

01Z0

01NN

0111

1101

0100

1011

1010

1011

1010

1110

0110

0111

1KKK KKKK

KKKK KKKK

‡

FRET[D]

Far return (FRETD is for delayed return)

Far return, enable interrupts, optional delay

Idle until interrupt

1/6,4

1/4

1110

110K

IAAA

1001

IAAA

0100

0101

‡

FRETE[D]

IDLE K

0001

INTR K

Software interrupt

1/3

KKKK

AAAA

0101

MAR Smem

Modify auxiliary register

1/1

NOP

No operation

1/1

POPD Smem

POPM MMR

PSHD Smem

PSHM MMR

Pop top of stack to data memory

Pop top of stack to memory-mapped register

Push data-memory value onto stack

Push memory-mapped register onto stack

Return conditionally, optional delay

Software reset

1/1

AAAA

1/1

§

¶, ‡

3

RC[D] cond [, cond [, cond ]]

RESET

1/5 ,3

11Z0 CCCC CCCC

1/3

1/5,3

1/3,1

1/1

0111

11Z0

01Z0

0111

1100

0000

00Z0

000D

01N0

01N1

0100

1110

0000

1110

1001

IAAA

0000

1011

AAAA

‡

RET[D]

Return, optional delay

RETE[D]

Return and enable interrupts, optional delay

Return fast and enable interrupts, optional delay

Repeat next instruction, count is in operand

Repeat next instruction, count is short immediate

Repeat next instruction, count is long immediate

Block repeat, optional delay

RETF[D]

RPT Smem

RPT #K

1/1

KKKK KKKK

RPT #lk

2/2

0111

1011

110K

0000

0010

0001

SBIT

KKKK

‡

RPTB[D] pmad

RPTZ dst, #lk

RSBX N, SBIT

SSBX N, SBIT

TRAP K

2/4,2

Repeat next instruction and clear accumulator

Reset status-register bit

2/2

1/1

Set status-register bit

1/1

Software interrupt

1/3

XC n, cond [, cond [, cond ] ]

Execute conditionally

1/1

11N1 CCCC CCCC

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes (Continued)

WORDS/

CYCLES

OPCODE

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

I/O INSTRUCTIONS

PORTR PA, Smem

Read data from port

Write data to port

LOAD/STORE INSTRUCTIONS

2/2

0111

0100

IAAA

AAAA

PORTW Smem, PA

0101

CMPS src, Smem

DLD Lmem, dst

DST src, Lmem

LD Smem, dst

Compare, select and store maximum

Long-word load to accumulator

1/1

1/2

1/1

1000

0101

0100

0001

0100

111S

011D

111S

000D

010D

IAAA

AAAA

Store accumulator in long word

Load accumulator with operand

LD Smem, TS, dst

LD Smem, 16, dst

Shift operand by TREG[5:0], then load into ACC

Shift operand by 16 bits, then load into ACC

Shift operand, then load into ACC

(2-word opcode)

0110

0000

1111

110D

IAAA

010S

AAAA

HIFT

LD Smem [, SHIFT ], dst

2/2

LD Xmem, SHFT, dst

LD #K, dst

Shift operand, then load into ACC

1/1

2/2

1/1

1/3

1/1

1001

1110

1111

0011

0100

1110

1111

0011

010D XXXX SHFT

100D KKKK KKKK

Load ACC with short-immediate operand

Shift long-immediate, then load into ACC

Shift long-immediate 16 bits, load into ACC

Shift ACC by value in ASM register

Shift accumulator

LD #lk [, SHFT ], dst

LD #lk, 16, dst

LD src, ASM [, dst ]

LD src [, SHIFT ] [, dst ]

LD Smem, T

000D

01SD

0000

0110

101K

1101

0100

0010

0110

1000

010S

IAAA

SHFT

0010

HIFT

AAAA

Load TREG with single data-memory operand

Load DP with single data-memory operand

Load DP with 9-bit operand

LD Smem, DP

LD #k9, DP

KKKK KKKK

LD #k5, ASM

Load ACC shift-mode register with 5-bit operand

Load ARP with 3-bit operand

000K

1010

IAAA

KKKK

0KKK

AAAA

LD #k3, ARP

LD Smem, ASM

Load operand bits 4–0 into ASM register

LD Xmem, dst

|| MAC[R] Ymem [, dst_ ]

Parallel load, multiply/accumulate [round]

Parallel load, multiply/subtract [round]

1/1

1010 10RD XXXX YYYY

LD Xmem, dst

|| MAS[R] Ymem [, dst_ ]

1010

11RD XXXX YYYY

LDM MMR, dst

LDR Smem, dst

LDU Smem, dst

LTD Smem

Load memory-mapped register

Load memory value in ACC high with rounding

Load unsigned memory value

Load TREG and insert delay

Store accumulator conditionally

Store block-repeat counter conditionally

Store TREG

1/1

2/2

1/1

0100

0001

0100

1001

1000

0111

1000

100D

011D

001D

1100

111S

1101

1100

1101

0110

001S

IAAA

AAAA

SACCD src, Xmem, cond

SRCCD Xmem, cond

ST T, Smem

XXXX COND

IAAA

AAAA

ST TRN, Smem

ST #lk, Smem

Store TRN

Store long-immediate operand

Store accumulator high to data memory

STH src, Smem

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes (Continued)

WORDS/

CYCLES

OPCODE

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

LOAD/STORE INSTRUCTIONS (CONTINUED)

Shift ACC high by ASM, store to data memory

Shift ACC high, then store to data memory

STH src, ASM, Smem

1/1

1000

1001

011S

101S

IAAA

AAAA

STH src, SHFT, Xmem

XXXX SHFT

Shift ACC high, then store to data memory

(2-word opcode)

0110

0000

1111

110S

IAAA

011S

AAAA

HIFT

STH src [, SHIFT ], Smem

2/2

1/1

ST src, Ymem

|| ADD Xmem, dst

Store ACC with parallel add

1100

1110

00SD XXXX YYYY

10SD XXXX YYYY

ST src, Ymem

|| LD Xmem, dst

Store ACC with parallel load into accumulator

Store ACC with parallel load into TREG

Parallel store and multiply ACC [round]

Parallel store, multiply, and subtract

Parallel store and multiply

ST src, Ymem

|| LD Xmem, T

01S0

XXXX YYYY

ST src, Ymem

|| MAC[R] Xmem, dst

1101 0RSD XXXX YYYY

1101 1RSD XXXX YYYY

ST src, Ymem

|| MAS[R] Xmem, dst

ST src, Ymem

|| MPY Xmem, dst

1100

11SD XXXX YYYY

01SD XXXX YYYY

ST src, Ymem

|| SUB Xmem, dst

Parallel store and subtract

STL src, Smem

Store ACC low to data memory

1/1

1000

1001

000S

010S

100S

IAAA

AAAA

STL src, ASM, Smem

STL src, SHFT, Xmem

Shift ACC low by ASM, store to data memory

Shift ACC low, then store to data memory

XXXX SHFT

Shift ACC low, then store to data memory

(2-word opcode)

0110

0000

1111

110S

IAAA

100S

AAAA

HIFT

STL src [, SHIFT], Smem

2/2

STLM src, MMR

STM #lk, MMR

Store accumulator low to memory

Store ACC low into memory-mapped register

Store TREG conditionally

1/1

2/2

1/1

1000

0111

1001

100S

0111

1100

IAAA

AAAA

STRCD Xmem, cond

XXXX COND

LOGICAL INSTRUCTIONS

AND Smem, src

AND single data-memory operand with ACC

Shift long-immediate operand, AND with ACC

Shift long-immediate 16 bits, AND with ACC

AND accumulator(s), then shift result

AND memory with long-immediate operand

Test bit

1/1

2/2

1/1

2/2

1/1

2/2

1/1

2/2

1/1

0001

1111

0110

1001

0110

0011

1111

0110

1111

0001

100S

00SD

1000

0110

IAAA

0011

0110

100S

IAAA

XXXX

IAAA

1001

IAAA

1010

IAAA

AAAA

SHFT

0011

AND #lk [, SHFT ], src [, dst ]

AND #lk, 16, src [, dst ]

AND src [, SHIFT ], [, dst ]

ANDM #lk, Smem

BIT Xmem, BITC

BITF Smem, #lk

HIFT

AAAA

BITC

AAAA

0011

Test bit field specified by immediate value

Test bit specified by TREG

0001

0100

01SD

0000

01CC

101S

BITT Smem

CMPL src [, dst ]

Complement accumulator

CMPM Smem, #lk

CMPR CC, ARx

Compare memory with long-immediate operand

Compare auxiliary register with AR0

OR single data-memory operand with ACC

AAAA

1ARX

AAAA

OR Smem, src

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

instruction set summary (continued)

Table 13. ’54x Instruction Set Opcodes (Continued)

WORDS/

CYCLES

OPCODE

MNEMONIC SYNTAX

DESCRIPTION

†

MSB

LSB

LOGICAL INSTRUCTIONS (CONTINUED)

Shiftlong-immediate operand, then OR with ACC

Shift long-immediate 16 bits, then OR with ACC

OR accumulator(s), then shift result

OR memory with constant

OR #lk [, SHFT ], src [, dst ]

OR #lk, 16, src [, dst ]

OR src [, SHIFT ], [, dst ]

ORM #lk, Smem

2/2

1/1

2/2

1/1

2/2

1/1

2/2

1111

0110

1111

0001

1111

0110

00SD

0100

0110

101S

IAAA

1001

011S

1001

111S

IAAA

0101

0110

110S

IAAA

SHFT

0100

HIFT

AAAA

0001

0010

0000

HIFT

0100

HIFT

AAAA

SHFT

0101

HIFT

AAAA

00SD

1001

010S

01SD

010S

00SD

110S

00SD

1010

ROL src

Rotate accumulator left

ROLTC src

Rotate accumulator left using TC

Rotate accumulator right

ROR src

SFTA src, SHIFT [, dst ]

SFTC src

Shift accumulator arithmetically

Shift accumulator conditionally

SFTL src, SHIFT [, dst ]

XOR Smem, src

Shift accumulator logically

XOR operand with ACC

XOR #lk [, SHFT], src [, dst ]

XOR #lk, 16, src [, dst ]

XOR src [, SHIFT] [, dst ]

XORM #lk, Smem

Shift long-immediate, then XOR with ACC

Shift long-immediate 16 bits, then XOR with ACC

XOR accumulator(s), then shift result

XOR memory with constant

MOVE INSTRUCTIONS

MVDD Xmem, Ymem

MVDK Smem, dmad

MVDM dmad, MMR

MVDP Smem, pmad

MVKD dmad, Smem

MVMD MMR, dmad

MVMM MMRx, MMRy

MVPD pmad, Smem

READA Smem

Move within data memory, X/Y addressing

Move data, destination addressing

Move data to memory-mapped register

Move data to program memory

1/1

2/2

2/4

2/2

1/1

2/3

1/5

1110

0111

1110

0111

0101

0001

0010

1101

0000

0011

XXXX YYYY

IAAA

AAAA

Move data with source addressing

Move memory-mapped register to data

Move between memory-mapped registers

Move program memory to data memory

Read data memory addressed by ACCA

Write data memory addressed by ACCA

0111 MMRX MMRY

1100

1110

1111

IAAA

AAAA

WRITA Smem

†

Values for words and cycles assume the use of DARAM for data. Add one word and one cycle when using long-offset indirect addressing or

absolute addressing with a single data-memory operand.

Delayed Instruction

Condition true

‡

§

¶

Condition false

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

development support

Texas Instruments offers an extensive line of development tools for the ’54x generation of DSPs, including tools

to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

The following products support development of ’54x-based applications:

Software Development Tools:

Assembler/Linker

Simulator

Optimizing ANSI C compiler

Application algorithms

C/Assembly debugger and code profiler

Hardware Development Tools:

Extended development system (XDS ) emulator (supports ’54x multiprocessor system debug)

’54x EVM (Evaluation Module)

’54x DSK (DSP Starter Kit)

The TMS320 Family Development Support Reference Guide (SPRU011) contains information about

development support products for all TMS320 family member devices, including documentation. Refer to this

document for further information about TMS320 documentation or any other TMS320 support products from

Texas Instruments. There is an additional document, the TMS320 Third Party Support Reference Guide

(SPRU052), which contains information about TMS320-related products from other companies in the industry.

To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924.

See Table 14 for complete listings of development support tools for the ’54x. For information on pricing and

availability, contact the nearest TI field sales office or authorized distributor.

Table 14. Development Support Tools

DEVELOPMENT TOOL

PLATFORM

Software

PART NUMBER

Assembler/Linker

PC-DOS , OS/2

PC-DOS, OS/2

SPARC

TMDS324L850-02

TMDS324L855-02

TMDS324L555-09

TMDS324L851-02

TMDS324L551-09

DFDP

Compiler/Assembler/Linker

Simulator

PC-DOS, WIN

SPARC, WIN

PC-DOS

Simulator

Digital Filter Design Package for PC

XDS510 Debugger/Emulation Software

XDS510WS Debugger/Emulation Software

PC-DOS, OS/2, WIN

SPARC, WIN

Hardware

TMDS32401L0

TMDS32406L0

†

XDS510 Emulator

PC-DOS, OS/2

SPARC, WIN

N/A

TMDS00510

‡

XDS510WS Emulator

TMDS00510WS

TMDS3080002

TMDX3260051

TMDX32400L0

3 V/5 V PC/SPARC JTAG Emulation Cable

EVM Evaluation Module

PC-DOS, WIN

PC-DOS

DSK DSP Starter Kit

†

‡

Includes XDS510 board and JTAG emulation cable; TMDS32401L0 C-source debugger conversion software not included

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable; TMDS32406L0 C-source debugger conversion software not

included

PC-DOS and OS/2 are trademarks of International Business Machines Corp.

SPARC is a trademark of SPARC International, Inc.

WIN is a trademark of Microstate Corporation.

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

device and development support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320

devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas

Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These

prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)

through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below.

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

Fully-qualified production device

Support tool development evolutionary flow:

TMDX

Development support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development support product

TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability

of the device has been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, PZ, PGE, PBK, or GGU) and temperature range (for example, L). Figure 10 provides a legend

for reading the complete device name for any TMS320 family member.

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

device and development support tool nomenclature (continued)

TMS 320 (B) C 542 PGE (L)

PREFIX

TEMPERATURE RANGE (DEFAULT: 0°C TO 70°C)

H = 0°C to 50°C

TMX= experimental device

TMP= prototype device

TMS= qualified device

SMJ = MIL-STD-883C

L

=

0°C to 70°C

S

–55°C to 100°C

M = –55°C to 125°C

SM = High Rel (non-883C)

A

= –40°C to 85°C

†

PACKAGE TYPE

DEVICE FAMILY

320 = TMS320 Family

N

=

plastic DIP

ceramic DIP

J

JD

GB

FZ

FN

FD

PJ

PQ

PZ

ceramic DIP side-brazed

ceramic PGA

BOOT-LOADER OPTION

ceramic CC

plastic leaded CC

ceramic leadless CC

100-pin plastic EIAJ QFP

132-pin plastic bumpered QFP

100-pin plastic TQFP

TECHNOLOGY

C = CMOS

E

F

=

CMOS EPROM

PBK = 128-pin plastic TQFP

PGE = 144-pin plastic TQFP

GGU = 144-pin BGA

CMOS Flash EEPROM

LC = Low-Voltage CMOS (3.3 V)

VC= Low Voltage CMOS [3 V (2.5 V core)]

DEVICE

’1x DSP:

10

14

15

16

17

’2x DSP:

’2xx DSP:

’3x DSP:

25

26

203 206 240

204 209

30

31

32

’4x DSP:

’5x DSP:

40

44

50

51

52

53

56

57

’54x DSP:

’6x DSP:

541 545

542 546

543 548

549

6201

6701

†

DIP = Dual-In-Line Package

PGA = Pin Grid Array

CC = Chip Carrier

QFP = Quad Flat Package

TQFP = Thin Quad Flat Package

Figure 10. TMS320 DSP Device Nomenclature

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement

through applications development. The types of documentation available include: data sheets, such as this

document, with design specifications; complete user’s guides for all devices; development support tools; and

hardware and software applications.

The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:

Volume 1: CPU and Peripherals (literature number SPRU131)

Volume 2: Mnemonic Instruction Set (literature number SPRU172)

Volume 3: Algebraic Instruction Set (literature number SPRU179)

Volume 4: Applications Guide (literature number SPRU173)

The reference set describes in detail the ’54x TMS320 products currently available and the hardware and

software applications, including algorithms, for fixed-point TMS320 devices.

For general background information on DSPs and TI devices, see the three-volume publication Digital Signal

Processing Applications with the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017).

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 newsletter, Details on Signal Processing, is published

quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board

service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source

code and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

electrical characteristics and operating conditions (’541, ’542)

absolute maximum ratings over specified temperature range (unless otherwise noted)

†

Supply voltage range, V ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

NOM

MAX

UNIT

V

Supply voltage

4.75

5

0

5.25

DD

V

SS

RS, INTn, NMI,CNT,CLKMDn

X2/CLKIN

3

V

+ 0.3

DD

V

IH

High-level input voltage

V

All other inputs

2

DD

V

Low-level input voltage

High-level output current

Low-level output current

Operating case temperature

–0.3

0.8

–300

2

V

IL

I

µA

mA

°C

OH

OL

T

C

–40

100

Refer to Figure 11 for 5-V device test load circuit values.

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

electrical characteristics and operating conditions (’541, ’542) (continued)

electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

†

TYP

PARAMETER

TEST CONDITIONS

= –300 µA

MIN

2.4

MAX

UNIT

‡

V

High-level output voltage

I

V

OH

‡

Low-level output voltage

Input current in high impedance

TRST

= 2 mA

= MAX,

0.6

20

V

OL

I

IZ

V

O

= V

to V

DD

–20

–10

µA

DD

SS

With internal pulldown

800

400

10

HPIENA

With internal pulldown, RS = 0

With internal pullups

–10

||

Input current

(V = V to V )

DD

TMS, TCK, TDI, HPI

–500

I

SS

µA

Bus holders enabled, V

DD

= MAX,

D[15:0], HD[7:0]

–175

–10

175

10

V = V

to V

I

SS

DD

All other input-only pins

§

¶

#

I

Supply current, core CPU

Supply current, pins

V

= 5 V, f = 40 MHz,

T

= 25°C

47

mA

DDC

DD

x

C

= 5 V, f = 40 MHz,

= 25°C

18

DDP

DD

x

C

IDLE2

IDLE3

PLL × 1 mode, 40 MHz input

Divide-by-two mode, CLKIN stopped

4

5

I

Supply current, standby

DD

µA

C

Input capacitance

Output capacitance

10

pF

i

o

†

‡

§

¶

All typical values are at V

= 5 V, T = 25°C.

C

DD

All input and output voltage levels except RS, INT0–INT3, NMI, CNT, X2/CLKIN, CLKMD0–CLKMD3 are TTL-compatible.

Clock mode: PLL × 1 with external source

This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being

executed.

#

||

This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,

refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).

HPI input signals except for HPIENA.

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

a

access time

H

L

High

c

cycle time (period)

delay time

Low

d

V

Z

Valid

dis

en

f

disable time

High impedance

enable time

fall time

h

hold time

r

rise time

su

t

setup time

transition time

valid time

v

w

X

pulse duration (width)

Unknown, changing, or don’t care level

I

OL

50 Ω

Output

Under

Test

Tester Pin

Electronics

V

Load

C

T

I

OH

Where: I

I

= 2 mA (all outputs)

= 300 µA (all outputs)

= 1.5 V

OL

OH

Load

T

V

C

= 40 pF typical load circuit capacitance.

Figure 11. 5-V Test Load Circuit

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

electrical characteristics and operating conditions (’LC54x, ’VC54x)

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

DD

‡

Supply voltage core range, CV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.75 V

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

3

NOM

3.3

MAX

3.6

UNIT

V

DV

CV

Device supply voltage, I/O (’LC54x -40, -50, -66, -80, -100)

Device supply voltage, core (’VC549-100)

DD

2.4

2.5

2.75

V

Supply voltage, GND

0

V

SS

RS,INTn,NMI,CNT, X2/CLKIN,

CLKMDn, DV = 3.3 0.3 V

2.5

DV

+ 0.3

High-level input voltage, I/O

(’LC54x -40, -50, -66, -80, -100)

DD

All other inputs

V

IH

2

+ 0.3

Low-level input voltage

High-level output current

Low-level output current

Operating case temperature

–0.3

0.8

V

IL

I

–300

1.5

µA

mA

°C

OH

OL

T

C

–40

100

Refer to Figure 12 for 3.3-V device test load circuit values.

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

electrical characteristics and operating conditions (’LC54x, ’VC54x) (continued)

electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

2.4

MAX

UNIT

‡

V

DD

= 3.3 0.3 V,

I

= MAX

V

High-level output voltage

OH

‡

Low-level output voltage

I

= MAX

0.4

V

OL

A[22:0] (’548/’549 only)

All other ’54x devices

V

DD

V

DD

= MAX, V = V

to V

–175

–10

175

O

SS

DD

Input current in high

impedance

I

IZ

µA

= MAX, V = V

10

O

TRST

With internal pulldown

–10

800

400

10

HPIENA

With internal pulldown, RS = 0

With internal pullups

||

TMS, TCK, TDI, HPI

Input current

(V = V to V )

DD

–400

I

µA

I

SS

Bus holders enabled, V

DD

= MAX,

D[15:0], HD[7:0]

–175

–10

175

10

V = V

to V

I

SS

DD

All other input-only pins

§

¶

I

Supply current, core CPU

DV

CV

= 3.0 V, f = 40 MHz,

T

= 25°C

28

mA

DDC

DD

x

C

Supply current, core CPU (’549 only)

= 2.5 V, f = 40 MHz,

x

20

DDC

§

#

2

I

Supply current, pins

V

DD

= 3.0 V, f = 40 MHz,

T

= 25°C

10.8

mA

DDP

DD

x

C

IDLE2

PLL × 1 mode, 40 MHz input

Divide-by-two mode, CLKIN stopped

Supply current,

standby

I

IDLE3

5

µA

C

Input capacitance

Output capacitance

10

pF

i

o

†

‡

§

¶

All values are typical unless otherwise specified.

All input and output voltage levels except RS, INT0–INT3, NMI, CNT, X2/CLKIN, CLKMD0–CLKMD3 are LVTTL-compatible.

Clock mode: PLL × 1 with external source

This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being

executed.

#

||

This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,

refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).

HPI input signals except for HPIENA.

Values derived from characterization data and not tested.

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

PARAMETER MEASUREMENT INFORMATION

I

OL

50 Ω

Output

Under

Test

Tester Pin

Electronics

V

Load

C

T

I

OH

Where: I

I

= 1.5 mA (all outputs)

= 300 µA (all outputs)

= 1.5 V

OL

OH

Load

T

V

C

= 40 pF typical load circuit capacitance.

Figure 12. 3.3-V Test Load Circuit

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

internal divide-by-two clock option with external crystal

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT

is one-half the crystal’s oscillating frequency. The crystal should be either fundamental or overtone operation,

and parallel resonant, with an effective series resistance of 30 Ω and power dissipation of 1 mW; it should be

specified at a load capacitance of 20 pF. Note the circuit shown in Figure 13 represents fundamental mode

operation. For overtone mode operation, additional components are generally required.

recommended operating conditions (see Figure 13)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN NOM

MAX

MIN NOM

MAX

MIN NOM

MAX

†

0

†

‡

133.33

f

Input clock frequency

80

0

100

0

MHz

pF

x

C1, C2

10

’LC54x-80

’VC54x-100

MIN NOM

UNIT

MIN NOM

MAX

‡§

†

0

‡§

160

†

0

f

x

200

MHz

pF

C1, C2

10

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

§

Values derived from characterization data and not tested.

It is recommended that the PLL clocking option be used for maximum frequency operation.

X1

X2/CLKIN

Crystal

C1

C2

Figure 13. Internal Divide-by-Two Clock Option With External Crystal

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

external divide-by-two clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected, CLKMD1 and CLKMD2 set low, and CLKMD3 set high. This external frequency is divided by two

to generate the internal machine cycle.

The external frequency injected must conform to specifications listed in the timing requirements table.

switching characteristics over recommended operating conditions [H = 0.5t

] (see Figure 13

c(CO)

†

and Figure 14, and the recommended operating conditions table )

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

PARAMETER

UNIT

MIN

25 2t

TYP

MAX

MIN

20 2t

TYP

MAX

MIN

TYP

MAX

‡

t

Cycle time, CLKOUT

15 2t

ns

c(CO)

c(CI)

10

Delay time, X2/CLKIN high to

CLKOUT high/low

t

6

12

18

6

12

18

4

16

d(CIH-CO)

†

t

Fall time, CLKOUT

2

ns

f(CO)

†

t

Rise time, CLKOUT

r(CO)

†

Pulse duration, CLKOUT low

H–4

H–2

H

H–4

H–2

H

H–4

H–2

H

w(COL)

w(COH)

†

Pulse duration, CLKOUT high

’LC54x-80

TYP

’VC54x-100

TYP

PARAMETER

UNIT

MIN

MAX

MIN

MAX

†§

‡

†§

‡

t

Cycle time, CLKOUT

12.5

2t

10

2t

ns

c(CO)

c(CI)

10

c(CI)

10

t

Delay time, X2/CLKIN high to CLKOUT high/low

4

16

4

16

d(CIH-CO)

†

t

Fall time, CLKOUT

2

f(CO)

†

t

Rise time, CLKOUT

Pulse duration, CLKOUT low

r(CO)

†

H–3

H–1

H

H–2

H–1

H

w(COL)

w(COH)

†

Pulse duration, CLKOUT high

†

‡

Values derived from characterization data and not tested.

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

§

It is recommended that the PLL clocking option be used for maximum frequency operation.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

external divide-by-two clock option (continued)

timing requirements over recommended operating conditions (see Figure 14)

’C54x-40

’LC54x-50

’LC54x-40

’54x-66

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

†

t

Cycle time, X2/CLKIN

12.5

10

7.5

ns

c(CI)

‡

Fall time, X2/CLKIN

4

f(CI)

‡

Rise time, X2/CLKIN

4

†

4

†

4

†

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

3

w(CIL)

w(CIH)

†

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

†

t

Cycle time, X2/CLKIN

6.25

5

ns

c(CI)

‡

Fall time, X2/CLKIN

1

f(CI)

‡

Rise time, X2/CLKIN

1

†

1

†

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

2

w(CIL)

w(CIH)

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

Values assured by design but not tested.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

t

r(CI)

t

f(CI)

w(CIH)

t

w(CIL)

c(CI)

X2/CLKIN

CLKOUT

t

f(CO)

t

c(CO)

t

r(CO)

w(COH)

t

d(CIH–CO)

t

w(COL)

Figure 14. External Divide-by-Two Clock Timing

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

external multiply-by-N clock option

An external frequency can be used by injecting the frequency directly into X2/CLKIN, with X1 left unconnected,

CLKMD1, CLKMD2, and CLKMD3 set according to the clock mode configuration table (Table 4). This external

frequency is multiplied by N to generate the internal machine cycle.

The external frequency injected must conform to specifications listed in the timing requirements table.

switching characteristics over recommended operating conditions [H = 0.5t

and Figure 15, and the recommended operating conditions table)

] (see Figure 13

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

TYP

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

t

Cycle time, CLKOUT

25

t

20

t

15

t

ns

c(CO)

c(CI)/N

Delay time, X2/CLKIN

high/low to CLKOUT

high/low

t

6

12

18

6

12

18

4

10

16

d(CIH-CO)

t

Fall time, CLKOUT

2

ns

s

f(CO)

r(CO)

w(COL)

w(COH)

p

t

Rise time, CLKOUT

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Transitory phase, PLL lock-up time

H–4

H–2

H

H–4

H–2

H

H–4

H–2

H

†

50

†

50

†

50

’LC54x-80

TYP

’VC54x-100

TYP

PARAMETER

UNIT

MIN

12.5

4

MAX

MIN

10

4

MAX

t

Cycle time, CLKOUT

t

ns

s

c(CO)

c(CI)/N

10

c(CI)/N

10

†

t

Delay time, X2/CLKIN high/low to CLKOUT high/low

16

d(CIH-CO)

t

Fall time, CLKOUT

2

f(CO)

r(CO)

w(COL)

w(COH)

p

t

Rise time, CLKOUT

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Transitory phase, PLL lock-up time

H–3

H–1

H

H–2

H–1

H

†

29

†

35

†

Values derived from characterization data and not tested

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

66

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

external multiply-by-N clock option (continued)

timing requirements over recommended operating conditions (see Figure 15)

’C54x-40

’LC54x-50

’LC54x-40

’54x-66

MIN MAX

UNIT

MIN

MAX

MIN

MAX

Integer PLL multiplier N (N = 1–15)

PLL multiplier N = x.5

25N 400N

25N 200N

20N 400N

20N 200N

15N 400N

15N 200N

t

Cycle time, X2/CLKIN

ns

c(CI)

PLL multiplier N = x.25, x.75

100N

25N 100N

20N 100N

15N

†

t

Fall time, X2/CLKIN

4

ns

f(CI)

†

Rise time, X2/CLKIN

4

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

8

6

3.5

w(CIL)

w(CIH)

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

Integer PLL multiplier N (N = 1–15)

PLL multiplier N = x.5

12.5N 400N

12.5N 200N

12.5N 100N

10N 400N

10N 200N

10N 100N

t

Cycle time, X2/CLKIN

ns

c(CI)

PLL multiplier N = x.25, x.75

†

t

Fall time, X2/CLKIN

2

ns

f(CI)

†

Rise time, X2/CLKIN

2

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

3

2

w(CIL)

w(CIH)

†

Values derived from characterization data and not tested.

t

w(CIL)

t

f(CI)

t

w(CIH)

t

r(CI)

t

c(CI)

X2/CLKIN

CLKOUT

t

d(CIH–CO)

t

f(CO)

t

w(COH)

t

c(CO)

t

w(COL)

t

r(CO)

P

Unstable

Figure 15. External Multiply-by-One Clock Timing

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

67

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a memory read

†‡

(MSTRB = 0) [H = 0.5 t

]

(see Figure 16)

c(CO)

’LC542-40

’LC543-40

’C54x-40

’LC54x-40

’LC54x-50

MIN MAX

’54x-66

MIN MAX

PARAMETER

UNIT

MIN MAX

MIN

MAX

Delay time, address valid from

CLKOUT low

¶

t

0

5

0

5

0

5

0

5

3

5

ns

d(CLKL-A)

§

Delay time, address valid from

¶

– 2

d(CLKH-A)

#

CLKOUT high (transition)

Delay time, MSTRB low from CLKOUT

low

t

0

d(CLKL-MSL)

Delay time, MSTRB high from

CLKOUT low

t

– 2

0

3

¶

– 2

0

3

¶

– 2

0

3

¶

– 2

0

3

¶

d(CLKL-MSH)

Hold time, address valid after CLKOUT

t

5

h(CLKL-A)R

h(CLKH-A)R

§

low

Hold time, address valid after CLKOUT

¶

5

¶

5

¶

5

¶

3

t

0

– 2

#

high

’LC54x-80

’VC54x-100

PARAMETER

Delay time, address valid from CLKOUT low

UNIT

MIN

MAX

MIN

MAX

§

¶

t

0

4

2

0

3

2

ns

d(CLKL-A)

#

¶

Delay time, address valid from CLKOUT high (transition)

d(CLKH-A)

t

Delay time, MSTRB low from CLKOUT low

0

d(CLKL-MSL)

t

Delay time, MSTRB high from CLKOUT low

– 2

0

– 2

0

d(CLKL-MSH)

§

¶

t

Hold time, address valid after CLKOUT low

4

3

h(CLKL-A)R

h(CLKH-A)R

#

¶

t

Hold time, address valid after CLKOUT high

0

†

Address, PS, and DS timings are all included in timings referenced as address.

‡

§

¶

#

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

In the case of a memory read preceded by a memory read

Values derived from characterization data and not tested.

In the case of a memory read preceded by a memory write

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

68

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

timing requirements over recommended operating conditions for a memory read (MSTRB = 0)

†‡

[H = 0.5 t

]

(see Figure 16)

c(CO)

’LC542-40

’LC543-40

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Access time, read data access from

address valid

t

2H–12

2H–10

ns

a(A)M

Access time, read data access from

MSTRB low

a(MSTRBL)

su(D)R

h(D)R

Setup time, read data before CLKOUT

low

7

0

5

0

5

0

5

2

Hold time, read data after CLKOUT

low

Hold time, read data after address

invalid

t

0

1

0

ns

h(A-D)R

Hold time, read data after MSTRB high

h(D)MSTRBH

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

2H–6

t

Access time, read data access from address valid

Access time, read data access from MSTRB low

Setup time, read data before CLKOUT low

Hold time, read data after CLKOUT low

2H–7.5

ns

a(A)M

a(MSTRBL)

su(D)R

5

2

1

0

4

2

1

0

h(D)R

Hold time, read data after address invalid

Hold time, read data after MSTRB high

h(A-D)R

h(D)MSTRBH

†

‡

Address, PS, and DS timings are all included in timings referenced as address.

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

69

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

CLKOUT

t

d(CLKL–A)

t

h(CLKL-A)R

A15–A0

t

h(A–D)R

t

su(D)R

t

a(A)M

t

h(D)R

D15–D0

t

h(D)MSTRBH

t

d(CLKL–MSL)

t

d(CLKL–MSH)

t

a(MSTRBL)

MSTRB

R/W

PS, DS

Figure 16. Memory Read (MSTRB = 0)

70

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

†‡

(MSTRB = 0) [H = 0.5 t

]

(see Figure 17)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

MIN MAX

PARAMETER

UNIT

MIN

MAX

§

#

t

Delay time, address valid from CLKOUT high

0

5

– 2

0

3

ns

d(CLKH-A)

¶

#

Delay time, address valid from CLKOUT low

Delay time, MSTRB low from CLKOUT low

Delay time, data valid from CLKOUT low

Delay time, MSTRB high from CLKOUT low

Delay time, R/W low from CLKOUT high

Delay time, R/W high from CLKOUT high

5

d(CLKL-A)

t

0

#

5

0

#

5

d(CLKL-MSL)

t

0

10

3

0

6

d(CLKL-D)W

t

– 2

0

– 2

3

d(CLKL-MSH)

t

5

3

d(CLKH-RWL)

t

– 2

H – 2

0

3

d(CLKH-RWH)

#

t

Delay time, MSTRB low after R/W low

H + 3 H – 2

H + 3

5

d(RWL-MSTRBL)

§

t

Hold time, address valid after CLKOUT high

5

0

h(A)W

’LC54x-80

MIN MAX

’VC54x-100

MIN MAX

PARAMETER

UNIT

§

#

t

Delay time, address valid from CLKOUT high

– 2

0

3

4

5

3

– 2

0

3

ns

d(CLKH-A)

¶

#

Delay time, address valid from CLKOUT low

Delay time, MSTRB low from CLKOUT low

Delay time, data valid from CLKOUT low

Delay time, MSTRB high from CLKOUT low

Delay time, R/W low from CLKOUT high

Delay time, R/W high from CLKOUT high

3

d(CLKL-A)

t

0

#

0

#

3

d(CLKL-MSL)

t

0

3

d(CLKL-D)W

t

– 2

3

d(CLKL-MSH)

t

3

d(CLKH-RWL)

t

– 2

d(CLKH-RWH)

#

t

Delay time, MSTRB low after R/W low

H – 2

0

H + 2 H – 2

H + 2

3

d(RWL-MSTRBL)

§

t

Hold time, address valid after CLKOUT high

3

0

h(A)W

†

‡

§

¶

#

Address, PS, and DS timings are all included in timings referenced as address.

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

In the case of a memory write preceded by a memory write.

In the case of a memory write preceded by an I/O cycle.

Values derived from characterization data and not tested.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

71

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

timing requirements over recommended operating conditions for a memory write (MSTRB = 0)

†‡

[H = 0.5 t

]

(see Figure 17)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

H–5

MAX

§¶

MIN

MAX

§¶

t

Hold time, write data valid after MSTRB high

H+5

H–5 H+5

2H–5

ns

h(D)MSH

w(SL)MS

su(A)W

¶

Pulse duration, MSTRB low

2H–5

Setup time, address valid before MSTRB low

Setup time, write data valid before MSTRB high

2H–5

§¶

2H–10 2H+10

2H–10 2H+8

su(D)MSH

’LC54x-80

’VC54x-100

UNIT

MIN

H–4

MAX

§¶

MIN

MAX

§¶

t

Hold time, write data valid after MSTRB high

H+4

H–3 H+3

2H–4

ns

h(D)MSH

w(SL)MS

su(A)W

¶

Pulse duration, MSTRB low

2H–5

Setup time, address valid before MSTRB low

Setup time, write data valid before MSTRB high

2H–4

§¶

2H–7 2H+7

2H–5 2H+5

su(D)MSH

†

Address, PS, and DS timings are all included in timings referenced as address.

‡

§

¶

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

In the case of a memory write preceded by an I/O cycle.

Values derived from characterization data and not tested.

CLKOUT

t

d(CLKH-A)

t

d(CLKL-A)

h(A)W

A15–A0

t

d(CLKL-D)W

t

h(D)MSH

t

su(D)MSH

D15–D0

MSTRB

R/W

t

d(CLKL-MSL)

t

d(CLKL-MSH)

t

su(A)W

t

d(CLKH-RWH)

d(CLKH-RWL)

t

w(SL)MS

t

d(RWL-MSTRBL)

PS, DS

Figure 17. Memory Write (MSTRB = 0)

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

72

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port read

†‡

(IOSTRB = 0) [H = 0.5 t

]

(see Figure 18)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’LC542-40

’LC543-40

’54x-66

MIN MAX

PARAMETER

UNIT

MIN

MAX

MIN

MAX

§

0

t

Delay time, address valid from CLKOUT low

Delay time, IOSTRB low from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Hold time, address after CLKOUT low

0

5

0

5

3

ns

d(CLKL-A)

t

0

– 2

0

d(CLKH-ISTRBL)

t

– 2

0

3

§

– 2

0

3

§

3

§

d(CLKH-ISTRBH)

t

5

h(A)IOR

’LC54x-80

’VC54x-100

PARAMETER

UNIT

MIN

MAX

MIN

MAX

§

t

Delay time, address valid from CLKOUT low

Delay time, IOSTRB low from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Hold time, address after CLKOUT low

0

4

0

3

ns

d(CLKL-A)

t

– 2

0

3

– 2

0

d(CLKH-ISTRBL)

t

3

§

d(CLKH-ISTRBH)

§

3

t

4

h(A)IOR

†

‡

§

Address and IS timings are included in timings referenced as address.

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

Values derived from characterization data and not tested.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

73

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

timing requirements over recommended operating conditions for a parallel I/O port read

†‡

(IOSTRB = 0) [H = 0.5 t

]

(see Figure 18)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’LC542-40

’LC543-40

’54x-66

MIN

UNIT

MIN

MAX

MIN

MAX

t

Access time, read data access from address valid

Access time, read data access from IOSTRB low

Setup time, read data before CLKOUT high

Hold time, read data after CLKOUT high

3H–12

2H–12

3H–10

2H–10

3H–10

2H–10

ns

a(A)IO

a(ISTRBL)IO

su(D)IOR

7

0

5

0

5

0

h(D)IOR

Hold time, read data after IOSTRB high

h(ISTRBH-D)R

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

t

Access time, read data access from address valid

Access time, read data access from IOSTRB low

Setup time, read data before CLKOUT high

Hold time, read data after CLKOUT high

3H–5

2H–5

3H–3

2H–3

ns

a(A)IO

a(ISTRBL)IO

su(D)IOR

4

0

4

0

h(D)IOR

Hold time, read data after IOSTRB high

h(ISTRBH-D)R

†

‡

Address and IS timings are included in timings referenced as address.

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

CLKOUT

t

h(A)IOR

d(CLKL–A)

A15–A0

t

h(D)IOR

t

su(D)IOR

t

a(A)IO

D15–D0

IOSTRB

t

h(ISTRBH–D)R

t

a(ISTRBL)IO

t

d(CLKH–ISTRBH)

t

d(CLKH–ISTRBL)

R/W

IS

Figure 18. Parallel I/O Port Read (IOSTRB = 0)

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

74

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

†

(IOSTRB = 0) [H = 0.5 t

] (see Figure 19)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

PARAMETER

UNIT

MIN

MAX

MIN MAX

‡

§

0

t

Delay time, address valid from CLKOUT low

0

5

3

ns

d(CLKL-A)

t

Delay time, IOSTRB low from CLKOUT high

0

§

5

–2

d(CLKH-ISTRBL)

§

t

Delay time, write data valid from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Delay time, R/W low from CLKOUT low

Delay time, R/W high from CLKOUT low

H–5

H+10 H–5

H+8

3

d(CLKH-D)IOW

t

– 2

0

3

5

3

§

–2

0

d(CLKH-ISTRBH)

t

5

d(CLKL-RWL)

d(CLKL-RWH)

h(A)IOW

t

– 2

0

–2

0

3

‡

§

5

Hold time, address valid from CLKOUT low

Hold time, write data after IOSTRB high

Setup time, write data before IOSTRB high

5

§

H+5

§

H–5

H–7

H–5 H+5

h(D)IOW

H

H–5

H

su(D)IOSTRBH

§

Setup time, address valid before IOSTRB low

H–5

H+5

ns

su(A)IOSTRBL

’LC54x-80

MIN MAX

’VC54x-100

MIN MAX

PARAMETER

UNIT

‡

§

0

t

Delay time, address valid from CLKOUT low

0

4

3

ns

d(CLKL-A)

t

Delay time, IOSTRB low from CLKOUT high

– 2

3

– 2

d(CLKH-ISTRBL)

§

H–5

§

t

Delay time, write data valid from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Delay time, R/W low from CLKOUT low

Delay time, R/W high from CLKOUT low

H+5 H–5

H+3

3

d(CLKH-D)IOW

t

– 2

0

3

4

2

§

–2

0

d(CLKH-ISTRBH)

t

3

d(CLKL-RWL)

d(CLKL-RWH)

h(A)IOW

t

– 2

0

–2

0

2

‡

§

3

Hold time, address valid from CLKOUT low

Hold time, write data after IOSTRB high

Setup time, write data before IOSTRB high

4

§

H+4

§

H–4

H–5

H–3 H+3

ns

h(D)IOW

H+1

H+5

H–3

H+1

H+3

su(D)IOSTRBH

su(A)IOSTRBL

§

Setup time, address valid before IOSTRB low

†

‡

§

See Table 15, Table 16, and Table 17 for address bus timing variation with load capacitance.

Address and IS timings are included in timings referenced as address.

Values derived from characterization data and not tested

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

75

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

memory and parallel I/O interface timing (continued)

CLKOUT

t

su(A)IOSTRBL

t

h(A)IOW

t

d(CLKL–A)

A15–A0

t

d(CLKH–D)IOW

t

h(D)IOW

D15–D0

t

d(CLKH–ISTRBL)

t

d(CLKH–ISTRBH)

su(D)IOSTRBH

IOSTRB

R/W

t

d(CLKL–RWH)

d(CLKL–RWL)

IS

Figure 19. Parallel I/O Port Write (IOSTRB = 0)

I/O timing variation with load capacitance: SPICE simulation results

Condition: Temperature : 125° C

Capacitance : 0–100pF

Voltage

Model

: 2.7/3.0/3.3 V

: Weak/Nominal/Strong

90%

10%

Figure 20. Rise and Fall Time Diagram

76

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

I/O timing variation with load capacitance: SPICE simulation results (continued)

Table 15. Timing Variation With Load Capacitance: [2.7 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.476 ns

1.511 ns

2.551 ns

3.614 ns

4.664 ns

5.752 ns

6.789 ns

7.817 ns

8.897 ns

10.021 ns

11.072 ns

0.457 ns

1.278 ns

2.133 ns

3.011 ns

3.899 ns

4.786 ns

5.656 ns

6.598 ns

7.531 ns

8.332 ns

9.299 ns

0.429 ns

1.386 ns

2.350 ns

3.327 ns

4.394 ns

5.273 ns

6.273 ns

7.241 ns

8.278 ns

9.152 ns

10.208 ns

0.391 ns

1.148 ns

1.956 ns

2.762 ns

3.566 ns

4.395 ns

5.206 ns

6.000 ns

6.928 ns

7.735 ns

8.537 ns

0.382 ns

1.215 ns

2.074 ns

2.929 ns

3.798 ns

4.655 ns

5.515 ns

6.442 ns

7.262 ns

8.130 ns

8.997 ns

0.323 ns

1.049 ns

1.779 ns

2.512 ns

3.264 ns

4.010 ns

4.750 ns

5.487 ns

6.317 ns

7.066 ns

7.754 ns

Table 16. Timing Variation With Load Capacitance: [3 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.436 ns

1.349 ns

2.273 ns

3.226 ns

4.168 ns

5.110 ns

6.033 ns

7.077 ns

8.020 ns

8.917 ns

9.885 ns

0.387 ns

1.185 ns

1.966 ns

2.765 ns

3.573 ns

4.377 ns

5.230 ns

5.997 ns

6.899 ns

7.709 ns

8.541 ns

0.398 ns

1.240 ns

2.098 ns

2.974 ns

3.849 ns

4.732 ns

5.660 ns

6.524 ns

7.416 ns

8.218 ns

9.141 ns

0.350 ns

1.064 ns

1.794 ns

2.539 ns

3.292 ns

4.052 ns

4.811 ns

5.601 ns

6.336 ns

7.124 ns

7.830 ns

0.345 ns

1.092 ns

1.861 ns

2.637 ns

3.406 ns

4.194 ns

5.005 ns

5.746 ns

6.559 ns

7.323 ns

8.101 ns

0.290 ns

0.964 ns

1.634 ns

2.324 ns

3.013 ns

3.710 ns

4.401 ns

5.117 ns

5.861 ns

6.498 ns

7.238 ns

77

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

I/O timing variation with load capacitance: SPICE simulation results (continued)

Table 17. Timing Variation With Load Capacitance: [3.3 V] 10% – 90% [3 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.404 ns

1.227 ns

2.070 ns

2.931 ns

3.777 ns

4.646 ns

5.487 ns

6.405 ns

7.284 ns

8.159 ns

8.994 ns

0.361 ns

1.081 ns

1.822 ns

2.567 ns

3.322 ns

4.091 ns

4.859 ns

5.608 ns

6.463 ns

7.097 ns

7.935 ns

0.371 ns

1.133 ns

1.915 ns

2.719 ns

3.515 ns

4.319 ns

5.145 ns

5.980 ns

6.723 ns

7.560 ns

8.300 ns

0.310 ns

1.001 ns

1.675 ns

2.367 ns

3.072 ns

3.779 ns

4.503 ns

5.234 ns

5.873 ns

6.692 ns

7.307 ns

0.321 ns

1.000 ns

1.704 ns

2.414 ns

3.120 ns

3.842 ns

4.571 ns

5.301 ns

5.941 ns

6.740 ns

7.431 ns

0.284 ns

0.892 ns

1.530 ns

2.169 ns

2.823 ns

3.466 ns

4.142 ns

4.767 ns

5.446 ns

6.146 ns

6.822 ns

78

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

ready timing for externally generated wait states

timing requirements over recommended operating conditions for externally generated wait states

†

[H = 0.5 t

] (see Figure 21, Figure 22, Figure 23, and Figure 24)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

MIN MAX

UNIT

MIN

10

0

MAX

MIN

8

MAX

t

Setup time, READY before CLKOUT low

Hold time, READY after CLKOUT low

7

0

ns

su(RDY)

0

h(RDY)

§

Valid time, READY after MSTRB low

4H–15

5H–15

4H–12

5H–12

4H–10

5H–10

v(RDY)MSTRB

h(RDY)MSTRB

v(RDY)IOSTRB

h(RDY)IOSTRB

v(MSCL)

§

Hold time, READY after MSTRB low

4H

5H

4H

5H

4H

5H

§

Valid time, READY after IOSTRB low

§

Hold time, READY after IOSTRB low

‡

0

‡

0

‡

0

Valid time, MSC low after CLKOUT low

Valid time, MSC high after CLKOUT low

5

3

5

3

5

3

‡

–2

‡

–2

‡

–2

v(MSCH)

’LC54x-80

’VC54x-100

UNIT

MIN

6

MAX

MIN

5

MAX

t

Setup time, READY before CLKOUT low

Hold time, READY after CLKOUT low

ns

su(RDY)

0

h(RDY)

§

Valid time, READY after MSTRB low

4H–10

5H–10

4H–8

5H–8

v(RDY)MSTRB

h(RDY)MSTRB

v(RDY)IOSTRB

h(RDY)IOSTRB

v(MSCL)

§

Hold time, READY after MSTRB low

4H

5H

4H

5H

§

Valid time, READY after IOSTRB low

§

Hold time, READY after IOSTRB low

‡

0

‡

Valid time, MSC low after CLKOUT low

Valid time, MSC high after CLKOUT low

4

2

0

3

2

‡

–2

‡

–2

v(MSCH)

†

The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by

READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

Values derived from characterization data and not tested.

‡

§

These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

79

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

ready timing for externally generated wait states (continued)

CLKOUT

A15–A0

t

su(RDY)

t

h(RDY)

READY

MSTRB

MSC

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait State

Generated

by READY

Wait States

Generated Internally

Figure 21. Memory Read With Externally Generated Wait States

80

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

ready timing for externally generated wait states (continued)

CLKOUT

A15–A0

D15–D0

READY

MSTRB

MSC

t

h(RDY)

t

su(RDY)

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait State

Generated Internally

Wait State Generated

by READY

Figure 22. Memory Write With Externally Generated Wait States

81

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

ready timing for externally generated wait states (continued)

CLKOUT

A15–A0

t

h(RDY)

t

su(RDY)

READY

IOSTRB

MSC

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait State

Generated

Internally

Figure 23. I/O Read With Externally Generated Wait States

82

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

ready timing for externally generated wait states (continued)

CLKOUT

A15–A0

D15–D0

READY

IOSTRB

MSC

t

h(RDY)

t

su(RDY)

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait State

Generated

Internally

Figure 24. I/O Write With Externally Generated Wait States

83

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

HOLD and HOLDA timing

switching characteristics over recommended operating conditions for memory control signals

and HOLDA [H = 0.5 t

] (see Figure 25)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’LC54x-80

’VC54x-100

’54x-66

PARAMETER

UNIT

MIN

MAX MIN

MAX

MIN

MAX

Disable time, CLKOUT low to address, PS, DS, IS high

t

5

ns

dis(CLKL-A)

dis(CLKL-RW)

dis(CLKL-S)

‡

impedance

Disable time, CLKOUT low to R/W high impedance

Disable time, CLKOUT low to MSTRB, IOSTRB high

‡

impedance

‡

t

Enable time, CLKOUT low to address, PS, DS, IS

2H+5

ns

en(CLKL-A)

en(CLKL-RW)

en(CLKL-S)

‡

Enable time, CLKOUT low to R/W enabled

‡

Enable time, CLKOUT low to MSTRB, IOSTRB enabled

Valid time, HOLDA low after CLKOUT low

2

†

0

– 2

5

0

5

ns

t

v(HOLDA)

†

3

†

3

– 2

Valid time, HOLDA high after CLKOUT low

Pulse duration, HOLDA low duration

2H–3

w(HOLDA)

†

‡

Values derived from characterization data and not tested.

Values assured by design but not tested.

timing

[H = 0.5 t

requirements

c(CO)

over

recommended

operating

conditions

for

HOLD

] (see Figure 25)

’C54x-40

’LC54x-40

’LC54x-50

’LC54x-80

’VC54x-100

’54x-66

UNIT

MIN

MAX

MIN

4H+10

10

MAX

4H+10

10

MIN

t

Pulse duration, HOLD low duration

4H+10

10

ns

w(HOLD)

Setup time, HOLD before CLKOUT low

su(HOLD)

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

84

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TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

HOLD and HOLDA timing (continued)

CLKOUT

t

su(HOLD)

t

w(HOLD)

HOLD

t

v(HOLDA)

w(HOLDA)

t

HOLDA

t

en(CLKL–A)

dis(CLKL–A)

A15–A0

PS, DS, IS

D15–D0

R/W

t

en(CLKL–RW)

dis(CLKL–RW)

dis(CLKL–S)

t

en(CLKL–S)

MSTRB

IOSTRB

t

en(CLKL–S)

Figure 25. HOLD and HOLDA Timing (HM = 1)

85

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

reset, BIO, interrupt, and MP/MC timings

timing requirements over recommended operating conditions for reset, interrupt, BIO, and MP/MC

[H = 0.5 t

] (see Figure 26, Figure 27, and Figure 28)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

MIN MAX

UNIT

MIN

0

MAX

MIN

0

MAX

t

Hold time, RS after CLKOUT low

0

ns

h(RS)

Hold time, BIO after CLKOUT low

0

h(BIO)

†

Hold time, INTn, NMI, after CLKOUT low

0

h(INT)

‡

Hold time, MP/MC after CLKOUT low

§¶||

0

h(MPMC)

w(RSL)

Pulse duration, RS low

Pulse duration, BIO low, synchronous

4H+10

2H+15

4H

4H+10

2H+12

4H

4H+10

2H+10

4H

¶

w(BIO)S

w(BIO)A

w(INTH)S

w(INTH)A

w(INTL)S

w(INTL)A

‡

Pulse duration, BIO low, asynchronous

Pulse duration, INTn, NMI high (synchronous)

¶

2H+15

4H

2H+12

4H

2H+10

4H

‡

Pulse duration, INTn, NMI high (asynchronous)

¶

Pulse duration, INTn, NMI low (synchronous)

2H+15

4H

2H+12

4H

2H+10

4H

‡

Pulse duration, INTn, NMI low (asynchronous)

Pulse duration, INTn, NMI low for IDLE2/IDLE3

wakeup

t

10

ns

w(INTL)WKP

‡

#

t

Setup time, RS before X2/CLKIN low

5

15

10

5

12

10

5

10

ns

su(RS)

Setup time, BIO before CLKOUT low

su(BIO)

su(INT)

su(MPMC)

Setup time, INTn, NMI, RS before CLKOUT low

‡

Setup time, MP/MC before CLKOUT low

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is

corresponding to three CLKOUTs sampling sequence.

Values assured by design but not tested.

IfthePLLmodeisselected,thenatpower-onsequence,oratwakeupfromIDLE3,RSmustbeheldlowforatleast50µstoassuresynchronization

and lock-in of the PLL.

‡

§

¶

#

||

Values derived from characterization data and not tested.

Divide-by-two mode

Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).

86

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

reset, BIO, interrupt, and MP/MC timings (continued)

timing requirements over recommended operating conditions for reset, interrupt, BIO, and MP/MC

[H = 0.5 t ] (see Figure 26, Figure 27, and Figure 28) (continued)

c(CO)

’LC54x-80

’VC54x-100

UNIT

MIN

0

MAX

MIN

0

MAX

t

Hold time, RS after CLKOUT low

ns

h(RS)

Hold time, BIO after CLKOUT low

0

h(BIO)

†

Hold time, INTn, NMI, after CLKOUT low

0

h(INT)

‡

Hold time, MP/MC after CLKOUT low

§¶||

0

h(MPMC)

w(RSL)

Pulse duration, RS low

Pulse duration, BIO low, synchronous

4H+7

2H+7

4H

2H+7

4H

2H+7

4H

10

4H+5

2H+5

4H

2H+7

4H

2H+7

4H

8

¶

w(BIO)S

w(BIO)A

w(INTH)S

w(INTH)A

w(INTL)S

w(INTL)A

w(INTL)WKP

su(RS)

‡

Pulse duration, BIO low, asynchronous

Pulse duration, INTn, NMI high (synchronous)

¶

‡

Pulse duration, INTn, NMI high (asynchronous)

¶

Pulse duration, INTn, NMI low (synchronous)

‡

Pulse duration, INTn, NMI low (asynchronous)

‡

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

#

Setup time, RS before X2/CLKIN low

5

Setup time, BIO before CLKOUT low

10

8

su(BIO)

Setup time, INTn, NMI, RS before CLKOUT low

10

8

su(INT)

‡

Setup time, MP/MC before CLKOUT low

10

8

su(MPMC)

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is

corresponding to three CLKOUTs sampling sequence.

Values assured by design but not tested.

IfthePLLmodeisselected,thenatpower-onsequence,oratwakeupfromIDLE3,RSmustbeheldlowforatleast50µstoassuresynchronization

and lock-in of the PLL.

‡

§

¶

#

||

Values derived from characterization data and not tested.

Divide-by-two mode

Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

87

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

reset, BIO, interrupt, and MP/MC timings (continued)

X2/CLKIN

t

su(RS)

t

w(RSL)

RS, INTn, NMI

t

su(INT)

t

h(RS)

CLKOUT

t

su(BIO)

t

h(BIO)

BIO

t

w(BIO)S

Figure 26. Reset and BIO Timings

CLKOUT

t

su(INT)

h(INT)

INTn, NMI

t

w(INTH)A

t

w(INTL)A

Figure 27. Interrupt Timing

CLKOUT

RS

t

h(MPMC)

t

su(MPMC)

MP/MC

Figure 28. MP/MC Timing

88

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing

switching characteristics over recommended operating conditions for IAQ and IACK

[H = 0.5 t

] (see Figure 29)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

’LC54x-80

’VC54x-100

PARAMETER

UNIT

MIN

0

MAX

MIN

0

MAX

t

Delay time, IAQ low from CLKOUT low

Delay time, IAQ high from CLKOUT low

Delay time, address valid before IAQ low

Delay time, IACK low from CLKOUT low

5

3

4

3

5

3

4

3

ns

d(CLKL-IAQL)

t

– 2

d(CLKL-IAQH)

d(A)IAQ

†

t

– 2

d(CLKL-IACKL)

†

– 2

†

– 2

t

Delay time , IACK high from CLKOUT low

Delay time, address valid before IACK low

d(CLKL-IACKH)

d(A)IACK

h(A)IAQ

†

t

†

Hold time, address valid after IAQ high

0

†

Hold time, address valid after IACK high

h(A)IACK

w(IAQL)

†

Pulse duration, IAQ low

2H–10

†

Pulse duration, IACK low

w(IACKL)

†

Values derived from characterization data and not tested.

CLKOUT

A15–A0

t

d(CLKL–IAQH)

h(A)IAQ

d(CLKL–IAQL)

t

d(A)IAQ

t

w(IAQL)

IAQ

t

d(CLKL–IACKH)

h(A)IACK

d(CLKL–IACKL)

t

d(A)IACK

t

w(IACKL)

IACK

MSTRB

Figure 29. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timing

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

89

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing

(continued)

switching characteristics over recommended operating conditions for external flag (XF) and TOUT

[H = 0.5 t

] (see Figure 30 and Figure 31)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

’LC54x-80

’VC54x-100

PARAMETER

UNIT

MIN

MAX

MIN

MAX

†

Delay time, XF high after CLKOUT low

Delay time, XF low after CLKOUT low

– 2

3

– 2

3

t

ns

d(XF)

†

0

†

0

5

t

Delay time, TOUT high after CLKOUT low

Delay time, TOUT low after CLKOUT low

Pulse duration, TOUT

– 2

–2

3

– 2

–2

3

ns

d(TOUTH)

d(TOUTL)

w(TOUT)

†

2H–10

†

Values derived from characterization data and not tested.

CLKOUT

t

d(XF)

XF

Figure 30. External Flag (XF) Timing

CLKOUT

TOUT

t

d(TOUTL)

d(TOUTH)

t

w(TOUT)

Figure 31. TOUT Timing

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

90

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial port receive timing

switching characteristics over recommended operating conditions for serial port receive

[H = 0.5 t

] (see Figure 32)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

PARAMETER

UNIT

MIN

7

MAX

MIN

6

MAX

MIN

6

MAX

t

Hold time, FSR after CLKR falling edge

Hold time, DR after CLKR falling edge

ns

h(FSR)

7

6

h(DR)

timing requirements over recommended operating conditions for serial port receive [H = 0.5 t

(see Figure 32)

]

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

†

t

Cycle time, serial port clock

6H

†

6

ns

c(SCK)

f(SCK)

r(SCK)

w(SCK)

su(FSR)

su(DR)

‡

Fall time, serial port clock

6

‡

Rise time, serial port clock

Pulse duration, serial port clock low/high

Setup time, FSR before CLKR falling edge

Setup time, DR before CLKR falling edge

3H

7

3H

6

3H

6

7

6

†

The serial port design is fully static and, therefore, can operate with t

of 0 Hz but tested at a much higher frequency to minimize test time.

Values assured by design but not tested.

approaching ∞. It is characterized approaching an input frequency

c(SCK)

‡

t

c(SCK)

t

f(SCK)

t

w(SCK)

CLKR

FSR

t

r(SCK)

h(FSR)

t

w(SCK)

t

su(FSR)

t

su(DR)

t

h(DR)

DR

BIT

1

2

7/15

8/16

Figure 32. Serial Port Receive Timing

91

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial port transmit timing

switching characteristics over recommended operating conditions for serial port transmit with

external clocks and frames [H = 0.5t

] (see Figure 33)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

MIN MAX

’54x-66

MIN MAX

PARAMETER

UNIT

MIN MAX

t

Delay time, DX valid after CLKX rising

Delay time, FSX after CLKX rising edge

25

2H–8

40

25

2H–5

40

25

2H–5

40

ns

d(DX)

d(FSX)

dis(DX)

†

Disable time, DX after CLKX rising

†

Values derived from characterization data and not tested

timing requirements over recommended operating conditions for serial port transmit with external

clocks and frames [H = 0.5t ] (see Figure 33)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

UNIT

MIN

6H

–5

7

MAX

MIN

6H

–5

6

MAX

MIN

6H

– 5

6

MAX

‡

t

Cycle time, serial port clock

ns

c(SCK)

Hold time, DX valid after CLKX rising

h(DX)

Hold time, FSX after CLKX falling edge (see Note 1)

Hold time, FSX after CLKX rising edge (see Note 1)

h(FSX)

h(FSX)H

f(SCK)

r(SCK)

w(SCK)

§

2H–5

2H–8

2H–5

¶

Fall time, serial port clock

6

¶

Rise time, serial port clock

Pulse duration, serial port clock low/high

3H

‡

The serial port design is fully static and, therefore, can operate with t

of 0 Hz but tested at a much higher frequency to minimize test time.

approaching ∞. It is characterized approaching an input frequency

c(SCK)

§

¶

If the FSX pulse does not meet this specification, the first bit of serial data is driven on DX until the falling edge of FSX. After the falling edge of

FSX, data is shifted out on DX pin. The transmit buffer-empty interrupt is generated when the t

Values assured by design but not tested.

t

specification is met.

h(FSX) and h(FSX)H

NOTE 1: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on

the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX

is independent of the source of CLKX.

t

c(SCK)

t

w(SCK)

f(SCK)

CLKX

t

r(SCK)

d(FSX)

t

h(FSX)H

t

h(FSX)

t

w(SCK)

FSX

t

d(DX)

t

dis(DX)

8/16

t

h(DX)

DX BIT

1

2

7/15

Figure 33. Serial Port Transmit Timing With External Clocks and Frames

92

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial port transmit timing (continued)

switching characteristics over recommended operating conditions for serial port transmit with

internal clocks and frames [H = 0.5t

] (see Figure 34)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

PARAMETER

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

t

Cycle time, serial port clock

Delay time, CLKX rising to FSX

Delay time, CLKX rising to DX

Disable time, CLKX rising to DX

8H

ns

c(SCK)

d(FSX)

d(DX)

15

20

15

20

†

dis(DX)

h(DX)

Hold time, DX valid after CLKX rising edge

Fall time, serial port clock

–5

4

f(SCK)

r(SCK)

w(SCK)

Rise time, serial port clock

Pulse duration, serial port clock low/high

4H–8

†

Values derived from characterization data and not tested.

t

c(SCK)

t

w(SCK)

f(SCK)

CLKX

t

d(FSX)

t

w(SCK)

r(SCK)

t

d(FSX)

t

d(DX)

FSX

DX

t

dis(DX)

t

h(DX)

1

2

7/15

8/16

Figure 34. Serial Port Transmit Timing With Internal Clocks and Frames

93

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

buffered serial port receive timing

timing requirements over recommended operating conditions (see Figure 35)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

†

t

Cycle time, serial port clock

25

20

ns

c(SCK)

f(SCK)

r(SCK)

w(SCK)

‡

Fall time, serial port clock

4

‡

Rise time, serial port clock

‡

Pulse duration, serial port clock low/high

8.5

2

6

2

6

2

Setup time, BFSR before BCLKR falling

edge (see Note 2)

t

ns

su(BFSR)

h(BFSR)

Hold time, BFSR after BCLKR falling

edge (see Note 2)

§

t

10

t

10

t

10 t

c(SCK)–2

Setup time, BDR before BCLKR falling

edge

t

0

ns

su(BDR)

Hold time, BDR after BCLKR falling edge

10

h(BDR)

†

Theserialportdesignisfullystaticandthereforecanoperatewitht

of 0 Hz but tested at a much higher frequency to minimize test time.

Values assured by design but not tested.

approachinginfinity. Itischaracterizedapproachinganinputfrequency

c(SCK)

‡

§

First bit is read when BFSR is sampled low by BCLKR clock.

NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.

t

c(SCK)

t

f(SCK)

t

w(SCK)

BCLKR

BFSR

BDR

t

r(SCK)

t

w(SCK)

h(BFSR)

su(BFSR)

t

su(BDR)

t

h(BDR)

1

2

8/10/12/16

Figure 35. Buffered Serial Port Receive Timing

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

94

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

buffered serial port transmit timing of external frames

switching characteristics over recommended operating conditions (see Figure 36)

’C54x-40

’LC54x-40

’LC54x-50

’LC54x-80

’VC54x-100

’54x-66

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t

Delay time, BDX valid after BCLKX rising

18

6

18

6

ns

18

6

d(BDX)

†

Disable time, BDX after BCLKX rising

Disable time, PCM mode, BDX after BCLKX rising

4

dis(BDX)

†

6

dis(BDX)pcm

en(BDX)pcm

h(BDX)

†

Enable time, PCM mode, BDX after BCLKX rising

8

4

8

2

8

2

Hold time, BDX valid after BCLKX rising

†

Values assured by design but not tested.

timing requirements over recommended operating conditions (see Figure 36)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

‡

t

Cycle time, serial port clock

25

20

ns

c(SCK)

f(SCK)

r(SCK)

†

Fall time, serial port clock

4

†

Rise time, serial port clock

Pulse duration, serial port clock low/

high

t

8.5

6

ns

w(SCK)

†

Hold time, BFSX after CLKX falling edge

(see Notes 3 and 4)

§

6

t

c(SCK)–6

h(BFSX)

su(BFSX)

c(SCK)–6

Setup time, FSX before CLKX falling

edge (see Notes 3 and 4)

†

‡

Values assured by design but not tested.

Theserialportdesignisfullystaticandthereforecanoperatewitht

approachinginfinity. Itischaracterizedapproachinganinputfrequency

c(SCK)

of 0 Hz but tested at a much higher frequency to minimize test time.

If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).

After falling edge of the BFSX, data will be shifted out on the BDX pin.

§

NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

95

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

buffered serial port transmit timing of external frames (continued)

t

c(SCK)

t

f(SCK)

t

w(SCK)

BCLKX

BFSX

BDX

t

r(SCK)

t

h(BFSX)

t

w(SCK)

su(BFSX)

t

dis(BDX)

t

h(BDX)

t

d(BDX)

1

2

8/10/12/16

Figure 36. Buffered Serial Port Transmit Timing of External Clocks and External Frames

96

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

buffered serial port transmit timing of internal frame and internal clock

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 37)

’C54x-40

’LC54x-80

’VC54x-100

’LC54x-40

’LC54x-50

’54x-66

PARAMETER

UNIT

MIN

MAX

MIN

MAX

†

t

Cycle time, serial port clock, internal clock

2H 62H

2H

62H

ns

c(SCK)

Delay time, BFSX after BCLKX rising edge

(see Notes 3 and 4)

10

d(BFSX)

t

Delay time, BDX valid after BCLKX rising edge

8

5

8

5

ns

d(BDX)

†

Disable time, BDX after BCLKX rising edge

Disable time, PCM mode, BDX after BCLKX rising edge

0

dis(BDX)

dis(BDX)pcm

en(BDX)pcm

h(BDX)

†

Enable time, PCM mode, BDX after BCLKX rising edge

Hold time, BDX valid after BCLKX rising edge

7

0

7

0

†

Fall time, serial port clock

4

f(SCK)

†

Rise time, serial port clock

r(SCK)

†

Pulse duration, serial port clock low/high

H–4

w(SCK)

†

Values assured by design but not tested.

NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.

t

c(SCK)

t

f(SCK)

t

w(SCK)

BCLKX

t

r(SCK)

d(BFSX)

t

w(SCK)

t

d(BFSX)

BFSX

t

dis(BDX)

t

h(BDX)

t

d(BDX)

BDX

1

2

8/10/12/16

Figure 37. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

97

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial-port receive timing in TDM mode

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5t

] (’542/’543 only) (see Figure 38)

c(CO)

’542

’543

UNIT

†

MAX

MIN

t

Cycle time, serial-port clock

8H

‡

6

ns

c(SCK)

Fall time, serial-port clock

f(SCK)

Rise time, serial-port clock

r(SCK)

Pulse duration, serial-port clock low/high

Setup time, TDAT/TADD before TCLK falling edge

4H

–(3H–9)

0

w(SCK)

su(TD-TCL)

h(TCH-TD)

h(TCL-TD)

su(TF-TCH)

h(TCH-TF)

Hold time, TDAT/TADD after TCLK rising edge, t

w(SCKL)

< 5H

> 5H

Hold time, TDAT/TADD after TCLK falling edge, t

w(SCKL)

5H+5

10

§

Setup time, TFRM before TCLK rising edge

§

Hold time, TFRM after TCLK rising edge

10

†

‡

Values assured by design and are not tested.

Theserial-portdesignisfullystaticand,therefore,canoperatewitht

c(SCK)

of 0 Hz but tested at a much higher frequency to minimize test time.

TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 39.

approachinginfinity.Itischaracterizedapproachinganinputfrequency

§

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5t

] (all other ’C54x/’LC54x/’VC54x devices) (see Figure 38)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’LC54x-80

’VC54x-100

’54x-66

UNIT

†

MAX

MIN MAX

MIN

‡

t

Cycle time, serial-port clock

8H

‡

6

16H

‡

6

ns

c(SCK)

Fall time, serial-port clock

6

f(SCK)

Rise time, serial-port clock

r(SCK)

Pulse duration, serial-port clock low/high

Setup time, TDAT/TADD before TCLK rising edge

Hold time, TDAT/TADD after TCLK rising edge

4H

25

– 6

10

4H

10

1

8H

10

1

w(SCK)

su(TD-TCH)

h(TCH-TD)

su(TF-TCH)

h(TCH-TF)

§

Setup time, TFRM before TCLK rising edge

10

§

Hold time, TFRM after TCLK rising edge

†

‡

Values assured by design and are not tested.

Theserial-portdesignisfullystaticand,therefore,canoperatewitht

c(SCK)

of 0 Hz but tested at a much higher frequency to minimize test time.

TFRM timing and waveforms shown in Figure 38 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 39.

approachinginfinity.Itischaracterizedapproachinganinputfrequency

§

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

98

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial-port receive timing in TDM mode (continued)

t

w(SCK)

t

f(SCK)

t

r(SCK)

w(SCK)

TCLK

‡

t

su(TD-TCL)

t

c(SCK)

†

t

su(TD-TCH)

‡

t

h(TCL-TD)

t

h(TCH-TD)

B13

TDAT

B0

B14

A1

B12

B11

A4

B2

B1

B0

B15

A0

t

su(TF-TCH)

TADD

TFRM

A7

A2

A3

t

h(TCH-TF)

†

‡

All devices except ’542/’543

’542/’543 only

Figure 38. Serial-Port Receive Timing in TDM Mode

99

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial-port transmit timing in TDM mode

switching characteristics over recommended operating conditions [H = 0.5t

] (see Figure 39)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’542

’543

PARAMETER

UNIT

MIN

MAX

MIN

MAX

†

t

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK external

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal

3

1

0

ns

h(TCH-TDV)

†

– 5

h(TCH-TDV)

‡

§

Delay time, TFRM valid after TCLK rising edge TCLK ext

Delay time, TFRM valid after TCLK rising edge, TCLK int

H – 3 3H + 22

t

ns

d(TCH-TFV)

d(TC-TDV)

‡

H – 3 3H + 12

Delay time, TCLK to valid TDAT/TADD rising edge, TCLK ext

Delay time, TCLK to valid TDAT/TADD rising edge, TCLK int

18

25

18

t

’LC54x-80

’VC54x-100

’54x-66

MAX

PARAMETER

UNIT

MIN

1

MIN

MAX

t

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK external

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal

Delay time, TFRM valid after TCLK rising edge,

1

ns

h(TCH-TDV)

1

h(TCH-TDV)

§

H – 3

3H+22

H – 3

3H+22

‡

TCLK ext

t

ns

d(TCH-TFV)

d(TC-TDV)

Delay time, TFRM valid after TCLK rising edge,

3H+12

‡

TCLK int

Delay time, TCLK to valid TDAT/TADD rising edge, TCLK ext

Delay time, TCLK to valid TDAT/TADD rising edge, TCLK int

25

18

25

18

t

†

‡

Values derived from characterization data but not tested.

TFRM timing and waveforms shown in Figure 39 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is

illustrated in the receive timing diagram in Figure 38.

§

Values assured by design but are not tested.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

100

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

serial-port transmit timing in TDM mode (continued)

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5t ] (see Figure 39)

c(CO)

’C54x-40

’LC54x-40

’LC54x-50

’54x-66

’LC54x-80

’VC54x-100

UNIT

MIN

MAX

MIN

MAX

‡

§

†

‡

§

t

Cycle time, serial-port clock

Fall time, serial-port clock

8H

16H

8H

ns

c(SCK)

f(SCK)

r(SCK)

w(SCK)

†

6

Rise time, serial-port clock

6

‡

4H

‡

Pulse duration, serial-port clock low/high

†

Values assured by design but are not tested.

‡

§

When SCK is generated internally, this value is typical.

The serial-port design is fully static and, therefore, can operate with t

of 0 Hz but tested as a much higher frequency to minimize test time.

approaching . It is characterized approaching an input frequency

c(SCK)

t

f(SCK)

t

w(SCK)

t

w(SCK)

t

r(SCK)

B15

TCLK

t

c(SCK)

t

d(TC-TDV)

TDAT

TADD

B0

h(TCH-TDV)

B14

B13

A2

B12

A3

B8 B7

B2

B1

B0

t

h(TCH-TDV)

t

d(TC-TDV)

A1

A7

t

d(TCH-TFV)

A0

t

d(TCH-TFV)

TFRM

Figure 39. Serial-Port Transmit Timing in TDM Mode

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

101

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing

switching characteristics over recommended operating conditions [H = 0.5t

(see Notes 5 and 6) (see Figure 40 through Figure 43)

]

c(CO)

’C54x-40

’C54x-50

PARAMETER

’C54x-66

UNIT

MIN

‡

MAX

‡

12

t

Delay time, DS low to HD driven

5

ns

d(DSL-HDV)

d(HEL-HDV1)

Case 1: Shared-access mode if

< 7H

7H+20–t

w(DSH)

t

w(DSH)

Case 2: Shared-access mode if

> 7H

‡

20

t

w(DSH)

Case 3: Host-only mode if

< 20 ns

Delaytime,HDSfallingtoHDvalidforfirstbyte

of a non-subsequent read: → max 20 ns

t

ns

§¶

40–t

w(DSH)

t

w(DSH)

Case 4: Host-only mode if

> 20 ns

‡

20

t

w(DSH)

‡

¶

5

t

Delay time, DS low to HD valid, second byte

20

ns

d(DSL-HDV2)

d(DSH-HYH)

su(HDV-HYH)

h(DSH-HDV)R

‡

Delay time, DS high to HRDY high

10H+10

‡

†

Setup time, HD valid before HRDY rising edge

Hold time, HD valid after DS rising edge, read

3H–10

0

12

Delay time, CLKOUT rising edge to HRDY

high

‡

t

10

ns

d(COH-HYH)

d(DSH-HYL)

d(COH-HTX)

Delay time, HDS or HCS high to HRDY low

Delay time, CLKOUT rising edge to HINT

12

15

†

change

†

‡

§

Values derived from characterization data and not tested.

Values assured by design but not tested.

Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access

mode. HRDY does not go low for these accesses.

¶

Shared-access mode timings will be met automatically if HRDY is used.

NOTES: 5. SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be

specified here.

102

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

switching characteristics over recommended operating conditions [H = 0.5t

(see Notes 5 and 6) (see Figure 40 through Figure 43) (continued)

]

c(CO)

’LC54x-80

’VC54x-100

PARAMETER

UNIT

MIN

‡

MAX

‡

12

t

Delay time, DS low to HD driven

5

ns

d(DSL-HDV)

d(HEL-HDV1)

Case 1: Shared-access mode if

< 7H

7H+20–t

w(DSH)

t

w(DSH)

Case 2: Shared-access mode if

> 7H

‡

20

t

w(DSH)

Case 3: Host-only mode if

< 20 ns

Delaytime,HDSfallingtoHDvalidforfirstbyte

of a non-subsequent read: → max 20 ns

t

ns

§¶

40–t

w(DSH)

t

w(DSH)

Case 4: Host-only mode if

> 20 ns

‡

20

t

w(DSH)

‡

¶

5

t

Delay time, DS low to HD valid, second byte

20

ns

d(DSL-HDV2)

d(DSH-HYH)

su(HDV-HYH)

h(DSH-HDV)R

‡

Delay time, DS high to HRDY high

10H+10

‡

†

Setup time, HD valid before HRDY rising edge

Hold time, HD valid after DS rising edge, read

3H–10

0

12

Delay time, CLKOUT rising edge to HRDY

high

‡

t

10

ns

d(COH-HYH)

d(DSH-HYL)

d(COH-HTX)

Delay time, HDS or HCS high to HRDY low

Delay time, CLKOUT rising edge to HINT

12

15

†

change

†

‡

§

Values derived from characterization data and not tested.

Values assured by design but not tested.

Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access

mode. HRDY does not go low for these accesses.

¶

Shared-access mode timings will be met automatically if HRDY is used.

NOTES: 5. SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be

specified here.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

103

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

timing requirements over recommended operating conditions [H = 0.5t

(see Figure 40 through Figure 43)

] (see Note 5)

c(CO)

’C54x-40

’C54x-50

’C54x-66

’LC54x-80

’VC54x-100

UNIT

MIN

10

5

MAX

MIN

10

5

MAX

t

Setup time, HAD/HBIL valid before DS falling edge

Hold time, HAD/HBIL valid after DS falling edge

Setup time, HAS low before DS falling edge

Pulse duration, DS low

ns

su(HBV-DSL)

h(DSL-HBV)

su(HSL-DSL)

w(DSL)

12

†

30

†

30

Pulse duration, DS high

10

50

10

w(DSH)

Case 1: When using HRDY

(see Access Timing With HRDY)

50

Cycle time, DS rising Case 2a: SAM accesses and HOM active writes

edge to next DS rising to DSPINT or HINT without using HRDY

‡

10H

‡

10H

†

t

ns

c(DSH-DSH)

edge

(see Access Timings Without HRDY)

Case 2b: When not using HRDY for other HOM

accesses

50

t

Setup time, HD valid before DS rising edge

Hold time, HD valid after DS rising edge, write

12

3

12

3

ns

su(HDV-DSH)

h(DSH – HDV)W

†

A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according

to the HPI mode.

Values assured by design but not tested.

‡

NOTE 5: SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

104

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

Valid

HAD

t

h(DSL-HBV)

t

h(DSL-HBV)

t

su(HBV-DSL)

t

su(HBV-DSL)

HBIL

t

w(DSH)

t

w(DSL)

t

w(DSL)

HCS

HDS

t

c(DSH-DSH)

t

d(DSL-HDV2)

Valid

t

d(HEL-HDV1)

t

h(DSH-HDV)

t

h(DSH-HDV)R

t

d(DSL-HDV)

HD

READ

Valid

t

su(HDV-DSH)

t

h(DSH-HDV)W

h(DSH-HDV)

HD

WRITE

Valid

Figure 40. Read/Write Access Timings Without HRDY or HAS

105

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

HAS

t

su(HSL-DSL)

t

h(DSL-HBV)

Valid

HAD

HBIL

t

su(HBV-DSL)

t

c(DSH-DSH)

t

w(DSH)

t

c(DSH-DSH)

t

w(DSL)

HCS

HDS

t

d(HEL-HDV1)

t

d(DSL-HDV2)

Valid

t

h(DSH-HDV)R

t

h(DSH-HDV)R

t

d(DSL-HDV)

t

HD

READ

Valid

t

su(HDV-DSH)

t

h(DSH-HDV)W

t

h(DSH-HDV)W

HD

WRITE

Valid

Figure 41. Read/Write Access Timings Using HAS Without HRDY

106

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

HAS

t

su(HSL-DSL)

t

su(HBV-DSL)

t

h(DSL-HBV)

HAD

†

t

h(DSL-HBV)

†

t

su(HBV-DSL)

HBIL

t

c(DSH-DSH)

t

w(DSH)

t

w(DSL)

HCS

HDS

t

su(HDV-HYH)

t

d(DSH-HYH)

HRDY

t

d(DSH-HYL)

Valid

t

d(DSL-HDV2)

Valid

t

d(HEL-HDV1)

t

h(DSH-HDV)R

t

h(DSH-HDV)R

t

d(DSL-HDV)

HD

READ

t

su(HDV-DSH)

t

su(HDV-DSH)

t

h(DSH-HDV)W

t

h(DSH-HDV)W

HD

WRITE

Valid

t

d(COH-HYH)

CLKOUT

HINT

t

d(COH-HTX)

†

When HAS is tied to V

DD

Figure 42. Read/Write Access Timing With HRDY

107

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

host port interface timing (continued)

HCS

t

d(DSH-HYL)

HRDY

HDS

t

d(DSH-HYH)

Figure 43. HRDY Signal When HCS is Always Low

108

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

MECHANICAL DATA

TMS320LC542/’LC545 128-Pin Thin Plastic Quad Flatpack (TQFP)

PBK (S-PQFP-G128)

PLASTIC QUAD FLATPACK

0,23

0,40

96

M

0,07

64

0,13

65

97

128

33

0,13 NOM

1

32

Gage Plane

12,40 TYP

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040279-3/B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

Thermal Resistance Characteristics

PARAMETER

°C/W

R

58

ΘJA

ΘJC

R

10

109

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

MECHANICAL DATA

TMS320C542/’LC542/’LC548, ’LC549, ’VC549 144-Pin Thin Plastic Quad Flatpack (TQFP)

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

0,17

M

0,08

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/B 10/94

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-136

Thermal Resistance Characteristics

PARAMETER

°C/W

R

56

ΘJA

ΘJC

R

5

110

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

MECHANICAL DATA

TMS320C541/’LC541/’LC543/’LC546 100-Pin Thin Plastic Quad Flatpack (TQFP)

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 10/94

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-136

Thermal Resistance Characteristics

PARAMETER

°C/W

R

58

ΘJA

ΘJC

R

10

111

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998

MECHANICAL DATA

TMS320LC548, TMS320LC549, and TMS320VC549 144-Pin Plastic Ball Grid Array Package (BGA)

GGU (S-PBGA-N144)

PLASTIC BALL GRID ARRAY PACKAGE

12,10

11,90

SQ

13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

0,80

K

L

M

N

0,80

0,95

0,85

1,40 MAX

0,10

0,12

0,08

0,55

0,45

0,35

M

0,08

4073221/A 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

Thermal Resistance Characteristics

PARAMETER

°C/W

R

38

ΘJA

ΘJC

R

5

112

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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型号：	TMS320LC541PZ-80
厂家：	TEXAS INSTRUMENTS
描述：	16-BIT, 160MHz, OTHER DSP, PQFP100, PLASTIC, TQFP-100 时钟外围集成电路
文件：	总113页 (文件大小：1732K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320LC541PZ-80 [TI]

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