TMS320M642AZDK5_技术文档

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

1.1 Features

Memory Space

•

High-Performance Digital Media Processor

–

2-, 1.67-, 1.39-ns Instruction Cycle Time

500-, 600-, 720-MHz Clock Rate

Eight 32-Bit Instructions/Cycle

4000, 4800, 5760 MIPS

•

Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

10/100 Mb/s Ethernet MAC (EMAC)

–

IEEE 802.3 Compliant

Media Independent Interface (MII)

8 Independent Transmit (TX) Channels and

1 Receive (RX) Channel

Fully Software-Compatible With C64x™

•

VelociTI.2™ Extensions to VelociTI™

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x™ DSP Core

•

Management Data Input/Output (MDIO)

Three Configurable Video Ports

–

Eight Highly Independent Functional Units

With VelociTI.2™ Extensions:

–

Providing a Glueless I/F to Common Video

Decoder and Encoder Devices

•

Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle

–

Supports Multiple Resolutions/Video Stds

•

VCXO Interpolated Control Port (VIC)

Supports Audio/Video Synchronization

•

Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Results) per Clock Cycle

–

•

Host-Port Interface (HPI) [32-/16-Bit]

32-Bit/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.2

–

Load-Store Architecture With Non-Aligned

Support

64 32-Bit General-Purpose Registers

Instruction Packing Reduces Code Size

All Instructions Conditional

–

•

Multichannel Audio Serial Port (McASP)

–

Eight Serial Data Pins

Wide Variety of I²S and Similar Bit Stream

Format

•

Instruction Set Features

–

Byte-Addressable (8-/16-/32-/64-Bit Data)

8-Bit Overflow Protection

Bit-Field Extract, Set, Clear

Normalization, Saturation, Bit-Counting

VelociTI.2™ Increased Orthogonality

–

Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,

CP-430 Formats

•

Inter-Integrated Circuit (I²C Bus™)

Two Multichannel Buffered Serial Ports

Three 32-Bit General-Purpose Timers

Sixteen General-Purpose I/O (GPIO) Pins

Flexible PLL Clock Generator

L1/L2 Memory Architecture

–

128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)

128K-Bit (16K-Byte) L1D Data Cache (2-Way

Set-Associative)

2M-Bit (256K-Byte) L2 Unified Mapped

RAM/Cache (Flexible RAM/Cache

Allocation)

IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

•

548-Pin Ball Grid Array (BGA) Package

(GDK and ZDK Suffixes), 0.8-mm Ball Pitch

•

Endianess: Little Endian, Big Endian

64-Bit External Memory Interface (EMIF)

548-Pin Ball Grid Array (BGA) Package

(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch

•

0.13-µm/6-Level Cu Metal Process (CMOS)

3.3-V I/O, 1.2-V Internal (-500)

–

Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

Synchronous Memories (SDRAM, SBSRAM,

ZBT SRAM, and FIFO)

3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,

-720)

•

1024M-Byte Total Addressable External

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a registered trademark of Microsoft Corporation.

I²C Bus is a trademark of Philips Electronics N.V..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

1.2 Description

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point

DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on

the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architec-

ture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for

digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the

DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The

DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of

array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length

and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic

units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units

include new instructions to accelerate the performance in video and imaging applications and extend the

parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates

(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for

a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,

and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.

The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is

a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory

space that is shared between program and data space. L2 memory can be configured as mapped

memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a

10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO

interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated

circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose

timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component

interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event

generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of

interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port

peripherals provide a glueless interface to common video decoder and encoder devices. The DM642

video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video

display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display

buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated

Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can

be individually allocated to any of the two zones. The serial port supports time-division multiplexing on

each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins

transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on

multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC

Sound (I²S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,

CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of

user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection

circuit for each high-frequency master clock which verifies that the master clock is within a programmed

frequency range.

2

TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits

to up to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC

port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide

(literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP

core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10

Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of

service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows

efficient data transmission and reception.For more details on the EMAC, see the TMS320C6000 DSP

Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference

Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the

MDIO module transparently monitors its link state by reading the PHY status register. Link change events

are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link

status of the device without continuously performing costly MDIO accesses. For more details on the

MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data

Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and

communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP)

may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM642 has a complete set of development tools which includes: a new C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows^®debugger interface for visibility into

source code execution.

1.2.1 Device Compatibility

The DM642 device is a code-compatible member of the C6000™ DSP platform.

The C64x™ DSP generation of devices has a diverse and powerful set of peripherals.

For more detailed information on the device compatibility and similarities/differences among the DM642

and other C64x™ devices, see the TMS320DM642 Technical Overview (literature number SPRU615).

TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

3

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the DM642 device.

64

SDRAM

TMS320DM642

EMIF A

SBSRAM

Timer 2

L1P Cache

Direct-Mapped

16K Bytes Total

ZBT SRAM

Timer 1

FIFO

Timer 0

SRAM

VCXO

C64x DSP Core

Interpolated

ROM/FLASH

I/O Devices

Control Port

(VIC)

Instruction Fetch

Control

Registers

Instruction Dispatch

Advanced Instruction Packet

Video Port 2

(VP2)

Control

Logic

Instruction Decode

Video Port 0

(VP0)

Data Path A

Data Path B

Test

OR

A Register File

A31−A16

B Register File

B31−B16

Advanced

In-Circuit

Emulation

8/10-bit VP0

AND

A15−A0

B15−B0

(A)

McBSP0

OR

McASP0

Control

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

Interrupt

Control

L2

Cache

Enhanced

DMA

Memory

256kBytes

Controller

(EDMA)

Video Port 1

(VP1)

L1D Cache 2-Way Set-Associative

16K Bytes Total

OR

8/10-bit VP1

AND

McBSP1

(B)

(A)

Power-Down

Logic

PLL

(x1, x6, x12)

OR

McASP0

Data

PCI-66

OR

HPI32

OR

HPI16

AND/OR

EMAC

Boot Configuration

MDIO

16

2

GP0

I2C0

A. McBSPs: Framing Chips – H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs

B. The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video

Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is

muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these

peripherals, see the Device Configurations section of this data sheet.

Figure 1-1. Functional Block Diagram

4

TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Contents

1

2

TMS320DM642 Video/Imaging Fixed-Point Digital

5

DM642 Peripheral Information and Electrical

Signal Processor......................................... 1

1.1 Features .............................................. 1

1.2 Description............................................ 2

1.2.1 Device Compatibility ................................. 3

1.3 Functional Block Diagram ............................ 4

Device Overview ......................................... 6

2.1 Device Characteristics................................ 6

2.2 CPU (DSP Core) Description......................... 7

2.3 Memory Map Summary ............................. 13

2.4 Bootmode ........................................... 16

2.5 Pin Assignments .................................... 16

2.6 Development ........................................ 50

Device Configurations................................. 54

3.1 Configurations at Reset ............................. 54

3.2 Configurations After Reset .......................... 56

3.3 Peripheral Configuration Lock....................... 59

3.4 Device Status Register Description ................. 61

3.5 Multiplexed Pin Configurations...................... 63

3.6 Debugging Considerations .......................... 65

3.7 Configuration Examples............................. 66

Device Operating Conditions ........................ 70

Specifications ........................................... 72

5.1 Parameter Information .............................. 72

5.2

Recommended Clock and Control Signal Transition

Behavior ............................................. 74

5.3 Power Supplies...................................... 74

5.4

Enhanced Direct Memory Access (EDMA) Control-

ler.................................................... 79

5.5 Interrupts ............................................ 83

5.6 Reset ................................................ 85

5.7 Clock PLL ........................................... 88

5.8 External Memory Interface (EMIF) .................. 94

5.9

Multichannel Audio Serial Port (McASP0) Periph-

eral ................................................. 110

3

5.10 Inter-Integrated Circuit (I2C)....................... 118

5.11 Host-Port Interface (HPI) .......................... 124

5.12 Peripheral Component Interconnect (PCI) ........ 130

5.13 Multichannel Buffered Serial Port (McBSP) ....... 134

5.14 Video Port ......................................... 143

5.15 VCXO Interpolated Control (VIC).................. 151

5.16 Ethernet Media Access Controller (EMAC)........ 153

5.17 Management Data Input/Output (MDIO) .......... 159

5.18 Timer............................................... 161

5.19 General-Purpose Input/Output (GPIO) ............ 163

5.20 JTAG............................................... 166

4

4.1

Absolute Maximum Ratings Over Operating Case

Temperature Range

(Unless Otherwise Noted) .......................... 70

Revision History............................................ 168

6

4.2 Recommended Operating Conditions............... 70

Mechanical Data....................................... 170

6.1 Thermal Data ...................................... 170

6.2 Packaging Information ............................. 171

4.3

Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 71

Contents

5

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the DM642 DSP. The table shows significant features of the DM642

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type

with pin count.

Table 2-1. Characteristics of the DM642 Processor

HARDWARE FEATURES

DM642

EMIFA (64-bit bus width)

(clock source = AECLKIN)

1

EDMA (64 independent channels)

McASP0 (uses Peripheral Clock [AUXCLK])

I2C0 (uses Peripheral Clock)

1

HPI (32- or 16-bit user selectable)

1 (HPI16 or HPI32)

Peripherals

PCI (32-bit), 66-MHz/33-MHz

[DeviceID Register value 0x9065]

1

2

Not all peripherals pins are

available at the same time

(For more detail, see the

Device Configuration sec-

tion).

McBSPs

(internal clock source = CPU/4 clock frequency)

Configurable Video Ports (VP0, VP1, VP2)

10/100 Ethernet MAC (EMAC)

3

1

Management Data Input/Output (MDIO)

VCXO Interpolated Control Port (VIC)

32-Bit Timers

(internal clock source = CPU/8 clock frequency)

3

General-Purpose Input/Output Port (GP0)

Size (Bytes)

16

288K

16K-Byte (16KB) L1 Program (L1P) Cache

16KB L1 Data (L1D) Cache

On-Chip Memory

Organization

256KB Unified Mapped RAM/Cache (L2)

CPU ID + CPU Rev ID

JTAG BSDL_ID

Frequency

Control Status Register (CSR.[31:16])

JTAGID register (address location: 0x01B3F008)

MHz

0x0C01

0x0007902F

500, 600, 720

2 ns (DM642-500) and (DM642A-500)

[500 MHz CPU, 100 MHz EMIF⁽¹⁾, 33 MHz PCI port]

1.67 ns (DM642-600)

Cycle Time

Voltage

ns

[600 MHz CPU, 133 MHz EMIF⁽¹⁾, 66 MHz PCI port]

1.39 ns (DM642-720)

[720 MHz CPU, 133 MHz EMIF⁽¹⁾, 66 MHz PCI port]

1.2 V (–500)

1.4 V (A-500, A-600, -600, -720)

Core (V)

I/O (V)

3.3 V

PLL Options

CLKIN frequency multiplier

23 x 23 mm

Bypass (x1), x6, x12

548-Pin BGA (GDK and ZDK)

548-Pin BGA (GNZ and ZNZ)

0.13 µm

BGA Package

27 x 27 mm

Process Technology

Product Status⁽²⁾

µm

Product Preview (PP), Advance Information (AI),

or Production Data (PD)

PD

(1) On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the

EMIF device speed portion of this data sheet.

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

6

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.2 CPU (DSP Core) Description

The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to

eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW

architecture features controls by which all eight units do not have to be supplied with instructions if they

are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs

to the same execute packet as the previous instruction, or whether it should be executed in the following

clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute

packets can vary in size. The variable-length execute packets are a key memory-saving feature,

distinguishing the C64x CPUs from other VLIW architectures. The C64x™ VelociTI.2™ extensions add

enhancements to the TMS320C62x™ DSP VelociTI™ architecture. These enhancements include:

•

Register file enhancements

Data path extensions

Quad 8-bit and dual 16-bit extensions with data flow enhancements

Additional functional unit hardware

Increased orthogonality of the instruction set

Additional instructions that reduce code size and increase register flexibility

The CPU features two sets of functional units. Each set contains four units and a register file. One set

contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The

two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to

supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW

architecture, the C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The

two sets of functional units, along with two register files, compose sides A and B of the CPU [see the

functional block and CPU (DSP core) diagram, and Figure 2-1]. The four functional units on each side of

the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data

cross path"—a single data bus connected to all the registers on the other side, by which the two sets of

functional units can access data from the register files on the opposite side. The C64x CPU pipelines

data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a

data-cross-path operand by multiple functional units in the same execute packet. All functional units in the

C64x CPU can access operands via the data cross path. Register access by functional units on the same

side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a

delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that

register was updated in the previous clock cycle.

In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive

collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the

C64x CPU to operate directly on packed data to streamline data flow and increase instruction set

efficiency. This is a key factor for video and imaging applications.

Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on

registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are

responsible for all data transfers between the register files and the memory. The data address driven by

the .D units allows data addresses generated from one register file to be used to load or store data to or

from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and

words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load

and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store

instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU

supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit

offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers,

however, are singled out to support specific addressing modes or to hold the condition for conditional

instructions (if the condition is not automatically "true").

Device Overview

7

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform

two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 ×

32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit

multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count,

rotate, Galois field multiplies, and bidirectional variable shift hardware.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with

results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single

32-bit, dual 16-bit, and quad 8-bit operations.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program

memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits

in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for

simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an

instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A

C64x™ DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the

TMS320C62x™/TMS320C67x™ DSP devices, if an execute packet crosses the fetch-packet boundary

(256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch

packet is padded with NOP instructions. In the C64x™ DSP device, the execute boundary restrictions

have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus,

decreasing the overall code size. The number of execute packets within a fetch packet can vary from one

to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock

cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional

units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in

32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All

load and store instructions are byte-, half-word-, word-, or doubleword-addressable.

For more details on the C64x CPU functional units enhancements, see the following documents:

•

TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)

TMS320C64x Technical Overview (literature number SPRU395)

8

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

src1

.L1

src2

dst

8

long dst

8

long src

32 MSBs

32 LSBs

ST1b (Store Data)

ST1a (Store Data)

8

long src

8

long dst

dst

Register

File A

(A0−A31)

src1

.S1

Data Path A

src2

(A)

long dst

dst

src1

.M1

src2

32 MSBs

32 LSBs

LD1b (Load Data)

LD1a (Load Data)

dst

DA1 (Address)

src1

.D1

.D2

src2

2X

1X

src2

src1

dst

DA2 (Address)

32 LSBs

32 MSBs

LD2a (Load Data)

LD2b (Load Data)

src2

src1

dst

.M2

(A)

long dst

Register

File B

(B0− B31)

src2

Data Path B

.S2

src1

dst

long dst

long src

8

32 MSBs

32 LSBs

ST2a (Store Data)

ST2b (Store Data)

8

long src

8

long dst

dst

src2

.L2

src1

Control Register

File

A. For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.

Figure 2-1. TMS320C64x™ CPU (DSP Core) Data Paths

Device Overview

9

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.2.1 CPU Core Registers

Table 2-2. L2 Cache Registers (C64x)

HEX ADDRESS RANGE

0184 0000

ACRONYM

REGISTER NAME

Cache configuration register

Reserved

COMMENTS

CCFG

–

0184 0004 – 0184 0FFC

0184 1000

EDMAWEIGHT L2 EDMA access control register

0184 1004 – 0184 1FFC

0184 2000

–

Reserved

L2ALLOC0

L2ALLOC1

L2ALLOC2

L2ALLOC3

–

L2 allocation register 0

0184 2004

L2 allocation register 1

0184 2008

L2 allocation register 2

0184 200C

L2 allocation register 3

0184 2010 – 0184 3FFC

0184 4000

Reserved

L2WBAR

L2WWC

L2WIBAR

L2WIWC

L2IBAR

L2IWC

L2 writeback base address register

L2 writeback word count register

L2 writeback invalidate base address register

L2 writeback invalidate word count register

L2 invalidate base address register

L2 invalidate word count register

L1P invalidate base address register

L1P invalidate word count register

L1D writeback invalidate base address register

L1D writeback invalidate word count register

Reserved

0184 4004

0184 4010

0184 4014

0184 4018

0184 401C

0184 4020

L1PIBAR

L1PIWC

L1DWIBAR

L1DWIWC

–

0184 4024

0184 4030

0184 4034

0184 4038 – 0184 4044

0184 4048

L1DIBAR

L1DIWC

–

L1D invalidate base address register

L1D invalidate word count register

Reserved

0184 404C

0184 4050 – 0184 4FFC

0184 5000

L2WB

L2 writeback all register

0184 5004

L2WBINV

–

L2 writeback invalidate all register

Reserved

0184 5008 – 0184 7FFC

MAR0 to

MAR127

0184 8000 – 0184 81FC

Reserved

0184 8200

0184 8204

0184 8208

0184 820C

0184 8210

0184 8214

0184 8218

0184 821C

0184 8220

0184 8224

0184 8228

0184 822C

0184 8230

0184 8234

0184 8238

0184 823C

MAR128

MAR129

MAR130

MAR131

MAR132

MAR133

MAR134

MAR135

MAR136

MAR137

MAR138

MAR139

MAR140

MAR141

MAR142

MAR143

Controls EMIFA CE0 range 8000 0000 – 80FF FFFF

Controls EMIFA CE0 range 8100 0000 – 81FF FFFF

Controls EMIFA CE0 range 8200 0000 – 82FF FFFF

Controls EMIFA CE0 range 8300 0000 – 83FF FFFF

Controls EMIFA CE0 range 8400 0000 – 84FF FFFF

Controls EMIFA CE0 range 8500 0000 – 85FF FFFF

Controls EMIFA CE0 range 8600 0000 – 86FF FFFF

Controls EMIFA CE0 range 8700 0000 – 87FF FFFF

Controls EMIFA CE0 range 8800 0000 – 88FF FFFF

Controls EMIFA CE0 range 8900 0000 – 89FF FFFF

Controls EMIFA CE0 range 8A00 0000 – 8AFF FFFF

Controls EMIFA CE0 range 8B00 0000 – 8BFF FFFF

Controls EMIFA CE0 range 8C00 0000 – 8CFF FFFF

Controls EMIFA CE0 range 8D00 0000 – 8DFF FFFF

Controls EMIFA CE0 range 8E00 0000 – 8EFF FFFF

Controls EMIFA CE0 range 8F00 0000 – 8FFF FFFF

10

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-2. L2 Cache Registers (C64x) (continued)

HEX ADDRESS RANGE

0184 8240

0184 8244

0184 8248

0184 824C

0184 8250

0184 8254

0184 8258

0184 825C

0184 8260

0184 8264

0184 8268

0184 826C

0184 8270

0184 8274

0184 8278

0184 827C

0184 8280

0184 8284

0184 8288

0184 828C

0184 8290

0184 8294

0184 8298

0184 829C

0184 82A0

0184 82A4

0184 82A8

0184 82AC

0184 82B0

0184 82B4

0184 82B8

0184 82BC

0184 82C0

0184 82C4

0184 82C8

0184 82CC

0184 82D0

0184 82D4

0184 82D8

0184 82DC

0184 82E0

0184 82E4

0184 82E8

0184 82EC

0184 82F0

0184 82F4

0184 82F8

ACRONYM

REGISTER NAME

COMMENTS

MAR144

MAR145

MAR146

MAR147

MAR148

MAR149

MAR150

MAR151

MAR152

MAR153

MAR154

MAR155

MAR156

MAR157

MAR158

MAR159

MAR160

MAR161

MAR162

MAR163

MAR164

MAR165

MAR166

MAR167

MAR168

MAR169

MAR170

MAR171

MAR172

MAR173

MAR174

MAR175

MAR176

MAR177

MAR178

MAR179

MAR180

MAR181

MAR182

MAR183

MAR184

MAR185

MAR186

MAR187

MAR188

MAR189

MAR190

Controls EMIFA CE1 range 9000 0000 – 90FF FFFF

Controls EMIFA CE1 range 9100 0000 – 91FF FFFF

Controls EMIFA CE1 range 9200 0000 – 92FF FFFF

Controls EMIFA CE1 range 9300 0000 – 93FF FFFF

Controls EMIFA CE1 range 9400 0000 – 94FF FFFF

Controls EMIFA CE1 range 9500 0000 – 95FF FFFF

Controls EMIFA CE1 range 9600 0000 – 96FF FFFF

Controls EMIFA CE1 range 9700 0000 – 97FF FFFF

Controls EMIFA CE1 range 9800 0000 – 98FF FFFF

Controls EMIFA CE1 range 9900 0000 – 99FF FFFF

Controls EMIFA CE1 range 9A00 0000 – 9AFF FFFF

Controls EMIFA CE1 range 9B00 0000 – 9BFF FFFF

Controls EMIFA CE1 range 9C00 0000 – 9CFF FFFF

Controls EMIFA CE1 range 9D00 0000 – 9DFF FFFF

Controls EMIFA CE1 range 9E00 0000 – 9EFF FFFF

Controls EMIFA CE1 range 9F00 0000 – 9FFF FFFF

Controls EMIFA CE2 range A000 0000 – A0FF FFFF

Controls EMIFA CE2 range A100 0000 – A1FF FFFF

Controls EMIFA CE2 range A200 0000 – A2FF FFFF

Controls EMIFA CE2 range A300 0000 – A3FF FFFF

Controls EMIFA CE2 range A400 0000 – A4FF FFFF

Controls EMIFA CE2 range A500 0000 – A5FF FFFF

Controls EMIFA CE2 range A600 0000 – A6FF FFFF

Controls EMIFA CE2 range A700 0000 – A7FF FFFF

Controls EMIFA CE2 range A800 0000 – A8FF FFFF

Controls EMIFA CE2 range A900 0000 – A9FF FFFF

Controls EMIFA CE2 range AA00 0000 – AAFF FFFF

Controls EMIFA CE2 range AB00 0000 – ABFF FFFF

Controls EMIFA CE2 range AC00 0000 – ACFF FFFF

Controls EMIFA CE2 range AD00 0000 – ADFF FFFF

Controls EMIFA CE2 range AE00 0000 – AEFF FFFF

Controls EMIFA CE2 range AF00 0000 – AFFF FFFF

Controls EMIFA CE3 range B000 0000 – B0FF FFFF

Controls EMIFA CE3 range B100 0000 – B1FF FFFF

Controls EMIFA CE3 range B200 0000 – B2FF FFFF

Controls EMIFA CE3 range B300 0000 – B3FF FFFF

Controls EMIFA CE3 range B400 0000 – B4FF FFFF

Controls EMIFA CE3 range B500 0000 – B5FF FFFF

Controls EMIFA CE3 range B600 0000 – B6FF FFFF

Controls EMIFA CE3 range B700 0000 – B7FF FFFF

Controls EMIFA CE3 range B800 0000 – B8FF FFFF

Controls EMIFA CE3 range B900 0000 – B9FF FFFF

Controls EMIFA CE3 range BA00 0000 – BAFF FFFF

Controls EMIFA CE3 range BB00 0000 – BBFF FFFF

Controls EMIFA CE3 range BC00 0000 – BCFF FFFF

Controls EMIFA CE3 range BD00 0000 – BDFF FFFF

Controls EMIFA CE3 range BE00 0000 – BEFF FFFF

Device Overview

11

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-2. L2 Cache Registers (C64x) (continued)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

0184 82FC

MAR191

Controls EMIFA CE3 range BF00 0000 – BFFF FFFF

MAR192 to

MAR255

0184 8300 – 0184 83FC

0184 8400 – 0187 FFFF

Reserved

–

12

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.3 Memory Map Summary

Table 2-3 shows the memory map address ranges of the DM642 device. Internal memory is always

located at address 0 and can be used as both program and data memory. The external memory address

ranges in the DM642 device begin at the hex address location 0x8000 0000 for EMIFA.

Table 2-3. TMS320DM642 Memory Map Summary

BLOCK SIZE

MEMORY BLOCK DESCRIPTION

Internal RAM (L2)

HEX ADDRESS RANGE

(BYTES)

256K

768K

23M

0000 0000 – 0003 FFFF

0004 0000 – 000F FFFF

0010 0000 – 017F FFFF

0180 0000 – 0183 FFFF

0184 0000 – 0187 FFFF

0188 0000 – 018B FFFF

018C 0000 – 018F FFFF

0190 0000 – 0193 FFFF

0194 0000 – 0197 FFFF

0198 0000 – 019B FFFF

019C 0000 – 019F FFFF

01A0 0000 – 01A3 FFFF

01A4 0000 – 01AB FFFF

01AC 0000 – 01AF FFFF

01B0 0000 – 01B3 EFFF

01B3 F000 – 01B3 FFFF

01B4 0000 – 01B4 3FFF

01B4 4000 – 01B4 BFFF

01B4 C000 – 01B4 FFFF

01B5 0000 – 01B7 FFFF

01B8 0000 – 01BB FFFF

01BC 0000 – 01BF FFFF

01C0 0000 – 01C3 FFFF

01C4 0000 – 01C4 3FFF

01C4 4000 – 01C4 7FFF

01C4 8000 – 01C4 BFFF

01C4 C000 – 01C4 FFFF

01C5 0000 – 01C7 FFFF

01C8 0000 – 01C8 0FFF

01C8 1000 – 01C8 2FFF

01C8 3000 – 01C8 37FF

01C8 3800 – 01C8 3FFF

01C8 4000 – 01FF FFFF

0200 0000 – 0200 0033

0200 0034 – 2FFF FFFF

3000 0000 – 33FF FFFF

3400 0000 – 37FF FFFF

3800 0000 – 3BFF FFFF

3C00 0000 – 3C0F FFFF

3C10 0000 – 3FFF FFFF

Reserved

External Memory Interface A (EMIFA) Registers

L2 Registers

256K

512K

256K

256K – 4K

4K

HPI Registers

McBSP 0 Registers

McBSP 1 Registers

Timer 0 Registers

Timer 1 Registers

Interrupt Selector Registers

EDMA RAM and EDMA Registers

Reserved

Timer 2 Registers

GP0 Registers

Device Configuration Registers

I2C0 Data and Control Registers

Reserved

16K

32K

McASP0 Control Registers

Reserved

16K

192K

256K

16K

Reserved

Emulation

PCI Registers

VP0 Control

VP1 Control

16K

VP2 Control

16K

VIC Control

16K

Reserved

192K

4K

EMAC Control

EMAC Wrapper

EWRAP Registers

MDIO Control Registers

Reserved

8K

2K

3.5M

52

QDMA Registers

Reserved

928M – 52

64M

McBSP 0 Data

McBSP 1 Data

64M

Reserved

64M

McASP0 Data

1M

Reserved

64M – 1M

Device Overview

13

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-3. TMS320DM642 Memory Map Summary (continued)

BLOCK SIZE

(BYTES)

MEMORY BLOCK DESCRIPTION

HEX ADDRESS RANGE

Reserved

832M

32M

256M

1G

4000 0000 – 73FF FFFF

7400 0000 – 75FF FFFF

7600 0000 – 77FF FFFF

7800 0000 – 79FF FFFF

7A00 0000 – 7BFF FFFF

7C00 0000 – 7DFF FFFF

7E00 0000 – 7FFF FFFF

8000 0000 – 8FFF FFFF

9000 0000 – 9FFF FFFF

A000 0000 – AFFF FFFF

B000 0000 – BFFF FFFF

C000 0000 – FFFF FFFF

VP0 Channel A Data

VP0 Channel B Data

VP1 Channel A Data

VP1 Channel B Data

VP2 Channel A Data

VP2 Channel B Data

EMIFA CE0

EMIFA CE1

EMIFA CE2

EMIFA CE3

Reserved

14

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.3.1 L2 Architecture Expanded

Figure 2-2 shows the detail of the L2 architecture on the TMS320DM642 device. For more information on

the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x

Two-Level Internal Memory Reference Guide (literature number SPRU610).

L2MODE

010

L2 Memory

Block Base Address

000

001

011

111

0x0000 0000

128K-Byte SRAM

0x0002 0000

64K-Byte RAM

0x0003 0000

0x0003 8000

32K-Byte RAM

0x0003 FFFF

0x0004 0000

Figure 2-2. TMS320DM642 L2 Architecture Memory Configuration

Device Overview

15

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.4 Bootmode

The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in

reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics

and states of device pins during reset. The release of RESET starts the processor running with the

prescribed device configuration and boot mode.

The DM642 has three types of boot modes:

•

Host boot

If host boot is selected, upon release of RESET, the CPU is internally "stalled" while the remainder of

the device is released. During this period, an external host can initialize the CPU's memory space as

necessary through the host interface, including internal configuration registers, such as those that

control the EMIF or other peripherals. For the DM642 device, the HPI peripheral is used for host boot if

PCI_EN = 0, and the PCI peripheral is used if PCI_EN = 1. Once the host is finished with all necessary

initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This

transition causes the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then

begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs

while the CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if

the host boot process is selected. All memory may be written to and read by the host. This allows for

the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the

CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.

•

EMIF boot (using default ROM timings)

Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to

address 0 by the EDMA using the default ROM timings, while the CPU is internally "stalled". The data

should be stored in the endian format that the system is using. In this case, the EMIF automatically

assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is

automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After

completion of the block transfer, the CPU is released from the "stalled" state and starts running from

address 0.

•

No boot

With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation

is undefined if invalid code is located at address 0.

2.5 Pin Assignments

16

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.5.1 Pin Map

Figure 2-3 through Figure 2-6 show the DM642 pin assignments in four quadrants (A, B, C, and D).

1

2

3

4

5

6

7

8

9

10

11

12

13

AF

AE

AD

AC

AB

AA

Y

V

DV

RSV

VP1CTL0

VP1D[0]

V

VP1CLK0

VP1CLK1

V

VP0CLK1

V

SS

VP1D[1]

SS

DD

SS

V

SS

VP1D[2]/

CLKX1

VP1D[5]/

CLKS1

VP1D[15]/

AXR0[3]

DV

V

VP1CTL1

VP1CTL2

V

VP1D[10]

VP1D[11]

V

DV

DD

CLKMODE1

DD

SS

VDAC/

GP0[8]/

PCI66

VP1D[3]/

FSX1

VP1D[6]/

DR1

VP1D[8]/

CLKR1

VP1D[13]/

AXR0[1]

VP1D[16]/

AXR0[4]

VP0D[18]/

AFSX0

VP0D[15]/

AMUTEIN0

V

RSV

V

SS

VP1D[4]/

DX1

VP1D[7]/

FSR1

VP1D[12]/

AXR0[0]

VP1D[14]/

AXR0[2]

VP1D[17]/

AXR0[5]

VP0D[19]/

AHCLKX0

VP0D[16]/

AMUTE0

STCLK

CLKIN

V

RSV

V

VP1D[9]

SS

VP1D[18]/

AXR0[6]

VP1D[19]/

AXR0[7]

VP0D[17]/

ACLKX0

V

RSV

V

DV

V

DV

CV

DV

V

DV

DD

SS

DD

SS

DD

SS

HD1/

AD1

CLKMODE0

V

CV

V

DV

V

DV

V

SS

DD

SS

DD

SS

DD

HD5/

AD5

HD3/

AD3

HD0/

AD0

HD2/

AD2

DV

CV

V

CV

V

CV

DD

SS

DD

SS

HD7/

AD7

HD4/

AD4

HD6/

AD6

W

V

RSV

SS

HD10/

AD10

HD8/

AD8

HD9/

AD9

V

PLLV

V

SS

PCBE0

HD14/

AD14

HD12/

AD12

HD13/

AD13

HD11/

AD11

U

DV

V

CV

DD

SS

DD

HDS2/

PCBE1

HD15/

AD15

T

V

XSP_CS

XSP_DI

V

SS

HCS/

PPERR

HDS1/

PSERR

XSP_CLK/

MDCLK

HCNTL0/

PSTOP

R

RSV

V

CV

DD

SS

HCNTL1/

PDEVSEL

HAS/

PPAR

XSP_DO/

MDIO

P

V

RESET

4

V

CV

V

SS

DD

1

2

3

5

6

7

8

9

10

11

12

13

Figure 2-3. DM642 Pin Map [Quadrant A]

Device Overview

17

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

14

15

16

17

18

19

20

21

22

23

24

25

26

VP0D[3]/

FSX0

VP0D[2]/

CLKX0

AF

VP0CLK0

V

VP0D[0]

V

AED50

AED54

V

AED62

AED63

DV

V

SS

DD

VP0D[8]/

CLKR0

VP0D[4]/

DX0

AE

AD

AC

AB

AA

Y

V

VP0CTL0

VP0CTL2

VP0CTL1

VP0D[1]

V

AED52

AED53

AED51

AED56

AED57

AED55

AED58

AED59

AED61

AED60

V

DV

DD

SS

VP0D[12]/

ACLKR0

VP0D[5]/

CLKS0

VP0D[9]

VP0D[10]

VP0D[11]

V

AED48

AED49

DV

AED33

AED34

AED37

AED40

AED44

AED32

AED35

SS

DD

VP0D[13]/

AFSR0

VP0D[6]/

DR0

V

DV

V

SS

DD

VP0D[14]/

AHCLKR0

VP0D[7]/

FSR0

DV

CV

V

DV

AED38

AED41

AED45

AED47

AEA18

AEA22

ABE6

AED36

AED39

AED43

AHOLD

AEA21

AEA17

AEA14

AEA11

V

SS

DD

SS

DD

DV

V

DV

V

CV

V

SS

AED42

AED46

DD

SS

DD

SS

DD

V

SS

CV

V

CV

V

CV

DV

DD

SS

DD

SS

DD

W

V

DV

V

SS

DD

V

DV

V

SS

AEA20

AEA16

AEA13

ABE5

AEA19

AEA15

SS

DD

U

CV

V

DV

DD

SS

T

ABE7

V

SS

R

V

CV

V

DV

DD

ASOE3

AEA12

ABE4

SS

DD

SS

P

CV

V

CV

V

ABUSREQ

22

AEA10

23

AEA9

24

DV

DD

AEA8

26

DD

SS

DD

SS

14

15

16

17

18

19

20

21

25

Figure 2-4. DM642 Pin Map [Quadrant B]

18

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

1

2

3

4

5

6

7

8

9

10

11

12

13

HRDY/

PIRDY

HHWIL/

PTRDY

HINT/

PFRAME

N

M

L

DV

V

CV

V

CV

DD

SS

DD

SS

HD17/

AD17/

MTXD1

HD16/

AD16/

MTXD0

HD18/

AD18/

MTXD2

HR/W/

PCBE2

GP0[0]

DV

V

CV

V

SS

DD

SS

DD

HD19/

AD19/

MTXD3

HD20/

AD20/

MTXEN

HD22/

AD22/

MTCLK

GP0[3]/

PCIEEAI

V

CV

SS

DD

HD21/

AD21/

MCOL

HD24/

AD24/

MRXD0

HD23/

AD23

GP0[9]/

PIDSEL

K

J

DV

DD

SS

HD25/

AD25/

MRXD1

HD26/

AD26/

MRXD2

HD28/

AD28/

MRXDV

GP0[10]/

PCBE3

V

DV

V

SS

DD

HD27/

AD27/

MRXD3

HD30/

AD30/

MCRS

GP0[12]/

PGNT

H

G

F

V

DV

V

SS

RSV

SS

DD

HD31/

AD31/

MRCLK

HD29/

AD29/

MRXER

GP0[15]/

PRST

GP0[13]/

PINTA

CV

DV

CV

V

CV

V

CV

DD

SS

DD

SS

GP0[11]/

PREQ

GP0[6]/

GP0[5]/

GP0[4]/

V

DV

V

DV

V

SS

DD

SS

DD

EXT_INT6 EXT_INT5 EXT_INT4

GP0[7]/

EXT_INT7

E

D

C

B

A

PCI_EN

V

SCL0

DV

V

DV

V

DV

DD

VP2D[14]

VP2D[13]

VP2D[12]

VP2D[11]

VP2D[18]

VP2D[17]

VP2D[16]

VP2D[15]

VP2D[19]

SS

DD

SS

DD

SS

CLKOUT4/

GP0[1]

V

SDA0

DV

V

VP2CTL1

VP2CTL2

VP2D[1]

VP2D[0]

VP2CTL0

VP2D[5]

VP2D[4]

VP2D[3]

VP2D[9]

VP2D[8]

VP2D[7]

V

SS

DD

SS

GP0[14]/

PCLK

TOUT0/

MAC_EN

CLKOUT6/

GP0[2]

DV

V

SS

DD

TOUT1/

LENDIAN

DV

V

NMI

V

SS

DD

SS

V

TINP0

4

TINP1

5

VP2CLK0

V

VP2D[2]

9

VP2D[6]

10

VP2D[10]

11

V

SS

VP2CLK1

13

SS

1

2

3

6

7

8

12

Figure 2-5. DM642 Pin Map [Quadrant C]

Device Overview

19

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

14

15

16

17

18

19

20

21

22

23

24

25

26

N

M

L

V

CV

V

AHOLDA

AEA7

AEA6

V

SS

AEA5

SS

DD

SS

CV

V

DV

DD

APDT

AEA4

ABE1

ACE2

AEA3

ABE0

ABE3

ASDCKE

ACE0

ABE2

ACE3

DD

SS

CV

V

AARDY

DD

SS

AAWE/

ASDWE/

ASWE

K

J

DV

ACE1

SS

DD

AARE/

ASDCAS/

ASADS/

ASRE

AAOE/

AECLKOUT2 ASDRAS/

ASOE

V

DV

V

SS

AECLKOUT1

SS

DD

H

G

F

CV

DV

V

DV

AED17

AED19

AED23

AED16

AED21

AED25

AED27

AECLKIN

AED20

AED24

AED26

AED28

AED30

V

SS

DD

SS

DD

CV

V

CV

V

CV

AED18

AED22

DD

SS

DD

SS

DD

V

DV

V

DV

V

SS

DD

SS

DD

SS

E

D

C

B

A

RSV

TRST

EMU1

TMS

DV

V

DV

V

DV

V

SS

DD

SS

DD

SS

DD

SS

EMU4

EMU3

EMU2

EMU8

EMU6

EMU5

EMU11

EMU10

EMU9

AED14

AED15

AED12

AED10

AED11

AED8

AED6

AED7

V

DV

V

SS

AED29

AED31

SS

DD

AED4

AED3

V

DV

DD

SS

DV

TDO

V

AED2

AED0

DV

DD

SS

DD

V

EMU0

15

TCK

16

EMU7

17

TDI

18

AED13

20

AED9

21

V

AED5

23

AED1

24

V

SS

22

DD

25

14

19

26

Figure 2-6. DM642 Pin Map [Quadrant D]

20

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.5.2 Signal Groups Description

RESET

NMI

CLKIN

CLKOUT4/GP0[1]

(A)

(B)

GP0[7]/EXT_INT7

GP0[6]/EXT_INT6

GP0[5]/EXT_INT5

GP0[4]/EXT_INT4

Reset and

Interrupts

(B)

(A)

CLKOUT6/GP0[2]

Clock/PLL

CLKMODE1

CLKMODE0

PLLV

RSV08

RSV07

RSV06

RSV05

RSV04

RSV03

RSV02

RSV01

RSV00

TMS

TDO

TDI

TCK

TRST

EMU0

EMU1

EMU2

EMU3

EMU4

EMU5

EMU6

EMU7

EMU8

EMU9

EMU10

EMU11

Reserved

IEEE Standard

1149.1

(JTAG)

Emulation

PCI_EN

TOUT0/MAC_EN

Peripheral

Control/Status

(C)

GP0[15]/PRST

GP0[14]/PCLK

(B)

GP0[7]/EXT_INT7

GP0[6]/EXT_INT6

GP0[5]/EXT_INT5

GP0[4]/EXT_INT4

GP0[3]/PCIEEAI

(C)

(B)

(C)

GP0[13]/PINTA

(C)

GP0[12]/PGNT

GP0

(C)

GP0[11]/PREQ

(A)

CLKOUT6/GP0[2]

CLKOUT4/GP0[1]

GP0[0]

(C)

GP0[10]/PCBE3

GP0[9]/PIDSEL

(A)

(C)

VDAC/GP0[8]/PCI66

General-Purpose Input/Output 0 (GP0) Port

A. These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6).

To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly

enabled and configured. For more details, see the Device Configurations section of this data sheet.

B. These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is

EXT_INTx or GPIO as input-only.

C. These GP0 pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with

both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations

section of this data sheet.

Figure 2-7. CPU and Peripheral Signals

Device Overview

21

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

64

Data

AED[63:0]

AECLKIN

AECLKOUT1

AECLKOUT2

ASDCKE

ACE3

ACE2

Memory Map

Space Select

External

Memory I/F

Control

AARE/ASDCAS/ASADS/ASRE

ACE1

ACE0

AAOE/ASDRAS/ASOE

AAWE/ASDWE/ASWE

AARDY

20

Address

AEA[22:3]

ASOE3

ABE7

ABE6

ABE5

ABE4

ABE3

ABE2

ABE1

ABE0

APDT

Byte Enables

AHOLD

Bus

Arbitration

AHOLDA

ABUSREQ

EMIFA (64-bit)

Data

VDAC/GP0[8]/PCI66

VCXO Interpolated

Control Port (VIC)

Figure 2-8. EMIFA/VIC Peripheral Signals

22

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

(A)

HPI

32

(Host-Port Interface)

Data

HD[15:0]/AD[15:0]

(C)

HD[31:16]/AD[31:16]

HAS/PPAR

HR/W/PCBE2

HCS/PPERR

HDS1/PSERR

HDS2/PCBE1

HRDY/PIRDY

HCNTL0/PSTOP

HCNTL1/PDEVSEL

Register Select

Control

Half-Word

Select

HHWIL/PTRDY

(HPI16 ONLY)

HINT/PFRAME

32

HD[15:0]/AD[15:0]

Data/Address

Clock

GP0[14]/PCLK

(C)

HD[31:16]/AD[31:16]

GP0[9]/PIDSEL

HCNTL1/PDEVSEL

HINT/PFRAME

GP0[13]/PINTA

HAS/PPAR

GP0[15]/PRST

HRDY/PIRDY

GP0[10]/PCBE3

HR/W/PCBE2

HDS2/PCBE1

PCBE0

Command

Byte Enable

Control

HCNTL0/PSTOP

HHWIL/PTRDY

GP0[12]/PGNT

GP0[11]/PREQ

Arbitration

HDS1/PSERR

HCS/PPERR

Error

XSP_DO/MDIO

XSP_CS

Serial

EEPROM

XSP_CLK/MDCLK

XSP_DI

(B)

PCI Interface

A. These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on

these muxed pins, see the Device Configurations section of this data sheet.

B. These PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI or MDIO or GP0 peripherals. By default,

these signals function as HPI and no function, respectively. For more details on these muxed pins, see the Device

Configurations section of this data sheet.

C. These HPI/PCI data pins (HD[31:16/AD[31:16]) are muxed with the EMAC peripheral. By default, these pins function

as HPI. For more details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral signals section and

the terminal functions table portions of this data sheet.

Figure 2-9. HPI/PCI Peripheral Signals

Device Overview

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

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SPRS200J–JULY 2002–REVISED AUGUST 2005

McBSP1

McBSP0

Transmit

(A)

VP0D[2]/CLKX0

VP1D[2]/CLKX1

(A)

Transmit

VP0D[3]/FSX0

VP1D[3]/FSX1

VP1D[4]/DX1

(A)

VP0D[4]/DX0

(A)

VP1D[8]/CLKR1

VP1D[7]/FSR1

VP1D[6]/DR1

VP0D[8]/CLKR0

VP0D[7]/FSR0

(A)

Receive

Clock

Receive

Clock

(A)

VP0D[6]/DR0

(A)

VP0D[5]/CLKS0

VP1D[5]/CLKS1

McBSPs

(Multichannel Buffered

Serial Ports)

TOUT1/LENDIAN

TINP1

TOUT0/MACEN

TINP0

Timer 0

Timers

Timer 1

Timer 2

SCL0

SDA0

I2C0

A. These McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals,

respectively. By default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins,

see the Device Configurations section of this data sheet.

Figure 2-10. McBSP/Timer/I2C0 Peripheral Signals

24

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

EMAC

(A)

HD16/AD16/MTXD0

HD17/AD17/MTXD1

Transmit

(A)

HD18/AD18/MTXD2

HD19/AD19/MTXD3

(A)

MDIO

(A)

HD24/AD24/MRXD0

(A)

HD25/AD25/MRXD1

HD26/AD26/MRXD2

HD27/AD27/MRXD3

(B)

Receive

XSP_DO/MDIO

Input/Output

Clock

(A)

HD20/AD20/MTXEN

(B)

XSP_CLK/MDCLK

(A)

HD29/AD29/MRXER

HD28/AD28/MRXDV

HD21/AD21/MCOL

HD30/AD30/MCRS

Error Detect

and Control

(A)

HD22/AD22/MTCLK

HD31/AD31/MRCLK

Clocks

(A)

Ethernet MAC (EMAC)

and MDIO

A. These EMAC pins are muxed with the upper data pins of the HPI or PCI peripherals. By default, these signals

function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet.

B. These MDIO pins are muxed with the PCI peripherals. By default, these signals function as PCI. For more details on

these muxed pins, see the Device Configurations section of this data sheet.

Figure 2-11. EMAC/MDIO Peripheral Signals

Device Overview

25

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

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SPRS200J–JULY 2002–REVISED AUGUST 2005

(C)

STCLK

VP0CLK0

VP0CLK1

VP0CTL0

VP0CTL1

VP0CTL2

Timing and

Control Logic

VP0D[0]

VP0D[1]

VP0D[10]

VP0D[11]

VP0D[2]/CLKX0

VP0D[12]/ACLKR0

VP0D[13]/AFSR0

VP0D[3]/FSX0

Capture/Display

VP0D[4]/DX0

Buffer

VP0D[14]/AHCLKR0

VP0D[15]/AMUTEIN0

VP0D[16]/AMUTE0

VP0D[17]/ACLKX0

VP0D[18]/AFSX0

VP0D[5]/CLKS0

(2560 Bytes)

VP0D[6]/DR0

VP0D[7]/FSR0

VP0D[8]/CLKR0

VP0D[9]

VP0D[19]/AHCLKX0

(A)

Channel A

Channel B uses only

the VP0D[19:10]

bidirectional pins

Capture/Display

Buffer

(2560 Bytes)

(B)

Channel B

Video Port 0 (VP0)

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-12. Video Port 0 Peripheral Signals

26

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

(C)

STCLK

VP1CLK0

VP1CLK1

VP1CTL0

VP1CTL1

VP1CTL2

Timing and

Control Logic

VP1D[0]

VP1D[1]

VP1D[10]

VP1D[11]

VP1D[2]/CLKX1

VP1D[3]/FSX1

VP1D[4]/DX1

VP1D[5]/CLKS1

VP1D[6]/DR1

VP1D[7]/FSR1

VP1D[8]/CLKR1

VP1D[9]

VP1D[12]/AXR0[0]

VP1D[13]/AXR0[1]

VP1D[14]/AXR0[2]

VP1D[15]/AXR0[3]

VP1D[16]/AXR0[4]

VP1D[17]/AXR0[5]

VP1D[18]/AXR0[6]

VP1D[19]/AXR0[7]

Capture/Display

Buffer

(2560 Bytes)

(A)

Channel A

Channel B uses only

the VP1D[19:10]

bidirectional pins

Capture/Display

Buffer

(2560 Bytes)

(B)

Channel B

Video Port 1 (VP1)

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-13. Video Port 1 Peripheral Signals

Device Overview

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

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SPRS200J–JULY 2002–REVISED AUGUST 2005

(C)

STCLK

VP2CLK0

VP2CLK1

VP2CTL0

VP2CTL1

VP2CTL2

Timing and

Control Logic

VP2D[0]

VP2D[1]

VP2D[2]

VP2D[10]

VP2D[11]

VP2D[12]

VP2D[13]

VP2D[14]

VP2D[15]

VP2D[16]

VP2D[17]

VP2D[18]

VP2D[19]

VP2D[3]

Capture/Display

VP2D[4]

Buffer

(2560 Bytes)

VP2D[5]

VP2D[6]

VP2D[7]

VP2D[8]

VP2D[9]

(A)

Channel A

Channel B uses only

the VP2D[19:10]

bidirectional pins

Capture/Display

Buffer

(2560 Bytes)

(B)

Channel B

Video Port 2 (VP2)

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-14. Video Port 2 Peripheral Signals

28

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

(Transmit/Receive Data Pins)

VP1D[12]/AXR0[0]

VP1D[13]/AXR0[1]

VP1D[14]/AXR0[2]

VP1D[15]/AXR0[3]

VP1D[16]/AXR0[4]

VP1D[17]/AXR0[5]

VP1D[18]/AXR0[6]

VP1D[19]/AXR0[7]

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

(Transmit Bit Clock)

(Receive Bit Clock)

Transmit

Clock

Generator

VP0D[17]/ACLKX0

VP0D[19]/AHCLKX0

Receive Clock

Generator

VP0D[12]/ACLKR0

VP0D[14]/AHCLKR0

(Receive Master Clock)

(Transmit Master Clock)

Transmit

Clock Check

Circuit

Receive Clock

Check Circuit

Receive Frame

Sync

Transmit

Frame Sync

VP0D[13]/AFSR0

VP0D[18]/AFSX0

(Receive Frame Sync or

Left/Right Clock)

(Transmit Frame Sync or

Left/Right Clock)

VP0D[16]/AMUTE0

VP0D[15]/AMUTEIN0

Auto Mute

Logic

(A)

Error Detect

McASP0

(Multichannel Audio Serial Port 0)

NOTES:

On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Bolded and Italicized text within parentheses denotes the function of the pins in an audio system.

A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external

mute input.

Figure 2-15. McASP0 Peripheral Signals

2.5.3 Terminal Functions

Table 2-4, the terminal functions table, identifies the external signal names, the associated pin (ball)

numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin

has any internal pullup/pulldown resistors and a functional pin description. For more detailed information

on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see

the Device Configurations section of this data sheet.

Device Overview

29

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

CLOCK/PLL CONFIGURATION

Clock Input. This clock is the input to the on-chip PLL.

CLKIN

AC2

D6

I

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be

programmed as a GP0 1 pin (I/O/Z).

CLKOUT4/GP0[1]⁽³⁾

I/O/Z

IPU

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be

programmed as a GP0 2 pin (I/O/Z).

CLKOUT6/GP0[2]⁽³⁾

CLKMODE1

C6

I/O/Z

I

IPU

IPD

AE4

Clock mode select

•

Selects whether the CPU clock frequency = input clock frequency x1

(Bypass), x6, or x12.

CLKMODE0

PLLV⁽⁴⁾

AA2

V6

I

IPD

For more details on the CLKMODE pins and the PLL multiply factors, see

the Clock PLL section of this data sheet.

A⁽¹⁾

PLL voltage supply

JTAG EMULATION

TMS

TDO

TDI

E15

B18

A18

A16

I

IPU

JTAG test-port mode select

JTAG test-port data out

JTAG test-port data in

JTAG test-port clock

O/Z

I

TCK

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

JTAG compatibility statement portion of this data sheet.

TRST

D14

I

IPD

EMU11

EMU10

EMU9

EMU8

EMU7

EMU6

EMU5

EMU4

EMU3

EMU2

EMU1

EMU0

D17

C17

B17

D16

A17

C16

B16

D15

C15

B15

C14

A15

I/O/Z

IPU

Emulation pin 11. Reserved for future use, leave unconnected.

Emulation pin 10. Reserved for future use, leave unconnected.

Emulation pin 9. Reserved for future use, leave unconnected.

Emulation pin 8. Reserved for future use, leave unconnected.

Emulation pin 7. Reserved for future use, leave unconnected.

Emulation pin 6. Reserved for future use, leave unconnected.

Emulation pin 5. Reserved for future use, leave unconnected.

Emulation pin 4. Reserved for future use, leave unconnected.

Emulation pin 3. Reserved for future use, leave unconnected.

Emulation pin 2. Reserved for future use, leave unconnected.

(5)

Emulation pin 1

(5)

Emulation pin 0

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET

NMI

P4

B4

I

Device reset

Nonmaskable interrupt, edge-driven (rising edge)

Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the

NMI pin is not used, it is recommended that the NMI pin be grounded versus

relying on the IPD.

IPD

GP0[7]/EXT_INT7

GP0[6]/EXT_INT6

GP0[5]/EXT_INT5

E1

F2

F3

I/O/Z

IPU

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input

only). The default after reset setting is GPIO enabled as input-only.

•

When these pins function as External Interrupts [by selecting the

corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven

and the polarity can be independently selected via the External Interrupt

Polarity Register bits (EXTPOL.[3:0]).

GP0[4]/EXT_INT4

F4

I/O/Z

IPU

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the

opposite supply rail, a 1-kΩ resistor should be used.)

(3) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

(4) PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.

(5) The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external

pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated

1-kΩ resistor.

30

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NAME

NO.

G3

C1

G4

H4

F1

GP0[15]/PRST⁽³⁾

GP0[14]/PCLK⁽³⁾

GP0[13]/PINTA⁽³⁾

GP0[12]/PGNT⁽³⁾

GP0[11]/PREQ⁽³⁾

GP0[10]/PCBE3⁽³⁾

GP0[9]/PIDSEL⁽³⁾

General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I).

GP0 14 pin (I/O/Z) or PCI clock (I)

GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z)

GP0 12 pin (I/O/Z) or PCI bus grant (I)

GP0 11 pin (I/O/Z) or PCI bus request (O/Z)

GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z)

GP0 9 pin (I/O/Z) or PCI initialization device select (I)

I/O/Z

J2

Note: By default, no function is enabled upon reset. To configure these pins, see

the Device Configuration section of this data sheet.

K3

GP0 3 pin (I/O/Z)

Boot Configuration: PCI EEPROM Auto-Initialization (EEAI).

GP0[3]

L5

IPD

0 - PCI auto-initialization through EEPROM is disabled (default).

1 - PCI auto-initialization through EEPROM is enabled.

General-purpose 0 pin (GP0[0]) (I/O/Z) [default]

This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0]

(output only) pin or output as a general-purpose interrupt (GP0INT) signal

(output only).

GP0[0]

M5

I/O/Z

Note: This pin must remain low during device reset.

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter

(VDAC) output [output only] [default] or this pin can be programmed as a GP0 8

pin (I/O/Z)

Boot Configuration: PCI frequency selection (PCI66).

If the PCI peripheral is enabled (PCI_EN pin = 1), then:

0 - PCI operates at 66 MHz (default).

1 - PCI operates at 33 MHz.

VDAC/GP0[8]/PCI66⁽³⁾

AD1

I/O/Z

IPD

The –500 device supports PCI at 33 MHz only. For proper –500 device operation

when the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up

with a 1-kΩ resistor at device reset.

Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin be must not

pulled up.

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be

programmed as a GP0 2 pin (I/O/Z).

CLKOUT6/GP0[2]⁽³⁾

CLKOUT4/GP0[1]⁽³⁾

C6

D6

I/O/Z

IPU

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be

programmed as a GP0 1 pin (I/O/Z).

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or EMAC

Boot Configuration: PCI enable pin (I)

The PCI_EN pin and the MAC_EN pin control the selection (enable/disable) of

PCI_EN

E2

I

IPD

the HPI, EMAC, MDIO, and GP0[15:8], or PCI peripherals. The pins work in

conjunction to enable/disable these peripherals (for more details, see the Device

Configurations section of this data sheet).

HINT/PFRAME⁽³⁾

N4

P1

I/O/Z

Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)

Host control – selects between control, address, or data registers (I) [default] or

PCI device select (I/O/Z).

HCNTL1/PDEVSEL⁽³⁾

Host control – selects between control, address, or data registers (I) [default] or

PCI stop (I/O/Z)

HCNTL0/PSTOP⁽³⁾

HHWIL/PTRDY⁽³⁾

R3

N3

I/O/Z

Host half-word select – first or second half-word (not necessarily high or low

order)

[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)

HR/W/PCBE2⁽³⁾

HAS/PPAR⁽³⁾

HCS/PPERR⁽³⁾

HDS1/PSERR⁽³⁾

M1

P3

R1

R2

I/O/Z

Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)

Host address strobe (I) [default] or PCI parity (I/O/Z)

Host chip select (I) [default] or PCI parity error (I/O/Z)

Host data strobe 1 (I) [default] or PCI system error (I/O/Z)

Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)

Note: If unused, the following HPI control signals should be externally pulled

high.

HDS2/PCBE1⁽³⁾

HRDY/PIRDY⁽³⁾

T2

N1

I/O/Z

Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).

Device Overview

31

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

G1

H3

G2

J4

HD31/AD31/MRCLK⁽³⁾

HD30/AD30/MCRS⁽³⁾

HD29/AD29/MRXER⁽³⁾

HD28/AD28/MRXDV⁽³⁾

HD27/AD27/MRXD3⁽³⁾

HD26/AD26/MRXD2⁽³⁾

HD25/AD25/MRXD1⁽³⁾

HD24/AD24/MRXD0⁽³⁾

HD23/AD23⁽³⁾

HD22/AD22/MTCLK⁽³⁾

HD21/AD21/MCOL⁽³⁾

HD20/AD20/MTXEN⁽³⁾

HD19/AD19/MTXD3⁽³⁾

HD18/AD18/MTXD2⁽³⁾

HD17/AD17/MTXD1⁽³⁾

HD16/AD16/MTXD0⁽³⁾

HD15/AD15⁽³⁾

HD14/AD14⁽³⁾

HD13/AD13⁽³⁾

HD12/AD12⁽³⁾

HD11/AD11⁽³⁾

HD10/AD10⁽³⁾

HD9/AD9⁽³⁾

HD8/AD8⁽³⁾

HD7/AD7⁽³⁾

H2

J3

J1

K4

K1

L4

Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC

transmit/receive or control pins

As HPI data bus (PCI_EN pin = 0)

K2

L3

•

Used for transfer of data, address, and control

Host-Port bus width user-configurable at device reset via a 10-kΩ resistor

pullup/pulldown resistor on the HD5 pin:

L2

As PCI data-address bus (PCI_EN pin = 1)

Used for transfer of data and address

Boot Configuration:

M4

M2

M3

T3

•

I/O/Z

•

HD5 pin = 0: HPI operates as an HPI16.

(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining

HD[31:16] pins are reserved pins in the high-impedance state.)

U1

U3

U2

U4

V1

V3

V2

W2

W4

Y1

W3

Y2

Y4

AA1

Y3

•

HD5 pin = 1: HPI operates as an HPI32.

(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)

For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can

also function as EMAC transmit/receive or control pins (when PCI_EN pin = 0;

MAC_EN pin = 1). For more details on the EMAC pin functions, see the Ethernet

MAC (EMAC) peripheral section of this table and for more details on how to

configure the EMAC pin functions, see the device configuration section of this

data sheet.

HD6/AD6⁽³⁾

HD5/AD5⁽³⁾

HD4/AD4⁽³⁾

HD3/AD3⁽³⁾

HD2/AD2⁽³⁾

HD1/AD1⁽³⁾

HD0/AD0⁽³⁾

PCI command/byte enable 0 (I/O/Z).

When PCI is disabled (PCI_EN = 0), this pin is tied-off.

PCBE0

V4

I/O/Z

PCI serial interface chip select (O).

When PCI is disabled (PCI_EN = 0), this pin is tied-off.

XSP_CS

T4

R5

R4

O

I/O/Z

I

IPD

IPU

XSP_CLK/MDCLK⁽³⁾

XSP_DI

PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z).

PCI serial interface data in (I) [default].

In PCI mode, this pin is connected to the output data pin of the serial PROM.

PCI serial interface data out (O) [default] or MDIO serial data input/output

(I/O/Z). In PCI mode, this pin is connected to the input data pin of the serial

PROM.

XSP_DO/MDIO⁽³⁾

P5

I/O/Z

IPU

32

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NAME

NO.

G3

C1

G4

H4

F1

GP0[15]/PRST⁽³⁾

GP0[14]/PCLK⁽³⁾

GP0[13]/PINTA⁽³⁾

GP0[12]/PGNT⁽³⁾

GP0[11]/PREQ⁽³⁾

GP0[10]/PCBE3⁽³⁾

GP0[9]/PIDSEL⁽³⁾

General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I).

GP0 14 pin (I/O/Z) or PCI clock (I)

GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z)

GP0 12 pin (I/O/Z) or PCI bus grant (I)

GP0 11 pin (I/O/Z) or PCI bus request (O/Z)

GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z)

GP0 9 pin (I/O/Z) or PCI initialization device select (I)

I/O/Z

J2

Note: By default, no function is enabled upon reset. To configure these pins, see

the Device Configuration section of this data sheet.

K3

GP0 3 pin (I/O/Z)

Boot Configuration: PCI EEPROM Auto-Initialization (EEAI).

0 - PCI auto-initialization through EEPROM is disabled (default).

1 - PCI auto-initialization through EEPROM is enabled

GP0[3]

L5

I/O/Z

IPD

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter

(VDAC) output [output only] [default] or this pin can be programmed as a GP0 8

pin (I/O/Z)

Boot Configuration: PCI frequency selection (PCI66).

If the PCI peripheral is enabled (PCI_EN pin = 1), then:

0 - PCI operates at 66 MHz (default).

1 - PCI operates at 33 MHz.

VDAC/GP0[8]/PCI66⁽³⁾

AD1

I/O/Z

IPD

The –500 device supports PCI at 33 MHz only. For proper –500 device operation

when the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up

with a 1-kΩ resistor at device reset.

Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be

pulled up.

EMIFA (64-bit) – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

ACE3

ACE2

ACE1

ACE0

ABE7

ABE6

ABE5

ABE4

ABE3

ABE2

ABE1

ABE0

L26

K23

K24

K25

T22

T23

R25

R26

M25

M26

L23

L24

O/Z

IPU

EMIFA memory space enables

•

Enabled by bits 28 through 31 of the word address

Only one pin is asserted during any external data access

EMIFA byte-enable control

•

Decoded from the low-order address bits. The number of address bits or

byte enables used depends on the width of external memory.

•

Byte-write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIFA peripheral data transfer, allows direct transfer between external

peripherals

APDT

M22

O/Z

IPU

EMIFA (64-bit) – BUS ARBITRATION

AHOLDA

AHOLD

N22

W24

P22

O

I

IPU

EMIFA hold-request-acknowledge to the host

EMIFA hold request from the host

EMIFA bus request output

ABUSREQ

O

Device Overview

33

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

EMIFA (64-bit) – ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or

CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the

AEA[20:19] pins.

AECLKIN

H25

I

IPD

AECLKIN is the default for the EMIFA input clock.

EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,

CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.

AECLKOUT2

AECLKOUT1

J23

J26

O/Z

IPD

EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6

clock) frequency].

EMIFA asynchronous memory read-enable/SDRAM column-address

strobe/programmable synchronous interface-address strobe or read-enable

AARE/

ASDCAS/

ASADS/ASRE

•

For programmable synchronous interface, the RENEN field in the CE Space

Secondary Control Register (CExSEC) selects between ASADS and ASRE:

If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.

If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.

J25

O/Z

IPU

AAOE/

ASDRAS/

ASOE

EMIFA asynchronous memory output-enable/SDRAM row-address

strobe/programmable synchronous interface output-enable

J24

K26

L25

O/Z

IPU

AAWE/

ASDWE/

ASWE

EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable

synchronous interface write-enable

EMIFA SDRAM clock-enable (used for self-refresh mode).

ASDCKE

•

If SDRAM is not in system, ASDCKE can be used as a general-purpose

output.

EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO

interface)

ASOE3

AARDY

R22

L22

O/Z

I

IPU

Asynchronous memory ready input

EMIFA (64-bit) – ADDRESS

AEA22

AEA21

AEA20

AEA19

AEA18

AEA17

AEA16

AEA15

AEA14

AEA13

AEA12

AEA11

AEA10

AEA9

U23

V24

V25

V26

V23

U24

U25

U26

T24

T25

R23

R24

P23

P24

P26

N23

N24

N26

M23

M24

EMIFA external address (doubleword address)

EMIFA address numbering for the DM642 device starts with AEA3 to maintain

signal name compatibility with other C64x™ devices (e.g., C6414, C6415, and

C6416) [see the 64-bit EMIF addressing scheme in the TMS320C6000 DSP

External Memory Interface (EMIF) Reference Guide (literature number

SPRU266)].

Boot Configuration:

•

Controls initialization of DSP modes at reset (I) via pullup/pulldown resistors

–

Boot mode (AEA[22:21]):

00 - No boot (default mode)

01 - HPI/PCI boot (based on PCI_EN pin)

10 - Reserved

O/Z

IPD

11 - EMIFA boot

–

EMIF clock select (AEA[20:19]):

Clock mode select for EMIFA (AECLKIN_SEL[1:0])

00 - AECLKIN (default mode)

01 - CPU/4 Clock Rate

AEA8

10 - CPU/6 Clock Rate

11 - Reserved

AEA7

AEA6

For more details, see the Device Configurations section of this data sheet.

AEA5

AEA4

AEA3

34

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

EMIFA (64-bit) – DATA

AED63

AED62

AED61

AED60

AED59

AED58

AED57

AED56

AED55

AED54

AED53

AED52

AED51

AED50

AED49

AED48

AED47

AED46

AED45

AED44

AED43

AED42

AED41

AED40

AED39

AED38

AED37

AED36

AED35

AED34

AED33

AED32

AED31

AED30

AED29

AED28

AED27

AED26

AED25

AED24

AED23

AED22

AED21

AED20

AF24

AF23

AE23

AD23

AD22

AE22

AD21

AE21

AC21

AF21

AD20

AE20

AC20

AF20

AC19

AD19

W23

Y26

Y23

Y25

Y24

AA26

AA23

AA25

AA24

AB23

AB25

AB24

AC26

AC25

AD25

AD26

C26

I/O/Z

IPU

EMIFA external data

C25

D26

D25

E24

E25

F24

F25

F23

F26

G24

G25

Device Overview

35

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

G23

G26

H23

H24

C19

D19

A20

D20

B20

C20

A21

D21

B21

C21

A23

C22

B22

B23

A24

B24

AED19

AED18

AED17

AED16

AED15

AED14

AED13

AED12

AED11

AED10

AED9

I/O/Z

IPU

EMIFA external data

AED8

AED7

AED6

AED5

AED4

AED3

AED2

AED1

AED0

MANAGEMENT DATA INPUT/OUTPUT (MDIO)

XSP_CLK/MDCLK⁽³⁾

XSP_DO/MDIO⁽³⁾

R5

P5

I/O/Z

IPD

PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z).

PCI serial interface data out (O) [default] or MDIO serial data input/output

(I/O/Z). In PCI mode, this pin is connected to the input data pin of the serial

PROM.

IPU

VCXO INTERPOLATED CONTROL PORT (VIC)

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter

(VDAC) output [output only] [default] or this pin can be programmed as a GP0 8

pin (I/O/Z)

Boot Configuration: PCI frequency selection (PCI66).

If the PCI peripheral is enabled (PCI_EN pin = 1), then:

0 - PCI operates at 66 MHz (default).

VDAC/GP0[8]/PCI66⁽³⁾

AD1

AC1

I/O/Z

IPD

1 - PCI operates at 33 MHz.

The –500 device supports PCI at 33 MHz only. For proper –500 device operation

when the PCI peripheral is enabled (PCI_EN = 1), this pin must be pulled up

with a 1-kΩ resistor at device reset.

Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be

pulled up.

VIDEO PORTS (VP0, VP1, AND VP2)

IPD The STCLK signal drives the hardware counter on the video ports.

STCLK

I

36

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

VIDEO PORT 2 (VP2)

VP2D[19]

E13

E12

D12

C12

B12

E11

D11

C11

B11

A11

D10

C10

B10

A10

D9

VP2D[18]

VP2D[17]

VP2D[16]

VP2D[15]

VP2D[14]

VP2D[13]

VP2D[12]

VP2D[11]

VP2D[10]

VP2D[9]

VP2D[8]

VP2D[7]

VP2D[6]

VP2D[5]

VP2D[4]

VP2D[3]

VP2D[2]

VP2D[1]

VP2D[0]

VP2CLK1

VP2CLK0

VP2CTL2

VP2CTL1

VP2CTL0

Video port 2 (VP2) data input/output (I/O/Z)

I/O/Z

IPD

Note: By default, no function is enabled upon reset. To configure these pins, see

the Device Configuration section of this data sheet.

C9

B9

A9

D8

C8

A13

A7

I/O/Z

I

IPD

VP2 clock 1 (I/O/Z)

VP2 clock 0 (I)

C7

VP2 control 2 (I/O/Z)

VP2 control 1 (I/O/Z)

VP2 control 0 (I/O/Z)

D7

I/O/Z

IPD

B8

Device Overview

37

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

VIDEO PORT 1 (VP1) OR McASP0 DATA OR McBSP1

VP1D[19]/AXR0[7]⁽³⁾

VP1D[18]/AXR0[6]⁽³⁾

VP1D[17]/AXR0[5]⁽³⁾

VP1D[16]/AXR0[4]⁽³⁾

VP1D[15]/AXR0[3]⁽³⁾

VP1D[14]/AXR0[2]⁽³⁾

VP1D[13]/AXR0[1]⁽³⁾

VP1D[12]/AXR0[0]⁽³⁾

VP1D[11]

AB12

AB11

AC11

AD11

AE11

AC10

AD10

AC9

AD9

AE9

Video port 1 (VP1) data input/output (I/O/Z) or McASP0 data pins (I/O/Z)

[default] and Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data

input/output (I/O/Z) [default]

By default, standalone VP1 data input/output pins have no function enabled

upon reset. To configure these pins, see the Device Configuration section of this

data sheet.

VP1D[10]

I/O/Z

IPD

VP1D[9]

AC8

AD8

AC7

AD7

AE7

VP1D[8]/CLKR1⁽³⁾

VP1D[7]/FSR1⁽³⁾

VP1D[6]/DR1⁽³⁾

VP1D[5]/CLKS1⁽³⁾

VP1D[4]/DX1⁽³⁾

VP1D[3]/FSX1⁽³⁾

VP1D[2]/CLKX1⁽³⁾

VP1D[1]

For more details on the McBSP1 pin functions or the McASP0 data pin functions,

see McBSP1 or McASP0 data sections of this table and the Device Configur-

ations section of this data sheet.

AC6

AD6

AE6

AF6

VP1D[0]

AF5

VP1CLK1

AF10

AF8

I/O/Z

I

IPD

VP1 clock 1 (I/O/Z)

VP1 clock 0 (I)

VP1CLK0

VP1CTL2

AD5

AE5

VP1 control 2 (I/O/Z)

VP1 control 1 (I/O/Z)

VP1 control 0 (I/O/Z)

VP1CTL1

I/O/Z

IPD

VP1CTL0

AF4

38

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NAME

NO.

VIDEO PORT 0 (VP0) OR McASP0 CONTROL OR McBSP0

VP0D[19]/AHCLKX0⁽³⁾

VP0D[18]/AFSX0⁽³⁾

VP0D[17]/ACLKX0⁽³⁾

VP0D[16]/AMUTE0⁽³⁾

AC12

AD12

AB13

AC13

VP0D[15]/

AD13

AMUTEIN0⁽³⁾

VP0D[14]/AHCLKR0⁽³⁾

VP0D[13]/AFSR0⁽³⁾

VP0D[12]/ACLKR0⁽³⁾

VP0D[11]

AB14

AC14

AD14

AB15

AC15

AD15

AE15

AB16

AC16

AD16

AE16

AF16

AF17

AE18

AF18

AF12

AF14

AD17

AC17

AE17

Video port 0 (VP0) data input/output (I/O/Z) or McASP0 control pins (I/O/Z)

[default] and Video port 0 (VP0) data input/output (I/O/Z) or McBSP0 data

input/output (I/O/Z) [default]

By default, standalone VP0 data input/output pins have no function enabled

upon reset. To configure these pins, see the Device Configuration section of this

data sheet.

VP0D[10]

I/O/Z

IPD

VP0D[9]

VP0D[8]/CLKR0⁽³⁾

VP0D[7]/FSR0⁽³⁾

VP0D[6]/DR0⁽³⁾

VP0D[5]/CLKS0⁽³⁾

VP0D[4]/DX0⁽³⁾

VP0D[3]/FSX0⁽³⁾

VP0D[2]/CLKX0⁽³⁾

VP0D[1]

For more details on the McBSP0 pin functions or the McASP0 control pin

functions, see McBSP0 or McASP0 control sections of this table and the Device

Configurations section of this data sheet.

VP0D[0]

VP0CLK1

I/O/Z

I

IPD

VP0 clock 1 (I/O/Z)

VP0CLK0

VP0 clock 0 (I)

VP0CTL2

VP0 control 2 (I/O/Z)

VP0CTL1

I/O/Z

IPD

VP0 control 1 (I/O/Z)

VP0CTL0

VP0control 0 (I/O/Z)

TIMER 2

–

No external pins. The timer 2 peripheral pins are not pinned out as external pins.

TIMER 1

Timer 1 output (O/Z)

Boot Configuration: Device endian mode [LENDIAN] (I)

Controls initialization of DSP modes at reset via pullup/pulldown resistors

•

Device Endian mode

0 - Big Endian

1 - Little Endian (default)

TOUT1

TINP1

B5

A5

O/Z

IPU

IPD

For more details on LENDIAN, see the Device Configurations section of this data

sheet.

I

Timer 1 or general-purpose input

TIMER 0

Timer 0 output (O/Z)

Boot Configuration: MAC enable pin [MAC_EN] (I)

The PCI_EN and the MAC_EN pin control the selection (enable/disable) of the

HPI, EMAC, MDIO, and GP0[15:9], or PCI peripherals. The pins work in

conjunction to enable/disable these peripherals.

TOUT0

TINP0

C5

A4

O/Z

I

IPD

For more details, see the Device Configurations section of this data sheet.

Timer 0 or general-purpose input

Device Overview

39

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

INTER-INTEGRATED CIRCUIT 0 (I2C0)

SCL0

SDA0

E4

D3

I/O/Z

—

I2C0 clock.

I2C0 data.

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

Video Port 1 (VP1) input/output data 8 pin (I/O/Z) or McBSP1 receive clock

(I/O/Z) [default]

VP1D[8]/CLKR1⁽³⁾

AD8

I/O/Z

IPD

VP1 input/output data 7 pin (I/O/Z) or McBSP1 receive frame sync (I/O/Z)

[default]

VP1D[7]/FSR1⁽³⁾

VP1D[6]/DR1⁽³⁾

VP1D[5]/CLKS1⁽³⁾

VP1D[4]/DX1⁽³⁾

VP1D[3]/FSX1⁽³⁾

VP1D[2]/CLKX1⁽³⁾

AC7

AD7

AE7

AC6

AD6

AE6

I/O/Z

I

IPD

VP1 input/output data 6 pin (I/O/Z) or McBSP1 receive data (I) [default]

VP1 input/output data 5 pin (I/O/Z) or McBSP1 external clock source (I) (as

opposed to internal) [default]

I

I/O/Z

VP1 input/output data 4 pin (I/O/Z) or McBSP1 transmit data (O/Z) [default]

VP1 input/output data 3 pin (I/O/Z) or McBSP1 transmit frame sync (I/O/Z)

[default]

VP1 input/output data 2 pin (I/O/Z) or McBSP1 transmit clock (I/O/Z) [default]

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

Video Port 0 (VP0) input/output data 8 pin (I/O/Z) or McBSP0 receive clock

(I/O/Z) [default]

VP0D[8]/CLKR0⁽³⁾

AE15

I/O/Z

IPD

VP0 input/output data 7 pin (I/O/Z) or McBSP0 receive frame sync (I/O/Z)

[default]

VP0D[7]/FSR0⁽³⁾

VP0D[6]/DR0⁽³⁾

VP0D[5]/CLKS0⁽³⁾

VP0D[4]/DX0⁽³⁾

VP0D[3]/FSX0⁽³⁾

VP0D[2]/CLKX0⁽³⁾

AB16

AC16

AD16

AE16

AF16

AF17

I/O/Z

I

IPD

VP0 input/output data 6 pin (I/O/Z) or McBSP0 receive data (I) [default]

VP0 input/output data 5 pin (I/O/Z) or McBSP0 external clock source (I) (as

opposed to internal) [default]

I

O/Z

I/O/Z

VP0 input/output data 4 pin (I/O/Z) or McBSP0 transmit data (O/Z) [default]

VP0 input/output data 3 pin (I/O/Z) or McBSP0 transmit frame sync (I/O/Z)

[default]

VP0 input/output data 2 pin (I/O/Z) or McBSP0 transmit clock (I/O/Z) [default]

40

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NAME

NO.

ETHERNET MAC (EMAC)

HD31/AD31/MRCLK⁽³⁾

HD30/AD30/MCRS⁽³⁾

HD29/AD29/MRXER⁽³⁾

HD28/AD28/MRXDV⁽³⁾

HD27/AD27/MRXD3⁽³⁾

HD26/AD26/MRXD2⁽³⁾

HD25/AD25/MRXD1⁽³⁾

HD24/AD24/MRXD0⁽³⁾

HD22/AD22/MTCLK⁽³⁾

HD21/AD21/MCOL⁽³⁾

HD20/AD20/MTXEN⁽³⁾

HD19/AD19/MTXD3⁽³⁾

HD18/AD18/MTXD2⁽³⁾

HD17/AD17/MTXD1⁽³⁾

G1

H3

G2

J4

I

Host-port data (I/O/Z) [default] or EMAC transmit/receive or control pins (I) (O/Z)

HPI pin functions are default, see the Device Configurations section of this data

sheet. EMAC Media Independent I/F (MII) data, clocks, and control pins for

Transmit/Receive.

I

•

MII transmit clock (MTCLK),

I

Transmit clock source from the attached PHY.

MII transmit data (MTXD[3:0]),

H2

J3

I

Transmit data nibble synchronous with transmit clock (MTCLK).

MII transmit enable (MTXEN),

J1

I

K4

L4

K2

L3

L2

M4

M2

This signal indicates a valid transmit data on the transmit data pins

(MTDX[3:0]).

I

•

MII collision sense (MCOL)

I

Assertion of this signal during half-duplex operation indicates network

collision.

During full-duplex operation, transmission of new frames will not begin if this

pin is asserted.

O/Z

•

MII carrier sense (MCRS)

Indicates a frame carrier signal is being received.

MII receive data (MRXD[3:0]),

Receive data nibble synchronous with receive clock (MRCLK).

MII receive clock (MRCLK),

Receive clock source from the attached PHY.

MII receive data valid (MRXDV),

HD16/AD16/MTXD0⁽³⁾

M3

O/Z

This signal indicates a valid data nibble on the receive data pins

(MRDX[3:0]) and

•

MII receive error (MRXER),

Indicates reception of a coding error on the receive data.

Device Overview

41

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL

VP0 input/output data 19 pin (I/O/Z) or McASP0 transmit high-frequency master

clock (I/O/Z).

VP0D[19]/AHCLKX0⁽³⁾

VP0D[18]/AFSX0⁽³⁾

AC12

AD12

I/O/Z

IPD

VP0 input/output data 18 pin (I/O/Z) or McASP0 transmit frame sync or left/right

clock (LRCLK) (I/O/Z).

VP0D[17]/ACLKX0⁽³⁾

VP0D[16]/AMUTE0⁽³⁾

AB13

AC13

I/O/Z

O/Z

IPD

VP0 input/output data 17 pin (I/O/Z) or McASP0 transmit bit clock (I/O/Z).

VP0 input/output data 16 pin (I/O/Z) or McASP0 mute output (O/Z).

VP0D[15]/

AD13

AB14

I/O/Z

IPD

VP0 input/output data 15 pin (I/O/Z) or McASP0 mute input (I/O/Z).

AMUTEIN0⁽³⁾

VP0 input/output data 14 pin (I/O/Z) or McASP0 receive high-frequency master

clock (I/O/Z).

VP0D[14]/AHCLKR0⁽³⁾

VP0 input/output data 13 pin (I/O/Z) or McASP0 receive frame sync or left/right

clock (LRCLK) (I/O/Z).

VP0D[13]/AFSR0⁽³⁾

VP0D[12]/ACLKR0⁽³⁾

AC14

AD14

I/O/Z

IPD

VP0 input/output data 12 pin (I/O/Z) or McASP0 receive bit clock (I/O/Z).

MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA

VP1D[19]/AXR0[7]⁽³⁾

VP1D[18]/AXR0[6]⁽³⁾

VP1D[17]/AXR0[5]⁽³⁾

VP1D[16]/AXR0[4]⁽³⁾

VP1D[15]/AXR0[3]⁽³⁾

VP1D[14]/AXR0[2]⁽³⁾

VP1D[13]/AXR0[1]⁽³⁾

VP1D[12]/AXR0[0]⁽³⁾

AB12

AB11

AC11

AD11

AE11

AC10

AD10

AC9

VP1 input/output data pins [19:12] (I/O/Z) or McASP0 TX/RX data pins [7:0]

(I/O/Z) [default].

I/O/Z

IPD

RESERVED FOR TEST

Reserved. This pin must be connected directly to CV_DDfor proper device

operation.

RSV07

RSV08

H7

R6

A

—

Reserved. This pin must be connected directly to DV_DDfor proper device

operation.

RSV05

RSV06

RSV00

RSV01

RSV02

RSV03

RSV04

E14

W7

I

A

IPD

—

AA3

AB3

AC4

AD3

AF3

A

—

Reserved (leave unconnected, do not connect to power or ground. If the signal

must be routed out from the device, the internal pull-up/down resistance should

not be relied upon and an external pull-up/down should be used.)

I

—

O/Z

O

—

IPU

42

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

SUPPLY VOLTAGE PINS

A2

A25

B1

B2

B14

B25

B26

C3

C24

D4

D23

E5

E7

E8

E10

E17

E19

E20

E22

F9

F12

F15

F18

G5

3.3-V supply voltage

(see the Power-Supply Decoupling section of this data sheet)

DV_DD

S

G22

H5

H22

J6

J21

K5

K22

M6

M21

N2

P25

R21

U5

U22

V21

W5

W22

W25

Y5

Y22

Device Overview

43

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

AA9

AA12

AA15

AA18

AB5

AB7

AB8

AB10

AB17

AB19

AB20

AB22

AC23

AD24

AE1

3.3-V supply voltage

(see the Power-Supply Decoupling section of this data sheet)

DV_DD

S

AE2

AE13

AE25

AE26

AF2

AF25

44

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

F6

F7

F20

F21

G6

G7

G8

G10

G11

G13

G14

G16

G17

G19

G20

G21

H20

K7

K20

L7

L20

M12

M14

N7

1.2-V supply voltage (-500 device)

1.4 V supply voltage (A-500, A-600, -600, -720 devices)

(see the Power-Supply Decoupling section of this data sheet)

CV_DD

S

N13

N15

N20

P7

P12

P14

P20

R13

R15

T7

T20

U7

U20

W20

Y6

Y7

Y8

Y10

Y11

Y13

Y14

Device Overview

45

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

Y16

Y17

Y19

Y20

1.2-V supply voltage (-500 device)

CV_DD

Y21

S

1.4 V supply voltage (A-500, A-600, -600, -720 devices)

(see the Power-Supply Decoupling section of this data sheet)

AA6

AA7

AA20

AA21

GROUND PINS

A1

A3

A6

A8

A12

A14

A19

A22

A26

B3

B6

B7

B13

B19

C2

C4

C13

C18

C23

D1

V_SS

GND

Ground pins

D2

D5

D13

D18

D22

D24

E3

E6

E9

E16

E18

E21

E23

E26

F5

46

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

F8

F10

F11

F13

F14

F16

F17

F19

F22

G9

G12

G15

G18

H1

H6

H21

H26

J5

J7

J20

J22

K6

V_SS

K21

L1

GND

Ground pins

L6

L21

M7

M13

M15

M20

N5

N6

N12

N14

N21

N25

P2

P6

P13

P15

P21

R7

R12

R14

R20

Device Overview

47

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

T1

T5

T6

T21

T26

U6

U21

V5

V7

V20

V22

W1

W6

W21

W26

Y9

Y12

Y15

Y18

AA4

AA5

AA8

AA10

AA11

AA13

AA14

AA16

AA17

AA19

AA22

AB1

AB2

AB4

AB6

AB9

AB18

AB21

AB26

AC3

AC5

AC18

AC22

AC24

AD2

AD4

V_SS

GND

Ground pins

48

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 2-4. Terminal Functions (continued)

SIGNAL

NAME

IPD/

TYPE⁽¹⁾

DESCRIPTION

IPU⁽²⁾

NO.

AD18

AE3

AE8

AE10

AE12

AE14

AE19

AE24

AF1

V_SS

GND

Ground pins

AF7

AF9

AF11

AF13

AF15

AF19

AF22

AF26

Device Overview

49

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.6 Development

2.6.1 Development Support

TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

The following products support development of C6000™ DSP-based applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target

software needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)

EVM (Evaluation Module)

For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For

information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

50

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

2.6.2 Device Support

2.6.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,

TMP, or TMS (e.g., TMS320DM642GDKA500). Texas Instruments recommends two of three possible

prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of

product development from engineering prototypes (TMX/TMDX) through fully qualified production

devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, GDK), the temperature range (for example, “A” is the extended temperature

range), and the device speed range in megahertz (for example, 500 is 500 MHz). Figure 2-16 provides a

legend for reading the complete device name for any TMS320C6000™ DSP platform member.

The ZDK package, like the GDK package, is a 548-ball plastic BGA only with Pb-free balls. The ZNZ is the

Pb-free package version of the GNZ package.

For device part numbers and further ordering information for TMS320DM642 in the GDK, GNZ, ZDK, and

ZNZ package types, see the TI website (http://www.ti.com) or contact your TI sales representative.

Device Overview

51

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

A

TMS 320 DM642 GDK

500

PREFIX

DEVICE SPEED RANGE

TMX= Experimental device

TMP= Prototype device

500 (500-MHz CPU, 100-MHz EMIF, 33-MHz PCI)

600 (600-MHz CPU, 133-MHz EMIF, 66-MHz PCI)

720 (720-MHz CPU, 133-MHz EMIF, 66-MHz PCI)

TMS= Qualified device

SMX= Experimental device, MIL

SMJ = MIL-PRF-38535, QML

(A)

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature

SM

= High Rel (non-38535)

A

=

−40°C to 105°C, extended temperature

DEVICE FAMILY

320 = TMS320t DSP family

(B)(C)

PACKAGE TYPE

GDK = 548-pin plastic BGA

GNZ = 548-pin plastic BGA

ZDK = 548-pin plastic BGA, with Pb-free soldered balls

ZNZ = 548-pin plastic BGA, with Pb-free soldered balls

(D)

DEVICE

DM64x DSP:

643

642

641

640

A. The extended temperature "A version" devices may have different operating conditions than the commercial

temperature devices. For more details, see the recommended operating conditions portion of this data sheet.

B. BGA = Ball Grid Array

C. The ZDK and ZNZ mechanical package designators represent the version of the GDK and GNZ packages,

respectively, with Pb-free balls. For more detailed information, see the Mechanical Data section of this document.

D. For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).

Figure 2-16. TMS320DM64x™ DSP Device Nomenclature (Including the TMS320DM642 Device)

2.6.2.2 Documentation Support

Extensive documentation supports all TMS320™ DSP family generations of devices from product

announcement through applications development. The types of documentation available include: data

sheets, such as this document, with design specifications; complete user's reference guides for all devices

and tools; technical briefs; development-support tools; on-line help; and hardware and software

applications. The following is a brief, descriptive list of support documentation specific to the C6000™

DSP devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

C6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides

an overview and briefly describes the functionality of the peripherals available on the C6000™ DSP

platform of devices. This document also includes a table listing the peripherals available on the C6000

devices along with literature numbers and hyperlinks to the associated peripheral documents.

The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x™

digital signal processor, and discusses the application areas that are enhanced by the C64x™ DSP

VelociTI.2™ VLIW architecture.

The TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature

number SPRU629) describes the functionality of the Video Port and VIC Port peripherals.

The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number

SPRU041) describes the functionality of the McASP peripheral.

TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)

describes the functionality of the I²C peripheral.

52

Device Overview

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

TMS320C6000 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO)

Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO

peripherals.

TMS320DM642 Technical Overview (literature number SPRU615) describes the TMS320DM642 architec-

ture including details of its peripherals. This document also shows several example applications such as

using the DM642 device in development of IP phones, video-on-demand set-top boxes, and surveillance

digital video recorders.

The TMS320DM642 Digital Signal Processor Silicon Errata (literature number SPRZ196) describes the

known exceptions to the functional specifications for particular silicon revisions of the TMS320DM642

device.

The TMS320DM64x Power Consumption Summary application report (literature number SPRA962)

discusses the power consumption for user applications with the TMS320DM642 DSP devices.

The TMS320DM642 Hardware Designer’s Resource Guide (literature number SPRAA51) is organized by

development flow and functional areas to make design efforts as seamless as possible. This document

includes getting started, board design, system testing, and checklists to aid in initial designs and debug

efforts. Each section of this document includes pointers to valuable information including: technical

documentation, models, symbols, and reference designs for use in each phase of design. Particular

attention is given to peripheral interfacing and system-level design concerns.

The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how

to properly use IBIS models to attain accurate timing analysis for a given system.

The tools support documentation is electronically available within the Code Composer Studio™ Integrated

Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the

Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

2.6.2.3 Device Silicon Revision

The device silicon revision can be determined by the "Die PG code" marked on the top of the package.

For more detailed information on the DM642 silicon revision, package markings, and the known

exceptions to the functional specifications as well as any usage notes, refer to the device-specific silicon

errata: TMS320DM642 Digital Signal Processor Silicon Errata (literature number SPRZ196).

Device Overview

53

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

3 Device Configurations

On the DM642 device, bootmode and certain device configurations/peripheral selections are determined at

device reset, while other device configurations/peripheral selections are software-configurable via the

peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.

3.1 Configurations at Reset

For DM642 proper device operation, GP0[0] (pin M5) must remain low, do not oppose the internal

pulldown (IPD).

3.1.1 Peripheral Selection at Device Reset

Some DM642 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,

general-purpose input/output pins GP0[15:9], PCI and its internal EEPROM, EMAC, and MDIO). Other

DM642 peripherals (i.e., the Timers, I2C0, and the GP0[7:0] pins), are always available.

•

HPI, GP0[15:9], PCI, EEPROM (internal to PCI), EMAC, and MDIO peripherals

The PCI_EN and MAC_EN pins are latched at reset. They determine specific peripheral selection,

summarized in Table 3-1. For further clarification of the HPI vs. EMAC configuration, see Table 3-2.

Table 3-1. PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC, and MDIO)

PERIPHERAL SELECTION

PERIPHERALS SELECTED

PCI_EN

Pin [E2]

PCI_EEAI

Pin [L5]

HD5

Pin [Y1]

MAC_EN

Pin [C5]

HPI Data

Lower

HPI Data

Upper

EEPROM

32-Bit PCI

EMAC and

MDIO

GP0[15:9]

(Auto-Init)

0

1

0

1

0

1

√

Hi-Z

√

Disabled

N/A

Disabled

√

Disabled

√

Disabled

Enabled

(via External

EEPROM)

1

0

X

Disabled

√

Disabled

(default values)

•

If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and based on the HD5 and

MAC_EN pin configuration at reset, HPI16 mode or EMAC and MDIO can be selected. When the PCI

is disabled (PCI_EN = 0), the GP0[15:9] pins can also be programmed as GPIO, provided the GPxEN

and GPxDIR bits are properly configured.

This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and

XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GP0/PCI pins can be used as GPIO with the proper

software configuration of the GPIO enable and direction registers (for more details, see Table 3-8).

If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled.

This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GP0/PCI pins function

as PCI pins (for more details, see Table 3-8).

•

The MAC_EN pin, in combination with the PCI_EN and HD5 pins, controls the selection of the EMAC

and MDIO peripherals (for more details, see Table 3-2).

The PCI_EN pin (= 1) and the PCI_EEAI pin control the whether the PCI initializes its internal registers

via external EEPROM (PCI_EEAI = 1) or if the internal default values are used instead

(PCI_EEAI = 0).

54

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TMS320DM642

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Table 3-2. HPI vs. EMAC Peripheral Pin Selection

CONFIGURATION SELECTION

PERIPHERALS SELECTED

GP0[0] (Pin [M5])⁽¹⁾

HD5 (Pin [Y1])

MAC_EN (Pin [C5])

HD[15:0]

HD[31:16]

Hi-Z

0

1

0

1

0

1

HPI16

used for EMAC

HPI32 (HD[31:0])

Hi-Z

used for EMAC

(1) Invalid configuration. The GP0[0] pin must remain low during

device reset.

1

X

3.1.2 Device Configuration at Device Reset

Table 3-3 describes the DM642 device configuration pins, which are set up via external pullup/pulldown

resistors through the specified EMIFA address bus pins (AEA[22:19]), and the TOUT1/LENDIAN,

GP0[3]/PCIEEAI, and the HD5 pins (all of which are latched during device reset).

Table 3-3. DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI,

VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and MAC_EN)

CONFIGURATION

NO.

FUNCTIONAL DESCRIPTION

Device Endian mode (LEND)

TOUT1/LENDIAN

B5

0 - System operates in Big Endian mode

1 - System operates in Little Endian mode (default)

Bootmode [1:0]

00 - No boot (default mode)

01 - HPI/PCI boot (based on PCI_EN pin)

10 - Reserved

[U23,

V24]

AEA[22:21]

11 - EMIFA boot

EMIFA input clock select

Clock mode select for EMIFA (AECLKIN_SEL[1:0])

[V25,

V26]

00 - AECLKIN (default mode)

01 - CPU/4 Clock Rate

10 - CPU/6 Clock Rate

11 - Reserved

AEA[20:19]

PCI EEPROM Auto-Initialization (PCIEEAI)

PCI auto-initialization via external EEPROM

0 - PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI

default values (default).

GP0[3]/PCIEEAI

L5

1 - PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through

EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).

PCI frequency selection (PCI66) [PCI peripheral needs be enabled (PCI_EN = 1) to use this function]

Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating frequency is selected at reset

via the pullup/pulldown resistor on the PCI66 pin:

0 - PCI operates at 66 MHz (default).

1 - PCI operates at 33 MHz.

VDAC/GP0[8]/PCI66

AD1

The -500 speed device supports PCI at 33 MHz only. For proper -500 device operation when the PCI is

enabled (PCI_EN = 1), this pin must be pulled up with a 1-kΩ resistor at device reset.

Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.

Device Configurations

55

TMS320DM642

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 3-3. DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI,

VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and MAC_EN) (continued)

CONFIGURATION

NO.

FUNCTIONAL DESCRIPTION

HPI peripheral bus width (HPI_WIDTH)

0 - HPI operates as an HPI16.

(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in

the Hi-Z state.)

HD5/AD5

Y1

1 - HPI operates as an HPI32.

(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)

(Also see the PCI_EN; TOUT0/MAC_EN functional description in this table)

Peripheral Selection

00 - HPI (default mode) [HPI32, if HD5 = 1; HPI16 if HD5 = 0

01 - EMAC and MDIO; HPI16, if HD5 = 0; HPI disabled, if HD5 = 1

10 - PCI

PCI_EN;

TOUT0/MAC_EN

[E2; C5]

11 - Reserved

3.2 Configurations After Reset

3.2.1 Peripheral Selection After Device Reset

Video Ports, McBSP1, McBSP0, McASP0 and I2C0

The DM642 device has designated registers for peripheral configuration (PERCFG), device status

(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration

module and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these

registers via the CFGBUS.

The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the

Video Ports (VP0, VP1, VP2) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more detailed

information on the PERCFG register control bits, see Figure 3-1 and Table 3-4.

31

23

15

24

16

8

Reserved

R-0

Reserved

R-0

Reserved

R-0

7

6

5

4

3

2

1

0

Reserved

VP2EN

VP1EN

VP0EN

I2C0EN

MCBSP1EN

MCBSP0EN

MCASP0EN

R-0

R/W-0

R/W-1

R/W-0

Legend: R = Read only, R/W = Read/Write, -n = value after reset

Figure 3-1. Peripheral Configuration Register (PERCFG)

[Address Location: 0x01B3F000 - 0x01B3F003]

56

Device Configurations

TMS320DM642

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 3-4. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions

BIT

NAME

DESCRIPTION

31:7

Reserved

Reserved. Read-only, writes have no effect.

VP2 Enable bit.

Determines whether the VP2 peripheral is enabled or disabled.

(This feature allows power savings by disabling the peripheral when not in use.)

6

VP2EN

VP1EN

0 = VP2 is disabled, and the module is powered down (default).

1 = VP2 is enabled.

VP1 Enable bit.

Determines whether the VP1 peripheral is enabled or disabled.

5

0 = VP1 is disabled, and the module is powered down (default).

(This feature allows power savings by disabling the peripheral when not in use.)

1 = VP1 is enabled.

VP0 Enable bit.

Determines whether the VP0 peripheral is enabled or disabled.

4

3

VP0EN

I2C0EN

0 = VP0 is disabled, and the module is powered down (default).

(This feature allows power savings by disabling the peripheral when not in use.)

1 = VP0 is enabled.

Inter-integrated circuit 0 (I2C0) enable bit.

Selects whether I2C0 peripheral is enabled or disabled (default).

0 = I2C0 is disabled, and the module is powered down (default).

1 = I2C0 is enabled.

Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit.

Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled.

0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the remaining VP1

upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings.

1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default).

2

1

MCBSP1EN

MCBSP0EN

For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and

the signal pins controlled/selected, see Figure 3-2.

Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.

Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.

0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the remaining VP0

upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings.

1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).

For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and

the signal pins controlled/selected, see Figure 3-2.

McASP0 vs. VP0/VP1 upper-data pins select bit.

Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.

0 = McASP0 is disabled; VP0 and VP1 upper-data pins are enabled; and the VP0 and VP1lower-data

pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and VP1EN bits, respectively.

1 = McASP0 is enabled; VP0 and VP1 upper-data pins are disabled; and the VP0 and VP1lower-data

pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN andVP1EN bits, respectively.

0

MCASP0EN

For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and

the signal pins controlled/selected, see Figure 3-2.

Device Configurations

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McBSP0EN [PERCFG.1]

1

0

McBSP0

VP0

Lower Data (10 pins)

VP0 (Channel A)

(A)

VP0D[8:2] Muxed

VP0D[9,1,0] Standalone

McBSP1EN [PERCFG.2]

1

0

McBSP1

VP1

Lower Data (10 pins)

VP1 (Channel A)

(B)

VP1D[8:2] Muxed

VP1D[9,1,0] Standalone

McBSP0EN [PERCFG.1]

McASP0EN [PERCFG.0]

1

0

VP0 (Channel A)

VP0

McASP0EN [PERCFG.0]

Upper Data (10 pins)

(C)

VP0D[19:12] Muxed

VP0D[11:10] Standalone

McASP0 Control

1

0

VP0 (Channel B)

McBSP1EN [PERCFG.2]

McASP0EN [PERCFG.0]

1

0

VP1 (Channel A)

VP1

McASP0EN [PERCFG.0]

Upper Data (10 pins)

(D)

VP1D[19:12] Muxed

VP1D[11:10] Standalone

McASP0 Data

1

0

VP1 (Channel B)

A. Consists of: VP0D[8]/CLKR0, VP0D[7]/FSR0, VP0D[6]/DR0, VP0D[5]/CLKS0, VP0D[4]/DX0, VP0D[3]/FSX0,

VP0D[2]/CLKX0.

B. Consists of: VP1D[8]/CLKR1, VP1D[7]/FSR1, VP1D[6]/DR1, VP1D[5]/CLKS1, VP1D[4]/DX1, VP1D[3]/FSX1,

VP1D[2]/CLKX1.

C. Consists of: VP0D[19]/AHCLKX0, VP0D[18]/AFSX0, VP0D[17]/ACLKX0, VP0D[16]/AMUTE0, VP0D[15]/AMUTEIN0,

VP0D[14]/AHCLKR0, VP0D[13]/AFSR0, VP0D[12]/ACLKR0

D. Consists of: VP1D[19:12]/AXR0[7:0]

Figure 3-2. VP1, VP0, McBSP1, McBSP0, and McASP0 Data/Control Pin Muxing

58

Device Configurations

TMS320DM642

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SPRS200J–JULY 2002–REVISED AUGUST 2005

3.3 Peripheral Configuration Lock

By default, the McASP0, VP0, VP1, VP2, and I2C peripherals are disabled on power up. In order to use

these peripherals on the DM642 device, the peripheral must first be enabled in the Peripheral

Configuration register (PERCFG). Software muxed pins should not be programmed to switch

functionalities during run-time. Care should also be taken to ensure that no accesses are being

performed before disabling the peripherals. To help minimize power consumption in the DM642

device, unused peripherals may be disabled.

Figure 3-3 shows the flow needed to enable (or disable) a given peripheral on the DM642 device.

Unlock the PERCFG Register

Using the PCFGLOCK Register

Write to

PERCFG Register

to Enable/Disable Peripherals

Read from

PERCFG Register

Wait 128 CPU Cycles Before

Accessing Enabled Peripherals

Figure 3-3. Peripheral Enable/Disable Flow Diagram

Device Configurations

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A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register

(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register

determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked

(LOCKSTAT bit = 0), see Figure 3-4. A peripheral can only be enabled when the PERCFG register is

"unlocked" (LOCKSTAT bit = 0).

Read Accesses

31

1

0

Reserved

R-0

LOCKSTAT

R-1

Write Accesses

31

0

LOCK

W-0

Legend: R = Read only, R/W = Read/Write, -n = value after reset

Figure 3-4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] - Read/Write Accesses

Table 3-5. PCFGLOCK Register Selection Bit Descriptions - Read Accesses

BIT

NAME

DESCRIPTION

31:1

Reserved

Reserved. Read-only, writes have no effect.

Lock status bit.

Determines whether the PERCFG register is locked or unlocked.

0

LOCKSTAT

0 = Unlocked, read accesses to the PERCFG register allowed.

1 = Locked, write accesses to the PERCFG register do not modify the register state [default].

Reads are unaffected by Lock Status.

Table 3-6. PCFGLOCK Register Selection Bit Descriptions - Write Accesses

BIT

NAME

LOCK

DESCRIPTION

Lock bits.

0x10C0010C = Unlocks PERCFG register accesses.

31:0

Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary

overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the

PERCFG register with the necessary enable bits set.

Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation

between the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the

PERCFG register after the write is issued forces the CPU to wait for the write to the PERCFG register to

occur.

Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128

CPU cycles before accessing the enabled peripheral. The user must ensure that no accesses are

performed to a peripheral while it is disabled.

60

Device Configurations

TMS320DM642

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3.4 Device Status Register Description

The device status register depicts the status of the device peripheral selection. For the actual register bit

names and their associated bit field descriptions, see Figure 3-5 and Table 3-7.

31

24

Reserved

R-0

23

15

16

Reserved

R-0

12

11

10

9

8

Reserved

R-0

MAC_EN

HPI_WIDTH

PCI_EEAI

PCI_EN

R-x

3

R-x

2

R-x

1

R-x

0

7

6

5

4

Reserved

CLKMODE1

CLKMODE0

LENDIAN

BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0

R-x

R-x R-x R-x R-x

Legend: R = Read only, R/W = Read/Write, -n = value after reset

Figure 3-5. Device Status Register (DEVSTAT) Description - 0x01B3 F004

Device Configurations

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Table 3-7. Device Status (DEVSTAT) Register Selection Bit Descriptions

BIT

NAME

DESCRIPTION

31:12

Reserved

Reserved. Read-only, writes have no effect.

EMAC enable bit.

Shows the status of whether EMAC peripheral is enabled or disabled (default).

11

10

MAC_EN

0 = EMAC is disabled, and the module is powered down (default).

1 = EMAC is enabled.

This bit has no effect if the PCI peripheral is enabled (PCI_EN = 1).

HPI bus width control bit.

Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).

HPI_WIDTH

0 = HPI operates in 16-bit mode. (default).

1 = HPI operates in 32-bit mode.

PCI EEPROM auto-initialization bit (PCI auto-initialization via external EEPROM).

Shows the status of whether the PCI module initializes internal registers via external EEPROM or if the

internal PCI default values are used instead (default).

9

PCI_EEAI

PCI_EN

0 = PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default

values (default).

1 = PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through

EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).

PCI enable bit.

Shows the status of whether the PCI peripheral is enabled or disabled (default).

8

0 = PCI disabled. (default).

1 = PCI enabled.

Global select for the PCI vs. HPI/EMAC/MDIO/GPIO peripherals.

Reserved. Read-only, writes have no effect.

7

6

Reserved

CLKMODE1

Clock mode select bits

Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6,

or x12.

Clock mode select for CPU clock frequency (CLKMODE[1:0])

00 - Bypass (x1) (default mode)

01 - x6

10 - x12

5

CLKMODE0

11 - Reserved

For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this

data sheet.

Device Endian mode (LEND)

Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).

4

3

LENDIAN

0 - System is operating in Big Endian mode

1 - System is operating in Little Endian mode (default)

BOOTMODE1

Bootmode configuration bits

Shows the status of what device bootmode configuration is operational.

Bootmode [1:0]

00 - No boot (default mode)

01 - HPI/PCI boot (based on PCI_EN pin)

10 - Reserved

2

1

0

BOOTMODE0

AECLKINSEL1

AECLKINSEL0

11 - EMIFA boot

EMIFA input clock select

Shows the status of what clock mode is enabled or disabled for the EMIF.

Clock mode select for EMIFA (AECLKIN_SEL[1:0])

00 - AECLKIN (default mode)

01 - CPU/4 Clock Rate

10 - CPU/6 Clock Rate

11 - Reserved

62

Device Configurations

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3.5 Multiplexed Pin Configurations

Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed.

Some of these pins are configured by software, and the others are configured by external pullup/pulldown

resistors only at reset. Those muxed pins that are configured by software should not be programmed to

switch functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown

resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after

reset. Table 3-8 identifies the multiplexed pins on the DM642 device; shows the default (primary) function

and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific

multiplexed functions.

Table 3-8. DM642 Device Multiplexed Pin Configurations⁽¹⁾

MULTIPLEXED PINS

NAME

DEFAULT

FUNCTION

DEFAULT

SETTING

DESCRIPTION

NO.

CLKOUT4/GP0[1]

D6

CLKOUT4

GP1EN = 0 (disabled)

These pins are software-configurable. To use these pins

as GPIO pins, the GPxEN bits in the GPIO Enable

Register and the GPxDIR bits in the GPIO Direction

Register must be properly configured.

CLKOUT6/GP0[2]

C6

CLKOUT6

GP2EN = 0 (disabled)

GPxEN = 1: GPx pin enabled

GPxDIR = 0: GPx pin is an input

GPxDIR = 1: GPx pin is an output

The VDAC output pin function is default.

To use GP0[8] as a GPIO pin, the PCI needs to be

disabled (PCI_EN = 0), the GPxEN bits in the GPIO

Enable Register and the GPxDIR bits in the GPIO Direc-

tion Register must be properly configured.

GP8EN = 0 (disabled)

MAC_EN = 0 (disabled)

VDAC/GP0[8]

AD1

VDAC

GP8EN = 1: GP8 pin enabled

GP8DIR = 0: GP8 pin is an input

GP8DIR = 1: GP8 pin is an output

Note: If the PCI peripheral is disabled (PCI_EN pin = 0),

this pin must not be pulled up.

GP0[9]/PIDSEL

GP0[10]/PCBE3

GP0[11]/PREQ

K3

J2

To use GP0[15:9] as GPIO pins, the PCI needs to be

disabled (PCI_EN = 0), the GPxEN bits in the GPIO

Enable Register and the GPxDIR bits in the GPIO Direc-

tion Register must be properly configured.

F1

GPxEN = 0 (disabled)

GP0[12]/PGNT

H4

None

PCI_EN = 0 (disabled)⁽¹⁾

GPxEN = 1: GPx pin enabled

GPxDIR = 0: GPx pin is an input

GPxDIR = 1: GPx pin is an output

GP0[13]/PINTA

G4

GP0[14]/PCLK

C1

GP0[15]/PRST

G3

VP1D[19]/AXR0[7]

VP1D[18]/AXR0[6]

VP1D[17]/AXR0[5]

VP1D[16]/AXR0[4]

VP1D[15]/AXR0[3]

VP1D[14]/AXR0[2]

VP1D[13]/AXR0[1]

VP1D[12]/AXR0[0]

AB12

AB11

AC11

AD11

AE11

AC10

AD10

AC9

By default, no function is enabled upon reset.

To enable the Video Port 1 data pins, the VP1EN bit in the

VP1EN bit = 0 (disabled) PERCFG register must be set to a 1. (McASP0 data pins

None

MCASP0EN bit = 0

(disabled)

are disabled).

To enable the McASP0[7:0] data pins, the MCASP0EN bit

in the PERCFG register must be set to a 1. (VP1 upper

data pins are disabled).

(1) All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].

Device Configurations

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Table 3-8. DM642 Device Multiplexed Pin Configurations⁽¹⁾(continued)

MULTIPLEXED PINS

NAME

DEFAULT

FUNCTION

DEFAULT

SETTING

DESCRIPTION

NO.

AD8

VP1D[8]/CLKR1

VP1D[7]/FSR1

AC7

By default, the McBSP1 peripheral, function is enabled

upon reset (MCBSP1EN bit = 1).

VP1D[6]/DR1

AD7

VP1EN bit = 0 (disabled)

MCBSP1EN bit = 1

(enabled)

McBSP1

functions

VP1D[5]/CLKS1

VP1D[4]/DX1

AE7

To enable the Video Port 1 data pins, the VP1EN bit in the

PERCFG register must be set to a 1.

AC6

VP1D[3]/FSX1

AD6

VP1D[2]/CLKX1

VP0D[19]/AHCLKX0

VP0D[18]/AFSX0

VP0D[17]/ACLKX0

VP0D[16]/AMUTE0

VP0D[15]/AMUTEIN0

VP0D[14]/AHCLKR0

VP0D[13]/AFSR0

VP0D[12]/ACLKR0

VP0D[8]/CLKR0

VP0D[7]/FSR0

AE6

AC12

AD12

AB13

AC13

AD13

AB14

AC14

AD14

AE15

AB16

AC16

AD16

AE16

AF16

AF17

R5

By default, no function is enabled upon reset.

To enable the Video Port 0 data pins, the VP0EN bit in the

VP0EN bit = 0 (disabled) PERCFG register must be set to a 1. (McASP0 control

None

MCASP0EN bit = 0

(disabled)

pins are disabled).

To enable the McASP0 control pins, the MCASP0EN bit in

the PERCFG register must be set to a 1. (VP0 upper data

pins are disabled).

By default, the McBSP0 peripheral function is enabled

upon reset (MCBSP0EN bit = 1).

VP0D[6]/DR0

VP0EN bit = 0 (disabled)

MCBSP0EN bit = 1

(enabled)

McBSP0

functions

VP0D[5]/CLKS0

VP0D[4]/DX0

To enable the Video Port 0 data pins, the VP0EN bit in the

PERCFG register must be set to a 1.

VP0D[3]/FSX0

VP0D[2]/CLKX0

XSP_CLK/MDCLK

By default, no functions enabled upon reset (PCI is

disabled).

To enable the PCI peripheral, an external pullup resistor

PCI_EN = 0 (disabled)⁽¹⁾(1 kΩ) must be provided on the PCI_EN pin (setting

None

MAC_EN = 0

PCI_EN = 1 at reset)

(disabled)⁽¹⁾

XSP_DO/MDIO

P5

To enable the MDIO peripheral (which also enables the

EMAC peripheral), an external pullup resistor (1 kΩ) must

be provided on the MAC_EN pin (setting MAC_EN = 1 at

reset)

HAS/PPAR

P3

P1

R3

R2

T2

M1

HAS

HCNTL1/PDEVSEL

HCNTL0/PSTOP

HDS1/PSERR

HDS2/PCBE1

HR/W/PCBE2

HCNTL1

HCNTL0

HDS1

By default, HPI is enabled upon reset (PCI is disabled).

HDS2

PCI_EN = 0 (disabled)⁽¹⁾

To enable the PCI peripheral, an external pullup resistor

(1 kΩ) must be provided on the PCI_EN pin (setting

PCI_EN = 1 at reset).

HR/W

HHWIL

(HPI16 only)

HHWIL/PTRDY

N3

HINT/PFRAME

HCS/PPERR

HRDY/PIRDY

N4

R1

N1

HINT

HCS

HRDY

64

Device Configurations

TMS320DM642

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 3-8. DM642 Device Multiplexed Pin Configurations⁽¹⁾(continued)

MULTIPLEXED PINS

NAME

DEFAULT

FUNCTION

DEFAULT

SETTING

DESCRIPTION

NO.

By default, HPI is enabled upon reset (PCI is disabled).

(2)

PCI_EN = 0 (disabled)⁽¹⁾

To enable the PCI peripheral, an external pullup resistor

(1 kΩ) must be provided on the PCI_EN pin (setting

PCI_EN = 1 at reset).

HD[23,15:0]/AD[23,15:0]

HD[23, 15:0]

HD31/AD31/MRCLK

HD30/AD30/MCRS

HD29/AD29/MRXER

HD28/AD28/MRXDV

HD27/AD27/MRXD3

HD26/AD26/MRXD2

HD25/AD25/MRXD1

HD24/AD24/MRXD0

HD22/AD22/MTCLK

HD21/AD21/MCOL

HD20/AD20/MTXEN

HD19/AD19/MTXD3

HD18/AD18/MTXD2

HD17/AD17/MTXD1

HD16/AD16/MTXD0

G1

H3

G2

J4

HD31

HD30

HD29

HD28

HD27

HD26

HD25

HD24

HD22

HD21

HD20

HD19

HD18

HD17

HD16

H2

J3

By default, HPI is enabled upon reset (PCI is disabled).

To enable the PCI peripheral, an external pullup resistor

J1

PCI_EN = 0 (disabled)⁽¹⁾(1 kΩ) must be provided on the PCI_EN pin (setting

K4

L4

MAC_EN = 0

PCI_EN = 1 at reset).

(disabled)⁽¹⁾

To enable the EMAC peripheral, an external pullup resistor

(1 kΩ) must be provided on the MAC_EN pin (setting

MAC_EN = 1 at reset).

K2

L3

L2

M4

M2

M3

3.6 Debugging Considerations

It is recommended that external connections be provided to device configuration pins, including

TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, VDAC/GP0[8]/PCI66, HD5/AD5, PCI_EN, and

TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on these pins, providing external

connectivity adds convenience to the user in debugging and flexibility in switching operating modes.

Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do

not oppose the internal pullup/pulldown resistors on these non-configuration pins with external

pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these

signals must be driven to the default state of the pins at reset, or not be driven at all.

For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.

Device Configurations

65

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3.7 Configuration Examples

Figure 3-6 through Figure 3-8 illustrate examples of peripheral selections that are configurable on the

DM642 device.

66

Device Configurations

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64

AED[63:0]

PCI

EMIFA

AECLKIN, AARDY, AHOLD

AEA[22:3], ACE[3:0], ABE[7:0],

AECLKOUT1, AECLKOUT2,

ASDCKE, ASOE3, APDT,

AHOLDA, ABUSREQ,

AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE,

16

HD[15:0]

Clock

and

System

HPI

(16-Bit)

HRDY, HINT

HCNTL0, HCNTL1,

HHWIL, HAS, HR/W,

HCS, HDS1, HDS2

AAWE/ASDWE/ASWE

CLKIN,

CLKMODE0, CLKMODE1

MTXD[3:0], MTXEN

EMAC

MDIO

TIMER2

TIMER1

TIMER0

CLKOUT4, CLKOUT6, PLLV

MRXD[3:0], MRXER,

MRXDV, MCOL, MCRS,

MTCLK, MRCLK

TINP1

MDIO, MDCLK

TOUT1/LENDIAN

(A)

STCLK

TINP0

VP0

(20-Bit)

VP0CLK0

VP0CLK1,

VP0CTL[2:0],

VP0D[19:0]

TOUT0/MACEN

GP0

and

EXT_INT

GP0[15:9, 3:0]

GP0[7:4]

McBSP0

McASP0 Control

McASP0 Data

SCL0

SDA0

I2C0

VIC

McBSP1

VDAC/GP0[8]/PCI66

(A)

STCLK

VP2

(20-Bit)

VP1

(20-Bit)

VP1CLK0

VP2CLK0

VP1CLK1,

VP1CTL[2:0],

VP1D[19:0]

VP2CLK1,

VP2CTL[2:0],

VP2D[19:0]

PERCFG Register Value:

External Pins:

0x0000 0078

PCI_EN = 0

GP0[3]/PCIEEAI = 0 HD5 = 0 TOUT0/MAC_EN = 1

Shading denotes a peripheral module not available for this configuration.

A. STCLK supports all three video ports (VP2, VP1, and VP0).

Figure 3-6. Configuration Example A

(3 20-Bit Video Ports + HPI + EMAC + MDIO + I2C0 + EMIF + 3 Timers)

Device Configurations

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64

AED[63:0]

PCI

EMIFA

AECLKIN, AARDY, AHOLD

AEA[22:3], ACE[3:0], ABE[7:0],

AECLKOUT1, AECLKOUT2,

ASDCKE, ASOE3, APDT,

AHOLDA, ABUSREQ,

AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE,

16

HD[15:0]

Clock

and

System

HPI

HRDY, HINT

(16-Bit)

HCNTL0, HCNTL1,

HHWIL, HAS, HR/W,

HCS, HDS1, HDS2

AAWE/ASDWE/ASWE

CLKIN,

CLKMODE0, CLKMODE1

MTXD[3:0], MTXEN

EMAC

MRXD[3:0], MRXER,

MRXDV, MCOL, MCRS,

MTCLK, MRCLK

TIMER2

TIMER1

TIMER0

CLKOUT4, CLKOUT6, PLLV

TINP1

MDIO, MDCLK

MDIO

TOUT1/LENDIAN

(A)

STCLK

TINP0

VP0

VP0CLK0

(10-Bit)

VP0CLK1,

VP0CTL[2:0],

VP0D[19:10]

TOUT0/MACEN

GP0

and

EXT_INT

GP0[15:9, 3:0]

GP0[7:4]

CLKR0, FSR0, DR0,

CLKS0, DX0, FSX0,

CLKX0

McBSP0

McASP0 Control

McASP0 Data

SCL0

SDA0

I2C0

VIC

CLKR1, FSR1, DR1,

CLKS1, DX1, FSX1,

CLKX1

McBSP1

VDAC/GP0[8]/PCI66

(A)

STCLK

VP1

(10-Bit)

VP2

(20-Bit)

VP1CLK0

VP2CLK0

VP2CLK1,

VP2CTL[2:0],

VP2D[19:0]

VP1CLK1,

VP1CTL[2:0],

VP1D[19:10]

PERCFG Register Value:

Extenal Pins:

0x0000 007E

PCI_EN = 0

GP0[3]/PCIEEAI = 0

HD5 = 0

TOUT0/MAC_EN = 1

Shading denotes a peripheral module not available for this configuration.

A. STCLK supports all three video ports (VP2, VP1, and VP0).

Figure 3-7. Configuration Example B

(2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO + I2C0 + EMIF)

[Possible Video IP Phone Application]

68

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64

AED[63:0]

PCI

EMIFA

AECLKIN, AARDY, AHOLD

AEA[22:3], ACE[3:0], ABE[7:0],

AECLKOUT1, AECLKOUT2,

ASDCKE, ASOE3, APDT,

AHOLDA, ABUSREQ,

AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE,

16

HD[15:0]

Clock

and

System

HPI

(16-Bit)

HRDY, HINT

HCNTL0, HCNTL1,

HHWIL, HAS, HR/W,

HCS, HDS1, HDS2

AAWE/ASDWE/ASWE

CLKIN,

CLKMODE0, CLKMODE1

MTXD[3:0], MTXEN

EMAC

MDIO

TIMER2

TIMER1

TIMER0

CLKOUT4, CLKOUT6, PLLV

MRXD[3:0], MRXER,

MRXDV, MCOL, MCRS,

MTCLK, MRCLK

TINP1

MDIO, MDCLK

TOUT1/LENDIAN

(A)

STCLK

TINP0

VP0

(10-Bit)

VP0CLK0

VP0CLK1,

VP0CTL[2:0],

VP0D[9:0]

TOUT0/MACEN

GP0

and

EXT_INT

GP0[15:9, 3:0]

GP0[7:4]

McBSP0

AHCLKX0, AFSX0,

ACLKX0, AMUTE0,

AMUTEIN0, AHCLKR0,

AFSR0, ACLKR0

McASP0 Control

McASP0 Data

SCL0

SDA0

I2C0

VIC

AXR0[7:0]

McBSP1

VDAC/GP0[8]/PCI66

(A)

STCLK

VP2

(20-Bit)

VP1

(10-Bit)

VP1CLK0

VP2CLK0

VP1CLK1,

VP1CTL[2:0],

VP1D[9:0]

VP2CLK1,

VP2CTL[2:0],

VP2D[19:0]

PERCFG Register Value:

Extenal Pins:

0x0000 0079

PCI_EN = 0

GP0[3]/PCIEEAI = 0

HD5 = 0

TOUT0/MAC_EN = 1

Shading denotes a peripheral module not available for this configuration.

A. STCLK supports all three video ports (VP2, VP1, and VP0).

Figure 3-8. Configuration Example C

(1 20-Bit Video Port, 2 10-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF)

[Possible Set-Top Box Application]

Device Configurations

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4 Device Operating Conditions

4.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(1)

(Unless Otherwise Noted)

(2)

CV_DD

–0.3 V to 1.8 V

–0.3 V to 4 V

Supply voltage ranges:

(2)

DV_DD

(except PCI), V_I

–0.3 V to 4 V

Input voltage ranges:

(PCI), V_IP

–0.5 V to DV_DD+ 0.5 V

–0.3 V to 4 V

(except PCI), V_O

Output voltage ranges:

(PCI), V_OP

–0.5 V to DV_DD+ 0.5 V

0°C to 90°C

(default)

Operating case temperature ranges, T_C:

(A version) [A-500, A-600]

–40°C to 105°C

–65°C to 150°C

–40°C to 125°C

500

Storage temperature range, T_stg

:

Temperature Range

Number of Cycles

Package Temperature Cycling:

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS.

4.2 Recommended Operating Conditions

MIN NOM

MAX UNIT

(1)

Supply voltage, Core (–500 device)

1.14

1.36

3.14

0

1.2

1.4

3.3

0

1.26

1.44

3.46

0

V

CV_DD

(1)

Supply voltage, Core (A-500, A-600, -600, -720 devices)

Supply voltage, I/O

DV_DD

V_SS

V_IH

V

Supply ground

V

High-level input voltage (except PCI)

Low-level input voltage (except PCI)

Input voltage (PCI)

2

V

V_IL

0.8

DV_DD+ 0.5

0.3DV_DD

4.3⁽²⁾

V

V_IP

–0.5

0.5DV_DD

–0.5

V

V_IHP

V_ILP

V_OS

High-level input voltage (PCI)

Low-level input voltage (PCI)

V

(2)

Maximum voltage during overshoot/undershoot

–1.0

V

Default

Operating case temperature

A version (A-500 only)

0

90

°C

T_C

–40

105

(1) Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V,

1.3 V, 1.35 V, 1.4 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin

configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power

Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system's ability to easily adapt to future

versions of C64x devices.

(2) The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.

70

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4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Case Temperature (Unless Otherwise Noted)

(1)

PARAMETER

High-level output voltage (except PCI) DV_DD= MIN, I_OH= MAX

High-level output voltage (PCI) I_OHP= –0.5 mA, DV_DD= 3.3 V

Low-level output voltage (except PCI) DV_DD= MIN, I_OL= MAX

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OH

2.4

V

(2)

V_OHP

V_OL

0.9DV_DD

0.4

V

(2)

V_OLP

Low-level output voltage (PCI)

I_OLP= 1.5 mA, DV_DD= 3.3 V

0.1DV_DD

V_I= V_SSto DV_DDno opposing internal

resistor

±10

150

–50

uA

V_I= V_SSto DV_DDopposing internal pullup

I_I

Input current (except PCI)

50

100

(3)

resistor

V_I= V_SSto DV_DDopposing internal

–150

–100

(3)

pulldown resistor

(4)

I_IP

Input leakage current (PCI)

0 < V_IP< DV_DD= 3.3 V

±10

–16

uA

EMIF, CLKOUT4, CLKOUT6, EMUx

mA

Video Ports, Timer, TDO, GPIO

(Excluding GP0[15:9, 2, 1]), McBSP

I_OH

High-level output current

–8

mA

PCI/HPI

–0.5⁽²⁾

16

mA

EMIF, CLKOUT4, CLKOUT6, EMUx

Video Ports, Timer, TDO, GPIO

(Excluding GP0[15:9, 2, 1]), McBSP

8

mA

I_OL

Low-level output current

SCL0 and SDA0

3

1.5⁽²⁾

±10

mA

uA

PCI/HPI

I_OZ

Off-state output current

Core supply current⁽⁵⁾

V_O= DV_DDor 0 V

CV_DD= 1.4 V, CPU clock = 720 MHz

CV_DD= 1.4 V, CPU clock = 600 MHz

CV_DD= 1.2 V, CPU clock = 500 MHz

DV_DD= 3.3 V, CPU clock = 720 MHz

DV_DD= 3.3 V, CPU clock = 600 MHz

DV_DD= 3.3 V, CPU clock = 500 MHz

1090

890

620

210

165

mA

pF

I_CDD

I_DDD

I/O supply current⁽⁵⁾

C_i

Input capacitance

Output capacitance

10

C_o

pF

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2) These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Table 5-3 and

Table 5-4, respectively.

(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(4) PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.

(5) Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for –600 and –720 speeds

(100-MHz EMIF for –500 speed). This model represents a device performing high-DSP-activity operations 50% of the time, and the

remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

•

High-DSP-Activity Model:

–

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

–

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

•

Low-DSP-Activity Model:

–

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

–

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power

Consumption Summary application report (literature number SPRA962).

Device Operating Conditions

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5 DM642 Peripheral Information and Electrical Specifications

5.1 Parameter Information

5.1.1 Parameter Information Device-Specific Information

Tester Pin Electronics

Data Sheet Timing Reference Point

42 Ω

3.5 nH

Output

Under

Test

Transmission Line

Z0 = 50 Ω

(see note)

Device Pin

(see note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The

transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data

sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 5-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

5.1.1.1 Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.

V

ref

= 1.5 V

Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks,

V_OLMAX and V_OHMIN for output clocks, V_ILPMAX and V_IHPMIN for PCI input clocks, and V_OLPMAX and

V_OHPMIN for PCI output clocks.

V

ref

= V MIN (or V MIN or

IH OH

V

IHP

MIN or V

MIN)

OHP

V

ref

= V MAX (or V MAX or

IL OL

V

ILP

MAX or V

MAX)

OLP

Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels

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5.1.1.2 Signal Transition Rates

All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).

5.1.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external

device and from the external device to the DSP. This round-trip delay tends to negatively impact the input

setup time margin, but also tends to improve the input hold time margins (see Table 5-1 and Figure 5-4).

Figure 5-4 represents a general transfer between the DSP and an external device. The figure also

represents board route delays and how they are perceived by the DSP and the external device.

Table 5-1. Board-Level Timing Example

(see Figure 5-4)

NO.

1

DESCRIPTION

Clock route delay

2

Minimum DSP hold time

3

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

4

5

6

7

8

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

9

10

11

DM642 Peripheral Information and Electrical Specifications

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ECLKOUTx

(Output from DSP)

1

ECLKOUTx

(Input to External Device)

2

3

(A)

Control Signals

(Output from DSP)

4

5

6

Control Signals

(Input to External Device)

7

8

(B)

Data Signals

(Output from External Device)

9

10

11

(B)

Data Signals

(Input to DSP)

A. Control signals include data for Writes.

B. Data signals are generated during Reads from an external device.

Figure 5-4. Board-Level Input/Output Timings

5.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IHand V_IL(or between V_ILand V_IH) in a monotonic

manner.

5.3 Power Supplies

For more information regarding TI's power management products and suggested devices to power TI

DSPs, visit www.ti.com/dsppower.

5.3.1 Power-Supply Sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time

(>1 second) if the other supply is below the proper operating voltage.

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5.3.2 Power-Supply Design Considerations

A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and

I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 5-5).

I/O Supply

DV

DD

Schottky

Diode

C6000

DSP

Core Supply

CV

DD

V

SS

GND

Figure 5-5. Schottky Diode Diagram

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize

inductance and resistance in the power delivery path. Additionally, when designing for high-performance

applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes

for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

5.3.3 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for

the core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more

than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better

because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass

caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can

be obtained in a small package) should be next closest. TI recommends no less than 8 small and

8 medium caps per supply (32 total) be placed immediately next to the BGA vias, using the "interior" BGA

space and at least the corners of the "exterior".

Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on

the order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per

supply (8 total) should be placed outside of the BGA.

Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of

any component, verification of capacitor availability over the product’s production lifetime should be

considered.

5.3.4 Peripheral Power-Down Operation

The DM642 device can be powered down in three ways:

•

Power-down due to pin configuration

Power-down due to software configuration – relates to the default state of the peripheral configuration

bits in the PERCFG register.

•

Power-down during run-time via software configuration

On the DM642 device, the HPI, PCI, and EMAC and MDIO peripherals are controlled (selected) at the pin

level during chip reset (e.g., PCI_EN, HD5, and MAC_EN pins).

DM642 Peripheral Information and Electrical Specifications

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The McASP0, McBSP0, McBSP1, VP0, VP1, VP2, and I2C0 peripheral functions are selected via the

peripheral configuration (PERCFG) register bits.

For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the

Device Configurations section of this document.

5.3.5 Power-Down Modes Logic

Figure 5-6 shows the power-down mode logic on the DM642.

CLKOUT4

CLKOUT6

Internal Clock Tree

Clock

Distribution

and Dividers

PD1

PD2

IFR

Power-

Internal

Peripherals

Clock

PLL

IER

CSR

Down

Logic

PWRD

CPU

PD3

TMS320DM642

CLKIN

RESET

A. External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.

Figure 5-6. Power-Down Mode Logic^(A)

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5.3.6 Triggering, Wake-up, and Effects

The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits

15–10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 5-7 and

described in Table 5-2. When writing to the CSR, all bits of the PWRD field should be set at the same

time. Logic 0 should be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is

discussed in detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number

SPRU189).

31

16

8

(See NOTE)

15

14

13

12

11

10

9

Enable or

Non-Enabled

Interrupt Wake

Enabled

Interrupt Wake

Reserved

PD3

PD2

PD1

(See NOTE)

R/W-0

7

R/W-0

0

(See NOTE)

Legend: R/W = Readable/Writable, -n = value after reset

NOTE: The shaded bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 5-7. PWRD Field of the CSR Register

A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR

before the PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in

the CSR to account for this delay.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction

where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will

be executed first, then the program execution returns to the instruction where PD1 took effect. In the case

with an enabled interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER)

must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the

instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 5-2 summarizes all the power-down

modes.

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Table 5-2. Characteristics of the Power-Down Modes

PRWD Field

(BITS 15–10)

POWER-DOWN

WAKE-UP METHOD

EFFECT ON CHIP'S OPERATION

MODE

No power-down

PD1

000000

001001

—

Wake by an enabled interrupt

CPU halted (except for the interrupt logic)

Power-down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU's logic from

switching. During PD1, EDMA transactions can proceed be-

tween peripherals and internal memory.

Wake by an enabled or

non-enabled interrupt

010001

PD1

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

halted. All register and internal RAM contents are preserved. All

functional I/O "freeze" in the last state when the PLL clock is

turned off.

011010

PD2⁽¹⁾

Wake by a device reset

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O "freeze"

in the last state when the PLL clock is turned off. Following

reset, the PLL needs time to re-lock, just as it does following

power-up.

011100

PD3⁽¹⁾

Wake by a device reset

Wake-up from PD3 takes longer than wake-up from PD2

because the PLL needs to be re-locked, just as it does following

power-up.

All others

Reserved

—

(1) When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in

nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these

conditions, peripherals will not operate according to specifications.

5.3.7 C64x Power-Down Mode with an Emulator

If user power-down modes are programmed, and an emulator is attached, the modes will be masked to

allow the emulator access to the system. This condition prevails until the emulator is reset or the cable is

removed from the header. If power measurements are to be performed when in a power-down mode, the

emulator cable should be removed.

When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution

command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will

fail. A DSP reset will be required to get the DSP out of PD2/PD3.

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5.4 Enhanced Direct Memory Access (EDMA) Controller

The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and

the device peripherals on the DM642 DSP. These data transfers include cache servicing, non-cacheable

memory accesses, user-programmed data transfers, and host accesses.

5.4.1 EDMA Device-Specific Information

5.4.1.1 EDMA Channel Synchronization Events

The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external

memory. Table 5-3 lists the source of C64x EDMA synchronization events associated with each of the

programmable EDMA channels. For the DM642 device, the association of an event to a channel is fixed;

each of the EDMA channels has one specific event associated with it. These specific events are captured

in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable

registers (EERL, EERH). The priority of each event can be specified independently in the transfer

parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and

how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the

TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature

number SPRU234).

Table 5-3. TMS320DM642 EDMA Channel Synchronization Events⁽¹⁾

EDMA

CHANNEL

EVENT NAME

EVENT DESCRIPTION

0

1

DSP_INT

TINT0

HPI/PCI-to-DSP interrupt

Timer 0 interrupt

2

TINT1

Timer 1 interrupt

3

SD_INTA

EMIFA SDRAM timer interrupt

GP0 event 4/External interrupt pin 4

GP0 event 5/External interrupt pin 5

GP0 event 6/External interrupt pin 6

GP0 event 7/External interrupt pin 7

GP0 event 0

4

GPINT4/EXT_INT4

GPINT5/EXT_INT5

GPINT6/EXT_INT6

GPINT7/EXT_INT7

GPINT0

5

6

7

8

9

GPINT1

GP0 event 1

10

11

12

13

14

15

16

17

18

19

20–23

24

25

26

GPINT2

GP0 event 2

GPINT3

GP0 event 3

XEVT0

McBSP0 transmit event

McBSP0 receive event

McBSP1 transmit event

McBSP1 receive event

REVT0

XEVT1

REVT1

VP0EVTYA

VP0EVTUA

VP0EVTVA

TINT2

VP0 Channel A Y event DMA request

VP0 Channel A Cb event DMA request

VP0 Channel A Cr event DMA request

Timer 2 interrupt

–

None

VP0EVTYB

VP0EVTUB

VP0EVTVB

VP0 Channel B Y event DMA request

VP0 Channel B Cb event DMA request

VP0 Channel B Cr event DMA request

(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced

Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).

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Table 5-3. TMS320DM642 EDMA Channel Synchronization Events (continued)

EDMA

CHANNEL

EVENT NAME

EVENT DESCRIPTION

27–31

32

–

None

AXEVTE0

AXEVTO0

AXEVT0

McASP0 transmit even event

McASP0 transmit odd event

McASP0 transmit event

McASP0 receive even event

McASP0 receive odd event

McASP0 receive event

33

34

35

AREVTE0

AREVTO0

AREVT0

36

37

38

VP1EVTYB

VP1EVTUB

VP1EVTVB

VP2EVTYB

VP2EVTUB

VP2EVTVB

ICREVT0

ICXEVT0

–

VP1 Channel B Y event DMA request

VP1 Channel B Cb event DMA request

VP1 Channel B Cr event DMA request

VP2 Channel B Y event DMA request

VP2 Channel B Cb event DMA request

VP2 Channel B Cr event DMA request

I2C0 receive event

39

40

41

42

43

44

45

I2C0 transmit event

46–47

48

None

GPINT8

GP0 event 8

49

GPINT9

GP0 event 9

50

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

VP1EVTYA

VP1EVTUA

VP1EVTVA

VP2EVTYA

VP2EVTUA

VP2EVTVA

–

GP0 event 10

51

GP0 event 11

52

GP0 event 12

53

GP0 event 13

54

GP0 event 14

55

GP0 event 15

56

VP1 Channel A Y event DMA request

VP1 Channel A Cb event DMA request

VP1 Channel A Cr event DMA request

VP2 Channel A Y event DMA request

VP2 Channel A Cb event DMA request

VP2 Channel A Cr event DMA request

None

57

58

59

60

61

62–63

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5.4.2 EDMA Peripheral Register Description(s)

Table 5-4. EDMA Registers (C64x)

HEX ADDRESS RANGE

01A0 0800 – 01A0 FF98

01A0 FF9C

ACRONYM

–

REGISTER NAME

Reserved

EPRH

CIPRH

CIERH

CCERH

ERH

Event polarity high register

01A0 FFA4

Channel interrupt pending high register

Channel interrupt enable high register

Channel chain enable high register

Event high register

01A0 FFA8

01A0 FFAC

01A0 FFB0

01A0 FFB4

EERH

ECRH

ESRH

PQAR0

PQAR1

PQAR2

PQAR3

EPRL

PQSR

CIPRL

CIERL

CCERL

ERL

Event enable high register

Event clear high register

01A0 FFB8

01A0 FFBC

Event set high register

01A0 FFC0

Priority queue allocation register 0

Priority queue allocation register 1

Priority queue allocation register 2

Priority queue allocation register 3

Event polarity low register

01A0 FFC4

01A0 FFC8

01A0 FFCC

01A0 FFDC

01A0 FFE0

Priority queue status register

Channel interrupt pending low register

Channel interrupt enable low register

Channel chain enable low register

Event low register

01A0 FFE4

01A0 FFE8

01A0 FFEC

01A0 FFF0

01A0 FFF4

EERL

ECRL

ESRL

–

Event enable low register

01A0 FFF8

Event clear low register

01A0 FFFC

Event set low register

01A1 0000 – 01A3 FFFF

Reserved

Table 5-5. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE

0200 0000

ACRONYM

QOPT

REGISTER NAME

QDMA options parameter register

QDMA source address register

QDMA frame count register

QDMA destination address register

QDMA index register

0200 0004

QSRC

QCNT

0200 0008

0200 000C

QDST

0200 0010

QIDX

0200 0014 – 0200 001C

0200 0020

Reserved

QSOPT

QSSRC

QSCNT

QSDST

QSIDX

QDMA pseudo options register

QDMA psuedo source address register

QDMA psuedo frame count register

QDMA destination address register

QDMA psuedo index register

0200 0024

0200 0028

0200 002C

0200 0030

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Table 5-6. EDMA Parameter RAM (C64x)⁽¹⁾

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

Parameters for Event 0 (6 words)

COMMENTS

Parameters for Event 0

(6 words) or Reload/Link Par-

ameters for other Event

01A0 0000 – 01A0 0017

–

01A0 0018 – 01A0 002F

01A0 0030 – 01A0 0047

01A0 0048 – 01A0 005F

01A0 0060 – 01A0 0077

01A0 0078 – 01A0 008F

01A0 0090 – 01A0 00A7

01A0 00A8 – 01A0 00BF

01A0 00C0 – 01A0 00D7

01A0 00D8 – 01A0 00EF

01A0 00F0 – 01A0 00107

01A0 0108 – 01A0 011F

01A0 0120 – 01A0 0137

01A0 0138 – 01A0 014F

01A0 0150 – 01A0 0167

01A0 0168 – 01A0 017F

01A0 0180 – 01A0 0197

01A0 0198 – 01A0 01AF

...

–

Parameters for Event 1 (6 words)

Parameters for Event 2 (6 words)

Parameters for Event 3 (6 words)

Parameters for Event 4 (6 words)

Parameters for Event 5 (6 words)

Parameters for Event 6 (6 words)

Parameters for Event 7 (6 words)

Parameters for Event 8 (6 words)

Parameters for Event 9 (6 words)

Parameters for Event 10 (6 words)

Parameters for Event 11 (6 words)

Parameters for Event 12 (6 words)

Parameters for Event 13 (6 words)

Parameters for Event 14 (6 words)

Parameters for Event 15 (6 words)

Parameters for Event 16 (6 words)

Parameters for Event 17 (6 words)

...

01A0 05D0 – 01A0 05E7

01A0 05E8 – 01A0 05FF

–

Parameters for Event 62 (6 words)

Parameters for Event 63 (6 words)

Reload/Link Parameters for

other Event 0–15

01A0 0600 – 01A0 0617

–

Reload/link parameters for Event 0 (6 words)

01A0 0618 – 01A0 062F

...

Reload/link parameters for Event 1 (6 words)

...

01A0 07E0 – 01A0 07F7

01A0 07F8 – 01A0 080F

01A0 0810 – 01A0 0827

...

–

Reload/link parameters for Event 20 (6 words)

Reload/link parameters for Event 21 (6 words)

Reload/link parameters for Event 22 (6 words)

...

01A0 13C8 – 01A0 13DF

01A0 13E0 – 01A0 13F7

01A0 13F8 – 01A0 13FF

01A0 1400 – 01A3 FFFF

–

Reload/link parameters for Event 147 (6 words)

Reload/link parameters for Event 148 (6 words)

Scratch pad area (2 words)

Reserved

(1) The DM642 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words

each] that can be used to reload/link EDMA transfers.

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5.5 Interrupts

5.5.1 Interrupt Sources and Interrupt Selector

The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 5-7. The highest-priority

interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four

interrupts (INT_00–INT_03) are non-maskable and fixed. The remaining interrupts (INT_04–INT_15) are

maskable and default to the interrupt source specified in Table 5-7. The interrupt source for interrupts

4–15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the

Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).

Table 5-7. DM642 DSP Interrupts

INTERRUPT

CPU

INTERRUPT

NUMBER

SELECTOR

VALUE

(BINARY)

SELECTOR

CONTROL

REGISTER

INTERRUPT

EVENT

INTERRUPT SOURCE

INT_00⁽¹⁾

INT_01⁽¹⁾

–

RESET

NMI

–

INT_02⁽¹⁾

–

Reserved

Reserved. Do not use.

INT_03⁽¹⁾

–

Reserved

Reserved. Do not use.

INT_04⁽²⁾

INT_05⁽²⁾

INT_06⁽²⁾

INT_07⁽²⁾

INT_08⁽²⁾

INT_09⁽²⁾

INT_10⁽²⁾

INT_11⁽²⁾

INT_12⁽²⁾

INT_13⁽²⁾

INT_14⁽²⁾

INT_15⁽²⁾

MUXL[4:0]

00100

00101

00110

00111

01000

01001

00011

01010

01011

00000

00001

00010

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

GPINT4/EXT_INT4

GPINT5/EXT_INT5

GPINT6/EXT_INT6

GPINT7/EXT_INT7

EDMA_INT

EMU_DTDMA

SD_INTA

GP0 interrupt 4/External interrupt pin 4

GP0 interrupt 5/External interrupt pin 5

GP0 interrupt 6/External interrupt pin 6

GP0 interrupt 7/External interrupt pin 7

EDMA channel (0 through 63) interrupt

EMU DTDMA

MUXL[9:5]

MUXL[14:10]

MUXL[20:16]

MUXL[25:21]

MUXL[30:26]

MUXH[4:0]

EMIFA SDRAM timer interrupt

EMU real-time data exchange (RTDX) receive

EMU RTDX transmit

MUXH[9:5]

EMU_RTDXRX

EMU_RTDXTX

DSP_INT

MUXH[14:10]

MUXH[20:16]

HPI/PCI-to-DSP interrupt

Timer 0 interrupt

MUXH[25:21]

TINT0

MUXH[30:26]

TINT1

Timer 1 interrupt

–

XINT0

McBSP0 transmit interrupt

McBSP0 receive interrupt

McBSP1 transmit interrupt

McBSP1 receive interrupt

GP0 interrupt 0

RINT0

XINT1

RINT1

GPINT0

Reserved

Reserved. Do not use.

Reserved

Reserved. Do not use.

TINT2

Timer 2 interrupt

Reserved

Reserved. Do not use.

Reserved

Reserved. Do not use.

ICINT0

I2C0 interrupt

Reserved

Reserved. Do not use.

EMAC_MDIO_INT

VPINT0

EMAC/MDIO interrupt

VP0 interrupt

VPINT1

VP1 interrupt

(1) Interrupts INT_00 through INT_03 are non-maskable and fixed.Interrupts

(2) INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.

Table 5-7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources

and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).

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Table 5-7. DM642 DSP Interrupts (continued)

INTERRUPT

SELECTOR

CONTROL

REGISTER

CPU

INTERRUPT

NUMBER

SELECTOR

VALUE

(BINARY)

INTERRUPT

EVENT

INTERRUPT SOURCE

–

11011

11100

VPINT2

AXINT0

ARINT0

Reserved

VP2 interrupt

McASP0 transmit interrupt

McASP0 receive interrupt

Reserved. Do not use.

11101

11110 – 11111

5.5.2 Interrupts Peripheral Register Description(s)

Table 5-8. Interrupt Selector Registers (C64x)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

Interrupt multiplexer high

COMMENTS

Selects which interrupts drive CPU

interrupts 10–15 (INT10–INT15)

019C 0000

MUXH

Selects which interrupts drive CPU

interrupts 4–9 (INT04–INT09)

019C 0004

MUXL

Interrupt multiplexer low

Sets the polarity of the external inter-

rupts (EXT_INT4–EXT_INT7)

019C 0008

EXTPOL

–

External interrupt polarity

Reserved

019C 000C – 019F FFFF

5.5.3 External Interrupts Electrical Data/Timing

Table 5-9. Timing Requirements for External Interrupts⁽¹⁾(see Figure 5-8)

–500

–600

–720

NO.

UNIT

MIN

MAX

Width of the NMI interrupt pulse low

4P

8P

4P

8P

ns

1

2

t_w(ILOW)

Width of the EXT_INT interrupt pulse low

Width of the NMI interrupt pulse high

Width of the EXT_INT interrupt pulse high

t_w(IHIGH)

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

2

1

EXT_INTx, NMI

Figure 5-8. External/NMI Interrupt Timing

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5.6 Reset

A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The

RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core

and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held

low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should

be at their proper operating conditions and CLKIN should also be running at the correct frequency. When

PCI is enabled, the PCI input clock (PCLK) must be running prior to deasserting RESET as well.

When the PCI peripheral is enabled, a WARMRESET can be performed via the host. A WARMRESET

performs the same functionality as a hardware reset, but does not relatch the boot configuration pins.

Whatever boot configuration that was latched on the previous hardware reset will be performed during the

WARMRESET.

A hardware reset does not reset the PCI peripheral state machine. The PCI state machine is reset via the

PRST signal. The PRST signal does not affect the DSP.

Emulation resets, done using Code Composer Studio™ IDE, have the same affect as a PCI

WARMRESET.

For information on peripheral selection at the rising edge of RESET, see the Device Configuration section

of this data manual.

5.6.1 Reset Electrical Data/Timing

Table 5-10. Timing Requirements for Reset (see Figure 5-9)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

t_w(RST)

Width of the RESET pulse

250

4E or 4C⁽²⁾

4P⁽³⁾

µs

ns

(1)

16

17

18

t_su(boot)

Setup time, boot configuration bits valid before RESET high

(1)

t_h(boot)

Hold time, boot configuration bits valid after RESET high

Setup time, PCLK active before RESET high⁽⁴⁾

t_{su(PCLK-RSTH)}

32N

(1) AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 are the boot configuration pins during device reset.

(2) E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.

Select the MIN parameter value, whichever value is larger.

(3) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(4) N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met.

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Table 5-11. Switching Characteristics Over Recommended Operating Conditions During Reset^(1)(2)(3)

(see Figure 5-9)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

3P + 20E

8P + 20E

2

3

t_d(RSTL-ECKI)

Delay time, RESET low to AECLKIN synchronized internally

Delay time, RESET high to AECLKIN synchronized internally

Delay time, RESET low to AECLKOUT1 high impedance

Delay time, RESET high to AECLKOUT1 valid

Delay time, RESET low to EMIF Z high impedance

Delay time, RESET high to EMIF Z valid

2E

ns

t_d(RSTH-ECKI)

4

t_{d(RSTL-ECKO1HZ)}

t_{d(RSTH-ECKO1V)}

t_{d(RSTL-EMIFZHZ)}

t_{d(RSTH-EMIFZV)}

t_{d(RSTL-EMIFHIV)}

t_{d(RSTH-EMIFHV)}

t_{d(RSTL-EMIFLIV)}

t_{d(RSTH-EMIFLV)}

t_{d(RSTL-LOWIV)}

t_d(RSTH-LOWV)

t_d(RSTL-ZHZ)

5

8P + 20E

3P + 4E

6

2E

16E

2E

7

8P + 20E

8

Delay time, RESET low to EMIF high group invalid

Delay time, RESET high to EMIF high group valid

Delay time, RESET low to EMIF low group invalid

Delay time, RESET high to EMIF low group valid

Delay time, RESET low to low group invalid

9

8P + 20E

11P

10

11

12

13

14

15

2E

0

Delay time, RESET high to low group valid

Delay time, RESET low to Z group high impedance

Delay time, RESET high to Z group valid

0

t_d(RSTH-ZV)

2P

8P

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(3) EMIF Z group consists of: AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE,

AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT

EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)

EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)

Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO all of which apply only when PCI EEPROM is enabled (with

PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the XSP_CLK/MDCLK and XSP_DO/MDIO pins are in the Z group. For more details on

the PCI configuration pins, see the Device Configurations section of this data sheet.

Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0,

VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0, VP1D[8]/CLKR1, VP0D[7]/FSR0,

VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,

GP0[13]/PINTA, GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY

(16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0].

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CLKOUT4

CLKOUT6

1

RESET

PCLK

18

2

4

3

5

AECLKIN

AECLKOUT1

AECLKOUT2

(A)(B)

6

7

EMIF Z Group

9

8

(A)

EMIF High Group

EMIF Low Group

11

10

12

14

13

15

(A)

Low Group

(A)(B)

Z Group

16

17

Boot and Device

(C)

Configuration Inputs

A. EMIF

Z

group consists of: AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT

AAWE/ASDWE/ASWE,

EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)

EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)

Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO all of which apply only when PCI

EEPROM is enabled (with PCI_EN

XSP_DO/MDIO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations

section of this data sheet.

= 1 and MCBSP2_EN = 0). Otherwise, the XSP_CLK/MDCLK and

Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO,

VP0D[2]/CLKX0, VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0,

VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3,

HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA, GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR,

HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY,

HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0].

B. If AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing

contention between parameters 6, 7, 14, 15, 16, and 17.

C. Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5.

The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.

Figure 5-9. Reset Timing^(A)

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5.7 Clock PLL

The PLL controller features hardware-configurable PLL multiplier controller, dividers (/2, /4, /6, and /8),

and reset controller. The PLL controller accepts an input clock, as determined by the logic state on the

CLKMODE[1:0] pins, from the CLKIN pin. The resulting clock outputs are passed to the DSP core,

peripherals, and other modules inside the C6000™ DSP.

5.7.1 Clock PLL Device-Specific Information

Most of the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This

source clock either drives the PLL, which multiplies the source clock frequency to generate the internal

CPU clock, or bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed.

Figure 5-10 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.

To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and

the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For

the input clock timing requirements, see the input and output clocks electricals section.

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the DSP requirements in this data sheet (see the electrical characteristics over

recommended ranges of supply voltage and operating case temperature table and the input and output

clocks electricals section).

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3.3 V

CPU Clock

C1

C2

Peripheral Bus, EDMA

/2

EMI

filter

Clock

10 µF 0.1 µF

/8

/4

/6

Timer Internal Clock

PLLV

CLKOUT4, Peripheral Clock

(AUXCLK for McASP),

McBSP Internal Clock

CLKMODE0

CLKMODE1

CLKOUT6

PLLMULT

PLL

x6, x12

00 01 10

CLKIN

PLLCLK

1

0

/4

/2

ECLKIN

AEA[20:19]

EK2RATE

(GBLCTL.[19,18])

EMIF

00 01 10

Internal to DM642

ECLKOUT1 ECLKOUT2

(For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges, see the “TMS320DM642 PLL Multiply Factor

Options, Clock Frequency Ranges, and Typical Lock Time” table.)

NOTES: Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches,

or components other than the ones shown.

For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the

EMI Filter).

The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, D

.

VDD

EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.

Figure 5-10. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

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Table 5-12. TMS320DM642 PLL Multiply Factor Options, Clock Frequency Ranges,

and Typical Lock Time⁽¹⁾⁽²⁾

GDK and ZDK PACKAGES – 23 x 23 mm BGA,

GNZ and ZNZ PACKAGES – 27 x 27 mm BGA

CLKMODE

CLKMODE1 CLKMODE0 (PLL MULTIPLY

FACTORS)

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

TYPICAL

LOCK TIME

(µs)⁽³⁾

CLKOUT4

RANGE (MHz)

CLKOUT6

RANGE (MHz)

0

1

0

1

0

1

Bypass (x1)

x6

30–75

30–50

–

30–75

180–450

360–600

–

7.5–18.8

45–112.5

90–150

–

5–12.5

30–75

60–100

–

N/A

75

–

x12

Reserved

(1) These clock frequency range values are applicable to a DM642-600 speed device. For –500 and –720 device speed values, see the

CLKIN timing requirements table for the specific device speed.

(2) Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM642 device to one of the valid PLL

multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock

mode is x1 (bypass).

(3) Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For

example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

5.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks)

Table 5-13. Timing Requirements for CLKIN for –500 Devices^(1)(2)(3)(see Figure 5-11)

–500

NO.

PLL MODE x12

PLL MODE x6

x1 (Bypass)

UNIT

MIN

24

MAX

MIN

13.3

MAX

MIN

13.3

MAX

1

2

3

4

5

t_c(CLKIN)

t_w(CLKINH)

t_w(CLKINL)

t_t(CLKIN)

Cycle time, CLKIN

33.3

ns

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

Period jitter, CLKIN

0.45C

5

1

t_J(CLKIN)

0.02C

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.

(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

Table 5-14. Timing Requirements for CLKIN for –600 Devices^(1)(2)(3)(see Figure 5-11)

–600

NO.

PLL MODE x12

PLL MODE x6

x1 (Bypass)

UNIT

MIN

20

MAX

MIN

13.3

MAX

MIN

13.3

MAX

1

2

3

4

5

t_c(CLKIN)

t_w(CLKINH)

t_w(CLKINL)

t_t(CLKIN)

Cycle time, CLKIN

33.3

ns

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

Period jitter, CLKIN

0.45C

5

1

t_J(CLKIN)

0.02C

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.

(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

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Table 5-15. Timing Requirements for CLKIN for –720 Devices^(1)(2)(3)(see Figure 5-11)

–720

NO.

PLL MODE x12

PLL MODE x6

x1 (Bypass)

UNIT

MIN

16.6

MAX

MIN

13.3

MAX

MIN

13.3

MAX

1

2

3

4

5

t_c(CLKIN)

t_w(CLKINH)

t_w(CLKINL)

t_t(CLKIN)

Cycle time, CLKIN

33.3

ns

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

Period jitter, CLKIN

0.45C

5

1

t_J(CLKIN)

0.02C

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.

(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

1

5

4

2

CLKIN

3

4

Figure 5-11. CLKIN Timing

Table 5-16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4^(1)(2)(3)

(see Figure 5-12)

–500

–600

–720

NO.

PARAMETER

UNIT

CLKMODE = x1, x6, x12

MIN

MAX

1

2

3

t_w(CKO4H)

t_w(CKO4L)

t_t(CKO4)

Pulse duration, CLKOUT4 high

2P – 0.7

2P + 0.7

1

ns

Pulse duration, CLKOUT4 low

Transition time, CLKOUT4

(1) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(2) PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

(3) P = 1/CPU clock frequency in nanoseconds (ns)

3

1

CLKOUT4

2

3

Figure 5-12. CLKOUT4 Timing

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Table 5-17. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6^(1)(2)(3)

(see Figure 5-13)

–500

–600

–720

NO.

PARAMETER

UNIT

CLKMODE = x1, x6, x12

MIN

MAX

1

2

3

t_w(CKO6H)

t_w(CKO6L)

t_t(CKO6)

Pulse duration, CLKOUT6 high

3P – 0.7

3P + 0.7

1

ns

Pulse duration, CLKOUT6 low

Transition time, CLKOUT6

(1) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(2) PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

(3) P = 1/CPU clock frequency in nanoseconds (ns)

3

1

CLKOUT6

2

3

Figure 5-13. CLKOUT6 Timing

Table 5-18. Timing Requirements for AECLKIN for EMIFA^(1)(2)(3)(see Figure 5-14)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

4

5

t_c(EKI)

t_w(EKIH)

t_w(EKIL)

t_t(EKI)

Cycle time, AECLKIN

6⁽⁴⁾

2.7

16P

ns

Pulse duration, AECLKIN high

Pulse duration, AECLKIN low

Transition time, AECLKIN

Period jitter, AECLKIN

3

t_J(EKI)

0.02E

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(3) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(4) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times

are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600

and 720 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 devices,

100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.

1

5

4

2

AECLKIN

3

4

Figure 5-14. AECLKIN Timing for EMIFA

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Table 5-19. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the

EMIFA Module^(1)(2)(3)(see Figure 5-15)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

5

t_w(EKO1H)

Pulse duration, AECLKOUT1 high

EH – 0.7 EH + 0.7

EL – 0.7 EL + 0.7

1

ns

t_w(EKO1L)

Pulse duration, AECLKOUT1 low

t_t(EKO1)

Transition time, AECLKOUT1

t_{d(EKIH-EKO1H)}

t_{d(EKIL-EKO1L)}

Delay time, AECLKIN high to AECLKOUT1 high

Delay time, AECLKIN low to AECLKOUT1 low

1

8

(1) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(2) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

AECLKIN

5

2

3

1

4

AECLKOUT1

Figure 5-15. AECLKOUT1 Timing for the EMIFA Module

Table 5-20. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the

EMIFA Module⁽¹⁾⁽²⁾(see Figure 5-16)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

5

t_w(EKO2H)

Pulse duration, AECLKOUT2 high

0.5NE – 0.7

0.5NE + 0.7

ns

t_w(EKO2L)

Pulse duration, AECLKOUT2 low

0.5NE + 0.7

t_t(EKO2)

Transition time, AECLKOUT2

1

8

t_{d(EKIH-EKO2H)}

t_{d(EKIL-EKO2L)}

Delay time, AECLKIN high to AECLKOUT2 high

Delay time, AECLKIN low to AECLKOUT2 low

1

(1) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(2) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. N = the EMIF input clock divider; N = 1, 2,

or 4.

AECLKIN

5

2

3

1

4

AECLKOUT2

Figure 5-16. AECLKOUT2 Timing for the EMIFA Module

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5.8 External Memory Interface (EMIF)

EMIF supports a glueless interface to a variety of external devices, including:

•

Pipelined synchronous-burst SRAM (SBSRAM)

Synchronous DRAM (SDRAM)

Asynchronous devices, including SRAM, ROM, and FIFOs

An external shared-memory device

5.8.1 EMIF Device-Specific Information

EMIF Device Speed

The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets

the following requirements:

•

1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF

up to 1 CE space of buffers connected to EMIF

EMIF trace lengths between 1 and 3 inches

166-MHz SDRAM for 133-MHz operation

143-MHz SDRAM for 100-MHz operation

Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.

Verification of AC timings is mandatory when using configurations other than those specified above. TI

recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis application report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines

(see the Terminal Functions table for the EMIF output signals).

For more detailed information on the DM642 EMIF peripheral, see the TMS320C6000 DSP External

Memory Interface (EMIF) Reference Guide (literature number SPRU266).

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5.8.2 EMIF Peripheral Register Description(s)

Table 5-21. EMIFA Registers

HEX ADDRESS RANGE

0180 0000

ACRONYM

GBLCTL

CECTL1

CECTL0

–

REGISTER NAME

COMMENTS

EMIFA global control

0180 0004

EMIFA CE1 space control

EMIFA CE0 space control

Reserved

0180 0008

0180 000C

0180 0010

CECTL2

CECTL3

SDCTL

SDTIM

SDEXT

–

EMIFA CE2 space control

EMIFA CE3 space control

EMIFA SDRAM control

EMIFA SDRAM refresh control

EMIFA SDRAM extension

Reserved

0180 0014

0180 0018

0180 001C

0180 0020

0180 0024 – 0180 003C

0180 0040

PDTCTL

CESEC1

CESEC0

–

Peripheral device transfer (PDT) control

EMIFA CE1 space secondary control

EMIFA CE0 space secondary control

Reserved

0180 0044

0180 0048

0180 004C

0180 0050

CESEC2

CESEC3

–

EMIFA CE2 space secondary control

EMIFA CE3 space secondary control

Reserved

0180 0054

0180 0058 – 0183 FFFF

5.8.3 EMIF Electrical Data/Timing

5.8.3.1 Asynchronous Memory Timing

Table 5-22. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module⁽¹⁾⁽²⁾

(see Figure 5-17 and Figure 5-18)

–500

–600

–720

NO.

UNIT

MIN MAX

3

4

6

7

t_su(EDV-AREH)

t_h(AREH-EDV)

t_{su(ARDY-EKO1H)}

t_{h(EKO1H-ARDY)}

Setup time, AEDx valid before AARE high

Hold time, AEDx valid after AARE high

6.5

1

ns

Setup time, AARDY valid before AECLKOUTx high

Hold time, AARDY valid after AECLKOUTx high

3

2.5

(1) To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. The AARDY signal is only

recognized two cycles before the end of the programmed strobe time and while AARDY is low, the strobe time is extended

cycle-by-cycle. When AARDY is recognized low, the end of the strobe time is two cycles after AARDY is recognized high. To use

AARDY as an asynchronous input, the pulse width of the AARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup

and hold time is met.

(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.

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Table 5-23. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module^(1)(2)(3)(see Figure 5-17 and Figure 5-18)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

7

1

2

t_{osu(SELV-AREL)}

t_{oh(AREH-SELIV)}

t_{d(EKO1H-AREV)}

t_{osu(SELV-AWEL)}

t_{oh(AWEH-SELIV)}

t_{d(EKO1H-AWEV)}

Output setup time, select signals valid to AARE low

Output hold time, AARE high to select signals invalid

Delay time, AECLKOUTx high to AARE valid

RS * E – 1.8

RH * E – 1.9

1

ns

5

8

Output setup time, select signals valid to AAWE low

Output hold time, AAWE high to select signals invalid

Delay time, AECLKOUTx high to AAWE valid

WS * E – 2.0

WH * E – 2.5

1.3

9

10

7.1

(1) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIF CE space control registers.

(2) E = AECLKOUT1 period in ns for EMIFA

(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].

Setup = 2

Strobe = 3

Not Ready

Hold = 2

AECLKOUTx

ACEx

2

1

ABE[7:0]

BE

2

AEA[22:3]

Address

3

4

2

AED[63:0]

1

5

Read Data

(A)

AAOE/ASDRAS/ASOE

5

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

7

6

AARDY

A. AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified

under select signals), AARE, and AAWE, respectively, during asynchronous memory accesses.

Figure 5-17. Asynchronous Memory Read Timing for EMIFA

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Setup = 2

Hold = 2

Strobe = 3

Not Ready

AECLKOUTx

ACEx

9

8

ABE[7:0]

BE

9

AEA[22:3]

Address

Write Data

AED[63:0]

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

10

AAWE/ASDWE/ASWE

7

6

AARDY

A. AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified

under select signals), AARE, and AAWE, respectively, during asynchronous memory accesses.

Figure 5-18. Asynchronous Memory Write Timing for EMIFA

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5.8.3.2 Programmable Synchronous Interface Timing

Table 5-24. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 5-19)

–600

–720

–500, A-600

NO.

UNIT

MIN

3.1

MAX

MIN MAX

6

7

t_{su(EDV-EKOxH)}

t_h(EKOxH-EDV)

Setup time, read AEDx valid before AECLKOUTx high

Hold time, read AEDx valid after AECLKOUTx high

2

ns

1.8

1.5

Table 5-25. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module⁽¹⁾(see Figure 5-19–Figure 5-21)

–600

–720

–500, A-600

NO.

PARAMETER

UNIT

MIN

MAX

6.4

MIN

MAX

4.9

1

2

t_d(EKOxH-CEV)

t_d(EKOxH-BEV)

t_{d(EKOxH-BEIV)}

t_d(EKOxH-EAV)

t_{d(EKOxH-EAIV)}

t_{d(EKOxH-ADSV)}

t_d(EKOxH-OEV)

t_d(EKOxH-EDV)

t_{d(EKOxH-EDIV)}

t_d(EKOxH-WEV)

Delay time, AECLKOUTx high to ACEx valid

Delay time, AECLKOUTx high to ABEx valid

Delay time, AECLKOUTx high to ABEx invalid

Delay time, AECLKOUTx high to AEAx valid

Delay time, AECLKOUTx high to AEAx invalid

Delay time, AECLKOUTx high to ASADS/ASRE valid

Delay time, AECLKOUTx high to ASOE valid

Delay time, AECLKOUTx high to AEDx valid

Delay time, AECLKOUTx high to AEDx invalid

Delay time, AECLKOUTx high to ASWE valid

1.1

ns

6.4

4.9

3

1.1

4

6.4

4.9

5

1.1

8

6.4

4.9

9

10

11

12

1.1

6.4

4.9

(1) The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).

•

Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect

cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

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READ latency = 2

AECLKOUTx

1

2

1

3

5

ACEx

ABE[7:0]

BE1

BE2

BE3

EA3

BE4

4

AEA[22:3]

EA1

8

EA2

EA4

7

6

AED[63:0]

(C)

Q1

Q2

Q3

Q4

8

9

AARE/ASDCAS/ASADS/ASRE

9

(C)

AAOE/ASDRAS/ASOE

AAWE/ASDWE/ASWE

A. The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields,

respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and

CEEXT = 0.

B. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the

final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when

ASOE is active (CEEXT = 1).

•

Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as

ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect

cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

C. AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE,

ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 5-19. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) ^(A)(B)

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AECLKOUTx

1

ACEx

2

3

ABE[7:0]

AEA[22:3]

AED[63:0]

BE1

BE2

EA2

Q2

BE3

EA3

Q3

BE4

EA4

Q4

5

4

EA1

10

Q1

10

11

8

(C)

AARE/ASDCAS/ASADS/ASRE

(C)

AAOE/ASDRAS/ASOE

12

(C)

AAWE/ASDWE/ASWE

A. The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields,

respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and

CEEXT = 0.

B. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the

final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when

ASOE is active (CEEXT = 1).

•

Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as

ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect

cycles (RENEN = 1).

Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

C. AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE,

ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 5-20. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)^(A)(B)

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Write

Latency =

(B)

1

AECLKOUTx

1

3

ACEx

2

ABE[7:0]

BE1

BE2

EA2

BE3

EA3

Q2

BE4

EA4

Q3

5

4

AEA[22:3]

EA1

10

11

8

AED[63:0]

(C)

Q1

Q4

8

AARE/ASDCAS/ASADS/ASRE

(C)

AAOE/ASDRAS/ASOE

12

AAWE/ASDWE/ASWE

A. The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields,

respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and

CEEXT = 0.

B. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the

final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when

ASOE is active (CEEXT = 1).

•

Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as

ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect

cycles (RENEN = 1).Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface,

ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as

ASRE with NO deselect cycles (RENEN = 1).

•

Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

C. AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE,

ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 5-21. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) ^(A)(B)

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5.8.3.3 Synchronous DRAM Timing

Table 5-26. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 5-22)

–600

–500, A-600

–720

MIN MAX

0.6

NO.

UNIT

MIN MAX

6

7

t_{su(EDV-EKO1H)}

t_h(EKO1H-EDV)

Setup time, read AEDx valid before AECLKOUTx high

Hold time, read AEDx valid after AECLKOUTx high

2.1

2.8

ns

2.1

Table 5-27. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM

Cycles for EMIFA Module (see Figure 5-22–Figure 5-29)

–600

–720

–500, A-600

NO.

PARAMETER

UNIT

MIN

MAX

6.4

MIN

MAX

4.9

1

2

t_d(EKO1H-CEV)

t_d(EKO1H-BEV)

t_{d(EKO1H-BEIV)}

t_d(EKO1H-EAV)

t_{d(EKO1H-EAIV)}

t_{d(EKO1H-CASV)}

t_d(EKO1H-EDV)

t_{d(EKO1H-EDIV)}

t_d(EKO1H-WEV)

t_d(EKO1H-RAS)

t_{d(EKO1H-ACKEV)}

t_{d(EKO1H-PDTV)}

Delay time, AECLKOUTx high to ACEx valid

Delay time, AECLKOUTx high to ABEx valid

Delay time, AECLKOUTx high to ABEx invalid

Delay time, AECLKOUTx high to AEAx valid

Delay time, AECLKOUTx high to AEAx invalid

Delay time, AECLKOUTx high to ASDCAS valid

Delay time, AECLKOUTx high to AEDx valid

Delay time, AECLKOUTx high to AEDx invalid

Delay time, AECLKOUTx high to ASDWE valid

Delay time, AECLKOUTx high to ASDRAS valid

Delay time, AECLKOUTx high to ASDCKE valid

Delay time, AECLKOUTx high to APDT valid

1.3

ns

6.4

4.9

3

1.3

4

6.4

4.9

5

1.3

8

6.4

4.9

9

10

11

12

13

14

1.3

6.4

4.9

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READ

AECLKOUTx

ACEx

1

4

1

2

3

ABE[7:0]

BE1

BE2

BE3

BE4

5

Bank

AEA[22:14]

AEA[12:3]

4

Column

4

AEA13

6

7

D2

AED[63:0]

(A)

D1

D3

D4

AAOE/ASDRAS/ASOE

AARE/ASDCAS/ASADS/ASRE

AAWE/ASDWE/ASWE

8

(A)

(B)

14

APDT

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

B. APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter

RAM). For APDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL)

configures the latency of the APDT signal with respect to the data phase of a read transaction. The latency of the

APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively.

PDTRL equals 00 (zero latency) in Figure 5-22.

Figure 5-22. SDRAM Read Command (CAS Latency 3) for EMIFA

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WRITE

AECLKOUTx

1

2

4

5

9

ACEx

3

2

ABE[7:0]

BE1

Bank

BE2

BE3

BE4

4

9

AEA[22:14]

Column

AEA[12:3]

AEA13

10

AED[63:0]

D1

D2

D3

D4

(A)

AAOE/ASDRAS/ASOE

8

(A)

AARE/ASDCAS/ASADS/ASRE

11

14

11

(A)

AAWE/ASDWE/ASWE

14

(B)

APDT

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

B. APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter

RAM). For APDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL)

configures the latency of the APDT signal with respect to the data phase of a write transaction. The latency of the

APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11,

respectively. PDTWL equals 00 (zero latency) in Figure 5-23.

Figure 5-23. SDRAM Write Command for EMIFA

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ACTV

AECLKOUTx

1

ACEx

ABE[7:0]

4

5

Bank Activate

AEA[22:14]

AEA[12:3]

4

Row Address

4

Row Address

AEA13

AED[63:0]

12

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-24. SDRAM ACTV Command for EMIFA

DCAB

AECLKOUTx

1

ACEx

ABE[7:0]

AEA[22:14, 12:3]

4

12

11

5

12

11

AEA13

AED[63:0]

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-25. SDRAM DCAB Command for EMIFA

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DEAC

AECLKOUTx

1

ACEx

ABE[7:0]

4

5

AEA[22:14]

AEA[12:3]

Bank

4

5

AEA13

AED[63:0]

12

11

12

11

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-26. SDRAM DEAC Command for EMIFA

REFR

AECLKOUTx

1

ACEx

ABE[7:0]

AEA[22:14, 12:3]

AEA13

AED[63:0]

12

8

12

8

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-27. SDRAM REFR Command for EMIFA

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MRS

AECLKOUTx

1

4

1

5

ACEx

ABE[7:0]

AEA[22:3]

AED[63:0]

MRS value

12

8

12

8

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

11

(A)

AAWE/ASDWE/ASWE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-28. SDRAM MRS Command for EMIFA

≥ TRAS cycles

End Self-Refresh

Self Refresh

AECLKOUTx

ACEx

ABE[7:0]

AEA[22:14, 12:3]

AEA13

AED[63:0]

(A)

AAOE/ASDRAS/ASOE

(A)

AARE/ASDCAS/ASADS/ASRE

(A)

AAWE/ASDWE/ASWE

13

ASDCKE

A. AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,

and ASDRAS, respectively, during SDRAM accesses.

Figure 5-29. SDRAM Self-Refresh Timing for EMIFA

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5.8.3.4 HOLD/HOLDA Timing

Table 5-28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module⁽¹⁾(see Figure 5-30)

–600

–500, A-600

–720

MIN MAX

E

NO.

UNIT

MIN MAX

3

t_{h(HOLDAL-HOLDL)}

Hold time, HOLD low after HOLDA low

E

ns

(1) E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

Table 5-29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA

Cycles for EMIFA Module^(1)(2)(3)(see Figure 5-30)

–600

–720

–500, A-600

NO.

PARAMETER

UNIT

MIN

2E

0

MAX

MIN

MAX

(4)

1

2

4

5

6

7

t_{d(HOLDL-EMHZ)}

t_{d(EMHZ-HOLDAL)}

t_{d(HOLDH-EMLZ)}

t_{d(EMLZ-HOLDAH)}

t_{d(HOLDL-EKOHZ)}

t_{d(HOLDH-EKOLZ)}

Delay time, HOLD low to EMIFA Bus high impedance

Delay time, EMIF Bus high impedance to HOLDA low

Delay time, HOLD high to EMIF Bus low impedance

Delay time, EMIFA Bus low impedance to HOLDA high

Delay time, HOLD low to AECLKOUTx high impedance

Delay time, HOLD high to AECLKOUTx low impedance

2E

0

ns

2E

7E

2E

7E

2E

0

2E

0

2E

(4)

2E

7E

(1) E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

(2) EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

(3) The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ =

0, ECLKOUTx continues clocking during Hold mode. If

EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 5-30.

(4) All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the

minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

External Requestor

DSP Owns Bus

Owns Bus

3

HOLD

2

5

HOLDA

(A)

1

4

7

EMIF Bus

DM642

(B)

AECLKOUTx

(EKxHZ = 0)

6

(B)

AECLKOUTx

(EKxHZ = 1)

A. EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE,

AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

B. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during

HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high

impedance during Hold mode, as shown in Figure 5-30.

Figure 5-30. HOLD/HOLDA Timing for EMIFA

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5.8.3.5 BUSREQ Timing

Table 5-30. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles

for EMIFA Module (see Figure 5-31)

–600

–720

–500, A-600

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

t_{d(AEKO1H-ABUSRV)}

Delay time, AECLKOUTx high to ABUSREQ valid

0.6

7.1

1

5.5

ns

AECLKOUTx

1

ABUSREQ

Figure 5-31. BUSREQ Timing for EMIFA

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5.9 Multichannel Audio Serial Port (McASP0) Peripheral

The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel

audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated

Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

5.9.1 McASP0 Device-Specific Information

The TMS320DM642 device includes one multichannel audio serial port (McASP) interface peripheral

(McASP0). The McASP is a serial port optimized for the needs of multichannel audio applications.

The McASP consists of a transmit and receive section. These sections can operate completely

independently with different data formats, separate master clocks, bit clocks, and frame syncs or

alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a

pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or

general-purpose I/O (GPIO).

The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)

synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for

S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM

synchronous serial format.

The McASP can support one transmit data format (either a TDM format or DIT format) and one receive

format at a time. All transmit shift registers use the same format and all receive shift registers use the

same format. However, the transmit and receive formats need not be the same.

Both the transmit and receive sections of the McASP also support burst mode which is useful for

non-audio data (for example, passing control information between two DSPs).

The McASP peripheral has additional capability for flexible clock generation, and error detection/handling,

as well as error management.

For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000

DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).

5.9.1.1 McASP Block Diagram

Figure 5-32 illustrates the major blocks along with external signals of the TMS320DM642 McASP0

peripheral; and shows the 8 serial data [AXR] pins. The McASP also includes full general-purpose I/O

(GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O.

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McASP0

Transmit

Frame Sync

Generator

DIT

RAM

AFSX0

Transmit

Clock Check

(High-

Transmit

Clock

Generator

AHCLKX0

ACLKX0

Frequency)

AMUTE0

Error

Detect

AMUTEIN0

Receive

Clock Check

(High-

Receive

Clock

Generator

AHCLKR0

ACLKR0

Frequency)

Transmit

Data

Formatter

Receive

Frame Sync

Generator

AFSR0

Serializer 0

AXR0[0]

AXR0[1]

AXR0[2]

AXR0[3]

AXR0[4]

AXR0[5]

AXR0[6]

AXR0[7]

Serializer 1

Serializer 2

Serializer 3

Serializer 4

Serializer 5

Serializer 6

Serializer 7

Receive

Data

Formatter

GPIO

Control

Figure 5-32. McASP0 Configuration

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5.9.2 McASP0 Peripheral Register Description(s)

Table 5-31. McASP0 Control Registers

HEX ADDRESS RANGE

01B4 C000

ACRONYM

REGISTER NAME

PID

PWRDEMU

–

Peripheral Identification register [Register value: 0x0010 0101]

01B4 C004

Power down and emulation management register

01B4 C008

Reserved

01B4 C00C

–

Reserved

01B4 C010

PFUNC

PDIR

Pin function register

01B4 C014

Pin direction register

01B4 C018

PDOUT

PDIN/PDSET

PDCLR

–

Pin data out register

01B4 C01C

Pin data in / data set registerRead returns: PDINWrites affect: PDSET

Pin data clear register

01B4 C020

01B4 C024 – 01B4 C040

01B4 C044

Reserved

GBLCTL

AMUTE

DLBCTL

DITCTL

–

Global control register

01B4 C048

Mute control register

01B4 C04C

Digital Loop-back control register

DIT mode control register

Reserved

01B4 C050

01B4 C054 – 01B4 C05C

Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset

independently from receive.

01B4 C060

RGBLCTL

01B4 C064

01B4 C068

RMASK

RFMT

Receiver format UNIT bit mask register

Receive bit stream format register

Receive frame sync control register

Receive clock control register

High-frequency receive clock control register

Receive TDM slot 0–31 register

Receiver interrupt control register

Status register – Receiver

01B4 C06C

AFSRCTL

ACLKRCTL

AHCLKRCTL

RTDM

01B4 C070

01B4 C074

01B4 C078

01B4 C07C

RINTCTL

RSTAT

01B4 C080

01B4 C084

RSLOT

Current receive TDM slot register

Receiver clock check control register

Reserved

01B4 C088

RCLKCHK

–

01B4 C08C – 01B4 C09C

Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset

independently from receive.

01B4 C0A0

XGBLCTL

01B4 C0A4

01B4 C0A8

01B4 C0AC

01B4 C0B0

01B4 C0B4

01B4 C0B8

01B4 C0BC

01B4 C0C0

01B4 C0C4

01B4 C0C8

XMASK

XFMT

Transmit format UNIT bit mask register

Transmit bit stream format register

Transmit frame sync control register

Transmit clock control register

AFSXCTL

ACLKXCTL

AHCLKXCTL

XTDM

High-frequency Transmit clock control register

Transmit TDM slot 0–31 register

Transmit interrupt control register

Status register – Transmitter

XINTCTL

XSTAT

XSLOT

Current transmit TDM slot

XCLKCHK

Transmit clock check control register

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Table 5-31. McASP0 Control Registers (continued)

HEX ADDRESS RANGE

01B4 C0CC – 01B4 C0FC

01B4 C100

ACRONYM

–

REGISTER NAME

Reserved

DITCSRA0

DITCSRA1

DITCSRA2

DITCSRA3

DITCSRA4

DITCSRA5

DITCSRB0

DITCSRB1

DITCSRB2

DITCSRB3

DITCSRB4

DITCSRB5

DITUDRA0

DITUDRA1

DITUDRA2

DITUDRA3

DITUDRA4

DITUDRA5

DITUDRB0

DITUDRB1

DITUDRB2

DITUDRB3

DITUDRB4

DITUDRB5

–

Left (even TDM slot) channel status register file

Right (odd TDM slot) channel status register file

Left (even TDM slot) user data register file

Right (odd TDM slot) user data register file

Reserved

01B4 C104

01B4 C108

01B4 C10C

01B4 C110

01B4 C114

01B4 C118

01B4 C11C

01B4 C120

01B4 C124

01B4 C128

01B4 C12C

01B4 C130

01B4 C134

01B4 C138

01B4 C13C

01B4 C140

01B4 C144

01B4 C148

01B4 C14C

01B4 C150

01B4 C154

01B4 C158

01B4 C15C

01B4 C160 – 01B4 C17C

01B4 C180

SRCTL0

SRCTL1

SRCTL2

SRCTL3

SRCTL4

SRCTL5

SRCTL6

SRCTL7

–

Serializer 0 control register

01B4 C184

Serializer 1 control register

01B4 C188

Serializer 2 control register

01B4 C18C

Serializer 3 control register

01B4 C190

Serializer 4 control register

01B4 C194

Serializer 5 control register

01B4 C198

Serializer 6 control register

01B4 C19C

Serializer 7 control register

01B4 C1A0 – 01B4 C1FC

01B4 C200

Reserved

XBUF0

Transmit Buffer for Serializer 0

01B4 C204

XBUF1

Transmit Buffer for Serializer 1

01B4 C208

XBUF2

Transmit Buffer for Serializer 2

01B4 C20C

XBUF3

Transmit Buffer for Serializer 3

01B4 C210

XBUF4

Transmit Buffer for Serializer 4

01B4 C214

XBUF5

Transmit Buffer for Serializer 5

01B4 C218

XBUF6

Transmit Buffer for Serializer 6

01B4 C21C

XBUF7

Transmit Buffer for Serializer 7

01B4 C220 – 01B4 C27C

01B4 C280

–

Reserved

RBUF0

Receive Buffer for Serializer 0

01B4 C284

RBUF1

Receive Buffer for Serializer 1

01B4 C288

RBUF2

Receive Buffer for Serializer 2

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Table 5-31. McASP0 Control Registers (continued)

HEX ADDRESS RANGE

01B4 C28C

ACRONYM

RBUF3

RBUF4

RBUF5

RBUF6

RBUF7

–

REGISTER NAME

Receive Buffer for Serializer 3

Receive Buffer for Serializer 4

Receive Buffer for Serializer 5

Receive Buffer for Serializer 6

Receive Buffer for Serializer 7

Reserved

01B4 C290

01B4 C294

01B4 C298

01B4 C29C

01B4 C2A0 – 01B4 FFFF

Table 5-32. McASP0 Data Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

(Used when RSEL or XSEL

bits = 0 [these bits are located

in the RFMT or XFMT registers,

respectively].)

McASPx receive buffers or McASPx transmit buffers via

the Peripheral Data Bus.

3C00 0000 – 3C0F FFFF

RBUF/XBUFx

5.9.3 McASP0 Electrical Data/Timing

5.9.3.1 Multichannel Audio Serial Port (McASP) Timing

Table 5-33. Timing Requirements for McASP (see Figure 5-33 and Figure 5-34)⁽¹⁾

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(AHCKRX)

t_w(AHCKRX)

t_c(CKRX)

Cycle time, AHCLKR/X

20

ns

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

10

33

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

t_w(CKRX)

Pulse duration, ACLKR/X high or low

16.5

5

6

7

8

t_su(FRX-CKRX)

t_h(CKRX-FRX)

t_su(AXR-CKRX)

t_h(CKRX-AXR)

Setup time, AFSR/X input valid before ACLKR/X latches data

Hold time, AFSR/X input valid after ACLKR/X latches data

Setup time, AXR input valid before ACLKR/X latches data

Hold time, AXR input valid after ACLKR/X latches data

5

(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

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Table 5-34. Switching Characteristics Over Recommended Operating Conditions for McASP

(see Figure 5-33 and Figure 5-34)⁽¹⁾

–500

–600

NO.

PARAMETER

–720

UNIT

MIN

MAX

9

t_c(AHCKRX)

t_w(AHCKRX)

t_c(CKRX)

Cycle time, AHCLKR/X

20

10

33

ns

10

11

12

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

ACLKR/X int

ACLKR/X ext

ACLKX int

t_w(CKRX)

Pulse duration, ACLKR/X high or low

16.5

–1

0

5

13

14

15

t_d(CKRX-FRX)

Delay time, ACLKR/X transmit edge to AFSX/R output valid

Delay time, ACLKX transmit edge to AXR output valid

10

5

–1

0

t_d(CKX-AXRV)

ACLKX ext

10

ACLKR/X int

ACLKR/X ext

0

Disable time, AXR high impedance following last data bit from

ACLKR/X transmit edge

t_{dis(CKRX-AXRHZ)}

0

(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

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2

1

2

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

4

3

4

†

ACLKR/X (CLKRP = CLKXP = 0)

‡

ACLKR/X (CLKRP = CLKXP = 1)

6

5

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

8

7

AXR[n] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

†

‡

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling

edge (to shift data in).

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising

edge (to shift data in).

Figure 5-33. McASP Input Timings

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10

9

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

12

11

12

†

ACLKR/X (CLKRP = CLKXP = 1)

‡

ACLKR/X (CLKRP = CLKXP = 0)

13

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

13

14

15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

†

‡

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising

edge (to shift data in).

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling

edge (to shift data in).

Figure 5-34. McASP Output Timings

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5.10 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between a TMS320C6000™ DSP and other

devices compliant with Philips Semiconductors Inter-IC bus (I²C bus) specification version 2.1 and

connected by way of an I²C-bus. External components attached to this 2-wire serial bus can

transmit/receive up to 8-bit data to/from the DSP through the I2C module.

5.10.1 I2C Device-Specific Information

The I2C module on the TMS320DM642 may be used by the DSP to control local peripherals ICs (DACs,

ADCs, etc.) while the other may be used to communicate with other controllers in a system or to

implement a user interface.

The I2C port supports:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Fast Mode up to 400 Kbps (no fail-safe I/O buffers)

Noise Filter to Remove Noise 50 ns or less

Seven- and Ten-Bit Device Addressing Modes

Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

Events: DMA, Interrupt, or Polling

Slew-Rate Limited Open-Drain Output Buffers

Figure 5-35 is a block diagram of the I2C0 module.

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I2C0 Module

Clock

Prescale

Peripheral Clock

(CPU/4)

I2CPSCx

Bit Clock

Generator

Control

SCL

Noise

Filter

Own

I2C Clock

I2CCLKHx

I2CCLKLx

I2COARx

I2CSARx

I2CMDRx

I2CCNTx

Address

Slave

Address

Mode

Transmit

I2CXSRx

Data

Count

Transmit

Shift

Transmit

Buffer

I2CDXRx

SDA

Interrupt/DMA

I2CIERx

Noise

Filter

I2C Data

Interrupt

Enable

Receive

Buffer

I2CDRRx

Interrupt

Status

I2CSTRx

Interrupt

Source

Receive

Shift

I2CRSRx

I2CISRCx

Shading denotes a peripheral module not available for this configuration.

Figure 5-35. I2C0 Module Block Diagram

For more detailed information on the I2C peripheral, see the TMS320C6000 DSP Inter-Integrated Circuit

(I2C) Module Reference Guide (literature number SPRU175).

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5.10.2 I2C Peripheral Register Description(s)

Table 5-35. I2C0 Registers

HEX ADDRESS RANGE

01B4 0000

ACRONYM

I2COAR0

I2CIER0

I2CSTR0

I2CCLKL0

I2CCLKH0

I2CCNT0

I2CDRR0

I2CSAR0

I2CDXR0

I2CMDR0

I2CISRC0

–

REGISTER NAME

I2C0 own address register

I2C0 interrupt enable register

I2C0 interrupt status register

01B4 0004

01B4 0008

01B4 000C

I2C0 clock low-time divider register

I2C0 clock high-time divider register

I2C0 data count register

01B4 0010

01B4 0014

01B4 0018

I2C0 data receive register

01B4 001C

I2C0 slave address register

I2C0 data transmit register

01B4 0020

01B4 0024

I2C0 mode register

01B4 0028

I2C0 interrupt source register

Reserved

01B4 002C

01B4 0030

I2CPSC0

I2CPID10

I2CPID20

–

I2C0 prescaler register

01B4 0034

I2C0 Peripheral Identification register 1 [Value: 0x0000 0101]

I2C0 Peripheral Identification register 2 [Value: 0x0000 0005]

Reserved

01B4 0038

01B4 003C – 01B4 3FFF

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5.10.3 I2C Electrical Data/Timing

5.10.3.1 Inter-Integrated Circuits (I2C) Timing

Table 5-36. Timing Requirements for I2C Timings⁽¹⁾(see Figure 5-36)

–500

–600

–720

NO.

UNIT

STANDARD

MODE

FAST MODE

MIN

MAX

MIN

MAX

1

2

t_c(SCL)

Cycle time, SCL

10

2.5

µs

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

4.7

4

0.6

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

3

t_h(SCLL-SDAL)

µs

4

5

6

7

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100⁽²⁾

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_{su(SDAV-SDLH)}

t_h(SDA-SDLL)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low (For I²C bus™ devices)

250

0⁽³⁾

0⁽³⁾0.9⁽⁴⁾

Pulse duration, SDA high between STOP and START

conditions

8

t_w(SDAH)

4.7

1.3

µs

(5)

9

t_r(SDA)

Rise time, SDA

1000 20 + 0.1C_b

300 20 + 0.1C_b

300

ns

µs

ns

pF

(5)

10

11

12

13

14

15

t_r(SCL)

Rise time, SCL

t_f(SDA)

Fall time, SDA

t_f(SCL)

Fall time, SCL

t_{su(SCLH-SDAH)}

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4

0.6

0

t_w(SP)

50

(5)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus™ system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then

be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line t_rmax + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns

(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

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11

9

SDA

6

8

14

4

13

5

10

SCL

1

12

3

2

7

3

Stop

Start

Repeated

Start

Stop

Figure 5-36. I2C Receive Timings

Table 5-37. Switching Characteristics for I2C Timings⁽¹⁾(see Figure 5-37)

–500

–600

–720

NO.

PARAMETER

STANDARD

UNIT

FAST MODE

MODE

MIN MAX

MIN

MAX

16

17

t_c(SCL)

t_d(SCLH-SDAL)

t_d(SDAL-SCLL)

Cycle time, SCL

10

2.5

µs

Delay time, SCL high to SDA low (for a repeated START

condition)

4.7

0.6

Delay time, SDA low to SCL low (for a START and a repeated

START condition)

18

4

µs

19

20

21

22

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_d(SDAV-SDLH)

t_v(SDLL-SDAV)

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low (For I²C bus™ devices)

250

0

0.9

Pulse duration, SDA high between STOP and START con-

ditions

23

t_w(SDAH)

4.7

1.3

µs

(1)

24

25

26

27

28

29

t_r(SDA)

t_r(SCL)

Rise time, SDA

1000 20 + 0.1C_b

300

ns

µs

pF

(1)

Rise time, SCL

1000 20 + 0.1C_b

300 20 + 0.1C_b

t_f(SDA)

Fall time, SDA

t_f(SCL)

Fall time, SCL

t_d(SCLH-SDAH)

C_p

Delay time, SCL high to SDA high (for STOP condition)

Capacitance for each I2C pin

4

0.6

10

(1) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

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26

24

SDA

21

23

19

28

20

25

SCL

16

27

18

17

22

18

Stop

Start

Repeated

Start

Stop

Figure 5-37. I2C Transmit Timings

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5.11 Host-Port Interface (HPI)

The HPI is a parallel port through which a host processor can directly access the CPU memory space.

The host device functions as a master to the interface, which increases ease of access. The host and

CPU can exchange information via internal or external memory. The host also has direct access to

memory-mapped peripherals. Connectivity to the CPU memory space is provided through the enhanced

DMA (EDMA) controller. Both the host and the CPU can access the HPI control register (HPIC) and the

HPI address register (HPIA). The host can access the HPI data register (HPID) and the HPIC by using the

external data and interface control signals.

For more detailed information on the HPI peripheral, see the TMS320C6000 DSP Host Port Interface

(HPI) Reference Guide (literature number SPRU578).

5.11.1 HPI Peripheral Register Description(s)

Table 5-38. HPI Registers

HEX ADDRESS RANGE

ACRONYM

HPID

REGISTER NAME

HPI data register

COMMENTS

Host read/write access only

–

0188 0000

HPIC

HPI control register

HPIC has both Host/CPU read/write access

HPIA

HPI address register

(Write)

0188 0004

(HPIAW)⁽¹⁾

HPIA has both Host/CPU read/write access

HPIA

HPI address register

(Read)

0188 0008

(HPIAR)⁽¹⁾

0188 000C – 0189 FFFF

018A 0000

–

Reserved

HPI transfer request control

register

HPI_TRCTL

–

018A 0004 – 018B FFFF

Reserved

(1) Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR

independently.

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5.11.2 Host-Port Interface (HPI) Electrical Data/Timing

Table 5-39. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾(see Figure 5-38 through Figure 5-45)

–500

–600

–720

NO.

UNIT

MIN MAX

1

2

t_{su(SELV-HSTBL)}

t_{h(HSTBL-SELV)}

t_w(HSTBL)

Setup time, select signals⁽³⁾valid before HSTROBE low

Hold time, select signals⁽³⁾valid after HSTROBE low

Pulse duration, HSTROBE low

5

2.4

4P⁽⁴⁾

4P

5

ns

3

4

t_w(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

Setup time, select signals⁽³⁾valid before HAS low

Hold time, select signals⁽³⁾valid after HAS low

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

10

11

12

13

t_{su(SELV-HASL)}

t_h(HASL-SELV)

t_{su(HDV-HSTBH)}

t_h(HSTBH-HDV)

2

5

2.8

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated

until HRDY is active (low); otherwise, HPI writes will not complete properly.

14

t_{h(HRDYL-HSTBL)}

2

ns

18

19

t_{su(HASL-HSTBL)}

t_{h(HSTBL-HASL)}

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

2

ns

2.1

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

(4) Select the parameter value of 4P or 12.5 ns, whichever is larger.

Table 5-40. Switching Characteristics Over Recommended Operating Conditions During Host-Port

Interface Cycles⁽¹⁾⁽²⁾(see Figure 5-38 through Figure 5-45)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

1.3

2

MAX

6

7

t_{d(HSTBL-HRDYH)}

t_{d(HSTBL-HDLZ)}

t_d(HDV-HRDYL)

t_{oh(HSTBH-HDV)}

t_{d(HSTBH-HDHZ)}

t_d(HSTBL-HDV)

Delay time, HSTROBE low to HRDY high⁽³⁾

4P + 8

ns

Delay time, HSTROBE low to HD low impedance for an HPI read

Delay time, HD valid to HRDY low

8

-3

9

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)

1.5

15

16

12

4P + 8

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(2) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(3) This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word

transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and

HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes

high if the internal write buffer is full.

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HAS

1

2

HCNTL[1:0]

1

2

HR/W

1

2

HHWIL

4

3

(A)

HSTROBE

HCS

15

9

15

9

7

16

HD[15:0] (output)

1st half-word

6

2nd half-word

8

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-38. HPI16 Read Timing (HAS Not Used, Tied High)

(A)

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

10

HHWIL

4

3

(B)

HSTROBE

18

HCS

15

7

9

16

9

HD[15:0] (output)

HRDY

1st half-word

2nd half-word

6

8

A. For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-39. HPI16 Read Timing (HAS Used)

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HAS

HCNTL[1:0]

HR/W

1

2

1

2

1

2

HHWIL

3

4

(A)

HSTROBE

HCS

12

13

HD[15:0] (input)

1st half-word

2nd half-word

6

14

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-40. HPI16 Write Timing (HAS Not Used, Tied High)

19

11

19

(A)

HAS

11

10

HCNTL[1:0]

HR/W

11

HHWIL

3

4

(B)

HSTROBE

18

12

18

HCS

12

13

HD[15:0] (input)

1st half-word

2nd half-word

6

14

HRDY

A. For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-41. HPI16 Write Timing (HAS Used)

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HAS

1

2

HCNTL[1:0]

HR/W

3

(A)

HSTROBE

HCS

7

9

15

HD[31:0] (output)

HRDY

6

8

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-42. HPI32 Read Timing (HAS Not Used, Tied High)

19

(A)

HAS

11

10

HCNTL[1:0]

11

10

HR/W

18

3

(B)

HSTROBE

HCS

7

9

15

HD[31:0] (output)

HRDY

6

8

A. For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-43. HPI32 Read Timing (HAS Used)

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HAS

1

2

HCNTL[1:0]

HR/W

3

(A)

HSTROBE

HCS

12

13

HD[31:0] (input)

HRDY

6

14

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-44. HPI32 Write Timing (HAS Not Used, Tied High)

19

(A)

HAS

11

10

HCNTL[1:0]

11

10

HR/W

3

18

(B)

HSTROBE

HCS

12

13

HD[31:0] (input)

HRDY

6

14

A. For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

B. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 5-45. HPI32 Write Timing (HAS Used)

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5.12 Peripheral Component Interconnect (PCI)

The PCI port for the TMS320C600 supports connection of the DSP to a PCI host via the integrated PCI

master/slave bus interface. For the C64x devices, like the DM642, the PCI port interfaces to the DSP via

the EDMA internal address generation hardware. This architecture allows for both PCI Master and Slave

transactions, while keeping the EDMA channel resources available for other applications.

5.12.1 PCI Device-Specific Information

On the DM642 device, the PCI interface is multiplexed with the 32-bit Host Port Interface (HPI), or with a

combination of 16-bit HPI and EMAC/MDIO. This provides the following flexibility options to the user:

•

32-bit 66 MHz PCI bus

32-bit HPI

Combination of 16-bit HPI and EMAC/MDIO

For more detailed information on the PCI port peripheral module, see the TMS320C6000 DSP Peripheral

Component Interconnect (PCI) Reference Guide (literature number SPRU581).

5.12.2 PCI Peripheral Register Description(s)

Table 5-41. PCI Peripheral Registers

HEX ADDRESS RANGE

01C0 0000

ACRONYM

RSTSRC

–

REGISTER NAME

DSP Reset source/status register

01C0 0004

Reserved

01C0 0008

PCIIS

PCIIEN

DSPMA

PCIMA

PCIMC

CDSPA

CPCIA

CCNT

–

PCI interrupt source register

PCI interrupt enable register

DSP master address register

PCI master address register

PCI master control register

Current DSP address register

Current PCI address register

Current byte count register

Reserved

01C0 000C

01C0 0010

01C0 0014

01C0 0018

01C0 001C

01C0 0020

01C0 0024

01C0 0028

01C0 002C – 01C1 FFEF

0x01C1 FFF0

0x01C1 FFF4

0x01C1 FFF8

0x01C1 FFFC

01C2 0000

–

Reserved

HSR

Host status register

HDCR

DSPP

–

Host-to-DSP control register

DSP page register

Reserved

EEADD

EEDAT

EECTL

–

EEPROM address register

EEPROM data register

EEPROM control register

Reserved

01C2 0004

01C2 0008

01C2 000C – 01C2 FFFF

01C3 0000

PCI_TRCTL PCI transfer request control register

Reserved

01C3 0004 – 01C3 FFFF

–

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5.12.3 PCI Electrical Data/Timing

5.12.3.1 Peripheral Component Interconnect (PCI) Timing

Table 5-42. Timing Requirements for PCLK⁽¹⁾⁽²⁾(see Figure 5-46)

–500, A-600

[33 MHz]

–600, –720

[66 MHz]

NO.

UNIT

MIN MAX

30 (or 4P⁽³⁾

MIN MAX

15 (or 4P⁽³⁾

1

2

3

4

t_c(PCLK)

Cycle time, PCLK

)

ns

t_w(PCLKH)

t_w(PCLKL)

t_sr(PCLK)

Pulse duration, PCLK high

Pulse duration, PCLK low

∆v/∆t slew rate, PCLK

11

1

6

ns

4

1.5

4

V/ns

(1) For 3.3-V operation, the reference points for the rise and fall transitions are measured at V_ILPMAX and V_IHPMIN.

(2) P = 1/CPU clock frequency in ns. For example when running parts at 720 MHz,use P = 1.39 ns.

(3) Select the parameter value, whichever is larger.

0.4 DV V MIN

DD

Peak to Peak for

3.3V signaling

1

4

2

PCLK

3

4

Figure 5-46. PCLK Timing

Table 5-43. Timing Requirements for PCI Reset (see Figure 5-47)

–500

–600

–720

NO.

UNIT

MIN

1

MAX

1

2

t_w(PRST)

Pulse duration, PRST

ms

µs

t_{su(PCLKA-PRSTH)}

Setup time, PCLK active before PRST high

100

PCLK

1

PRST

2

Figure 5-47. PCI Reset (PRST) Timing

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Table 5-44. Timing Requirements for PCI Inputs (see Figure 5-48)

–600

–720

–500, A-600

33 MHz

NO.

UNIT

66 MHz

MIN

7

MAX

MIN

MAX

4

5

t_su(IV-PCLKH)

t_h(IV-PCLKH)

Setup time, input valid before PCLK high

Hold time, input valid after PCLK high

3

0

ns

0

PCLK

4

5

PCI Input

Inputs Valid

Figure 5-48. PCI Input Timing (33-/66-MHz)

Table 5-45. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs

(see Figure 5-49)

–600

–500, A-600

–720

NO.

parameter

UNIT

33 MHz

MIN MAX

66 MHz

MIN MAX

1

2

3

t_d(PCLKH-OV)

t_d(PCLKH-OLZ)

t_d(PCLKH-OHZ)

Delay time, PCLK high to output valid

2

11

2

6

ns

Delay time, PCLK high to output low impedance

Delay time, PCLK high to output high impedance

28

14

PCLK

1

PCI Output

2

3

Figure 5-49. PCI Output Timing (33-/66-MHz)

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Table 5-46. Timing Requirements for Serial EEPROM Interface (see Figure 5-50)

–500

–600

–720

NO.

UNIT

MIN

MAX

8

9

t_su(DIV-CLKH)

t_h(CLKH-DIV)

Setup time, XSP_DI valid before XSP_CLK high

Hold time, XSP_DI valid after XSP_CLK high

50

0

ns

Table 5-47. Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM

Interface⁽¹⁾(see Figure 5-50)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

TYP

MAX

1

2

3

4

5

6

7

t_w(CSL)

Pulse duration, XSP_CS low

4092P

0

ns

t_d(CLKL-CSL)

t_d(CSH-CLKH)

t_w(CLKH)

Delay time, XSP_CLK low to XSP_CS low

Delay time, XSP_CS high to XSP_CLK high

Pulse duration, XSP_CLK high

2046P

t_w(CLKL)

Pulse duration, XSP_CLK low

t_{osu(DOV-CLKH)}

t_oh(CLKH-DOV)

Output setup time, XSP_DO valid before XSP_CLK high

Output hold time, XSP_DO valid after XSP_CLK high

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

2

1

XSP_CS

3

4

5

XSP_CLK

7

9

6

XSP_DO

8

XSP_DI

Figure 5-50. PCI Serial EEPROM Interface Timing

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5.13 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

•

Full-duplex communication

Double-buffered data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

•

External shift clock or an internal, programmable frequency shift clock for data transfer

For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel

Buffered Serial Port (McBSP) Reference Guide (literature number SPRU580).

5.13.1 McBSP Peripheral Register Description(s)

Table 5-48. McBSP 0 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

The CPU and EDMA controller

can only read this register; they

cannot write to it.

018C 0000

DRR0

McBSP0 data receive register via Configuration Bus

0x3000 0000 – 0x33FF FFFF

018C 0004

DRR0

DXR0

McBSP0 data receive register via Peripheral Bus

McBSP0 data transmit register via Configuration Bus

McBSP0 data transmit register via Peripheral Bus

McBSP0 serial port control register

0x3000 0000 – 0x33FF FFFF

018C 0008

DXR0

SPCR0

RCR0

018C 000C

McBSP0 receive control register

018C 0010

XCR0

McBSP0 transmit control register

018C 0014

SRGR0

MCR0

McBSP0 sample rate generator register

018C 0018

McBSP0 multichannel control register

018C 001C

RCERE00

XCERE00

PCR0

McBSP0 enhanced receive channel enable register 0

McBSP0 enhanced transmit channel enable register 0

McBSP0 pin control register

018C 0020

018C 0024

018C 0028

RCERE10

XCERE10

RCERE20

XCERE20

RCERE30

XCERE30

–

McBSP0 enhanced receive channel enable register 1

McBSP0 enhanced transmit channel enable register 1

McBSP0 enhanced receive channel enable register 2

McBSP0 enhanced transmit channel enable register 2

McBSP0 enhanced receive channel enable register 3

McBSP0 enhanced transmit channel enable register 3

Reserved

018C 002C

018C 0030

018C 0034

018C 0038

018C 003C

018C 0040 – 018F FFFF

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Table 5-49. McBSP 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

The CPU and EDMA controller

can only read this register; they

cannot write to it.

0190 0000

DRR1

McBSP1 data receive register via Configuration Bus

0x3400 0000 – 0x37FF FFFF

0190 0004

DRR1

DXR1

McBSP1 data receive register via peripheral bus

McBSP1 data transmit register via configuration bus

McBSP1 data transmit register via peripheral bus

McBSP1 serial port control register

0x3400 0000 – 0x37FF FFFF

0190 0008

DXR1

SPCR1

RCR1

0190 000C

McBSP1 receive control register

0190 0010

XCR1

McBSP1 transmit control register

0190 0014

SRGR1

MCR1

McBSP1 sample rate generator register

0190 0018

McBSP1 multichannel control register

0190 001C

RCERE01

XCERE01

PCR1

McBSP1 enhanced receive channel enable register 0

McBSP1 enhanced transmit channel enable register 0

McBSP1 pin control register

0190 0020

0190 0024

0190 0028

RCERE11

XCERE11

RCERE21

XCERE21

RCERE31

XCERE31

–

McBSP1 enhanced receive channel enable register 1

McBSP1 enhanced transmit channel enable register 1

McBSP1 enhanced receive channel enable register 2

McBSP1 enhanced transmit channel enable register 2

McBSP1 enhanced receive channel enable register 3

McBSP1 enhanced transmit channel enable register 3

Reserved

0190 002C

0190 0030

0190 0034

0190 0038

0190 003C

0190 0040 – 0193 FFFF

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5.13.2 McBSP Electrical Data/Timing

5.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing

Table 5-50. Timing Requirements for McBSP⁽¹⁾(see Figure 5-51)

–500

–600

–720

NO.

UNIT

MIN

MAX

2

3

t_c(CKRX)

t_w(CKRX)

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

4P or 6.67⁽²⁾⁽³⁾

0.5t_c(CKRX)– 1⁽⁴⁾

ns

Pulse duration, CLKR/X high or CLKR/X low

9

1.3

6

5

6

t_su(FRH-CKRL)

t_h(CKRL-FRH)

t_su(DRV-CKRL)

t_h(CKRL-DRV)

t_su(FXH-CKXL)

t_h(CKXL-FXH)

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

3

8

7

0.9

3

8

Hold time, DR valid after CLKR low

3.1

9

10

11

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

1.3

6

3

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock

source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA

limitations and AC timing requirements.

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

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Table 5-51. Switching Characteristics Over Recommended Operating Conditions for McBSP⁽¹⁾⁽²⁾

(see Figure 5-51)

–500

–600

NO.

PARAMETER

–720

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X

generated from CLKS input

1

t_{d(CKSH-CKRXH)}

1.4

10

ns

2

3

4

t_c(CKRX)

Cycle time, CLKR/X

CLKR/X int

4P or 6.67^(3)(4)(5)

C – 1⁽⁶⁾

–2.1

ns

t_w(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

FSX int

C + 1⁽⁶⁾

t_d(CKRH-FRV)

3

–1.7

3

9

t_d(CKXH-FXV)

t_{dis(CKXH-DXHZ)}

t_d(CKXH-DXV)

Delay time, CLKX high to internal FSX valid

ns

1.7

9

4

–3.9

Disable time, DX high impedance following last data

bit from CLKX high

12

13

–2.1

9

–3.9 + D1⁽⁷⁾

–2.1 + D1⁽⁷⁾

–2.3 + D1⁽⁸⁾

4 + D2⁽⁷⁾

9 + D2⁽⁷⁾

5.6 + D2⁽⁸⁾

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

14

t_d(FXH-DXV)

ns

ONLY applies when in data

delay 0 (XDATDLY = 00b) mode

FSX ext

1.9 + D1⁽⁸⁾

9 + D2⁽⁸⁾

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(5) Use whichever value is greater.

(6) C = H or L

S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(7) Extra delay from CLKX high to DX valid appliesonly to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

(8) Extra delay from FSX high to DX valid appliesonly to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

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CLKS

1

2

3

CLKR

4

FSR (int)

5

6

FSR (ext)

7

8

DR

Bit(n-1)

(n-2)

(n-3)

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

(A)

13

14

13

(A)

12

DX

Bit 0

Bit(n-1)

(n-2)

(n-3)

A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.

Figure 5-51. McBSP Timing

Table 5-52. Timing Requirements for FSR When GSYNC = 1 (see Figure 5-52)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

t_su(FRH-CKSH)

t_h(CKSH-FRH)

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

4

ns

CLKS

1

2

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

Figure 5-52. FSR Timing When GSYNC = 1

138

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Table 5-53. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 5-53)

–500

–600

–720

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

12

4

MAX

4

5

t_su(DRV-CKXL)

t_h(CKXL-DRV)

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

2 – 12P

5 + 24P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5-54. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾(see Figure 5-53)

–500

–600

–720

NO.

PARAMETER

UNIT

MASTER⁽³⁾

SLAVE

MIN

MAX

1

2

3

t_h(CKXL-FXL)

t_d(FXL-CKXH)

t_d(CKXH-DXV)

Hold time, FSX low after CLKX low⁽⁴⁾

Delay time, FSX low to CLKX high⁽⁵⁾

Delay time, CLKX high to DX valid

T – 2 T + 3

L – 2.5 L + 3

ns

–2

4

12P + 2.8 20P + 17

Disable time, DX high impedance following last data bit

from CLKX low

6

t_{dis(CKXL-DXHZ)}

L – 2 L + 3

ns

Disable time, DX high impedance following last data bit

from FSX high

7

8

t_{dis(FXH-DXHZ)}

t_d(FXL-DXV)

4P + 3 12P + 17

ns

Delay time, FSX low to DX valid

8P + 1.8 16P + 17

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-4)

Figure 5-53. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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Table 5-55. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽²⁾

(see Figure 5-54)

–500

–600

–720

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

12

4

MAX

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 12P

5 + 24P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5-56. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 11b, CLKXP = 0⁽¹⁾⁽²⁾(see Figure 5-54)

–500

–600

–720

NO.

PARAMETER

UNIT

MASTER⁽³⁾

SLAVE

MIN MAX

MIN

MAX

1

2

3

t_h(CKXL-FXL)

t_d(FXL-CKXH)

t_d(CKXL-DXV)

Hold time, FSX low after CLKX low⁽⁴⁾

Delay time, FSX low to CLKX high⁽⁵⁾

Delay time, CLKX low to DX valid

L – 2 L + 3

T – 2.5 T + 3

ns

–2

4

12P + 3 20P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

7

t_{dis(CKXL-DXHZ)}

t_d(FXL-DXV)

–2

4

ns

Delay time, FSX low to DX valid

H – 2 H + 4 8P + 2 16P + 17

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

7

FSX

DX

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

Bit 0

(n-2)

(n-4)

Figure 5-54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

140

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Table 5-57. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 5-55)

–500

–600

–720

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

12

4

MAX

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 12P

5 + 24P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5-58. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 10b, CLKXP = 1⁽¹⁾⁽²⁾(see Figure 5-55)

–500

–600

–720

NO.

PARAMETER

UNIT

MASTER⁽³⁾

SLAVE

MIN MAX

MIN

MAX

1

2

3

t_h(CKXH-FXL)

t_d(FXL-CKXL)

t_d(CKXL-DXV)

Hold time, FSX low after CLKX high⁽⁴⁾

Delay time, FSX low to CLKX low⁽⁵⁾

Delay time, CLKX low to DX valid

T – 2 T + 3

H – 2.5 H + 3

ns

–2

4

12P + 3 20P + 17

Disable time, DX high impedance following last data bit

from CLKX high

6

t_{dis(CKXH-DXHZ)}

H – 2 H + 3

ns

Disable time, DX high impedance following last data bit

from FSX high

7

8

t_{dis(FXH-DXHZ)}

t_d(FXL-DXV)

4P + 3 12P + 17

8P + 2 16P + 17

ns

Delay time, FSX low to DX valid

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 5-55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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Table 5-59. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾

(see Figure 5-56)

–500

–600

–720

NO.

UNIT

MASTER

SLAVE

MIN MAX

MIN

12

4

MAX

4

5

t_su(DRV-CKXH)

t_h(CKXH-DRV)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 12P

5 + 24P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 5-60. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 11b, CLKXP = 1⁽¹⁾⁽²⁾(see Figure 5-56)

–500

–600

–720

NO.

PARAMETER

UNIT

MASTER⁽³⁾

SLAVE

MIN MAX

MIN

MAX

H + 3

1

2

3

t_h(CKXH-FXL)

t_d(FXL-CKXL)

t_d(CKXH-DXV)

Hold time, FSX low after CLKX high⁽⁴⁾

Delay time, FSX low to CLKX low⁽⁵⁾

Delay time, CLKX high to DX valid

H – 2

ns

T – 2.5 T + 1.5

–2

4

12P + 3 20P + 17

Disable time, DX high impedance following last data bit

from CLKX high

6

7

t_{dis(CKXH-DXHZ)}

t_d(FXL-DXV)

–2

4

ns

Delay time, FSX low to DX valid

L – 2

L + 4 8P + 2 16P + 17

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3) S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

CLKX

1

2

FSX

DX

7

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

(n-2)

(n-3)

(n-4)

Figure 5-56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

142

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5.14 Video Port

Each Video Port is capable of sending and receiving digital video data. The Video Ports are also capable

of capturing/displaying RAW data. The Video Port peripherals follow video standards such as BT.656 and

SMPTE296.

5.14.1 Video Port Device-Specific Information

The TMS320DM642 device has three video port peripherals.

The video port peripheral can operate as a video capture port, video display port, or as a transport stream

interface (TSI) capture port.

The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the

two channels. The entire port (both channels) is always configured for either video capture or display only.

Separate data pipelines control the parsing and formatting of video capture or display data for each of the

BT.656, Y/C, raw video, and TSI modes.

For video capture operation, the video port may operate as two 8/10-bit channels of BT.656 or raw video

capture; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw

video, or 8-bit TSI.

For video display operation, the video port may operate as a single channel of 8/10-bit BT.656; or as a

single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20 bit Y/C video, or 16/20-bit raw video. It may

also operate in a two channel 8/10-bit raw mode in which the two channels are locked to the same timing.

Channel B is not used during single channel operation.

For more detailed information on the DM642 Video Port peripherals, see the TMS320C64x DSP Video

Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

5.14.2 Video Port Peripheral Register Description(s)

Table 5-61. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

01C4 0000

01C4 0004

01C4 0008

01C4 000C

01C4 0020

01C4 0024

01C4 0028

01C4 002C

01C4 0030

01C4 0034

01C4 0038

01C4 003C

01C4 0040

01C4 0044

01C4 00C0

01C4 00C4

01C4 00C8

01C4 00CC

01C4 0100

01C4 4000

01C4 4004

01C4 4008

01C4 400C

01C4 4020

01C4 4024

01C4 4028

01C4 402C

01C4 4030

01C4 4034

01C4 4038

01C4 403C

01C4 4040

01C4 4044

01C4 40C0

01C4 40C4

01C4 40C8

01C4 40CC

01C4 4100

01C4 8000

01C4 8004

01C4 8008

01C4 800C

01C4 8020

01C4 8024

01C4 8028

01C4 802C

01C4 8030

01C4 8034

01C4 8038

01C4 803C

01C4 8040

01C4 8044

01C4 80C0

01C4 80C4

01C4 80C8

01C4 80CC

01C4 8100

VP_PIDx

VP_PCRx

–

Video Port Peripheral Identification Register

Video Port Peripheral Control Register

Reserved

–

Reserved

VP_PFUNCx

VP_PDIRx

VP_PDINx

VP_PDOUTx

VP_PDSETx

VP_PDCLRx

VP_PIENx

VP_PIPOx

VP_PISTATx

VP_PICLRx

VP_CTLx

VP_STATx

VP_IEx

Video Port Pin Function Register

Video Port Pin Direction Register

Video Port Pin Data Input Register

Video Port Pin Data Output Register

Video Port Pin Data Set Register

Video Port Pin Data Clear Register

Video Port Pin Interrupt Enable Register

Video Port Pin Interrupt Polarity Register

Video Port Pin Interrupt Status Register

Video Port Pin Interrupt Clear Register

Video Port Control Register

Video Port Status Register

Video Port Interrupt Enable Register

Video Port interrupt Status Register

Video Capture Channel A Status Register

VP_ISx

VC_STATx

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SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 5-61. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

01C4 0104

01C4 0108

01C4 010C

01C4 0110

01C4 0114

01C4 0118

01C4 011C

01C4 0120

01C4 0140

01C4 0144

01C4 0148

01C4 014C

01C4 0150

01C4 0154

01C4 0158

01C4 015C

01C4 0160

01C4 0180

01C4 0184

01C4 0188

01C4 018C

01C4 0190

01C4 0194

01C4 0198

01C4 019C

01C4 01A0

01C4 01A4

01C4 0200

01C4 0204

01C4 0208

01C4 020C

01C4 0210

01C4 0214

01C4 0218

01C4 021C

01C4 0220

01C4 0224

01C4 0228

01C4 022C

01C4 0230

01C4 0234

01C4 0238

01C4 023C

01C4 0240

01C4 0244

01C4 0248

01C4 4104

01C4 4108

01C4 410C

01C4 4110

01C4 4114

01C4 4118

01C4 411C

01C4 4120

01C4 4140

01C4 4144

01C4 4148

01C4 414C

01C4 4150

01C4 4154

01C4 4158

01C4 415C

01C4 4160

01C4 4180

01C4 4184

01C4 4188

01C4 418C

01C4 4190

01C4 4194

01C4 4198

01C4 419C

01C4 41A0

01C4 41A4

01C4 4200

01C4 4204

01C4 4208

01C4 420C

01C4 4210

01C4 4214

01C4 4218

01C4 421C

01C4 4220

01C4 4224

01C4 4228

01C4 422C

01C4 4230

01C4 4234

01C4 4238

01C4 423C

01C4 4240

01C4 4244

01C4 4248

01C4 8104

01C4 8108

01C4 810C

01C4 8110

01C4 8114

01C4 8118

01C4 811C

01C4 8120

01C4 8140

01C4 8144

01C4 8148

01C4 814C

01C4 8150

01C4 8154

01C4 8158

01C4 815C

01C4 8160

01C4 8180

01C4 8184

01C4 8188

01C4 818C

01C4 8190

01C4 8194

01C4 8198

01C4 819C

01C4 81A0

01C4 81A4

01C4 8200

01C4 8204

01C4 8208

01C4 820C

01C4 8210

01C4 8214

01C4 8218

01C4 821C

01C4 8220

01C4 8224

01C4 8228

01C4 822C

01C4 8230

01C4 8234

01C4 8238

01C4 823C

01C4 8240

01C4 8244

01C4 8248

VC_CTLx

VC_ASTRTx

VC_ASTOPx

VC_ASTRTx

VC_ASTOPx

VC_AVINTx

VC_ATHRLDx

VC_AEVTCTx

VC_BSTATx

VC_BCTLx

Video Capture Channel A Control Register

Video Capture Channel A Field 1 Start Register

Video Capture Channel A Field 1 Stop Register

Video Capture Channel A Field 2 Start Register

Video Capture Channel A Field 2 Stop Register

Video Capture Channel A Vertical Interrupt Register

Video Capture Channel A Threshold Register

Video Capture Channel A Event Count Register

Video Capture Channel B Status Register

Video Capture Channel B Control Register

Video Capture Channel B Field 1 Start Register

Video Capture Channel B Field 1 Stop Register

Video Capture Channel B Field 2 Start Register

Video Capture Channel B Field 2 Stop Register

Video Capture Channel B Vertical Interrupt Register

Video Capture Channel B Threshold Register

Video Capture Channel B Event Count Register

TCI Capture Control Register

VC_BSTRTx

VC_BSTOPx

VC_BSTRTx

VC_BSTOPx

VC_BVINTx

VC_BTHRLDx

VC_BEVTCTx

TSI_CTLx

TSI_CLKINITLx TCI Clock Initialization LSB Register

TSI_CLKINITMx TCI Clock Initialization MSB Register

TSI_STCLKLx

TSI_STCLKMx

TSI_STCMPLx

TCI System Time Clock LSB Register

TCI System Time Clock MSB Register

TCI System Time Clock Compare LSB Register

TSI_STCMPMx TCI System Time Clock Compare MSB Register

TSI_STMSKLx TCI System Time Clock Compare Mask LSB Register

TSI_STMSKMx TCI System Time Clock Compare Mask MSB Register

TSI_TICKSx

VD_STATx

TCI System Time Clock Ticks Interrupt Register

Video Display Status Register

VD_CTLx

Video Display Control Register

VD_FRMSZx

VD_HBLNKx

VD_VBLKS1x

VD_VBLKE1x

VD_VBLKS2x

VD_VBLKE2x

Video Display Frame Size Register

Video Display Horizontal Blanking Register

Video Display Field 1 Vertical Blanking Start Register

Video Display Field 1 Vertical Blanking End Register

Video Display Field 2 Vertical Blanking Start Register

Video Display Field 2 Vertical Blanking End Register

VD_IMGOFF1x Video Display Field 1 Image Offset Register

VD_IMGSZ1x Video Display Field 1 Image Size Register

VD_IMGOFF2x Video Display Field 2 Image Offset Register

VD_IMGSZ2x

VD_FLDT1x

VD_FLDT2x

VD_THRLDx

VD_HSYNCx

VD_VSYNS1x

VD_VSYNE1x

VD_VSYNS2x

Video Display Field 2 Image Size Register

Video Display Field 1 Timing Register

Video Display Field 2 Timing Register

Video Display Threshold Register

Video Display Horizontal Synchronization Register

Video Display Field 1 Vertical Synchronization Start Register

Video Display Field 1 Vertical Synchronization End Register

Video Display Field 2 Vertical Synchronization Start Register

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Table 5-61. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

01C4 024C

01C4 0250

01C4 0254

01C4 0258

01C4 025C

01C4 0260

01C4 0264

01C4 0268

01C4 026C

7400 000

01C4 424C

01C4 4250

01C4 4254

01C4 4258

01C4 425C

01C4 4260

01C4 4264

01C4 4268

01C4 426C

7800 0000

7800 0008

7800 0010

7800 0020

7800 0028

7800 0030

7A00 0000

7A00 0008

7A00 0010

7A00 0020

01C4 824C

01C4 8250

01C4 8254

01C4 8258

01C4 825C

01C4 8260

01C4 8264

01C4 8268

01C4 826C

7C00 0000

7C00 0008

7C00 0010

7C00 0020

7C00 0028

7C00 0030

7E00 0000

7E00 0008

7E00 0010

7E00 0020

VD_VSYNE2x

VD_RELOADx

Video Display Field 2 Vertical Synchronization End Register

Video Display Counter Reload Register

VD_DISPEVTx Video Display Display Event Register

VD_CLIPx

VD_DEFVALx

VD_VINTx

VD_FBITx

VD_VBIT1x

VD_VBIT2x

Y_RSCA

Video Display Clipping Register

Video Display Default Display Value Register

Video Display Vertical Interrupt Register

Video Display Field Bit Register

Video Display Field 1Vertical Blanking Bit Register

Video Display Field 2Vertical Blanking Bit Register

Y FIFO Source Register A

7400 0008

7400 0010

7400 0020

7400 0028

7400 0030

7600 0000

7600 0008

7600 0010

7600 0020

CB_SRCA

CR_SRCA

Y_DSTA

CB FIFO Source Register A

CR FIFO Source Register A

Y FIFO Destination Register A

CB FIFO Destination Register

CB_DST

CR_DST

CR FIFO Destination Register

Y_SRCB

Y FIFO Source Register B

CB_SRCB

CR_SRCB

Y_DSTB

CB FIFO Source Register b

CR FIFO Source Register B

Y FIFO Destination Register B

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5.14.3 Video Port (VP0, VP1, VP2) Electrical Data/Timing

5.14.3.1 VCLKIN Timing (Video Capture Mode)

Table 5-62. Timing Requirements for Video Capture Mode for VPxCLKINx⁽¹⁾

(see Figure 5-57)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(VKI)

Cycle time, VPxCLKINx

12.5

5.4

ns

t_w(VKIH)

t_w(VKIL)

t_t(VKI)

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx

5.4

3

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

VPxCLKINx

4

Figure 5-57. Video Port Capture VPxCLKINx TIming

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5.14.3.2 Video Data and Control Timing (Video Capture Mode)

Table 5-63. Timing Requirements in Video Capture Mode for Video Data and Control Inputs

(see Figure 5-58)

–500

–600

–720

NO.

UNIT

MIN

2.9

0.5

2.9

0.5

MAX

1

2

3

4

t_{su(VDATV-VKIH)}Setup time, VPxDx valid before VPxCLKINx high

ns

t_{h(VDATV-VKIH)}

t_{su(VCTLV-VKIH)}

t_{h(VCTLV-VKIH)}

Hold time, VPxDx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

VPxCLKINx

1

3

2

VPxD[19:0] (Input)

VPxCTLx (Input)

4

Figure 5-58. Video Port Capture Data and Control Input Timing

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5.14.3.3 VCLKIN Timing (Video Display Mode)

Table 5-64. Timing Requirements for Video Display Mode for VPxCLKINx⁽¹⁾(see Figure 5-59)

–500

–600

–720

NO.

UNIT

MIN

9

MAX

1

2

3

4

t_c(VKI)

Cycle time, VPxCLKINx

ns

t_w(VKIH)

t_w(VKIL)

t_t(VKI)

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx

4.1

3

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

VPxCLKINx

4

Figure 5-59. Video Port Display VPxCLKINx Timing

5.14.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx

and VPxCLKOUTx (Video Display Mode)

Table 5-65. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to

VPxCLKINx and VPxCLKOUTx (see Figure 5-60)

–500

–600

–720

NO.

UNIT

MIN

MAX

13 t_{su(VCTLV-VKIH)}

14 t_{h(VCTLV-VKIH)}

15 t_{su(VCTLV-VKOH)}

16 t_{h(VCTLV-VKOH)}

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKOUTx high⁽¹⁾

Hold time, VPxCTLx valid after VPxCLKOUTx high⁽¹⁾

2.9

0.5

ns

7.4

–0.9

(1) Assuming non-inverted VPxCLKOUTx signal.

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Table 5-66. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode

for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx⁽¹⁾⁽²⁾

(see Figure 5-60)

–500

–600

–720

MIN

V – 0.7

NO.

PARAMETER

UNIT

MAX

1

2

3

4

5

6

7

8

9

t_c(VKO)

Cycle time, VPxCLKOUTx

V + 0.7

ns

t_w(VKOH)

Pulse duration, VPxCLKOUTx high

VH – 0.7 VH + 0.7

VL – 0.7 VL + 0.7

1.8

t_w(VKOL)

Pulse duration, VPxCLKOUTx low

t_t(VKO)

Transition time, VPxCLKOUTx

t_d(VKIH-VKOH)

t_d(VKIL-VKOL)

t_d(VKIH-VKOL)

t_d(VKIL-VKOH)

t_{d(VKIH-VPOUTV)}

Delay time, VPxCLKINx high to VPxCLKOUTx high⁽³⁾

Delay time, VPxCLKINx low to VPxCLKOUTx low⁽³⁾

Delay time, VPxCLKINx high to VPxCLKOUTx low

Delay time, VPxCLKINx low to VPxCLKOUTx high

Delay time, VPxCLKINx high to VPxOUT valid⁽⁴⁾

Delay time, VPxCLKINx high to VPxOUT invalid⁽⁴⁾

Delay time, VPxCLKOUTx high to VPxOUT valid⁽¹⁾⁽⁴⁾

Delay time, VPxCLKOUTx high to VPxOUT invalid⁽¹⁾⁽⁴⁾

1.1

5.7

9

10 t_{d(VKIH-VPOUTIV)}

11 t_{d(VKOH-VPOUTV)}

12 t_{d(VKOH-VPOUTIV)}

1.7

4.3

–0.2

(1) V = the video input clock (VPxCLKINx) period in ns.

(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.

(3) Assuming non-inverted VPxCLKOUTx signal.

(4) VPxOUT consists of VPxCTLx and VPxD[19:0]

VPxCLKINx

5

7

2

1

6

8

3

VPxCLKOUTx

[VCLK2P = 0]

4

VPxCLKOUTx

(Inverted)

[VCLK2P = 1]

12

10

11

9

VPxCTLx,V

PxD[19:0]

(Outputs)

15

16

14

13

VPxCTLx

(Input)

Figure 5-60. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to

VPxCLKINx and VPxCLKOUTx

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5.14.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)

Table 5-67. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 5-61)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

t_skr(VKI)

Skew rate, VPxCLKINx before VPyCLKINy

±500

ps

VPxCLKINx

1

VPyCLKINy

Figure 5-61. Video Port Dual-Display Sync Timing

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5.15 VCXO Interpolated Control (VIC)

The VIC can be used in conjunction with the Video Ports (VPs) to maintain synchronization of a video

stream. The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.

5.15.1 VIC Device-Specific Information

The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from

9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).

Typical D/A converters provide a discrete output level for every value of the digital word that is being

converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A

converter by choosing a few widely spaced output levels and interpolating values between them. The

interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that

the average output represents the value of input code.

In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented

to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is

dependent on the resolution needed.

When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the

system clock, VCXO, for MPEG transport stream.

The VIC supports the following features:

•

Single interpolation for D/A conversion

Programmable precision from 9-to-16 bits

Interface for register accesses

For more detailed information on the DM642 VCXO interpolated control (VIC) peripheral, see the

TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number

SPRU629).

5.15.2 VIC Peripheral Register Description(s)

Table 5-68. VCXO Interpolated Control (VIC) Port Registers

HEX ADDRESS RANGE

01C4 C000

ACRONYM

VICCTL

VICIN

REGISTER NAME

VIC control register

01C4 C004

VIC input register

VIC clock divider register

Reserved

01C4 C008

VPDIV

–

01C4 C00C – 01C4 FFFF

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5.15.3 VIC Electrical Data/Timing

5.15.3.1 STCLK Timing

Table 5-69. Timing Requirments for STCLK⁽¹⁾(see Figure 5-62)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(STCLK)

t_w(STCLKH)

t_w(STCLKL)

t_t(STCLK)

Cycle time, STCLK

33.3

16

ns

Pulse duration, STCLK high

Pulse duration, STCLK low

Transition time, STCLK

16

3

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

STCLK

4

Figure 5-62. STCLK Timing

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5.16 Ethernet Media Access Controller (EMAC)

The EMAC controls the flow of packet data from the DSP to the PHY.

5.16.1 EMAC Device-Specific Information

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP

core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or

10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality

of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that

allows efficient data transmission and reception.

The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY

configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows

efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

control device reset, interrupts, and system priority.

The TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output

(MDIO) Module Reference Guide (literature number SPRU628) describes the DM642 EMAC peripheral in

detail. Some of the features documented in this peripheral reference guide are not supported on the

DM642 at this time. The DM642 supports one receive channel and does not support receive quality of

service (QOS). For a list of supported registers and register fields, see Table 5-70 [Ethernet MAC (EMAC)

Control Registers] and Table 5-71 [EMAC Statistics Registers] in this data manual.

5.16.2 EMAC Peripheral Register Description(s)

Table 5-70. Ethernet MAC (EMAC) Control Registers

HEX ADDRESS RANGE

01C8 0000

ACRONYM

TXIDVER

REGISTER NAME

Transmit Identification and Version Register

01C8 0004

TXCONTROL

TXTEARDOWN

–

Transmit Control Register

Transmit Teardown Register

Reserved

01C8 0008

01C8 000C

01C8 0010

RXIDVER

Receive Identification and Version Register

Receive Control Register

01C8 0014

RXCONTROL

Receive Teardown Register

(RXTDNCH field only supports writes of 0.)

01C8 0018

RXTEARDOWN

–

01C8 001C – 01C8 00FF

Reserved

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

(The RXQOSEN field is reserved and only supports writes of 0. The PROMCH,

BROADCH, and MUCTCH bit fields only support writes of 0.)

01C8 0100

RXMBPENABLE

Receive Unicast Set Register

(Bits 7–1 are reserved and only support writes of 0.)

01C8 0104

01C8 0108

RXUNICASTSET

Receive Unicast Clear Register

(Bits 7–1 are reserved and only support writes of 0.)

RXUNICASTCLEAR

01C8 010C

01C8 0110

RXMAXLEN

Receive Maximum Length Register

Receive Buffer Offset Register

RXBUFFEROFFSET

01C8 0114

RXFILTERLOWTHRESH Receive Filter Low Priority Packets Threshold Register

01C8 0118 – 01C8 011F

01C8 0120

–

Reserved

RX0FLOWTHRESH

Receive Channel 0 Flow Control Threshold Register

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Table 5-70. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS RANGE

01C8 0124

ACRONYM

RX1FLOWTHRESH

RX2FLOWTHRESH

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

RX7FLOWTHRESH

RX0FREEBUFFER

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

REGISTER NAME

01C8 0128

01C8 012C

01C8 0130

Reserved. Do not write.

01C8 0134

01C8 0138

01C8 013C

01C8 0140

Receive Channel 0 Free Buffer Count Register

01C8 0144

01C8 0148

01C8 014C

01C8 0150

Reserved. Do not write.

01C8 0154

01C8 0158

01C8 015C

01C8 0160

MAC Control Register

01C8 0164

MAC Status Register (RXQOSACT field is reserved.)

Reserved

01C8 0168 – 01C8 016C

01C8 0170

–

TXINTSTATRAW

TXINTSTATMASKED

TXINTMASKSET

TXINTMASKCLEAR

MACINVECTOR

–

Transmit Interrupt Status (Unmasked) Register

Transmit Interrupt Status (Masked) Register

Transmit Interrupt Mask Set Register

Transmit Interrupt Mask Clear Register

MAC Input Vector Register

01C8 0174

01C8 0178

01C8 017C

01C8 0180

01C8 0184 – 01C8 018F

Reserved

Receive Interrupt Status (Unmasked) Register

(Bits 7–1 are reserved.)

01C8 0190

01C8 0194

01C8 0198

01C8 019C

RXINTSTATRAW

RXINTSTATMASKED

RXINTMASKSET

Receive Interrupt Status (Masked) Register

(Bits 7–1 are reserved.)

Receive Interrupt Mask Set Register

(Bits 7–1 are reserved and only support writes of 0.)

Receive Interrupt Mask Clear Register

(Bits 7–1 are reserved and only support writes of 0.)

RXINTMASKCLEAR

01C8 01A0

01C8 01A4

01C8 01A8

01C8 01AC

01C8 01B0

01C8 01B4

01C8 01B8

01C8 01BC

01C8 01C0

01C8 01C4

01C8 01C8

01C8 01CC

01C8 01D0

01C8 01D4

01C8 01D8

01C8 01DC

MACINTSTATRAW

MACINTSTATMASKED

MACINTMASKSET

MACINTMASKCLEAR

MACADDRL0

MAC Interrupt Status (Unmasked) Register

MAC Interrupt Status (Masked) Register

MAC Interrupt Mask Set Register

MAC Interrupt Mask Clear Register

MAC Address Channel 0 Lower Byte Register

MACADDRL1

MACADDRL2

MACADDRL3

MACADDRL4

Reserved. Do not write.

MACADDRL5

MACADDRL6

MACADDRL7

MACADDRM

MAC Address Middle Byte Register

MAC Address High Bytes Register

MAC Address Hash 1 Register

MAC Address Hash 2 Register

MACADDRH

MACHASH1

MACHASH2

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Table 5-70. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS RANGE

01C8 01E0

ACRONYM

BOFFTEST

TPACETEST

RXPAUSE

TXPAUSE

–

REGISTER NAME

Backoff Test Register

01C8 01E4

Transmit Pacing Test Register

Receive Pause Timer Register

Transmit Pause Timer Register

Reserved

01C8 01E8

01C8 01EC

01C8 01F0 – 01C8 01FF

01C8 0200 – 01C8 05FF

01C8 0600

(see Table 5-71)

TX0HDP

EMAC Statistics Registers

Transmit Channel 0 DMA Head Descriptor Pointer Register

Transmit Channel 1 DMA Head Descriptor Pointer Register

Transmit Channel 2 DMA Head Descriptor Pointer Register

Transmit Channel 3 DMA Head Descriptor Pointer Register

Transmit Channel 4 DMA Head Descriptor Pointer Register

Transmit Channel 5 DMA Head Descriptor Pointer Register

Transmit Channel 6 DMA Head Descriptor Pointer Register

Transmit Channel 7 DMA Head Descriptor Pointer Register

Receive Channel 0 DMA Head Descriptor Pointer Register

01C8 0604

TX1HDP

01C8 0608

TX2HDP

01C8 060C

01C8 0610

TX3HDP

TX4HDP

01C8 0614

TX5HDP

01C8 0618

TX6HDP

01C8 061C

01C8 0620

TX7HDP

RX0HDP

01C8 0624

RX1HDP

01C8 0628

RX2HDP

01C8 062C

01C8 0630

RX3HDP

RX4HDP

Reserved. Do not write.

01C8 0634

RX5HDP

01C8 0638

RX6HDP

01C8 063C

01C8 0640

RX7HDP

TX0INTACK

TX1INTACK

TX2INTACK

TX3INTACK

TX4INTACK

TX5INTACK

TX6INTACK

TX7INTACK

RX0INTACK

RX1INTACK

RX2INTACK

RX3INTACK

RX4INTACK

RX5INTACK

RX6INTACK

RX7INTACK

–

Transmit Channel 0 Interrupt Acknowledge Register

Transmit Channel 1 Interrupt Acknowledge Register

Transmit Channel 2 Interrupt Acknowledge Register

Transmit Channel 3 Interrupt Acknowledge Register

Transmit Channel 4 Interrupt Acknowledge Register

Transmit Channel 5 Interrupt Acknowledge Register

Transmit Channel 6 Interrupt Acknowledge Register

Transmit Channel 7 Interrupt Acknowledge Register

Receive Channel 0 Interrupt Acknowledge Register

01C8 0644

01C8 0648

01C8 064C

01C8 0650

01C8 0654

01C8 0658

01C8 065C

01C8 0660

01C8 0664

01C8 0668

01C8 066C

01C8 0670

Reserved. Do not write.

01C8 0674

01C8 0678

01C8 067C

01C8 0680 – 01C8 0FFF

Reserved

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Table 5-71. EMAC Statistics Registers

HEX ADDRESS RANGE

01C8 0200

01C8 0204

01C8 0208

01C8 020C

01C8 0210

01C8 0214

01C8 0218

01C8 021C

01C8 0220

01C8 0224

01C8 0228

01C8 022C

01C8 0230

01C8 0234

01C8 0238

01C8 023C

01C8 0240

01C8 0244

01C8 0248

01C8 024C

01C8 0250

01C8 0254

01C8 0258

01C8 025C

01C8 0260

01C8 0264

01C8 0268

01C8 026C

01C8 0270

01C8 0274

01C8 0278

01C8 027C

01C8 0280

01C8 0284

01C8 0288

01C8 028C

01C8 0290 – 01C8 05FF

ACRONYM

RXGOODFRAMES

REGISTER NAME

Good Receive Frames Register

RXBCASTFRAMES

RXMCASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

RXALIGNCODEERRORS

RXOVERSIZED

RXJABBER

Broadcast Receive Frames Register

Multicast Receive Frames Register

Pause Receive Frames Register

Receive CRC Errors Register

Receive Alignment/Code Errors Register

Receive Oversized Frames Register

Receive Jabber Frames Register

Receive Undersized Frames Register

Receive Frame Fragments Register

Filtered Receive Frames Register

Reserved

RXUNDERSIZED

RXFRAGMENTS

RXFILTERED

RXQOSFILTERED

RXOCTETS

Receive Octet Frames Register

Good Transmit Frames Register

Broadcast Transmit Frames Register

Multicast Transmit Frames Register

Pause Transmit Frames Register

Deferred Transmit Frames Register

Collision Register

TXGOODFRAMES

TXBCASTFRAMES

TXMCASTFRAMES

TXPAUSEFRAMES

TXDEFERRED

TXCOLLISION

TXSINGLECOLL

TXMULTICOLL

TXEXCESSIVECOLL

TXLATECOLL

Single Collision Transmit Frames Register

Multiple Collision Transmit Frames Register

Excessive Collisions Register

Late Collisions Register

TXUNDERRUN

TXCARRIERSLOSS

TXOCTETS

Transmit Underrun Register

Transmit Carrier Sense Errors Register

Transmit Octet Frames Register

Transmit and Receive 64 Octet Frames Register

FRAME64

FRAME65T127

FRAME128T255

FRAME256T511

FRAME512T1023

FRAME1024TUP

NETOCTETS

Transmit and Receive 65 to 127 Octet Frames Register

Transmit and Receive 128 to 255 Octet Frames Register

Transmit and Receive 256 to 511 Octet Frames Register

Transmit and Receive 512 to 1023 Octet Frames Register

Transmit and Receive 1024 or Above Octet Frames Register

Network Octet Frames Register

RXSOFOVERRUNS

RXMOFOVERRUNS

RXDMAOVERRUNS

–

Receive Start of Frame Overruns Register

Receive Middle of Frame Overruns Register

Receive DMA Overruns Register

Reserved

Table 5-72. EMAC Wrapper

HEX ADDRESS RANGE

01C8 1000 – 01C8 1FFF

01C8 2000 – 01C8 2FFF

ACRONYM

REGISTER NAME

EMAC Control Module Descriptor Memory

Reserved

–

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Table 5-73. EWRAP Registers

HEX ADDRESS RANGE

01C8 3000

ACRONYM

EWTRCTRL

EWCTL

REGISTER NAME

TR control

01C8 3004

Interrupt control register

Interrupt timer count

Reserved

01C8 3008

EWINTTCNT

–

01C8 300C – 01C8 37FF

5.16.3 EMAC Electrical Data/Timing

Table 5-74. Timing Requirements for MRCLK (see Figure 5-63)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

t_c(MRCLK)

Cycle time, MRCLK

40

14

ns

t_w(MRCLKH)

t_w(MRCLKL)

Pulse duration, MRCLK high

Pulse duration, MRCLK low

1

2

3

MRCLK

Figure 5-63. MRCLK Timing (EMAC – Receive)

Table 5-75. Timing Requirements for MTCLK (see Figure 5-63)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

t_c(MTCLK)

Cycle time, MTCLK

40

14

ns

t_w(MTCLKH)

t_w(MTCLKL)

Pulse duration, MTCLK high

Pulse duration, MTCLK low

1

2

3

MTCLK

Figure 5-64. MTCLK Timing (EMAC – Transmit)

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Table 5-76. Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾(see Figure 5-65)

–500

–600

–720

NO.

UNIT

MIN

8

MAX

1

2

t_{su(MRXD-MRCLKH)}

t_{h(MRCLKH-MRXD)}

Setup time, receive selected signals valid before MRCLK high

Hold time, receive selected signals valid after MRCLK high

ns

8

(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.

1

2

MRCLK (Input)

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

Figure 5-65. EMAC Receive Interface Timing

Table 5-77. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit

10/100 Mbit/s⁽¹⁾(see Figure 5-66)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

t_{d(MTCLKH-MTXD)}

Delay time, MTCLK high to transmit selected signals valid

5

25

ns

(1) Transmit selected signals include: MTXD3–MTXD0, and MTXEN.

1

MTCLK (Input)

MTXD3−MTXD0,

MTXEN (Outputs)

Figure 5-66. EMAC Transmit Interface Timing

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5.17 Management Data Input/Output (MDIO)

The MDIO module controls PHY configuration and status monitoring.

5.17.1 Device-Specific Information

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system.

The management data input/output (MDIO) module implements the 802.3 serial management interface to

interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO

module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the

negotiation results, and configure required parameters in the EMAC module for correct operation. The

module is designed to allow almost transparent operation of the MDIO interface, with very little

maintenance from the core processor.

The TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output

(MDIO) Module Reference Guide (literature number SPRU628) describes the DM642 MDIO peripheral in

detail. Some of the features documented in this peripheral reference guide are not supported on the

DM642 at this time. The DM642 only supports one EMAC module. For a list of supported registers and

register fields, see Table 5-78 [MDIO Registers] in this data manual.

5.17.2 Peripheral Register Description(s)

Table 5-78. MDIO Registers

HEX ADDRESS RANGE

01C8 3800

ACRONYM

VERSION

CONTROL

ALIVE

REGISTER NAME

MDIO Version Register

MDIO Control Register

01C8 3804

01C8 3808

MDIO PHY Alive Indication Register

MDIO PHY Link Status Register

01C8 380C

LINK

MDIO Link Status Change Interrupt Register

(MAC1 field is reserved and only supports writes of 0.)

01C8 3810

01C8 3814

01C8 3818

01C8 381C

01C8 3820

01C8 3824

LINKINTRAW

LINKINTMASKED

USERINTRAW

MDIO Link Status Change Interrupt (Masked) Register

(MAC1 field is reserved and only supports writes of 0.)

MDIO User Command Complete Interrupt Register

(MAC1 field is reserved and only supports writes of 0.)

MDIO User Command Complete Interrupt (Masked) Register

(MAC1 field is reserved and only supports writes of 0.)

USERINTMASKED

USERINTMASKSET

USERINTMASKCLEAR

MDIO User Command Complete Interrupt Mask Set Register

(MAC1 field is reserved and only supports writes of 0.)

MDIO User Command Complete Interrupt Mask Clear Register

(MAC1 field is reserved and only supports writes of 0.)

01C8 3828

01C8 382C

USERACCESS0

USERACCESS1

USERPHYSEL0

USERPHYSEL1

–

MDIO User Access Register 0

Reserved. Do not write.

MDIO User PHY Select Register 0

Reserved. Do not write.

Reserved

01C8 3830

01C8 3834

01C8 3838 – 01C8 3FFF

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5.17.3 Management Data Input/Output (MDIO) Electrical Data/Timing

Table 5-79. Timing Requirements for MDIO Input (see Figure 5-67)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(MDCLK)

Cycle time, MDCLK

400

180

10

ns

t_w(MDCLK)

Pulse duration, MDCLK high/low

t_{su(MDIO-MDCLKH)}

t_{h(MDCLKH-MDIO)}

Setup time, MDIO data input valid before MDCLK high

Hold time, MDIO data input valid after MDCLK high

0

1

MDCLK

3

4

MDIO

(input)

Figure 5-67. MDIO Input Timing

Table 5-80. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

(see Figure 5-68)

–500

–600

–720

MIN

–10

NO.

UNIT

MAX

7

t_{d(MDCLKL-MDIO)}

Delay time, MDCLK low to MDIO data output valid

100

ns

1

MDCLK

7

MDIO

(output)

Figure 5-68. MDIO Output Timing

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5.18 Timer

The C6000™ DSP device has 32-bit general-purpose timers that can be used to:

•

Time events

Count events

Generate pulses

Interrupt the CPU

Send synchronization events to the DMA

The timers have two signaling modes and can be clocked by an internal or an external source. The timers

have an input pin and an output pin. The input and output pins (TINP and TOUT) can function as timer

clock input and clock output. They can also be respectively configured for general-purpose input and

output.

With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or

it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count

external events and interrupt the CPU after a specified number of events.

5.18.1 Timer Device-Specific Information

The DM642 device has a total of three 32-bit general-purpose timers (Timer0, Timer1, and Timer2).

Timer2 is not externally pinned out.

For more detailed information, see the TMS320C6000 DSP 32-Bit Timer Reference Guide (literature

number SPRU582).

5.18.2 Timer Peripheral Register Description(s)

Table 5-81. Timer 0 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Determines the operating mode of the timer, monitors the

timer status, and controls the function of the TOUT pin.

0194 0000

CTL0

Timer 0 control register

Contains the number of timer input clock cycles to count.

This number controls the TSTAT signal frequency.

0194 0004

PRD0

Timer 0 period register

0194 0008

CNT0

–

Timer 0 counter register

Reserved

Contains the current value of the incrementing counter.

0194 000C – 0197 FFFF

Table 5-82. Timer 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Determines the operating mode of the timer, monitors the

timer status, and controls the function of the TOUT pin.

0198 0000

CTL1

Timer 1 control register

Timer 1 period register

Contains the number of timer input clock cycles to count.

This number controls the TSTAT signal frequency.

0198 0004

PRD1

0198 0008

CNT1

–

Timer 1 counter register

Reserved

Contains the current value of the incrementing counter.

0198 000C – 019B FFFF

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Table 5-83. Timer 2 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Determines the operating mode of the timer, monitors the

timer status.

01AC 0000

CTL2

Timer 2 control register

Contains the number of timer input clock cycles to count.

This number controls the TSTAT signal frequency.

01AC 0004

PRD2

Timer 2 period register

01AC 0008

CNT2

–

Timer 2 counter register

Reserved

Contains the current value of the incrementing counter.

01AC 000C – 01AF FFFF

5.18.3 Timer Electrical Data/Timing

Table 5-84. Timing Requirements for Timer Inputs⁽¹⁾(see Figure 5-69)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

t_w(TINPH)

t_w(TINPL)

Pulse duration, TINP high

Pulse duration, TINP low

8P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

Table 5-85. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs⁽¹⁾

(see Figure 5-69)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

3

4

t_w(TOUTH)

t_w(TOUTL)

Pulse duration, TOUT high

Pulse duration, TOUT low

8P – 3

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

2

1

TINPx

4

3

TOUTx

Figure 5-69. Timer Timing

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5.19 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or

outputs. When configured as an output, you can write to an internal register to control the state driven on

the output pin. When configured as an input, you can detect the state of the input by reading the state of

an internal register.

In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event

generation modes.

5.19.1 GPIO Device-Specific Information

To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register

and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.

GPxEN = 1

GPxDIR = 0

GPxDIR = 1

GP[x] pin is enabled

GP[x] pin is an input

GP[x] pin is an output

where "x" represents one of the 15 through 0 GPIO pins

Figure 5-70 shows the GPIO enable bits in the GPEN register for the DM642 device. To use any of the

GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to "1"

(enabled). Default values are device-specific, so refer to Figure 5-70 for the DM642 default configuration.

31

15

16

Reserved

R-0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GP15 GP14 GP13 GP12 GP11 GP10

EN EN EN EN EN EN

GP9

EN

GP8

EN

GP7

EN

GP6

EN

GP5

EN

GP4

EN

GP3

EN

GP2

EN

GP1

EN

GP0

EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1

Legend: R/W = Readable/Writable, -n = value after reset, -x = undefined value after reset

Figure 5-70. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]

Figure 5-71 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO

pin is an input or an output providing the corresponding GPxEN bit is enabled (set to "1") in the GPEN

register. By default, all the GPIO pins are configured as input pins.

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31

16

Reserved

R-0

15

GP15 GP14 GP13 GP12 GP11 GP10

DIR DIR DIR DIR DIR DIR

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GP9

DIR

GP8

DIR

GP7

DIR

GP6

DIR

GP5

DIR

GP4

DIR

GP3

DIR

GP2

DIR

GP1

DIR

GP0

DIR

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1

Legend: R/W = Readable/Writable, -n = value after reset, -x = undefined value after reset

Figure 5-71. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]

For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP

General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

5.19.2 GPIO Peripheral Register Description(s)

Table 5-86. GP0 Registers

HEX ADDRESS RANGE

01B0 0000

ACRONYM

GPEN

GPDIR

GPVAL

–

REGISTER NAME

GP0 enable register

GP0 direction register

GP0 value register

01B0 0004

01B0 0008

01B0 000C

Reserved

01B0 0010

GPDH

GPHM

GPDL

GPLM

GPGC

GPPOL

–

GP0 delta high register

GP0 high mask register

GP0 delta low register

GP0 low mask register

GP0 global control register

GP0 interrupt polarity register

Reserved

01B0 0014

01B0 0018

01B0 001C

01B0 0020

01B0 0024

01B0 0028 – 01B3 EFFF

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5.19.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing

Table 5-87. Timing Requirements for GPIO Inputs⁽¹⁾⁽²⁾(see Figure 5-72)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

2

t_w(GPIH)

t_w(GPIL)

Pulse duration, GPIx high

Pulse duration, GPIx low

8P

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize

the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP

enough time to access the GPIO register through the CFGBUS.

Table 5-88. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs⁽¹⁾

(see Figure 5-72)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

3

4

t_w(GPOH)

t_w(GPOL)

Pulse duration, GPOx high

Pulse duration, GPOx low

24P – 8⁽²⁾

ns

(1) P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(2) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the

GPIO is dependent upon internal bus activity.

2

1

GPIx

4

3

GPOx

Figure 5-72. GPIO Port Timing

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5.20 JTAG

The JTAG interface is used for BSDL testing and emulation of the DM642 device.

Note: IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

5.20.1 JTAG Device-Specific Information

5.20.1.1 IEEE 1149.1 JTAG Compatibility Statement

The TMS320DM642 DSP requires that both TRST and RESET be asserted upon power up to be properly

initialized. While RESET initializes the DSP core, TRST initializes the DSP's emulation logic. Both resets

are required for proper operation.

Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as

expected after TRST is asserted.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for

the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port

interface and DSP's emulation logic in the reset state. TRST only needs to be released when it is

necessary to use a JTAG controller to debug the DSP or exercise the DSP's boundary scan functionality.

RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE

correctly. Other boundary-scan instructions work correctly independent of current state of RESET.

For maximum reliability, the TMS320DM642 DSP includes an internal pulldown (IPD) on the TRST pin to

ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will

always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high.

However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup

resistor on TRST. When using this type of JTAG controller, assert TRST to intialize the DSP after powerup

and externally drive TRST high before attempting any emulation or boundary scan operations.

Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of

EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation

mode. For more detailed information, see the terminal functions section of this data sheet.

Note: The DESIGN_WARNING section of the TMS320DM642 BSDL file contains information and

constraints regarding proper device operation while in Boundary Scan Mode.

5.20.1.2 JTAG ID Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

DM642 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value for

the DM642 device is: 0x0007 902F. For the actual register bit names and their associated bit field

descriptions, see Figure 5-73 and Table 5-89.

31-28

27-12

11-1

0

VARIANT (4-Bit)

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

R-0000

R-0000 0000 0111 1001

R-0000 0010 111

R-1

Legend: R = Read only, -n = value after reset

Figure 5-73. JTAG ID Register Description – TMS320DM642 Register Value – 0x0007 902F

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Table 5-89. JTAG ID Register Selection Bit Descriptions

BIT

31:28

27:12

11–1

0

NAME

VARIANT

DESCRIPTION

Variant (4-Bit) value. DM642 value: 0000.

Part Number (16-Bit) value. DM642 value: 0000 0000 0111 1001.

PART NUMBER

MANUFACTURER Manufacturer (11-Bit) value. DM642 value: 0000 0010 111.

LSB LSB. This bit is read as a "1" for DM642.

5.20.2 JTAG Peripheral Register Description(s)

Table 5-90. JTAG ID Register

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

JTAG Identification Register

COMMENTS

Read-only. Provides 32-bit

JTAG ID of the device.

01B3 F008

JTAGID

5.20.3 JTAG Test-Port Electrical Data/Timing

Table 5-91. Timing Requirements for JTAG Test Port (see Figure 5-74)

–500

–600

–720

NO.

UNIT

MIN

MAX

1

3

4

t_c(TCK)

Cycle time, TCK

35

10

9

ns

t_{su(TDIV-TCKH)}

t_h(TCKH-TDIV)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

Table 5-92. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port

(see Figure 5-74)

–500

–600

–720

NO.

PARAMETER

UNIT

MIN

MAX

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

18

ns

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 5-74. JTAG Test-Port Timing

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Revision History

This data sheet revision history highlights the technical changes made to the SPRS200H device-specific

data sheet to make it an SPRS200I revision. It also highlights technical changes made to SPRS200I to

generate SPRS200J; these changes are marked by "[Revision J]" in the Revision History table below.

Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM642 device,

have been incorporated.

Added device-specific information for 600 extended temperature device (A-600).

8-bit TSI Video Port mode now supported.

Added the device-specific information supporting the TMS320DM642 silicon revision 2.0 device, which is

now in the production data (PD) stage of development (see ADDS/CHANGES/DELETES).

Continued incorporation of new format/outline structure. Updated/corrected device-specific information for

clarity.

SEE

ADDS/CHANGES/DELETES

Clarified PCI66 signal as active low (PCI66) [Revision J]

Global Update

Device Overview, Terminal Functions table, Reset, Interrupts, and General-Purpose Input/Outputs section:

Updated Description for NMI signal name

Deleted the note in the GP03 pin description

CLKOUT6/[GPO/2] - Changed IPD to IPU [Revision J]

CLKOUT4/[GPO/1] - Changed IPD to IPU [Revision J]

Device Overview, Terminal Functions table, Host-Port Interface (HPI) or Peripheral Component Interconnect

(PCI) or EMAC section:

Deleted the note in the GP03 pin description

Device Overview, Terminal Functions table, Reserved for Test section:

Updated Description for RSV0-RSV6 signal names

Device Support, Device and Development-Support Tool Nomenclature, TMS320DM64x DSP Device

Nomenclature (Including the TMS320DM642 Device) figure:

Updated figure

Device Configurations, Device Configuration at Device Reset section:

DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA [22:19], GP0[3]/PCIEEAI, VDAC/GP0[8]/PCI66,

HD5/AD5, PCI_EN, AND MAC-EN) table:

Deleted the note in the GP03/PCIEEAI pin description

Device Configurations, Multiplexed Pin Configuratons section:

DM642 Device Multiplexed Pin Configurations table:

Updated the Default Function from "PCI66" to "VDAC" for VDAC/GPO[8] Multiplexed Pins Name

DM642 Peripheral Information and Electrical Specifications, Clock PLL Electrical Data/Timing (Input and

Output Clocks) section:

Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module

table:

Updated Parameter No. 5, from t_{d(EKIH-EK02L)}to t_{d(EKIL-EK02L)}

Updated Parameter No. 5 from "Delay time, AECLKIN high to AECLKOUT2 low" to "Delay time, AECLKIN

low to AECLKOUT2 low"

DM642 Peripheral Information and Electrical Specifications, EMIF Electrical Data/Timing, Asynchronous

Memory Timing section:

Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:

Updated Parameter No. 7, t_{h(EKO1H-ARDY)}MIN from "2.0" to "2.5"

DM642 Peripheral Information and Electrical Specifications, EMIF Electrical Data/Timing, Asynchronous

Memory Timing section:

Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for

EMIFA Module table:

Updated Parameter No. 1, t_{osu(SELV-AREL)}MIN from "RS*E - 1.5" to "RS*E - 1.8"

Updated Parameter No. 8, t_{osu(SELV-AWEL)}MIN from "WS*E - 1.7" to "WS*E - 2.0"

DM642 Peripheral Information and Electrical Specifications, EMIF Electrical Data/Timing, Programmable

Synchronous Interface Timing section:

Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module table:

Updated Parameter No. 7, t_h(ELOxH-EDV)MIN from "1.5" to "1.8" for -500 device speed

168

Revision History

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

(continued)

SEE

ADDS/CHANGES/DELETES

DM642 Peripheral Information and Electrical Specifications, EMIF Electrical Data/Timing, Programmable

Synchronous Interface Timing section:

Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous

Interface Cycles for EMIFA Module table:

Updated all delay times MIN for 500, 600 and 720 device speeds from "1.3"" to "1.1"

DM642 Peripheral Information and Electrical Specifications, EMIF Electrical Data/Timing, Synchronous

DRAM Timing section:

Timing Requirements for Synchronous DRAM Cycles for EMIFA Module table:

Updated Parameter No. 7, t_h(EKO1H-EDV)MIN from "2.5" to "2.8"for 500 device speed

Updated Parameter No. 7 t_h(EKO1H-EDV)MIN from "1.8" to "2.1" for -600 and -720 device speeds

DM642 Peripheral Information and Electrical Specifications, McASP0 Electrical Data/Timing, Multichannel

Audio Serial Port (McASP) Timing section:

Timing Requirements for McASP table:

Added footnote

DM642 Peripheral Information and Electrical Specifications, McASP0 Electrical Data/Timing, Multichannel

Audio Serial Port (McASP) Timing section:

Switching Characteristics Over Recommended Operating Conditions for McASP table:

Added footnote

DM642 Peripheral Information and Electrical Specifications, McASP0 Electrical Data/Timing, Multichannel

Audio Serial Port (McASP) Timing section:

Updated Input Timings drawing

Updated Output Timings drawing

DM642 Peripheral Information and Electrical Specifications, Host-Port Interface (HPI), Host-Port Interface

(HPI) Electrical Data/Timing section:

Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles

table:

Updated Parameter No. 8, t_d(HDV-HRDYL)- MIN from "3" to "-3"

DM642 Peripheral Information and Electrical Specifications, Multichannel Buffered Serial Port (McBSP),

McBSP Electrical/Timing, Multichannel Buffered Serial Port (McBSP) Timing section:

Switching Characteristics Over Recommended Operating Conditions for McBSP table:

Updated Parameter No. 12, t_{dis(CKXH-DXHZ)}MIN from "2.0" to "-2.1"

Updated Parameter No. 13 t_d(CKXH-DXV)MIN from "2.0 + D1" to "-2.1 + D1"

DM642 Peripheral Information and Electrical Specifications, Ethernet Media Access Controller, EMAC

Electrical Data/Timing section :

Timing Requirements for EMAC MII Receive 10/100 Mbit/s table:

Deleted paragraph

DM642 Peripheral Information and Electrical Specifications, Ethernet Media Access Controller, EMAC

Electrical Data/Timing section:

Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s

table:

Deleted paragraph

Revision History

169

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

6 Mechanical Data

The following table(s) show the thermal resistance characteristics for the PBGA – GDK, GNZ, ZDK, and

ZNZ mechanical packages.

6.1 Thermal Data

Table 6-1. Thermal Resistance Characteristics (S-PBGA Package) [GDK]

NO.

1

°C/W

AIR FLOW (m/s)⁽¹⁾

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

3.3

7.92

18.2

15.3

13.7

12.2

0.37

0.47

0.57

0.7

N/A

0.00

0.5

2

3

4

RΘ_JA

Psi_JT

Psi_JB

Junction-to-free air

Junction-to-package top

Junction-to-board

5

1.0

6

2.00

0.00

0.5

7

8

9

1.0

10

11

12

13

14

2.00

0.00

0.5

11.4

11

10.7

10.2

1.0

2.00

(1) m/s = meters per second

Table 6-2. Thermal Resistance Characteristics (S-PBGA Package) [GNZ]

NO.

1

°C/W

AIR FLOW (m/s)⁽¹⁾

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

3.3

7.46

17.4

14.0

12.3

10.8

0.37

0.47

0.57

0.7

N/A

0.00

0.5

2

3

4

RΘ_JA

Psi_JT

Psi_JB

Junction-to-free air

Junction-to-package top

Junction-to-board

5

1.0

6

2.00

0.00

0.5

7

8

9

1.0

10

11

12

13

14

2.00

0.00

0.5

11.4

11

10.7

10.2

1.0

2.00

(1) m/s = meters per second

170

Mechanical Data

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

www.ti.com

SPRS200J–JULY 2002–REVISED AUGUST 2005

Table 6-3. Thermal Resistance Characteristics (S-PBGA Package) [ZDK]

NO.

°C/W

3.3

AIR FLOW (m/s)⁽¹⁾

1

2

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

N/A

0.00

0.5

7.92

18.2

15.3

13.7

12.2

0.37

0.47

0.57

0.7

3

4

RΘ_JA

Psi_JT

Psi_JB

Junction-to-free air

Junction-to-package top

Junction-to-board

5

1.0

6

2.00

0.00

0.5

7

8

9

1.0

10

11

12

13

14

2.00

0.00

0.5

11.4

11

10.7

10.2

1.0

2.00

(1) m/s = meters per second

Table 6-4. Thermal Resistance Characteristics (S-PBGA Package) [ZNZ]

NO.

1

°C/W

AIR FLOW (m/s)⁽¹⁾

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

3.3

7.46

17.4

14.0

12.3

10.8

0.37

0.47

0.57

0.7

N/A

0.00

0.5

2

3

4

RΘ_JA

Psi_JT

Psi_JB

Junction-to-free air

Junction-to-package top

Junction-to-board

5

1.0

6

2.00

0.00

0.5

7

8

9

1.0

10

11

12

13

14

2.00

0.00

0.5

11.4

11

10.7

10.2

1.0

2.00

(1) m/s = meters per second

6.2 Packaging Information

The following packaging information and addendum reflect the most current released data available for the

designated device(s). This data is subject to change without notice and without revision of this document.

Mechanical Data

171

PACKAGE OPTION ADDENDUM

www.ti.com

5-Dec-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Type

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Drawing

GDK

GNZ

ZDK

ZNZ

GDK

GNZ

ZDK

ZNZ

GDK

GNZ

ZDK

ZNZ

GDK

GNZ

TMS320DM642AGDK5

TMS320DM642AGDK6

TMS320DM642AGDK7

TMS320DM642AGDKA5

TMS320DM642AGNZ5

TMS320DM642AGNZ6

TMS320DM642AGNZ7

TMS320DM642AGNZA5

TMS320DM642AGNZA6

TMS320DM642AZDK5

TMS320DM642AZDK6

TMS320DM642AZDK7

TMS320DM642AZDKA5

TMS320DM642AZNZ5

TMS320DM642AZNZ6

TMS320DM642AZNZ7

TMS320DM642GDK500

TMS320DM642GDK600

TMS320DM642GDK720

TMS320DM642GDKA500

TMS320DM642GNZ500

TMS320DM642GNZ600

TMS320DM642GNZ720

TMS320DM642GNZA500

TMS320DM642ZDK500

TMS320DM642ZDK600

TMS320DM642ZNZ500

TMS320DM642ZNZ600

TMS320M642AGDK5

TMS320M642AGDK6

TMS320M642AGDK7

TMS320M642AGNZ5

TMS320M642AGNZ6

TMS320M642AGNZ7

TMS320M642AZDK5

TMS320M642AZDK6

TMS320M642AZNZ5

TMS320M642AZNZ6

TMS320M642AZNZ7

TMS320V642AGDK5

TMS320V642AGDK6

TMS320V642AGNZ6

ACTIVE

FCBGA

548

60

40

60

40

TBD

SNPB

Level-4-220C-72HR

Level-4-260C-72HR

Call TI

SNPB

SNAGCU

Call TI

SNPB

Level-4-220C-72HR

Call TI

40

SNPB

Call TI

SNAGCU

Call TI

Level-4-260C-72HR

Call TI

60

40

60

40

60

40

SNPB

Level-4-220C-72HR

Level-4-260C-72HR

Level-4-220C-72HR

SNPB

SNAGCU

SNPB

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

5-Dec-2005

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TMS320V642AZDK5

TMS320V642AZDK6

TMS320V642AZDK7

TMS320V642AZNZ5

TMS320V642AZNZ6

TMS320V642AZNZ7

ACTIVE

FCBGA

ZDK

548

60

40

TBD

SNAGCU

Level-4-260C-72HR

ZDK

ZNZ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MPBG301 – JULY 2002

GDK (S–PBGA–N548)

PLASTIC BALL GRID ARRAY

23,10

22,90

SQ

20,00 TYP

21,10

20,90

0,80

0,40

AF

AD

AB

Y

AE

AC

AA

W

U

V

0,80

T

R

P

N

M

K

L

0,40

A1 Corner

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

2

4

6

8

10 12 14 16 18 20 22 24 26

Bottom View

2,80 MAX

0,50 NOM

Seating Plane

0,12

0,55

0,45

0,10

0,45

0,35

4203481-3/B 07/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Flip chip application only.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ

MPBG314A – OCTOBER 2002 – REVISED DECEMBER 2002

GNZ (S–PBGA–N548)

PLASTIC BALL GRID ARRAY

27,20

26,80

25,00 TYP

1,00

SQ

25,20

24,80

0,50

AF

AE

AD

AC

AB

AA

Y

W

V

1,00

U

T

R

P

N

M

L

0,50

K

J

H

A1 Corner

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

10 12 14 16 18 20 22 24 26

2

4

6

8

Bottom View

2,80 MAX

0,50 NOM

Seating Plane

0,15

0,70

0,50

0,10

0,60

0,40

4202595-5\E 12/02

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Flip chip application only.

D. Substrate color may vary.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Use of such information may require a license from a third party under the patents or other intellectual property

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

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amplifier.ti.com

www.ti.com/audio

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Digital Control

Military

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www.ti.com/digitalcontrol

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Logic

interface.ti.com

logic.ti.com

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Microcontrollers

power.ti.com

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Security

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microcontroller.ti.com

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Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TMS320M642AZDK5
厂家：	TEXAS INSTRUMENTS
描述：	Video/Imaging Fixed-Point Digital Signal Processor 视频/影像定点数字信号处理器数字信号处理器
文件：	总178页 (文件大小：1669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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