TMS320UVC5402GGU_技术文档

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

D

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

D

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface (HPI-8)

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

D

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

– Two 16-Bit Timers

– Six-Channel Direct Memory Access

(DMA) Controller

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

D

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

D

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 1M × 16-Bit

Maximum Addressable External Program

Space

D

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

†

IEEE Std 1149.1 (JTAG) Boundary Scan

D

4K x 16-Bit On-Chip ROM

Logic

16K x 16-Bit Dual-Access On-Chip RAM

D

33-ns Single-Cycle Fixed-Point Instruction

Execution Time (30 MIPS)

Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D

1.2-V Core Power Supply

Block-Memory-Move Instructions for

Efficient Program and Data Management

D

1.2-V to 2.75-V I/O Power Supply Enables

Operation With a Single 1.2-V Supply or

With Dual Supplies

Instructions With a 32-Bit Long Word

Operand

D

Available in a 144-Pin Plastic Thin Quad

Flatpack (TQFP) (PGE Suffix) and a 144-Pin

Ball Grid Array (BGA) (GGU Suffix)

Instructions With Two- or Three-Operand

Reads

description

TheTMS320UVC5402fixed-point, digitalsignalprocessor(DSP)(hereafterreferredtoasthe’UVC5402unless

otherwise specified) is the industry’s first 1.2-V DSP. This processor offers ultra low power consumption and

the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to

operate with a single 1.2-V power supply or with dual power supplies for mixed voltage systems. This feature

eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

description (continued)

The TMS320UVC5402 is based on an advanced modified Harvard architecture that has one program memory

bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree

of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The

basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

For detailed information on the architecture of the ’C5000 family of DSPs, see the TMS320C5000 DSP Family

Functional Overview (literature number SPRU307).

†‡

PGE PACKAGE

(TOP VIEW)

1

108

107

106

105

104

103

102

101

100

99

NC

A18

A17

2

3

V

SS

DD

SS

4

DV

A16

D5

5

A10

HD7

A11

A12

A13

A14

A15

NC

6

D4

D3

D2

D1

D0

RS

X2/CLKIN

X1

HD3

CLKOUT

7

8

9

10

11

12

13

14

98

97

HAS

96

V

95

SS

NC 15

CV

16

HCS 17

HR/W 18

READY 19

PS 20

94

93

V

DD

SS

HPIENA

92

91

CV

NC

DD

90

89

TMS

DS 21

88

TCK

IS 22

R/W 23

87

TRST

TDI

86

MSTRB 24

IOSTRB 25

MSC 26

XF 27

HOLDA 28

IAQ 29

85

TDO

84

EMU1/OFF

EMU0

TOUT0

HD2

83

82

81

80

NC

HOLD 30

BIO 31

MP/MC 32

79

CLKMD3

CLKMD2

CLKMD1

78

77

DV

DD

SS

NC 35

NC

33

V

DV

NC

76

SS

DD

V

34

75

74

36

73

†

‡

NC = No internal connection

DV is the power supply for the I/O pins while CV

is the power supply for the core CPU. V

DD SS

is the ground for both the I/O

DD

pins and the core CPU.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

GGU PACKAGE

(BOTTOM VIEW)

13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

The pin assignments table to follow lists each signal name and BGA ball number for the TMS320UVC5402GGU

(144-pin BGA) package.

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

†

Pin Assignments for the TMS320UVC5402GGU (144-Pin BGA) Package

SIGNAL

NAME

SIGNAL

NAME

SIGNAL

NAME

SIGNAL

NAME

BGA BALL #

NC

A1

B1

C2

C1

D4

D3

D2

D1

E4

E3

E2

E1

F4

F3

F2

F1

G2

G1

G3

G4

H1

H2

H3

H4

J1

NC

N13

M13

L12

L13

K10

K11

K12

K13

J10

J11

NC

N1

N2

M3

N3

K4

A19

NC

A13

A12

B11

A11

D10

C10

B10

A10

D9

C9

B9

V

DV

HCNTL0

V

SS

DV

DD

SS

DV

V

SS

V

SS

DD

A10

DD

D6

CLKMD1

CLKMD2

CLKMD3

NC

BCLKR0

BCLKR1

BFSR0

BFSR1

BDR0

HD7

A11

A12

A13

A14

A15

NC

L4

D7

D8

M4

N4

K5

D9

HD2

D10

D11

D12

HD4

D13

D14

D15

HD5

TOUT0

EMU0

EMU1/OFF

TDO

HCNTL1

BDR1

L5

J12

J13

H10

H11

H12

H13

G12

G13

G11

G10

F13

F12

F11

F10

E13

E12

E11

E10

D13

D12

D11

C13

C12

C11

B13

B12

M5

N5

K6

BCLKX0

BCLKX1

A9

HAS

D8

C8

B8

V

TDI

V

L6

SS

NC

CV

SS

HINT/TOUT1

CV

TRST

TCK

M6

N6

M7

N7

L7

A8

DD

HCS

HR/W

READY

PS

TMS

BFSX0

BFSX1

HRDY

CV

B7

DD

NC

A7

CV

DD

HPIENA

HDS1

C7

D7

A6

DV

K7

V

DD

SS

HDS2

DV

DS

V

SS

V

SS

N8

M8

L8

IS

CLKOUT

HD3

X1

HD0

BDX0

BDX1

IACK

HBIL

NMI

B6

DD

A0

R/W

C6

D6

A5

MSTRB

IOSTRB

MSC

XF

K8

A1

A2

A3

HD6

A4

A5

A6

A7

A8

A9

X2/CLKIN

RS

N9

M9

L9

J2

B5

J3

D0

C5

D5

A4

HOLDA

IAQ

J4

D1

INT0

INT1

INT2

INT3

K9

K1

K2

K3

L1

D2

N10

M10

L10

N11

M11

L11

N12

M12

HOLD

BIO

D3

B4

D4

C4

A3

MP/MC

D5

CV

DD

DV

L2

A16

HD1

B3

DD

V

SS

L3

V

SS

V

SS

CV

C3

A2

DD

NC

M1

M2

A17

A18

NC

is the power supply for the core CPU. V

NC

B2

†

DV

is the power supply for the I/O pins while CV

DD

is the ground for both the I/O pins and the core

SS

DD

CPU.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

†

TYPE

DESCRIPTION

DATA SIGNALS

A19 (MSB)

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

O/Z

Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper

four address pins (A16 to A19) are only used to address external program space. These pins are placed in the

high-impedance state when the hold mode is enabled, or when EMU1/OFF is low.

A8

A7

A6

A5

A4

A3

A2

A1

A0

(LSB)

D15 (MSB)

D14

D13

D12

D11

D10

D9

D8

D7

D6

I/O/Z

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer

data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the

high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the

high-impedance state when EMU1/OFF is low.

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus

holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven

by the ’UVC5402, the bus holders keep the pins at the previous logic level. The data bus holders on the

’UVC5402are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register

(BSCR).

D5

D4

D3

D2

D1

D0

(LSB)

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the

interruptvectorlocationdesignatedbyA15–A0. IACKalsogoesintothehigh-impedancestatewhenEMU1/OFF

is low.

IACK

O/Z

I

INT0

INT1

INT2

INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and

the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).

Nonmaskableinterrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

NMI

I

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the

CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program

memory. RS affects various registers and status bits.

RS

†

I = input, O = output, Z = high impedance, S = supply

5

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

TYPE

DESCRIPTION

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the

internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high

during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin

isonlysampledatreset, andtheMP/MCbitoftheprocessormodestatus(PMST)registercanoverridethemode

that is selected at reset.

MP/MC

I

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the

conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the

pipeline; all other instructions sample BIO during the read phase of the pipeline.

BIO

XF

I

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low

by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor

configurations or used as a general-purpose output pin. XF goes into the high-impedance state when

EMU1/OFF is low, and is set high at reset.

O/Z

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing

a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are

placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when

EMU1/OFF is low.

DS

PS

IS

O/Z

I

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to

data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when EMU1/OFF is low.

MSTRB

READY

R/W

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the

device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

processor performs ready detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally

in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in

the high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF is low.

O/Z

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O

device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when EMU1/OFF is low.

IOSTRB

HOLD

O/Z

I

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the

’C54x, these lines go into the high-impedance state.

Hold acknowledge. HOLDA indicates that the ’UVC5402 is in a hold state and that the address, data, and control

lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.

HOLDA also goes into the high-impedance state when EMU1/OFF is low.

HOLDA

O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait

states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive

high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external

wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when

EMU1/OFF is low.

MSC

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus. IAQ goes into the high-impedance state when EMU1/OFF is low.

CLOCK/TIMER SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

isboundedbytherisingedgesofthissignal. CLKOUTalsogoesintothehigh-impedancestatewhenEMU1/OFF

is low.

CLKOUT

O/Z

†

I = input, O = output, Z = high impedance, S = supply

6

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

TYPE

DESCRIPTION

CLOCK/TIMER SIGNALS (CONTINUED)

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The

logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select

signals have no effect until the device is reset again.

CLKMD1

CLKMD2

CLKMD3

I

Clock input. An external clock source should be provided at this input. The frequency of this clock source can

be internally divided to produce the CPU clock.

X2/CLKIN

X1

I

O

This pin is reserved and should be left unconnected.

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT

cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.

TOUT0

O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one

CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.

TOUT1

O/Z

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0

BCLKR1

I/O/Z

I

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

Serial data receive input

BFSR0

BFSR1

I/O/Z

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when

EMU1/OFF goes low.

BCLKX0

BCLKX1

I/O/Z

O/Z

BDX0

BDX1

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

asserted, or when EMU1/OFF is low.

Framesynchronizationpulsefortransmitinput/output.TheBFSXpulseinitiatesthetransmitdataprocess.BFSX

can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the

high-impedance state when EMU1/OFF is low.

BFSX0

BFSX1

I/O/Z

MISCELLANEOUS SIGNAL

No connection

NC

HOST-PORT INTERFACE SIGNALS

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the

HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the

high-impedance state when not outputting data or when EMU1/OFF is low. The HPI data bus includes bus

holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not

beingdrivenbythe’UVC5402, thebusholderskeepthepinsatthepreviouslogiclevel. TheHPIdatabusholders

are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

HD0–HD7

I/O/Z

HCNTL0

HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have

internal pullup resistors that are only enabled when HPIENA = 0.

I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup

resistor that is only enabled when HPIENA = 0.

HBIL

HCS

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input

has an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1

HDS2

Datastrobe. HDS1andHDS2aredrivenbythehostreadandwritestrobestocontroltransfers. Thestrobeinputs

have internal pullup resistors that are only enabled when HPIENA = 0.

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA

register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.

HAS

†

I = input, O = output, Z = high impedance, S = supply

7

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

TYPE

DESCRIPTION

HOST-PORT INTERFACE SIGNALS (CONTINUED)

Read/write. HR/W controls the direction of an HPI transfer. HR/W has an internal pullup resistor that is only

enabled when HPIENA = 0.

HR/W

I

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the

high-impedance state when EMU1/OFF is low.

HRDY

HINT

O/Z

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can also

be configured as the timer 1 output (TOUT1) when the HPI is disabled. The signal goes into the high-impedance

state when EMU1/OFF is low.

O/Z

I

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor

is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low

during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the

’UVC5402 is reset.

HPIENA

SUPPLY PNS

CV

DV

S

+V . Dedicated power supply for the core CPU

DD

+V . Dedicated power supply for the I/O pins

DD

V

SS

Ground

TEST PINS

IEEEstandard1149.1testclock. TCKisnormallyafree-runningclocksignalwitha50%dutycycle. Thechanges

on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction

register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur

on the falling edge of TCK.

TCK

I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDI

I

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when EMU1/OFF is low.

TDO

TMS

TRST

O/Z

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,

and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by

way of the IEEE standard 1149.1 scan system.

EMU0

I/O/Z

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the

emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST

is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers

into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for

multiprocessing applications). Therefore, for the OFF feature, the following apply:

TRST = low

EMU1/OFF

I/O/Z

EMU0 = high

EMU1/OFF = low

†

I = input, O = output, Z = high impedance, S = supply

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory

The ’UVC5402 device provides both on-chip ROM and RAM memories to aid in system performance and

integration.

on-chip ROM with bootloader

The ’UVC5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM

of the ’UVC5402 programmed with contents unique to any particular application.

A bootloader is available in the standard ’UVC5402 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin

is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location

contains a branch instruction to the start of the bootloader program. The standard ’UVC5402 bootloader

provides different ways to download the code to accomodate various system requirements:

D

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space 8-bit or 16-bit mode

Serial boot from serial ports 8-bit or 16-bit mode

Host-port interface boot

The standard on-chip ROM layout is shown in Table 1.

†

Table 1. Standard On-Chip ROM Layout

ADDRESS RANGE

DESCRIPTION

F000h – F7FFh

Reserved

F800h – FBFFh

FC00h – FCFFh

FD00h – FDFFh

FE00h – FEFFh

FF00h – FF7Fh

FF80h – FFFFh

Bootloader

µ-law expansion table

A-law expansion table

Sine look-up table

Reserved

Interrupt vector table

†

In the ’UVC5402 ROM, 128 words are reserved for factory device-testing purposes. Application

code to be implemented in on-chip ROM must reserve these 128 words at addresses

FF00h–FF7Fh in program space.

on-chip RAM

The ’UVC5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed

of two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and

a write in one cycle. The DARAM is located in the address range 0080h–3FFFh in data space, and can be

mapped into program/data space by setting the OVLY bit to one.

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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memory map

Page 0 Program

Data

Hex

0000

Hex

0000

Hex

0000

Memory

Mapped

Registers

Reserved

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

005F

0060

Scratch-Pad

RAM

007F

0080

007F

0080

007F

0080

On-Chip

DARAM

On-Chip

DARAM

On-Chip

DARAM

(16K x 16-bit)

(OVLY = 1)

External

(OVLY = 0)

External

(OVLY = 0)

3FFF

4000

3FFF

4000

3FFF

4000

External

EFFF

F000

EFFF

F000

External

ROM (DROM=1)

or External

On-Chip ROM

(4K x 16-bit)

(DROM=0)

FEFF

FF00

FEFF

FF00

Reserved

(DROM=1)

or External

(DROM=0)

FF7F

FF80

FF7F

FF80

Interrupts

(External)

Interrupts

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate

interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate

128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new

128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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extended program memory

The ’UVC5402 uses a paged extended memory scheme in program space to allow access of up to 1024K

program memory locations.

D

Twenty address lines, instead of sixteen

D

An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

Six extra instructions for addressing extended program space. These six instructions affect the XPC.

D

–

FB[D] pmad (20 bits) – Far branch

FBACC[D] Accu[19:0] – Far branch to the location specified by the value in accumulator A or

accumulator B

–

FCALL[D] pmad (20 bits) – Far call

FCALA[D] Accu[19:0] – Far call to the location specified by the value in accumulator A or accumulator B

FRET[D] – Far return

FRETE[D] – Far return with interrupts enabled

D

In addition to these new instructions, two ’54x instructions are extended to use 20 bits in the ’UVC5402:

–

READA data_memory (using 20-bit accumulator address)

WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access

only memory within the current page.

Program memory in the ’UVC5402 is organized into 16 pages that are each 64K in length, as shown in Figure 2.

0 0000

1 0000

2 0000

F 0000

Page 1

Lower

16K}

Page 2

Lower

16K}

. . .

Page 15

Lower

16K}

1 3FFF

1 4000

2 3FFF

2 4000

F 3FFF

F 4000

External

Page 0

Page 1

Upper

48K

Page 2

Upper

48K

Page 15

Upper

48K

64K

Words{

External

2 FFFF

F FFFF

0 FFFF

1 FFFF

. . .

†

‡

See Figure 1

The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM

is mapped to the lower 16K words of all program space pages.

Figure 2. Extended Program Memory

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on-chip peripherals

The ’UVC5402 device has the following peripherals:

D

Software-programmable wait-state generator with programmable bank-switching wait states

An enhanced 8-bit host-port interface (HPI-8)

Two multichannel buffered serial ports (McBSPs)

Two hardware timers

A clock generator with a phase-locked loop (PLL)

A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the ’UVC5402 can extend external bus cycles by up to 14 machine cycles.

Devices that require more than 14 wait states can be interfaced using the hardware READY line. When all

external accesses are configured for zero wait states, the internal clocks to the wait-state generator are

automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the

’UVC5402.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 15 LSBs of

the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five

separate address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)

definesamultiplicationfactorof1or2forthenumberofwaitstates. Atreset, thewait-stategeneratorisinitialized

to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3

and described in Table 2.

15

14

12 11

9

8

6

5

3

2

0

XPA

I/O

R/W-111

Data

R/W-111

Data

Program

R/W-111

Program

R/W-111

R/W-0

R/W-111

LEGEND: R=Read, W=Write, 0=Value after reset

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

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software-programmable wait-state generator (continued)

Table 2. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

VALUE

FUNCTION

NO.

NAME

Extended program address control bit. XPA is used in conjunction with the program space fields

(bits 0 through 5) to select the address range for the program space wait states.

15

XPA

0

1

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses

within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

the base number of wait states.

14–12

11–9

8–6

I/O

Upper data space. The field value (0–7) corresponds to the base number of wait states for external

data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a

multiplication factor of 1 or 2 for the base number of wait states.

Data

1

Lower data space. The field value (0–7) corresponds to the base number of wait states for external

data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a

multiplication factor of 1 or 2 for the base number of wait states.

Upper program space. The field value (0–7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

-

XPA = 0: x8000 – xFFFFh

5–3

2–0

Program

1

XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait

states.

Program space. The field value (0–7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

-

XPA = 0: x0000–x7FFFh

XPA = 1: 00000–FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait

states.

The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the

base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described

in Table 3.

15

1

0

SWSM

Reserved

R/W-0

LEGEND: R = Read, W = Write

Figure 4. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]

Table 3. Software Wait-State Control Register (SWCR) Bit Fields

BIT

NAME

RESET

VALUE

FUNCTION

NO.

15–1

Reserved

0

These bits are reserved and are unaffected by writes.

Softwarewait-statemultiplier. UsedtomultiplythenumberofwaitstatesdefinedintheSWWSRbyafactor

of 1 or 2.

0

SWSM

0

-

SWSM = 0: wait-state base values are unchanged (multiplied by 1).

SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.

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programmable bank-switching wait states

The programmable bank-switching logic of the ’UVC5402 is functionally equivalent to that of the ’548/’549

devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within

program or data memory space. A bank-switching wait state can also be automatically inserted when accesses

cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 5

shows the BSCR and its bits are described in Table 4.

15

12

11

10

3

2

1

0

BNKCMP

PS-DS

Reserved

R-0

HBH

BH

EXIO

R/W-1111

R/W-1

R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register (BSCR) Bit Fields

BIT

NAME

RESET

FUNCTION

VALUE

NO.

Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of an

15–12 BNKCMP

1111

address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a bank size

of 4K words. Bank sizes of 4K words to 64K words are allowed.

Program read – data read access. Inserts an extra cycle between consecutive accesses of program read and

data read or data read and program read.

11

10–3

2

PS - DS

Reserved

HBH

1

0

PS-DS = 0

PS-DS = 1

No extra cycles are inserted by this feature.

One extra cycle is inserted between consecutive data and program reads.

These bits are reserved and are unaffected by writes.

HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.

HBH = 0

HBH = 1

The bus holder is disabled.

The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.

BH = 0

BH = 1

The bus holder is disabled.

The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the previous

logic level.

1

0

BH

0

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

EXIO = 1

The external bus interface functions as usual.

Theaddress bus, data bus, and control signals become inactive after completing thecurrent

bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1

cannot be modified when the interface is disabled.

EXIO

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TMS320UVC5402

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parallel I/O ports

The ’UVC5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the

PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’UVC5402 can

interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding

circuits.

enhanced 8-bit host-port interface (HPI-8)

The ’UVC5402 host-port interface, also referred to as the HPI-8, is an enhanced version of the standard 8-bit

HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI-8 is an 8-bit parallel port for interprocessor

communication. The features of the HPI-8 include:

Standard features:

D

Sequential transfers (with autoincrement) or random-access transfers

Host interrupt and ’54x interrupt capability

Multiple data strobes and control pins for interface flexibility

Enhanced features of the ’UVC5402 HPI-8:

D

Access to entire on-chip RAM through DMA bus

Capability to continue transferring during emulation stop

The HPI-8 functions as a slave and enables the host processor to access the on-chip memory of the ’UVC5402.

A major enhancement to the ’UVC5402 HPI over previous versions is that it allows host access to the entire

on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and

host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the

same location, the host has priority, and the DSP waits for one HPI-8 cycle. Note that since host accesses are

alwayssynchronizedtothe’UVC5402clock, anactiveinputclock(CLKIN)isrequiredforHPI-8accessesduring

IDLE states, and host accesses are not allowed while the ’UVC5402 reset pin is asserted.

The HPI-8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers

are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with

the HPI-8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an

HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register

is accessible by both the host and the ’UVC5402.

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multichannel buffered serial ports

The ’UVC5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that

allow direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are

based on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP

provides:

D

Full-duplex communication

Double-buffered data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

D

Direct interface to:

–

T1/E1 framers

MVIP switching compatible and ST-BUS compliant devices

IOM-2 compliant devices

Serial peripheral interface devices

D

Multichannel transmit and receive of up to 128 channels

A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

µ-law and A-law companding

Programmable polarity for both frame synchronization and data clocks

Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external

interface of each McBSP consists of the following pins:

D

BCLKX

BDX

BFSX

BCLKR

BDR

Transmit reference clock

Transmit data

Transmit frame synchronization

Receive reference clock

Receive data

BFSR

Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family

ofDSPs. Onthetransmitter, transmitframesynchronizationandclockingareindicatedbytheBFSXandBCLKX

pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register

(DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure

allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

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multichannel buffered serial ports (continued)

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,

respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on

the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).

If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR

is available. This structure allows storage of the two previous words while the reception of the current word is

in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP

interrupts, event signals, and status flags. The DMA is capable of handling data movement between the

McBSPs and memory with no intervention from the CPU.

In addition to the standard serial port functions, the McBSP provides programmable clock and frame

synchronization generation. Among the programmable functions are:

D

Frame synchronization pulse width

Frame period

Frame synchronization delay

Clock reference (internal vs. external)

Clock division

Clock and frame synchronization polarity

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.

When companding is used, transmit data is encoded according to specified companding law and received data

is decoded to 2s complement format.

The McBSP allows multiple channels to be independently selected for the transmitter and receiver. When

multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using

TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,

multichannel selection allows independent enabling of particular channels for transmission and reception. Up

to 32 channels in a stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface

protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes

supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is

configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a

slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU

clock frequency divided by 2.

hardware timer

The ’UVC5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer

is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is

generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides the internal clock for the ’UVC5402 and requires an external reference clock

source at the X2/CLKIN pin. The clock generator includes three clock options.

D

The reference clock can be used directly to clock the ’UVC5402.

The reference clock frequency can be divided by a factor of two.

The reference clock frequency can be divided by a factor of four.

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clock generator (continued)

Unlikeprevious ’54x products, the ’UVC5402 does not include an on-chip oscillator or phased-locked loop (PLL)

circuit.

The clock option is selected using the 16-bit memory-mapped (address 0058h) clock mode (CLKMD) register.

Upon reset, the CLKMD register is initialized to one of the three clock options dependent on the state of the clock

mode select pins (CLKMD1 – CLKMD3). The clock mode select pins are latched while the reset pin is low and

the clock generator is configured in the selected mode. The clock mode select pin combinations and

corresponding clock modes are listed in Table 5.

Table 5. Clock Mode Settings at Reset

CLKMD

RESET VALUE

CLKMD1

CLKMD2

CLKMD3

CLOCK MODE

0

1

0F01h

1/1 (bypass)

1/2

0000h

1

0

1

0

1

0

1

0

1

0

F000h

—

1/4

Reserved

—

The state of the clock mode select pins should not be changed while the reset pin is high. Following reset, the

clock mode can be changed through software by writing to the CLKMD register. Only the three values listed in

the CLKMD RESET VALUE column of Table 5 can be written to the clock mode register and no other bit

combinations are allowed.

DMA controller

The ’UVC5402 direct memory access (DMA) controller transfers data between points in the memory map

without intervention by the CPU. The DMA controller allows movements of data to and from internal

program/data memory or internal peripherals (such as the McBSPs) to occur in the background of CPU

operation. The DMA has six independent programmable channels, allowing six different contexts for DMA

operation.

features

The DMA has the following features:

D

The DMA operates independently of the CPU.

The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

The DMA has higher priority than the CPU for internal accesses.

Each channel has independently programmable priorities.

Each channel’s source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be postincremented,

postdecremented, or be adjusted by a programmable value.

D

Each read or write transfer may be initialized by selected events.

Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the

CPU.

The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).

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DMA memory map

The DMA memory map is shown in Figure 6 to allow DMA transfers to be unaffected by the status of the MPMC,

DROM, and OVLY bits.

Hex

0000

Reserved

005F

0060

Scratch-Pad

RAM

007F

0080

On-Chip DARAM

(16K x 16-bit)

3FFF

4000

Undefined

FFFF

Figure 6. ’UVC5402 DMA Memory Map

DMA priority level

Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple

DMA channels that are assigned to the same priority level are handled in a round-robin manner.

DMA source/destination address modification

The DMA provides flexible address-indexing modes for easy implementation of data management schemes

such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and

can be postincremented, postdecremented, or postincremented with a specified index offset.

DMA in autoinitialization mode

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can

be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and

DMGCR). Autoinitialization allows:

D

Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfer; but with the global reload registers, it can reinitialize these values

for the next block transfer any time after the current block transfer begins.

D

Repetitive operation: The CPU does not preload the global reload register with new values for each block

transfer but only loads them on the first block transfer.

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DMA transfer counting

The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields

that represent the number of frames and the number of elements per frame to be transferred.

D

Framecount. This8-bitvaluedefinesthetotalnumberofframesintheblocktransfer. Themaximumnumber

of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read

transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with

the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default

value) means the block transfer contains a single frame.

Element count. This 16-bit value defines the number of elements per frame. This counter is decremented

after the read transfer of each element. The maximum number of elements per frame is 65536

(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded

with the DMA global count reload register (DMGCR).

DMA transfers in double-word mode

Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated

following each transfer. In this mode, each 32-bit word is considered to be one element.

DMA channel index registers

The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode

control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and

DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is

the last in the current frame. The normal adjustment value (element index) is contained in the element index

registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by

the selected DMA frame index register, either DMFRI0 or DMFRI1.

The element index and the frame index affect address adjustment as follows:

D

Element index: For all except the last transfer in the frame, the element index determines the amount to be

added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by

the SIND/DIND bits.

D

Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected

by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.

DMA interrupts

The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is

determined by the IMOD and DINM bits in the DMA mode control register (DMMCRn). The available modes

are shown in Table 6.

Table 6. DMA Interrupts

MODE

ABU (non-decrement)

Multi-Frame

DINM

IMOD

INTERRUPT

1

0

1

0

1

X

At full buffer only

At half buffer and full buffer

At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

At end of frame and end of block (DMCTRn = 0)

No interrupt generated

Multi-Frame

Either

No interrupt generated

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TMS320UVC5402

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DMA controller synchronization events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit

field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event

for a channel. The list of possible events and the DSYN values are shown in Table 7.

Table 7. DMA Synchronization Events

DSYN VALUE

0000b

DMA SYNCHRONIZATION EVENT

No synchronization used

0001b

McBSP0 receive event

McBSP0 transmit event

Reserved

0010b

0011–0100b

0101b

McBSP1 receive event

McBSP1 transmit event

Reserved

0110b

0111b–0110b

1101b

Timer0 interrupt

1110b

External interrupt 3

Timer1 interrupt

1111b

DMA channel interrupt selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 1, 2,

and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt line with the receive

and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an interrupt line with

timer 1 (IMR/IFR bit 7). When the ’UVC5402 is reset, the interrupts from these three DMA channels are

deselected. TheINTSELbitfieldintheDMAchannelpriorityandenablecontrol(DMPREC)registercanbeused

to select these interrupts, as shown in Table 8.

Table 8. DMA Channel Interrupt Selection

INTSEL Value

00b (reset)

01b

IMR/IFR[7]

TINT1

IMR/IFR[10]

BRINT1

IMR/IFR[11]

BXINT1

TINT1

DMAC2

DMAC3

10b

DMAC1

DMAC2

DMAC3

11b

Reserved

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory-mapped registers

The ’UVC5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses

0hto1Fh. Table 9 gives a list of the CPU memory-mapped registers (MMRs) available on ’UVC5402. The device

also has a set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show

additional peripheral MMRs associated with the ’UVC5402.

Table 9. CPU Memory-Mapped Registers

ADDRESS

NAME

IMR

DESCRIPTION

DEC

0

HEX

0

Interrupt mask register

Interrupt flag register

Reserved for testing

Status register 0

IFR

–

1

2–5

6

2–5

6

ST0

ST1

AL

7

Status register 1

8

Accumulator A low word (15–0)

AH

9

Accumulator A high word (31–16)

Accumulator A guard bits (39–32)

Accumulator B low word (15–0)

Accumulator B high word (31–16)

Accumulator B guard bits (39–32)

Temporary register

AG

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

BL

B

BH

C

BG

D

TREG

TRN

AR0

AR1

AR2

AR3

AR4

AR5

AR6

AR7

SP

E

F

Transition register

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Auxiliary register 0

Auxiliary register 1

Auxiliary register 2

Auxiliary register 3

Auxiliary register 4

Auxiliary register 5

Auxiliary register 6

Auxiliary register 7

Stack pointer register

BK

Circular buffer size register

Block-repeat counter

BRC

RSA

REA

PMST

XPC

–

Block-repeat start address

Block-repeat end address

Processor mode status (PMST) register

Extended program page register

Reserved

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FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory-mapped registers (continued)

Table 10. Peripheral Memory-Mapped Registers

NAME

DRR20

ADDRESS

20h

DESCRIPTION

TYPE

McBSP #0

Timer0

McBSP0 data receive register 2

McBSP0 data receive register 1

McBSP0 data transmit register 2

McBSP0 data transmit register 1

Timer0 register

DRR10

DXR20

DXR10

TIM

21h

22h

23h

24h

PRD

25h

Timer0 period counter

Timer0 control register

Reserved

Timer0

TCR

26h

Timer0

–

27h

SWWSR

BSCR

–

28h

Software wait-state register

Bank-switching control register

Reserved

External Bus

29h

2Ah

SWCR

HPIC

–

2Bh

Software wait-state control register

HPI control register

External Bus

HPI

2Ch

2Dh–2Fh

30h

Reserved

TIM1

PRD1

TCR1

–

Timer1 register

Timer1

31h

Timer1 period counter

Timer1 control register

Reserved

32h

33h–37h

38h

†

SPSA0

SPSD0

–

McBSP0 subbank address register

McBSP #0

†

39h

McBSP0 subbank data register

Reserved

3Ah–3Bh

3Ch

GPIOCR

GPIOSR

–

General-purpose I/O pins control register

General-purpose I/O pins status register

Reserved

GPIO

3Dh

3Eh–3Fh

40h

DRR21

DRR11

DXR21

DXR11

–

McBSP1 data receive register 2

McBSP1 data receive register 1

McBSP1 data transmit register 2

McBSP1 data transmit register 1

Reserved

McBSP #1

41h

42h

43h

44h–47h

48h

†

SPSA1

SPSD1

–

McBSP1 subbank address register

McBSP #1

†

49h

McBSP1 subbank data register

4Ah–53h

54h

Reserved

DMPREC

DMSA

DMSDI

DMSDN

CLKMD

–

DMA channel priority and enable control register

DMA

PLL

‡

55h

DMA subbank address register

DMA subbank data register with autoincrement

‡

56h

‡

57h

DMA subbank data register

Clock mode register

Reserved

58h

59h–5Fh

†

‡

See Table 11 for a detailed description of the McBSP control registers and their subaddresses.

See Table 12 for a detailed description of the DMA subbank addressed registers.

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

McBSP control registers and subaddresses

The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank

addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.

The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the

subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.

Table 11 shows the McBSP control registers and their corresponding subaddresses.

Table 11. McBSP Control Registers and Subaddresses

McBSP0

McBSP1

SUB-

ADDRESS

NAME

ADDRESS

NAME

ADDRESS

DESCRIPTION

Serial port control register 1

SPCR10

SPCR20

RCR10

39h

SPCR11

SPCR21

RCR11

49h

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

Serial port control register 2

Receive control register 1

RCR20

RCR21

Receive control register 2

XCR10

XCR11

Transmit control register 1

XCR20

XCR21

Transmit control register 2

SRGR10

SRGR20

MCR10

MCR20

RCERA0

RCERB0

XCERA0

XCERB0

PCR0

SRGR11

SRGR21

MCR11

MCR21

RCERA1

RCERB1

XCERA1

XCERB1

PCR1

Sample rate generator register 1

Sample rate generator register 2

Multichannel register 1

Multichannel register 2

Receive channel enable register partition A

Receive channel enable register partition B

Transmit channel enable register partition A

Transmit channel enable register partition B

Pin control register

DMA subbank addressed registers

The direct memory access (DMA) controller has several control registers associated with it. The main control

register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using

the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single

memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register

within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with

autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically

postincremented so that a subsequent access affects the next register within the subbank. This autoincrement

feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature

is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller

subbank addressed registers and their corresponding subaddresses.

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FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

DMA subbank addressed registers (continued)

Table 12. DMA Subbank Addressed Registers

DMA

SUB-

ADDRESS

NAME

ADDRESS

DESCRIPTION

DMSRC0

DMDST0

DMCTR0

DMSFC0

DMMCR0

DMSRC1

DMDST1

DMCTR1

DMSFC1

DMMCR1

DMSRC2

DMDST2

DMCTR2

DMSFC2

DMMCR2

DMSRC3

DMDST3

DMCTR3

DMSFC3

DMMCR3

DMSRC4

DMDST4

DMCTR4

DMSFC4

DMMCR4

DMSRC5

DMDST5

DMCTR5

DMSFC5

DMMCR5

DMSRCP

DMDSTP

DMIDX0

DMIDX1

DMFRI0

56h/57h

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

DMA channel 0 source address register

DMA channel 0 destination address register

DMA channel 0 element count register

DMA channel 0 sync select and frame count register

DMA channel 0 transfer mode control register

DMA channel 1 source address register

DMA channel 1 destination address register

DMA channel 1 element count register

DMA channel 1 sync select and frame count register

DMA channel 1 transfer mode control register

DMA channel 2 source address register

DMA channel 2 destination address register

DMA channel 2 element count register

DMA channel 2 sync select and frame count register

DMA channel 2 transfer mode control register

DMA channel 3 source address register

DMA channel 3 destination address register

DMA channel 3 element count register

DMA channel 3 sync select and frame count register

DMA channel 3 transfer mode control register

DMA channel 4 source address register

DMA channel 4 destination address register

DMA channel 4 element count register

DMA channel 4 sync select and frame count register

DMA channel 4 transfer mode control register

DMA channel 5 source address register

DMA channel 5 destination address register

DMA channel 5 element count register

DMA channel 5 sync select and frame count register

DMA channel 5 transfer mode control register

DMA source program page address (common channel)

DMA destination program page address (common channel)

DMA element index address register 0

DMA element index address register 1

DMA frame index register 0

DMFRI1

DMA frame index register 1

DMGSA

DMA global source address reload register

DMA global destination address reload register

DMA global count reload register

DMGDA

DMGCR

DMGFR

DMA global frame count reload register

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.

Table 13. Interrupt Locations and Priorities

LOCATION

DECIMAL

NAME

PRIORITY

FUNCTION

HEX

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

RS, SINTR

NMI, SINT16

SINT17

0

1

2

Reset (hardware and software reset)

Nonmaskable interrupt

Software interrupt #17

Software interrupt #18

Software interrupt #19

Software interrupt #20

Software interrupt #21

Software interrupt #22

Software interrupt #23

Software interrupt #24

Software interrupt #25

Software interrupt #26

Software interrupt #27

Software interrupt #28

Software interrupt #29

Software interrupt #30

External user interrupt #0

External user interrupt #1

External user interrupt #2

Timer0 interrupt

4

8

—

3

SINT18

12

16

20

24

28

32

36

40

44

48

52

56

60

64

68

72

76

80

84

88

SINT19

SINT20

SINT21

SINT22

SINT23

SINT24

SINT25

SINT26

SINT27

SINT28

SINT29

SINT30

INT0, SINT0

INT1, SINT1

INT2, SINT2

TINT0, SINT3

4

5

6

BRINT0, SINT4

BXINT0, SINT5

DMAC0, SINT7

7

McBSP #0 receive interrupt

McBSP #0 transmit interrupt

DMA channel 0 interrupt

8

9

Timer1 interrupt (default) or DMA channel 1

interrupt. The selection is made in the

DMPREC register.

TINT1(DMAC1), SINT7

92

5C

10

INT3, SINT8

96

60

64

11

12

External user interrupt #3

HPI interrupt

HPINT, SINT9

100

McBSP #1 receive interrupt (default) or DMA

channel 2 interrupt. The selection is made in

the DMPREC register.

BRINT1(DMAC2), SINT10

BXINT1(DMAC3), SINT11

104

108

68

13

14

McBSP #1 transmit interrupt (default) or DMA

channel 3 interrupt. The selection is made in

the DMPREC register.

6C

DMAC4,SINT12

DMAC5,SINT13

Reserved

112

116

70

74

15

16

—

DMA channel 4 interrupt

DMA channel 5 interrupt

Reserved

120–127

78–7F

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

interrupts (continued)

The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 7.

15–14

RES

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DMAC5

DMAC4

BXINT1 BRINT1 HPINT

or or

DMAC3 DMAC2

INT3

TINT1

or

DMAC1

DMAC0 BXINT0 BRINT0

TINT0

INT2

INT1

INT0

Figure 7. IFR and IMR Registers

Table 14. IFR and IMR Register Bit Fields

BIT

FUNCTION

NUMBER

NAME

15–14

13

–

Reserved for future expansion

DMAC5

DMAC4

DMA channel 5 interrupt flag/mask bit

DMA channel 4 interrupt flag/mask bit

12

This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA

channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.

11

10

BXINT1/DMAC3

BRINT1/DMAC2

This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA

channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.

9

8

HPINT

INT3

Host to ’54x interrupt flag/mask

External interrupt 3 flag/mask

This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1

interrupt flag/mask bit. The selection is made in the DMPREC register.

7

TINT1/DMAC1

6

5

4

3

2

1

0

DMAC0

BXINT0

BRINT0

TINT0

INT2

DMA channel 0 interrupt flag/mask bit

McBSP0 transmit interrupt flag/mask bit

McBSP0 receive interrupt flag/mask bit

Timer 0 interrupt flag/mask bit

External interrupt 2 flag/mask bit

External interrupt 1 flag/mask bit

External interrupt 0 flag/mask bit

INT1

INT0

27

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement

through applications development. The following types of documentation are available to support the design

and use of the ’C5000 family of DSPs:

D

TMS320C5000 DSP Family Functional Overview (literature number SPRU307)

Device-specific data sheets (such as this document)

Complete User Guides

Development-support tools

Hardware and software application reports

The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:

D

Volume 1: CPU and Peripherals (literature number SPRU131)

Volume 2: Mnemonic Instruction Set (literature number SPRU172)

Volume 3: Algebraic Instruction Set (literature number SPRU179)

Volume 4: Applications Guide (literature number SPRU173)

The reference set describes in detail the ’54x TMS320 products currently available and the hardware and

software applications, including algorithms, for fixed-point TMS320 devices.

For general background information on DSPs and Texas Instruments (TIt) devices, see the three-volume

publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012,

SPRA016, and SPRA017).

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 newsletter, Details on Signal Processing, is published

quarterly and distributed to update TMS320 customers on product information.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

TI is a trademark of Texas Instruments Incorporated.

28

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V

DD

‡

Supply voltage core range, CV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.0 V

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V

Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

I

O

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

1.14

NOM

MAX

2.75

1.32

UNIT

V

DV

CV

Device supply voltage, I/O

Device supply voltage, core

DD

1.2

0

V

SS

Supply voltage, GND

V

DV

= 1.14 V to 1.89 V

= 1.90 V to 2.75 V

0.65 x DV

DV

+ 0.3

High-level input

voltage

DD

1.3

DD

V

IH

IL

+ 0.3

DD

DV

= 1.14 V to 1.89 V

= 1.90 V to 2.75 V

–0.3

0.3 x DV

0.6

Low-level input

voltage

DD

V

DD

I

High-level output current

Low-level output current

–300

1.5

µA

mA

°C

OH

OL

T

Operating case temperature

0

70

C

29

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

†

TYP

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

= MAX

MIN

DV –0.3

DD

MAX

UNIT

V

I

V

OH

= MAX

0.3

V

OL

Bus holders enabled, DV

DD

= MAX,

Input current for

outputs in high

impedance

D[15:0], HD[7:0]

–175

175

V = V

to DV

I

SS

DD

I

IZ

µA

All other inputs

X2/CLKIN

DV

= MAX, V = V

to DV

DD

–5

5

DD

O

SS

–40

40

TRST

With internal pulldown

–5

300

Input current

HPIENA

(V = V

I SS

I

µA

to DV

)

DD

With internal pullups,

HPIENA = 0

}

TMS, TCK, TDI, HPI

–300

–5

5

All other input-only pins

w

CV

= 1.2 V, f

= 30 MHz,

DD

= 25°C

clock

I

Supply current, core CPU

Supply current, pins

10

mA

DDC

T

C

w

DV

= 1.2 V, f

= 25°C

= 30 MHz,

DD

DDP

T

C

IDLE2

IDLE3

DIV1 mode,

30 MHz input

500

2

µA

Supply current,

standby

I

DD

CLKIN stopped

C

Input capacitance

Output capacitance

3

pF

i

o

†

‡

§

All values are typical unless otherwise specified.

HPI input signals except for HPIENA.

Clock mode: DIV1

30

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TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

divide-by-two clock option

The frequency of the external reference clock provided at the X2/CLKIN pin can be divided by a factor of two

to generate the internal machine cycle. The selection of the clock mode is described in the clock generator

section.

The external frequency injected must conform to specifications listed in the timing requirements table.

†

switching characteristics over recommended operating conditions [H = 0.5t

and the recommended operating conditions table)

] (see Figure 8

c(CO)

PARAMETER

MIN

TYP

MAX

UNIT

ns

‡

t

Cycle time, CLKOUT

33

15

c(CO)

t

Delay time, X2/CLKIN high to CLKOUT high/low

Fall time, CLKOUT

25

ns

d(CIH-CO)

t

5

ns

f(CO)

t

Rise time, CLKOUT

ns

r(CO)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

H–4

H–2

ns

w(COL)

w(COH)

ns

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

It is recommended that the PLL clocking option be used for maximum frequency operation.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

timing requirements (see Figure 8)

MIN

MAX

UNIT

ns

†

t

Cycle time, X2/CLKIN

Fall time, X2/CLKIN

Rise time, X2/CLKIN

15

c(CI)

f(CI)

r(CI)

8

ns

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

t

r(CI)

t

f(CI)

t

c(CI)

X2/CLKIN

CLKOUT

t

w(COH)

t

f(CO)

t

c(CO)

t

r(CO)

t

d(CIH-CO)

t

w(COL)

Figure 8. External Divide-by-Two Clock Timing

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a memory read

†

(MSTRB = 0) (see Figure 9)

PARAMETER

MIN

0

MAX

UNIT

ns

‡

t

Delay time, CLKOUT low to address valid

8

d(CLKL-A)

§

Delay time, CLKOUT high (transition) to address valid

0

ns

d(CLKH-A)

t

Delay time, CLKOUT low to MSTRB low

0

ns

d(CLKL-MSL)

t

Delay time, CLKOUT low to MSTRB high

0

ns

d(CLKL-MSH)

‡

t

Hold time, address valid after CLKOUT low

0

ns

h(CLKL-A)R

§

t

Hold time, address valid after CLKOUT high

0

ns

h(CLKH-A)R

†

‡

§

Address, PS, and DS timings are all included in timings referenced as address.

In the case of a memory read preceded by a memory read

In the case of a memory read preceded by a memory write

†

timing requirements for a memory read (MSTRB = 0) [H = 0.5 t

] (see Figure 9)

c(CO)

MIN

MAX

2H–15

UNIT

ns

t

Access time, read data access from address valid

Access time, read data access from MSTRB low

Setup time, read data before CLKOUT low

Hold time, read data after CLKOUT low

a(A)M

ns

a(MSTRBL)

su(D)R

10

0

ns

h(D)R

Hold time, read data after address invalid

Hold time, read data after MSTRB high

0

ns

h(A-D)R

0

ns

h(D)MSTRBH

†

Address, PS, and DS timings are all included in timings referenced as address.

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

CLKOUT

t

d(CLKL-A)

t

h(CLKL-A)R

A[19:0]

t

h(A-D)R

t

su(D)R

t

a(A)M

t

h(D)R

D[15:0]

t

h(D)MSTRBH

t

d(CLKL-MSL)

t

d(CLKL-MSH)

t

a(MSTRBL)

MSTRB

R/W

PS, DS

Figure 9. Memory Read (MSTRB = 0)

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

†

(MSTRB = 0) [H = 0.5 t

] (see Figure 10)

c(CO)

PARAMETER

MIN

0

MAX

UNIT

ns

‡

t

Delay time, CLKOUT high to address valid

8

d(CLKH-A)

§

Delay time, CLKOUT low to address valid

Delay time, CLKOUT low to MSTRB low

Delay time, CLKOUT low to data valid

Delay time, CLKOUT low to MSTRB high

Delay time, CLKOUT high to R/W low

Delay time, CLKOUT high to R/W high

Delay time, R/W low to MSTRB low

0

ns

d(CLKL-A)

t

0

8

ns

d(CLKL-MSL)

t

0

10

8

ns

d(CLKL-D)W

t

0

ns

d(CLKL-MSH)

t

0

8

ns

d(CLKH-RWL)

t

0

8

ns

d(CLKH-RWH)

t

H–2

0

H+2

8

ns

d(RWL-MSTRBL)

‡

t

Hold time, address valid after CLKOUT high

ns

h(A)W

§

t

Hold time, write data valid after MSTRB high

Pulse duration, MSTRB low

H–3 H+3

ns

h(D)MSH

w(SL)MS

su(A)W

2H–4

Setup time, address valid before MSTRB low

Setup time, write data valid before MSTRB high

Enable time, data bus driven after R/W low

Disable time, R/W high to data bus high impedance

2H–4

§

2H

2H–10

H–5

su(D)MSH

en(D–RWL)

dis(RWH–D)

0

†

‡

§

Address, PS, and DS timings are all included in timings referenced as address.

In the case of a memory write preceded by a memory write

In the case of a memory write preceded by an I/O cycle

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

CLKOUT

A[19:0]

D[15:0]

MSTRB

R/W

t

d(CLKH-A)

t

d(CLKL-A)

t

h(A)W

t

d(CLKL-D)W

t

h(D)MSH

t

su(D)MSH

t

d(CLKL-MSL)

t

dis(RWH-D)

t

d(CLKL-MSH)

t

su(A)W

t

d(CLKH-RWL)

d(CLKH-RWH)

t

w(SL)MS

en(D-RWL)

t

d(RWL-MSTRBL)

PS, DS

Figure 10. Memory Write (MSTRB = 0)

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port read

†

(IOSTRB = 0) (see Figure 11)

PARAMETER

Delay time, CLKOUT low to address valid

Delay time, CLKOUT high to IOSTRB low

Delay time, CLKOUT high to IOSTRB high

Hold time, address after CLKOUT low

MIN

0

MAX

UNIT

ns

t

8

d(CLKL-A)

t

0

ns

d(CLKH-ISTRBL)

t

0

ns

d(CLKH-ISTRBH)

t

0

ns

h(A)IOR

†

Address and IS timings are included in timings referenced as address.

†

timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t

] (see Figure 11)

c(CO)

MIN

MAX

3H–15

2H–15

UNIT

ns

t

Access time, read data access from address valid

Access time, read data access from IOSTRB low

Setup time, read data before CLKOUT high

Hold time, read data after CLKOUT high

a(A)IO

ns

a(ISTRBL)IO

su(D)IOR

10

0

ns

h(D)IOR

Hold time, read data after IOSTRB high

0

ns

h(ISTRBH-D)R

†

Address and IS timings are included in timings referenced as address.

CLKOUT

t

h(A)IOR

d(CLKL-A)

A[19:0]

t

h(D)IOR

t

su(D)IOR

t

a(A)IO

D[15:0]

t

h(ISTRBH-D)R

d(CLKH-ISTRBH)

t

a(ISTRBL)IO

t

d(CLKH-ISTRBL)

IOSTRB

R/W

IS

Figure 11. Parallel I/O Port Read (IOSTRB = 0)

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

†

(IOSTRB = 0) [H = 0.5 t

] (see Figure 12)

c(CO)

PARAMETER

MIN MAX

UNIT

ns

t

Delay time, CLKOUT low to address valid

Delay time, CLKOUT high to IOSTRB low

Delay time, CLKOUT high to write data valid

Delay time, CLKOUT high to IOSTRB high

Delay time, CLKOUT low to R/W low

0

8

d(CLKL-A)

t

ns

d(CLKH-ISTRBL)

t

H–5

0

H+3

8

ns

d(CLKH-D)IOW

t

ns

d(CLKH-ISTRBH)

t

0

8

ns

d(CLKL-RWL)

d(CLKL-RWH)

t

Delay time, CLKOUT low to R/W high

0

8

ns

Hold time, address valid after CLKOUT low

Hold time, write data after IOSTRB high

Setup time, write data before IOSTRB high

Setup time, address valid before IOSTRB low

0

H–3

8

H+3

H+1

H+3

ns

h(A)IOW

h(D)IOW

su(D)IOSTRBH

su(A)IOSTRBL

†

Address and IS timings are included in timings referenced as address.

CLKOUT

t

su(A)IOSTRBL

t

h(A)IOW

t

d(CLKL-A)

A[19:0]

t

d(CLKH-D)IOW

t

h(D)IOW

D[15:0]

t

d(CLKH-ISTRBL)

t

d(CLKH-ISTRBH)

t

su(D)IOSTRBH

t

IOSTRB

R/W

t

d(CLKL-RWL)

d(CLKL-RWH)

IS

Figure 12. Parallel I/O Port Write (IOSTRB = 0)

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states

†

timing requirements for externally generated wait states [H = 0.5 t

Figure 15, and Figure 16)

] (see Figure 13, Figure 14,

c(CO)

MIN

10

0

MAX

UNIT

ns

t

Setup time, READY before CLKOUT low

Hold time, READY after CLKOUT low

su(RDY)

ns

h(RDY)

‡

Valid time, READY after MSTRB low

4H–15

5H–15

ns

v(RDY)MSTRB

h(RDY)MSTRB

v(RDY)IOSTRB

h(RDY)IOSTRB

v(MSCL)

‡

Hold time, READY after MSTRB low

4H

ns

‡

Valid time, READY after IOSTRB low

ns

‡

Hold time, READY after IOSTRB low

5H

0

ns

Valid time, MSC low after CLKOUT low

Valid time, MSC high after CLKOUT low

8

ns

0

ns

v(MSCH)

†

The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using

READY, at least two software wait states must be programmed.

These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

‡

CLKOUT

A[19:0]

t

su(RDY)

t

h(RDY)

READY

MSTRB

MSC

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait State

Generated

by READY

Wait States

Generated Internally

Figure 13. Memory Read With Externally Generated Wait States

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

D[15:0]

READY

MSTRB

MSC

t

h(RDY)

t

su(RDY)

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait States

Generated Internally

Wait State Generated

by READY

Figure 14. Memory Write With Externally Generated Wait States

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

t

h(RDY)

t

su(RDY)

READY

IOSTRB

MSC

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait

States

Generated

Internally

Figure 15. I/O Read With Externally Generated Wait States

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

D[15:0]

READY

t

h(RDY)

t

su(RDY)

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

IOSTRB

MSC

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait States

Generated

Internally

Figure 16. I/O Write With Externally Generated Wait States

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

HOLD and HOLDA timings

switching characteristics over recommended operating conditions for memory control signals

and HOLDA, [H = 0.5 t

] (see Figure 17)

c(CO)

PARAMETER

MIN

MAX

2

UNIT

ns

t

Disable time, address, PS, DS, IS high impedance from CLKOUT low

Disable time, R/W high impedance from CLKOUT low

Disable time, MSTRB, IOSTRB high impedance from CLKOUT low

Enable time, address, PS, DS, IS from CLKOUT low

dis(CLKL-A)

dis(CLKL-RW)

dis(CLKL-S)

en(CLKL-A)

en(CLKL-RW)

en(CLKL-S)

2

ns

2

ns

2H+10

ns

Enable time, R/W enabled from CLKOUT low

ns

Enable time, MSTRB, IOSTRB enabled from CLKOUT low

2

0

ns

10

8

ns

Valid time, HOLDA low after CLKOUT low

t

v(HOLDA)

–2

Valid time, HOLDA high after CLKOUT low

Pulse duration, HOLDA low duration

2H–3

w(HOLDA)

timing requirements for memory control signals and HOLDA, [H = 0.5 t

] (see Figure 17)

c(CO)

MIN

4H+10

15

MAX

UNIT

ns

t

Pulse duration, HOLD low

w(HOLD)

Setup time, HOLD low/high before CLKOUT low

ns

su(HOLD)

CLKOUT

t

su(HOLD)

t

w(HOLD)

HOLD

t

v(HOLDA)

t

w(HOLDA)

HOLDA

dis(CLKL-A)

t

en(CLKL-A)

A[19:0]

PS, DS, IS

D[15:0]

R/W

t

dis(CLKL-RW)

dis(CLKL-S)

en(CLKL-RW)

t

en(CLKL-S)

MSTRB

IOSTRB

t

en(CLKL-S)

Figure 17. HOLD and HOLDA Timings (HM = 1)

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

reset, BIO, interrupt, and MP/MC timings

timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t

and Figure 20)

] (see Figure 18, Figure 19,

c(CO)

MIN

0

MAX

UNIT

ns

t

Hold time, RS after CLKOUT low

Hold time, BIO after CLKOUT low

Hold time, INTn, NMI, after CLKOUT low

Hold time, MP/MC after CLKOUT low

h(RS)

0

h(BIO)

†

0

h(INT)

0

h(MPMC)

w(RSL)

‡§

Pulse duration, RS low

4H+5

2H+5

4H

2H+7

4H

2H+7

4H

12

Pulse duration, BIO low, synchronous

Pulse duration, BIO low, asynchronous

w(BIO)S

w(BIO)A

w(INTH)S

w(INTH)A

w(INTL)S

w(INTL)A

w(INTL)WKP

su(RS)

Pulse duration, INTn, NMI high (synchronous)

Pulse duration, INTn, NMI high (asynchronous)

Pulse duration, INTn, NMI low (synchronous)

Pulse duration, INTn, NMI low (asynchronous)

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

¶

Setup time, RS before X2/CLKIN low

5

Setup time, BIO before CLKOUT low

12

15

su(BIO)

Setup time, INTn, NMI, RS before CLKOUT low

Setup time, MP/MC before CLKOUT low

12

su(INT)

12

su(MPMC)

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is

corresponding to three CLKOUT sampling sequences.

If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure

synchronization and lock-in of the PLL.

‡

§

¶

Note that RS may cause a change in clock frequency, therefore changing the value of H.

Divide-by-two mode

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

reset, BIO, interrupt, and MP/MC timings (continued)

X2/CLKIN

t

su(RS)

t

w(RSL)

RS, INTn, NMI

t

su(INT)

t

h(RS)

CLKOUT

t

su(BIO)

t

h(BIO)

BIO

t

w(BIO)S

Figure 18. Reset and BIO Timings

CLKOUT

t

su(INT)

h(INT)

INTn, NMI

t

w(INTH)A

t

w(INTL)A

Figure 19. Interrupt Timing

CLKOUT

RS

t

h(MPMC)

t

su(MPMC)

MP/MC

Figure 20. MP/MC Timing

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings

switching characteristics over recommended operating conditions for IAQ and IACK

[H = 0.5 t

] (see Figure 21)

c(CO)

PARAMETER

MIN

0

MAX

UNIT

ns

t

Delay time, CLKOUT low to IAQ low

Delay time, CLKOUT low to IAQ high

Delay time, address valid to IAQ low

Delay time, CLKOUT low to IACK low

Delay time , CLKOUT low to IACK high

Delay time, address valid to IACK low

Hold time, IAQ high after address invalid

Hold time, IACK high after address invalid

Pulse duration, IAQ low

8

d(CLKL-IAQL)

t

0

ns

d(CLKL-IAQH)

d(A)IAQ

t

10

8

ns

t

0

ns

d(CLKL-IACKL)

t

8

ns

d(CLKL-IACKH)

d(A)IACK

h(A)IAQ

t

8

ns

0

ns

h(A)IACK

w(IAQL)

2H–5

ns

Pulse duration, IACK low

ns

w(IACKL)

CLKOUT

A[19:0]

IAQ

t

d(CLKL-IAQH)

d(CLKL-IAQL)

t

h(A)IAQ

t

d(A)IAQ

t

w(IAQL)

t

d(CLKL-IACKH)

d(CLKL-IACKL)

t

h(A)IACK

t

d(A)IACK

t

w(IACKL)

IACK

MSTRB

Figure 21. IAQ and IACK Timings

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings

(continued)

switching characteristics over recommended operating conditions for XF and TOUT

[H = 0.5 t

] (see Figure 22 and Figure 23)

c(CO)

PARAMETER

MIN

0

MAX

UNIT

Delay time, CLKOUT low to XF high

Delay time, CLKOUT low to XF low

8

t

ns

d(XF)

0

t

Delay time, CLKOUT low to TOUT high

Delay time, CLKOUT low to TOUT low

Pulse duration, TOUT

0

8

ns

d(TOUTH)

d(TOUTL)

w(TOUT)

2H–10

CLKOUT

t

d(XF)

XF

Figure 22. XF Timing

CLKOUT

TOUT

t

d(TOUTL)

d(TOUTH)

t

w(TOUT)

Figure 23. TOUT Timing

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing

timing requirements for McBSP [H=0.5t

†

] (see Figure 24 and Figure 25)

c(CO)

MIN

4H

2H–1

15

1

MAX UNIT

t

Cycle time, BCLKR/X

BCLKR/X ext

ns

c(BCKRX)

Pulse duration, BCLKR/X high or BCLKR/X low

BCLKR/X ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BCLKR/X ext

w(BCKRX)

t

Setup time, external BFSR high before BCLKR low

ns

su(BFRH-BCKRL)

h(BCKRL-BFRH)

su(BDRV-BCKRL)

h(BCKRL-BDRV)

su(BFXH-BCKXL)

h(BCKXL-BFXH)

10

3

Hold time, external BFSR high after BCLKR low

Setup time, BDR valid before BCLKR low

Hold time, BDR valid after BCLKR low

15

0

3

15

1

Setup time, external BFSX high before BCLKX low

Hold time, external BFSX high after BCLKX low

0

t

Rise time, BCKR/X

Fall time, BCKR/X

8

ns

r(BCKRX)

f(BCKRX)

†

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

†

switching characteristics for McBSP [H=0.5t

] (see Figure 24 and Figure 25)

c(CO)

PARAMETER

MIN

4H

MAX UNIT

t

Cycle time, BCLKR/X

BCLKR/X int

BCLKR int

BCLKR ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

ns

c(BCKRX)

‡

Pulse duration, BCLKR/X high

Pulse duration, BCLKR/X low

D–1

C–1

D+1

ns

w(BCKRXH)

w(BCKRXL)

‡

C+1

0

8

t

Delay time, BCLKR high to internal BFSR valid

Delay time, BCLKX high to internal BFSX valid

d(BCKRH-BFRV)

d(BCKXH-BFXV)

10

0

15

8

ns

10

2

15

7

Disable time, BCLKX high to BDX high impedance following last data

bit of transfer

t

dis(BCKXH-BDXHZ)

10

15

7

§

2

DXENA = 0

10

15

20

t

Delay time, BCLKX high to BDX valid

ns

d(BCKXH-BDXV)

d(BFXH-BDXV)

§

10

DXENA = 1, first bit

only

15

§

2

Delay time, BFSX high to BDX valid

BFSX int

BFSX ext

7

t

ns

10

15

ONLY applies when in data delay 0 (XDATDLY = 00b) mode

†

‡

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

T = BCLKRX period = (1 + CLKGDV) * 2H

C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

Minimum delay times also represent minimum output hold times.

§

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

t

c(BCKRX)

t

w(BCKRXH)

w(BCKRXL)

t

f(BCKRX)

r(BCKRX)

t

BCLKR

BFSR (int)

BFSR (ext)

BDR

t

d(BCKRH-BFRV)

t

d(BCKRH-BFRV)

t

su(BFRH-BCKRL)

t

h(BCKRL-BFRH)

t

su(BDRV-BCKRL)

t

h(BCKRL-BDRV)

(n-2)

(n-3)

Bit(n-1)

Figure 24. McBSP Receive Timings

t

c(BCKRX)

t

w(BCKRXH)

t

f(BCKRX)

r(BCKRX)

w(BCKRXL)

BCLKX

t

d(BCKXH-BFXV)

t

d(BCKXH-BFXV)

BFSX (int)

t

h(BCKXL-BFXH)

t

su(BFXH-BCKXL)

BFSX (ext)

BFSX

(XDATDLY=00b)

t

d(BCKXH-BDXV)

t

d(BFXH-BDXV)

t

dis(BCKXH-BDXHZ)

d(BCKXH-BDXV)

BDX

Bit 0

Bit(n-1)

(n-2)

(n-3)

Figure 25. McBSP Transmit Timings

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

timing requirements for McBSP general-purpose I/O (see Figure 26)

MIN

15

0

MAX UNIT

†

t

Setup time, BGPIOx input mode before CLKOUT high

ns

su(BGPIO-COH)

†

Hold time, BGPIOx input mode after CLKOUT high

h(COH-BGPIO)

†

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

switching characteristics for McBSP general-purpose I/O (see Figure 26)

PARAMETER

MIN

MAX UNIT

‡

t

Delay time, CLKOUT high to BGPIOx output mode

0

10

ns

d(COH-BGPIO)

‡

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

t

su(BGPIO-COH)

d(COH-BGPIO)

CLKOUT

t

h(COH-BGPIO)

BGPIOx Input

†

mode

BGPIOx Output

‡

mode

†

‡

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

Figure 26. McBSP General-Purpose I/O Timings

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 27)

] CLKSTP = 10b, CLKXP = 0

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

15

6

MAX

t

Setup time, BDR valid before BCLKX low

Hold time, BDR valid after BCLKX low

–12H

ns

su(BDRV-BCKXL)

5+12H

h(BCKXL-BDRV)

t

Setup time, BFSX low before BCLKX high

15

ns

su(BFXL-BCKXH)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

] CLKSTP = 10b,

c(CO)

†

CLKXP = 0 (see Figure 27)

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN

T–2

C–2

0

MAX

T+3

C+3

7

MIN

MAX

§

t

Hold time, BFSX low after BCLKX low

ns

h(BCKXL-BFXL)

d(BFXL-BCKXH)

d(BCKXH-BDXV)

¶

Delay time, BFSX low to BCLKX high

Delay time, BCLKX high to BDX valid

6H+10

10H+25

Disable time, BDX high impedance following last data bit from

BCLKX low

t

C–2

C+3

ns

dis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

t

2H+10

4H+10

6H+25

8H+25

ns

dis(BFXH-BDXHZ)

Delay time, BFSX low to BDX valid

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

t

MSB

LSB

su(BFXL-BCKXH)

BCLKX

BFSX

t

h(BCKXL-BFXL)

t

d(BFXL-BCKXH)

t

dis(BFXH-BDXHZ)

t

d(BFXL-BDXV)

t

d(BCKXH-BDXV)

(n-2)

dis(BCKXL-BDXHZ)

BDX

BDR

Bit 0

Bit(n-1)

(n-3)

(n-4)

t

su(BDRV-BCLXL)

t

h(BCKXL-BDRV)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 27. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 28)

] CLKSTP = 11b, CLKXP = 0

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

15

6

MAX

t

Setup time, BDR valid before BCLKX high

Hold time, BDR valid after BCLKX high

–12H

ns

su(BDRV-BCKXH)

5+12H

h(BCKXH-BDRV)

t

Setup time, BFSX low before BCLKX high

15

ns

su(BFXL-BCKXH)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 0 (see Figure 28)

] CLKSTP = 11b,

c(CO)

†

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN

C–2

T–2

0

MAX

C+3

T+3

6

MIN

MAX

§

t

Hold time, BFSX low after BCLKX low

ns

h(BCKXL-BFXL)

d(BFXL-BCKXH)

d(BCKXL-BDXV)

¶

Delay time, BFSX low to BCLKX high

Delay time, BCLKX low to BDX valid

6H+10

10H+25

8H+25

Disable time, BDX high impedance following last data bit from

BCLKX low

t

0

6

ns

dis(BCKXL-BDXHZ)

t

Delay time, BFSX low to BDX valid

D–2

D+4 4H+10

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

MSB

t

LSB

su(BFXL-BCKXH)

BCLKX

t

d(BFXL-BCKXH)

h(BCKXL-BFXL)

BFSX

t

d(BCKXL-BDXV)

dis(BCKXL-BDXHZ)

t

d(BFXL-BDXV)

BDX

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

t

su(BDRV-BCKXH)

t

h(BCKXH-BDRV)

BDR

Bit 0

(n-2)

(n-3)

(n-4)

Figure 28. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 29)

] CLKSTP = 10b, CLKXP = 1

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

15

6

MAX

t

Setup time, BDR valid before BCLKX high

Hold time, BDR valid after BCLKX high

–12H

ns

su(BDRV-BCKXH)

5+12H

h(BCKXH-BDRV)

t

Setup time, BFSX low before BCLKX low

15

ns

su(BFXL-BCKXL)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 1 (see Figure 29)

] CLKSTP = 10b,

c(CO)

†‡

MASTER

SLAVE

UNIT

PARAMETER

MIN

T–2

D–2

0

MAX

T+3

MIN

MAX

§

t

Hold time, BFSX low after BCLKX high

ns

h(BCKXH-BFXL)

d(BFXL-BCKXL)

d(BCKXL-BDXV)

¶

Delay time, BFSX low to BCLKX low

D+3

6

Delay time, BCLKX low to BDX valid

6H+10

10H+25

Disable time, BDX high impedance following last data bit from

BCLKX high

t

D–2

D+3

ns

dis(BCKXH-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

t

2H+10

4H+10

6H+25

8H+25

ns

dis(BFXH-BDXHZ)

Delay time, BFSX low to BDX valid

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

t

LSB

su(BFXL-BCKXL)

MSB

BCLKX

BFSX

t

h(BCKXH-BFXL)

t

d(BFXL-BCKXL)

t

d(BFXL-BDXV)

dis(BFXH-BDXHZ)

t

d(BCKXL-BDXV)

dis(BCKXH-BDXHZ)

BDX

BDR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

t

su(BDRV-BCKXH)

h(BCKXH-BDRV)

(n-2)

Bit 0

Bit(n-1)

(n-3)

(n-4)

Figure 29. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 30)

] CLKSTP = 11b, CLKXP = 1

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

15

6

MAX

t

Setup time, BDR valid before BCLKX low

Hold time, BDR valid after BCLKX low

–12H

ns

su(BDRV-BCKXL)

5+12H

h(BCKXL-BDRV)

t

Setup time, BFSX low before BCLKX low

15

ns

su(BFXL-BCKXL)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 1 (see Figure 30)

] CLKSTP = 11b,

c(CO)

†‡

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN

D–2

T–2

0

MAX

D+3

MIN

MAX

§

t

Hold time, BFSX low after BCLKX high

ns

h(BCKXH-BFXL)

d(BFXL-BCKXL)

d(BCKXH-BDXV)

¶

Delay time, BFSX low to BCLKX low

T+1

6

Delay time, BCLKX high to BDX valid

6H+10

10H+25

8H+25

Disable time, BDX high impedance following last data bit from

BCLKX high

t

0

6

ns

dis(BCKXH-BDXHZ)

t

Delay time, BFSX low to BDX valid

C–2

C+4 4H+10

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

t

su(BFXL-BCKXL)

MSB

LSB

BCLKX

t

h(BCKXH-BFXL)

t

d(BFXL-BCKXL)

BFSX

t

d(BCKXH-BDXV)

(n-2)

dis(BCKXH-BDXHZ)

d(BFXL-BDXV)

BDX

Bit 0

Bit(n-1)

(n-3)

(n-4)

t

su(BDRV-BCKXL)

t

h(BCKXL-BDRV)

BDR

Bit 0

(n-2)

(n-3)

(n-4)

Figure 30. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing

switching characteristics over recommended operating conditions†‡§¶ [H = 0.5t

(see Figure 31, Figure 32, Figure 33, and Figure 34)

]

c(CO)

PARAMETER

MIN

MAX

UNIT

t

Enable time, HD driven from DS low

10

25

ns

en(DSL-HD)

Case 1a: Memory accesses when

DMAC is active in 16-bit mode and

18H+20–t

w(DSH)

t

< 18H

w(DSH)

Case 1b: Memory accesses when

DMAC is active in 16-bit mode and

20

26H+20–t

20

t

≥ 18H

w(DSH)

Case 1c: Memory access when

DMAC is active in 32-bit mode and

w(DSH)

t

< 26H

Delay time, DS low to HDx valid for

first byte of an HPI read

w(DSH)

t

ns

d(DSL-HDV1)

Case 1d: Memory access when

DMAC is active in 32-bit mode and

t

≥ 26H

w(DSH)

Case 2a: Memory accesses when

DMAC is inactive and t < 10H

10H+20–t

20

w(DSH)

Case 2b: Memory accesses when

DMAC is inactive and t ≥ 10H

w(DSH)

Case 3: Register accesses

20

10

8

t

Delay time, DS low to HDx valid for second byte of an HPI read

Hold time, HDx valid after DS high, for a HPI read

Valid time, HDx valid after HRDY high

ns

d(DSL-HDV2)

h(DSH-HDV)R

v(HYH-HDV)

d(DSH-HYL)

5

Delay time, DS high to HRDY low (see Note 1)

10

ns

Case 1a: Memory accesses when

DMAC is active in 16-bit mode

18H+15

Case 1b: Memory accesses when

DMAC is active in 32-bit mode

26H+15

10H+15

6H+15

ns

t

Delay time, DS high to HRDY high

d(DSH-HYH)

Case 2: Memory accesses when

DMAC is inactive

Case 3: Write accesses to HPIC

register (see Note 2)

15

ns

t

Delay time, HCS low/high to HRDY low/high

Delay time, CLKOUT high to HRDY high

Delay time, CLKOUT high to HINT change

d(HCS-HRDY)

)

d(COH-HYH

d(COH-HTX)

d(COH-GPIO)

Delay time, CLKOUT high to HDx output change. HDx is configured as a

general-purpose output.

t

8

ns

NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.

2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur

asynchronoulsy, and do not cause HRDY to be deasserted.

DS refers to the logical OR of HCS, HDS1, and HDS2.

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are

affected by DMAC activity.

†

‡

§

¶

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

timing requirements†‡§ (see Figure 31, Figure 32, Figure 33, and Figure 34)

MIN

10

5

MAX

UNIT

ns

t

Setup time, HBIL valid before DS low

Hold time, HBIL valid after DS low

su(HBV-DSL)

ns

h(DSL-HBV)

t

Setup time, HAS low before DS low

10

20

10

5

ns

su(HSL-DSL)

Pulse duration, DS low

w(DSL)

Pulse duration, DS high

w(DSH)

Setup time, HDx valid before DS high, HPI write

Hold time, HDx valid after DS high, HPI write

su(HDV-DSH)

h(DSH-HDV)W

su(GPIO-COH)

h(GPIO-COH)

3

Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input

Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input

8

0

†

DS refers to the logical OR of HCS, HDS1, and HDS2.

‡

§

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

Second Byte

First Byte

Second Byte

HAS

t

su(HBV-DSL)

t

su(HSL-DSL)

t

h(DSL-HBV)

†

HAD

Valid

‡

t

su(HBV-DSL)

‡

t

h(DSL-HBV)

HBIL

HCS

t

w(DSH)

t

w(DSL)

HDS

t

d(DSH-HYH)

t

d(DSH-HYL)

HRDY

t

en(DSL-HD)

t

d(DSL-HDV2)

t

d(DSL-HDV1)

Valid

t

h(DSH-HDV)R

HD READ

Valid

t

su(HDV-DSH)

t

v(HYH-HDV)

Valid

t

h(DSH-HDV)W

HD WRITE

CLKOUT

Valid

t

d(COH-HYH)

†

‡

HAD refers to HCNTL0, HCNTL1, and HR/W.

When HAS is not used (HAS always high)

Figure 31. Using HDS to Control Accesses (HCS Always Low)

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

Second Byte

First Byte

Second Byte

HCS

HDS

t

d(HCS-HRDY)

HRDY

Figure 32. Using HCS to Control Accesses

CLKOUT

t

d(COH-HTX)

HINT

Figure 33. HINT Timing

CLKOUT

t

su(GPIO-COH)

t

h(GPIO-COH)

†

GPIOx Input Mode

t

d(COH-GPIO)

GPIOx Output Mode

†

GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).

†

Figure 34. GPIOx Timings

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

MECHANICAL DATA

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

0,17

M

0,08

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/B 10/94

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-136

Thermal Resistance Characteristics

PARAMETER

°C/W

R

56

ΘJA

ΘJC

R

5

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UVC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS100A – APRIL 1999 – REVISED AUGUST 1999

MECHANICAL DATA

GGU (S-PBGA-N144)

PLASTIC BALL GRID ARRAY PACKAGE

12,10

11,90

SQ

9,60 TYP

0,80

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2 3 4 5 6 7 8 9 10 11 12 13

0,95

0,85

1,40 MAX

Seating Plane

0,10

0,55

0,45

0,12

0,08

M

0,08

0,45

0,35

4073221/A 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar BGA configuration

Thermal Resistance Characteristics

PARAMETER

°C/W

R

38

ΘJA

ΘJC

R

5

MicroStar BGA is a trademark of Texas Instruments Incorporated.

59

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型号：	TMS320UVC5402GGU
厂家：	TEXAS INSTRUMENTS
描述：	FIXED-POINT DIGITAL SIGNAL PROCESSOR 定点数字信号处理器数字信号处理器
文件：	总60页 (文件大小：771K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320UVC5402GGU [TI]

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