TMS320VC5407 [TI]
Fixed-Point Digital Signal Processors; 定点数字信号处理器
| 型号： | TMS320VC5407 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processors |
| 文件： | 总110页 (文件大小：1351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5407/TMS320VC5404
Fixed-Point Digital Signal
Processors
Data Manual
Literature Number: SPRS007D
November 2001 − Revised April 2004
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright 2004, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS007C device-specific data
sheet to make it an SPRS007D revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
21
Added “This pin must be tied directly to DV to enable HPI.” to the HPIENA description and “This pin must be tied directly to
DD
DV to enable HPI16 mode.” to the HPI16 description in Table 2−2. Also deleted “Internally pulled low.” from the HPI16
DD
description.
38
Added the following to Section 3.9: “Since the Timer1 output is multiplexed externally with the HINT output, the HPI must be
disabled (HPIENA input pin = 0) if the Timer1 output is to be used. The Timer1 output also has a dedicated enable bit in the
General Purpose I/O Control Register (GPIOCR) located at data memory address 003Ch. If the external Timer1 output is to
be used, in addition to disabling the HPI, the TOUT1 bit in the GPIOCR must also be set to 1.”
42
48
Changed the parenthetical statement “(such as the McBSPs)” in Section 3.12. to read “(such as the McBSPs, but not the
UART)”
Added the following footnote to Table 3−12: “Note that the UART DMA synchronization event is usable as a synchronization
event only, and is not usable for transferring data to or from the UART. The DMA cannot be used to transfer data to or from
the UART.”
59
60
Changed Figure 3−23, bit 15 from “Reserved” to “TOUT1”.
Added the following paragraph to Section 3.14.2: “Bit 15 of the GPIOCR is also used as the Timer1 output enable bit, TOUT1.
The TOUT1 bit enables or disables the Timer1 output on the HINT/TOUT1 pin. If TOUT1 = 0, the Timer1 output is not
available externally; if TOUT1 = 1, the Timer1 output is driven on the HINT/TOUT1 pin. Note also that the Timer1 output is
only available when the HPI is disabled (HPIENA input pin = 0).”
71
Changed the I
parameter from “60” to “42” in the Electrical Characteristics Over Recommended Operating Case
DDC
Temperature Range table.
3
November 2001 − Revised April 2004
SPRS007D
Revision History
4
SPRS007D
November 2001 − Revised April 2004
Contents
Contents
Section
Page
1
2
TMS320VC5407/TMS320VC5404 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
15
17
18
2.1
2.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
2.2.2
Terminal Assignments for the GGU Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
24
24
24
25
25
26
26
27
28
30
30
32
33
33
33
35
36
38
39
40
42
43
43
44
46
46
46
47
47
47
48
48
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
3.1.3
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
3.3
3.4
3.5
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
3.5.2
3.5.3
5407 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5404 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
3.7
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
3.6.2
3.6.3
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Bank-Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
3.7.2
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
3.9
3.10
3.11
3.12
Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced External Parallel Interface (XIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1
3.12.2
3.12.3
3.12.4
3.12.5
3.12.6
3.12.7
3.12.8
3.12.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Source/Destination Address Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA in Autoinitialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Transfer in Doubleword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.10 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.11 DMA Controller Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
November 2001 − Revised April 2004
SPRS007D
Contents
Section
3.13
Page
Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
52
53
53
54
54
54
55
56
57
57
59
59
59
60
61
63
64
66
67
3.13.1
3.13.2
3.13.3
3.13.4
3.13.5
3.13.6
3.13.7
3.13.8
3.13.9
UART Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO Control Register (FCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO Interrupt Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO Polled Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Identification Register (IIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Status Register (LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modem Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.10 Programmable Baud Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14
3.14.1
3.14.2
McBSP Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Data Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15
3.16
3.17
3.18
3.19
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.1
IFR and IMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
69
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
70
70
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
72
72
72
73
73
75
76
76
79
81
83
84
87
88
90
91
5.4
5.5
5.6
5.7
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
5.7.2
Divide-By-Two and Divide-By-Four Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1
5.8.2
5.8.3
5.8.4
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . .
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
5.11
5.12
5.13
6
SPRS007D
November 2001 − Revised April 2004
Contents
Page
Section
5.14
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
92
95
5.14.1
5.14.2
5.14.3
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
5.15
5.16
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
100
104
107
5.15.1
5.15.2
HPI8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
108
108
109
6.1
6.2
Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
November 2001 − Revised April 2004
SPRS007D
Figures
Figure
List of Figures
Page
2−1
2−2
144-Ball GGU MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PGE Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
17
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
TMS320VC5407/TMS320VC5404 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5407 Program and Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5407 Extended Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5404 Program and Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5404 Extended Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . .
Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
26
26
27
28
29
30
31
32
35
35
37
37
38
40
41
42
43
45
46
47
50
59
60
60
67
3−10 Host-Port Interface — Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 HPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Multichannel Control Register (MCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Multichannel Control Register (MCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Nonconsecutive Memory Read and I/O Read Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Consecutive Memory Read Bus Sequence (n = 3 reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Memory Write and I/O Write Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 DMA Transfer Mode Control Register (DMMCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . . .
3−20 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . .
3−21 DMPREC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−22 UART Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−23 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] . . . . . . . . . . . . . . . . . . . .
3−24 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] . . . . . . . . . . . . . . . . . . . . .
3−25 Device ID Register (CSIDR) [MMR Address 003Eh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−26 IFR and IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Divide-by-Two Clock Option With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonconsecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Consecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write (MSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Read (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel I/O Port Write (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
73
74
75
77
78
80
82
83
8
SPRS007D
November 2001 − Revised April 2004
Figures
Page
Figure
5−10 Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15 Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17 MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . .
5−19 External Flag (XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20 TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−21 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−22 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−23 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−28 Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−29 Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−30 HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−31 GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−32 Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−33 Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−34 HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−35 UART Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
85
86
86
87
88
89
89
90
91
91
93
94
95
96
97
98
99
102
103
103
103
105
106
106
107
6−1
6−2
TMS320VC5407/TMS320VC5404 144-Ball MicroStar BGA Plastic Ball Grid Array Package . . . .
TMS320VC5407/TMS320VC5404 144-Pin Low-Profile Quad Flatpack (PGE) . . . . . . . . . . . . . . . .
108
109
9
November 2001 − Revised April 2004
SPRS007D
Tables
Table
List of Tables
Page
2−1
2−2
Terminal Assignments for the 144-Pin BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
18
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
Standard On-Chip ROM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Mode Status (PMST) Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bank-Switching Control Register (BSCR) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMD Section of the DMMCRn Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Reload Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA/CPU Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Reset Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary of Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver FIFO Trigger Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Character Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Number of Stop Bits Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rates Using a 1.8432-MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rates Using a 3.072-MHz Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID Register (CSIDR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
29
31
31
32
33
38
39
44
47
48
48
49
51
52
53
55
55
56
58
58
60
61
62
63
64
66
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
3−18
3−19
3−20
3−21
3−22
3−23
3−24
3−25
3−26
3−27
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
5−13
Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clock Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
72
73
74
74
75
75
76
76
79
81
81
83
10
SPRS007D
November 2001 − Revised April 2004
Tables
Page
Table
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
5−36
5−37
5−38
Ready Timing Requirements for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . .
Ready Switching Characteristics for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . . .
External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
84
87
87
88
90
91
92
93
95
95
96
96
97
97
98
98
99
99
100
101
104
105
107
107
11
November 2001 − Revised April 2004
SPRS007D
Tables
12
SPRS007D
November 2001 − Revised April 2004
Features
1
TMS320VC5407/TMS320VC5404 Features
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
D
D
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
Arithmetic Instructions With Parallel Store
and Parallel Load
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D
D
D
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
− On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source
− Two 16-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
− Universal Asynchronous Receiver/
Transmitter (UART) With Integrated Baud
Rate Generator
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
D
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D
D
On-Chip ROM
− 128K × 16-Bit (5407) Configured for
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
Program Memory
− 64K × 16-Bit (5404) Configured for
Program Memory
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
On-Chip RAM
− 40K x 16-Bit (5407) Composed of
Five Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
− 16K x 16-Bit (5404) Composed of
Two Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
†
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D
D
D
144-Pin Ball Grid Array (BGA)
(GGU Suffix)
144-Pin Low-Profile Quad Flatpack (LQFP)
(PGE Suffix)
D
D
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and
8.33-ns Single-Cycle Fixed-Point
Block-Repeat Operations for Program Code
Instruction Execution Time (120 MIPS)
D
Block-Memory-Move Instructions for Better
Program and Data Management
D
D
3.3-V I/O Supply Voltage
1.5-V Core Supply Voltage
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
All trademarks are the property of their respective owners.
13
November 2001 − Revised April 2004
SPRS007D
Introduction
2
Introduction
This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404
(hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407
and 5404 are essentially the same device except for differences in their memory maps.
This section lists the pin assignments and describes the function of each pin. This data manual also provides
a detailed description section, electrical specifications, parameter measurement information, and mechanical
data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1 Description
The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function
calls.
2.2 Pin Assignments
Figure 2−1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers. Figure 2−2 provides the pin assignments for the
144-pin low-profile quad flatpack (LQFP) package.
TMS320C54x is a trademark of Texas Instruments.
14
SPRS007D
November 2001 − Revised April 2004
Introduction
2.2.1 Terminal Assignments for the GGU Package
13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 2−1. 144-Ball GGU MicroStar BGA (Bottom View)
Table 2−1 lists each signal name and BGA ball number for the 144-pin TMS320VC5407/
TMS320VC5404GGU package. Table 2−2 lists each terminal name, terminal function, and operating modes
for the TMS320VC5407/TMS320VC5404.
MicroStar BGA is a trademark of Texas Instruments.
15
November 2001 − Revised April 2004
SPRS007D
Introduction
†
Table 2−1. Terminal Assignments for the 144-Pin BGA Package
SIGNAL
SIGNAL
SIGNAL
SIGNAL
QUADRANT 1
QUADRANT 2
QUADRANT 3
QUADRANT 4
BGA BALL #
A1
BGA BALL #
N13
M13
L12
BGA BALL #
N1
BGA BALL #
A13
A12
B11
A11
D10
C10
B10
A10
D9
V
SS
BCLKRX2
BDX2
V
SS
A19
A20
A22
B1
TX
N2
V
SS
C2
C1
D4
D3
D2
D1
E4
DV
HCNTL0
M3
N3
V
SS
DD
DV
V
SS
L13
V
SS
DV
DD
DD
A10
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
K10
K11
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
K4
D6
HD7
A11
A12
A13
A14
A15
L4
D7
D8
K12
K13
J10
M4
N4
D9
K5
D10
D11
D12
HD4
D13
D14
D15
HD5
E3
TOUT
EMU0
EMU1/OFF
TDO
J11
HCNTL1
BDR1
L5
C9
E2
J12
M5
N5
B9
CV
E1
J13
BCLKX0
BCLKX1
A9
DD
HAS
F4
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
K6
D8
V
SS
V
SS
F3
TDI
V
SS
L6
C8
F2
TRST
HINT/TOUT1
CVDD
M6
N6
B8
CV
F1
TCK
A8
DD
HCS
HR/W
READY
PS
G2
G1
G3
G4
H1
H2
H3
H4
J1
TMS
BFSX0
M7
N7
CV
B7
DD
V
SS
BFSX1
V
SS
A7
CV
HRDY
L7
HDS1
C7
DD
HPIENA
DV
K7
V
SS
D7
DD
DS
V
SS
V
SS
N8
HDS2
DV
A6
IS
CLKOUT
HD3
X1
HD0
BDX0
BDX1
IACK
HBIL
NMI
M8
L8
B6
DD
R/W
A0
C6
MSTRB
IOSTRB
MSC
XF
F10
E13
E12
E11
K8
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
D6
X2/CLKIN
RS
N9
A5
J2
M9
L9
B5
J3
D0
C5
HOLDA
IAQ
J4
D1
E10
D13
D12
D11
C13
C12
C11
B13
B12
INT0
INT1
INT2
INT3
K9
D5
K1
D2
N10
M10
L10
N11
M11
L11
N12
M12
A4
HOLD
BIO
K2
D3
B4
K3
D4
C4
MP/MC
L1
D5
CV
A3
DD
DV
L2
A16
HD1
B3
DD
V
SS
L3
V
SS
V
SS
CV
DD
C3
BDR2
M1
M2
A17
A18
RX
A21
A2
BFSRX2
V
SS
V
SS
B2
†
DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and the
DD
DD
SS
core CPU.
16
SPRS007D
November 2001 − Revised April 2004
Introduction
2.2.2 Pin Assignments for the PGE Package
The TMS320VC5407/TMS320VC5404PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are
shown in Figure 2−2.
1
108
107
106
105
104
103
102
101
100
99
V
A22
A18
A17
SS
2
3
V
SS
V
SS
4
DV
DD
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
5
A10
HD7
A11
A12
A13
A14
A15
6
7
8
9
10
11
12
13
14
15
16
98
CV
DD
97
HAS
96
V
V
95
HD3
CLKOUT
SS
SS
DD
94
CV
93
V
SS
HCS 17
HR/W 18
READY 19
PS 20
92
HPIENA
CV
91
DD
90
V
SS
89
TMS
DS 21
88
TCK
IS 22
87
TRST
R/W 23
86
TDI
MSTRB 24
IOSTRB 25
MSC 26
XF 27
HOLDA 28
IAQ 29
HOLD 30
BIO 31
MP/MC 32
85
TDO
84
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
83
82
81
80
79
78
77
DV
DD
33
V
SS
76
V
SS
34
DV
DD
75
BDR2 35
BFSRX2
BDX2
BCLKRX2
74
36
73
NOTE A: DV is the power supply for the I/O pins while CV is the power supply for the core CPU. V is the ground for both the I/O pins and
DD
DD
SS
the core CPU.
Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
17
November 2001 − Revised April 2004
SPRS007D
Introduction
2.3 Signal Descriptions
Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2−2. Signal Descriptions
TERMINAL
NAME
†
I/O
DESCRIPTION
EXTERNAL MEMORY INTERFACE PINS
A22
A21
A20
A19
A18
A17
A16
(MSB)
O/Z
Parallel address bus A22 (MSB) through A0 (LSB). The lower sixteen address pins—A0 to A15—are
multiplexed to address all external memory (program, data) or I/O, while the upper seven address
pins—A22 to A16—are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF is low.
A15
A14
A13
A12
A11
A10
A9
A15 (MSB)
I
These pins can be used to address internal memory via the HPI when the HPI16 pin
is high.
A14
A13
A12
A11
A10
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
(LSB)
A0
(LSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
(MSB)
I/O/Z
D15 (MSB) I/O
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins, D0 to D15,
are multiplexed to transfer data between the core CPU and external data/program
memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The
data bus also goes into the high-impedance state when OFF is low.
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
The data bus includes bus holders to reduce the static power dissipation caused by
floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the data bus is not being driven by the DSP, the bus
holders keep the pins at the logic level that was most recently driven. The data bus
holders of the DSP are disabled at reset, and can be enabled/disabled via the BH bit
of the BSCR.
D4
D4
D3
D3
D2
D2
D1
D1
D0
(LSB)
D0
(LSB)
INITIALIZATION, INTERRUPT, AND RESET PINS
IACK
O/Z
I
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching
the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when OFF
is low.
INT0
INT1
INT2
INT3
External user interrupt inputs. INT0−3 are prioritized and maskable via the interrupt mask register and
interrupt mode bit. The status of these pins can be polled by way of the interrupt flag register.
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location.
†
I = Input, O = Output, Z = High-impedance, S = Supply
18
SPRS007D
November 2001 − Revised April 2004
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
INITIALIZATION, INTERRUPT, AND RESET PINS (CONTINUED)
RS
I
Reset input. RS causes the DSP to terminate execution and causes a re-initialization of the CPU and
peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory.
RS affects various registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode select pin. If active low at reset, microcomputer mode is selected, and
the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is
driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program
space. This pin is only sampled at reset, and the MP/MC bit of the PMST register can override the mode
that is selected at reset.
MULTIPROCESSING AND GENERAL PURPOSE PINS
BIO
XF
I
Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor
executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline
for XC instruction, and all other instructions sample BIO during the read phase of the pipeline.
O/Z
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set
low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
MEMORY CONTROL PINS
DS
PS
IS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
accessing a particular external memory space. Active period corresponds to valid address information.
Placed into a high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state
when OFF is low.
MSTRB
READY
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access
to data or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the
high-impedance state when OFF is low.
Data ready input. READY indicates that an external device is prepared for a bus transaction to be
completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY
again. Note that the processor performs ready detection if at least two software wait states are
programmed. The READY signal is not sampled until the completion of the software wait states.
R/W
O/Z
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device. Normally in
read mode (high), unless asserted low when the DSP performs a write operation. Placed in high-impedance
state in hold mode. R/W also goes into the high-impedance state when OFF is low.
IOSTRB
I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an
I/O device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state
when OFF is low.
HOLD
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When
acknowledged by the C54x DSP, these lines go into high-impedance state.
HOLDA
O/Z
Hold acknowledge signal. HOLDA indicates that the DSP is in a hold state and that the address, data, and
control lines are in a high-impedance state, allowing the external memory interface to be accessed by other
devices. HOLDA also goes into the high-impedance state when is OFF low.
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state, and goes
inactive (high) at the beginning of the last software wait state. If connected to the ready input, MSC forces
one external wait state after the last internal wait state is completed. MSC also goes into the high
impedance state when OFF is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the
address bus and goes into the high-impedance state when OFF is low.
†
I = Input, O = Output, Z = High-impedance, S = Supply
C54x is a trademark of Texas Instruments.
19
November 2001 − Revised April 2004
SPRS007D
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
OSCILLATOR/TIMER PINS
CLKOUT
O/Z
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine
cycle is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when
OFF is low.
CLKMD1
CLKMD2
CLKMD3
I
I
Clock mode external/internal input signals. CLKMD1−CLKMD3 allows you to select and configure different
clock modes such as crystal, external clock, various PLL factors.
X2/CLKIN
Input pin to internal oscillator from the crystal. If the internal oscillator is not being used, an external clock
source can be applied to this pin. The internal machine cycle time is determined by the clock operating
mode pins (CLKMD1, CLKMD2 and CLKMD3).
X1
O
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision depended,
see Section 3.10 for additional information.)
TOUT
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT1
I/O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is a
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI, and TOUT1 is only
available when the HPI is disabled.
MULTICHANNEL BUFFERED SERIAL PORT PINS
BCLKR0
BCLKR1
BCLKRX2
I/O/Z
I
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver. BCLKRX2
is McBSP2 transmit AND receive clock.
BDR0
BDR1
BDR2
Serial data receive input.
BFSR0
BFSR1
BFSRX2
I/O/Z
I/O/Z
O/Z
I/O/Z
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over
BDR. BFSRX2 is McBSP2 transmit AND receive frame sync.
BCLKX0
BCLKX1
Transmit clock. BCLKX serves as the serial shift clock for the buffered serial port transmitter. The BCLKX
pins are configured as inputs after reset. BCLKX goes into the high-impedance state when OFF is low.
BDX0
BDX1
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted or when OFF is low.
BFSX0
BFSX1
Frame synchronization pulse for transmit output. The BFSX pulse initiates the transmit data process over
BDX. The BFSX pins are configured as inputs after reset. BFSX goes into the high-impedance state when
OFF is low.
UART
TX
RX
O
I
UART asynchronous serial transmit data output.
UART asynchronous serial receive data input.
†
I = Input, O = Output, Z = High-impedance, S = Supply
20
SPRS007D
November 2001 − Revised April 2004
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
HOST PORT INTERFACE PINS
A0−A15
I
These pins can be used to address internal memory via the HPI when the HPI16 pin is HIGH.
D0−D15
I/O
These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen
data pins, D0 to D15, are multiplexed to transfer data between the core CPU and external data/program
memory, I/O devices, or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not
outputting or when RS or HOLD is asserted. The data bus also goes into the high-impedance state when
OFF is low.
The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins.
The bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is
not being driven by the DSP, the bus holders keep the pins at the logic level that was most recently driven.
The data bus holders of the DSP are disabled at reset, and can be enabled/disabled via the BH bit of the
BSCR.
HD0−HD7
I/O/Z
Parallel bi-directional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin
is high. HD0−HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The
HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When
the HPI data bus is not being driven by the DSP, the bus holders keep the pins at the logic level that was most
recently driven. The HPI data bus holders are disabled at reset, and can be enabled/disabled via the HBH bit
of the BSCR.
HCNTL0
HCNTL1
I
I
I
I
I
Control inputs. These inputs select a host access to one of the three HPI registers. (Pullup only enabled when
HPIENA=0, HPI16=1)
HBIL
Byte identification input. Identifies first or second byte of transfer. (Pullup only enabled when HPIENA=0, invalid
when HPI16=1)
HCS
Chip select input. This pin is the select input for the HPI, and must be driven low during accesses.
(Pullup only enabled when HPIENA=0, or HPI16=1)
HDS1
HDS2
Data strobe inputs. These pins are driven by the host read and write strobes to control transfers.
(Pullup only enabled when HPIENA=0)
HAS
Address strobe input. Address strobe input. Hosts with multiplexed address and data pins require this input,
to latch the address in the HPIA register. (Pull-up only enabled when HPIENA=0)
HR/W
HRDY
I
Read/write input. This input controls the direction of an HPI transfer. (Pullup only enabled when HPIENA=0)
O/Z
Ready output. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into
the high-impedance state when OFF is low.
HINT
O/Z
I
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, this signal is driven
high. HINT can also be used for timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the
high-impedance state when OFF is low. (invalid when HPI16=1)
HPIENA
HPI enable input. This pin must be tied directly to DV to enable the HPI. An internal pulldown resistor is
DD
always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the DSP
is reset.
HPI16
I
HPI 16-bit Select Pin. This pin must be tied directly to DV to enable HPI16 mode. This input pin has an
DD
internal pulldown resistor which is always active. If HPI16 is left open or driven low, HPI16 mode is disabled.
The non-multiplexed mode allows hosts with separate address/data buses to access the HPI address range
via the 16 address pins A0−A15. 16-bit Data is also accessible through pins D0−D15. HOST-to-DSP and
DSP-to-HOST interrupts are not supported. There are no HPIC and HPIA registers in the non-multiplexed
mode since there are HCNTRL0,1 signals available.
†
I = Input, O = Output, Z = High-impedance, S = Supply
21
November 2001 − Revised April 2004
SPRS007D
Introduction
Table 2−2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
SUPPLY PINS
CV
DV
S
S
S
I
+V . Dedicated 1.5V power supply for the core CPU.
DD
DD
+V . Dedicated 3.3V power supply for I/O pins.
DD
DD
V
SS
Ground.
TCK
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The
changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TDI
I
IEEE standard 1149.1 test data input, pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
O/Z
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted
out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is
in progress. TDO also goes into the high-impedance state when OFF is low.
TMS
I
I
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the test access port (TAP) controller on the rising edge of TCK.
TRST
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of
the operations of the device. If TRST is not connected or driven low, the device operates in its functional
mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
EMU0
I/O/Z
I/O/Z
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of IEEE standard 1149.1 scan system. Should be pulled up to DV with a separate 4.7-kΩ resistor.
DD
EMU1/OFF
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from
the emulator system and is defined as input/output via IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers
into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Thus, for the OFF feature, the following conditions apply: TRST=low,
EMU0=high, EMU1/OFF = low. Should be pulled up to DV with a separate 4.7-kΩ resistor.
DD
†
I = Input, O = Output, Z = High-impedance, S = Supply
22
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
P, C, D, E Buses and Control Signals
40K RAM
Dual Access
Program/Data
128K Program
54X cLEAD
‡
ROM
†
MBus
GPIO
RHEA
Bridge
TI BUS
RHEA Bus
McBSP0
XIO
Enhanced XIO
McBSP1
McBSP2
UART
16HPI
16 HPI
xDMA
logic
RHEAbus
TIMER
APLL
JTAG
Clocks
†
16K for 5404
64K for 5404
‡
Figure 3−1. TMS320VC5407/TMS320VC5404 Functional Block Diagram
3.1 Memory
The 5407/5404 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.1.1 Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
23
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.1.2 Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are
within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:
•
•
•
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3 Extended Program Memory
The 5407/5404 uses a paged extended memory scheme in program space to allow access of up to 8192K
of program memory. In order to implement this scheme, the 5407/5404 includes several features which are
also present on C548/549/5410:
•
•
•
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC
Six extra instructions for addressing extended program space
Program memory in the 5407/5404 is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2 On-Chip ROM With Bootloader
The 5407 features a 128K-word × 16-bit on-chip maskable ROM that is mapped into program memory space,
but 16K words of which can also optionally be mapped into data memory. The 5404 features a 64K-word ×
16-bit on-chip maskable ROM that is mapped into program memory space.
Customers can also arrange to have the ROM of the 5407/5404 programmed with contents unique to any
particular application.
A bootloader is available in the standard 5407/5404 on-chip ROM. This bootloader can be used to
automatically transfer user code from an external source to anywhere in the program memory at power up.
If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the
on-chip ROM. This location contains a branch instruction to the start of the bootloader program.
The standard 5407/5404 devices provide different ways to download the code to accommodate various
system requirements:
•
•
•
•
•
•
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space, 8-bit or 16-bit mode
Serial boot from serial ports, 8-bit or 16-bit mode
UART boot mode
Host-port interface boot
Warm boot
24
SPRS007D
November 2001 − Revised April 2004
Functional Overview
The standard on-chip ROM layout is shown in Table 3−1.
Table 3−1. Standard On-Chip ROM Layout
†
ADDRESS RANGE
C000h−D4FFh
D500h−F7FFh
F800h−FBFFh
FC00h−FCFFh
FD00h−FDFFh
FE00h−FEFFh
FF00h−FF7Fh
FF80h−FFFFh
DESCRIPTION
ROM tables for the GSM EFR speech codec
Reserved
Bootloader
µ-Law expansion table
A-Law expansion table
Sine look-up table
†
Reserved
Interrupt vector table
†
In the 5407/5404 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h−FF7Fh in program space.
3.3 On-Chip RAM
The 5407 device contains 40K-words × 16-bit of on-chip dual-access RAM (DARAM), while the 5404 device
contains 16K-words x 16-bit of DARAM.
The DARAM is composed of five blocks of 8K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. The five blocks of DARAM on the 5407 are located in the
address range 0080h−9FFFh in data space, and can be mapped into program/data space by setting the OVLY
bit to one.
On the 5404, the two blocks of DARAM are located at 0080h−3FFFh in data space and can also be mapped
into data space by setting OVLY to one.
3.4 On-Chip Memory Security
The 5407/5404 device provides maskable options to protect the contents of on-chip memories. When the
ROM protect option is selected, no externally originating instruction can access the on-chip ROM; when the
RAM protect option is selected, HPI RAM is protected; HPI writes are not restricted, but HPI reads are
restricted to 2000h − 3FFFh.
25
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.5 Memory Maps
3.5.1 5407 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
Hex
Hex
0000
0000
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Memory-Mapped
Registers
005F
007F
0080
007F
0080
0060
007F
0080
Scratch-Pad
RAM
On-Chip
DARAM0−4
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−2
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−4
(40K x 16-bit)
5FFF
6000
9FFF
A000
9FFF
A000
BFFF
C000
External
On-Chip ROM
(40K x 16-bit)
External
On-Chip
PDROM0−1
(DROM=1)
or
External
(DROM=0)
FF7F
FF80
FEFF
FF00
FF7F
FF80
FFFF
Interrupts
(External)
Reserved
Interrupts
(On-Chip)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Figure 3−2. 5407 Program and Data Memory Map
Hex
7F0000
Hex
010000
Program
Program
Hex
020000
Hex
030000
Hex
040000
Program
Program
Program
†
†
†
†
†
External
External
External
External
External
7F7FFF
7F8000
017FFF
018000
027FFF
028000
037FFF
038000
047FFF
048000
......
On-Chip
ROM
On-Chip
ROM
On-Chip
ROM
External
External
03DFFF
03E000
03FFFF
External
7FFFFF
04FFFF
01FFFF
02FFFF
Page 1
XPC=1
Page 2
XPC=2
Page 127
XPC=7Fh
Page 3
XPC=3
Page 4
XPC=4
†
The lower 32K words of pages 1 through 127 are only available when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip memory
is mapped to the lower 32K words of all program space pages.
Figure 3−3. 5407 Extended Program Memory Map
26
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3.5.2 5404 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
Hex
Hex
0000
0000
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Memory-Mapped
Registers
005F
0060
007F
0080
Scratch-Pad
RAM
007F
0080
007F
0080
On-Chip
DARAM0−1
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−1
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−1
(32K x 16-bit)
3FFF
4000
3FFF
4000
3FFF
4000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
5FFF
6000
Reserved
7FFF
8000
9FFF
A000
9FFF
A000
On-Chip ROM
(32K x 16-bit)
External
BFFF
C000
External
FEFF
FF00
FF7F
PDROM0−1
Reserved
FF7F
FF80
(DROM = 1)
or
FF80
Interrupts
(External)
Interrupts
(On-Chip)
External
(DROM = 0)
FFFF
FFFF
FFFF
MP/MC= 0
(Microcomputer Mode)
MP/MC= 1
(Microprocessor Mode)
Figure 3−4. 5404 Program and Data Memory Map
27
November 2001 − Revised April 2004
SPRS007D
Functional Overview
Hex
7F0000
Hex
010000
Program
Program
Hex
020000
Hex
030000
Hex
040000
Program
Program
Program
†
†
†
†
†
External
External
External
External
External
7F3FFF
7F4000
013FFF
014000
023FFF
024000
033FFF
034000
043FFF
044000
......
Reserved
Reserved
Reserved
Reserved
Reserved
(OVLY = 1)
(OVLY = 1)
(OVLY = 1)
(OVLY = 1)
(OVLY = 1)
External
(OVLY = 0)
External
(OVLY = 0)
External
(OVLY = 0)
External
(OVLY = 0)
External
(OVLY = 0)
017FFF
018000
027FFF
028000
037FFF
038000
047FFF
048000
7F7FFF
7F8000
On-Chip
ROM
Reserved
External
External
External
Reserved
03DFFF
03E000
03FFFF
01FFFF
7FFFFF
02FFFF
04FFFF
Page 1
XPC=1
Page 2
XPC=2
Page 127
XPC=7Fh
Page 3
XPC=3
Page 4
XPC=4
†
The lower 16K words of pages 1 through 127 are only available when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip memory
is mapped to the lower 16K words of all program space pages.
Figure 3−5. 5404 Extended Program Memory Map
3.5.3 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the
appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
28
SPRS007D
November 2001 − Revised April 2004
Functional Overview
15
IPTR
R/W-1FF
7
6
5
4
3
2
1
0
IPTR
MP/MC
OVLY
R/W-0
AVIS
R/W-0
DROM
R/W-0
CLKOFF
R/W-0
SMUL
R/W-0
SST
MP/MC Pin
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−6. Processor Mode Status (PMST) Register
Table 3−2. Processor Mode Status (PMST) Register Bit Fields
BIT
RESET
FUNCTION
VALUE
NO.
NAME
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these
bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The
RESET instruction does not affect this field.
15−7
IPTR
1FFh
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.
-
-
MP/MC = 0: The on-chip ROM is enabled and addressable.
MP/MC = 1: The on-chip ROM is not available.
MP/MC
pin
6
5
MP/MC
OVLY
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This
pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can
also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
-
-
OVLY = 0: The on-chip RAM is addressable in data space but not in program space.
0
OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses
0h to 7Fh), however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
-
AVIS = 0: The external address lines do not change with the internal program address. Control and
data lines are not affected and the address bus is driven with the last address on the bus.
4
3
AVIS
0
0
-
AVIS = 1: This mode allows the internal program address to appear at the pins of the 5407/5404 so
that the internal program address can be traced. Also, it allows the interrupt vector to be decoded
in conjunction with IACK when the interrupt vectors reside on on-chip memory.
Data ROM. DROM enables on-chip ROM to be mapped into data space. The DROM bit values are:
-
-
DROM = 0: The on-chip ROM is not mapped into data space.
DROM
DROM = 1: A portion of the on-chip ROM is not mapped into data space.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
2
1
0
CLKOFF
SMUL
SST
0
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
N/A
N/A
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
29
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.6 On-Chip Peripherals
The 5407/5404 device has the following peripherals:
•
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
A UART with an integrated baud rate generator
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the 5407/5404 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5407/5404.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3−7 and described in Table 3−3.
15
14
12
11
9
8
XPA
I/O
DATA
DATA
R/W-0
R/W-111
R/W-111
6
5
3
2
0
DATA
PROGRAM
R/W-111
PROGRAM
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−7. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
30
SPRS007D
November 2001 − Revised April 2004
Functional Overview
Table 3−3. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
15
XPA
0
I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14−12
11−9
8−6
I/O
111
111
111
Upper data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
Lower data space. The field value (0−7) corresponds to the base number of wait states for external
data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx8000 − xxFFFFh
XPA = 1: 400000h − 7FFFFFh
5−3
2−0
Program
Program
111
111
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Lower program space. The field value (0−7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx0000 − xx7FFFh
XPA = 1: 000000 − 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3−8 and
described in Table 3−4.
15
Reserved
R/W-0
1
0
Reserved
R/W-0
SWSM
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−8. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3−4. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NAME
RESET
VALUE
FUNCTION
NO.
15−1
Reserved
0
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
31
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.6.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5407/5404 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3−9 and are described in Table 3−5.
15
14
13
12
11
CONSEC
R/W-1
DIVFCT
R/W-11
IACKOFF
R/W-1
Reserved
R
3
2
1
0
Reserved
R
Reserved
R
HBH
BH
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−9. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
Table 3−5. Bank-Switching Control Register (BSCR) Fields
RESET
VALUE
BIT
NAME
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
CONSEC = 0: Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
†
15
CONSEC
1
CONSEC = 1:
Consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
DIVFCT = 00: CLKOUT is not divided.
13−14 DIVFCT
11
DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
IACKOFF = 0: The IACK signal output off function is disabled.
IACKOFF = 1: The IACK signal output off function is enabled.
Reserved
12
IACKOFF
1
11−3
Reserved
HBH
−
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
HBH = 0:
The bus holder is disabled except when HPI16=1.
2
0
HBH = 1:
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
BH = 0:
BH = 1:
The bus holder is disabled.
1
0
BH
0
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
Reserved
−
Reserved
†
For additional information, see Section 3.11 of this document.
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Functional Overview
The 5407/5404 has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address
used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)
signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new
address. The contents of the internal register are replaced with the MSB for the read of the current address.
If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
•
•
•
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
3.6.3 Bus Holders
The 5407/5404 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers
of the address bus (A[17−0]), data bus (D[15−0]), and the HPI data bus (HD[7−0]). Bus keeper
enabling/disabling is described in Table 3−5.
Table 3−6. Bus Holder Control Bits
HPI16 PIN
BH
0
HBH
D[15−0]
OFF
OFF
ON
A[17−0]
OFF
OFF
OFF
OFF
OFF
ON
HD[7−0]
OFF
ON
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
OFF
ON
1
ON
0
OFF
OFF
ON
ON
0
ON
1
OFF
ON
ON
1
ON
ON
3.7 Parallel I/O Ports
The 5407/5404 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 5407/5404 can
interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding
circuits.
3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The 5407/5404 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard
8-bit HPI found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The 5407/5404 HPI can be used
to interface to an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface
to external devices in program/data/IO spaces), the 5407/5404 HPI can be configured as an HPI16 to interface
to a 16-bit host. This configuration can be accomplished by connecting the HPI16 pin to logic “1”.
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November 2001 − Revised April 2004
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Functional Overview
When the HPI16 pin is connected to a logic “0”, the 5407/5404 HPI is configured as an HPI8. The HPI8 is an
8-bit parallel port for interprocessor communication. The features of the HPI8 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and C54x interrupt capability
Multiple data strobes and control pins for interface flexibility
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — the HPI address register (HPIA), the HPI data register (HPID),
and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the
HPIC register is accessible by both the host and the 5407/5404.
Enhanced features:
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
The HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The
HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master
of the interface. Some of the features of the HPI16 include:
•
•
•
•
16-bit bidirectional data bus
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
Only nonmultiplexed address/data modes are supported
18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal
extended address pages)
•
•
HRDY signal to hold off host accesses due to DMA latency
The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP.
NOTE: Only the nonmultiplexed mode is supported when the 5407/5404 HPI is configured as
a HPI16 (see Figure 3−10).
The 5407/5404 HPI functions as a slave and enables the host processor to access the on-chip memory. A
major enhancement to the 5407/5404 HPI over previous versions is that it allows host access to the entire
on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times
and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to
the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are
always synchronized to the 5407/5404 clock, an active input clock (CLKIN) is required for HPI accesses during
IDLE states, and host accesses are not allowed while the 5407/5404 reset pin is asserted.
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Functional Overview
3.7.2 HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 23-bit HA address bus. The
host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access
with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register
is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate
a DMA read or write access. Figure 3−10 shows a block diagram of the HPI16 in nonmultiplexed mode.
HOST
HPI16
PPD[15:0]
DATA[15:0]
HPID[15:0]
HINT
DMA
Address[22:0]
HCNTL0
V
CC
HCNTL1
HBIL
HAS
R/W
HR/W
54xx
CPU
Data Strobes
HDS1, HDS2, HCS
HRDY
READY
Figure 3−10. Host-Port Interface — Nonmultiplexed Mode
Address (Hex)
0000
Reserved
005F
0060
DARAM0
1FFF
2000
DARAM1
3FFF
4000
†
DARAM2
5FFF
6000
†
DARAM3
7FFF
8000
†
DARAM4
9FFF
A000
Reserved
FFFF
†
Reserved on 5404 devices
Figure 3−11. HPI Memory Map
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Functional Overview
3.8 Multichannel Buffered Serial Ports (McBSPs)
The 5407/5404 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow
direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs provide:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSPs have the following capabilities:
•
Direct interface to:
−
−
−
−
−
−
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
IIS-compliant devices
Serial peripheral interface
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and
BCLKR, connect the control and data paths to external devices. The implemented pins can be programmed
as general-purpose I/O pins if they are not used for serial communication. Note that on McBSP2, the transmit
and receive clocks and the transmit and receive frame sync have been combined.
The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for
transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the data
receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written
to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR
pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then
copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data
communications simultaneously.
Control information in the form of clocking and frame synchronization is communicated by way of BCLKX,
BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers
accessible via the internal peripheral bus.
The control block consists of internal clock generation, frame synchronization signal generation, and their
control, and multichannel selection. This control block sends notification of important events to the CPU and
DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT.
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmitted data is encoded according to the specified companding law and
received data is decoded to 2s complement format.
The sample rate generator provides the McBSP with several means of selecting clocking and framing for both
the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently.
36
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November 2001 − Revised April 2004
Functional Overview
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can
be enabled.
15
10
9
8
Reserved
R
XMCME
R/W
XPBBLK
R/W
7
6
5
4
2
1
0
XPBBLK
R/W
XPABLK
R/W
XCBLK
R
XMCM
R/W
LEGEND: R = Read, W = Write
Figure 3−12. Multichannel Control Register (MCR1)
15
10
9
8
Reserved
R
RMCME
R/W
RPBBLK
R/W
7
6
5
4
2
1
Reserved
R
0
RPBBLK
R/W
RPABLK
R/W
RCBLK
R
RMCM
R/W
LEGEND: R = Read, W = Write
Figure 3−13. Multichannel Control Register (MCR2)
The 5407/5404 McBSP has two working modes:
•
•
In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the
normal 32-channel selection is enabled (default).
In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control
register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME = 1, twelve
new registers ((R/X)CERC − (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by
the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured
to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.
Although the BCLKS pin is not available on the 5407/5404 PGE and GGU packages, the 5407/5404 is capable
of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for
external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
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November 2001 − Revised April 2004
SPRS007D
Functional Overview
15
14
6
13
12
11
10
9
8
Reserved
R/W
XIOEN
R/W
RIOEN
R/W
FSXM
R/W
FSRM
R/W
CLKXM
R/W
CLKRM
R/W
7
5
4
3
2
1
0
SCLKME
R/W
CLKS STAT
R/W
DX STAT
R/W
DR STAT
R/W
FSXP
R/W
FSRP
R/W
CLKXP
R/W
CLKRP
R/W
LEGEND: R = Read, W = Write
Figure 3−14. Pin Control Register (PCR)
The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value
and the SCLKME bit value as shown in Table 3−7.
Table 3−7. Sample Rate Input Clock Selection
SCLKME
CLKSM
SAMPLE RATE CLOCK MODE
0
0
Reserved (CLKS pin unavailable)
0
1
1
1
0
1
CPU clock
BCLKR
BCLKX
When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or the
CLKS pin (not bonded out on the 5407/5404 device package) as the sample rate input clock. Setting the
SCLKME bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate
input clock.
When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically
disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the input of the
sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate
generator output by setting the CLKXM and CLKRM bits of the pin configuration register (PCR) to 1. Note that
the sample rate generator output will only be driven on the BCLKX pin since the BCLKR output buffer is
automatically disabled.
The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency,
see Section 5.14.
3.9 Hardware Timers
The 5407/5404 device features two 16-bit timing circuits with 4-bit prescalers. The timer counters are
decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.
Both timers can be use to generate interrupts to the CPU, however, the second timer (Timer1) has its interrupt
combined with external interrupt 3 (INT3) in the interrupt flag register. Therefore, to use the Timer1 interrupt,
the INT3 input should be disabled (tied high), and to use the INT3 input, the timer should be disabled (placed
in reset).
Since the Timer1 output is multiplexed externally with the HINT output, the HPI must be disabled (HPIENA
input pin = 0) if the Timer1 output is to be used. The Timer1 output also has a dedicated enable bit in the
General Purpose I/O Control Register (GPIOCR) located at data memory address 003Ch. If the external
Timer1 output is to be used, in addition to disabling the HPI, the TOUT1 bit in the GPIOCR must also be set
to 1.
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Functional Overview
3.10 Clock Generator
The clock generator provides clocks to the 5407/5404 device, and consists of a phase-locked loop (PLL)
circuit. The clock generator requires a reference clock input, which can be provided from an external clock
source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 5407/5404
device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference
clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.
The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
5407/5404 device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5407/5404 to enable the internal oscillator.
•
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note
that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state
of the CLKMD1 − CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference
Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options
are shown in Table 3−8.
Table 3−8. Clock Mode Settings at Reset
CLKMD RESET
†
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
VALUE
0000h
9007h
4007h
1007h
F007h
F000h
0000h
—
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
0
0
0
1
1
1
1/2 (PLL and oscillator disabled)
PLL x 10
PLL x 5
PLL x 2
PLL x 1
1/4 (PLL disabled)
1/2 (PLL disabled)
Reserved
†
The external CLKMD1−CLKMD3 pins are sampled to determine the desired clock generation mode
while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal
clock mode register in software.
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November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.11 Enhanced External Parallel Interface (XIO2)
The 5407/5404 external interface has been redesigned to include several improvements, including:
simplification of the bus sequence, more immunity to bus contention when transitioning between read and
write operations, the ability for external memory access to the DMA controller, and optimization of the
power-down modes.
The bus sequence on the 5407/5404 still maintains all of the same interface signals as on previous 54x
devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed
of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
54x devices is available.
Figure 3−15 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 3−15 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3−15. Nonconsecutive Memory Read and I/O Read Bus Sequence
40
SPRS007D
November 2001 − Revised April 2004
Functional Overview
Figure 3−16 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown
in Figure 3−16 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads
performed.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
READ
READ
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3−16. Consecutive Memory Read Bus Sequence (n = 3 reads)
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November 2001 − Revised April 2004
SPRS007D
Functional Overview
Figure 3−17 shows the bus sequence for all memory writes and I/O writes. The accesses shown in
Figure 3−17 always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
WRITE
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 3−17. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more
information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000 DSP
platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature
is automatic, requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching
cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program up to 14 wait states
through software (see Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing
down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral
devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow
down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides
a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled
through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3−5).
3.12 DMA Controller
The 5407/5404 direct memory access (DMA) controller transfers data between points in the memory map
without intervention by the CPU. The DMA allows movements of data to and from internal program/data
memory, internal peripherals (such as the McBSPs, but not the UART), or external memory devices to occur
in the background of CPU operation. The DMA has six independent programmable channels, allowing six
different contexts for DMA operation.
TMS320C5000 is a trademark of Texas Instruments.
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SPRS007D
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Functional Overview
3.12.1 Features
The DMA has the following features:
•
•
•
•
•
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
be post-decremented, or be adjusted by a programmable value.
•
•
•
Each read or write internal transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2 DMA External Access
The 5407/5404 DMA supports external accesses to extended program, extended data, and extended I/O
memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can
be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external
writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive mode
(CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests.
•
Only two channels are available for external accesses. (One for external reads and one for external
writes.)
•
•
•
•
•
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from the peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external-to-external transfers.
The DMA does not support synchronized external transfers.
15
14
13
12
11
10
2
8
AUTOINIT
DINM
IMOD
CTMOD
SLAXS
SIND
1
7
6
5
4
0
DMS
DLAXS
DIND
DMD
Figure 3−18. DMA Transfer Mode Control Register (DMMCRn)
These new bit fields were created to allow the user to define the space-select for the DMA (internal/external).
Also, a new extended destination data page (XDSTDP[6:0], subaddress 029h) and extended source data
page (XSRCDP[6:0], subaddress 028h) have been created. The functions of the DLAXS and SLAXS bits are
as follows:
DLAXS(DMMCRn[5]) Destination
SLAXS(DMMCRn[11]) Source
0 = No external access (default internal)
1 = External access
0 = No external access (default internal)
1 = External access
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November 2001 − Revised April 2004
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Functional Overview
Table 3−9 lists the DMD bit values and their corresponding destination space.
Table 3−9. DMD Section of the DMMCRn Register
DMD
DESTINATION SPACE
00
PS
DS
01
10
I/O
11
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program
address map. When the cells are mapped into program space, the device automatically accesses them when
their addresses are within bounds. When the address generation logic generates an address outside its
bounds, the device automatically generates an external access.
Two new registers are added to the 5407/5404 DMA to support DMA accesses to/from DMA extended data
memory, page 1 to page 127.
•
•
The DMA extended source data page register (XSRCDP[6:0]) is located at subbank address 028h.
The DMA extended destination data page register (XDSTDP[6:0]) is located at subbank address 029h.
3.12.3 DMA Memory Map
The DMA memory map, shown in Figure 3−19, allows the DMA transfer to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
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Functional Overview
Program
Program
Reserved
Hex
xx0000
Hex
0000
005F
0060
On-Chip
DARAM0
8K Words
DLAXS = 0
SLAXS = 0
1FFF
2000
On-Chip
DARAM1
8K Words
3FFF
4000
On-Chip
†
DARAM2
8K Words
5FFF
6000
On-Chip
†
DARAM3
8K Words
7FFF
8000
Reserved
On-Chip
†
DARAM4
8K Words
9FFF
A000
Reserved
xxFFFF
FFFF
Page 0
Page 1 − 127
†
Reserved on the 5404
Figure 3−19. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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Functional Overview
Data Space (0000 − 005F)
Data Space
I/O Space
Hex
Hex
0000
0000
001F
0020
0021
0022
0000
Reserved
Data Space
(See Breakout)
DRR20
DRR10
DXR20
005F
0060
0023
0024
002F
0030
0031
0032
0033
DXR10
Scratch-Pad
RAM
Reserved
DRR22
DRR12
DXR22
DXR12
007F
0080
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
0034
3FFF
4000
On-Chip
†
DARAM2
Reserved
8K Words
Reserved
5FFF
6000
On-Chip
†
DARAM3
8K Words
003F
0040
0041
0042
0043
0044
7FFF
8000
DRR21
On-Chip
†
DRR11
DXR21
DXR11
DARAM4
8K Words
9FFF
A000
Reserved
Reserved
005F
FFFF
FFFF
†
Reserved on the 5404
Figure 3−20. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
•
Repetitive operation:The CPU does not preload the reload register with new values for each block transfer
but only loads them on the first block transfer.
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Functional Overview
The 5407/5404 DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now
has its own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0,
DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and
DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in
Figure 3−21.
15
14
13
5
8
FREE
AUTOIX
DPRC[5:0]
7
6
0
INT0SEL
DE[5:0]
Figure 3−21. DMPREC Register
Table 3−10. DMA Reload Register Selection
AUTOIX
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
0 (default)
1
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
3.12.7 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
3.12.8 DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.12.9 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer
mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index
DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element
transfer is the last in the current frame. The normal adjustment value (element index) is contained in the
element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame,
is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfers.
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Functional Overview
3.12.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available
modes are shown in Table 3−11.
Table 3−11. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi frame
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multi frame
Either
Either
No interrupt generated
3.12.11 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events
and the DSYN values are shown in Table 3−12.
Table 3−12. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
†
UART
1000b
1001b
1010b
1011b
1100b
1101b
1110b
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 0 interrupt event
External interrupt 3
Timer 1 interrupt event
1111b
†
Note that the UART DMA synchronization event is usable as a synchronization event only, and is not usable
for transferring data to or from the UART. The DMA cannot be used to transfer data to or from the UART.
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5407/5404 is reset, the interrupts from these three DMA channels are deselected. The INT0SEL bit field
in the DMPREC register can be used to select these interrupts, as shown in Table 3−13.
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Functional Overview
Table 3−13. DMA/CPU Channel Interrupt Selection
INT0SEL VALUE
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
00b (reset)
01b
BXINT1
DMAC3
DMAC3
BXINT2
DMAC2
10b
DMAC1
DMAC2
11b
Reserved
3.13 Universal Asynchronous Receiver/Transmitter (UART)
The UART peripheral is based on the industry-standard TL16C550B asynchronous communications element,
which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up
(character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves
the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and
transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time.
The UART includes control capability and a processor interrupt system that can be tailored to minimize software
management of the communications link.
The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors from
1 to 65535 and producing a 16× reference clock for the internal transmitter and receiver logic. See Section 5.16
for detailed timing specifications for the UART.
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Functional Overview
S
e
l
e
c
t
Receiver
FIFO
8
Receiver
Shift
Register
RX
Data
Bus
Buffer
Receiver
Buffer
Register
Peripheral
Bus
8
Receiver
Timing and
Control
Line
Control
Register
Divisor
Latch (LS)
Baud
Generator
Divisor
Latch (MS)
Transmitter
Timing and
Control
Line
Status
Register
Transmitter
FIFO
S
e
l
e
c
t
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
TX
Modem
Control
Register
Control
Logic
Interrupt
Enable
Register
Interrupt
Control
Logic
8
Interrupt
Identification
Register
8
INTRPT
(To CPU)
FIFO
Control
Register
Figure 3−22. UART Functional Block Diagram
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Functional Overview
Table 3−14. UART Reset Functions
REGISTER/SIGNAL
Interrupt enable register
RESET CONTROL
RESET STATE
Master reset
All bits cleared (0−3 forced and 4−7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4−5 are
permanently cleared
Interrupt identification register
Master reset
FIFO control register
Line control register
Master reset
Master reset
All bits cleared
All bits cleared
Modem control register
Line status register
Master reset
All bits cleared (6−7 permanent)
Master reset
Bits 5 and 6 are set; all other bits are cleared
Reserved register
Master reset
Indeterminate
High
SOUT
Master reset
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
Scratch register
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
Master reset
Low
Low
Low
No effect
No effect
No effect
No effect
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
Master reset
Master reset
Master reset
MR/FCR1−FCR0/∆FCR0 All bits cleared
MR/FCR2−FCR0/∆FCR0 All bits cleared
XMIT FIFO
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November 2001 − Revised April 2004
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Functional Overview
3.13.1 UART Accessible Registers
The system programmer has access to and control over any of the UART registers that are summarized in
Table 3−14. These registers control UART operations, receive data, and transmit data. Descriptions of these
registers follow Table 3−15. See Table 3−24 for more information on peripheral memory mapped registers.
Table 3−15. Summary of Accessible Registers
UART SUBBANK ADDRESS
0
0
0 (DLAB = 1)
or 8
1
1 (DLAB = 1)
or 9
2
2
3
4
5
6
7
(DLAB = 0)
(DLAB = 0)
(DLAB = 0)
Receiver
Buffer
Register
(Read
Transmitter
Holding
Register
(Write
Interrupt
Ident.
Register
(Read
FIFO
Control
Register
(Write
BIT
NO.
Divisor
Latch
(LSB)
Interrupt
Enable
Register
Divisor
Latch
(MSB)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Re-
served
Register
Scratch
Register
Only)
Only)
Only)
Only)
RBR
THR
DLL
IER
DLM
IIR
FCR
LCR
MCR
LSR
RSV
SCR
Enable
Received
Data
Available
Interrupt
(ERBI)
Word
Length
Select
Bit 0
0 if
Interrupt
Pending
Data
Ready
(DR)
FIFO
Enable
†
0
Data Bit 0
Data Bit 0
Bit 0
Bit 8
X
X
Bit 0
(WLS0)
Enable
Transmitter
Holding
Register
Empty
Word
Length
Select
Bit 1
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Overrun
Error
(OE)
1
2
Data Bit 1
Data Bit 2
Data Bit 1
Data Bit 2
Bit 1
Bit 2
Bit 9
X
X
X
X
Bit 1
Bit 2
Interrupt
(ETBEI)
(WLS1)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Number
of
Stop Bits
(STB)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Parity
Error
(PE)
Bit 10
Interrupt
ID
Parity
Enable
(PEN)
Framing
Error
(FE)
‡
0
‡
0
3
4
Data Bit 3
Data Bit 4
Data Bit 3
Data Bit 4
Bit 3
Bit 4
Bit 11
Bit 12
X
X
X
Bit 3
Bit 4
§
Bit 3
Even
Parity
Select
(EPS)
Break
Interrupt
(BI)
0
0
Reserved
Reserved
Loop
Transmitter
Holding
Register
(THRE)
Stick
Parity
‡
0
5
6
Data Bit 5
Data Bit 6
Data Bit 5
Data Bit 6
Bit 5
Bit 6
0
0
Bit 13
Bit 14
0
X
X
Bit 5
Bit 6
Receiver
Trigger
(LSB)
Transmitter
Empty
(TEMT)
FIFOs
Break
Control
0
§
Enabled
Divisor
Latch
Access
Bit
Error in
RCVR
Receiver
Trigger
(MSB)
FIFOs
7
Data Bit 7
0
Data Bit 7
0
Bit 7
0
0
0
Bit 15
0
0
0
X
0
Bit 7
0
§
Enabled
§
FIFO
(DLAB)
8 − 15
0
0
0
0
†
‡
§
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Must always be written as zero.
These bits are always 0 in the TL16C450 mode.
NOTE: X = Don’t care for write, indeterminate on read.
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Functional Overview
3.13.2 FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
•
•
•
Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
•
•
Bits 3, 4, and 5: These three bits are reserved for future use.
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 3−16).
Table 3−16. Receiver FIFO Trigger Level
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
BIT 7
BIT 6
0
0
1
1
0
1
0
1
01
04
08
14
3.13.3 FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of
160 ms at a 300 baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).
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November 2001 − Revised April 2004
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Functional Overview
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor
reads one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received
or after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3−0) = 2] occurs when the transmit FIFO is empty.
It is cleared [IIR (3−0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit
FIFO while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time
that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
3.13.4 FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the UART in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•
•
LSR0 is set as long as there is one byte in the receiver FIFO.
LSR1 − LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
•
•
•
LSR5 indicates when the THR is empty.
LSR6 indicates that both the THR and TSR are empty.
LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
3.13.5 Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (refer to Table 3−17) and enables INTRPT in response to
an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table 3−15 and are described in the following bullets.
•
•
•
•
Bit 0: When set, this bit enables the received data available interrupt.
Bit 1: When set, this bit enables the THRE interrupt.
Bit 2: When set, this bit enables the receiver line status interrupt.
Bits 3 through 7: These bits are not used
3.13.6 Interrupt Identification Register (IIR)
The UART has an on-chip interrupt generation and prioritization capability that permits flexible communication
with the CPU.
The UART provides three prioritized levels of interrupts:
•
•
•
Priority 1 − Receiver line status (highest priority)
Priority 2 − Receiver data ready or receiver character time-out
Priority 3 − Transmitter holding register empty
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Functional Overview
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3−15
and described in Table 3−17. Detail on each bit is as follows:
•
Bit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending If bit 0 is set, no interrupt is pending.
•
•
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3−15
Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
•
•
Bits 4 and 5: These two bits are not used (always cleared).
Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
Table 3−17. Interrupt Control Functions
INTERRUPT
IDENTIFICATION REGISTER
PRIORITY
LEVEL
INTERRUPT RESET
METHOD
INTERRUPT TYPE
INTERRUPT SOURCE
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
0
1
1
0
None
1
None
None
None
Overrun error, parity error,
framing error, or break interrupt
Receiver line status
Read the line status register
Receiver data available in the
0
1
0
0
2
Received data available TL16C450 mode or trigger level Read the receiver buffer register
reached in the FIFO mode
No characters have been
removed from or input to the
Character time-out
indication
receiver FIFO during the last four
character times, and there is at
least one character in it during
this time
1
1
0
0
2
Read the receiver buffer register
Read the interrupt identification
register (if source of interrupt) or
writing into the transmitter
holding register
Transmitter holding
register empty
Transmitter holding register
empty
0
0
1
0
3
3.13.7 Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3−15 and described in the following bulleted list.
•
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 3−18.
Table 3−18. Serial Character Word Length
BIT 1
BIT 0
WORD LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
•
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit
regardless of the number of stop bits selected. The number of stop bits generated in relation to word length
and bit 2 are shown in Table 3−19.
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November 2001 − Revised April 2004
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Functional Overview
Table 3−19. Number of Stop Bits Generated
WORD LENGTH SELECTED
BY BITS 1 AND 2
NUMBER OF STOP
BITS GENERATED
BIT 2
0
1
1
1
1
Any word length
5 bits
1
1 1/2
2
6 bits
7 bits
2
8 bits
2
•
•
•
•
•
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked
as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
If bit 5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
affect on the transmitter logic; it only effects SOUT.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
3.13.8 Line Status Register (LSR)†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3−15 and described in the following bulleted list.
•
Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
‡
•
Bit 1 : This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in
the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
‡
•
•
Bit 2 : This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO
to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
‡
Bit 3 : This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character
did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error
is revealed to the CPU when its associated character is at the top of the FIFO. The UART tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next
start bit. The UART samples this start bit twice and then accepts the input data.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
56
SPRS007D
November 2001 − Revised April 2004
Functional Overview
‡
•
•
Bit 4 : This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input
was held low for longer than a full-word transmission time. A full-word transmission time is defined as the
total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the UART is ready
to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated.
THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the
loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared
when at least one byte is written to the transmit FIFO.
•
•
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
Bit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.
In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is
cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
3.13.9 Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device. On the UART
peripheral, only one bit is active in this register
•
Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the UART. When LOOP
is set, the following occurs:
−
−
−
The transmitter SOUT is set high.
The receiver SIN is disconnected.
The output of the TSR is looped back into the receiver shift register input.
3.13.10 Programmable Baud Generator
The UART contains a programmable baud generator that takes a clock input in the range between DC and
16
16 MHz and divides it by a divisor in the range between 1 and (2 −1). The output frequency of the baud
generator is sixteen times (16×) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When
either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 3−20 and Table 3−21 illustrate the use of the baud generator with clock frequencies of 1.8432 MHz and
3.072 MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected clock frequency.
‡
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
57
November 2001 − Revised April 2004
SPRS007D
Functional Overview
NOTE: The clock rates in Table 3−20 and Table 3−21 are shown, for example only, to illustrate
the relationship of clock rate and divisor value, to baud rate and baud rate error. Typically,
higher clock rates will normally be used, and error values will differ accordingly.
Table 3−20. Baud Rates Using a 1.8432-MHz Clock
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
2304
1536
1047
857
768
384
192
96
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
Table 3−21. Baud Rates Using a 3.072-MHz Clock
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
0.312
80
53
0.628
1.23
40
27
20
10
5
58
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3.13.10.1 Receiver Buffer Register (RBR)
The UART receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16× receiver clock. Receiver section control is a function of the UART line control
register.
The UART RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt
is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
3.13.10.2 Scratch Register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other UART operation.
3.13.10.3 Transmitter Holding Register (THR)
The UART transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Transmitter section control is a function of the UART line control register.
The UART THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the
transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
3.14 General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the 5407/5404 has pins that can be configured for
general-purpose I/O. These pins are:
•
16 McBSP pins — BCLKX0/1, BCLKR0/1, BDR0/1/2, BFSX0/1, BFSR0/1, BDX0/1/2, BCLKRX2,
BFSRX2
•
8 HPI data pins — HD0−HD7
The general-purpose I/O function of these pins is only available when the primary pin function is not required.
3.14.1 McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose
inputs or outputs. For more details on this feature, see Section 3.8.
3.14.2 HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the
HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped
registers are used to control the GPIO function of the HPI data pins — the general-purpose I/O control register
(GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3−23.
15
14
8
TOUT1
R/W-0
Reserved
0
7
4
3
0
DIR7
R/W-0
DIR6
DIR5
DIR4
R/W-0
DIR3
R/W-0
DIR2
DIR1
DIR0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−23. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
59
November 2001 − Revised April 2004
SPRS007D
Functional Overview
The direction bits (DIRx) are used to configure HD0−HD7 as inputs or outputs (0 = input, 1 = output).
Bit 15 of the GPIOCR is also used as the Timer1 output enable bit, TOUT1. The TOUT1 bit enables or disables
the Timer1 output on the HINT/TOUT1 pin. If TOUT1 = 0, the Timer1 output is not available externally; if
TOUT1 = 1, the Timer1 output is driven on the HINT/TOUT1 pin. Note also that the Timer1 output is only
available when the HPI is disabled (HPIENA input pin = 0).
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
Figure 3−24. When read, these bits reflect the state of the input pins, and when written, determine the state
of outputs.
15
8
Reserved
0
7
4
3
0
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−24. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
3.15 Device ID Register
A read-only memory-mapped register has been added to the 5407/5404 to allow user application software
to identify on which device the program is being executed.
15
8
Chip ID
R
7
4
3
0
Chip Revision
R
SUBSYSID
R
LEGEND: R = Read, W = Write
Figure 3−25. Device ID Register (CSIDR) [MMR Address 003Eh]
Table 3−22. Device ID Register (CSIDR) Bit Functions
BIT
NO.
BIT
NAME
FUNCTION
15−8
7−4
Chip ID
Chip identification (hex code of 06 for 5407 and 03 for 5404)
Chip revision identification
Chip Revision
SUBSYSID
3−0
Subsystem identification (0000b for single core devices)
60
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3.16 Memory-Mapped Registers
The 5407/5404 has 27 memory-mapped CPU registers, which are mapped in data memory space address
0h to 1Fh. Each 5407/5404 device also has a set of memory-mapped registers associated with peripherals.
Table 3−23 gives a list of CPU memory-mapped registers (MMRs) available on 5407/5404. Table 3−24 shows
additional peripheral MMRs associated with the 5407/5404.
Table 3−23. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
—
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2−5
6
2−5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15−0)
AH
9
9
Accumulator A high word (31−16)
Accumulator A guard bits (39−32)
Accumulator B low word (15−0)
Accumulator B high word (31−16)
Accumulator B guard bits (39−32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
—
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
61
November 2001 − Revised April 2004
SPRS007D
Functional Overview
Table 3−24. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DESCRIPTION
DEC
HEX
DRR20
DRR10
DXR20
DXR10
TIM
32
20
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer 0 Register
33
34
21
22
35
36
23
24
PRD
37
25
Timer 0 Period Register
TCR
38
26
Timer 0 Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
41
28
29
Software Wait-State Register
Bank-Switching Control Register
Reserved
42
2A
SWCR
HPIC
—
43
2B
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
44
45−47
48
2C
2D−2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
SPSA0
SPSD0
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
49
50
31
32
51
52
33
34
†
McBSP 2 Subbank Address Register
†
53
54−55
56
35
36−37
38
McBSP 2 Subbank Data Register
Reserved
McBSP 0 Subbank Address Register
†
†
57
58−59
60
39
3A−3B
3C
McBSP 0 Subbank Data Register
Reserved
GPIOCR
GPIOSR
CSIDR
—
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
61
3D
62
63
3E
3F
Reserved
DRR21
DRR11
DXR21
DXR11
USAR
USDR
—
SPSA1
SPSD1
—
64
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
UART Subbank Address Register
UART Subbank Data Register
Reserved
65
66
41
42
67
68
43
44
69
70−71
72
45
46−47
48
†
McBSP 1 Subbank Address Register
†
73
74−75
76
49
4A−4B
4C
McBSP 1 Subbank Data Register
Reserved
TIM1
Timer 1 Register
PRD1
TCR1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
77
4D
Timer 1 Period Register
Timer 1 Control Register
Reserved
78
79−83
84
4E
4F−53
54
DMA Priority and Enable Control Register
‡
85
86
55
56
DMA Subbank Address Register
DMA Subbank Data Register with Autoincrement
‡
‡
87
88
57
58
DMA Subbank Data Register
Clock Mode Register (CLKMD)
Reserved
89−95
59−5F
†
See Table 3−25 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3−26 for a detailed description of the DMA subbank addressed registers.
‡
62
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3.17 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within
the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3−25 shows the McBSP control registers and their corresponding subaddresses.
Table 3−25. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB-
ADDRESS
DESCRIPTION
NAME
ADDRESS
39h
NAME
ADDRESS
49h
NAME
ADDRESS
35h
SPCR10
SPCR20
RCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
39h
49h
35h
Serial port control register 2
39h
49h
35h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
35h
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
39h
49h
35h
39h
49h
35h
39h
49h
35h
Multichannel register 2
39h
49h
35h
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
Additional channel enable register for
128-channel selection
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
63
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.18 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3−26 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
Table 3−26. DMA Subbank Addressed Registers
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
64
SPRS007D
November 2001 − Revised April 2004
Functional Overview
Table 3−26. DMA Subbank Addressed Registers (Continued)
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
DMIDX1
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
DMA element index address register 1
DMFRI0
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA0
DMGDA0
DMGCR0
DMGFR0
XSRCDP
XDSTDP
DMGSA1
DMGDA1
DMGCR1
DMGFR1
DMGSA2
DMGDA2
DMGCR2
DMGFR2
DMGSA3
DMGDA3
DMGCR3
DMGFR3
DMGSA4
DMGDA4
DMGCR4
DMGFR4
DMGSA5
DMGDA5
DMGCR5
DMGFR5
DMA global source address reload register, channel 0
DMA global destination address reload register, channel 0
DMA global count reload register, channel 0
DMA global frame count reload register, channel 0
DMA extended source data page
DMA extended destination data page
DMA global source address reload register, channel 1
DMA global destination address reload register, channel 1
DMA global count reload register, channel 1
DMA global frame count reload register, channel 1
DMA global source address reload register, channel 2
DMA global destination address reload register, channel 2
DMA global count reload register, channel 2
DMA global frame count reload register, channel 2
DMA global source address reload register, channel 3
DMA global destination address reload register, channel 3
DMA global count reload register, channel 3
DMA global frame count reload register, channel 3
DMA global source address reload register, channel 4
DMA global destination address reload register, channel 4
DMA global count reload register, channel 4
DMA global frame count reload register, channel 4
DMA global source address reload register, channel 5
DMA global destination address reload register, channel 5
DMA global count reload register, channel 5
DMA global frame count reload register, channel 5
65
November 2001 − Revised April 2004
SPRS007D
Functional Overview
3.19 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−27.
Table 3−27. Interrupt Locations and Priorities
LOCATION
DECIMAL
0
NAME
PRIORITY
FUNCTION
HEX
00
RS, SINTR
NMI, SINT16
SINT17
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer 0 interrupt
4
04
8
08
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
SINT18
12
0C
10
SINT19
16
SINT20
20
14
SINT21
24
18
SINT22
28
1C
20
SINT23
32
SINT24
36
24
SINT25
40
28
SINT26
44
2C
30
SINT27
48
SINT28
52
34
SINT29
56
38
SINT30
60
3C
40
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT0, SINT3
64
68
44
4
72
48
5
76
4C
50
6
BRINT0, SINT4
BXINT0, SINT5
BRINT2, SINT6
BXINT2, SINT7
INT3, TINT1, SINT8
HINT, SINT9
80
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
84
54
8
†
88
58
9
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
†
92
5C
60
10
11
12
13
14
15
16
—
—
‡
96
External user interrupt #3/Timer 1 interrupt
HPI interrupt
100
104
108
112
116
120
124−127
64
†
BRINT1, SINT10
BXINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
UART, SINT14
Reserved
68
McBSP #1 receive interrupt (default)
†
6C
70
McBSP #1 transmit interrupt (default)
DMA channel 4
DMA channel 5
UART interrupt
Reserved
74
78
7C−7F
†
‡
See Table 3−13 for other interrupt selections.
The INT3 and TINT1 interrupts are ORed together. To distinguish one from the other, one of these two interrupt sources must be inhibited.
66
SPRS007D
November 2001 − Revised April 2004
Functional Overview
3.19.1 IFR and IMR Registers
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3−26.
15
14
13
12
11
10
9
8
†
Reserved
UART
DMAC5
DMAC4
BXINT1
BRINT1
HINT
INT3
7
6
5
4
3
2
1
0
BXINT2
BRINT2
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
†
Bit 8 reflects the status of either INT3 or TINT1: these two interrupts are ORed together. To distinguish one from the other, one of these two interrupt
sources must be inhibited.
Figure 3−26. IFR and IMR
67
November 2001 − Revised April 2004
SPRS007D
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
68
SPRS007D
November 2001 − Revised April 2004
Documentation Support
4.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320VC5407/TMS320VC5404). Texas Instruments recommends two
of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320 is a trademark of Texas Instruments.
69
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5407/TMS320VC5404 DSP.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to DV . Figure 5−1 provides the test load circuit
SS
values for a 3.3-V device.
Supply voltage I/O range, DV
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.0 V
DD
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 100°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
5.2 Recommended Operating Conditions
MIN
2.7
NOM
3.3
MAX
3.6
UNIT
V
DV
CV
Device supply voltage, I/O
Device supply voltage, core
DD
1.42
1.5
1.65
V
DD
DV
CV
,
SS
SS
Supply voltage, GND
0
V
RS, INTn, NMI, X2/CLKIN,
BIO, TRST, Dn, An, HDn,
CLKMDn, BCLKRn, BCLKXn,
HCS, HDS1, HDS2, HAS, RX,
TCK
2.4
DV + 0.3
DD
V
V
High-level input voltage, I/O
V
IH
All other inputs
2
DV + 0.3
DD
Low-level input voltage
High-level output current
Low-level output current
Operating case temperature
−0.3
0.8
−2
V
IL
OH
OL
I
I
mA
mA
°C
2
T
C
0
100
70
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX
UNIT
DV = 3 V to 3.6 V, I = MAX
DD
OH
‡
V
V
High-level output voltage
V
OH
DV = 2.7 V to 3 V, I = MAX
2.2
DD
OH
‡
Low-level output voltage
I
OL
= MAX
0.4
V
OL
Input current in high
impedance
I
A[22:0]
DV = MAX, V = DV to DV
DD
−275
275
µA
µA
IZ
DD
O
SS
X2/CLKIN
−40
−10
40
800
400
10
TRST
With internal pulldown
HPIENA
With internal pulldown, RS = 0
With internal pullups
−10
Input current
I
I
§
(V = DV to DV
)
I
SS
DD
TMS, TCK, TDI, HPI
D[15:0], HD[7:0]
−400
−275
−5
µA
Bus holders enabled, DV = MAXk
275
5
DD
All other input-only pins
¶
#
||
I
I
Supply current, core CPU
Supply current, pins
CV = 1.5 V, f = 120 MHz, T = 25°C
42
mA
DDC
DD
x
C
¶
DV = 3.0 V, f = 120 MHz, T = 25°C
20
mA
mA
DDP
DD
x
C
IDLE2
IDLE3
PLL × 1 mode, 20 MHz input
Divide-by-two mode, CLKIN stopped
2
Supply current,
standby
I
DD
1h
mA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
§
¶
#
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0−INT3, NMI, X2/CLKIN, CLKMD1−CLKMD3 are LVTTL-compatible.
HPI input signals except for HPIENA.
Clock mode: PLL × 1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
||
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
kV
≤ V ≤ V
or V ≤ V ≤ V
IH(MIN) I IH(MAX)
IL(MIN)
I
IL(MAX)
hMaterial with high I has been observed with an I as high as 7 mA during high temperature testing.
DD
DD
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 20-pF typical load circuit capacitance
T
Figure 5−1. 3.3-V Test Load Circuit
71
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.4 Package Thermal Resistance Characteristics
Table 5−1 provides the estimated thermal resistance characteristics for the recommended package types
used on the TMS320VC5407/TMS320VC5404 DSP.
Table 5−1. Thermal Resistance Characteristics
GGU
PACKAGE
PGE
PACKAGE
PARAMETER
UNIT
R
R
38
5
56
5
°C/W
°C/W
Θ
JA
JC
Θ
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
5.6 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;
see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by
the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting
of the crystal and two load capacitors, is shown in Figure 5−2. The load capacitors, C and C , should be
1
2
chosen such that the equation below is satisfied. C (recommended value of 10 pF) in the equation is the load
L
specified for the crystal.
C1C2
CL +
(C1 ) C2)
Table 5−2. Input Clock Frequency Characteristics
MIN
MAX
UNIT
†
‡
f
x
Input clock frequency
10
20
MHz
†
‡
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz
It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
approaching ∞. The device is characterized at frequencies
c(CI)
72
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
X1
X2/CLKIN
Crystal
C1
C2
Figure 5−2. Internal Divide-by-Two Clock Option With External Crystal
5.7 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.7.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5−4.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5−3 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5−3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
1/2, PLL and oscillator disabled
0
1
1
0
0
1
0
1
1
1/4, PLL and oscillator disabled
1/2, PLL and oscillator disabled
73
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5t
(see
c(CO)
Figure 5−3).
Table 5−4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
MIN
MAX
UNIT
t
t
t
t
t
Cycle time, X2/CLKIN
20
ns
ns
ns
ns
ns
c(CI)
Fall time, X2/CLKIN
4
4
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
w(CIL)
w(CIH)
Table 5−5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ns
†
‡
t
Cycle time, CLKOUT
8.33
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
7
1
11
ns
d(CIH-CO)
t
ns
f(CO)
t
t
t
Rise time, CLKOUT
1
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H − 3
H − 3
H
H
H + 3
H + 3
ns
w(COL)
w(COH)
ns
†
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
r(CI)
t
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5−3. External Divide-by-Two Clock Timing
74
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.7.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5−6.
Table 5−6 and Table 5−7 assume testing over recommended operating conditions and H = 0.5t
Figure 5−4).
(see
c(CO)
Table 5−6. Multiply-By-N Clock Option Timing Requirements
MIN
20
MAX
UNIT
†
Integer PLL multiplier N (N = 1−15)
200
100
50
†
PLL multiplier N = x.5
20
t
Cycle time, X2/CLKIN
ns
c(CI)
†
PLL multiplier N = x.25, x.75
20
t
t
t
t
Fall time, X2/CLKIN
4
4
ns
ns
ns
ns
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
w(CIL)
w(CIH)
†
N is the multiplication factor.
Table 5−7. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
MIN
8.33
4
TYP
MAX
UNIT
ns
t
Cycle time, CLKOUT
c(CO)
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
7
2
11
ns
d(CI-CO)
t
ns
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
2
ns
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
H
H
ns
ns
30
ms
t
t
f(CI)
w(CIH)
t
r(CI)
t
t
c(CI)
w(CIL)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5−4. Multiply-by-One Clock Timing
75
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.8 Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5−8 and Table 5−9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
(see Figure 5−5 and Figure 5−6).
c(CO)
Table 5−8. Memory Read Timing Requirements
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
4H−9
ns
Access time, read data access from address
valid, first read access
t
a(A)M1
†
For read accesses immediately following a
HOLD operation
4H−11
2H−9
ns
†
t
t
t
Access time, read data access from address valid, consecutive read accesses
Setup time, read data valid before CLKOUT low
ns
ns
ns
a(A)M2
su(D)R
h(D)R
7
0
Hold time, read data valid after CLKOUT low
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5−9. Memory Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
− 1
4
ns
†
t
Delay time, CLKOUT low to address valid
d(CLKL-A)
For read accesses immediately following a
HOLD operation
− 1
6
ns
t
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
− 1
4
4
ns
ns
d(CLKL-MSL)
t
0
d(CLKL-MSH)
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
76
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
CLKOUT
t
d(CLKL-A)
†
A[22:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(A)M1
D[15:0]
MSTRB
t
su(D)R
t
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5−5. Nonconsecutive Mode Memory Reads
77
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-MSH)
†
A[22:0]
t
a(A)M1
t
a(A)M2
D[15:0]
MSTRB
t
t
su(D)R
su(D)R
t
t
h(D)R
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5−6. Consecutive Mode Memory Reads
78
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.8.2 Memory Write
Table 5−10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
(see
c(CO)
Figure 5−7).
Table 5−10. Memory Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
For accesses not immediately following a
− 1
4
ns
ns
ns
ns
HOLD operation
Delay time, CLKOUT low to address
valid
t
d(CLKL-A)
†
For read accesses immediately following a
HOLD operation
− 1
2H − 3
2H − 5
6
For accesses not immediately following a
HOLD operation
Setup time, address valid before MSTRB
low
t
su(A)MSL
†
For read accesses immediately following a
HOLD operation
t
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
− 1
2H − 5
2H − 5
− 1
5
2H + 6
2H + 6
4
ns
ns
ns
ns
ns
ns
d(CLKL-D)W
t
su(D)MSH
t
h(D)MSH
t
d(CLKL-MSL)
t
2H − 2
0
w(SL)MS
t
Delay time, CLKOUT low to MSTRB high
4
d(CLKL-MSH)
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
79
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-D)W
t
su(A)MSL
†
A[22:0]
t
su(D)MSH
t
h(D)MSH
D[15:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
w(SL)MS
MSTRB
†
R/W
†
PS/DS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5−7. Memory Write (MSTRB = 0)
80
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.8.3 I/O Read
Table 5−11 and Table 5−12 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t (see Figure 5−8).
c(CO)
Table 5−11. I/O Read Timing Requirements
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
4H − 9
ns
Access time, read data access from
address valid, first read access
t
a(A)M1
†
For read accesses immediately following a
HOLD operation
4H − 11
ns
t
t
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
7
ns
ns
su(D)R
0
h(D)R
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 5−12. I/O Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
For accesses not immediately following a
HOLD operation
− 1
− 1
4
ns
†
t
Delay time, CLKOUT low to address valid
d(CLKL-A)
For read accesses immediately following a
HOLD operation
6
ns
t
Delay time, CLKOUT low to IOSTRB low
Delay time, CLKOUT low to IOSTRB high
− 1
4
4
ns
ns
d(CLKL-IOSL)
t
0
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
81
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
†
A[22:0]
t
a(A)M1
t
su(D)R
t
h(D)R
D[15:0]
IOSTRB
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5−8. Parallel I/O Port Read (IOSTRB = 0)
82
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.8.4 I/O Write
Table 5−13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
(see
c(CO)
Figure 5−9).
Table 5−13. I/O Write Switching Characteristics
PARAMETER
MIN
− 1
MAX
UNIT
For accesses not immediately following a
HOLD operation
4
6
ns
ns
ns
ns
Delay time, CLKOUT low to address
t
d(CLKL-A)
†
valid
For read accesses immediately following a
HOLD operation
− 1
For accesses not immediately following a
HOLD operation
2H − 3
Setup time, address valid before IOSTRB
t
su(A)IOSL
†
low
For read accesses immediately following a
HOLD operation
2H − 5
− 1
t
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
4
ns
ns
ns
ns
ns
ns
d(CLKL-D)W
t
2H − 5 2H + 6
2H − 5 2H + 6
su(D)IOSH
t
h(D)IOSH
t
t
t
− 1
2H − 2
0
4
d(CLKL-IOSL)
w(SL)IOS
Delay time, CLKOUT low to IOSTRB high
4
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
t
d(CLKL-A)
†
A[22:0]
t
d(CLKL-D)W
t
d(CLKL-D)W
t
su(A)IOSL
D[15:0]
t
su(D)IOSH
t
d(CLKL-IOSH)
t
h(D)IOSH
t
d(CLKL-IOSL)
IOSTRB
t
w(SL)IOS
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5−9. Parallel I/O Port Write (IOSTRB = 0)
83
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5−14 and Table 5−15 assume testing over recommended operating conditions and H = 0.5t
Figure 5−10, Figure 5−11, Figure 5−12, and Figure 5−13).
(see
c(CO)
†
Table 5−14. Ready Timing Requirements for Externally Generated Wait States
MIN
7
MAX
UNIT
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H − 4
4H − 4
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
4H
†
‡
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
†
Table 5−15. Ready Switching Characteristics for Externally Generated Wait States
PARAMETER
Delay time, MSC low to CLKOUT low
Delay time, CLKOUT low to MSC high
MIN
− 1
− 1
MAX
UNIT
ns
t
4
d(MSCL)
t
4
ns
d(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
84
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MCSL)
t
d(MCSH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5−10. Memory Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
Wait
States
States
Generated
by READY
Trailing
Cycle
Generated
Internally
Figure 5−11. Memory Write With Externally Generated Wait States
85
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5−12. I/O Read With Externally Generated Wait States
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
Trailing
Cycle
States
Wait
Generated
Internally
States
Generated
by READY
Figure 5−13. I/O Write With Externally Generated Wait States
86
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.10 HOLD and HOLDA Timings
Table 5−16 and Table 5−17 assume testing over recommended operating conditions and H = 0.5t
Figure 5−14).
(see
c(CO)
Table 5−16. HOLD and HOLDA Timing Requirements
MIN
4H+8
7
MAX
UNIT
t
t
Pulse duration, HOLD low duration
ns
ns
w(HOLD)
Setup time, HOLD before CLKOUT low
su(HOLD)
Table 5−17. HOLD and HOLDA Switching Characteristics
PARAMETER
MIN
MAX
3
UNIT
ns
t
t
t
t
t
t
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
3
ns
3
ns
2H+4
2H+3
2H+3
ns
ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
ns
− 1
4
4
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
− 1
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H−3
w(HOLDA)
CLKOUT
t
t
su(HOLD)
su(HOLD)
t
w(HOLD)
HOLD
t
t
v(HOLDA)
v(HOLDA)
t
w(HOLDA)
HOLDA
t
t
en(CLKL−A)
dis(CLKL−A)
A[22:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL−RW)
dis(CLKL−S)
dis(CLKL−S)
en(CLKL−RW)
t
en(CLKL−S)
MSTRB
IOSTRB
t
en(CLKL−S)
Figure 5−14. HOLD and HOLDA Timings (HM = 1)
87
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.11 Reset, BIO, Interrupt, and MP/MC Timings
Table 5−18 assumes testing over recommended operating conditions and H = 0.5t
Figure 5−16, and Figure 5−17).
(see Figure 5−15,
c(CO)
Table 5−18. Reset, BIO, Interrupt, and MP/MC Timing Requirements
MIN
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
h(RS)
4
h(BIO)
†
Hold time, INTn, NMI, after CLKOUT low
1
h(INT)
Hold time, MP/MC after CLKOUT low
4
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+3
2H+3
4H
Pulse duration, BIO low, synchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
2H+2
4H
2H+2
4H
8
¶
Setup time, RS before X2/CLKIN low
3
Setup time, BIO before CLKOUT low
7
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
7
su(INT)
5
su(MPMC)
†
‡
The external interrupts (INT0−INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1−0−0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure synchronization
and lock-in of the PLL.
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
CLKOUT
BIO
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
t
w(BIO)S
Figure 5−15. Reset and BIO Timings
88
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
CLKOUT
t
t
su(INT)
t
h(INT)
su(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 5−16. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 5−17. MP/MC Timing
89
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5−19 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 5−18).
c(CO)
Table 5−19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
PARAMETER
Delay time, CLKOUT low to IAQ low
MIN
− 1
MAX
UNIT
ns
t
4
d(CLKL-IAQL)
t
t
Delay time, CLKOUT low to IAQ high
Delay time, IAQ low to address valid
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, IACK low to address valid
Hold time, address valid after IAQ high
Hold time, address valid after IACK high
Pulse duration, IAQ low
− 1
4
2
4
4
2
ns
d(CLKL-IAQH)
d(A)IAQ
ns
t
− 1
− 1
ns
d(CLKL-IACKL)
t
ns
d(CLKL-IACKH)
d(A)IACK
h(A)IAQ
t
t
t
t
t
ns
− 2
− 2
ns
ns
h(A)IACK
w(IAQL)
2H − 2
2H − 2
ns
Pulse duration, IACK low
ns
w(IACKL)
CLKOUT
A[22:0]
t
t
d(CLKL−IAQH)
d(CLKL−IAQL)
t
h(A)IAQ
t
d(A)IAQ
t
w(IAQL)
IAQ
t
t
t
d(CLKL−IACKH)
d(CLKL−IACKL)
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
Figure 5−18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
90
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.13 External Flag (XF) and TOUT Timings
Table 5−20 assumes testing over recommended operating conditions and H = 0.5t
Figure 5−20).
(see Figure 5−19 and
c(CO)
Table 5−20. External Flag (XF) and TOUT Switching Characteristics
PARAMETER
MIN
− 1
MAX
UNIT
Delay time, CLKOUT low to XF high
4
t
ns
d(XF)
Delay time, CLKOUT low to XF low
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
− 1
− 1
4
4
4
t
t
t
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
− 1
2H − 4
CLKOUT
t
d(XF)
XF
Figure 5−19. External Flag (XF) Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 5−20. TOUT Timing
91
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1 McBSP Transmit and Receive Timings
Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−21 and
Figure 5−22).
†
Table 5−21. McBSP Transmit and Receive Timing Requirements
MIN
MAX
UNIT
ns
‡
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4P
c(BCKRX)
‡
Pulse duration, BCLKR/X high or BCLKR/X low
2P−1
ns
w(BCKRX)
8
1
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
1
2
7
1
2
Hold time, BDR valid after BCLKR low
3
10
1
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
0
2
t
t
Rise time, BCKR/X
Fall time, BCKR/X
6
6
ns
ns
r(BCKRX)
f(BCKRX)
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
92
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
†
Table 5−22. McBSP Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
‡
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4P
c(BCKRX)
§
§
Pulse duration, BCLKR/X high
Pulse duration, BCLKR/X low
D − 1
D + 1
ns
w(BCKRXH)
w(BCKRXL)
§
§
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
C − 1
C + 1
ns
ns
ns
− 3
0
3
12
5
t
t
t
t
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
d(BCKXH-BFXV)
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
d(BFXH-BDXV)
− 1
2
ns
ns
ns
ns
10
6
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
10
10
20
7
¶
− 1
#
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
2
¶
−1
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
BFSX ext
2
11
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 0.5 * processor clock
T
C
D
=
=
=
BCLKRX period = (1 + CLKGDV) * 2P
BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
#
Minimum delay times also represent minimum output hold times.
The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5407/TMS320VC5404.
t
c(BCKRX)
t
w(BCKRXH)
t
t
r(BCKRX)
f(BCKRX)
t
w(BCKRXL)
BCLKR
BFSR (int)
BFSR (ext)
BDR
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
(n-2)
(n-3)
Bit(n-1)
Figure 5−21. McBSP Receive Timings
93
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
t
c(BCKRX)
t
t
w(BCKRXH)
t
t
f(BCKRX)
r(BCKRX)
w(BCKRXL)
BCLKX
t
d(BCKXH-BFXV)
BFSX (int)
BFSX (ext)
t
h(BCKXL-BFXH)
t
su(BFXH-BCKXL)
BFSX
(XDATDLY=00b)
t
d(BCKXH-BDXV)
t
d(BFXH-BDXV)
t
t
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
BDX
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 5−22. McBSP Transmit Timings
94
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.14.2 McBSP General-Purpose I/O Timing
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−23).
Table 5−23. McBSP General-Purpose I/O Timing Requirements
MIN
7
MAX
UNIT
ns
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
ns
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5−24. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
MIN
MAX
UNIT
‡
t
Delay time, CLKOUT high to BGPIOx output mode
− 2
4
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5−23. McBSP General-Purpose I/O Timings
95
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.14.3 McBSP as SPI Master or Slave Timing
Table 5−25 to Table 5−32 assume testing over recommended operating conditions (see Figure 5−24,
Figure 5−25, Figure 5−26, and Figure 5−27).
†
Table 5−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
UNIT
MIN
12
4
MAX
MIN
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2 − 6P
ns
ns
su(BDRV-BCKXL)
‡
5 + 12P
h(BCKXL-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
§
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
t
t
Hold time, BFSX low after BCLKX low
T − 3 T + 4
C − 4 C + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
#
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid
‡
‡
− 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C − 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
t
t
2P− 4
6P + 17
ns
ns
dis(BFXH-BDXHZ)
‡
Delay time, BFSX low to BDX valid
4P+ 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
C
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5−24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
96
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
†
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
UNIT
MIN
12
4
MAX
MIN
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
2 − 6P
ns
ns
su(BDRV-BCKXL)
‡
5 + 12P
h(BCKXH-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
§
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
t
t
Hold time, BFSX low after BCLKX low
C −3 C + 4
T − 4 T + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
#
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
‡
‡
‡
− 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
‡
t
− 2
4
6P − 4
10P + 17
ns
ns
dis(BCKXL-BDXHZ)
‡
‡
t
Delay time, BFSX low to BDX valid
D − 2 D + 4 4P + 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
=
=
BCLKX period = (1 + CLKGDV) * 2P
C
D
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
#
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
MSB
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5−25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
97
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
†
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
UNIT
MIN
12
4
MAX
MIN
MAX
‡
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 − 6P
ns
ns
su(BDRV-BCKXH)
‡
5 + 12P
h(BCKXH-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
§
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
t
t
Hold time, BFSX low after BCLKX high
T − 3 T + 4
D − 4 D + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
#
Delay time, BFSX low to BCLKX low
‡
‡
Delay time, BCLKX low to BDX valid
− 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D − 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
t
t
2P − 4
6P + 17
ns
ns
dis(BFXH-BDXHZ)
‡
Delay time, BFSX low to BDX valid
4P + 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
D
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
LSB
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 5−26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
98
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
†
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
UNIT
MIN
12
4
MAX
MIN
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2 − 6P
ns
ns
su(BDRV-BCKXL)
‡
5 + 12P
h(BCKXL-BDRV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
†
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
§
MASTER
SLAVE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
¶
t
t
t
Hold time, BFSX low after BCLKX high
D − 3 D + 4
T − 4 T + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
#
Delay time, BFSX low to BCLKX low
‡
‡
‡
Delay time, BCLKX high to BDX valid
− 4
5
6P + 2
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
‡
t
− 2
4
6P − 4
10P + 17
ns
ns
dis(BCKXH-BDXHZ)
‡
‡
t
Delay time, BFSX low to BDX valid
C − 2 C + 4 4P + 2
8P + 17
d(BFXL-BDXV)
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 0.5 * processor clock
T
=
=
=
BCLKX period = (1 + CLKGDV) * 2P
C
D
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
#
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5−27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
99
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.15 Host-Port Interface Timing
5.15.1 HPI8 Mode
Table 5−33 and Table 5−34 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5−28 through Figure 5−31). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0,
HCNTL1, and HR/W.
Table 5−33. HPI8 Mode Timing Requirements
MIN
6
MAX
UNIT
ns
Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS
low
t
t
su(HBV-DSL)
Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low
3
ns
h(DSL-HBV)
t
t
t
t
t
t
t
Setup time, HAS low before DS low
8
13
7
ns
ns
ns
ns
ns
ns
ns
su(HSL-DSL)
Pulse duration, DS low
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
3
su(HDV-DSH)
h(DSH-HDV)W
2
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
3
su(GPIO-COH)
h(GPIO-COH)
0
100
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
Table 5−34. HPI8 Mode Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
Enable time, HD driven from DS low
0
10
ns
en(DSL-HD)
Case 1a: Memory accesses when DMAC is active
18P+10−t
36P+10−t
10
w(DSH)
†
in 16-bit mode and t
< I8H
w(DSH)
Case 1b: Memory accesses when DMAC is active
w(DSH)
†
in 32-bit mode and t
≥ I8H
w(DSH)
Case 1c: Memory accesses when DMAC is active
†
in 16-bit mode and t
≥ I8H
w(DSH)
Delay time, DS low to HD valid
for first byte of an HPI read
Case 1d: Memory accesses when DMAC is active
t
ns
d(DSL-HDV1)
10
†
in 32-bit mode and t
≥ I8H
w(DSH)
Case 2a: Memory accesses when DMAC is inactive
10P+15−t
10
w(DSH)
†
and t
< 10H
w(DSH)
Case 2b: Memory accesses when DMAC is inactive
†
and t
≥ 10H
w(DSH)
Case 3: Register accesses
10
10
t
t
t
t
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
ns
ns
ns
ns
d(DSL-HDV2)
h(DSH-HDV)R
v(HYH-HDV)
d(DSH-HYL)
2
2
8
‡
Delay time, DS high to HRDY low
Case 1a: Memory accesses when DMAC is active
in 16-bit mode
18P+6
36P+6
†
Case 1b: Memory accesses when DMAC is active
Delay time, DS high to HRDY
high
t
†
ns
d(DSH-HYH)
in 32-bit mode
‡
†
Case 2: Memory accesses when DMAC is inactive
10P+6
§
Case 3: Write accesses to HPIC register
6P+6
6
9
6
ns
ns
ns
t
t
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
d(COH-HYH)
d(COH-HTX)
Delay time, CLKOUT high to HDx output change. HDx is configured as
general-purpose output
a
t
5
ns
d(COH-GPIO)
†
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times
are affected by DMAC activity.
The HRDY output is always high when the HCS input is high, regardless of DS timings.
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously,
and do not cause HRDY to be deasserted.
‡
§
101
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
HDS
t
w(DSH)
t
w(DSL)
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
t
h(DSH-HDV)R
HD READ
HD WRITE
Valid
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
t
h(DSH-HDV)W
Valid
Valid
Valid
t
d(COH-HYH)
Processor
CLK
†
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
‡
Figure 5−28. Using HDS to Control Accesses (HCS Always Low)
102
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 5−29. Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 5−30. HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
GPIOx Input Mode
t
d(COH-GPIO)
†
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 5−31. GPIOx Timings
103
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
5.15.2 HPI16 Mode
Table 5−35 and Table 5−36 assume testing over recommended operating conditions and P = 0.5 * processor
clock (see Figure 5−32 through Figure 5−34). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are
shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.
Table 5−35. HPI16 Mode Timing Requirements
MIN
6
MAX
UNIT
ns
t
t
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
su(HBV-DSL)
5
ns
h(DSL-HBV)
t
t
t
t
t
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
5
ns
ns
ns
ns
ns
su(HAV-DSH)
su(HAV-DSL)
h(DSH-HAV)
w(DSL)
−(4P − 6)
1
30
Pulse duration, DS high
10
w(DSH)
Reads
Writes
Reads
Writes
Reads
Writes
10P + 30
10P + 10
16P + 30
16P + 10
24P + 30
24P + 10
8
Memory accesses with no DMA activity.
Cycle time, DS rising edge to
next DS rising edge
t
Memory accesses with 16-bit DMA activity.
Memory accesses with 32-bit DMA activity.
ns
c(DSH-DSH)
t
t
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
ns
ns
su(HDV-DSH)W
2
h(DSH-HDV)W
104
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
Table 5−36. HPI16 Mode Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
t
Delay time, DS low to HD driven
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 18H
0
10
ns
d(DSL-HDD)
32P + 20 − t
w(DSH)
w(DSH)
Case 1b: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
16P + 20
48P + 20 − t
Delay time,
DS low to HD
valid for first
word of an
HPI read
Case 1c: Memory accesses initiated immediately following a write
w(DSH)
when DMAC is active in 32-bit mode and t
was < 26H
w(DSH)
ns
d(DSL-HDV1)
Case 1d: Memory access not immediately following a write when
DMAC is active in 32-bit mode
24P + 20
20P + 20 − t
Case 2a: Memory accesses initiated immediately following a write
w(DSH)
when DMAC is inactive and t
was < 10H
w(DSH)
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
10P + 20
Memory writes when no DMA is active
10P + 5
16P + 5
24P + 5
7
Delay
DS high to
HRDY high
time,
Memory writes with one or more 16-bit DMA channels active
Memory writes with one or more 32-bit DMA channels active
t
ns
d(DSH-HYH)
ns
ns
ns
ns
ns
t
t
t
t
t
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
v(HYH-HDV)
h(DSH-HDV)R
d(COH-HYH)
d(DSL-HYL)
d(DSH−HYL)
1
6
5
12
12
Delay time, DS high to HRDY low
HCS
t
w(DSH)
t
c(DSH−DSH)
HDS
t
t
su(HBV−DSL)
w(DSL)
t
su(HBV−DSL)
t
t
h(DSL−HBV)
h(DSL−HBV)
HR/W
t
su(HAV−DSL)
t
h(DSH−HAV)
HA[17:0]
Valid Address
Valid Address
t
h(DSH−HDV)R
t
d(DSL−HDV1)
t
t
h(DSH−HDV)R
d(DSL−HDV1)
Data
HD[15:0]
HRDY
Data
t
d(DSL−HDD)
t
d(DSL−HDD)
t
v(HYH−HDV)
t
v(HYH−HDV)
t
t
d(DSL−HYL)
d(DSL−HYL)
Figure 5−32. Nonmultiplexed Read Timings
105
November 2001 − Revised April 2004
SPRS007D
Electrical Specifications
HCS
t
w(DSH)
t
c(DSH−DSH)
HDS
t
su(HBV−DSL)
t
su(HBV−DSL)
t
t
h(DSL−HBV)
h(DSL−HBV)
HR/W
t
su(HAV−DSH)
t
w(DSL)
t
h(DSH−HAV)
Valid Address
Valid Address
HA[15:0]
HD[15:0]
HRDY
t
t
su(HDV−DSH)W
su(HDV−DSH)W
t
h(DSH−HDV)W
t
h(DSH−HDV)W
Data Valid
Data Valid
t
d(DSH−HYH)
t
d(DSH−HYL)
Figure 5−33. Nonmultiplexed Write Timings
HRDY
t
d(COH−HYH)
CLKOUT
Figure 5−34. HRDY Relative to CLKOUT
106
SPRS007D
November 2001 − Revised April 2004
Electrical Specifications
5.16 UART Timing
Table 5−37 to Table 5−38 assume testing over recommended operating conditions (see Figure 5−35).
Table 5−37. UART Timing Requirements
MIN
MAX
UNIT
ns
†
†
t
t
Pulse width, receive data bit
Pulse width, receive start bit
0.99U
1.01U
w(UDB)R
†
†
0.99U
1.01U
ns
w(USB)R
†
U = UART baud time = 1/programmed baud rate
Table 5−38. UART Switching Characteristics
PARAMETER
Maximum programmable baud rate
Pulse width, transmit data bit
MIN
MAX
UNIT
MHz
ns
f
t
t
5
baud
†
†
U − 2
U + 2
w(UDB)X
w(USB)X
†
†
Pulse width, transmit start bit
U − 2
U + 2
ns
†
U = UART baud time = 1/programmed baud rate
t
w(USB)X
Data Bits
Start
Bit
TX
t
w(UDB)X
Data Bits
Start
Bit
RX
t
w(UDB)R
t
w(USB)R
Figure 5−35. UART Timings
107
November 2001 − Revised April 2004
SPRS007D
Mechanical Data
6
Mechanical Data
6.1 Ball Grid Array Mechanical Data
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
9,60 TYP
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6 7 8 9 10 11 12 13
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,08
0,45
0,45
0,35
4073221-2/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGAt configuration
Figure 6−1. TMS320VC5407/TMS320VC5404 144-Ball MicroStar BGA Plastic Ball Grid Array Package
MicroStar BGA is a trademark of Texas Instruments.
108
SPRS007D
November 2001 − Revised April 2004
Mechanical Data
6.2 Low-Profile Quad Flatpack Mechanical Data
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°−ꢀ7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
Figure 6−2. TMS320VC5407/TMS320VC5404 144-Pin Low-Profile Quad Flatpack (PGE)
109
November 2001 − Revised April 2004
SPRS007D
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320VC5404GGU
TMS320VC5404PGE
ACTIVE
ACTIVE
BGA
GGU
144
144
160
TBD
SNPB
Level-3-220C-168HR
LQFP
PGE
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320VC5407GGU
TMS320VC5407PGE
ACTIVE
ACTIVE
BGA
GGU
PGE
144
144
160
TBD
SNPB
Level-3-220C-168HR
LQFP
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
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