TMS320VC5441AGGU [TI]
TMS320VC5441 Fixed-Point Digital Signal Processor; TMS320VC5441定点数字信号处理器
| 型号： | TMS320VC5441AGGU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320VC5441 Fixed-Point Digital Signal Processor |
| 文件： | 总86页 (文件大小：1105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5441 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS122E
December 1999 – Revised April 2002
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
December 1999
Product Preview
Original
Converted from data sheet to data manual format and
updated characteristics data.
A
B
November 2000
May 2001
Product Preview
Revised signal descriptions table and updated characteristics
data
Product Preview
C
D
E
July 2001
December 2001
April 2002
Production Data
Production Data
Production Data
Revised electrical characteristics to reflect production data.
Updated characteristics data
Updated characteristic data
iii
Contents
Contents
Section
Page
1
2
TMS320VC5441 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
3
3
5
7
2.1
2.2
2.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Migration From the 5421 to the 5441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
2.3.2
Pin Assignments for the GGU Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
14
14
18
18
19
19
19
19
19
20
20
20
20
24
29
33
35
40
42
44
44
45
47
48
50
52
52
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Two-Way Shared RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multicore Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Bootload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Bidirectional Host-Port Interface (HPI16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software-Programmable Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory Map Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
3.4
3.5
3.6
3.7
3.8
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDLE3 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emulating the 5441 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
54
54
54
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
v
December 1999 – Revised April 2002
SPRS122E
Contents
Section
Page
5.4
5.5
5.6
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
56
57
57
58
59
61
62
63
63
66
67
5.6.1
5.6.2
Divide-By-Two, Divide-By-Four, and Bypass Clock Options – PLL Disabled . . . . .
Multiply-By-N Clock Option – PLL Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
5.8
5.9
Reset, x_BIO, and Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (x_XF), Timer (x_TOUT), and Watchdog Timer Output (x_WTOUT) Timings . .
General-Purpose Input/Output (GPIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
5.10.1
5.10.2
McBSP0/1/2 Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11
Host-Port Interface (HPI16) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
76
6.1
6.2
Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Profile Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SPRS122E
December 1999 – Revised April 2002
Figures
Page
List of Figures
Figure
2–1
2–2
169-Ball GGU MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
176-Pin PGF Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
3–9
Overall Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Subsystem Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem A CPU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem B CPU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem C CPU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem D CPU Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Memory Map of Local Data Memory Relative to CPU Subsystems A, B, C, and D . . . . .
Subsystem A Local DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Subsystem B Local DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
16
17
18
21
21
22
22
26
27
28
29
30
30
31
31
32
33
35
36
38
39
40
43
44
44
51
3–10 Subsystem C Local DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Subsystem D Local DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Interfacing to the HPI-16 in Non-Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 BSCR Register Bit Layout for Subsystem A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 XA Multiplexer for HPI Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–15 Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 Multichannel Control Register 2 for McBSPx (MCR2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Multichannel Control Register 1 for McBSPx (MCR1x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Receive Channel Enable Registers Bit Layout for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Transmit Channel Enable Registers Bit Layout for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 SA Multiplexer for McBSP1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–21 Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–22 Timer Second Control Register (TSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–23 Watchdog Timer Control Register (WDTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–24 Watchdog Timer Second Control Register (WDTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–25 Watchdog Operation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–26 Clock Mode Register (CLKMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–27 General-Purpose I/O Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–28 Chip Subsystem ID Register (CSIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–29 Data Memory Map Register (DMMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–30 Bit Layout of the IMR and IFR Registers for Each Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1
5–2
5–3
5–4
5–5
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset and x_BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
57
58
59
60
vii
December 1999 – Revised April 2002
SPRS122E
Figures
Figure
Page
5–6
5–7
5–8
5–9
External Flag (x_XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer (x_TOUT) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer (x_WTOUT) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
61
61
62
65
65
66
69
70
71
72
73
74
74
5–10 McBSP0/1/2 Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 McBSP0/1/2 Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 McBSP0 General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Multiplexed Read Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–14 Multiplexed Read Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–15 Multiplexed Write Timings Using HAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–16 Multiplexed Write Timings With HAS Held High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–17 Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–18 Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–19 HPI_SEL1 and HPI_SEL2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1
6–2
TMS320VC5441 169-Ball MicroStar BGA Plastic Ball Grid Array (GGU) Package . . . . . . . . . . . . .
TMS320VC5441 176-Pin Low-Profile Quad Flatpack (PGF) Package . . . . . . . . . . . . . . . . . . . . . . .
75
76
viii
SPRS122E
December 1999 – Revised April 2002
Tables
Page
List of Tables
Table
2–1
2–2
2–3
Pin Assignments for TMS320VC5441GGU (169-Ball BGA Package) . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for TMS320VC5441PGF (176-Pin LQFP Package) . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
6
7
3–1
3–2
3–3
3–4
3–5
3–6
3–7
3–8
DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Local/Shared Memory Selection Via HA[20] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Local/Shared Memory Selection Via HA[18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BSCR Register Bit Functions for Subsystem A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI Module Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample Rate Generator Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Channel Enable Registers for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Channel Enable Registers for Partitions A to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TCR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSCR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WDTCR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WDTSCR Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode Register (CLKMD) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplier Related to PLLNDIV, PLLDIV, and PLLMUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCO Lockup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Initialization at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O Control Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip Subsystem ID Register Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory Map Register Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5441 Interrupt Locations and Priorities for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Functions for IMR and IFR Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
26
27
28
30
31
31
34
35
37
38
41
41
41
42
42
43
44
44
45
46
47
48
50
51
3–9
3–10
3–11
3–12
3–13
3–14
3–15
3–16
3–17
3–18
3–19
3–20
3–21
3–22
3–23
3–24
3–25
3–26
3–27
5–1
5–2
5–3
5–4
5–5
5–6
5–7
Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Divide-By-Two, Divide-By-Four, and Bypass Clock Options Timing Requirements . . . . . . . . . . . .
Divide-By-Two, Divide-By-Four, and Bypass Clock Options Switching Characteristics . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset, x_BIO, and Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Flag (x_XF), Timer (x_TOUT), and Watchdog Timer Output (x_WTOUT)
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0/1/2 Transmit and Receive Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0/1/2 Transmit and Receive Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
57
57
58
58
59
61
62
62
63
64
5–8
5–9
5–10
5–11
ix
December 1999 – Revised April 2002
SPRS122E
Tables
Table
Page
5–12
5–13
5–14
5–15
McBSP0 General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
66
67
68
x
SPRS122E
December 1999 – Revised April 2002
Features
1
TMS320VC5441 Features
ꢀ
ꢀ
532-MIPS Quad-Core DSP Consisting of
Four Independent Subsystems
ꢀ
ꢀ
ꢀ
ꢀ
Conditional Store Instructions
Output Control of CLKOUT
Each Core has an Advanced Multibus
Architecture With Three Separate 16-Bit
Data Memory Buses and One Program Bus
Output Control of Timer Output (TOUT)
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions
ꢀ
ꢀ
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel-Shifter and Two
40-Bit Accumulators Per Core
ꢀ
Dual 1.6-V (Core) and 3.3-V (I/O) Power
Supplies for Low-Power, Fast Operations
ꢀ
ꢀ
7.5-ns Single-Cycle Fixed-Point Instruction
Each Core has a 17-Bit × 17-Bit Parallel
Multiplier Coupled to a 40-Bit Adder for
Non-Pipelined Single-Cycle Multiply/
Accumulate (MAC) Operations
Twenty-Four Channels of Direct Memory
Access (DMA) for Data Transfers With No
CPU Loading (Six Channels Per
Subsystem)
ꢀ
ꢀ
ꢀ
Each Core has a Compare, Select, and
Store Unit (CSSU) for the Add/Compare
Selection of the Viterbi Operator
ꢀ
Twelve Multichannel Buffered Serial Ports
(McBSPs), Each With 128-Channel
Selection Capability (Three McBSPs per
Subsystem)
Each Core has an Exponent Encoder to
Compute an Exponent Value of a 40-Bit
Accumulator Value in a Single Cycle
ꢀ
ꢀ
16-Bit Host-Port Interface (HPI)
Software-Programmable Phase-Locked
Loop (PLL) Provides Several Clocking
Options (Requires External TTL Oscillator)
Each Core has Two Address Generators
With Eight Auxiliary Registers and Two
Auxiliary Register Arithmetic Units
(ARAUs)
ꢀ
On-Chip Scan-Based Emulation Logic,
ꢁ
IEEE Standard 1149.1 (JTAG) Boundary-
ꢀ
Total 640K-Word × 16-Bit Dual-Access
On-Chip RAM (256K-Word x 16-Bit Shared
Memory and 96K-Word x 16-Bit Local
Memory Per Subsystem)
Scan Logic
ꢀ
ꢀ
ꢀ
ꢀ
Four Software-Programmable Timers
(One Per Subsystem)
ꢀ
ꢀ
Single-Instruction Repeat and
Block-Repeat Operations
Four Software-Programmable Watchdog
Timers (One Per Subsystem)
Instructions With 32-Bit Long Word
Operands
Sixteen General-Purpose I/Os
(Four Per Subsystem)
ꢀ
ꢀ
ꢀ
Instructions With 2 or 3 Operand Reads
Fast Return From Interrupts
Provided in 176-pin Plastic Low-Profile
Quad Flatpack (LQFP) Package
(PGF Suffix)
Arithmetic Instructions With Parallel Store
and Parallel Load
ꢀ
Provided in 169-ball MicroStar BGAꢂ
Package (GGU Suffix)
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990, Standard Test-Access Port and Boundary Scan Architecture.
1
December 1999 – Revised April 2002
SPRS122E
Introduction
2
Introduction
This section describes the main features of the TMS320VC5441 digital signal processor (DSP), lists the pin
assignments, and describes the function of each pin. This data manual also provides a detailed description
section, electrical specifications, parameter measurement information, and mechanical data about the
available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1 Description
The TMS320VC5441 fixed-point digital signal processor is a quad-core solution running at 532-MIPS
performance. The 5441 consists of four DSP subsystems with shared program memory. Each subsystem
consists of one TMS320C54x DSP core, 32K-word program/data DARAM, 64K-word data DARAM, three
multichannel buffered serial ports, DMA logic, one watchdog timer, one general-purpose timer, and other
miscellaneous circuitry.
The 5441 also contains a host-port interface (HPI) that allows the 5441 to be viewed as a memory-mapped
peripheral to a host processor.
Each subsystem has its separate program and data spaces, allowing simultaneous accesses to program
instructionsanddata. Tworeadoperationsandonewriteoperationcanbeperformedinonecycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. Furthermore, data can
be transferred between program and data spaces. Such parallelism supports a powerful set of arithmetic,
logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5441 includes
the control mechanisms to manage interrupts, repeated operations, and function calls. In addition, the 5441
has a total of 256K words of shared program memory (128K words shared by subsystems A and B, and
another 128K words shared by subsystems C and D).
The 5441 is intended as a high-performance, low-cost, high-density DSP for remote data access or voice-over
IP subsystems. It is designed to maintain the current modem architecture with minimal hardware and software
impacts, thus maximizing reuse of existing modem technologies and development efforts.
The 5441 is offered in two temperature ranges and individual part numbers are shown below. (Please note
that the industrial temperature device part numbers do not follow the typical numbering tradition.)
Commercial temperature devices (0°C to 85°C)
TMS320VC5441PGF532 (176-pin LQFP)
TMS320VC5441GGU532 (169-ball BGA)
Industrial temperature range devices (–40°C to 100°C)
TMS320VC5441APGF532 (176-pin LQFP)
TMS320VC5441AGGU532 (169-ball BGA)
NOTE: Leading “x” in signal names identifies the subsystem; x = A, B, C, or D for subsystem A, B, C,
or D, respectively. Trailing “n” in signal names identifies the McBSP; n = 0, 1, or 2 for McBSP0, McBSP1,
or McBSP2, respectively.
TMS320C54x is a trademark of Texas Instruments.
2
SPRS122E
December 1999 – Revised April 2002
Introduction
2.2 Migration From the 5421 to the 5441
Customers who are migrating from the 5421 to the 5441 need to take into account the following differences
between the two devices.
•
The 5441 provides four cores in a 169-ball ball grid array (BGA) and a 176-pin low-profile quad flatpack
(LQFP).
•
•
The 5441 does not have a XIO interface for external memory connection.
Each subsystem includes a 32K-word DARAM program/data memory and a 64K-word DARAM data
memory.
•
•
•
•
•
The DMA has been changed and now provides no access to external memory.
The HPI and DMA memory maps have been changed to incorporate the new 5441 memory structure.
The 2K words of ROM on the 5421 is not implemented on the 5441.
The four McBSP1s and four McBSP2s have been internally multiplexed onto two sets of external pins.
The HPI_SEL1 and HPI_SEL2 pins on 5441 are used to facilitate HPI module selection among the four
subsystems.
•
•
•
The 5441 provides four watchdog timers (one per subsystem).
GPIO0 and GPIO1 pins are multiplexed with x_XF and x_BIO pins, respectively.
Only the global reset (RESET) will reset the PLL.
2.3 Pin Assignments
Figure 2–1 illustrates the ball locations for the 169-ball ball grid array (BGA) package and is used in
conjunction with Table 2–1 to locate signal names and ball grid numbers. Figure 2–2 illustrates the pin
locations for the 176-pin low-profile quad flatpack (LQFP); Table 2–2 lists each pin number and its associated
pin name for this package.
2.3.1 Pin Assignments for the GGU Package
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
Figure 2–1. 169-Ball GGU MicroStar BGA (Bottom View)
3
December 1999 – Revised April 2002
SPRS122E
Introduction
†
Table 2–1. Pin Assignments for TMS320VC5441GGU (169-Ball BGA Package)
BALL #
A1
SIGNAL NAME
BALL #
A2
SIGNAL NAME
BALL #
A3
SIGNAL NAME
BALL #
A4
SIGNAL NAME
HA[0]/HCNTL0
DV
V
SS
B_BDR0
DD
A5
CV
CV
A6
V
A7
DV
A8
V
DD
DD
SS
DD
SS
SS
DV
A9
A10
B1
D_BDR0
A11
B2
V
A12
B3
DD
A13
B4
D_BFSX0
B_BDX0
HA[1]/HCNTL1
B_BFSX0
HD[7]
B_BFSR0
HD[3]
B5
CV
CV
B6
B7
DD
DD
B8
HD[0]
B9
B10
C1
D_GPIO0/D_XF
B11
C2
D_BDX0
B12
C3
D_BFSR0
B_GPIO1/B_BIO
HD[4]
B13
C4
HA[18]
B_GPIO0/B_XF
D_GPIO3/D_TOUT
HA[15]
V
SS
HA[3]/B_HINT
B_BCLKR0
D_BCLKX0
CLKMD
C5
CV
CV
C6
DD
DD
SS
C7
C8
C9
C10
D1
C11
D2
HA[17]
C12
D3
C13
D4
V
B_NMI
B_RS
HA[4]/C_HINT
D_GPIO1/D_BIO
D_INT
D5
CV
CV
DD
DD
D6
B_BCLKX0
D_BCLKR0
D7
HD[5]
D8
D9
D10
E1
D11
E2
D_RS
D12
E3
D13
E4
TRST
B_INT
HD[1]
DV
TESTB
TDI
DD
E5
HA[2]/A_HINT
E6
B_GPIO3/B_TOUT
TESTD
E7
HD[6]
E8
E9
D_GPIO2/D_WTOUT
E10
F1
E11
F2
TMS
E12
F3
TCK
E13
F4
DV
DD
HAS
V
SSA
V
SS
HCS
F5
CLKIN
D_NMI
F6
B_GPIO2/B_WTOUT
EMU1/OFF
F7
HD[2]
F8
HA[16]
HPI_SEL1
EMU0
F9
F10
G1
G5
G9
G13
H4
F11
G2
G6
G10
H1
HPI_SEL2
F12
G3
G7
G11
H2
F13
G4
G8
G12
H3
V
SS
V
CCA
CV
DD
BCLKR2
HMODE
HR/W
BCLKX2
HDS2
HRDY
C_NMI
BDR1
RESET
BFSR2
HA[7]
CV
V
SS
DD
BFSX2
HD[9]
CLKOUT
C_GPIO1/C_BIO
BFSX1
H5
A_INT
H6
H7
H8
H9
BCLKX1
H10
J1
BCLKR1
H11
J2
BFSR1
BDR2
H12
J3
H13
J4
V
SS
DV
BDX2
A_RS
C_BCLKR0
BDX1
DD
J5
A_GPIO1/A_BIO
HA[11]
J6
HD[8]
J7
HD[13]
J8
J9
J10
K1
C_INT
J11
K2
C_RS
J12
K3
J13
K4
DV
V
SS
A_NMI
TDO
DD
A_GPIO3/A_TOUT
C_BCLKX0
TESTC
K5
CV
CV
K6
A_GPIO2/A_WTOUT
HA[13]
K7
HD[12]
DD
DD
K8
K9
K10
L1
K11
L2
HA[14]
K12
L3
K13
L4
HDS1
A_GPIO0/A_XF
HD[15]
HA[5]/D_HINT
HA[6]
HA[8]
L5
CV
CV
L6
A_BCLKR0
C_GPIO0/C_XF
DD
DD
SS
L7
HD[11]
L8
L9
L10
M1
M5
M9
M13
N4
L11
M2
M6
M10
N1
C_GPIO2/C_WTOUT
HA[9]
L12
M3
M7
M11
N2
HA[12]
L13
M4
M8
M12
N3
V
V
SS
A_BFSR0
HD[10]
A_BDR0
HD[14]
CV
CV
DD
DD
A_BCLKX0
C_GPIO3/C_TOUT
A_BFSX0
C_BDX0
C_BFSR0
HA[10]
DV
V
SS
A_BDX0
DD
N5
CV
CV
N6
V
N7
DV
N8
V
DD
DD
SS
DD
SS
SS
DV
N9
N10
C_BDR0
N11
V
N12
DD
N13
C_BFSX0
†
Cells highlighted in gray indicate pins that perform a multiplexed function.
4
SPRS122E
December 1999 – Revised April 2002
Introduction
2.3.2 Pin Assignments for the PGF Package
132
89
133
88
176
45
1
44
Figure 2–2. 176-Pin PGF Low-Profile Quad Flatpack (Top View)
5
December 1999 – Revised April 2002
SPRS122E
Introduction
†
Table 2–2. Pin Assignments for TMS320VC5441PGF (176-Pin LQFP Package)
PIN NO.
1
SIGNAL NAME
HA[0]/HCNTL0
HA[4]/C_HINT
B_NMI
PIN NO.
SIGNAL NAME
PIN NO.
SIGNAL NAME
PIN NO.
SIGNAL NAME
HA[3]/B_HINT
B_RS
2
HA[1]/HCNTL1
3
HA[2]/A_HINT
4
5
6
V
7
V
SS
8
SS
B_INT
9
10
11
CLKMD
HAS
12
TDI
13
TESTB
14
DV
15
16
HCS
DD
17
V
SS
18
V
SSA
19
CLKIN
20
HRDY
21
V
CCA
22
CV
23
CV
24
EMU0
DD
DD
25
BCLKR2
BFSX2
26
BCLKX2
CLKOUT
27
V
28
BFSR2
BDR2
SS
29
30
31
DV
32
DD
33
BDX2
34
V
SS
35
A_RS
36
A_NMI
37
A_INT
38
TDO
39
HA[5]/D_HINT
40
HA[6]
41
HA[7]
42
HA[8]
43
V
SS
44
HA[9]
45
A_BFSX0
A_GPIO3/A_TOUT
46
DV
47
A_GPIO1/A_BIO
A_GPIO0/A_XF
48
A_BFSR0
A_BDR0
DD
49
50
V
SS
51
52
53
CV
54
A_BDX0
A_GPIO2/A_WTOUT
HD[8]
55
CV
56
CV
DD
DD
SS
DD
DD
A_BCLKX0
DV
57
CV
58
59
A_BCLKR0
HD[9]
60
61
V
62
63
64
DD
65
DV
66
HD[10]
67
HD[11]
68
HD[12]
HD[15]
DD
69
HD[13]
C_BCLKX0
C_BDR0
70
V
SS
71
HD[14]
72
73
74
CV
CV
75
CV
76
CV
DD
DD
DD
SS
DD
77
78
79
C_GPIO3/C_TOUT
C_BDX0
80
C_BCLKR0
C_GPIO1/C_BIO
C_BFSR0
HA[12]
81
C_GPIO0/C_XF
C_GPIO2/C_WTOUT
C_BFSX0
HA[13]
82
V
83
84
85
86
DV
DD
HA[10]
87
DV
88
DD
89
90
91
HA[11]
HA[14]
C_RS
92
93
94
V
SS
95
96
TESTC
97
C_INT
98
HDS1
99
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
BDX1
101
105
109
113
117
121
125
129
133
137
141
145
149
153
157
161
165
169
173
BDR1
102
106
110
114
118
122
126
130
134
138
142
146
150
154
158
162
166
170
174
BCLKR1
103
107
111
115
119
123
127
131
135
139
143
147
151
155
159
163
167
171
175
DV
BFSR1
DD
BFSX1
V
SS
HR/W
BCLKX1
RESET
HPI_SEL1
TCK
HMODE
CV
C_NMI
DD
HDS2
EMU1/OFF
TRST
V
HPI_SEL2
TMS
SS
DV
DD
TESTD
D_INT
D_NMI
D_RS
V
V
HA[15]
SS
HA[17]
DV
SS
HA[18]
HA[16]
D_BFSR0
D_GPIO2/D_WTOUT
D_BCLKX0
D_BFSX0
D_BDX0
D_GPIO0/D_XF
DV
DD
D_BCLKR0
DD
V
SS
CV
CV
D_BDR0
D_GPIO1/D_BIO
HD[1]
CV
DD
DD
DD
SS
CV
D_GPIO3/D_TOUT
HD[2]
DD
HD[0]
DV
V
HD[3]
HD[4]
HD[5]
DD
HD[6]
V
SS
HD[7]
B_BCLKR0
B_BCLKX0
CV
CV
CV
DD
DD
DD
SS
DD
B_BDR0
CV
B_BDX0
B_GPIO3/B_TOUT
B_GPIO2/B_WTOUT
B_BFSX0
B_GPIO0/B_XF
B_GPIO1/B_BIO
V
B_BFSR0
DV
DV
DD
DD
†
Cells highlighted in gray indicate pins that perform a multiplexed function.
6
SPRS122E
December 1999 – Revised April 2002
Introduction
2.4 Signal Descriptions
Table 2–3 lists all the signals, grouped by function. See Section 2.3 for the exact pin locations based on the
package type. Pin functions highlighted in gray are secondary (multiplexed) functions.
Table 2–3. Signal Descriptions
†
NAME
TYPE
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
HA18 (MSB)
HA17
HA16
HA15
HA14
HA13
HA12
HA11
HA10
HA9
HPI address pins when HPI is in nonmultiplexed mode. HA18 is used to facilitate program (shared) memory and data
(local) memory selection.
The pins include bus holders to reduce power dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external pullup resistors on unused pins. When the address bus is not being driven by the
external host, the bus holders keep address pins at the last driven logic level. The address bus keepers are disabled
atglobalresetorsubsystemAreset, andcanbeenabled/disabledviatheBHA bit of the BSCR register in subsystemA.
‡
I
HA8
HA7
HA6
SECONDARY
HA5
HA4
HA3
HA2
D_HINT
C_HINT
B_HINT
A_HINT
§
O/Z
HA1
HA0 (LSB)
HCNTL1
HCNTL0
I
HD15 (MSB)
HD14
HD13
HD12
HD11
HD10
HD9
Parallel bidirectional data bus. These pins are the HPI data bus.
The pins include bus holders to reduce power dissipation caused by floating, unused pins. The bus holders also
eliminate the need for external pullup resistors on unused pins. When the data bus is not being driven by the 5441,
the bus holders keep data pins at the last driven logic level. The data bus keepers are disabled at global reset or
subsystem A reset, and can be enabled/disabled via the BHD bit of the BSCR register in subsystem A.
HD8
HD7
‡§
I/O/Z
HD6
HD5
HD4
HD3
HD2
HD1
HD0 (LSB)
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
7
December 1999 – Revised April 2002
SPRS122E
Introduction
Table 2–3. Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
HPImodeselect. Whenthispinislow, itselectstheHPImultiplexedaddress/datamode.Themultiplexedaddress/data
mode allows hosts with multiplexed address/data lines access to the HPI registers HPIA, HPIC, and HPID.
Host-to-DSP and DSP-to-host interrupts are supported in this mode.
¶
HMODE
I
I
When HMODE is high, it selects the HPI nonmultiplexed mode. HPI nonmultiplexed mode allows hosts with separate
address/databusestoaccesstheHPIaddressrangebywayofthe19-bitaddressbusandtheHPIdata(HPID)register
via the 16-bit data bus. Host-to-DSP and DSP-to-host interrupts are not supported in this mode.
HPI address latch enable (ALE) or address strobe input. Hosts with multiplexed address and data pins require HAS
to latch the address in the HPIA register. This signal is used only in HPI multiplexed address/data mode
(HMODE = 0).
¶#
HAS
HPI data ready output. The ready output informs the host when the HPI is ready for the next transfer. While driving,
it is in output state and while not driving, it is in high-Z state.
§
HRDY
HR/W
O/Z
I
I
I
HPI read/write strobe. This signal is used by the host to control the direction of an HPI transfer.
¶#
¶#
HDS1
HDS2
HPI data strobes. Driven by the host read and write strobes to control HPI transfers.
¶#
HCS
HPI chip select. Must be active during HPI transfers and can remain active between concurrent transfers.
PRIMARY
D_HINT
C_HINT
B_HINT
A_HINT
HA5
HA4
HA3
HA2
Host interrupt pins. HPI can interrupt the host by asserting this low. The host can clear this
interrupt by writing a “1” to the HINT bit of the HPIC register. Only supported in HPI
multiplexed address/data mode (HMODE pin low)
§
O/Z
I
I
HCNTL1
HCNTL0
HA1
HA0
HPI control pins. These pins select a host access to the HPIA, HPIC, and HPID registers.
Only supported in HPI multiplexed address/data mode (HMODE pin low)
I
I
HPI_SEL1
HPI_SEL2
Subsystem HPI module select
MULTICHANNEL BUFFERED SERIAL PORTS 0, 1, AND 2 SIGNALS
Receive clocks. x_BCLKR0 serve as the serial shift clocks for the buffered serial-port receiver. Input from an external
clock source for clocking data into the McBSP. When not being used as clocks, these pins can be used as
general-purpose I/Os by setting RIOEN = 1.
#
#
#
#
A_BCLKR0
B_BCLKR0
C_BCLKR0
D_BCLKR0
§
§
I/O/Z
x_BCLKR0 can be configured as outputs by way of the CLKRM bit in the PCR register.
#
#
#
#
A_BCLKX0
B_BCLKX0
C_BCLKX0
D_BCLKX0
Transmit clocks. Clock signals used to clock data from the transmit register. These pins can also be configured as
inputs by setting CLKXM = 0 in the PCR register. x_BCLKX0 can be sampled as inputs by way of the IN1 bit in the
SPC register. When not being used as clocks, these pins can be used as general-purpose I/Os by setting XIOEN = 1.
I/O/Z
A_BDR0
B_BDR0
C_BDR0
D_BDR0
Buffered serial data receive (input) pins. When not being used as data-receive pins, these pins can be used as
general-purpose I/Os by setting RIOEN = 1.
I
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
8
SPRS122E
December 1999 – Revised April 2002
Introduction
Table 2–3. Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORTS 0, 1, AND 2 SIGNALS (CONTINUED)
A_BDX0
Buffered serial-port transmit (output) pins. When not being used as data-transmit pins, x_BDX0 can be used as
general-purpose I/Os by setting XIOEN = 1.
B_BDX0
C_BDX0
D_BDX0
§
O/Z
A_BFSR0
B_BFSR0
C_BFSR0
D_BFSR0
Frame synchronization pins for buffered serial-port input data. The x_BFSR0 pulse initiates the receive-data process
over x_BDR0. When not being used as data-receive synchronization pins, these pins can be used as general-purpose
I/Os by setting RIOEN = 1.
§
§
I/O/Z
A_BFSX0
B_BFSX0
C_BFSX0
D_BFSX0
Buffered serial-port frame synchronization pins for transmitting data. The x_BFSX0 pulse initiates the transmit-data
process over the x_BDX0 pin. If x_RS is asserted when x_BFSX0 is configured as output, then x_BFSX0 is turned
into input mode by the reset operation. When not being used as data-transmit synchronization pins, these pins can
be used as general-purpose I/Os by setting XIOEN = 1.
I/O/Z
#
BCLKR1
Receive clock, multiplexed McBSP1
Transmit clock, multiplexed McBSP1
Receive data, multiplexed McBSP1
Transmit data, multiplexed McBSP1
Receive frame sync, multiplexed McBSP1
Transmit frame sync, multiplexed McBSP1
Receive clock, multiplexed McBSP2
Transmit clock, multiplexed McBSP2
Receive data, multiplexed McBSP2
Transmit data, multiplexed McBSP2
Receive frame sync, multiplexed McBSP2
Transmit frame sync, multiplexed McBSP2
CLOCKING SIGNALS
#
BCLKX1
BDR1
I
§
BDX1
O/Z
BFSR1
BFSX1
BCLKR2
I
#
#
BCLKX2
BDR2
I
§
BDX2
O/Z
BFSR2
BFSX2
I
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is
bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOUT bit of
the PMST register.
Multiplexed as shown below based on the selection bits in the GPIO register
§
CLKOUT
O/Z
GPIO[7]
GPIO[6]
A_CLKOUT
B_CLKOUT
C_CLKOUT
D_CLKOUT
0
0
1
1
0
1
0
1
(default)
||
||
||
#
CLKIN
I
I
Input clock to the device. CLKIN connects to a PLL.
#
CLKMD
Clock mode configuration pin at reset. When CLKMD = 0, bypasses PLL; when CLKMD = 1, CLKINx2
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
9
December 1999 – Revised April 2002
SPRS122E
Introduction
Table 2–3. Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
GENERAL-PURPOSE I/O PINS
A_GPIO0/
A_XF
Subsystem A GPIO0/
Subsystem A external flag output
These pins act according to the
general-purpose I/O register. The
x_XF bit must be set to “1” to drive the
x_XF output on the pin. If x_XF=0,
then these pins are general-purpose
I/Os.
B_GPIO0/
B_XF
Subsystem B GPIO0/
Subsystem B external flag output
§
I/O/Z
I/O/Z
I/O/Z
I/O/Z
C_GPIO0/
C_XF
Subsystem C GPIO0/
Subsystem C external flag output
D_GPIO0/
D_XF
Subsystem D GPIO0/
Subsystem D external flag output
A_GPIO1/
A_BIO
Subsystem A GPIO1/
Subsystem A branch control input
These pins act according to the
general-purpose I/O register. The
x_BIObitmustbesetto“1”todrivethe
x_BIO input into the device. If
x_BIO=0, then these pins are
general-purpose I/Os.
B_GPIO1/
B_BIO
Subsystem B GPIO1/
Subsystem B branch control input
§
C_GPIO1/
C_BIO
Subsystem C GPIO1/
Subsystem C branch control input
General-purpose I/O pins (software-
programmable I/O signal). Values
can be latched (output) by writing into
theGPIOregister. ThestatesofGPIO
pins (inputs) can be determined by
reading the GPIO register. The GPIO
direction is also programmable by
way of the DIRn field in the register.
register
D_GPIO1/
D_BIO
Subsystem D GPIO1/
Subsystem D branch control input
A_GPIO2/
A_WTOUT
Subsystem A GPIO2/
Subsystem A watchdog timer output
The watchdog enable (WDEN) bit in
B_GPIO2/
B_WTOUT
Subsystem B GPIO2/
Subsystem B watchdog timer output
the
watchdog
timer
(WDTSCR) is used to multiplex the
watchdog timer output and GPIO2. If
WDEN=0, then these pins are
general-purpose I/Os.
§
C_GPIO2/
C_WTOUT
Subsystem C GPIO2/
Subsystem C watchdog timer output
D_GPIO2/
D_WTOUT
Subsystem D GPIO2/
Subsystem D watchdog timer output
A_GPIO3/
A_TOUT
Subsystem A GPIO3/
Subsystem A timer output
These pins act according to the
general-purpose I/O register. The
X_TOUT bit must be set to “1” to drive
the timer output on the pin. If
X_TOUT=0, then these pins are
general-purpose I/Os.
B_GPIO3/
B_TOUT
Subsystem B GPIO3/
Subsystem B timer output
§
C_GPIO3/
C_TOUT
Subsystem C GPIO3/
Subsystem C timer output
D_GPIO3/
D_TOUT
Subsystem D GPIO3/
Subsystem D timer output
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
10
SPRS122E
December 1999 – Revised April 2002
Introduction
Table 2–3. Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
¶#
¶#
¶#
A_INT
B_INT
C_INT
D_INT
External user interrupts. A_INT–D_INT are prioritized and are maskable by the interrupt mask register (IMR) and the
interrupt mode bit. The status of these pins can be polled and reset by way of the interrupt flag register (IFR).
I
¶#
¶#
¶#
¶#
A_NMI
B_NMI
C_NMI
D_NMI
Nonmaskableinterrupts.x_NMIisanexternalinterruptthatcannotbemaskedbywayoftheINTMbitortheIMR.When
x_NMI is activated, the processor traps to the appropriate vector location.
I
¶#
#
#
#
#
A_RS
B_RS
C_RS
D_RS
Reset. x_RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU
andperipherals. Whenx_RS is brought to a high level, execution begins at location0FF80hofprogrammemory. x_RS
affects various registers and status bits.
I
I
#
RESET
Global/HPI reset. This signal resets the four subsystems and the HPI.
SUPPLY PINS
V
CCA
Dedicated power supply that powers the PLL. V = 1.6 V
DD
CV
Dedicated power supply that powers the core CPUs. CV = 1.6 V
DD
DD
DD
DV
Dedicated power supply that powers the I/O pins. DV
DD
= 3.3 V
S
V
V
Digital ground. Dedicated ground plane for the device.
SS
Analog ground. Dedicated ground for the PLL. V
separated.
can be connected to V
if digital and analog grounds are not
SSA
SS
SSA
EMULATION/TEST PINS
||
||
||
TESTB
TESTC
TESTD
No connection
Standard test clock. This is normally a free-running clock signal with a 50% duty cycle. Changes on the test access
port (TAP) input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test-data
register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
¶#
TCK
I
I
Test data input. Pin with an internal pullup device. TDI is clocked into the selected register (instruction or data) on a
rising edge of TCK.
¶
TDI
Test data pin. The contents of the selected register is shifted out of TDO on the falling edge of TCK. TDO is in
high-impedance state except when the scanning of data is in progress.
§
O/Z
TDO
TMS
Test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising
edge of TCK.
¶
I
I
Test reset. When high, TRST gives the scan system control of the operations of the device. If TRST is driven low, the
device operates in its functional mode and the IEEE 1149.1 signals are ignored. Pin with internal pulldown device.
TRSTꢃ
Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF condition.
When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as I/O.
EMU0
I/O/Z
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
11
December 1999 – Revised April 2002
SPRS122E
Introduction
Table 2–3. Signal Descriptions (Continued)
†
NAME
TYPE
DESCRIPTION
EMULATION/TEST PINS (CONTINUED)
Emulator interrupt 1 pin. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system
and is defined as I/O. When TRST transitions from high to low, then EMU1 operates as OFF. EMU/OFF = 0 puts all
output drivers into the high-impedance state.
EMU1/OFF
I/O/Z
Note that OFF is used exclusively for testing and emulation purposes (and not for multiprocessing applications).
Therefore, for the OFF condition, the following conditions apply:
TRST = 0, EMU0 = 1, EMU1 = 0
†
‡
§
I = Input, O = Output, S = Supply, Z = High Impedance
This pin has an internal bus holder controlled by way of the BSCR register in TMS320C54x cLEAD core of DSP subsystem A.
This pin is placed in high-impedance when the EMU1/OFF pin operates as OFF and when EMU1/OFF = 0, this case is exclusively for testing
and emulation purposes.
¶
#
||
This pin has an internal pullup resistor.
These pins are Schmitt triggered inputs.
This pin is used by Texas Instruments for device testing and should be left unconnected.
ꢃ This pin has an internal pulldown resistor.
NOTE: Pins highlighted in grey indicate the multiplexed function of the pin.
12
SPRS122E
December 1999 – Revised April 2002
Functional Overview
3
Functional Overview
The functional overview in this section is based on the overall system block diagram in Figure 3–1 and the
typical subsystem block diagram in Figure 3–2.
GPIO
Shared P Bus
GPIO
DSP
DSP
Subsystem A
DSP ID: 0000
Subsystem B
DSP ID: 0001
McBSP0
McBSP1
McBSP2
McBSP0
McBSP1
McBSP2
PLL
HPI
HPI
SA1
SA2
McBSP1
McBSP2
XA
HPI
HPI
McBSP2
McBSP1
McBSP0
McBSP2
McBSP1
McBSP0
DSP
Subsystem C
DSP ID: 0010
DSP
Subsystem D
DSP ID: 0011
GPIO
Shared P Bus
GPIO
Figure 3–1. Overall Functional Block Diagram
DSP Subsystem
P. C. D. E. Busses and Control Signals
32K-Word
Program/Data
DARAM
TMS320C54x cLEAD
(Core)
64K-Word
Data DARAM
64K-Word
Program DARAM
M Bus
3 × McBSP
M Bus
Timer
WDTimer
GPIO
DMA
M Bus
M Bus
HPI
HPI Bus
Shared P Bus
Figure 3–2. Typical Subsystem Functional Block Diagram
13
December 1999 – Revised April 2002
SPRS122E
Functional Overview
3.1 Memory
Each 5441 DSP subsystem maintains the peripheral register memory map and interrupt location/priorities of
the standard 5421. Each individual subsystem CPU memory map is illustrated in Figure 3–3 through
Figure 3–6.
The arbitration and access for local program/data memory and local data memory is based on a 16K-word
block size. The arbitration and access for all the shared memory is based on a 32K-word block size.
3.1.1 Memory Maps
Figure 3–3 through Figure 3–6 illustrate the CPU memory maps for subsystem A through subsystem D.
Figure 3–7 provides a detailed memory map of the local data memory relative to CPU subsystems A, B, C,
and D.
Memory Map with OVLY = 1
Page 1
Page 0
Page 2 Page 3
0000h
8000h
MPDA
MPDA
MPDA
MPDA
MPDA
MDA0
or
MDA1
MPAB0
MPAB1
MPAB2
MPAB3
FFFFh
Data Memory
Program Memory
Memory Map with OVLY = 0
Page 0
Page 1
Page 2
Page 3
0000h
8000h
MPDA
MPAB3
MPAB0
MPAB3
MPAB3
MPAB3
MDA0
or
MDA1
MPAB1
MPAB2
FFFFh
Data Memory
Program Memory
: reserved
NOTES: A. MPDA: local program/data memory in subsystem A
B. MDA: local data memory in subsystem A. MDA is controlled by the data memory map register (DMMR).
DMMR=0, MDA0 is mapped in 8000h – FFFFh.
DMMR=1, MDA1 is mapped in 8000h – FFFFh.
C. MPAB: shared program memory in subsystems A and B
Figure 3–3. Subsystem A CPU Memory Map
14
SPRS122E
December 1999 – Revised April 2002
Functional Overview
Memory Map with OVLY = 1
Page 0
Page 1
Page 2 Page 3
0000h
MPDB
MPDB
MPDB
MPDB
MPDB
8000h
MDB0
or
MDB1
MPAB0
MPAB1
MPAB2
MPAB3
FFFFh
Data Memory
Program Memory
Memory Map with OVLY = 0
Page 1
Page 0
Page 2
Page 3
0000h
8000h
MPDB
MPAB3
MPAB3
MPAB1
MPAB3
MPAB3
MDB0
or
MDB1
MPAB0
MPAB2
FFFFh
Data Memory
Program Memory
: reserved
NOTES: A. MPDB: local program/data memory in subsystem B
B. MDB: local data memory in subsystem B. MDB is controlled by the data memory map register (DMMR).
DMMR=0, MDB0 is mapped in 8000h – FFFFh.
DMMR=1, MDB1 is mapped in 8000h – FFFFh.
C. MPAB: shared program memory in subsystems A and B
Figure 3–4. Subsystem B CPU Memory Map
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Memory Map with OVLY = 1
Page 0
Page 1
Page 2 Page 3
0000h
MPDC
MPDC
MPDC
MPDC
MPDC
8000h
MDC0
or
MDC1
MPCD0
MPCD1
MPCD2
MPCD3
FFFFh
Data Memory
Program Memory
Memory Map with OVLY = 0
Page 0
Page 1
Page 2
Page 3
0000h
8000h
MPDC
MPCD3
MPCD0
MPCD3
MPCD1
MPCD3
MPCD3
MDC0
or
MDC1
MPCD2
FFFFh
Data Memory
Program Memory
: reserved
NOTES: A. MPDC: local program/data memory in subsystem C
B. MDC: local data memory in subsystem C. MDC is controlled by the data memory map register (DMMR).
DMMR=0, MDC0 is mapped in 8000h – FFFFh.
DMMR=1, MDC1 is mapped in 8000h – FFFFh.
C. MPCD: shared program memory in subsystems C and D
Figure 3–5. Subsystem C CPU Memory Map
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Functional Overview
Memory Map with OVLY = 1
Page 0
Page 1
Page 2
Page 3
0000h
8000h
MPDD
MPDD
MPDD
MPDD
MPDD
MDD0
or
MDD1
MPCD0
MPCD1
MPCD2
MPCD3
FFFFh
Data Memory
Program Memory
Memory Map with OVLY = 0
Page 0
Page 1
Page 2
Page 3
0000h
8000h
MPDD
MPCD3
MPCD0
MPCD3
MPCD1
MPCD3
MPCD3
MDD0
or
MDD1
MPCD2
FFFFh
Data Memory
Program Memory
reserved
NOTES: A. MPDD: local program/data memory in subsystem D
B. MDD: local data memory in subsystem D. MDD is controlled by the data memory map register (DMMR).
DMMR=0, MDD0 is mapped in 8000h – FFFFh.
DMMR=1, MDD1 is mapped in 8000h – FFFFh.
C. MPCD: shared program memory in subsystems C and D
Figure 3–6. Subsystem D CPU Memory Map
Figure 3–7 shows the CPU data memory map. The lower 32K-word data memory location in all pages is the
overlay area. Program memory has overlay area over the lower 32K words on all pages as well.
The overlay areas refer to:
1. When OVLY = 1, the lower 32K words of data space are mapped to the lower 32K words of all program
pages in the memory map.
2. WhenOVLY=0, thelower32Kwordsofdata spacearemappedonlytothelower32Kwordsofdataspace
and the lower 32K words of program page 3 are mapped to the lower 32K words of all program pages.
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Functional Overview
Hex
00 0000
Memory-
Mapped
Registers
00 005F
00 0060
DARAM0
16K Words
00 3FFF
00 4000
DARAM1
16K Words
00 7FFF
00 8000
DARAM2
(DMMR=0)
16K Words
DARAM4
(DMMR=1)
00 BFFF
00 C000
DARAM3
(DMMR=0)
16K Words
DARAM5
(DMMR=1)
00 FFFF
Data Memory
NOTE: The upper part of data memory is controlled by the Data Memory Map Register (DMMR).
1. DMMR=0, DARAM2 and DARAM3 are mapped in 8000h – FFFFh.
2. DMMR=1, DARAM4 and DARAM5 are mapped in 8000h – FFFFh.
Figure 3–7. Detailed Memory Map of Local Data Memory Relative to CPU Subsystems A, B, C, and D
3.1.2 On-Chip Dual-Access RAM (DARAM)
Each 5441 subsystem has 96K 16-bit words of on-chip DARAM (six blocks of 16K words). Each of these
DARAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store data
values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory
space (OVLY=0). The lower part of DARAM (0000h–8000h) can be mapped into program/data memory space
by setting the OVLY bit in the processor-mode status (PMST) register of the TMS320C54x cLEAD CPU in
each DSP subsystem.
3.1.3 On-Chip Two-Way Shared RAM
There are 128K 16-bit words of on-chip RAM (four blocks of 32K words) that are shared between subsystems
A and B. There are 128K 16-bit words of on-chip RAM (four blocks of 32K words) that are shared between
subsystems C and D. This memory is intended to store program only. Both subsystems are able to make one
instruction fetch from any location in the two-way shared memory each cycle simultaneously. No subsystem
CPU can write to the shared memory as only the DMA can write to shared memory.
If any of the CPU program fetches are requested at the same time as an M-bus transfer request, the CPU is
stalled until all M bus transfers are completed. In other words, any read or write requested by the M bus (driven
by DMA controller or HPI) has priority over the CPUs’ (A, B, C, and D) program fetches. The M-bus reads or
writes always take two cycles to complete.
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Functional Overview
3.1.4 Extended Data Memory
The data memory space of each 5441 subsystem addresses 128K 16-bit words. There are two pages of data
memory location with each page consisting of 64K words. The 5441 device uses a data memory map register
(DMMR)tofacilitateextendeddatamemoryaccess. TheDMMRisaperipheralmemory-mappedregister. The
contents of the DMMR register, once being written with an extended data number by the DSP CPU, will be
associated with the address decoding for all the data memory CPU accesses.
3.1.5 Extended Program Memory
The 5441 device uses a paged extended memory scheme in program space to allow access to 256K 16-bit
words. This extended program memory (each subsystem) is organized into four pages (0–3), pages 0–3 are
two-way shared memory. Each page is 64K words in length. The program counter extension register (XPC)
defines the program page selection. To implement the extended program memory scheme, the 5441 device
includes the following feature:
•
Two C54x instructions allow each subsystem CPU access to the on-chip program memory.
–
–
READA – Read program memory addressed by accumulator A and store in data memory
WRITA – Write data to program memory addressed by accumulator A
(Writes not allowed for CPUs to shared program memory)
3.1.6 Program Memory
The program memory is accessible on multiple pages, depending on the XPC value. Within these pages,
memory is accessible depending on the address range.
•
•
Access in the lower 32K words of each page is dependent on the state of OVLY.
–
–
OVLY = 0 – Program memory is accessed from program memory page 3 for all values of XPC.
OVLY = 1 – Program memory is accessed from local data/program DARAM for all values of XPC.
Access in the upper 32K words of each page is dependent on the state of OVLY.
–
–
OVLY = 0 – All pages of program memory except page 3 (which is reserved) are accessible for all
values of XPC.
OVLY = 1 – All pages of program memory are accessible for all values of XPC.
3.1.7 Data Memory
Accesses on extended data spaces are dependent on the value of the data memory map register (DMMR).
Within the page, memory is accessible depending on the address range.
•
Access in the lower 32K words
Data memory is accessed from local data/program DARAM for all values of DMMR.
Access in the upper 32K words
–
•
–
–
Which data memory block is accessed depends on the value of DMMR.
There are four 16K-word DARAM blocks for the upper addresses (8000h – FFFFh)
DMMR=0: DARAM2 and DARAM3 are mapped to the upper addresses
DMMR=1: DARAM4 and DARAM5 are mapped to the upper addresses
3.1.8 I/O Memory
The 5441 does not support I/O memory accesses.
C54x is a trademark of Texas Instruments.
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Functional Overview
3.1.9 Multicore Reset Signals
The 5441 device includes five reset signals: A_RS, B_RS, C_RS, D_RS, and RESET. The A_RS, B_RS,
C_RS, and D_RS local reset signals function as the CPU reset signal for subsystem A, B, C, and D,
respectively. The RESET services as a global reset for the whole device.
The global reset (RESET) is a superset of local resets A_RS, B_RS, C_RS, and D_RS. The assertion of
RESET triggers all the local resets; however, none of the local resets triggers the global reset. The local reset
signals reset the state of the CPU registers and CPU memory-mapped peripheral registers, and upon release,
initiate the reset function. The global reset, RESET, resets the on-chip PLL and clears the watchdog timer flag
(WDFLAG) bit. The local reset signals are not able to reset the PLL or clear the WDFLAG.
Theglobalreset(RESET)andlocalresets(x_RS)clearstheprogramcounterextensionregister(XPC)tozero
while the RESET instruction does not affect the XPC.
3.1.10 Device Bootload
The 5441 device supports an HPI boot sequence, which is used to download code while the DSP is in reset.
The external master holds the device in reset while it loads code to the on-chip memory of each subsystem,
subsystem selection is made by HPI_SEL1 and HPI_SEL2 signals. The host can release the 5441 from reset
by using either of the following methods.
•
If the x_RS (x = A, B, C, or D for subsystem A, B, C, or D, respectively) pins are held low while RESET
transitions from low to high, the reset of each subsystem will be controlled by the x_RS pins. When the
host has finished downloading code, it can drive x_RS high to release the cores from reset.
•
If the x_RS pins are held high while RESET transitions from low to high, the subsystems will stay in reset
until an HPI data write to address 0x2F occurs. This means the host can download code to subsystem
x and then release core x from reset by writing any data to core x’s address 0x2F via the HPI. The host
can then repeat the sequence for other cores. This mode allows the host to control 5441 reset without
additional hardware.
3.2 On-Chip Peripherals
All the C54x devices have the same CPU structure; however, they have different on-chip peripherals
connected to their CPUs. The on-chip peripheral options provided are:
•
•
•
•
•
•
•
DMA controller
16-bit host-port interface I/O ports
Multichannel buffered serial ports (McBSPs)
A hardware timer
A hardware watchdog timer
A software-programmable clock generator using a phase-locked loop (PLL)
General-purpose I/O
3.2.1 Direct Memory Access (DMA) Controller
The 5441 includes four 6-channel direct memory access (DMA) controllers for performing data transfers
independent of the CPU, one controller for each subsystem. The primary function of the 5441 DMA controller
is to provide code overlays and to manage data transfers between on-chip memory, the peripherals, and
off-chip host.
In the background of CPU operation, the 5441 DMA allows movement of data between internal program/data
memory and internal peripherals, such as the McBSPs and the HPI. Each subsystem has its own independent
DMA with six programmable channels, which allows for six different contexts for DMA operation. The HPI has
a dedicated auxiliary DMA channel. The remapped areas represent address aliasing for DMA accesses within
each subsystem. Figure 3–8 through Figure 3–11 illustrate the local DMA memory map of each subsystem.
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Functional Overview
Page 1
MPDA
Page 0
MPDA
Page 2
MPDA
Page 3
MPDA
Page 0 Page 1
0000h
0020h
0060h
MPDA
MPDA
8000h
FFFFh
MPAB0
MPAB1
MPAB0
MPAB1
MDA0
MDA1
Data Memory
Program Memory
Reserved
McBSP DXR/DRR MMRegs only
: Remapped areas
NOTES: A. MPDA: local program/data memory in subsystem A
B. MDA: local data memory in subsystem A
C. MPAB: two-way shared program memory in subsystems A and B
Figure 3–8. Subsystem A Local DMA Memory Map
Page 1
Page 0
Page 2
Page 3
Page 0 Page 1
0000h
0020h
0060h
MPDB
MPDB
MPDB
MPDB
MPDB
MPDB
8000h
MDB0
MDB1
MPAB2
MPAB3
MPAB2
MPAB3
FFFFh
Data Memory
Reserved
Program Memory
McBSP DXR/DRR MMRegs only
: Remapped areas
NOTES: A. MPDB: local program/data memory in subsystem B
B. MDB: local data memory in subsystem B
C. MPAB: two-way shared program memory in subsystems A and B
Figure 3–9. Subsystem B Local DMA Memory Map
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Functional Overview
Page 1
Page 0
Page 2
Page 3
Page 0 Page 1
0000h
0020h
0060h
MPDC
MPDC
MPDC
MPDC
MPDC
MPDC
8000h
FFFFh
MDC0
MDC1
MPCD0
MPCD1
MPCD0
MPCD1
Data Memory
Program Memory
McBSP DXR/DRR MMRegs only
Reserved
: Remapped areas
NOTES: A. MPDC: local program/data memory in subsystem C
B. MDC: local data memory in subsystem C
C. MPCD: two-way shared program memory in subsystems C and D
Figure 3–10. Subsystem C Local DMA Memory Map
Page 1
Page 0
Page 2 Page 3
Page 0 Page 1
0000h
0020h
0060h
MPDD
MPDD
MPDD
MPDD
MPDD
MPDD
8000h
MDD0
MDD1
MPCD2
MPCD3
MPCD2
MPCD3
FFFFh
Data Memory
Reserved
Program Memory
McBSP DXR/DRR MMRegs only
: Remapped areas
NOTES: A. MPDD: local program/data memory in subsystem D
B. MDD: local data memory in subsystem D
C. MPCD: two-way shared program memory in subsystems C and D
Figure 3–11. Subsystem D Local DMA Memory Map
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Functional Overview
3.2.1.1 DMA Controller Features
The 5441 DMA has the following features:
•
•
•
•
•
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU.
Each channel has independently programmable priority.
Each channel’s source and destination address registers include configurable indexing modes. The
addresscanbeheldconstant, postincremented, postdecremented, oradjustedbyaprogrammablevalue.
Each read or write transfer can be initialized by selected events.
The DMA supports single-word (16-bit) and double-word (32-bit) transfers.
Each DMA channel has independent reload registers.
•
•
•
•
•
Each DMA channel has independent extended source/destination data page registers.
The DMA does not support I/O memory access.
A 16-bit DMA transfer requires four CPU clock cycles to complete—two cycles for reads and two cycles for
writes. Since the DMA controller shares the DMA bus with the HPI module, the DMA access rate is reduced
when the HPI is active.
3.2.1.2 DMA Reload Registers
Each DMA channel has its own reload registers which are utilized when autoinitialization is enabled for the
current DMA channel. The reload registers include:
•
•
•
•
Source address reload register (DMGSAn)
Destination address reload register (DMGDAn)
Element count reload register (DMGCRn)
Frame count reload register (DMGFRn)
The “n” in the register names refers to DMA channel number: 0, 1, 2, 3, 4, and 5.
In the DMPREC register, bit 14 (IAUTO) is used to enable individual reload register for each channel. If that
bit is not set, the channel 0 reload register will be loaded to all chanels (this is backward compatible).
3.2.1.3 Extended Source/Destination Data Page Registers (DMSRCDPn/DMDSTDPn)
The DMA controller has the ability to perform transfers to and from the extended data memory space. The
DMA extended source data page register and extended destination data page register service this purpose
and only the least significant seven bits are used to designate the extended data memory page. Each of the
DMAchannels will have one set of these registers for extended data memory page (other than page 0)access.
Data memory space transfers cannot cross 64K page boundaries. If a data page boundary is crossed during
a transfer, the next transfer will wrap on to the same page.
For detailed information on DMA registers, see TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals (literature number SPRU302).
3.2.1.4 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization
event for a channel. The list of possible events and the DSYN values are shown in Table 3–1.
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December 1999 – Revised April 2002
SPRS122E
Functional Overview
Table 3–1. DMA Synchronization Events
DSYN VALUE
0000b
DMA SYNCHRONIZATION EVENT
No synchronization used
0001b
0010b
McBSP0 Receive Event
McBSP0 Transmit Event
McBSP2 Receive Event
McBSP2 Transmit Event
McBSP1 Receive Event
McBSP1 Transmit Event
Reserved
0011b
0100b
0101b
0110b
0111b – 1111b
3.2.1.5 DMA Channel Interrupt Selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2,
and 3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the
receive and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the 5441 is reset, the
interrupts from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and
enable control (DMPREC) register can be used to select these interrupts, as shown in Table 3–2.
Table 3–2. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7] IMR/IFR[10] IMR/IFR[11]
BXINT2
BXINT2
DMAC1
BRINT1
DMAC2
DMAC2
BXINT1
DMAC3
DMAC3
10b
11b
Reserved
3.2.2 16-Bit Bidirectional Host-Port Interface (HPI16)
3.2.2.1 HPI16 Memory Map
The HPI16 is an enhanced 16-bit version of the C54x DSP 8-bit host-port interface (HPI). The HPI16 is
designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the
interface. Each HPI subsystem memory map is identical to its corresponding DMA memory map except the
HPI memory map does not support accesses to any memory-mapped registers.
Some of the features of the HPI16 include:
•
•
•
•
A 16-bit bidirectional data bus
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
Multiplexed and nonmultiplexed address/data modes
A 19-bit address bus used in nonmultiplexed mode to allow access to all on-chip (including extended
address pages) memory
•
A 19-bit address register used in multiplexed mode. Includes address autoincrement feature for faster
accesses to sequential addresses
•
•
•
Interface to on-chip DMA module to allow access to entire on-chip memory space
HRDY signal to hold off host accesses due to DMA latency
Control register available in multiplexed mode only. Accessible by either host or DSP to provide host/DSP
interrupts, extended addressing, and data prefetch capability
•
•
HPI_SEL1 and HPI_SEL2 pins are used to make selection among the four subsystem HPI modules.
Both the HPI data bus and address bus have bus-holder features. The bus holders can be
enabled/disabled by the CPUs.
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Functional Overview
3.2.2.2 HPI Multiplexed Mode
In multiplexed mode, HPI16 operation is very similar to that of the standard 8-bit HPI, which is available with
other C54x DSP products. A host with a multiplexed address/data bus can access the HPI16 data register
(HPID), address register (HPIA), or control register (HPIC) via the HD bidirectional data bus. The host initiates
the access with the strobe signals (HDS1, HDS2, HCS) and controls the type of access with the HCNTL,
HR/W, and HAS signals. The DSP can interrupt the host via the x_HINT signal, and can stall host accesses
via the HRDY signal. Bit 20 of the HPIA register is used to make selection between program (shared) memory
and data (local) memory access. Table 3–3 shows the memory selection via HA[20].
Table 3–3. HPI Local/Shared Memory Selection Via HA[20]
HA[20]
Memory Type
0
1
Local (data)
Shared (program)
3.2.2.3 Host/DSP Interrupts
In multiplexed mode, the HPI16 offers the capability for the host and DSP to interrupt each other through the
HPIC register.
For host-to-DSP interrupts, the host must write a “1” to the DSPINT bit of the HPIC register. This generates
an interrupt to the DSP. This interrupt can also be used to wake the DSP from any of the IDLE 1,2, or 3 states.
Note that the DSPINT bit is always read as “0” by both the host and DSP. The DSP cannot write to this bit (see
Figure 3–12).
For DSP-to-host interrupts, the DSP must write a “1” to the HINT bit of the HPIC register to interrupt the host
via the x_HINT pin. The host acknowledges and clears this interrupt by also writing a “1” to the HINT bit of the
HPIC register. Note that writing a “0” to the HINT bit by either host or DSP has no effect.
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SPRS122E
Functional Overview
3.2.2.4 HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the 16-bit HD bidirectional data bus, and the address register (HPIA) via the 19-bit HA address bus. The
HA[18] signal is used to make selection between program (shared) memory and data (local) memory access.
Table 3–4 shows the memory selection via HA[18].
Table 3–4. HPI Local/Shared Memory Selection Via HA[18]
HA[18]
Memory Type
0
1
Local (data)
Shared (program)
The host initiates the access with the strobe signals (HDS1, HDS2, and HCS) and controls the direction of
the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC
register is not available in nonmultiplexedmodesincetherearenoHCNTLsignalsavailable. Allhostaccesses
initiate a DMA read or write access. Figure 3–12 shows a block diagram of the HPI16 in nonmultiplexed mode.
HPI-16
HOST
HD[15:0]
Data[15:0]
HPID[15:0]
DMA
†
HA[ :0]
n
†
Address[n:0]
R/W
Data strobes
Ready
HR/W
C54x
CPU
HDS1, HDS2, HCS
HRDY
†
n = 0 to 18
Figure 3–12. Interfacing to the HPI-16 in Non-Multiplexed Mode
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Functional Overview
3.2.2.5 HPI Bus Holder Control
Both the HPI data and address buses have bus holders. By default, the bus holders are disabled after global
reset or subsystem A reset. The bus holders are configured via the BHD and BHA bits in the bank switching
control register (BSCR) located at 29h in subsystem A. Figure 3–13 shows the BSCR bit layout for
subsystem A and Table 3–5 describes the bit functions of BSCR.
15
14
13
12
11
10
9
Reserved
U
8
7
6
5
4
3
2
1
0
Reserved
U
BHD
BHA
R/W+0 R/W+0
LEGEND: R = Read, W = Write, U = Undefined
Figure 3–13. BSCR Register Bit Layout for Subsystem A
Table 3–5. BSCR Register Bit Functions for Subsystem A
BIT
NO.
BIT
NAME
FUNCTION
15–3
Reserved These bits are reserved and are read as 0.
Data bus holder. BHD is cleared to 0 at reset.
2
BHD
BHD = 0: The HPI data bus holder is disabled.
BHD = 1: The HPI data bus holder is enabled.
Address bus holder. BHA is cleared to 0 at reset.
BHA = 0: The HPI address bus holder is disabled.
BHA = 1: The HPI address bus holder is enabled.
1
0
BHA
Reserved This bit is reserved and is read as 0.
3.2.2.6 Other HPI16 System Considerations
•
Operation During IDLE – The HPI16 can continue to operate during IDLE1 or IDLE2 by using special clock
management logic that turns on relevant clocks to perform a synchronous memory access, and then turns
the clocks back off to save power. The DSP CPU does not wake up from the IDLE mode during this
process.
•
Downloading Code During Reset – The HPI16 can download code while the DSP is in reset. The system
provides a pin (RESET) that provides a way to take the HPI16 module out of reset while leaving the DSP
in reset.
•
•
Emulation considerations – The HPI16 can continue operation even when the DSP CPU is halted due to
debugger breakpoints or other emulation events.
XA Multiplexer – XA multiplexer controls the HPI data traffic from each subsystem to the device boundary.
The HPI module is the slave on the HPI bus. Figure 3–14 shows the 5441 block diagram with XA logic.
The XA basic function includes:
–
Making the HPI bus available for the selected subsystem HPI module according to HPI selection pins
HPI_SEL1/HPI_SEL2.
–
Granting HPI path to one of the subsystems at one time
•
TheHPI_SEL1andHPI_SEL2pinsareusedtoselecttheHPImoduleamongthefourcores. Theselection
is indicated in Table 3–6.
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December 1999 – Revised April 2002
SPRS122E
Functional Overview
HPI Bus
HPI Bus
HPI Bus
HPI Bus
DSP Subsystem A
DSP ID: 0000
HPI_SEL1
HPI_SEL2
DSP Subsystem B
DSP ID: 0001
XA
DSP Subsystem C
DSP ID: 0010
DSP Subsystem D
DSP ID: 0011
NOTE: XA is the MUXing logic for HPI access.
Figure 3–14. XA Multiplexer for HPI Access
Table 3–6. HPI Module Selection
HPI_SEL2
HPI_SEL1
SELECTED HPI MODULE
Subsystem A
0
0
1
1
0
1
0
1
Subsystem B
Subsystem C
Subsystem D
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Functional Overview
3.2.3 Multichannel Buffered Serial Port (McBSP)
The 5441 device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x
devices, codecs, and other devices in a system. There are twelve multichannel buffered serial ports (McBSPs)
on chip (three per subsystem).
The McBSP provides:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
Direct interface to:
–
–
–
–
–
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant device
AC97-compliant device
Serial peripheral interface (SPI)
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
3.2.3.1 McBSP Clock Source
The 5441 McBSPs allow either the receive clock pin (BCLKRn) or the transmit clock pin (BCLKXn) to be
configured as the input clock to the sample rate generator. This enhancement is enabled through two register
bits: bit 7 [the enhanced sample clock mode bit (SCLKME)] of the pin control register (PCR), and bit 13 [the
McBSP sample rate generator clock mode bit (CLKSM)] of the sample rate generator register 2 (SRGR2).
SCLKME is an addition to the PCR contained in the McBSPs on previous TMS320C5000 DSP platform
devices. The new bit layout of the PCR is shown in Figure 3–15. For a description of the remaining bits, see
TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302).
15
14
13
12
11
10
9
8
Reserved
R,+0
XIOEN
RW,+0
RIOEN
RW,+0
FSXM
RW,+0
FSRM
RW,+0
CLKXM
RW,+0
CLKRM
RW,+0
7
6
5
4
3
2
1
0
SCLKME
RW,+0
CLKS_STAT
R,+0
DX_STAT
R,+0
DR_STAT
R,+0
FSXP
RW,+0
FSRP
RW,+0
CLKXP
RW,+0
CLKRP
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–15. Pin Control Register (PCR)
TMS320C5000 is a trademark of Texas Instruments.
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December 1999 – Revised April 2002
SPRS122E
Functional Overview
Theselectionofthesamplerategenerator(SRG)clockinputsourceismadebythecombinationoftheCLKSM
and SCLKME bit values as shown in Table 3–7.
Table 3–7. Sample Rate Generator Clock Source Selection
SCLKME
CLKSM
SRG Clock Source
0
0
0
1
Reserved
CPU clock
BCLKRn pin
BCLKXn pin
1
1
0
1
When either of the bidirectional pins, BCLKRn or BCLKXn, is configured as the clock input, its output buffer
is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKRn pin is configured as
the SRG input. In this case, both the transmitter and receiver circuits can be synchronized to the SRG output
by setting PCR[9:8] for CLKXM = 1 and CLKRM = 1. However, the SRG output is only driven onto the BCLKXn
pin because the BCLKR output is automatically disabled.
3.2.3.2 Multichannel Selection
The McBSP supports independent selection of multiple channels for the transmitter and receiver. When
multiplechannelsareselected, eachframerepresentsatime-divisionmultiplexed(TDM)datastream. Inusing
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. Up to a maximum of 128 channels in a bit stream can be enabled or disabled.
The 5441 McBSPs have two working modes that are selected by setting the RMCME and XMCME bits in the
multichannel control registers MCR1x and MCR2x, respectively (see Figure 3–16 and Figure 3–17). For a
description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals
(literature number SPRU302).
•
In the first mode, when RMCME = 0 and XMCME = 0, there are two partitions (A and B), with each
containing 16 channels as shown in Figure 3–16 and Figure 3–17. This is compatible with the McBSPs
used in the 5420, where only 32-channel selection is enabled (default).
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
XMC
ME
Reserved
R,+0
XPBBLK
RW,+0
XPABLK
RW,+0
XCBLK
R,+0
XMCM
RW,+0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2
Figure 3–16. Multichannel Control Register 2 for McBSPx (MCR2x)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RMC
ME
Reserved
R,+0
RPBBLK
RW,+0
RPABLK
RW,+0
RCBLK
R,+0
RMCM
RW,+0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; x = McBSP 0,1, or 2
Figure 3–17. Multichannel Control Register 1 for McBSPx (MCR1x)
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December 1999 – Revised April 2002
Functional Overview
•
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128-channel selection
capability. Twelve registers (RCERCx–RCERHx and XCERCx–XCERHx) are used to enable the
128-channel selection. The subaddresses of the registers are shown in Table 3–24. These registers,
functionally equivalent to the RCERA0–RCERB1 and XCERA0–XCERB1 registers, are used to
enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the
128-channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112
to 127) of McBSP1 for each DSP subsystem. See Figure 3–18, Table 3–8, Figure 3–19, and Table 3–9
for bit layouts and functions of the receive and transmit registers.
15
RCERyz15
RW,+0
7
14
RCERyz14
RW,+0
6
13
RCERyz13
RW,+0
5
12
RCERyz12
RW,+0
4
11
RCERyz11
RW,+0
3
10
RCERyz10
RW,+0
2
9
8
RCERyz9
RW,+0
1
RCERyz8
RW,+0
0
RCERyz7
RW,+0
RCERyz6
RW,+0
RCERyz5
RW,+0
RCERy4
RW,+0
RCERyz3
RW,+0
RCERyz2
RW,+0
RCERyz1
RW,+0
RCERyz0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–18. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 3–8. Receive Channel Enable Registers for Partitions A to H
Bit
Name
Function
RCERyz[15:0]
15–0
Receive Channel Enable Register
RCERyz n = 0
RCERyz n = 1
Disables reception of nth channel in partition y.
Enables reception of nth channel in partition y.
Note:
y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
15
14
XCERyz14
RW,+0
6
13
XCERyz13
RW,+0
5
12
XCERyz12
RW,+0
4
11
XCERyz11
RW,+0
3
10
XCERyz10
RW,+0
2
9
8
XCERyz15
RW,+0
7
XCERyz9
RW,+0
1
XCERyz8
RW,+0
0
XCERyz7
RW,+0
XCERyz6
RW,+0
XCERyz5
RW,+0
XCERy4
RW,+0
XCERyz3
RW,+0
XCERyz2
RW,+0
XCERyz1
RW,+0
XCERyz0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–19. Transmit Channel Enable Registers Bit Layout for Partitions A to H
Table 3–9. Transmit Channel Enable Registers for Partitions A to H
Bit
Name
Function
XCERyz[15:0]
15–0
Transmit Channel Enable Register
XCERyz n = 0
XCERyz n = 1
Disables transmit of nth channel in partition y.
Enables transmit of nth channel in partition y.
LEGEND: y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
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Functional Overview
The McBSP is fully static and operates at arbitrarily low clock frequencies. For the maximum McBSP
multichannel operating frequency, see Section 5.10 of this data manual.
3.2.3.3 McBSP1 and McBSP2
The four McBSP1s from each subsystem share the same external signal pins. The four McBSP2s from each
subsystem share the same set of external signal pins. They can only operate in either of the following modes:
•
multichannel mode (x_BCLKR, x_BCLKX, x_BFSR, and x_BFSX are external and the McBSPs share
TDM stream with no single time slot assigned to more than one McBSP)
•
standardserialportmode(x_BCLKR, x_BCLKX, x_BFSR, andx_BFSXareexternalandonlyoneMcBSP
is enabled at one time).
For McBSP1 and McBSP2, no other mode is supported.
3.2.3.4 SA Multiplexer
The SA1 and SA2 multiplexers provide multiplexing for the four McBSP1s and the four McBSP2s from each
subsystem and present the data path to the device boundary. All the same functional pins from the four
McBSP1s are multiplexed together by SA1 and connect to the device external pins. All the same functional
pins from the four McBSP2s are multiplexed together by SA2 and connect to the device external pins. The
functional pins are: data receive (BDRn), data transmit (BDXn), receive frame sync (BFSRn), transmit frame
sync (BFSXn), receive shift clock (BCLKRn), and transmit shift clock (BCLKXn).
When McBSP operates in multichannel mode, software shall ensure that the same channel (time slot) not be
assigned by more than one subsystem. If more than one subsystem enables the same transmit time slot, the
results are undefined.
Figure 3–20 shows 5441 block diagram with SA1 logic; SA2 logic is identical.
DSP Subsystem A
DSP ID: 0000
DSP Subsystem B
DSP ID: 0001
DSP Subsystem C
DSP ID: 0010
DSP Subsystem D
DSP ID: 0011
McBSP1
McBSP1
McBSP1
McBSP1
SA1
NOTE: SA is the MUX/Arbitration logic for McBSP1 operation.
Figure 3–20. SA Multiplexer for McBSP1 Operation
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Functional Overview
3.2.4 Hardware Timer
Each 5441 subsystem has one independent software programmable timer. The memory-mapped registers
control the operation of the timer. The timer resolution is the clock rate of the CPU. The timer output shares
the pin with GPIO3 and is controlled by GPIO register bit 15.
The timer supports a 32-bit dynamic range. The timer consists of a programmable 16-bit main counter and
a programmable prescalar. The main counter is driven by the prescalar, which decrements by one at every
CPU clock. Once the prescalar reaches zero, the 16-bit counter decrements by one. When the 16-bit counter
decrements to zero, a maskable interrupt (TINT) is generated and the timer output pin (TOUT) asserts an
active-high pulse (2H – 2 ns, H = 0.5 clock cycle). The timer output pulse is driven on GPIO3 when the TOUT
bit is set to high in the GPIO register. When the timer is configured in continuous mode, the timer counter and
prescalar will be reloaded accordingly after the timer counter exhausts. The timer can be stopped, restarted,
reset, or disabled via the bits of the timer control register.
There are four 16-bit registers associated with the timer.
•
•
•
•
Timer counter register (TIM)
Timer period register (PRD)
Timer control register (TCR)
Timer second control register (TSCR)
3.2.4.1 TIM Register
This register is loaded with the period register (PRD) value and decrements once the PRD value is loaded.
3.2.4.2 PRD Register
This register is used to reload the timer counter register (TIM).
3.2.4.3 TCR Register
This register provides the control and status information. TCR bit fields are shown in Figure 3–21 and
described in Table 3–10.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SOFT FREE
R/W+0 R/W+0
PSC
TRB
R/W+0
TSS
R/W+0
TDDR
R/W+0
R/W+0
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–21. Timer Control Register (TCR)
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December 1999 – Revised April 2002
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Functional Overview
Table 3–10. TCR Bit Description
FUNCTION
BIT
NO.
BIT
NAME
15–12
Reserved
Register bit is reserved. Read 0, write has no effect.
Used in conjunction with the FREE bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
SOFT
11
10
When FREE = 0 and SOFT = 0 the timer stops immediately.
When FREE = 0 and SOFT = 1, the timer stops when the counter decrements to 0.
Used in conjunction with the SOFT bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
FREE
When FREE = 0, the SOFT bit selects the timer mode.
When FREE = 1, the timer runs free regardless of the SOFT bit.
9–6
PSC
TRB
Timer prescalar counter, used only when PREMD = 0 (in TSCR register) and the prescaler is in direct mode.
Timer reload. When TRB is set, TIM is loaded with the value in the PRD register and the PSC field is loaded with
the value in the TDDR field (when prescalar is in direct mode). TRB is always read a 0.
5
Timer stop status.
4
TSS
Stops or starts the timer at reset. TSS is cleared and the timer starts timing.
0 = timer is started
1 = timer is stopped
Timer prescalar.
Case 1: When PREMD = 0, TDDR is a 4-bit reload prescalar. When PSC decrements to 0, PSC is loaded with
the contents of TDDR.
Case 2: When PREMD = 1,TDDR is an indirect prescalar, the contents in TDDR is used to specify the timer
prescalar.
TDDR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
PRESCALAR
0001h
0003h
0007h
000Fh
001Fh
003Fh
007Fh
00FFh
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
7FFFh
FFFFh
3–0
TDDR
1000
1001
1010
1011
1100
1101
1110
1111
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December 1999 – Revised April 2002
Functional Overview
3.2.4.4 TSCR Register
This 16-bit register contains bits to set prescalar mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
PREMD
R/W+0
Reserved
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–22. Timer Second Control Register (TSCR)
Table 3–11. TSCR Bit Description
BIT
NO.
BIT
NAME
FUNCTION
15–13
Reserved
Register bit is reserved. Read 0, write has no effect.
Prescalar mode select bit.
PREMD
12
0 = direct mode, TDDR is a 4-bit reload prescalar (default value after reset).
1 = indirect mode, TDDR is used to select individual prescalar value.
Register bit is reserved. Read 0, write has no effect.
11–0
Reserved
Out of reset, the TIM and PRD registers are set to a maximum value of FFFFh, the PREMD bit (TSCR[12])
is set to 0, the TDDR field (TCR[3:0]) is cleared to 0, and the timer is started.
3.2.5 Watchdog Timer
Each subsystem contains a watchdog timer. The purpose of the watchdog timer is to prevent the system from
lock in case the software becomes trapped in loops with no controlled exit. The watchdog timer has a
“watchdog output” pin associated with it. This watchdog output pin is shared with the x_GPIO2/x_WTOUT pin;
once the watchdog timer is enabled, this pin is automatically configured as x_WTOUT. The watchdog timer
requires a special service sequence to be executed periodically. Without this periodic servicing, the watchdog
timercounterreacheszeroandtimesout. Consequently, anactive-lowpulsewillbeassertedonthe“watchdog
output” pin and an internal maskable interrupt will be triggered. The watchdog output (x_WTOUT) pin can be
gluelessly external-connected to the local hardware reset or NMI (nonmaskable interrupt). This allows
maximum flexibility in utilizing the watchdog as required by the particular application.
The watchdog timer is a prescaled 16-bit counter that supports up to a 32-bit dynamic range. Out of reset, the
watchdog is disabled in order to allow as much time as needed for code to be loaded into the 5441 on-chip
memory via the HPI. Prior to being enabled, the watchdog counter will, in fact, still count down from its initial
default value using the default prescalar value. When the counter reaches zero, a watchdog time-out event
will occur in that a WD interrupt (WDTINT) request will be sent to the core, and the WDFLAG will be set.
However, since all maskable interrupts are disabled by default at reset, the WDTINT will not be serviced by
the core. Additionally, the watchdog pin (x_WTOUT) is disconnected from the watchdog time-out event, so
no pulse will be generated on this pin. After this time-out, the counter and prescalar will be reloaded
automatically and the watchdog will continue to count, time out, reload, etc. After code-download, the
watchdog can be enabled to connect the x_WTOUT pin to the time-out event. To enable the watchdog, certain
sequence shall be followed as shown in Figure 3–25.
Once the watchdog is enabled, it cannot be disabled by software. It can be disabled by watchdog time-out,
local hardware reset, or global hardware reset. A special key sequence is provided to prevent the watchdog
frombeingaccidentallyservicedwhilethesoftwareistrappedinadeadlooporinsomeothersoftwarefailures.
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December 1999 – Revised April 2002
SPRS122E
Functional Overview
3.2.5.1 Watchdog Timer Registers
There are four 16-bit registers associated with the watchdog timer.
•
•
•
•
WD Timer Counter Register (WDTIM)
WD Timer Period Register (WDPRD)
WD Timer Control Register (WDTCR)
WD Timer Second Control Register (WDTSCR)
3.2.5.2 WDTIM Register
This register contains the 16-bit watchdog counter value. It is decremented once every watchdog clock cycle.
3.2.5.3 WDPRD Register
This register is used to reload the WD timer counter register (WDTIM).
3.2.5.4 WDTCR Register
This register provides the control and status information. WDTCR bit fields are as shown in Figure 3–23 and
are described in Table 3–12.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SOFT FREE
R/W+0 R/W+0
PSC
R
Reserved
TDDR
R/W+1111
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–23. Watchdog Timer Control Register (WDTCR)
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SPRS122E
December 1999 – Revised April 2002
Functional Overview
Table 3–12. WDTCR Bit Description
FUNCTION
BIT
NO.
BIT
NAME
15–12
Reserved
Register bit is reserved. Read 0, write has no effect.
Used in conjunction with the FREE bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
SOFT
11
10
When FREE = 0 and SOFT = 0 the timer stops immediately.
When FREE = 0 and SOFT = 1, the timer stops when the counter decrements to 0.
Used in conjunction with the SOFT bit to determine the state of the timer when a breakpoint is encountered in
the HLL debugger.
FREE
When FREE = 0, the SOFT bit selects the timer mode.
When FREE = 1, the timer runs free regardless of the SOFT bit.
Timer prescalar counter, used only when PREMD = 0 (in WDTSCR register) and the prescaler is in direct mode.
Register bit is reserved. Read 0, write has no effect.
9–6
5–4
PSC
Reserved
Timer prescalar.
Case 1: When PREMD = 0, TDDR is a 4-bit reload prescalar. When PSC decrements to 0, PSC is loaded with
the contents of TDDR.
Case 2: When PREMD = 1,TDDR is an indirect prescalar, the contents in TDDR is used to specify the timer
prescalar.
TDDR[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
PRESCALAR
0001h
0003h
0007h
000Fh
3–0
TDDR
001Fh
003Fh
007Fh
00FFh
1000
1001
1010
1011
1100
1101
1110
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
7FFFh
1111
FFFFh (Default)
3.2.5.5 WDTSCR Register
This 16-bit register contains bits to indicate watchdog flag, to enable watchdog, to set prescalar mode as well
as to provide the 12-bit WDKEY for watchdog service.
WDTSCR bit fields are shown in Figure 3–24 and are described in Table 3–13.
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December 1999 – Revised April 2002
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Functional Overview
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDFLAG
R/W+0
WDEN
R/W+0
Reserved
PREMD
R/W+1
WDKEY
R/W+0
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–24. Watchdog Timer Second Control Register (WDTSCR)
Table 3–13. WDTSCR Bit Description
BIT
BIT
NAME
FUNCTION
NO.
Watchdog flag bit. This bit can be cleared by enabling the watchdog timer, by device global reset, and by being
written with “1”.
15
14
WDFLAG
WDEN
It is set by a watchdog time-out.
0 =
1 =
No watchdog time-out occurred
Watchdog time-out occurred
Watchdog timer enable bit.
0 =
Watchdog disable. Default value after device reset. Watchdog output pin is disconnected to the
watchdog time-out event, counter starts to run.
1 =
Watchdog enable. Once enabled, the watchdog output pin is connected to the watchdog time-out
event, and can be disabled by watchdog time-out or reset.
13
12
Reserved
PREMD
WDKEY
Register bit is reserved. Read 0, write has no effect.
Prescalar mode select bit.
0 =
1 =
Direct mode, TDDR is 4-bit reload prescalar.
Indirect mode, TDDR is used to select individual prescalar value (default value after local or global
hardware reset).
11–0
12-bit watchdog reset key, only the sequence of a 5C6h followed by an A7Eh services the watchdog.
The watchdog has to be serviced periodically with the sequence of 5C6h followed by A7Eh, written to WDKEY
before the watchdog timer times out. Both 5C6h and A7Eh are allowed to be written to WDKEY. Only the
sequence of 5C6h followed by A7Eh, to WDKEY services the watchdog. Any other writes to WDKEY will
trigger the watchdog time-out immediately, and consequently:
•
•
•
the watchdog output pin will generate an active-low pulse (6H ns, H=0.5 clock cycle)
the WDFLAG bit in WDTSCR will be set to 1
the internal maskable WD interrupt (WD_TINT) will be triggered
Read from WDTSCR register will not cause time-out.
When the watchdog is in time-out state, the watchdog is disabled and WDEN is cleared. The watchdog output
pin (x_WTOUT) is disconnected to the watchdog time-out event. Finally, the timer is reloaded and continues
to run.
Out of reset, the watchdog is disabled, and reads and writes to the watchdog registers are allowed. Once 5C6h
is written to WDKEY in the WDTSCR register from the initial state, the watchdog enters the preactive state.
The next write to the WDTSCR register should be completed with a “1” written to WDEN and A7Eh written
to WDKEY. This causes the watchdog timer to enter the active state. Once the watchdog is enabled, it cannot
be disabled by software. Any writes to the WDTSCR register from the active or service states that do not write
5C6h or A7Eh to WDKEY will result in an immediate watchdog time-out. Writing the sequence of 5C6h and
A7Eh to WDKEY causes the watchdog timer to transition between the active and service states. The transition
from the service state to the active state results in the timer register reload that is necessary to keep the
watchdog timer from timing out. Each time the watchdog is serviced by the sequence, the watchdog timer
counter and prescalar will automatically be reloaded.
38
SPRS122E
December 1999 – Revised April 2002
Functional Overview
The registers WDTIM, WDPRD, WDTCR, and the PREMD bit in WDTSCR must be configured before the
watchdog enters the active state. By default, WDTIM =FFFFh, WDPRD = FFFFh, PREMD = 1, TDDR = 1111b.
Writing a ‘1’ to WDEN and configuring the PREMD bit must be done at the same time that A7Eh is written to
WDKEY in watchdog pre-active state.
3.2.5.6 Watchdog State Diagram
Figure 3–25 shows the watchdog operation state diagram.
Not 5C6h to
Power Up/
Reset
(Hardware)
WDKEY
5C6h to
WDKEY
A7Eh to
WDKEY
A7Eh to WDKEY
with ”1” to WDEN
(Reload Timer,
Clear WDFLAG,
Enable Output Pin)
Initial State
(Watchdog
Disabled)
5C6h to WDKEY
(WDTIM=FFFFh)
(WDPRD=FFFFh)
(TDDR=1111b)
(PREMD=1)
Pre-Active
State
Active State
(Waiting for
5C6h)
Not A7Eh or 5C6h
to WDKEY
Not 5C6h or A7Eh
to WDKEY
Output Pin Asserted
WDFLAG Set
WD INT Triggered
5C6h to
WDKEY
A7Eh to
WDKEY
(Register
Reload)
Timeout!
Output Pin Asserted
WDFLAG Set
WD INT Triggered
Timeout
State
(Watchdog
Disabled)
(Output Pin
Disconnected)
Timeout!
Output Pin Asserted
WDFLAG Set
Service
State
WD INT Triggered
(Waiting for
A7Eh)
Not A7Eh or 5C6h
to WDKEY
Output Pin Asserted
WDFLAG Set
WD INT Triggered
5C6h to
WDKEY
Figure 3–25. Watchdog Operation State Diagram
As shown in Figure 3–25, the watchdog is disabled before it enters the active state. Even though disabled,
the WD interrupt (WD_TINT) may be triggered periodically although the watchdog output pin (x_WTOUT) will
not be asserted. The interrupt may be utilized to:
•
•
Indicate that watchdog is not in active state
Allow the watchdog timer to act as a general-purpose time counter if the watchdog functionality is not
needed.
3.2.5.7 Watchdog Register Write Protection
Once the watchdog is enabled, writes to registers WDTIM, WDPRD, and WDTCR will have no effect. Writes
to the WDFLAG, WDEN, and PREMD bits in register WDTSCR will have no effect. However, writing an
incorrect key (not 5C6h or A7Eh) to WDKEY will result in an immediate time-out.
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December 1999 – Revised April 2002
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Functional Overview
3.2.6 Software-Programmable Phase-Locked Loop (PLL)
The clock generator provides clocks to the 5441 device, and consists of a phase-locked loop (PLL) circuit. The
clock generator requires a reference clock input, which must be provided by using an external clock source.
Thereferenceclockinputisthendividedbytwo(DIVmode)togenerateclocksforthe5441device. Alternately,
the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock
frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The
PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. When the PLL
is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once
the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal
clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5441 device. Only
subsystem A controls the PLL. Subsystems B, C, and D cannot access the PLL registers.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
•
PLLmode. Theinputclock(CLKIN)ismultipliedby1of31possibleratios. Theseratiosareachievedusing
the PLL circuitry.
•
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module.
Figure 3–26 shows the bit layout of the clock mode register and Table 3–14 describes the bit functions.
15
12
11
PLLDIV
R/W
10
3
2
PLLON/OFF
R/W
1
0
†
†
†
†
PLLMUL
PLLCOUNT
PLLNDIV
R/W
STATUS
R/W
R/W
R/W
†
When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.
LEGEND: R = Read, W = Write
Figure 3–26. Clock Mode Register (CLKMD)
40
SPRS122E
December 1999 – Revised April 2002
Functional Overview
Table 3–14. Clock Mode Register (CLKMD) Bit Functions
BIT
BIT
NAME
FUNCTION
NO.
PLL multiplier. PLLMUL defines the frequency multiplier in conjunction with PLLDIV and PLLNDIV. See
Table 3–15.
†
15–12
PLLMUL
PLLdivider. PLLDIVdefinesthefrequencymultiplierinconjunctionwithPLLMULandPLLNDIV. SeeTable 3–15.
†
PLLDIV = 0
PLLDIV = 1
Means that an integer multiply factor is used
Means that a noninteger multiply factor is used
11
PLLDIV
PLLcounter value. PLLCOUNT specifies the number of input clock cycles (in increments of16 cycles) for the PLL
lock timer to count before the PLL begins clocking the processor after the PLL is started. The PLL counter is a
down-counter, which is driven by the input clock divided by 16; therefore, for every 16 input clocks, the PLL
counter decrements by one.
†
10–3
PLLCOUNT
The PLL counter can be used to ensure that the processor is not clocked until the PLL is locked, so that only valid
clock signals are sent to the device.
PLL on/off. PLLON/OFF enables or disables the PLL part of the clock generator in conjunction with the PLLNDIV
bit (see Table 3–16). Note that PLLON/OFF and PLLNDIV can both force the PLL to run; when PLLON/OFF is
high, the PLL runs independently of the state of PLLNDIV.
†
2
1
PLLON/OFF
PLLNDIV configures PLL mode when high or DIV mode when low. PLLNDIV defines the frequency multiplier in
conjunction with PLLDIV and PLLMUL. See Table 3–15.
PLLNDIV
Indicates the PLL mode.
STATUS = 0 Indicates DIV mode
STATUS = 1 Indicates PLL mode
0
STATUS
†
When in DIV mode (PLLSTATUS is low), PLLMUL, PLLDIV, PLLCOUNT, and PLLON/OFF are don’t cares, and their contents are indeterminate.
Table 3–15. Multiplier Related to PLLNDIV, PLLDIV, and PLLMUL
‡
PLLNDIV
PLLDIV
PLLMUL
0–14
15
MULTIPLIER
0
x
x
0
0
1
1
0.5
0
0.25
1
0–14
15
PLLMUL + 1
bypass (multiply by 1)
(PLLMUL + 1)/2
PLLMUL/4
1
1
0 or even
odd
1
‡
CLKOUT = CLKIN * Multiplier
Table 3–16. VCO Truth Table
PLLON/OFF
PLLNDIV
VCO STATE
0
1
0
1
0
0
1
1
off
on
on
on
3.2.6.1 PLL Clock Programmable Timer
During the lockup period, the PLL should not be used to clock the 5441. The PLLCOUNT programmable lock
timer provides a convenient method of automatically delaying clocking of the device by the PLL until lock is
achieved.
The PLL lock timer is a counter, loaded from the PLLCOUNT field in the CLKMD register, that decrements from
its preset value to 0. The timer can be preset to any value from 0 to 255, and its input clock is CLKIN divided
by 16. The resulting lockup delay can therefore be set from 0 to 255 × 16 CLKIN cycles.
41
December 1999 – Revised April 2002
SPRS122E
Functional Overview
The lock timer is activated when the operating mode of the clock generator is switched from DIV to PLL. During
the lockup period, the clock generator continues to operate in DIV mode; after the PLL lock timer decrements
to zero, the PLL begins clocking the 5441.
Accordingly, the value loaded into PLLCOUNT is chosen based on the following formula:
Lockup Time
PLLCOUNT +
16 TCLKIN
where T
is the input reference clock period and lockup time is the required VCO lockup time, as shown
CLKIN
in Table 3–17.
Table 3–17. VCO Lockup Time
†
CLKOUT FREQUENCY (MHz) LOCKUP TIME (µs)
5
23
17
16
19
24
29
35
45
10
20
40
60
80
100
135
†
Approximate values
3.2.6.2 CLKMD Register Initialization At Reset
The clock mode pin (CLKMD) is used to initialize the PLL to a known value at reset. The CLKMD pin is sampled
when the reset signal is low. Only global reset (RESET) will reset the PLL. Subsystem A local reset (A_RS)
has no effect on the PLL.
Table 3–18. PLL Initialization at Reset
CLKMD PIN
PLL MODE
Bypass
0
1
CLKINx2
3.2.7 General-Purpose I/O
The 5441 has 16 general-purpose I/O pins. These pins are:
A_GPIO0, A_GPIO1, A_GPIO2, A_GPIO3
B_GPIO0, B_GPIO1, B_GPIO2, B_GPIO3
C_GPIO0, C_GPIO1, C_GPIO2, C_GPIO3
D_GPIO0, D_GPIO1, D_GPIO2, D_GPIO3
Four bits of general-purpose I/O are available to each core. Each GPIO pin can be individually selected as
either an input or an output through the GPIO register. The x_XF, x_BIO, and timer output are selectable on
GPIO pins 0, 1, and 3 through the GPIO register also. Each output driver has an independent three-state
control. All nonreserved GPIO register bits are readable and writeable. The GPIO register bits will be set
to0whenthecoreisinreset, whichwillconfigureallGPIOasinputs. GPIOdataandcontrolbitsareaccessible
through a memory-mapped register at 3Ch with the format shown in Figure 3–27 and the bit functions
described in Table 3–19.
42
SPRS122E
December 1999 – Revised April 2002
Functional Overview
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPIO GPIO GPIO GPIO
CLK
CLK
GPIO GPIO GPIO GPIO
DAT3 DAT2 DAT1 DAT0
TOUT Rsvd X_BIO X_XF
Reserved
DIR3 DIR2 DIR1
DIR0 OUT1 OUT0
R/W+0
R/W+0 R/W+0 R/W+0 R/W+0 R/W+0 R/W+0 R/W+0 R/W+0
R/W+0 R/W+0 R/W+0 R/W+0
LEGEND: R = Read, W = Write, +0 = Value at reset
Figure 3–27. General-Purpose I/O Control Register
Table 3–19. General-Purpose I/O Control Register Bit Functions
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
0
1
X
0
Timer output disable. Uses GPIO3 as general-purpose I/O.
15
14
TOUT
Timer output enable. Overrides DIR3. Timer output is driven on GPIO3 and readable in DAT3.
Register bit is reserved. Read 0, write has no effect.
Reserved
Branch control input disable. Uses GPIO1 as general-purpose I/O.
13
X_BIO
Branch control input enable. Overrides DIR1. The X_BIO output is driven on GPIO1 and readable in
DAT0.
1
0
1
0
1
External flag output disable. Uses GPIO0 as general-purpose I/O.
External flag output enable. Overrides DIR0. The X_XF output is driven on GPIO0 and readable in DAT1.
GPIOn pin is used as an input.
12
X_XF
GPIO
11–8
†
GPIOn pin is used as an output.
DIRn
CLKOUT muxing selection bits.
CLKOUT1[7]
0
CLKOUT0[6]
0
A_CLKOUT
(default)
7–6
CLKOUT
B_CLKOUT
C_CLKOUT
D_CLKOUT
0
1
1
1
0
1
5–4
3–0
Reserved
GPIO
X
0
1
Register bit is reserved. Read 0, write has no effect.
GPIOn is driven with a 0 (DIRn = 1). GPIOn is read as 0 (DIRn = 0).
GPIOn is driven with a 1 (DIRn = 1). GPIOn is read as 1 (DIRn = 0).
†
DATn
†
n = 3, 2, 1, or 0
The timer output (TOUT) bit is used to multiplex the output of the timer and GPIO3. The X_XF bit is used to
multiplex the output of the external flag, and the X_BIO bit is used to multiplex the input of the branch control.
The watchdog enable (WDEN) bit in the watchdog timer second control register (WDTSCR) is used to
multiplex the watchdog timer output and GPIO2. All GPIO pins are programmable as an input or output by the
direction bit (GPIODIRn). Data is either driven or read from the data bit field (GPIODATn). GPIODIR3 has no
effect when TOUT = 1.
43
December 1999 – Revised April 2002
SPRS122E
Functional Overview
3.2.8 Chip Subsystem ID Register
The chip subsystem ID register (CSIDR) is a read-only memory-mapped register located at 3Eh within each
DSP subsystem. This register contains two elements for electrically readable device identification. The
Chip ID bits identify the type of C54x device (41h for 5441). The SubSysID contains a unique subsystem
identifier. Figure 3–28 shows the CSIDR and Table 3–20 describes its bit functions.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Chip ID
Reserved
SubSysID
R
R
LEGEND: R = Read
Figure 3–28. Chip Subsystem ID Register (CSIDR)
Table 3–20. Chip Subsystem ID Register Bit Functions
FUNCTION
BIT
NO.
BIT FIELD
NAME
15–8
7–4
Chip ID
Reserved
SubSysID
54x device type. Contains 41h for 5441.
3–0
Identifier for DSP subsystem: A = 00b, B = 01b, C = 10b, and D = 11b
3.2.9 Data Memory Map Register
To access the extended data memory, the DSP CPU need to configure the data memory map register
(DMMR), which is used to point to extended data memory. The content of DMMR register is used to select
the extended data for all CPU data memory accesses. Figure 3–29 shows the DMMR and Table 3–21
describes its bit functions.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Extended
Data
Reserved
R/W+0
LEGEND: R = Read, W = Write
Figure 3–29. Data Memory Map Register (DMMR)
Table 3–21. Data Memory Map Register Functions
BIT
NO.
BIT FIELD
NAME
FUNCTION
15–1
Reserved
Extended data memory for CPU access:
Extended_Data = 0b, DARAM2 and DARAM3 are mapped in.
Extended_Data = 1b, DARAM4 and DARAM5 are mapped in.
0
Extended data
44
SPRS122E
December 1999 – Revised April 2002
Functional Overview
3.3 Memory-Mapped Registers
The 5441 has 27 processor memory-mapped registers, which are mapped in data memory space addresses
0h to 1Fh as shown in Table 3–22. Each device also has a set of memory-mapped registers associated with
the peripherals as shown in Table 3–23.
Table 3–22. Processor Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DESCRIPTION
DEC
HEX
IMR
IFR
—
0
0
Interrupt Mask Register
Interrupt Flag Register
Reserved for testing
Status Register 0
1
1
2–5
6
2–5
6
ST0
ST1
AL
7
7
Status Register 1
8
8
Accumulator A Low Word (15–0)
AH
AG
BL
9
9
Accumulator A High Word (31–16)
Accumulator A Guard Bits (39–32)
Accumulator B Low Word (15–0)
Accumulator B High Word (31–16)
Accumulator B Guard Bits (39–32)
Temporary Register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
BH
BG
C
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition Register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary Register 0
Auxiliary Register 1
Auxiliary Register 2
Auxiliary Register 3
Auxiliary Register 4
Auxiliary Register 5
Auxiliary Register 6
Auxiliary Register 7
Stack Pointer
BK
Circular Buffer Size Register
Block-Repeat Counter
Block-Repeat Start Address
Block-Repeat End Address
Processor Mode Status Register
Extended Program Counter
Reserved
BRC
RSA
REA
PMST
XPC
—
45
December 1999 – Revised April 2002
SPRS122E
Functional Overview
Table 3–23. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
(HEX)
NAME
DRR20
DESCRIPTION
20
21
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
DRR10
DXR20
DXR10
TIM
22
23
24
PRD
25
Timer Period Register
TCR
26
Timer Control Register
TSCR
–
27
Timer Second Control Register
Reserved
28
BSCR
—
29
Bank-Switching Control Register
Reserved
2A–2B
2C
HPIC
—
HPI Control Register (HMODE=0 only)
Reserved
2D–2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
31
32
33
†
†
34
McBSP 2 Subbank Address Register
†
35
McBSP 2 Subbank Data Register
Reserved
36–37
38
SPSA0
SPSD0
—
McBSP 0 Subbank Address Register
†
39
McBSP 0 Subbank Data Register
Reserved
3A–3B
3C
GPIO
—
General-Purpose I/O Register
Reserved
3D
CSIDR
—
3E
Chip Subsystem ID register
Reserved
3F
DRR21
DRR11
DXR21
DXR11
—
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
41
42
43
44–47
48
†
SPSA1
SPSD1
—
McBSP 1 Subbank Address Register
†
49
McBSP 1 Subbank Data Register
Reserved
4A–4B
4C
TIM
Watchdog Timer Register
Watchdog Timer Period Register
Watchdog Timer Control Register
PRD
4D
TCR
4E
WDTSCR
DMMR
—
4F
Watchdog Timer Second Control Register
Data Memory Map Register
Reserved
50
51–53
54
DMPREC
DMSA
DMSDI
DMA Priority and Enable Control Register
‡
55
DMA Subbank Address Register
DMA Subbank Data Register with Autoincrement
‡
56
†
See Table 3–24 for a detailed description of the McBSP control registers and their subaddresses.
‡
See Table 3–25 for a detailed description of the DMA subbank addressed registers.
46
SPRS122E
December 1999 – Revised April 2002
Functional Overview
Table 3–23. Peripheral Memory-Mapped Registers for Each DSP Subsystem (Continued)
ADDRESS
(HEX)
NAME
DMSDN
DESCRIPTION
‡
DMA Subbank Data Register
57
58
CLKMD
Clock Mode Register (CLKMD), subsystem A only (reserved in subsystems B, C, and D)
Reserved
—
59–5F
†
See Table 3–24 for a detailed description of the McBSP control registers and their subaddresses.
‡
See Table 3–25 for a detailed description of the DMA subbank addressed registers.
3.4 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. The McBSP subbank address register (SPSAx) is used as a pointer to select a particular register
within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3–24 shows the McBSP control registers and their corresponding subaddresses.
Table 3–24. McBSP Control Registers and Subaddresses
McBSP0
NAME
McBSP1
NAME
McBSP2
NAME
SUB-
ADDRESS
DESCRIPTION
ADDRESS
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
ADDRESS
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
ADDRESS
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
SPCR10
SPCR20
RCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
00h
01h
Serial port control register 1
Serial port control register 2
02h
Receive control register 1
RCR20
RCR21
RCR22
03h
Receive control register 2
XCR10
XCR11
XCR12
04h
Transmit control register 1
XCR20
XCR21
XCR22
05h
Transmit control register 2
SRGR10
SRGR20
MCR10
SRGR11
SRGR21
MCR11
SRGR12
SRGR22
MCR12
06h
Sample rate generator register 1
07h
Sample rate generator register 2
08h
Multichannel register 1
MCR20
MCR21
MCR22
09h
Multichannel register 2
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
RCERA2
RCERB2
XCERA2
XCERB2
PCR2
0Ah
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
0Bh
0Ch
0Dh
0Eh
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
Receive channel enable register partition C
Receive channel enable register partition D
Transmit channel enable register partition C
Transmit channel enable register partition D
Receive channel enable register partition E
Receive channel enable register partition F
Transmit channel enable register partition E
Transmit channel enable register partition F
Receive channel enable register partition G
Receive channel enable register partition H
Transmit channel enable register partition G
Transmit channel enable register partition H
47
December 1999 – Revised April 2002
SPRS122E
Functional Overview
3.5 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincrementedsothatasubsequentaccessaffectsthenextregisterwithinthesubbank. Thisautoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3–25 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
Table 3–25. DMA Subbank Addressed Registers
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
48
SPRS122E
December 1999 – Revised April 2002
Functional Overview
Table 3–25. DMA Subbank Addressed Registers (Continued)
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
DMDSTP
DMIDX0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
DMA destination program page address (common channel)
DMA element index address register 0
DMIDX1
DMA element index address register 1
DMFRI0
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA0
DMGDA0
DMGCR0
DMGFR0
–
DMA channel 0 global source address reload register
DMA channel 0 global destination address reload register
DMA channel 0 global count reload register
DMA channel 0 global frame count reload register
Reserved
–
Reserved
DMGSA1
DMGDA1
DMGCR1
DMGFR1
DMGSA2
DMGDA2
DMGCR2
DMGFR2
DMGSA3
DMGDA3
DMGCR3
DMGFR3
DMGSA4
DMGDA4
DMGCR4
DMGFR4
DMGSA5
DMGDA5
DMGCR5
DMGFR5
DMSRCDP0
DMDSTDP0
DMSRCDP1
DMDSTDP1
DMSRCDP2
DMDSTDP2
DMSRCDP3
DMDSTDP3
DMSRCDP4
DMDSTDP4
DMA channel 1 global source address reload register
DMA channel 1 global destination address reload register
DMA channel 1 global count reload register
DMA channel 1 global frame count reload register
DMA channel 2 global source address reload register
DMA channel 2 global destination address reload register
DMA channel 2 global count reload register
DMA channel 2 global frame count reload register
DMA channel 3 global source address reload register
DMA channel 3 global destination address reload register
DMA channel 3 global count reload register
DMA channel 3 global frame count reload register
DMA channel 4 global source address reload register
DMA channel 4 global destination address reload register
DMA channel 4 global count reload register
DMA channel 4 global frame count reload register
DMA channel 5 global source address reload register
DMA channel 5 global destination address reload register
DMA channel 5 global count reload register
DMA channel 5 global frame count reload register
DMA channel 0 extended source data page register
DMA channel 0 extended destination data page register
DMA channel 1 extended source data page register
DMA channel 1 extended destination data page register
DMA channel 2 extended source data page register
DMA channel 2 extended destination data page register
DMA channel 3 extended source data page register
DMA channel 3 extended destination data page register
DMA channel 4 extended source data page register
DMA channel 4 extended destination data page register
49
December 1999 – Revised April 2002
SPRS122E
Functional Overview
Table 3–25. DMA Subbank Addressed Registers (Continued)
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
DMSRCDP5
DMDSTDP5
56h/57h
56h/57h
48h
49h
DMA channel 5 extended source data page register
DMA channel 5 extended destination data page register
3.6 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3–26.
Table 3–26. 5441 Interrupt Locations and Priorities for Each DSP Subsystem
LOCATION
NAME
RS, SINTR
PRIORITY
FUNCTION
DECIMAL
0
HEX
00
1
2
Reset (Hardware and Software Reset)
Nonmaskable Interrupt
NMI, SINT16
SINT17
4
04
8
08
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software Interrupt #17
SINT18
12
0C
10
Software Interrupt #18
SINT19
16
Software Interrupt #19
SINT20
20
14
Software Interrupt #20
SINT21
24
18
Software Interrupt #21
SINT22
28
1C
20
Software Interrupt #22
SINT23
32
Software Interrupt #23
SINT24
36
24
Software Interrupt #24
SINT25
40
28
Software Interrupt #25
SINT26
44
2C
30
Software Interrupt #26
SINT27
48
Software Interrupt #27
SINT28
52
34
Software Interrupt #28
SINT29
56
38
Software Interrupt #29
SINT30
60
3C
40
Software Interrupt #30
INT, SINT0
WDTINT, SINT1
INT2, SINT2
TINT, SINT3
BRINT0, SINT4
BXINT0, SINT5
BRINT2, DMAC0
BXINT2, DMAC1
INT3, SINT8
HPINT, SINT9
BRINT1, DMAC2
BXINT1, DMAC3
DMAC4, SINT12
DMAC5, SINT13
—
64
External User Interrupt
68
44
4
Watchdog Timer Interrupt
Software interrupt #2
72
48
5
76
4C
50
6
External Timer Interrupt
BSP #0 Receive Interrupt
BSP #0 Transmit Interrupt
BSP #2 Receive Interrupt or DMA Channel 0
BSP #2 Receive Interrupt or DMA Channel 1
Software interrupt #8
80
7
84
54
8
88
58
9
92
5C
60
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120–127
64
HPI Interrupt (from DSPINT in HPIC)
BSP #1 Receive Interrupt or DMA Channel 2
BSP #1 transmit Interrupt or DMA channel 3
DMA Channel 4
68
6C
70
74
DMA Channel 5
78–7F
Reserved
50
SPRS122E
December 1999 – Revised April 2002
Functional Overview
Figure 3–30 shows the bit layout of the IMR and the IFR. Table 3–27 describes the bit functions.
15
14
13
12
11
10
9
8
XINT1 or
DMAC3
RINT1 or
DMAC2
Reserved
DMAC5
R/W
DMAC4
R/W
HPINT
R/W
Reserved
R/W
R/W
7
6
5
4
3
2
1
0
XINT2 or
DMAC1
RINT2 or
DMAC0
XINT0
R/W
RINT0
R/W
TINT
R/W
Reserved
WDTINT
R/W
INT
R/W
R/W
R/W
LEGEND: R = Read, W = Write
Figure 3–30. Bit Layout of the IMR and IFR Registers for Each Subsystem
Table 3–27. Bit Functions for IMR and IFR Registers for Each DSP Subsystem
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
15–14
Reserved
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
1
0
1
0
1
0
1
0
1
0
1
Register bit is reserved.
IFR/IMR: DMA Channel 5 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 5 has an interrupt pending/is enabled.
IFR/IMR: DMA Channel 4 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 4 has an interrupt pending/is enabled.
IFR/IMR: McBSP_1 has no transmit interrupt pending/is disabled (masked).
IFR/IMR: McBSP_1 has a transmit interrupt pending/is enabled.
IFR/IMR: DMA Channel 3 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 3 has an interrupt pending/is enabled.
IFR/IMR: McBSP_1 has no receive interrupt pending/is disabled (masked).
IFR/IMR: McBSP_1 has a receive interrupt pending/is enabled.
IFR/IMR: DMA Channel 2 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 2 has an interrupt pending/is enabled.
IFR/IMR: Host-port interface has no DSPINT interrupt pending/is disabled (masked).
IFR/IMR: Host-port interface has an DSPINT interrupt pending/is enabled.
Register bit is reserved.
13
DMAC5
DMAC4
XINT1
12
11
DMAC3
RINT1
10
DMAC2
9
8
HPINT
Reserved
IFR/IMR: McBSP_2 has no transmit interrupt pending/is disabled (masked).
IFR/IMR: McBSP_2 has a transmit interrupt pending/is enabled.
IFR/IMR: DMA Channel 1 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 1 has an interrupt pending/is enabled.
IFR/IMR: McBSP_2 has no receive interrupt pending/is disabled (masked).
IFR/IMR: McBSP_2 has a receive interrupt pending/is enabled.
IFR/IMR: DMA Channel 0 has no interrupt pending/is disabled (masked).
IFR/IMR: DMA Channel 0 has an interrupt pending/is enabled.
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
IFR/IMR: McBSP_0 has no receive interrupt pending/is disabled (masked).
IFR/IMR: McBSP_0 has a receive interrupt pending/is enabled.
XINT2
DMAC1
RINT2
DMAC0
XINT0
7
6
5
4
RINT0
51
December 1999 – Revised April 2002
SPRS122E
Functional Overview
Table 3–27. Bit Functions for IMR and IFR Registers for Each DSP Subsystem (Continued)
BIT
NO.
BIT
NAME
BIT
VALUE
FUNCTION
0
1
X
0
1
0
1
IFR/IMR: Timer has no interrupt pending/is disabled (masked).
IFR/IMR: Timer has an interrupt pending/is enabled.
3
2
TINT
Reserved
Register bit is reserved.
IFR/IMR: Watchdog interrupt has no interrupt pending/is disabled (masked).
IFR/IMR: Watchdog interrupt has an interrupt pending/is enabled.
IFR/IMR: Ext user interrupt pin 0 has no interrupt pending/is disabled (masked).
IFR/IMR: Ext user interrupt pin 0 has an interrupt pending/is enabled.
1
0
WDTINT
INT
3.7 IDLE3 Power-Down Mode
The IDLE1 and IDLE2 power-down modes operate as described in the TMS320C54x DSP Reference Set,
Volume 1: CPU and Peripherals (literature number SPRU131). The IDLE3 mode is special in that the clocking
circuitry is shut off to conserve power. The 5441 cannot enter an IDLE3 mode unless all the subsystems
execute an IDLE3 instruction. The power-reduced benefits of IDLE3 cannot be realized until all the
subsystems enter the IDLE3 state and the internal clocks are automatically shut off. The order in which
subsystems enter IDLE3 does not matter.
3.8 Emulating the 5441 Device
The 5441 is a single device, but actually consists of four independent subboundary systems that contain
register/status information used by the emulator tools. Code Composer Studio has a setup wizard called
“Code Composer Setup.” The setup wizard prompts the user for the I/O address of the XDSSIO card and the
number of processors in the system. The board.dat file is then created and placed in the correct directory
automatically. The board.dat file contents would look something like this:
“CPU_D” TI320C5xx
“CPU_C” TI320C5xx
“CPU_B” TI320C5xx
“CPU_A” TI320C5xx
The subsystems are serially connected together internally. Emulation information is serially transmitted into
the device using TDI. The device responds with serial scan information transmitted out the TDO pin.
Code Composer Studio is a trademark of Texas Instruments.
52
SPRS122E
December 1999 – Revised April 2002
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete User Guides
Development-support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding Texas Instruments (TI) DSP products is also available on the Worldwide Web at
http://www.ti.com uniform resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
53
December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5441 DSP.
Leading “x” in signal names identifies the subsystem; x = A, B, C, or D for subsystem A, B, C, or D, respectively.
Trailing“n”insignalnamesidentifiestheMcBSP;n=0, 1, or2forMcBSP0, McBSP1, orMcBSP2,respectively.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to V . Figure 5–1 provides the test load circuit
SS
values for a 3.3-V device.
Supply voltage I/O range, DV
Supply voltage core range, CV
Supply voltage analog PLL, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.0 V
DD
CCA
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to DV
+ 0.5 V
+ 0.5 V
I
DD
DD
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to DV
o
Operating case temperature range, T (Commercial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
C
T (Industrial) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
C
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65ꢄC to 150ꢄC
stg
5.2 Recommended Operating Conditions
MIN
3
NOM
3.3
1.6
1.6
0
MAX
3.6
UNIT
†
DV
CV
Device supply voltage, I/O
V
V
V
V
DD
DD
†
Device supply voltage, core
Device supply voltage, PLL
Supply voltage, GND
1.55
1.55
1.65
1.65
V
CCA
SS
V
Schmitt triggered inputs
DV = 3.3 ± 0.3 V
0.7DV
DV
DV
+0.3
+0.3
DD
DD
DD
V
High-level input voltage, I/O
V
V
DD
IH
IL
All other inputs
2
Schmitt triggered inputs
0
0
0.3DV
DD
DV
= 3.3 ± 0.3 V
V
Low-level input voltage, I/O
High-level output current
DD
All other inputs
0.8
I
I
– 1
mA
mA
OH
Low-level output current
1.5
85
OL
Operating case temperature, Commercial
Operating case temperature, Industrial
0
T
C
°C
–40
100
†
Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long-term reliability of the devices. System-level concerns such as bus
contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior
to the I/O buffers, and then powered down after the I/O buffers.
54
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
TYP
PARAMETER
TEST CONDITIONS
= 3.3 ± 0.3 V, I = MAX
MIN
MAX
UNIT
V
‡
V
V
High-level output voltage
V
2.4
OH
DD
= MAX
OH
‡
Low-level output voltage
Input current in high impedance
TRST
I
0.4
V
OL
OL
I
IZ
V
DD
= MAX, V = V
to V
DD
–10
10
10
300
–10
275
10
µA
O
SS
With internal pulldown
With internal pullups
Bus holders enabled, V
Input current
(V = V to V )
DD
See pin descriptions
D[15:0], HA[18:0]
–300
–275
–10
I
I
µA
I
SS
||
= MAX
DD
All other input-only pins
§
= 1.6 V, f = 133 MHz ,
x
CV
DD
= 25°C
¶
I
Supply current, all four core CPUs
Supply current, pins
200
mA
mA
DDC
T
C
¶
= 133 MHz ,
clock
DV
= 3.3 V, f
= 25°C
DD
I
I
40
DDP
#
T
C
Supply current, PLL
IDLE2
3
10
3
mA
mA
mA
pF
DDA
PLL × n mode, 20 MHz input
I
Supply current, standby
DDC
IDLE3
PLL x n mode, 20 MHz input
C
C
Input capacitance
Output capacitance
5
i
5
pF
o
†
‡
All values are typical unless otherwise specified.
All input and output voltage levels except x_RS, x_INT, x_NMI, CLKIN, x_BCLKX0, x_BCLKR0, BCLKX2, BCLKR2, HAS, HCS, HDS1, HDS2,
and RESET are LVTTL-compatible.
§
¶
#
Clock mode: PLL × 1 with external source
This value is based on 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with the program being executed.
This value was obtained using the following conditions: HPI in multiplexed mode with address autoincrement, HPI read, CLKOFF = 0, full-duplex
operation of all 12 McBSPs at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this calculation
is performed, refer to the Calculation of TMS320LC54x Power Dissipation Application Report (literature number SPRA164).
||
V
≤ V ≤ V
or V
≤ V ≤ V
IH(MIN) I IH(MAX)
IL(MIN)
I
IL(MAX)
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
V
=
1.5 mA (all outputs)
300 µA (all outputs)
1.6 V
OL
OH
Load
T
=
=
=
C
20 pF typical load circuit capacitance
Figure 5–1. 3.3-V Test Load Circuit
55
December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
5.4 Package Thermal Resistance Characteristics
Table 5–1 provides the thermal resistance characteristics for the recommended package types used on the
TMS320VC5441 DSP.
Table 5–1. Thermal Resistance Characteristics
GGU
PACKAGE
PGF
PACKAGE
PARAMETER
UNIT
R
R
38
5
56
5
°C/W
°C/W
ΘJA
ΘJC
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
56
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
5.6 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in Section 3.2.6.
5.6.1 Divide-By-Two, Divide-By-Four, and Bypass Clock Options – PLL Disabled
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four to
generate the internal machine cycle. The selection of the clock mode is described in Section 3.2.6.
Table 5–2 and Table 5–3 assume testing over recommended operating conditions and H = 0.5t
Figure 5–2).
(see
c(CO)
Table 5–2. Divide-By-Two, Divide-By-Four, and Bypass Clock Options Timing Requirements
MIN
MAX
UNIT
†
t
t
t
t
t
Cycle time, CLKIN
20
ns
ns
ns
ns
ns
c(CI)
Fall time, CLKIN
6
6
f(CI)
Rise time, CLKIN
r(CI)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
5
5
w(CIL)
w(CIH)
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
Table 5–3. Divide-By-Two, Divide-By-Four, and Bypass Clock Options Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
ns
†
t
t
Cycle time, CLKOUT
7.5 2t
c(CO)
c(CI)
†
Cycle time, CLKOUT – bypass mode
Delay time, CLKIN high to CLKOUT high/low
Fall time, CLKOUT
7.5 2t
ns
c(CO)
c(CI)
7
t
2
11
ns
d(CIH-CO)
t
1
1
ns
f(CO)
t
t
t
Rise time, CLKOUT
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H–2
H–2
H–1
H–1
H
H
ns
w(COL)
w(COH)
ns
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
t
r(CI)
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
CLKIN
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
CLKOUT
Figure 5–2. External Divide-by-Two Clock Timing
57
December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
5.6.2 Multiply-By-N Clock Option – PLL Enabled
The frequency of the reference clock provided at the CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in Section 3.2.6.
Table 5–4 and Table 5–5 assume testing over recommended operating conditions and H = 0.5t
Figure 5–3).
(see
c(CO)
Table 5–4. Multiply-By-N Clock Option Timing Requirements
MIN
MAX
200
UNIT
†
‡
20
‡
20
‡
20
Integer PLL multiplier N (N = 1–15)
†
PLL multiplier N = x.5
100
50
t
Cycle time, CLKIN
ns
c(CI)
†
PLL multiplier N = x.25, x.75
t
t
t
t
Fall time, CLKIN
6
6
ns
ns
ns
ns
f(CI)
Rise time, CLKIN
r(CI)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
5
5
w(CIL)
w(CIH)
†
‡
N = Multiplication factor
ThemultiplicationfactorandminimumCLKINcycletimeshouldbechosensuchthattheresultingCLKOUTcycletimeiswithinthespecifiedrange
(t
)
c(CO)
Table 5–5. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
MIN
7.5
2
TYP
MAX
UNIT
ns
†
/N
c(CI)
t
Cycle time, CLKOUT
t
c(CO)
t
Delay time, CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
7
11
ns
d(CI-CO)
t
1.5
1.5
ns
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
ns
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock up time
H–2
H–2
H–1
H–1
H
H
ns
ns
45
ms
†
N = Multiplication factor
t
t
f(CI)
w(CIH)
t
t
r(CI)
w(CIL)
t
c(CI)
CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
t
r(CO)
p
Unstable
CLKOUT
Figure 5–3. External Multiply-by-One Clock Timing
58
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December 1999 – Revised April 2002
Electrical Specifications
5.7 Reset, x_BIO, and Interrupt Timings
Table 5–6 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–5).
(see Figure 5–4 and
c(CO)
Table 5–6. Reset, x_BIO, and Interrupt Timing Requirements
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
Hold time, x_RS after CLKOUT low
0
0
h(RS)
Hold time, x_BIO after CLKOUT low
ns
h(BIO)
h(INT)
†
Hold time, x_INT, x_NMI, after CLKOUT low
0
ns
‡§
Pulse duration, x_RS low
4H+4
5H
4H
4H
6
ns
w(RSL)
w(BIO)
w(INTH)
w(INTL)
†
Pulse duration, x_BIO low, synchronous
ns
†
Pulse duration, x_INT, x_NMI high (synchronous)
ns
†
Pulse duration, x_INT, x_NMI low (synchronous)
ns
†
t
Pulse duration, x_INT, x_NMI low for IDLE2/IDLE3 wakeup
ns
w(INTL)WKP
§
t
Setup time, x_RS before CLKIN low
4
ns
su(RS)
su(BIO)
su(INT)
t
t
Setup time, x_BIO before CLKOUT low
7
ns
Setup time, x_INT, x_NMI, x_RS before CLKOUT low
7
ns
†
The external interrupts (x_INT, x_NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer, which samples these inputs with
consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding
to a three-CLKOUT sampling sequence.
‡
§
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, x_RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
x_RS can cause a change in clock frequency, changing the value of H (see Section 3.2.6).
CLKIN
t
su(RS)
t
w(RSL)
x_RS, x_NMI, x_INT
t
su(INT)
t
h(RS)
CLKOUT
t
su(BIO)
t
h(BIO)
x_BIO
t
w(BIO)
Figure 5–4. Reset and x_BIO Timings
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December 1999 – Revised April 2002
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Electrical Specifications
CLKOUT
t
t
t
su(INT)
su(INT)
h(INT)
x_INT, x_NMI
t
w(INTH)
t
w(INTL)
Figure 5–5. Interrupt Timing
60
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
5.8 External Flag (x_XF), Timer (x_TOUT), and Watchdog Timer Output (x_WTOUT)
Timings
Table 5–7 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–7, and Figure 5–8).
(see Figure 5–6,
c(CO)
Table 5–7. External Flag (x_XF), Timer (x_TOUT), and Watchdog Timer Output (x_WTOUT)
Switching Characteristics
PARAMETER
Delay time, CLKOUT high to x_XF high
MIN
– 1
MAX UNIT
4
t
ns
d(XF)
Delay time, CLKOUT high to x_XF low
Delay time, CLKOUT high to x_TOUT high
Delay time, CLKOUT high to x_TOUT low
Pulse duration, x_TOUT
– 1
6
t
t
t
– 1
4
6
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
– 1
2H –8
2H
t
Delay time, CLKOUT high to x_WTOUT high
Delay time, CLKOUT high to x_WTOUT low
Pulse duration, x_WTOUT
– 1
– 1
4
4
ns
ns
ns
d(WTOUTH)
t
d(WTOUTL)
t
2H – 8
w(WTOUT)
CLKOUT
t
d(XF)
x_XF
Figure 5–6. External Flag (x_XF) Timing
CLKOUT
t
t
d(TOUTL)
d(TOUTH)
x_TOUT
t
w(TOUT)
Figure 5–7. Timer (x_TOUT) Timing
CLKOUT
t
t
d(WTOUTL)
d(WTOUTH)
t
w(WTOUT)
x_WTOUT
Figure 5–8. Watchdog Timer (x_WTOUT) Timing
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December 1999 – Revised April 2002
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Electrical Specifications
5.9 General-Purpose Input/Output (GPIO) Timing
Table 5–8 and Table 5–9 assume testing over recommended operating conditions (see Figure 5–9).
Table 5–8. GPIO Timing Requirements
MIN
MAX
UNIT
Setup time, x_GPIOn input valid before CLKOUT high, x_GPIOn configured as
general-purpose input.
t
t
8
ns
su(GPIO-COH)
Hold time, x_GPIOn input valid after CLKOUT high, x_GPIOn configured as
general-purpose input.
0
ns
h(GPIO-COH)
Table 5–9. GPIO Switching Characteristics
PARAMETER
MIN
MAX
UNIT
Delay time, CLKOUT high to x_GPIOn output change. x_GPIOn configured as
general-purpose output.
t
0
6
ns
d(COH-GPIO)
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
x_GPIOn Input Mode
t
d(COH-GPIO)
x_GPIOn Output Mode
Figure 5–9. GPIO Timings
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December 1999 – Revised April 2002
Electrical Specifications
5.10 Multichannel Buffered Serial Port Timing
5.10.1 McBSP0/1/2 Transmit and Receive Timings
The serial port timings that are referenced to CLKOUT are actually related to the internal CPU clock frequency.
These timings are not affected by the value of the DIVFCT bit field in the BSCR register (see Section 3.2.2.5
of this data manual for details on the BSCR register). Any references to CLKOUT in these timing parameters
refer to the CLKOUT timings when no divide factor is selected (DIVFCT = 00b).
Table 5–10 and Table 5–11 assume testing over recommended operating conditions and H = 0.5t
Figure 5–10 and Figure 5–11).
(see
c(CO)
†
Table 5–10. McBSP0/1/2 Transmit and Receive Timing Requirements
MIN
50
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
Cycle time, x_BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR ext
BCLKR ext
BCLKX ext
BCLKR ext
BCLKR ext
BCLKX ext
BCLKR/X ext
BCLKR/X ext
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(BCKRX)
Pulse duration, x_BCLKR/X low or x_BCLKR/X high
Hold time, external x_BFSR high after x_BCLKR low
Hold time, x_BDR valid after x_BCLKR low
Hold time, external x_BFSX high after x_BCLKX low
Setup time, external x_BFSR high before x_BCLKR low
Setup time, x_BDR valid before x_BCLKR low
Setup time, external x_BFSX high before x_BCLKX low
Rise time, x_BCLKR/X
24
w(BCKRX)
7.5
7.5
7.5
7.5
7.5
7.5
h(BCKRL-BFRH)
h(BCKRL-BDRV)
h(BCKXL-BFXH)
su(BFRH-BCKRL)
su(BDRV-BCKRL)
su(BFXH-BCKXL)
r(BCKRX)
6
6
Fall time, x_BCLKR/X
f(BCKRX)
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
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December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
†
Table 5–11. McBSP0/1/2 Transmit and Receive Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
t
Delay time, x_BCLKX high to internal x_BFSX valid
BCLKX ext
BCLKX ext
2
15
ns
d(BCKXH-BFXV)
Disable time, x_BCLKX high to x_BDX high impedance following last data
bit
1
18
20
ns
dis(BCKXH-BDXHZ)
Delay time, x_BCLKX high to x_BDX valid. This applies to all bits except
the first bit transmitted.
BCLKX ext
4
‡
Delay time, x_BCLKX high to x_BDX valid.
DXENA = 0
t
ns
d(BCKXH-BDXV)
BCLKX ext
BCLKX ext
BCLKX ext
BCLKX ext
BFSX ext
BFSX ext
BFSX ext
BFSX ext
16
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
4H+19
‡
Enable time, x_BCLKX high to x_BDX driven.
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
2
t
t
t
ns
ns
ns
Only applies to first bit transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b) modes
en(BCKXH-BDX)
d(BFXH-BDXV)
en(BFXH-BDX)
4H+2
‡
Delay time, x_BFSX high to x_BDX valid.
17
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode.
4H+15
‡
Enable time, x_BFSX high to x_BDX driven.
1
Only applies to first bit transmitted when in Data Delay 0
(XDATDLY=00b) mode
4H+5
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡
See the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302) for a description of the DX enable
(DXENA) and data delay features of the McBSP.
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SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
x_BCLKR
x_BFSR (int)
x_BFSR (ext)
t
d(BCKRH–BFRV)
t
d(BCKRH–BFRV)
t
r(BCKRX)
t
su(BFRH–BCKRL)
t
h(BCKRL–BFRH)
t
h(BCKRL–BDRV)
(n–2)
t
su(BDRV–BCKRL)
x_BDR
(RDATDLY=00b)
Bit (n–1)
(n–3)
(n–4)
t
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
(n–2)
x_BDR
(RDATDLY=01b)
Bit (n–1)
(n–3)
t
t
su(BDRV–BCKRL)
h(BCKRL–BDRV)
(n–2)
x_BDR
(RDATDLY=10b)
Bit (n–1)
Figure 5–10. McBSP0/1/2 Receive Timings
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
x_BCLKX
x_BFSX (int)
x_BFSX (ext)
t
d(BCKXH–BFXV)
t
d(BCKXH–BFXV)
t
su(BFXH–BCKXL)
t
h(BCKXL–BFXH)
t
d(BFXH–BDXV)
Bit (n–1)
t
t
t
d(BCKXH–BDXV)
(n–3)
en(BFXH–BDX)
x_BDX
Bit 0
(n–2)
(n–4)
(n–3)
(n–2)
(XDATDLY=00b)
d(BCKXH–BDXV)
(n–2)
t
en(BCKXH–BDX)
Bit (n–1)
x_BDX
(XDATDLY=01b)
Bit 0
t
d(BCKXH–BDXV)
Bit (n–1)
t
dis(BCKXH–BDXHZ)
t
en(BCKXH–BDX)
x_BDX
(XDATDLY=10b)
Bit 0
Figure 5–11. McBSP0/1/2 Transmit Timings
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December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
5.10.2 McBSP0 General-Purpose I/O Timing
Table 5–12 and Table 5–13 assume testing over recommended operating conditions (see Figure 5–12).
Table 5–12. McBSP0 General-Purpose I/O Timing Requirements
MIN
7
MAX
UNIT
ns
†
Setup time, BGPIOx input mode before CLKOUT high
t
t
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
ns
h(COH-BGPIO)
†
BGPIOx refers to x_BCLKR, x_BFSR, x_BDR, x_BCLKX, or x_BFSX when configured as a general-purpose input.
Table 5–13. McBSP0 General-Purpose I/O Switching Characteristics
PARAMETER
MIN
MAX
UNIT
‡
t
Delay time, CLKOUT high to BGPIOx output mode
–8
8
ns
d(COH-BGPIO)
‡
BGPIOx refers to x_BCLKR, x_BFSR, x_BCLKX, x_BFSX, or x_BDX when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to x_BCLKR, x_BFSR, x_BDR, x_BCLKX, or x_BFSX when configured as a general-purpose input.
BGPIOx refers to x_BCLKR, x_BFSR, x_BCLKX, x_BFSX, or x_BDX when configured as a general-purpose output.
Figure 5–12. McBSP0 General-Purpose I/O Timings
66
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December 1999 – Revised April 2002
Electrical Specifications
5.11 Host-Port Interface (HPI16) Timing
Table 5–14 and Table 5–15 assume testing over recommended operating conditions and H = 0.5t
Figure 5–13 through Figure 5–19). In the following tables, DS refers to the logical OR of HCS, HDS1, and
(see
c(CO)
HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
Table 5–14. HPI16 Timing Requirements
MIN
4
MAX
UNIT
ns
†‡
Setup time, HAD valid before DS falling edge
t
t
su(HBV-DSL)
†‡
Hold time, HAD valid after DS falling edge
4
ns
h(DSL-HBV)
†
t
t
t
t
t
t
t
t
t
Setup time, HAD valid before HAS falling edge
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(HBV-HSL)
h(HSL-HBV)
su(HAV-DSH)
su(HAV-DSL)
h(DSH-HAV)
su(HSL-DSL)
h(HSL-DSL)
w(DSL)
†
Hold time, HAD valid after HAS falling edge
4
‡
Setup time, address valid before DS rising edge (nonmultiplexed write)
5
‡
Setup time, address valid before DS falling edge (nonmultiplexed read)
–(4H + 5)
‡
Hold time, address valid after DS rising edge (nonmultiplexed mode)
2
4
‡
Setup time, HAS low before DS falling edge
‡
Hold time, HAS low after DS falling edge
2
‡
Pulse duration, DS low
23
8
‡
Pulse duration, DS high
w(DSH)
Nonmultiplexed or multiplexed mode
(no increment) memory accesses (or
writes to the FETCH bit) with no DMA
activity.
Reads
Writes
Reads
Writes
Reads
10H + 20
10H + 10
16H + 20
16H + 10
24H + 20
24H + 10
ns
ns
ns
Nonmultiplexed or multiplexed mode
(no increment) memory accesses (or
writes to the FETCH bit) with 16-bit
DMA activity.
Cycle time, DS rising edge to next DS
‡
rising edge
Nonmultiplexed or multiplexed mode
(no increment) memory accesses (or
writes to the FETCH bit) with 32-bit
DMA activity.
Writes
t
c(DSH-DSH)
Multiplexed
(autoincrement)
memory
accesses (or writes to the FETCH bit) with no 10H + 10
DMA activity.
ns
ns
ns
Cycle time, DS rising edge to next DS
rising edge
‡
Multiplexed
(autoincrement)
memory
accesses (or writes to the FETCH bit) with 16H + 10
16-bit DMA activity.
(In autoincrement mode, WRITE
timings are the same as READ
timings.)
Multiplexed
(autoincrement)
memory
accesses (or writes to the FETCH bit) with 24H + 10
32-bit DMA activity.
Cycle time, DS rising edge to next DS rising edge for writes to DSPINT and x_HINT
8H
ns
ns
Cycle time, DS rising edge to next DS rising edge for HPIC reads, HPIC XADD bit
writes, and address register reads and writes
40
‡
t
t
t
t
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
Setup time, HPI_SEL1/SEL2 valid before DS falling edge
4
2
4
1
ns
ns
ns
ns
su(HDV-DSH)W
h(DSH-HDV)W
su(SELV-DSL)
h(DSH-SELV)
‡
‡
‡
Hold time, HPI_SEL1/SEL2 valid after DS rising edge
†
‡
HAD stands for HCNTL0, HCNTL1, and HR/W.
DS refers to either HCS or HDS, whichever is controlling the transfer. Refer to the TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals (literature number SPRU302) for information regarding logical operation of the HPI16. These timings are shown assuming that HDS
is the signal controlling the transfer.
67
December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
Table 5–15. HPI16 Switching Characteristics
PARAMETER
MIN
MAX
UNIT
†
t
Delay time, DS low to HD driven
3
20
ns
d(DSL-HDD)
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 18H
32H+20 – t
ns
ns
w(DSH)
w(DSH)
w(DSH)
Case 1b: Memory accesses initiated by an autoincrement when
DMAC is active in 16-bit mode and t was < 18H
16H+20 – t
w(DSH)
Case 1c: Memory accesses not initiated by an autoincrement (or not
immediately following a write) when DMAC is active in 16-bit mode
16H+20
ns
ns
Case 1d: Memory accesses initiated by an autoincrement when
20
48H+20 – t
24H+20 – t
DMAC is active in 16-bit mode and t
w(DSH)
was ≥ 18H
Case 1e: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 26H
w(DSH)
w(DSH)
w(DSH)
Case 1f: Memory access initiated by an autoincrement when DMAC
is active in 32-bit mode and t was < 26H
Delay time, DS
low to HD valid
for first word of
an HPI read
w(DSH)
Case 1g: Memory access not initiated by an autoincrement (or not
immediately following a write) when DMAC is active in 32-bit mode
t
d(DSL-HDV1)
24H+20
ns
ns
Case 1h: Memory access initiated by an autoincrement when DMAC
20
is active in 32-bit mode and t
was ≥ 26H
w(DSH)
Case 2a: Memory accesses initiated immediately following a write
when DMAC is active in 16-bit mode and t was < 10H
20H+20 – t
10H+20 – t
w(DSH)
w(DSH)
Case 2b: Memory accesses initiated by an autoincrement when
DMAC is inactive and t was < 10H
w(DSH)
w(DSH)
Case 2c: Memory accesses not initiated by an autoincrement (or not
immediately following a write) when DMAC is inactive
10H+20
ns
Case 2d: Memory accesses initiated by an autoincrement when
20
DMAC is inactive and t
was ≥ 10H
w(DSH)
Case 3: HPIC/HPIA reads
Multiplexed reads with autoincrement. Prefetch completed.
20
20
t
3
ns
ns
d(DSL-HDV2)
Memory accesses (or writes to the FETCH bit) when no DMA is
active
10H+5
16H+5
Delay time, DS
high to HRDY
high
Memory accesses (or writes to the FETCH bit) with one or more
16-bit DMA channels active
†
t
d(DSH-HYH)
(writes
and
Memory accesses (or writes to the FETCH bit) with one or more
32-bit DMA channels active
autoincrement
reads)
24H+5
4H + 5
‡
Writes to DSPINT and x_HINT
6
ns
ns
ns
ns
ns
t
Valid time, HD valid after HRDY high
v(HYH-HDV)
†
t
Hold time, HD valid after DS rising edge, read
0
10
18
18
18
h(DSH-HDV)R
†
Delay time, DS low to HRDY low
t
d(DSL-HYL)
†
Delay time, DS high to HRDY low
t
d(DSH-HYL)
t
Delay time, HAS low to HRDY low, read
d(HSL-HYL)
†
DS refers to either HCS or HDS, whichever is controlling the transfer. Refer to the TMS320C54x DSP Reference Set, Volume 5: Enhanced
Peripherals (literature number SPRU302) for information regarding logical operation of the HPI16. These timings are shown assuming that
HDS is the signal controlling the transfer.
‡
HRDY does not go low for other register accesses.
68
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
HCS
HAS
HDS
t
su(HSL–DSL)
t
h(HSL–DSL)
t
t
c(DSH–DSH)
su(HBV–HSL)
t
w(DSH)
t
t
w(DSL)
h(HSL–HBV)
HR/W
01
01
HCNTL[1:0]
t
t
d(DSL–HDV1)
h(DSH–HDV)R
t
d(DSL–HDV2)
Data 1
PF Data
HD[15:0]
t
†
d(DSL–HDD)
t
d(DSH–HYL)
‡
HRDY
t
d(HSL–HYL)
†
t
d(DSH–HYH)
t
v(HYH–HDV)
†
‡
HRDY goes low at these times only after autoincrement reads.
While HCS is not selected, HRDY is in high-Z state.
Figure 5–13. Multiplexed Read Timings Using HAS
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December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
HCS
t
su(HBV–DSL)
t
c(DSH–DSH)
HDS
t
w(DSH)
t
t
h(DSL–HBV)
w(DSL)
HR/W
01
01
HCNTL[1:0]
t
t
h(DSH–HDV)R
d(DSL–HDV1)
t
d(DSL–HDV2)
PF Data
Data 1
HD[15:0]
t
†
d(DSL–HDD)
t
d(DSH–HYL)
‡
HRDY
†
t
t
d(DSH–HYH)
d(DSL–HYL)
t
v(HYH–HDV)
†
‡
HRDY goes low at these times only after autoincrement reads.
While HCS is not selected, HRDY is in high-Z state.
Figure 5–14. Multiplexed Read Timings With HAS Held High
70
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
HCS
t
su(HBV–HSL)
t
h(HSL–DSL)
HAS
HR/W
t
su(HSL–DSL)
t
h(HSL–HBV)
HCNTL[1:0]
HDS
01
01
t
c(DSH–DSH)
t
w(DSH)
t
w(DSL)
t
su(HDV–DSH)W
HD[15:0]
Data 1
Data 2
t
h(DSH–HDV)W
†
HRDY
t
d(DSH–HYL)
t
d(DSH–HYH)
†
While HCS is not selected, HRDY is in high-Z state.
Figure 5–15. Multiplexed Write Timings Using HAS
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December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
HCS
t
c(DSH–DSH)
t
w(DSH)
HDS
HR/W
t
t
w(DSL)
su(HBV–DSL)
t
h(DSL–HBV)
HCNTL[1:0]
01
01
t
su(HDV–DSH)W
t
h(DSH–HDV)W
Data 1
Data 2
HD[15:0]
t
d(DSH–HYL)
†
HRDY
t
d(DSH–HYH)
†
While HCS is not selected, HRDY is in high-Z state.
Figure 5–16. Multiplexed Write Timings With HAS Held High
72
SPRS122E
December 1999 – Revised April 2002
Electrical Specifications
HCS
HDS
t
w(DSH)
t
c(DSH–DSH)
t
t
su(HBV–DSL)
w(DSL)
t
su(HBV–DSL)
h(DSL–HBV)
t
t
h(DSL–HBV)
HR/W
t
su(HAV–DSL)
t
h(DSH–HAV)
HA[18:0]
Valid Address
Valid Address
t
h(DSH–HDV)R
t
d(DSL–HDV1)
t
t
h(DSH–HDV)R
d(DSL–HDV1)
Data
HD[15:0]
Data
v(HYH–HDV)
t
d(DSL–HDD)
t
d(DSL–HDD)
t
t
v(HYH–HDV)
†
HRDY
t
t
d(DSL–HYL)
d(DSL–HYL)
†
While HCS is not selected, HRDY is in high-Z state.
Figure 5–17. Nonmultiplexed Read Timings
73
December 1999 – Revised April 2002
SPRS122E
Electrical Specifications
HCS
t
w(DSH)
t
c(DSH–DSH)
HDS
t
su(HBV–DSL)
t
su(HBV–DSL)
t
t
h(DSL–HBV)
h(DSL–HBV)
HR/W
t
su(HAV–DSH)
t
w(DSL)
t
h(DSH–HAV)
Valid Address
Valid Address
su(HDV–DSH)W
HA[18:0]
HD[15:0]
t
t
su(HDV–DSH)W
t
h(DSH–HDV)W
t
h(DSH–HDV)W
Data Valid
Data Valid
t
d(DSH–HYH)
†
HRDY
t
d(DSH–HYL)
†
While HCS is not selected, HRDY is in high-Z state.
Figure 5–18. Nonmultiplexed Write Timings
HCS
t
su(SELV1–DSL)
t
h(DSH–SELV1)
HPI_SEL1
t
su(SELV2–DSL)
t
h(DSH–SELV2)
HPI_SEL2
HDS
Figure 5–19. HPI_SEL1 and HPI_SEL2 Timing
74
SPRS122E
December 1999 – Revised April 2002
Mechanical Data
6
Mechanical Data
6.1 Ball Grid Array Mechanical Data
GGU (S-PBGA-N169)
PLASTIC BALL GRID ARRAY
12,10
SQ
9,60 TYP
11,90
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
M
0,08
0,12
0,08
0,45
0,35
4073221-3/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Figure 6–1. TMS320VC5441 169-Ball MicroStar BGA Plastic Ball Grid Array (GGU) Package
MicroStar BGA is a trademark of Texas Instruments.
75
December 1999 – Revised April 2002
SPRS122E
Mechanical Data
6.2 Low-Profile Quad Flatpack Mechanical Data
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
0,17
M
0,08
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
0,25
0,05 MIN
26,20
SQ
0°–ā7°
25,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Figure 6–2. TMS320VC5441 176-Pin Low-Profile Quad Flatpack (PGF) Package
76
SPRS122E
December 1999 – Revised April 2002
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320VC5441AGGU
TMS320VC5441APGF
TMS320VC5441GGU
TMS320VC5441PGF
ACTIVE
ACTIVE
ACTIVE
ACTIVE
BGA
GGU
169
176
169
176
160
1
None
None
None
None
Call TI
CU
Level-3-220C-168HRS
Level-1-220C-UNLIM
Level-3-220C-168HRS
Level-1-220C-UNLIM
LQFP
BGA
PGF
GGU
160
40
Call TI
CU
LQFP
PGF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
相关型号：
TMS320VC5441GGUR
IC 16-BIT, 50 MHz, OTHER DSP, PBGA169, PLASTIC, BGA-169, Digital Signal Processor
TI
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