TMS320VC549PGE-100_技术文档

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

D

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

D

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

40-Bit Arithmetic Logic Unit (ALU)

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

– Time-Division Multiplexed (TDM) Serial

Port

– Buffered Serial Port (BSP)

– 8-Bit Parallel Host Port Interface (HPI)

– One 16-Bit Timer

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

D

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

– External-Input/Output (XIO) Off Control

to Disable the External Data Bus,

Address Bus and Control Signals

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

D

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

D

Data Bus With a Bus Holder Feature

Address Bus With a Bus Holder Feature

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space

D

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

†

IEEE Std 1149.1 (JTAG) Boundary Scan

D

192K × 16-Bit Maximum Addressable

Memory Space (64K Words Program,

64K Words Data, and 64K Words I/O)

Logic

D

12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS) for

3.3-V Power Supply)

On-Chip ROM with Some Configurable to

Program/Data Memory

10-ns Single-Cycle Fixed-Point Instruction

Execution Time (100 MIPS) for 3.3-V Power

Supply (2.5-V Core)

Dual-Access On-Chip RAM

Single-Access On-Chip RAM

Single-Instruction Repeat and

Block-Repeat Operations for Program Code

8.3-ns Single-Cycle Fixed-Point Instruction

Execution Time (120 MIPS) for 3.3-V Power

Supply (2.5-V Core) (Product Preview Data)

Block-Memory-Move Instructions for Better

Program and Data Management

Available in a 144-Pin Plastic Thin Quad

Flatpack (TQFP) (PGE Suffix) and a 144-Pin

Ball Grid Array (BGA) (GGU Suffix)

Instructions With a 32-Bit Long Word

Operand

Instructions With Two- or Three-Operand

Reads

NOTE: The data provided in this data sheet for the 8.3-ns, 120 MIPS device is considered to be

Product Preview data as the devices have not completed reliability performance qualification

testing according to TI Quality Systems Specifications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

Table of Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . 12

Recommended Operating Conditions . . . . . . . . . . . 12

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 13

Parameter Measurement Information . . . . . . . . . . . . 14

Timing Parameter Symbology . . . . . . . . . . . . . . . . . . 14

Signal Transition Reference Points . . . . . . . . . . . . . . 14

Internal Oscillator With External Crystal . . . . . . . . . 15

Divide-By-Two/Divide-By-Four Clock Option . . . . . 16

Multiply-By-N Clock Option . . . . . . . . . . . . . . . . . . . . 18

Memory and Parallel I/O Interface Timing . . . . . . . . 20

Timing Requirements for a Parallel I/O Port Read . 26

SPICE Simulation Results . . . . . . . . . . . . . . . . . . . . . 28

Ready Timing for Externally Generated Wait States 31

HOLD and HOLDA Timing . . . . . . . . . . . . . . . . . . . . . 36

Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . 38

Serial Port Receive Timing . . . . . . . . . . . . . . . . . . . . . 42

Buffered Serial Port Receive Timing . . . . . . . . . . . . . 45

Serial-Port Receive Timing in TDM Mode . . . . . . . . 49

Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . 53

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

description

The TMS320VC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’549) is based on

an advanced modified Harvard architecture that has one program memory bus and three data memory buses.

The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism,

application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’549 also utilizes

a highly specialized instruction set, which is the basis of its operational flexibility and speed.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the

high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions

with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’549

includes the control mechanisms to manage interrupts, repeated operations, and function calls.

This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549

DSP. For additional information, see the TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital

Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional

overview and should be used in conjunction with this data sheet.

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

†‡

PGE PACKAGE

(TOP VIEW)

1

108

V

A18

A17

SS

A22

2

107

3

106

V

DV

V

A16

D5

D4

D3

D2

D1

D0

RS

X2/CLKIN

X1

HD3

CLKOUT

SS

DD

SS

4

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

5

A10

HD7

A11

A12

A13

A14

A15

6

7

8

9

10

11

12

13

14

15

16

17

18

CV

HAS

DD

V

SS

DD

CV

HCS

V

SS

HPIENA

CV

HR/W

DD

READY 19

PS 20

V

TMS

SS

DS 21

IS 22

TCK

TRST

TDI

TDO

EMU1/OFF

EMU0

TOUT

HD2

TEST1

CLKMD3

CLKMD2

CLKMD1

R/W 23

MSTRB 24

IOSTRB 25

MSC 26

XF 27

HOLDA 28

IAQ 29

HOLD 30

BIO 31

MP/MC 32

DV

V

33

V

DD

SS

DV

34

DD

BDR1 35

BFSR1 36

BDX1

BFSX1

†

‡

NC = No connection

DV

is the power supply for the I/O pins while CV

DD

is the power supply for the core CPU, and V is the ground for both the I/O pins and the

SS

DD

core CPU.

For the 144-pin TQFP, the letter B in front of CLKRn, FSRn, DRn, CLKXn, FSXn, and DXn pin names denotes

buffered serial port (BSP), where n = 0 or 1 port. The letter T in front of CLKR, FSR, DR, CLKX, FSX, and DX

pin names denotes time-division multiplexed (TDM) serial port.

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

GGU PACKAGE

(BOTTOM VIEW)

13 12 11 10

9

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4

3

2

1

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B

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J

K

L

M

N

The pin assignments table to follow lists each signal quadrant and BGA ball pin number for the 144-pin BGA

package.

The ’549 signal descriptions table lists each terminal name, function, and operating mode(s).

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

†

Pin Assignments for the 144-Pin GGU Package

SIGNAL

QUADRANT 1

SIGNAL

QUADRANT 2

SIGNAL

QUADRANT 3

SIGNAL

QUADRANT 4

BGA BALL #

V

A1

B1

C2

C1

D4

D3

D2

D1

E4

E3

E2

E1

F4

F3

F2

F1

G2

G1

G3

G4

H1

H2

H3

H4

J1

BFSX1

BDX1

N13

M13

L12

L13

K10

K11

K12

K13

J10

J11

V

N1

N2

M3

N3

K4

A19

A20

A13

A12

B11

A11

D10

C10

B10

A10

D9

C9

B9

SS

A22

SS

BCLKR1

HCNTL0

V

DV

V

SS

DV

DD

SS

DV

V

SS

V

SS

DD

A10

DD

D6

CLKMD1

CLKMD2

CLKMD3

TEST1

HD2

BCLKR0

TCLKR

BFSR0

HD7

A11

A12

A13

A14

A15

L4

D7

D8

M4

N4

K5

TFSR/TADD

BDR0

D9

D10

D11

D12

HD4

D13

D14

D15

HD5

TOUT

HCNTL1

TDR

L5

EMU0

EMU1/OFF

TDO

J12

J13

H10

H11

H12

H13

G12

G13

G11

G10

F13

F12

F11

F10

E13

E12

E11

E10

D13

D12

D11

C13

C12

C11

B13

B12

M5

N5

K6

CV

DD

HAS

BCLKX0

TCLKX

A9

D8

C8

B8

V

TDI

V

SS

L6

SS

TRST

HINT

CVDD

M6

N6

M7

N7

L7

SS

CV

DD

HCS

TCK

A8

TMS

BFSX0

CV

B7

DD

HR/W

READY

PS

V

TFSX/TFRM

HRDY

V

SS

HDS1

A7

SS

CV

C7

D7

A6

DD

HPIENA

DV

K7

V

DD

SS

HDS2

DV

DS

V

SS

V

SS

N8

M8

L8

IS

CLKOUT

HD3

X1

HD0

BDX0

TDX

IACK

HBIL

NMI

B6

DD

A0

R/W

C6

D6

A5

MSTRB

IOSTRB

MSC

XF

K8

A1

A2

A3

HD6

A4

A5

A6

A7

A8

A9

X2/CLKIN

RS

N9

M9

L9

J2

B5

J3

D0

C5

D5

A4

HOLDA

IAQ

J4

D1

INT0

INT1

INT2

INT3

K9

K1

K2

K3

L1

D2

N10

M10

L10

N11

M11

L11

N12

M12

HOLD

BIO

D3

B4

D4

C4

A3

MP/MC

D5

CV

DD

DV

L2

A16

HD1

B3

DD

V

SS

L3

V

SS

V

SS

CV

DD

A21

C3

A2

BDR1

M1

M2

A17

A18

BCLKX1

BFSR1

V

SS

B2

SS

is the power supply for the core CPU, and V

†

DV

is the power supply for the I/O pins while CV

DD

is the ground for both the I/O pins and the

SS

DD

core CPU.

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

’549 Signal Descriptions

TERMINAL

DESCRIPTION

†

NAME

TYPE

DATA SIGNALS

A22 (MSB)

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

Parallel port address bus A22 (MSB) through A0 (LSB). The sixteen LSBs (A15–A0) are multiplexed to address

external data/program memory or I/O. A15–A0 are placed in the high-impedance state in the hold mode. A15–A0

also go into the high-impedance state when EMU1/OFF is low. The seven MSBs (A22 to A16) are used for

extended program memory addressing.

The address bus have a feature called bus holder that eliminates passive components and the power dissipation

associated with it. The bus holders keep the address bus at the previous logic level when the bus goes into a

high-impedance state. The bus holders on the address bus are always enabled.

O/Z

A8

A7

A6

A5

A4

A3

A2

A1

A0

(LSB)

D15 (MSB)

D14

D13

D12

D11

D10

D9

Parallel port data bus D15 (MSB) through D0 (LSB). D15–D0 are multiplexed to transfer data between the core

CPU and external data/program memory or I/O devices. D15–D0 are placed in the high-impedance state when

not output or when RS or HOLD is asserted. D15–D0 also go into the high-impedance state when EMU1/OFF

is low.

The data bus has a feature called bus holder that eliminates passive components and the power dissipation

associated with it. The bus holders keep the data bus at the previous logic level when the bus goes into a

high-impedance state. These bus holders are enabled or disabled by the BH bit in the bank switching control

register (BSCR).

D8

D7

I/O/Z

D6

D5

D4

D3

D2

D1

D0

(LSB)

INITIALIZATION, INTERRUPT AND RESET OPERATIONS

Interrupt acknowledge signal. IACK indicates the receipt of an interrupt and that the program counter is fetching

the interrupt vector location designated by A15–0. IACK also goes into the high-impedance state when

EMU1/OFF is low.

IACK

O/Z

I

INT0

INT1

INT2

INT3

External user interrupt inputs. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the

interrupt mode bit. INT0 –INT3 can be polled and reset by the interrupt flag register.

†

I = Input, O = Output, Z = High impedance

6

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

’549 Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

INITIALIZATION, INTERRUPT AND RESET OPERATIONS (CONTINUED)

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

NMI

RS

I

Reset input. RS causes the DSP to terminate execution and forces the program counter to 0FF80h. When RS

is brought to a high level, execution begins at location 0FF80h of the program memory. RS affects various

registers and status bits.

Microprocessor/microcomputer mode-select pin. If active-low at reset (microcomputer mode), MP/MC causes

the internal program ROM to be mapped into the upper program memory space. In the microprocessor mode,

off-chip memory and its corresponding addresses (instead of internal program ROM) are accessed by the DSP.

MP/MC

CNT

I

I/O level select. With CMOS-compatible I/O interface levels, CNT is pulled to a high level.

MULTIPROCESSING SIGNALS

Branch control input. A branch can be conditionally executed when BIO is active. If low, the processor executes

the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC

instruction, and all other instructions sample BIO during the read phase of the pipeline.

BIO

XF

I

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low

by RSBX XF instruction or by loading the ST1 status register. XF is used for signaling other processors in

multiprocessor configurations or as a general-purpose output pin. XF goes into the high-impedance state when

OFF is low, and is set high at reset.

O/Z

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating

to a particular external space. Active period corresponds to valid address information. Placed into a

high-impedance state in hold mode. DS, PS, and IS also go into the high-impedance state when EMU1/OFF is

low.

DS

PS

IS

O/Z

I

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data

or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance

state when OFF is low.

MSTRB

READY

R/W

Data-ready input. READY indicates that an external device is prepared for a bus transaction to be completed.

If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

processor performs ready-detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device and is normally

high (in read mode), unless asserted low when the DSP performs a write operation. Placed in the high-impedance

state in hold mode, R/W also goes into the high-impedance state when EMU1/OFF is low.

O/Z

I/O strobe signal. IOSTRB is always high unless low level asserted to indicate an external bus access to an I/O

device. Placed in high-impedance state in hold mode. IOSTRB also goes into the high-impedance state when

EMU1/OFF is low.

IOSTRB

HOLD

O/Z

I

Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged,

these lines go into high-impedance state.

Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that

the address, data, and control lines are in a high-impedance state, allowing them to be available to the external

circuitry. HOLDA also goes into the high-impedance state when EMU1/OFF is low.

HOLDA

O/Z

Microstate complete signal. Goes low on CLKOUT falling at the start of the first software wait state. Remains low

until one CLKOUT cycle before the last programmed software wait state. If connected to the READY line, MSC

forces one external wait state after the last internal wait state has been completed. MSC also goes into the

high-impedance state when EM1/OFF is low.

MSC

O/Z

†

I = Input, O = Output, Z = High impedance

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

’549 Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

MEMORY CONTROL SIGNALS (CONTINUED)

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus and goes into the high-impedance state when EMU1/OFF is low.

IAQ

O/Z

OSCILLATOR/TIMER SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

is bounded by the falling edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF

is low.

CLKOUT

O/Z

CLKMD1

CLKMD2

CLKMD3

Clock mode external/internal input signals. CLKMD1, CLKMD2, and CLKMD3 allow you to select and configure

different clock modes, such as crystal, external clock, and various PLL factors. Refer to PLL section for a detailed

functional description of these pins.

I

Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can

become input to the device using this pin. The internal machine cycle time is determined by the clock

operating-mode pins (CLKMD1, CLKMD2 and CLKMD3).

X2/CLKIN

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.

X1

O

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT-cycle

wide. TOUT also goes into the high-impedance state when EMU1/OFF is low.

TOUT

O/Z

BUFFERED SERIAL PORT 0 AND BUFFERED SERIAL PORT 1 SIGNALS

Receive clocks. External clock signal for clocking data from the data-receive (DR) pin into the buffered serial port

receive shift registers (RSRs). Must be present during buffered serial port transfers. If the buffered serial port is

not being used, BCLKR0 and BCLKR1 can be sampled as an input by way of IN0 bit of the SPC register.

BCLKR0

BCLKR1

I

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. BCLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven

by the device at 1/(CLKDV + 1) where CLKDV range is 0–31 CLKOUT frequency when MCM is set to 1. If the

buffered serial port is not used, BCLKX can be sampled as an input by way of IN1 of the SPC register. BCLKX0

and BCLKX1 go into the high-impedance state when OFF is low.

BCLKX0

BCLKX1

I/O/Z

BDR0

BDR1

I

O/Z

I

Buffered serial-data-receive input. Serial data is received in the RSR by BDR0/BDR1.

BDX0

BDX1

Buffered serial-port-transmit output. Serial data is transmitted from the XSR by way of BDX. BDX0 and BDX1 are

placed in the high-impedance state when not transmitting and when EMU1/OFF is low.

BFSR0

BFSR1

Frame synchronization pulse for receive input. The falling edge of the BFSR pulse initiates the data-receive

process, beginning the clocking of the RSR.

Frame synchronization pulse for transmit input/output. The falling edge of the BFSX pulse initiates the

data-transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of

BFSX is an input. BFSX0 and BFSX1 can be selected by software to be an output when TXM in the serial control

register is set to 1. This pin goes into the high-impedance state when EMU1/OFF is low.

BFSX0

BFSX1

I/O/Z

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS

Receive clocks. External clock signal for clocking data from the data receive (DR) pin into the serial port receive

shift register (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKR0 and

CLKR1 can be sampled as an input via IN0 bit of the SPC register.

CLKR0

CLKR1

I

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit

(DX) pin. CLKX can be an input if MCM in the serial port control register is cleared to 0. It also can be driven by

the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled

as an input via IN1 of the SPC register. CLKX0 and CLKX1 go into the high-impedance state when EMU1/OFF

is low.

CLKX0

CLKX1

I/O/Z

I

DR0

DR1

Serial-data-receive input. Serial data is received in the RSR by DR.

†

I = Input, O = Output, Z = High impedance

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

’549 Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS (CONTINUED)

DX0

DX1

Serial port transmit output. Serial data is transmitted from the XSR via DX. DX0 and DX1 are placed in the

high-impedance state when not transmitting and when EMU1/OFF is low.

O/Z

I

FSR0

FSR1

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive

process, beginning the clocking of the RSR.

Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data transmit

process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is an input.

FSX0 and FSX1 can be selected by software to be an output when TXM in the serial control register is set to 1.

This pin goes into the high-impedance state when EMU1/OFF is low.

FSX0

FSX1

I/O/Z

TDM SERIAL PORT SIGNALS

TDM receive clock input

TCLKR

I

TDR

I

TDM serial data-receive input

TFSR/TADD

TCLKX

I/O

TDM receive frame synchronization or TDM address

TDM transmit clock

I/O/Z

O/Z

I/O/Z

TDX

TDM serial data-transmit output

TFSX/TFRM

TDM transmit frame synchronization

HOST PORT INTERFACE SIGNALS

Parallel bidirectional data bus. HD0–HD7 are placed in the high-impedance state when not outputting data. The

signals go into the high-impedance state when EMU1/OFF is low. These pins each have bus holders similar to

those on the address/data bus, but which are always enabled.

HD0–HD7

I/O/Z

I

HCNTL0

HCNTL1

Control inputs

HBIL

HCS

I

Byte-identification input

Chip-select input

HDS1

HDS2

I

Data strobe inputs

HAS

I

Address strobe input

HR/W

HRDY

Read/write input

O/Z

Ready output. This signal goes into the high-impedance state when EMU1/OFF is low.

Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance

HINT

O/Z

I

state when EMU1/OFF is low.

HPI module select input. This signal must be tied to a logic 1 state to have HPI selected. If this input is left open

or connected to ground, the HPI module will not be selected, internal pullup for the HPI input pins are enabled,

and the HPI data bus has keepers set. This input is provided with an internal pull-down resistor which is active

only when RS is low. HPIENA is sampled when RS goes high and ignored until RS goes low again. Refer to the

Electrical Characteristics section for the input current requirements for this pin.

HPIENA

SUPPLY PINS

CV

DV

Supply

+V . CV

DD

is the dedicated power supply for the core CPU.

is the dedicated power supply for I/O pins.

is the dedicated power ground for the device.

DD

SS

+V . DV

DD

V

†

Ground. V

SS

I = Input, O = Output, Z = High impedance

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

’549 Signal Descriptions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

IEEE1149.1 TEST PINS

IEEE standard 1149.1 test clock. Pin with internal pullup device. This is normally a free-running clock signal with

a 50% duty cycle. The changes on the test-access port (TAP) of input signals TMS and TDI are clocked into the

TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP

output signal (TDO) occur on the falling edge of TCK.

TCK

I

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDI

I

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when EMU1/OFF is low.

TDO

TMS

TRST

O/Z

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

Emulator interrupt 0 pin. When TRST is driven low, EMU0 must be high for the activation of the EMU1/OFF

condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined

as input/output by way of IEEE standard 1149.1 scan system.

EMU0

I/O/Z

Emulator interrupt 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or

from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When

TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output

drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not

for multiprocessing applications). Therefore, for the OFF condition, the following conditions apply:

TRST = low,

EMU1/OFF

I/O/Z

EMU0 = high

EMU1/OFF = low

DEVICE TEST PIN

TEST1

I

Test1 – Reserved for internal use only. This pin must not be connected (NC).

†

I = Input, O = Output, Z = High impedance

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†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

DD

‡

Supply voltage core range, CV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.75 V

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

3

NOM

3.3

MAX

3.6

UNIT

V

†

Device supply voltage, I/O

DV

CV

DD

†

Device supply voltage, core

Supply voltage, GND

2.4

2.5

2.75

V

0

V

SS

Schmitt trigger inputs, DV

DD

=

2.5

DV

+ 0.3

DD

‡

3.3"0.3 V

High-level input voltage, I/O

V

IH

All other inputs

2

+ 0.3

Low-level input voltage

High-level output current

Low-level output current

Operating case temperature

–0.3

0.8

V

IL

I

–300

1.5

µA

mA

°C

OH

OL

I

T

C

–40

100

†

Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be

designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.

Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention

may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and

powered down after), the I/O buffers. For additional power sequencing information, see the Power Supply Sequencing Solutions For Dual Supply

Voltage DSPs application report (literature number SLVA073).

‡

On the ’VC549 devices, the following pins have schmitt trigger inputs: RS, INTn, NMI, X2/CLKIN, CLKMDn, TCK, HAS, HCS, HDSn, BCLKRn,

TCLKR, BCLKXn, and TCLKX

Refer to Figure 1 for 3.3-V device test load circuit values.

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electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

†

TYP

PARAMETER

TEST CONDITIONS

= 3.3"0.3 V, = MAX

MIN

2.4

MAX

UNIT

‡

V

DD

I

OH

V

High-level output voltage

OH

‡

Low-level output voltage

I

= MAX

0.4

V

OL

A[22:0]

V

= MAXk

–150

–10

250

DD

Input current in high

impedance

I

IZ

µA

All other pins

V

DD

= MAX, V = V to V

SS DD

10

I

TRST

With internal pulldown

–10

800

400

10

HPIENA

With internal pulldown, RS = 0

With internal pullups

||

TMS, TCK, TDI, HPI

D[15:0], HD[7:0]

X2/CLKIN

–400

–150

–40

Input current

I

µA

(V = V

SS

to V )

DD

Bus holders enabled, V

= MAXk

250

40

I

DD

Oscillator enabled

All other input-only pins

–10

10

§

¶

#

2

I

Supply current, core CPU

Supply current, pins

CV

DV

= 2.5 V, f = 40 MHz,

T

= 25°C

20

mA

DDC

DD

x

C

= 3.3 V, f = 40 MHz,

12

mA

DDP

x

C

IDLE2

PLL × 1 mode, 40 MHz input

Divide-by-two mode, CLKIN stopped

(’VC549-80 and ’VC549-100)

15

Supply current,

standby

I

DD

IDLE3

µA

Divide-by-two mode, CLKIN stopped

(’VC549-120 only)

170

C

Input capacitance

Output capacitance

10

pF

i

o

†

‡

§

¶

All values are typical unless otherwise specified.

All input and output voltage levels except RS, INT0–INT3, NMI, CNT, X2/CLKIN, CLKMD0–CLKMD3 are LVTTL-compatible.

Clock mode: PLL × 1 with external source

This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being

executed.

#

||

This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,

refer to the Calculation of TMS320C54x Power Dissipation application report (literature number SPRA164).

HPI input signals except for HPIENA.

kV

≤ V ≤ V

IL(MAX)

or V

IH(MIN)

≤ V ≤ V

IH(MAX)

IL(MIN)

I

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their meanings:

Letters and symbols and their meanings:

a

access time

H

L

High

c

cycle time (period)

delay time

Low

d

V

Z

Valid

dis

en

f

disable time

High impedance

enable time

fall time

h

hold time

r

rise time

su

t

setup time

transition time

valid time

v

w

X

pulse duration (width)

Unknown, changing, or don’t care level

signal transition reference points

All timing references are made at a voltage of 1.5 volts, except rise and fall times which are referenced at the

10% and 90% points of the specified low and high logic levels, respectively.

I

OL

50 Ω

Output

Under

Test

Tester Pin

Electronics

V

Load

C

T

I

OH

Where: I

I

= 1.5 mA (all outputs)

= 300 µA (all outputs)

= 1.5 V

OL

OH

Load

T

V

C

= 40 pF typical load circuit capacitance.

Figure 1. 3.3-V Test Load Circuit

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internal oscillator with external crystal

The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device dependent –

see PLL section) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock

frequency is one-half the crystal’s oscillation frequency following reset. After reset, the clock mode of the devices

with the software PLL can also be changed to divide-by-four.

The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance

of 30ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and

two load capacitors, is shown in Figure 2. The load capacitors, C and C , should be chosen such that the

1

2

equation below is satisfied. C in the equation is the load specified for the crystal.

L

C₁C₂

C_L+

(C₁) C₂)

recommended operating conditions (see Figure 2)

’549-80

’549-100

’549-120

UNIT

MIN NOM

MAX

MIN NOM

MAX

MIN NOM

MAX

†

10

‡

20

†

10

‡

20

†

10

‡

20

f

x

Input clock frequency

MHz

†

‡

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

It is recommended that the PLL clocking option be used for maximum frequency operation.

approaching ∞. The device is characterized at frequencies

c(CI)

X1

X2/CLKIN

Crystal

C1

C2

Figure 2. Internal Divide-by-Two Clock Option With External Crystal

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divide-by-two/divide-by-four clock option – PLL disabled

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to

generate the internal machine cycle.

When an external clock source is used, the frequency injected must conform to specifications listed in the timing

requirements table.

switching characteristics over recommended operating conditions for divide-by-two/

divide-by-four clock option – PLL disabled [H = 0.5t

recommended operating conditions table)

] (see Figure 2 and Figure 3, and the

c(CO)

’549-80

’549-100

TYP

’549-120

TYP

PARAMETER

UNIT

ns

MIN

TYP

MAX

MIN

MAX

MIN

MAX

‡

12.5

†

‡

10

†

‡

8.33

†

t

Cycle time, CLKOUT

2t

c(CI)

2t

c(CO)

c(CI)

6

c(CI)

6

Delay time, X2/CLKIN high to

CLKOUT high/low

t

3

6

10

3

10

3

10

ns

d(CIH-CO)

†

t

Fall time, CLKOUT

2

ns

f(CO)

†

t

Rise time, CLKOUT

r(CO)

†

Pulse duration, CLKOUT low

H–3

H–1

H

H–2

H–1

H

H–2

H–1

H

w(COL)

w(COH)

†

Pulse duration, CLKOUT high

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

It is recommended that the PLL clocking option be used for maximum frequency operation.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

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divide-by-two/divide-by-four clock option – PLL disabled (continued)

timing requirements for divide-by-two/divide-by-four clock option – PLL disabled (see Figure 3)

’549-80

MIN MAX

’549-100

MIN MAX

’549-120

MIN MAX

UNIT

‡

†

‡

†

‡

†

t

Cycle time, X2/CLKIN

20

ns

c(CI)

Fall time, X2/CLKIN

8

f(CI)

Rise time, X2/CLKIN

8

†

8

†

8

†

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

5

w(CIL)

w(CIH)

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

It is recommended that the PLL clocking option be used for maximum frequency operation.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

t

r(CI)

t

f(CI)

t

w(CIH)

t

c(CI)

X2/CLKIN

CLKOUT

t

w(CIL)

t

w(COH)

t

f(CO)

t

c(CO)

t

r(CO)

t

d(CIH-CO)

t

w(COL)

Figure 3. External Divide-by-Two Clock Timing

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multiply-by-N clock option – PLL enabled

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate

the internal machine cycle.

When an external clock source is used, the frequency injected must conform to specifications listed in the timing

requirements table.

switching characteristics over recommended operating conditions for multiply-by-N clock option

– PLL enabled [H = 0.5t

conditions table)

] (see Figure 2 and Figure 4, and the recommended operating

c(CO)

’549-80

TYP

’549-100

TYP

’549-120

TYP

PARAMETER

UNIT

ns

MIN

MAX

MIN

MAX

MIN

MAX

t

Cycle time, CLKOUT

12.5

t

10

t

8.33

t

c(CO)

c(CI)/N

6

c(CI)/N

6

c(CI)/N

6

Delay time, X2/CLKIN high/low to

CLKOUT high/low

t

3

10

3

10

3

10

ns

d(CIH-CO)

t

Fall time, CLKOUT

2

ns

ms

f(CO)

r(CO)

w(COL)

w(COH)

p

t

Rise time, CLKOUT

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Transitory phase, PLL lock-up time

H–3

H–1

H

H–2

H–1

H

H–2

H–1

H

29

35

45

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multiply-by-N clock option – PLL enabled (continued)

timing requirements for multiply-by-N clock option – PLL enabled (see Figure 4)

’549-100

’549-120

’549-80

UNIT

MIN

MAX

200

100

50

MIN

MAX

†

20

†

20

†

20

†

20

†

20

†

20

Integer PLL multiplier N (N = 1–15)

PLL multiplier N = x.5

200

100

50

t

Cycle time, X2/CLKIN

ns

c(CI)

PLL multiplier N = x.25, x.75

t

Fall time, X2/CLKIN

8

ns

f(CI)

Rise time, X2/CLKIN

r(CI)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

5

w(CIL)

w(CIH)

†

Note that for all values of t

, the minimum t

period must not be exceeded.

c(CI)

c(CO)

t

f(CI)

t

w(CIL)

t

w(CIH)

r(CI)

t

c(CI)

X2/CLKIN

t

d(CIH-CO)

t

f(CO)

t

w(COH)

t

c(CO)

t

w(COL)

t

tp

r(CO)

Unstable

CLKOUT

Figure 4. External Multiply-by-One Clock Timing

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a memory read

†‡

(MSTRB = 0) (see Figure 5)

’549-80

MIN

– 1

’549-100

MIN MAX

’549-120

MIN MAX

PARAMETER

UNIT

MAX

§

t

Delay time, address valid from CLKOUT low

5

– 1

–1

4

5

4

– 1

–1

4

3

4

ns

d(CLKL-A)

¶

Delay time, address valid from CLKOUT high (transition)

Delay time, MSTRB low from CLKOUT low

– 1

d(CLKH-A)

t

– 1

d(CLKL-MSL)

t

Delay time, MSTRB high from CLKOUT low

– 1

d(CLKL-MSH)

§

t

Hold time, address valid after CLKOUT low

– 1

h(CLKL-A)R

h(CLKH-A)R

¶

t

Hold time, address valid after CLKOUT high

– 1

†

Address, PS, and DS timings are all included in timings referenced as address.

‡

§

¶

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

In the case of a memory read preceded by a memory read

In the case of a memory read preceded by a memory write

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

†‡

timing requirements for a memory read (MSTRB = 0) [H = 0.5 t

]

(see Figure 5)

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

2H–9

2H–8

MIN

MAX

2H–8

2H–7

MIN

MAX

t

Access time, read data access from address valid

Access time, read data access from MSTRB low

Setup time, read data before CLKOUT low

Hold time, read data after CLKOUT low

2H–8

2H–7

ns

a(A)M

a(MSTRBL)

su(D)R

5

0

5

0

5

0

h(D)R

Hold time, read data after address invalid

Hold time, read data after MSTRB high

h(A-D)R

h(D)MSTRBH

†

‡

Address, PS, and DS timings are all included in timings referenced as address.

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

CLKOUT

t

d(CLKL-A)

t

h(CLKL-A)R

A[15:0]

t

h(A-D)R

t

su(D)R

t

a(A)M

t

h(D)R

D[15:0]

t

h(D)MSTRBH

t

d(CLKL-MSL)

t

d(CLKL-MSH)

t

a(MSTRBL)

MSTRB

R/W

PS, DS

Figure 5. Memory Read (MSTRB = 0)

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

†‡

(MSTRB = 0) [H = 0.5 t

]

(see Figure 6)

c(CO)

’549-80

MIN MAX

’549-100

MIN MAX

’549-120

MIN MAX

UNIT

ns

PARAMETER

Delay time, address valid from CLKOUT high

§

t

– 1

5

7

5

– 1

0

4

7

5

4

– 1

0

4

3

5

3

4

d(CLKH-A)

¶

Delay time, address valid from CLKOUT low

Delay time, MSTRB low from CLKOUT low

Delay time, data valid from CLKOUT low

Delay time, MSTRB high from CLKOUT low

Delay time, R/W low from CLKOUT high

Delay time, R/W high from CLKOUT high

Delay time, MSTRB low after R/W low

ns

d(CLKL-A)

t

– 1

ns

d(CLKL-MSL)

t

0

ns

d(CLKL-D)W

t

– 1

0

– 1

ns

d(CLKL-MSH)

t

0

ns

d(CLKH-RWL)

t

– 1

ns

d(CLKH-RWH)

t

H – 2

– 1

H + 3 H – 2

H + 2 H – 2 H + 2

ns

d(RWL-MSTRBL)

§

t

Hold time, address valid after CLKOUT high

Hold time, write data valid after MSTRB high

Pulse duration, MSTRB low

5

– 1

4

– 1

4

ns

h(A)W

¶

t

H–4

2H–5

2H–7

H+4

H–3 H+3

ns

h(D)MSH

w(SL)MS

su(A)W

2H–4

Setup time, address valid before MSTRB low

2H–4

¶

2H–4 2H+4

Setup time, write data valid before MSTRB high

2H+7

2H–5 2H+5

su(D)MSH

†

Address, PS, and DS timings are all included in timings referenced as address.

‡

§

¶

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

In the case of a memory write preceded by a memory write.

In the case of a memory write preceded by an I/O cycle.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

CLKOUT

t

d(CLKH-A)

t

d(CLKL-A)

t

h(A)W

A[15:0]

D[15:0]

MSTRB

R/W

t

d(CLKL-D)W

t

h(D)MSH

t

su(D)MSH

t

d(CLKL-MSL)

t

d(CLKL-MSH)

t

su(A)W

t

d(CLKH-RWL)

d(CLKH-RWH)

t

w(SL)MS

t

d(RWL-MSTRBL)

PS, DS

Figure 6. Memory Write (MSTRB = 0)

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port read

†‡

(IOSTRB = 0) (see Figure 7)

’549-80

MIN

– 1

’549-100

MIN

– 1

’549-120

MIN

– 1

PARAMETER

UNIT

MAX

t

Delay time, address valid from CLKOUT low

Delay time, IOSTRB low from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Hold time, address after CLKOUT low

5

4

ns

d(CLKL-A)

t

0

d(CLKH-ISTRBL)

t

– 1

d(CLKH-ISTRBH)

t

– 1

h(A)IOR

†

‡

Address and IS timings are included in timings referenced as address.

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t

†‡

]

(see Figure 7)

c(CO)

’549-80

MAX

’549-100

’549-120

UNIT

MIN

MAX

3H–8

2H–8

MIN

MAX

3H–8

2H–7

t

Access time, read data access from address valid

Access time, read data access from IOSTRB low

Setup time, read data before CLKOUT high

Hold time, read data after CLKOUT high

3H–9

2H–9

ns

a(A)IO

a(ISTRBL)IO

su(D)IOR

4

0

4

0

h(D)IOR

Hold time, read data after IOSTRB high

h(ISTRBH-D)R

†

‡

Address and IS timings are included in timings referenced as address.

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

CLKOUT

t

h(A)IOR

d(CLKL-A)

A[15:0]

t

h(D)IOR

t

su(D)IOR

t

a(A)IO

D[15:0]

t

h(ISTRBH-D)R

d(CLKH-ISTRBH)

t

a(ISTRBL)IO

t

d(CLKH-ISTRBL)

IOSTRB

R/W

IS

Figure 7. Parallel I/O Port Read (IOSTRB = 0)

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

†

(IOSTRB = 0) [H = 0.5 t

] (see Figure 8)

c(CO)

’549-80

MIN

’549-100

’549-120

PARAMETER

UNIT

MAX

5

MIN MAX

‡

t

Delay time, address valid from CLKOUT low

– 1

0

– 1

0

4

– 1

0

4

ns

d(CLKL-A)

t

Delay time, IOSTRB low from CLKOUT high

5

d(CLKH-ISTRBL)

t

Delay time, write data valid from CLKOUT high

Delay time, IOSTRB high from CLKOUT high

Delay time, R/W low from CLKOUT low

Delay time, R/W high from CLKOUT low

H–5

– 1

0

H+7

5

H–5

– 1

0

H+7

4

H–5

– 1

0

H+6

4

d(CLKH-D)IOW

t

d(CLKH-ISTRBH)

t

5

4

d(CLKL-RWL)

d(CLKL-RWH)

h(A)IOW

t

0

5

0

4

0

4

‡

Hold time, address valid from CLKOUT low

Hold time, write data after IOSTRB high

Setup time, write data before IOSTRB high

– 1

H–4

H–5

5

– 1

H–3

H–5

4

– 1

H–3

H–5

4

H+4

H+1

H+3

H+1

H+3

H

h(D)IOW

su(D)IOSTRBH

Setup time, address valid before IOSTRB low

H–5

H+5

H–3

H+3

H–3

H+3

ns

su(A)IOSTRBL

†

‡

See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

Address and IS timings are included in timings referenced as address.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

memory and parallel I/O interface timing (continued)

CLKOUT

t

su(A)IOSTRBL

t

h(A)IOW

t

d(CLKL-A)

A[15:0]

t

d(CLKH-D)IOW

t

h(D)IOW

D[15:0]

t

d(CLKH-ISTRBL)

t

d(CLKH-ISTRBH)

t

su(D)IOSTRBH

t

IOSTRB

R/W

t

d(CLKL-RWL)

d(CLKL-RWH)

IS

Figure 8. Parallel I/O Port Write (IOSTRB = 0)

I/O timing variation with load capacitance: SPICE simulation results

Condition: Temperature : 125° C

Capacitance : 0–100pF

Voltage

Model

: 2.7/3.0/3.3 V

: Weak/Nominal/Strong

90%

10%

Figure 9. Rise and Fall Time Diagram

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

I/O timing variation with load capacitance: SPICE simulation results (continued)

Table 1. Timing Variation With Load Capacitance: [2.7 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.476 ns

1.511 ns

2.551 ns

3.614 ns

4.664 ns

5.752 ns

6.789 ns

7.817 ns

8.897 ns

10.021 ns

11.072 ns

0.457 ns

1.278 ns

2.133 ns

3.011 ns

3.899 ns

4.786 ns

5.656 ns

6.598 ns

7.531 ns

8.332 ns

9.299 ns

0.429 ns

1.386 ns

2.350 ns

3.327 ns

4.394 ns

5.273 ns

6.273 ns

7.241 ns

8.278 ns

9.152 ns

10.208 ns

0.391 ns

1.148 ns

1.956 ns

2.762 ns

3.566 ns

4.395 ns

5.206 ns

6.000 ns

6.928 ns

7.735 ns

8.537 ns

0.382 ns

1.215 ns

2.074 ns

2.929 ns

3.798 ns

4.655 ns

5.515 ns

6.442 ns

7.262 ns

8.130 ns

8.997 ns

0.323 ns

1.049 ns

1.779 ns

2.512 ns

3.264 ns

4.010 ns

4.750 ns

5.487 ns

6.317 ns

7.066 ns

7.754 ns

Table 2. Timing Variation With Load Capacitance: [3 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.436 ns

1.349 ns

2.273 ns

3.226 ns

4.168 ns

5.110 ns

6.033 ns

7.077 ns

8.020 ns

8.917 ns

9.885 ns

0.387 ns

1.185 ns

1.966 ns

2.765 ns

3.573 ns

4.377 ns

5.230 ns

5.997 ns

6.899 ns

7.709 ns

8.541 ns

0.398 ns

1.240 ns

2.098 ns

2.974 ns

3.849 ns

4.732 ns

5.660 ns

6.524 ns

7.416 ns

8.218 ns

9.141 ns

0.350 ns

1.064 ns

1.794 ns

2.539 ns

3.292 ns

4.052 ns

4.811 ns

5.601 ns

6.336 ns

7.124 ns

7.830 ns

0.345 ns

1.092 ns

1.861 ns

2.637 ns

3.406 ns

4.194 ns

5.005 ns

5.746 ns

6.559 ns

7.323 ns

8.101 ns

0.290 ns

0.964 ns

1.634 ns

2.324 ns

3.013 ns

3.710 ns

4.401 ns

5.117 ns

5.861 ns

6.498 ns

7.238 ns

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

I/O timing variation with load capacitance: SPICE simulation results (continued)

Table 3. Timing Variation With Load Capacitance: [3.3 V] 10% – 90% [3 V] 10% – 90%

WEAK

NOMINAL

STRONG

RISE

FALL

RISE

FALL

RISE

FALL

0 pF

10 pF

20 pF

30 pF

40 pF

50 pF

60 pF

70 pF

80 pF

90 pF

100 pF

0.404 ns

1.227 ns

2.070 ns

2.931 ns

3.777 ns

4.646 ns

5.487 ns

6.405 ns

7.284 ns

8.159 ns

8.994 ns

0.361 ns

1.081 ns

1.822 ns

2.567 ns

3.322 ns

4.091 ns

4.859 ns

5.608 ns

6.463 ns

7.097 ns

7.935 ns

0.371 ns

1.133 ns

1.915 ns

2.719 ns

3.515 ns

4.319 ns

5.145 ns

5.980 ns

6.723 ns

7.560 ns

8.300 ns

0.310 ns

1.001 ns

1.675 ns

2.367 ns

3.072 ns

3.779 ns

4.503 ns

5.234 ns

5.873 ns

6.692 ns

7.307 ns

0.321 ns

1.000 ns

1.704 ns

2.414 ns

3.120 ns

3.842 ns

4.571 ns

5.301 ns

5.941 ns

6.740 ns

7.431 ns

0.284 ns

0.892 ns

1.530 ns

2.169 ns

2.823 ns

3.466 ns

4.142 ns

4.767 ns

5.446 ns

6.146 ns

6.822 ns

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

ready timing for externally generated wait states

†

timing requirements for externally generated wait states [H = 0.5 t

Figure 12, and Figure 13)

] (see Figure 10, Figure 11,

c(CO)

’549-80

’549-100

MIN MAX

’549-120

MIN MAX

UNIT

MIN

6

MAX

t

Setup time, READY before CLKOUT low

Hold time, READY after CLKOUT low

5

0

5

0

ns

su(RDY)

0

h(RDY)

‡

Valid time, READY after MSTRB low

4H–10

5H–10

4H–8

5H–8

4H–8

5H–8

v(RDY)MSTRB

h(RDY)MSTRB

v(RDY)IOSTRB

h(RDY)IOSTRB

v(MSCL)

‡

Hold time, READY after MSTRB low

4H

‡

Valid time, READY after IOSTRB low

‡

Hold time, READY after IOSTRB low

5H

0

5H

0

5H

0

Valid time, MSC low after CLKOUT low

Valid time, MSC high after CLKOUT low

5

4

0

v(MSCH)

†

The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by

READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

‡

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

ready timing for externally generated wait states (continued)

CLKOUT

A[15:0]

t

su(RDY)

t

h(RDY)

READY

MSTRB

MSC

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait State

Generated

by READY

Wait States

Generated Internally

Figure 10. Memory Read With Externally Generated Wait States

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

ready timing for externally generated wait states (continued)

CLKOUT

A[15:0]

D[15:0]

t

h(RDY)

t

su(RDY)

READY

MSTRB

MSC

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait States

Generated Internally

Wait State Generated

by READY

Figure 11. Memory Write With Externally Generated Wait States

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

ready timing for externally generated wait states (continued)

CLKOUT

A[15:0]

t

h(RDY)

t

su(RDY)

READY

IOSTRB

MSC

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait

States

Generated

Internally

Figure 12. I/O Read With Externally Generated Wait States

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

ready timing for externally generated wait states (continued)

CLKOUT

A[15:0]

D[15:0]

t

h(RDY)

t

su(RDY)

READY

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

IOSTRB

MSC

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait States

Generated

Internally

Figure 13. I/O Write With Externally Generated Wait States

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

HOLD and HOLDA timing

switching characteristics over recommended operating conditions for memory control signals

and HOLDA [H = 0.5 t

] (see Figure 14)

c(CO)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

MAX

t

Disable time, CLKOUT low to address, PS, DS, IS high impedance

Disable time, CLKOUT low to R/W high impedance

5

ns

dis(CLKL-A)

dis(CLKL-RW)

Disable time, CLKOUT low to MSTRB, IOSTRB high

impedance

t

5

ns

dis(CLKL-S)

t

Enable time, CLKOUT low to address, PS, DS, IS

Enable time, CLKOUT low to R/W enabled

2H+5

ns

en(CLKL-A)

en(CLKL-RW)

en(CLKL-S)

Enable time, CLKOUT low to MSTRB, IOSTRB enabled

2

0

5

ns

Valid time, HOLDA low after CLKOUT low

t

v(HOLDA)

0

Valid time, HOLDA high after CLKOUT low

Pulse duration, HOLDA low duration

2H–3

w(HOLDA)

timing requirements for HOLD [H = 0.5 t

] (see Figure 14)

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

t

Pulse duration, HOLD low duration

Setup time, HOLD before CLKOUT low

4H+10

10

ns

w(HOLD)

su(HOLD)

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

HOLD and HOLDA timing (continued)

CLKOUT

t

su(HOLD)

t

w(HOLD)

HOLD

t

v(HOLDA)

t

w(HOLDA)

HOLDA

t

dis(CLKL-A)

t

en(CLKL-A)

A[15:0]

PS, DS, IS

D[15:0]

R/W

t

dis(CLKL-RW)

dis(CLKL-S)

en(CLKL-RW)

t

en(CLKL-S)

MSTRB

IOSTRB

t

en(CLKL-S)

Figure 14. HOLD and HOLDA Timing (HM = 1)

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

reset, BIO, interrupt, and MP/MC timings

timing requirements over recommended operating conditions for reset, interrupt, BIO, and MP/MC

[H = 0.5 t ] (see Figure 15, Figure 16, and Figure 17) (continued)

c(CO)

’549-80

’549-100

’549-120

MIN MAX

UNIT

MIN

0

MAX

MIN

0

MAX

t

Hold time, RS after CLKOUT low

0

ns

h(RS)

Hold time, BIO after CLKOUT low

0

h(BIO)

†

Hold time, INTn, NMI, after CLKOUT low

0

h(INT)

Hold time, MP/MC after CLKOUT low

0

h(MPMC)

w(RSL)

‡§¶

Pulse duration, RS low

4H+7

2H+7

4H

2H+7

4H

2H+7

4H

10

4H+5

2H+5

4H

2H+7

4H

2H+7

4H

8

4H+5

2H+5

4H

2H+7

4H

2H+7

4H

8

Pulse duration, BIO low, synchronous

Pulse duration, BIO low, asynchronous

w(BIO)S

w(BIO)A

w(INTH)S

w(INTH)A

w(INTL)S

w(INTL)A

w(INTL)WKP

su(RS)

Pulse duration, INTn, NMI high (synchronous)

Pulse duration, INTn, NMI high (asynchronous)

Pulse duration, INTn, NMI low (synchronous)

Pulse duration, INTn, NMI low (asynchronous)

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

§

Setup time, RS before X2/CLKIN low

5

Setup time, BIO before CLKOUT low

10

2H

9

2H

8

2H

su(BIO)

Setup time, INTn, NMI, RS before CLKOUT low

Setup time, MP/MC before CLKOUT low

10

9

8

su(INT)

10

8

su(MPMC)

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is

corresponding to three CLKOUTs sampling sequence.

If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to assure synchronization

and lock-in of the PLL.

‡

§

¶

Divide-by-two mode

Note that RS may cause a change in clock frequency, therefore changing the value of H (see the PLL section).

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

reset, BIO, interrupt, and MP/MC timings (continued)

X2/CLKIN

t

su(RS)

t

w(RSL)

RS, INTn, NMI

t

su(INT)

t

h(RS)

CLKOUT

t

su(BIO)

t

h(BIO)

BIO

t

w(BIO)S

Figure 15. Reset and BIO Timings

CLKOUT

t

su(INT)

h(INT)

INTn, NMI

t

w(INTH)A

t

w(INTL)A

Figure 16. Interrupt Timing

CLKOUT

RS

t

h(MPMC)

t

su(MPMC)

MP/MC

Figure 17. MP/MC Timing

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing

switching characteristics over recommended operating conditions for IAQ and IACK

[H = 0.5 t

] (see Figure 18)

c(CO)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

– 1

MAX

MIN

– 1

MAX

t

Delay time, IAQ low from CLKOUT low

Delay time, IAQ high from CLKOUT low

Delay time, address valid before IAQ low

Delay time, IACK low from CLKOUT low

Delay time , IACK high from CLKOUT low

Delay time, address valid before IACK low

Hold time, address valid after IAQ high

Hold time, address valid after IACK high

Pulse duration, IAQ low

5

4

5

3

4

3

ns

d(CLKL-IAQL)

t

– 1

d(CLKL-IAQH)

d(A)IAQ

t

0

d(CLKL-IACKL)

t

d(CLKL-IACKH)

d(A)IACK

h(A)IAQ

t

– 3

h(A)IACK

w(IAQL)

2H–3

Pulse duration, IACK low

w(IACKL)

CLKOUT

A[15:0]

IAQ

t

d(CLKL-IAQH)

d(CLKL-IAQL)

t

h(A)IAQ

t

d(A)IAQ

t

w(IAQL)

t

d(CLKL-IACKH)

d(CLKL-IACKL)

t

h(A)IACK

t

d(A)IACK

t

w(IACKL)

IACK

MSTRB

Figure 18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timing

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing

(continued)

switching characteristics over recommended operating conditions for external flag (XF) and TOUT

[H = 0.5 t

] (see Figure 19 and Figure 20)

c(CO)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

0

MAX

MIN

0

MAX

Delay time, XF high after CLKOUT low

Delay time, XF low after CLKOUT low

5

4

t

ns

d(XF)

0

t

Delay time, TOUT high after CLKOUT low

Delay time, TOUT low after CLKOUT low

Pulse duration, TOUT

0

–1

5

– 1

4

ns

d(TOUTH)

d(TOUTL)

w(TOUT)

2H–3

CLKOUT

t

d(XF)

XF

Figure 19. External Flag (XF) Timing

CLKOUT

TOUT

t

d(TOUTL)

d(TOUTH)

t

w(TOUT)

Figure 20. TOUT Timing

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial port receive timing

timing requirements over recommended operating conditions for serial port receive [H = 0.5 t

(see Figure 21)

]

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

t

Cycle time, serial port clock

6H

†

6

ns

c(SCK)

f(SCK)

r(SCK)

w(SCK)

su(FSR)

h(FSR)

h(DR)

Fall time, serial port clock

Rise time, serial port clock

Pulse duration, serial port clock low/high

Setup time, FSR before CLKR falling edge

Hold time, FSR after CLKR falling edge

Hold time, DR after CLKR falling edge

Setup time, DR before CLKR falling edge

3H

4

6

su(DR)

†

The serial port design is fully static and, therefore, can operate with t

of 0 Hz but tested at a much higher frequency to minimize test time.

approaching ∞. It is characterized approaching an input frequency

c(SCK)

t

c(SCK)

t

f(SCK)

t

w(SCK)

CLKR

FSR

t

h(FSR)

t

r(SCK)

t

w(SCK)

t

su(FSR)

t

su(DR)

t

h(DR)

DR

BIT

1

2

7/15

8/16

Figure 21. Serial Port Receive Timing

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial port transmit timing

switching characteristics over recommended operating conditions for serial port transmit with

external clocks and frames [H = 0.5t ] (see Figure 22)

c(CO)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

MAX

t

Delay time, DX valid after CLKX rising

25

ns

d(DX)

h(DX)

dis(DX)

Hold time, DX valid after CLKX rising

Disable time, DX after CLKX rising

– 5

40

timing requirements over recommended operating conditions for serial port transmit with external

clocks and frames [H = 0.5t ] (see Figure 22)

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

6H

6

MAX

†

t

Cycle time, serial port clock

ns

c(SCK)

h(FSX)

h(FSX)H

d(FSX)

f(SCK)

r(SCK)

w(SCK)

Hold time, FSX after CLKX falling edge (see Note 1)

Hold time, FSX after CLKX rising edge (see Note 1)

Delay time, FSX after CLKX rising edge

Fall time, serial port clock

‡

2H–3

6

Rise time, serial port clock

Pulse duration, serial port clock low/high

3H

†

The serial port design is fully static and, therefore, can operate with t

of 0 Hz but tested at a much higher frequency to minimize test time.

If the FSX pulse does not meet this specification, the first bit of serial data is driven on DX until the falling edge of FSX. After the falling edge of

FSX, data is shifted out on DX pin. The transmit buffer-empty interrupt is generated when the t specification is met.

approaching ∞. It is characterized approaching an input frequency

c(SCK)

‡

t

h(FSX) and h(FSX)H

NOTE 1: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on

the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX

is independent of the source of CLKX.

t

c(SCK)

t

f(SCK)

w(SCK)

CLKX

t

h(FSX)H

t

d(FSX)

t

r(SCK)

t

w(SCK)

t

h(FSX)

FSX

t

d(DX)

1

t

dis(DX)

8/16

t

h(DX)

DX BIT

2

7/15

Figure 22. Serial Port Transmit Timing With External Clocks and Frames

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial port transmit timing (continued)

switching characteristics over recommended operating conditions for serial port transmit with

internal clocks and frames [H = 0.5t

] (see Figure 23)

c(CO)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

TYP

MAX

t

Cycle time, serial port clock

Delay time, CLKX rising to FSX

Delay time, CLKX rising to DX

Disable time, CLKX rising to DX

8H

ns

c(SCK)

d(FSX)

d(DX)

7

20

dis(DX)

h(DX)

Hold time, DX valid after CLKX rising edge

Fall time, serial port clock

–2

3

f(SCK)

r(SCK)

w(SCK)

Rise time, serial port clock

Pulse duration, serial port clock low/high

4H–4

t

c(SCK)

t

f(SCK)

w(SCK)

CLKX

t

d(FSX)

t

w(SCK)

t

r(SCK)

t

d(FSX)

t

d(DX)

FSX

DX

t

dis(DX)

t

h(DX)

1

2

7/15

8/16

Figure 23. Serial Port Transmit Timing With Internal Clocks and Frames

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

buffered serial port receive timing

timing requirements over recommended operating conditions (see Figure 24)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

†

t

Cycle time, serial port clock

20

ns

c(SCK)

Fall time, serial port clock

4

f(SCK)

Rise time, serial port clock

r(SCK)

Pulse duration, serial port clock low/high

Setup time, BFSR before BCLKR falling edge (see Note 2)

Hold time, BFSR after BCLKR falling edge (see Note 2)

Setup time, BDR before BCLKR falling edge

Hold time, BDR after BCLKR falling edge

6

2

7

0

7

w(SCK)

su(BFSR)

h(BFSR)

su(BDR)

h(BDR)

‡

t

c(SCK)–2

†

The serial port design is fully static and therefore can operate with t

of 0 Hz but tested at a much higher frequency to minimize test time.

First bit is read when BFSR is sampled low by BCLKR clock.

approaching infinity. It is characterized approaching an input frequency

c(SCK)

‡

NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.

t

c(SCK)

t

w(SCK)

t

f(SCK)

BCLKR

BFSR

BDR

t

r(SCK)

t

w(SCK)

h(BFSR)

t

su(BFSR)

t

su(BDR)

t

h(BDR)

1

2

8/10/12/16

Figure 24. Buffered Serial Port Receive Timing

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

buffered serial port transmit timing of external frames

switching characteristics over recommended operating conditions (see Figure 25)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN

MAX

t

Delay time, BDX valid after BCLKX rising

18

6

ns

d(BDX)

Disable time, BDX after BCLKX rising

4

dis(BDX)

Disable time, PCM mode, BDX after BCLKX rising

Enable time, PCM mode, BDX after BCLKX rising

Hold time, BDX valid after BCLKX rising

6

dis(BDX)pcm

en(BDX)pcm

h(BDX)

8

2

timing requirements over recommended operating conditions (see Figure 25)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

†

t

Cycle time, serial port clock

20

ns

c(SCK)

Fall time, serial port clock

4

f(SCK)

Rise time, serial port clock

r(SCK)

Pulse duration, serial port clock low/high

Hold time, BFSX after CLKX falling edge (see Notes 3 and 4)

Setup time, FSX before CLKX falling edge (see Notes 3 and 4)

6

w(SCK)

h(BFSX)

su(BFSX)

‡

t

c(SCK)–6

†

The serial port design is fully static and therefore can operate with t

c(SCK)

approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡

If BFSX does not meet this specification, the first bit of the serial data is driven on BDX until BFSX goes low (sampled on falling edge of BCLKX).

After falling edge of the BFSX, data will be shifted out on the BDX pin.

NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

buffered serial port transmit timing of external frames (continued)

t

c(SCK)

t

w(SCK)

t

f(SCK)

BCLKX

BFSX

BDX

t

r(SCK)

t

h(BFSX)

t

w(SCK)

t

su(BFSX)

t

dis(BDX)

t

h(BDX)

t

d(BDX)

1

2

8/10/12/16

Figure 25. Buffered Serial Port Transmit Timing of External Clocks and External Frames

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P RO C ES S O R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

buffered serial port transmit timing of internal frame and internal clock

switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 26)

’549-80

’549-100

’549-120

PARAMETER

UNIT

MIN MAX

t

Cycle time, serial port clock, internal clock

20

62H

7

ns

c(SCK)

Delay time, BFSX after BCLKX rising edge

(see Notes 3 and 4)

d(BFSX)

t

Delay time, BDX valid after BCLKX rising edge

Disable time, BDX after BCLKX rising edge

Disable time, PCM mode, BDX after BCLKX rising edge

Enable time, PCM mode, BDX after BCLKX rising edge

Hold time, BDX valid after BCLKX rising edge

Fall time, serial port clock

7

5

ns

d(BDX)

0

dis(BDX)

dis(BDX)pcm

en(BDX)pcm

h(BDX)

7

0

3.5

f(SCK)

Rise time, serial port clock

r(SCK)

Pulse duration, serial port clock low/high

6

w(SCK)

NOTES: 3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined

depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.

4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.

t

c(SCK)

t

w(SCK)

t

f(SCK)

BCLKX

BFSX

BDX

t

r(SCK)

t

d(BFSX)

t

w(SCK)

t

d(BFSX)

t

dis(BDX)

t

h(BDX)

t

d(BDX)

1

2

8/10/12/16

Figure 26. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames

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PRO CE SSO R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial-port receive timing in TDM mode

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5t ] (see Figure 27)

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

†

t

Cycle time, serial-port clock

16H

ns

c(SCK)

Fall time, serial-port clock

6

f(SCK)

Rise time, serial-port clock

r(SCK)

Pulse duration, serial-port clock low/high

Setup time, TDAT/TADD before TCLK rising edge

Hold time, TDAT/TADD after TCLK rising edge

Setup time, TFRM before TCLK rising edge‡

Hold time, TFRM after TCLK rising edge‡

8H

10

1

w(SCK)

su(TD-TCH)

h(TCH-TD)

su(TF-TCH)

h(TCH-TF)

10

†

The serial-port design is fully static and, therefore, can operate with t

c(SCK)

approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡

TFRM timing and waveforms shown in Figure 27 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is

illustrated in the transmit timing diagram in Figure 28.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial-port receive timing in TDM mode (continued)

t

w(SCK)

t

f(SCK)

w(SCK)

TCLK

‡

t

su(TD-TCL)

t

c(SCK)

t

†

r(SCK)

t

su(TD-TCH)

‡

t

h(TCL-TD)

t

h(TCH-TD)

TDAT

B0

B14

A1

B13

B12

A3

B11

A4

B2

B1

B0

B15

A0

t

su(TF-TCH)

A7

A2

TADD

TFRM

t

h(TCH-TF)

†

‡

All devices except ’542/’543

’542/’543 only

Figure 27. Serial-Port Receive Timing in TDM Mode

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial-port transmit timing in TDM mode

switching characteristics over recommended operating conditions [H = 0.5t

] (see Figure 28)

c(CO)

’549-80

549-100

’549-120

PARAMETER

UNIT

MIN

MAX

t

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK external

Hold time, TDAT/TADD valid after TCLK rising edge, TCLK internal

1

ns

h(TCH-TDV)

†

Delay time, TFRM valid after TCLK rising edge, TCLK ext

H – 3

3H+22

3H+12

25

t

ns

d(TCH-TFV)

d(TC-TDV)

†

Delay time, TFRM valid after TCLK rising edge, TCLK int

Delay time, TCLK to valid TDAT/TADD, TCLK ext

Delay time, TCLK to valid TDAT/TADD, TCLK int

t

18

†

TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is

illustrated in the receive timing diagram in Figure 27.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

serial-port transmit timing in TDM mode (continued)

timing requirements over recommended ranges of supply voltage and operating free-air

temperature [H = 0.5t ] (see Figure 28)

c(CO)

’549–80

’549-100

’549-120

UNIT

MIN

MAX

†

‡

t

Cycle time, serial-port clock

Fall time, serial-port clock

16H

ns

c(SCK)

f(SCK)

r(SCK)

w(SCK)

6

Rise time, serial-port clock

†

8H

Pulse duration, serial-port clock low/high

†

‡

When SCK is generated internally, this value is typical.

The serial-port design is fully static and, therefore, can operate with t

approaching 1. It is characterized approaching an input frequency

c(SCK)

of 0 Hz but tested as a much higher frequency to minimize test time.

t

w(SCK)

t

w(SCK)

t

f(SCK)

TCLK

t

c(SCK)

t

d(TC-TDV)

r(SCK)

B1

B15

TDAT

TADD

B0

h(TCH-TDV)

B14

B13

A2

B12

A3

B8 B7

B2

B0

t

h(TCH-TDV)

t

d(TC-TDV)

A1

A7

t

d(TCH-TFV)

A0

t

d(TCH-TFV)

TFRM

Figure 28. Serial-Port Transmit Timing in TDM Mode

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing

switching characteristics over recommended operating conditions [H = 0.5t

(see Notes 5 and 6) (see Figure 29 through Figure 32) (continued)

]

c(CO)

’549-80

’549-100

PARAMETER

’549-120

UNIT

MIN

MAX

t

Delay time, DS low to HD driven

5

12

ns

d(DSL-HDV)

d(HEL-HDV1)

Case 1: Shared-access mode if

< 7H

7H+20–t

w(DSH)

20

t

w(DSH)

Case 2: Shared-access mode if

> 7H

t

w(DSH)

Case 3: Host-only mode if

< 20 ns

Delay time, HDS falling to HD valid for first byte

of a non-subsequent read: → max 20 ns

ns

†‡

40–t

w(DSH)

20

t

w(DSH)

Case 4: Host-only mode if

> 20 ns

t

w(DSH)

‡

t

Delay time, DS low to HD valid, second byte

Delay time, DS high to HRDY high

5

20

10H+10

ns

d(DSL-HDV2)

d(DSH-HYH)

su(HDV-HYH)

h(DSH-HDV)R

d(COH-HYH)

d(DSH-HYL)

d(COH-HTX)

Setup time, HD valid before HRDY rising edge

Hold time, HD valid after DS rising edge, read

Delay time, CLKOUT rising edge to HRDY high

Delay time, HDS or HCS high to HRDY low

3H–10

0

12

10

12

15

Delay time, CLKOUT rising edge to HINT change

†

Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access

mode. HRDY does not go low for these accesses.

Shared-access mode timings will be met automatically if HRDY is used.

‡

NOTES: 5. SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be

specified here.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing (continued)

timing requirements over recommended operating conditions [H = 0.5t

(see Figure 29 through Figure 32)

] (see Note 7)

c(CO)

’549-80

’549-100

’549-120

UNIT

MIN

10

5

MAX

MIN

10

5

MAX

t

Setup time, HAD/HBIL valid before DS or HAS falling edge

Hold time, HAD/HBIL valid after DS or HAS falling edge

Setup time, HAS low before DS falling edge

Pulse duration, DS low

ns

su(HBV-DSL)

h(DSL-HBV)

su(HSL-DSL)

w(DSL)

12

30

10

12

30

10

Pulse duration, DS high

w(DSH)

Case 1: HOM access timings

(see Access Timing Without HRDY)

50

40

Cycle time, DS rising

edge to next DS rising

edge

t

ns

Case 2a: SAM accesses and HOM active writes

to DSPINT or HINT

(see Access Timings With HRDY)

c(DSH-DSH)

†

10H

t

Setup time, HD valid before DS rising edge

Delay time, DS high to next HAS low

12

10H

3

12

10H

3

ns

su(HDV-DSH)

‡

d(DSH-HSL)

Hold time, HD valid after DS rising edge, write

h(DSH – HDV)W

†

A host not using HRDY should meet this timing requirement all the time unless a software handshake is used to change the access rate according

to the HPI mode.

Must only be met if HAS is going low when not accessing the HPI (as would be the case where multiple devices are being driven by one host).

‡

NOTE 7: SAM = shared-access mode, HOM = host-only mode

HAD stands for HCNTRL0, HCNTRL1, and HR/W.

HDS refers to either HDS1 or HDS2.

DS refers to the logical OR of HCS and HDS.

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

Valid

HAD

t

h(DSL-HBV)

t

h(DSL-HBV)

t

su(HBV-DSL)

t

su(HBV-DSL)

HBIL

t

w(DSH)

t

w(DSL)

t

w(DSL)

HCS

HDS

t

c(DSH-DSH)

t

d(DSL-HDV2)

Valid

t

d(HEL-HDV1)

t

h(DSH-HDV)

t

h(DSH-HDV)R

t

d(DSL-HDV)

HD

READ

Valid

t

su(HDV-DSH)

h(DSH-HDV)

su(HDV-DSH)

t

h(DSH-HDV)W

HD

WRITE

Valid

Figure 29. Read/Write Access Timings Without HRDY or HAS

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

HAS

t

su(HBV-DSL)

t

d(DSH-HSL)

t

h(DSL-HBV)

t

su(HSL-DSL)

Valid

HAD

†

t

h(DSL-HBV)

†

t

su(HBV-DSL)

HBIL

t

c(DSH-DSH)

t

w(DSH)

t

w(DSL)

HCS

HDS

t

d(HEL-HDV1)

t

d(DSL-HDV2)

Valid

t

h(DSH-HDV)R

t

h(DSH-HDV)R

t

d(DSL-HDV)

HD

READ

Valid

t

su(HDV-DSH)

t

h(DSH-HDV)W

t

h(DSH-HDV)W

HD

WRITE

Valid

†

When HAS is tied to V

DD

Figure 30. Read/Write Access Timings Using HAS Without HRDY

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R

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing (continued)

FIRST BYTE

SECOND BYTE

HAS

t

su(HSL-DSL)

t

d(DSH-HSL)

t

su(HBV-DSL)

t

h(DSL-HBV)

HAD

†

t

h(DSL-HBV)

†

t

su(HBV-DSL)

HBIL

t

c(DSH-DSH)

t

w(DSH)

t

w(DSL)

HCS

HDS

t

su(HDV-HYH)

t

d(DSH-HYH)

HRDY

t

d(DSH-HYL)

t

d(DSL-HDV2)

Valid

t

d(HEL-HDV1)

t

h(DSH-HDV)R

t

h(DSH-HDV)R

t

d(DSL-HDV)

HD

READ

Valid

t

su(HDV-DSH)

t

su(HDV-DSH)

t

h(DSH-HDV)W

t

h(DSH-HDV)W

HD

WRITE

Valid

t

d(COH-HYH)

CLKOUT

HINT

t

d(COH-HTX)

†

When HAS is tied to V

DD

Figure 31. Read/Write Access Timing With HRDY

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

host port interface timing (continued)

HCS

t

d(DSH-HYL)

HRDY

HDS

t

d(DSH-HYH)

Figure 32. HRDY Signal When HCS is Always Low

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

MECHANICAL DATA

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

0,17

M

0,08

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–ā7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

Thermal Resistance Characteristics

PARAMETER

°C/W

R

56

ΘJA

ΘJC

R

5

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

MECHANICAL DATA

TMS320VC5409 144-Pin Plastic Ball Grid Array Package (BGA)

GGU (S-PBGA-N144)

PLASTIC BALL GRID ARRAY PACKAGE

12,10

11,90

SQ

13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

0,80

K

L

M

N

0,80

0,95

0,85

1,40 MAX

0,10

0,12

0,08

0,55

0,45

0,35

M

0,08

4073221/A 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

Thermal Resistance Characteristics

PARAMETER

°C/W

R

38

ΘJA

ΘJC

R

5

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TMS320VC549PGE-100
厂家：	TEXAS INSTRUMENTS
描述：	IC-SMD-DSP PROCESSOR IC- SMD- DSP处理器\n 微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总60页 (文件大小：785K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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