TMS320VC5502GBE200 [TI]
定点数字信号处理器 | GBE | 201 | -40 to 85;
| 型号： | TMS320VC5502GBE200 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 定点数字信号处理器 | GBE | 201 | -40 to 85 外围集成电路 数字信号处理器 |
| 文件： | 总189页 (文件大小：1650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5502
Fixed-Point Digital Signal Processor
Data Manual
Literature Number: SPRS166H
April 2001–Revised November 2004
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Revision History
This data sheet revision history highlights the technical changes made to the SPRS166G device-specific
data sheet to make it an SPRS166H revision.
Scope: Deleted Section 7.1 (Ball Grid Array Mechanical Data) and Section 7.2 (Low-Profile Quad
Flatpack Mechanical Data). Mechanical drawings of the 201-terminal GZZ, 201-terminal ZZZ, and 176-pin
PGF packages will be appended to this document via an automated process.
Added 201-terminal ZZZ package information/data, added Section 4.1 [Notices Concerning JTAG (IEEE
1149.1) Boundary Scan Test Capability], added Section 6.2 (Packaging Information), etc.
ADDITIONS/CHANGES/DELETIONS
Global:
•
•
added 201-terminal ZZZ package information/data
updated title of SPRU146 to "TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference
Guide"
•
updated title of SPRU592 to "TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP)
Reference Guide"
•
moved "Package Thermal Resistance Characteristics" section to Chapter 6, Mechanical Data
Section 1.1, Features:
added 201-terminal ZZZ package to "Packages" feature
Section 2.2.1:
•
•
•
changed title from "Ball Grid Array (GZZ)" to "Ball Grid Array (GZZ and ZZZ)"
updated "The TMS320VC5502 is offered in ..." paragraph
Figure 2-1:
changed title from "201-Terminal GZZ Ball Grid Array (Bottom View)" to "201-Terminal GZZ and ZZZ Ball Grid Array (Bottom
View)"
Table 2-1:
changed title from "201-Terminal GZZ Ball Grid Array Thermal Ball Locations" to "201-Terminal GZZ and ZZZ Ball Grid Array
Thermal Ball Locations"
Table 2-2:
changed title from "201-Terminal GZZ Ball Grid Array Ball Assignments" to "201-Terminal GZZ and ZZZ Ball Grid Array Ball
Assignments"
Table 2-4, Signal Descriptions:
updated FUNCTION of HCS, HDS1, HDS2, and HPIENA
Figure 3-2, TMS320VC5502 Memory Map:
•
•
•
•
•
•
added "Byte Address" above addresses
added footnote about CE space size
Updated Section 3.8, Host-Port Interface (HPI)
Section 3.10.6, Reset Sequence:
•
updated "After all internal delay cycles have expired, ..." bulleted item
Table 3-57, Peripheral Bus Controller Configuration Registers:
added Time-Out Control Register (TOCR) at 0x9000
Chapter 4, Support:
•
•
•
•
added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
added Section 4.1.1, Initialization Requirements for Boundary Scan Test
added Section 4.1.2, Boundary Scan Description Language (BSDL) Model
Section 4.2, Documentation Support:
•
updated title of SPRU146 to "TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference
Guide"
•
updated title of SPRU592 to "TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP)
Reference Guide"
2
Revision History
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
ADDITIONS/CHANGES/DELETIONS (continued)
Table 5-43, HPI Read and Write Timing Requirements:
•
•
H13 [tw(DSL)]: deleted "K = 1", "K = 2", and "K = 4" column
H14 [tw(DSH)]:
–
–
deleted "K = 1", "K = 2", and "K = 4" column
changed MIN value from 3P, P, and 1.75P to 2P (ns)
•
•
deleted "K = divider ratio ..." footnote
added "A host must not initiate transfer requests ..." footnote
Table 5-44, HPI Read and Write Switching Characteristics:
added "A host must not initiate transfer requests ..." footnote
Chapter 6, Mechanical Data:
•
•
•
deleted 201-terminal GZZ package drawing and 176-pin PGF package drawing
Mechanical drawings of the 201-terminal GZZ, 201-terminal ZZZ, and 176-pin PGF packages will be appended to this
document via an automated process.
Table 6-1, Thermal Resistance Characteristics (Ambient):
•
•
changed "GZZ" to "GZZ, ZZZ"
updated "Adding thermal vias will significantly improve ..." footnote to include ZZZ package
Table 6-2, Thermal Resistance Characteristics (Case):
changed "GZZ" to "GZZ, ZZZ"
Added Section 6.2, Packaging Information
•
Revision History
3
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Contents
1
2
TMS320VC5502 ................................................................................................................. 15
Features ..................................................................................................................... 15
Introduction....................................................................................................................... 16
1.1
2.1
Description .................................................................................................................. 16
Pin Assignments............................................................................................................ 17
2.2
2.2.1
2.2.2
2.2.3
Ball Grid Array (GZZ and ZZZ) ................................................................................ 17
Low-Profile Quad Flatpack (PGF)............................................................................. 19
Signal Descriptions.............................................................................................. 21
3
Functional Overview ........................................................................................................... 33
3.1
Memory ...................................................................................................................... 34
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
On-Chip ROM ................................................................................................... 34
On-Chip Dual-Access RAM (DARAM)........................................................................ 35
Instruction Cache ................................................................................................ 35
Memory Map ..................................................................................................... 36
Boot Configuration............................................................................................... 37
3.2
3.3
Peripherals .................................................................................................................. 37
Configurable External Ports and Signals................................................................................ 38
3.3.1
3.3.2
3.3.3
3.3.4
Parallel Port Mux ................................................................................................ 38
Host Port Mux.................................................................................................... 39
Serial Port 2 Mux ................................................................................................ 40
External Bus Selection Register (XBSR)..................................................................... 41
3.4
3.5
Configuration Examples ................................................................................................... 43
Timers........................................................................................................................ 44
3.5.1
3.5.2
3.5.3
Timer Interrupts.................................................................................................. 45
Timer Pins ........................................................................................................ 46
Timer Signal Selection Register (TSSR) ..................................................................... 47
3.6
3.7
3.8
3.9
Universal Asynchronous Receiver/Transmitter (UART)............................................................... 48
Inter-Integrated Circuit (I2C) Module..................................................................................... 50
Host-Port Interface (HPI) .................................................................................................. 51
Direct Memory Access (DMA) Controller................................................................................ 52
3.9.1
DMA Channel 0 Control Register (DMA_CCR0) ........................................................... 52
3.10 System Clock Generator .................................................................................................. 54
3.10.1 Input Clock Source .............................................................................................. 55
3.10.2 Clock Groups..................................................................................................... 57
3.10.3 EMIF Input Clock Selection .................................................................................... 58
3.10.4 Changing the Clock Group Frequencies ..................................................................... 58
3.10.5 PLL Control Registers .......................................................................................... 60
3.10.6 Reset Sequence ................................................................................................. 72
3.11 Idle Control.................................................................................................................. 72
3.11.1 Clock Domains................................................................................................... 73
3.11.2 IDLE Procedures ................................................................................................ 73
3.11.3 Module Behavior at Entering IDLE State..................................................................... 75
3.11.4 Wake-Up Procedure ............................................................................................ 76
3.11.5 Auto-Wakeup/Idle Function for McBSP and DMA........................................................... 78
3.11.6 Clock State of Multiplexed Modules........................................................................... 78
4
Contents
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
3.11.7 IDLE Control and Status Registers............................................................................ 79
3.12 General-Purpose I/O (GPIO) ............................................................................................. 87
3.12.1 General-Purpose I/O Port ...................................................................................... 87
3.12.2 Parallel Port General-Purpose I/O (PGPIO) ................................................................. 89
3.13 External Bus Control Register ............................................................................................ 95
3.13.1 External Bus Control Register (XBCR) ....................................................................... 97
3.14 Internal Ports and System Registers .................................................................................... 98
3.14.1 XPORT Interface ................................................................................................ 98
3.14.2 DPORT Interface............................................................................................... 100
3.14.3 IPORT Interface ................................................................................................ 102
3.14.4 System Configuration Register (CONFIG).................................................................. 103
3.14.5 Time-Out Control Register (TOCR).......................................................................... 104
3.15 CPU Memory-Mapped Registers ....................................................................................... 105
3.16 Peripheral Registers...................................................................................................... 107
3.17 Interrupts................................................................................................................... 120
3.17.1 IFR and IER Registers ....................................................................................... 121
3.17.2 Interrupt Timing ................................................................................................ 122
3.17.3 Interrupt Acknowledge......................................................................................... 122
3.18 Notice Concerning TCK.................................................................................................. 123
Support ........................................................................................................................... 125
4
5
4.1
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability ....................................... 125
4.1.1
Initialization Requirements for Boundary Scan Test ...................................................... 125
Boundary Scan Description Language (BSDL) Model .................................................... 125
4.1.2
4.2
4.3
Documentation Support.................................................................................................. 125
Device and Development-Support Tool Nomenclature .............................................................. 126
Specifications .................................................................................................................. 127
5.1
Electrical Specifications.................................................................................................. 127
5.2
Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 127
5.3
5.4
Recommended Operating Conditions.................................................................................. 127
Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted) ............................................................................................... 128
5.5
5.6
Timing Parameter Symbology........................................................................................... 129
Clock Options ............................................................................................................. 130
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Internal System Oscillator With External Crystal........................................................... 130
Layout Considerations......................................................................................... 131
Clock Generation in Bypass Mode (APLL Disabled)...................................................... 132
Clock Generation in Lock Mode (APLL Synthesis Enabled) ............................................. 133
EMIF Clock Options ........................................................................................... 134
5.7
Memory Timings .......................................................................................................... 136
5.7.1
5.7.2
5.7.3
Asynchronous Memory Timings.............................................................................. 136
Programmable Synchronous Interface Timings ........................................................... 139
Synchronous DRAM Timings................................................................................. 142
5.8
5.9
HOLD/HOLDA Timings .................................................................................................. 147
Reset Timings ............................................................................................................. 148
5.10 External Interrupt and Interrupt Acknowledge (IACK) Timings ..................................................... 150
5.11 XF Timings................................................................................................................. 151
5.12 General-Purpose Input/Output (GPIOx) Timings ..................................................................... 152
Contents
5
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings.......................................................... 153
5.14 TIM0/TIM1/WDTOUT Timings .......................................................................................... 154
5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings ................................................................... 154
5.14.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings...................................................... 155
5.14.3 TIM0/TIM1/WDTOUT Interrupt Timings..................................................................... 157
5.15 Multichannel Buffered Serial Port (McBSP) Timings................................................................. 158
5.15.1 McBSP Transmit and Receive Timings ..................................................................... 158
5.15.2 McBSP General-Purpose I/O Timings ...................................................................... 161
5.15.3 McBSP as SPI Master or Slave Timings.................................................................... 162
5.16 Host-Port Interface Timings ............................................................................................. 169
5.16.1 HPI Read and Write Timings ................................................................................. 169
5.16.2 HPI General-Purpose I/O Timings ........................................................................... 176
5.16.3 HPI.HAS Interrupt Timings.................................................................................... 178
5.17 Inter-Integrated Circuit (I2C) Timings................................................................................... 179
5.18 Universal Asynchronous Receiver/Transmitter (UART) Timings ................................................... 181
Mechanical Data ............................................................................................................... 182
6
6.1
Package Thermal Resistance Characteristics ........................................................................ 182
Packaging Information ................................................................................................... 183
6.2
6
Contents
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
List of Figures
2-1
2-2
3-1
3-2
3-3
3-4
201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View) ................................................................. 17
176-Pin PGF Low-Profile Quad Flatpack (Top View) ........................................................................ 19
TMS320VC5502 Functional Block Diagram ................................................................................... 33
TMS320VC5502 Memory Map .................................................................................................. 36
External Bus Selection Register Layout (0x6C00)............................................................................ 41
Configuration Example A
(GPIO6 = 1 and GPIO7 = 1 at Reset).......................................................................................... 43
3-5
Configuration Example B
(GPIO6 = 0 and GPIO7 = 0 at Reset).......................................................................................... 44
3-6
Timer Interrupts.................................................................................................................... 45
Timer Pins.......................................................................................................................... 46
Timer Signal Selection Register Layout (0x8000) ............................................................................ 47
UART Functional Block Diagram................................................................................................ 49
I2C Module Block Diagram....................................................................................................... 50
DMA Channel 0 Control Register Layout (0x0C01) .......................................................................... 52
System Clock Generator ......................................................................................................... 54
Internal System Oscillator With External Crystal.............................................................................. 55
Clock Generator Registers....................................................................................................... 59
PLL Control/Status Register Layout (0x1C80) ................................................................................ 61
PLL Multiplier Control Register Layout (0x1C88) ............................................................................. 62
PLL Divider 0 Register Layout (0x1C8A) ...................................................................................... 63
PLL Divider 1 Register Layout (0x1C8C) ...................................................................................... 65
PLL Divider 2 Register Layout (0x1C8E) ...................................................................................... 66
PLL Divider 3 Register Layout (0x1C90)....................................................................................... 67
Oscillator Divider1 Register Layout (0x1C92) ................................................................................. 67
Oscillator Wakeup Control Register Layout (0x1C98) ....................................................................... 69
CLKOUT3 Select Register Layout (0x1C82) .................................................................................. 70
CLKOUT Selection Register Layout (0x8400)................................................................................. 71
Clock Mode Control Register Layout (0x8C00) ............................................................................... 71
IDLE Configuration Register Layout (0x0001)................................................................................. 79
IDLE Status Register Layout (0x0002)......................................................................................... 81
Peripheral IDLE Control Register Layout (0x9400)........................................................................... 82
Peripheral IDLE Status Register Layout (0x9401)............................................................................ 85
Master IDLE Control Register Layout (0x9402)............................................................................... 86
Master IDLE Status Register Layout (0x9403)................................................................................ 86
GPIO Direction Register Layout (0x3400) ..................................................................................... 87
GPIO Data Register Layout (0x3401) .......................................................................................... 88
Parallel GPIO Enable Register 0 Layout (0x4400) ........................................................................... 90
Parallel GPIO Direction Register 0 Layout (0x4401) ......................................................................... 90
Parallel GPIO Data Register 0 Layout (0x4402) .............................................................................. 91
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
3-36
List of Figures
7
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
5-1
Parallel GPIO Enable Register 1 Layout (0x4403) ........................................................................... 92
Parallel GPIO Direction Register 1 Layout (0x4404) ......................................................................... 93
Parallel GPIO Data Register 1 Layout (0x4405) .............................................................................. 93
Parallel GPIO Enable Register 2 Layout (0x4406) ........................................................................... 94
Parallel GPIO Direction Register 2 Layout (0x4407) ......................................................................... 94
Parallel GPIO Data Register 2 Layout (0x4408) .............................................................................. 95
External Bus Control Register Layout (0x8800)............................................................................... 97
XPORT Configuration Register Layout (0x0100) ............................................................................. 99
XPORT Bus Error Register Layout (0x0102) ................................................................................ 100
DPORT Configuration Register Layout (0x0200)............................................................................ 101
DPORT Bus Error Register Layout (0x0202) ................................................................................ 101
IPORT Bus Error Register Layout (0x0302) ................................................................................. 102
System Configuration Register Layout (0x07FD) ........................................................................... 103
Time-Out Control Register Layout (0x9000) ................................................................................. 104
IFR0, IER0, DBIFR0, and DBIER0 Registers Layout....................................................................... 122
IFR1, IER1, DBIFR1, and DBIER1 Registers Layout....................................................................... 122
Bad TCK Transition ............................................................................................................. 123
Good TCK Transition............................................................................................................ 124
Sample Noise Filtering Circuitry ............................................................................................... 124
3.3-V Test Load Circuit ......................................................................................................... 129
Internal System Oscillator With External Crystal ............................................................................ 130
Bypass Mode Clock Timings................................................................................................... 132
External Multiply-by-N Clock Timings......................................................................................... 134
ECLKIN Timings for EMIF...................................................................................................... 135
ECLKOUT1 Timings for EMIF Module........................................................................................ 135
ECLKOUT2 Timings for EMIF Module........................................................................................ 135
Asynchronous Memory Read Timings ........................................................................................ 137
Asynchronous Memory Write Timings ........................................................................................ 138
Programmable Synchronous Interface Read Timings (With Read Latency = 2)........................................ 140
Programmable Synchronous Interface Write Timings (With Write Latency = 0) ........................................ 141
Programmable Synchronous Interface Write Timings (With Write Latency = 1) ........................................ 141
SDRAM Read Command (CAS Latency 3) .................................................................................. 143
SDRAM Write Command ....................................................................................................... 143
SDRAM ACTV Command ...................................................................................................... 144
SDRAM DCAB Command...................................................................................................... 144
SDRAM DEAC Command...................................................................................................... 145
SDRAM REFR Command ...................................................................................................... 145
SDRAM MRS Command ....................................................................................................... 146
SDRAM Self-Refresh Timings ................................................................................................. 146
EMIF.HOLD/HOLDA Timings .................................................................................................. 147
Reset Timings.................................................................................................................... 149
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
8
List of Figures
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
External Interrupt Timings ...................................................................................................... 150
External Interrupt Acknowledge Timings ..................................................................................... 150
XF Timings ....................................................................................................................... 151
General-Purpose Input/Output (GPIOx) Signal Timings.................................................................... 152
Parallel General-Purpose Input/Output (PGPIOx) Signal Timings ........................................................ 153
TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins ................................................... 154
TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins ................................................. 154
TIM0/TIM1/WDTOUT General-Purpose I/O Timings ....................................................................... 156
TIM0/TIM1/WDTOUT Interrupt Timings ...................................................................................... 157
McBSP Receive Timings ....................................................................................................... 160
McBSP Transmit Timings....................................................................................................... 160
McBSP General-Purpose I/O Timings ........................................................................................ 161
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 .................................................. 163
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 .................................................. 165
McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 .................................................. 166
McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 .................................................. 168
Non-Multiplexed Read/Write Timings ......................................................................................... 171
Multiplexed Read Timings Using HPI.HAS................................................................................... 172
Multiplexed Read Timings With HPI.HAS Held High ....................................................................... 173
Multiplexed Write Timings Using HPI.HAS................................................................................... 174
Multiplexed Write Timings With HPI.HAS Held High........................................................................ 175
HINT Timings..................................................................................................................... 175
HPI General-Purpose I/O Timings............................................................................................. 177
HPI.HAS Interrupt Timings ..................................................................................................... 178
I2C Receive Timings............................................................................................................. 179
I2C Transmit Timings............................................................................................................ 180
UART Timings.................................................................................................................... 181
List of Figures
9
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
List of Tables
2-1
201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations....................................................... 17
2-2
201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments ............................................................ 18
176-Pin PGF Low-Profile Quad Flatpack Pin Assignments ................................................................. 20
Signal Descriptions ............................................................................................................... 21
On-Chip ROM Layout............................................................................................................. 34
DARAM Blocks .................................................................................................................... 35
Boot Configuration Selection Via the BOOTM[2:0] Pins ..................................................................... 37
TMS320VC5502 Routing of Parallel Port Mux Signals ...................................................................... 39
TMS320VC5502 Routing of Host Port Mux Signals.......................................................................... 40
TMS320VC5502 Routing of Serial Port 2 Mux Signals ...................................................................... 40
External Bus Selection Register Bit Field Description........................................................................ 42
Timer Signal Selection Register Bit Field Description........................................................................ 47
Synchronization Control Function............................................................................................... 53
Recommended Crystal Parameters ............................................................................................ 56
Internal Clocks Frequency Ranges ............................................................................................. 57
PLL Control Registers ............................................................................................................ 60
PLL Control/Status Register Bit Field Description ............................................................................ 61
PLL Multiplier Control Register Bit Field Description ......................................................................... 62
PLL Divider 0 Register Bit Field Description................................................................................... 63
PLL Divider 1 Register Bit Field Description................................................................................... 65
PLL Divider 2 Register Bit Field Description................................................................................... 66
PLL Divider 3 Register Bit Field Description................................................................................... 67
Oscillator Divider1 Register Bit Field Description............................................................................. 68
Oscillator Wakeup Control Register Bit Field Description ................................................................... 69
CLKOUT3 Select Register Bit Field Description .............................................................................. 70
CLKOUT Selection Register Bit Field Description ............................................................................ 71
Clock Mode Control Register Bit Field Description ........................................................................... 71
Number of Reference Clock Cycles Needed Until Program Flow Begins ................................................. 72
Peripheral Behavior at Entering IDLE State ................................................................................... 75
Wake-Up Procedures............................................................................................................. 78
Clock Domain Memory-Mapped Registers .................................................................................... 79
IDLE Configuration Register Bit Field Description ............................................................................ 80
IDLE Status Register Bit Field Description .................................................................................... 81
Peripheral IDLE Control Register Bit Field Description ...................................................................... 83
Peripheral IDLE Status Register Bit Field Description ....................................................................... 85
Master IDLE Control Register Bit Field Description .......................................................................... 86
Master IDLE Status Register Bit Field Description ........................................................................... 87
GPIO Direction Register Bit Field Description................................................................................. 88
GPIO Data Register Bit Field Description...................................................................................... 88
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
10
List of Tables
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3-66
3-67
3-68
3-69
3-70
3-71
3-72
3-73
3-74
3-75
3-76
TMS320VC5502 PGPIO Cross-Reference .................................................................................... 89
Parallel GPIO Enable Register 0 Bit Field Description....................................................................... 90
Parallel GPIO Direction Register 0 Bit Field Description..................................................................... 90
Parallel GPIO Data Register 0 Bit Field Description ......................................................................... 91
Parallel GPIO Enable Register 1 Bit Field Description....................................................................... 92
Parallel GPIO Direction Register 1 Bit Field Description..................................................................... 93
Parallel GPIO Data Register 1 Bit Field Description ......................................................................... 93
Parallel GPIO Enable Register 2 Bit Field Description....................................................................... 94
Parallel GPIO Direction Register 2 Bit Field Description..................................................................... 94
Parallel GPIO Data Register 2 Bit Field Description ......................................................................... 95
Pins With Pullups, Pulldowns, and Bus Holders .............................................................................. 96
External Bus Control Register Bit Field Description .......................................................................... 97
I/O Addresses Under Scope of XPORT........................................................................................ 98
XPORT Configuration Register Bit Field Description......................................................................... 99
XPORT Bus Error Register Bit Field Description............................................................................ 100
DPORT Configuration Register Bit Field Description ....................................................................... 101
DPORT Bus Error Register Bit Field Description............................................................................ 102
IPORT Bus Error Register Bit Field Description............................................................................. 102
System Configuration Register Bit Field Description ....................................................................... 103
Time-Out Control Register Bit Field Description............................................................................. 104
CPU Memory-Mapped Registers .............................................................................................. 105
Peripheral Bus Controller Configuration Registers.......................................................................... 107
External Memory Interface Registers ......................................................................................... 107
DMA Configuration Registers .................................................................................................. 109
Instruction Cache Registers.................................................................................................... 112
Trace FIFO ....................................................................................................................... 112
Timer Signal Selection Register ............................................................................................... 112
Timers............................................................................................................................. 112
Multichannel Serial Port #0..................................................................................................... 114
Multichannel Serial Port #1..................................................................................................... 115
Multichannel Serial Port #2..................................................................................................... 116
HPI................................................................................................................................. 117
GPIO .............................................................................................................................. 117
Device Revision ID .............................................................................................................. 118
I2C ................................................................................................................................. 118
UART.............................................................................................................................. 119
External Bus Selection.......................................................................................................... 119
Clock Mode Register ............................................................................................................ 119
CLKOUT Selector Register..................................................................................................... 120
Clock Controller Registers...................................................................................................... 120
IDLE Control Registers ......................................................................................................... 120
List of Tables
11
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
3-77
5-1
Interrupt Table ................................................................................................................... 120
Recommended Crystal Parameters........................................................................................... 130
CLKIN in Bypass Mode Timing Requirements............................................................................... 132
CLKOUT in Bypass Mode Switching Characteristics ....................................................................... 132
CLKIN in Lock Mode Timing Requirements.................................................................................. 133
CLKOUT in Lock Mode Switching Characteristics .......................................................................... 133
EMIF Timing Requirements for ECLKIN...................................................................................... 134
EMIF Switching Characteristics for ECLKOUT1............................................................................. 134
EMIF Switching Characteristics for ECLKOUT2............................................................................. 135
Asynchronous Memory Cycle Timing Requirements for ECLKIN......................................................... 136
Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1................................................ 136
Programmable Synchronous Interface Timing Requirements ............................................................. 139
Programmable Synchronous Interface Switching Characteristics......................................................... 139
Synchronous DRAM Cycle Timing Requirements........................................................................... 142
Synchronous DRAM Cycle Switching Characteristics ...................................................................... 142
EMIF.HOLD/HOLDA Timing Requirements.................................................................................. 147
EMIF.HOLD/HOLDA Switching Characteristics ............................................................................. 147
Reset Timing Requirements.................................................................................................... 148
Reset Switching Characteristics ............................................................................................... 148
External Interrupt and Interrupt Acknowledge Timing Requirements..................................................... 150
External Interrupt and Interrupt Acknowledge Switching Characteristics ................................................ 150
XF Switching Characteristics................................................................................................... 151
GPIO Pins Configured as Inputs Timing Requirements .................................................................... 152
GPIO Pins Configured as Outputs Switching Characteristics ............................................................. 152
PGPIO Pins Configured as Inputs Timing Requirements .................................................................. 153
PGPIO Pins Configured as Outputs Switching Characteristics............................................................ 153
TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements..................................... 154
TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics .............................. 154
TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements ....................................................... 155
TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics................................................... 155
TIM0/TIM1/WDTOUT Interrupt Timing Requirements ...................................................................... 157
McBSP Transmit and Receive Timing Requirements ...................................................................... 158
McBSP Transmit and Receive Switching Characteristics .................................................................. 159
McBSP General-Purpose I/O Timing Requirements........................................................................ 161
McBSP General-Purpose I/O Switching Characteristics ................................................................... 161
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................. 162
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................. 162
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................. 164
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................. 164
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................. 165
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................. 165
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
5-36
5-37
5-38
5-39
5-40
12
List of Tables
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
6-1
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................. 167
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)............................. 167
HPI Read and Write Timing Requirements .................................................................................. 169
HPI Read and Write Switching Characteristics .............................................................................. 170
HPI General-Purpose I/O Timing Requirements ............................................................................ 176
HPI General-Purpose I/O Switching Characteristics........................................................................ 176
HPI.HAS Interrupt Timing Requirements ..................................................................................... 178
I2C Signals (SDA and SCL) Timing Requirements.......................................................................... 179
I2C Signals (SDA and SCL) Switching Characteristics ..................................................................... 180
UART Timing Requirements ................................................................................................... 181
UART Switching Characteristics............................................................................................... 181
Thermal Resistance Characteristics (Ambient).............................................................................. 182
Thermal Resistance Characteristics (Case).................................................................................. 183
6-2
List of Tables
13
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
14
List of Tables
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
1
TMS320VC5502
1.1 Features
•
•
Programmable Low-Power Control of Six
Device Functional Domains
•
High-Performance, Low-Power, Fixed-Point
TMS320C55x™ Digital Signal Processor (DSP)
–
–
–
–
–
3.33-/5-ns Instruction Cycle Time
300-/200-MHz Clock Rate
16K-Byte Instruction Cache (I-Cache)
One/Two Instructions Executed per Cycle
Dual Multipliers [Up to 600 Million
Multiply-Accumulates Per Second
(MMACS)]
On-Chip Peripherals
–
–
–
–
–
–
Six-Channel Direct Memory Access (DMA)
Controller
Three Multichannel Buffered Serial Ports
(McBSPs)
Programmable Analog Phase-Locked Loop
(APLL) Clock Generator
General-Purpose I/O (GPIO) Pins and a
Dedicated Output Pin (XF)
–
–
Two Arithmetic/Logic Units (ALUs)
One Program Bus, Three Internal
Data/Operand Read Buses, and Two
Internal Data/Operand Write Buses
8-Bit/16-Bit Parallel Host-Port Interface
(HPI)
Four Timers
•
•
Instruction Cache (16K Bytes)
•
•
•
Two 64-Bit General-Purpose Timers
64-Bit Programmable Watchdog Timer
64-Bit DSP/BIOS™ Counter
32K x 16-Bit On-Chip RAM That is Composed
of Eight Blocks of 4K × 16-Bit Dual-Access
RAM (DARAM) (64K Bytes)
–
–
Inter-Integrated Circuit (I2C) Interface
•
•
•
16K × 16-Bit One-Wait-State On-Chip ROM
(32K Bytes)
Universal Asynchronous Receiver/
Transmitter (UART)
8M × 16-Bit Maximum Addressable External
Memory Space
•
•
On-Chip Scan-Based Emulation Logic
IEEE Std 1149.1(1) (JTAG) Boundary Scan
Logic
32-Bit External Parallel Bus Memory Support-
ing External Memory Interface (EMIF) With
General-Purpose Input/Output (GPIO) Capabili-
ties and Glueless Interface to:
•
Packages:
–
176-Terminal LQFP (Low-Profile Quad
Flatpack) (PGF Suffix)
–
–
–
–
Asynchronous Static RAM (SRAM)
Asynchronous EPROM
Synchronous DRAM (SDRAM)
Synchronous Burst RAM (SBRAM)
–
201-Terminal MicroStar BGA™ (Ball Grid
Array) (GZZ and ZZZ Suffixes)
•
•
3.3-V I/O Supply Voltage
1.26-V Core Supply Voltage
•
Emulation/Debug Trace Capability Saves Last
16 Program Counter (PC) Discontinuities and
Last 32 PC Values
(1) IEEE Standard 1149.1 - 1990 Standard Test Access Port and
Boundary Scan Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320,
TMS320C5000 are trademarks of Texas Instruments.
I2C bus is a trademark of Koninklijke Philips Electronics N.V.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
2
Introduction
This section describes the main features of the TMS320VC5502 and gives a brief description of the
device.
NOTE
This document is designed to be used in conjunction with the TMS320C55x DSP CPU
Reference Guide (literature number SPRU371).
2.1 Description
The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™
DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low
power through increased parallelism and total focus on reduction in power dissipation. The CPU supports
an internal bus structure that is composed of one program bus, three data read buses, two data write
buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to
perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can
perform data transfers independent of the CPU activity.
The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional
16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel
activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit
(DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues
instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and
DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline
flushes on execution of conditional instructions.
The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such
as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog
timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless
interface to a variety of industry-standard serial devices, and multichannel communication with up to 128
separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide
host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either
multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors.
The DMA controller provides data movement for six independent channel contexts without CPU
intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog
phase-locked loop (APLL) clock generation are also included.
The 5502 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the
industry's largest third-party network. The Code Composer Studio™ IDE features code generation tools
that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and
evaluation modules. The 5502 is also supported by the C55x™ DSP Library, which features more than 50
foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and
board support libraries.
16
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
2.2 Pin Assignments
2.2.1 Ball Grid Array (GZZ and ZZZ)
The TMS320VC5502 is offered in two 201-terminal ball grid array (BGA) packages, both of which include
25 thermal balls to improve thermal dissipation. Except for their Eco-Status (refer to Section 6.2,
Packaging Information), both packages are essentially the same. Figure 2-1 illustrates the ball locations
for both BGA packages. Table 2-1 lists the locations of the thermal balls and Table 2-2 lists the signal
names and terminal numbers.
NOTE
Some TMX samples were shipped in the GGW package. For more information on the
GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors
Silicon Errata (literature number SPRZ020D or later).
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17
10 12 14 16
2
4
6
8
Figure 2-1. 201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View)
Table 2-1. 201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations(1)
BALL NO.
BALL NO.
BALL NO.
BALL NO.
G10
BALL NO.
G11
G7
H7
J7
G8
H8
J8
G9
H9
J9
H10
H11
J10
J11
K7
L7
K8
L8
K9
L9
K10
K11
L10
L11
(1) For best device thermal performance:
•
•
An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted.
The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability
Temperature Cycle performance.
•
•
The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be
connected to the ground plane for heat dissipation.
A solid internal plane is preferred for spreading the heat.
Refer to the MicroStar BGA™ Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount,
and reliability considerations.
Introduction
17
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-2. 201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments(1)
BALL NO.
B1
C2
C1
D3
D2
D1
E3
E2
E1
F3
SIGNAL NAME
GPIO6
GPIO4
GPIO2
GPIO1
GPIO0
TIM1
BALL NO.
U2
SIGNAL NAME
HCNTL1
HCNTL0
VSS
BALL NO.
T17
R16
R17
P15
P16
P17
N15
N16
N17
M15
M16
M17
L14
SIGNAL NAME
A19
A18
VSS
BALL NO.
A16
B15
A15
C14
B14
A14
C13
B13
A13
C12
B12
A12
D11
C11
B11
A11
A10
D10
C10
B10
A9
SIGNAL NAME
D16
T3
D15
U3
D14
R4
HR/W
HDS2
CVDD
HDS1
HRDY
DVDD
CLKOUT
XF
A17
A16
DVDD
A15
A14
VSS
D13
T4
D12
U4
D11
TIM0
R5
D10
INT0
T5
D9
CVDD
INT1
U5
DVDD
D8
R6
A13
A12
CVDD
A11
A10
A9
F2
INT2
T6
D7
F1
DVDD
INT3
U6
VSS
VSS
G4
G3
G2
G1
H1
H4
H3
H2
J1
P7
C15
D6
NMI/WDTOUT
IACK
VSS
R7
C14
L15
D5
T7
HINT
PVDD
NC(2)
X1
L16
D4
U7
L17
A8
CVDD
D3
CLKR0
DR0
U8
K17
K14
K15
K16
J17
DVDD
A7
P8
D2
FSR0
CLKX0
CVDD
DX0
R8
X2/CLKIN
EMIFCLKS
VSS
A6
D1
T8
A5
D0
U9
VSS
VSS
J4
P9
C13
J14
A4
D9
EMU1/OFF
EMU0
TDO
VSS
J3
FSX0
CLKR1
DR1
R9
C12
J15
A3
C9
J2
T9
C11
J16
A2
B9
K1
K2
K4
K3
L1
U10
T10
P10
R10
U11
T11
R11
P11
U12
T12
R12
U13
T13
R13
U14
T14
R14
U15
T15
U16
C10
H17
H16
H14
H15
G17
G16
G15
G14
F17
F16
F15
E17
E16
E15
D17
D16
D15
C17
C16
B17
CVDD
D31
D30
D29
VSS
A8
FSR1
DX1
C9
B8
TDI
C8
D8
TRST
TCK
TMS
RESET
HPIENA
HD7
CVDD
HD6
HD5
DVDD
HD4
HD3
CVDD
HD2
HD1
VSS
CLKX1
VSS
C7
C8
VSS
A7
L2
FSX1
DR2
ECLKIN
ECLKOUT2
ECLKOUT1
CVDD
C6
D28
D27
D26
CVDD
D25
D24
DVDD
D23
D22
D21
D20
D19
VSS
B7
L3
C7
L4
DX2
D7
M1
M2
M3
N1
N2
N3
P1
P2
P3
R1
R2
T1
CVDD
SP3
A6
B6
SP2
C5
C6
DVDD
SP1
DVDD
C4
A5
B5
SP0
C3
C5
VSS
VSS
A4
SCL
C2
B4
SDA
C1
C4
HC1
C0
A3
HC0
A21
D18
D17
B3
HD0
GPIO7
HCS
A20
A2
(1) CVDD is core VDD, DVDD is I/O VDD, and PVDD is PLL VDD
.
(2) NC = No Connect
18
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
2.2.2 Low-Profile Quad Flatpack (PGF)
The TMS320VC5502 is offered in a 176-pin low-profile quad flatpack (LQFP). Figure 2-2 illustrates the pin
locations for the 176-pin LQFP. Table 2-3 lists the signal names and pin numbers.
NOTE
TMS320VC5502PGF has completed Temp Cycle reliability qualification testing with no
failures through 1500 cycles of –55°C to 125°C following an EIA/JEDEC Moisture
Sensitivity Level 4 pre-condition at 220+5/–0°C peak reflow. Exceeding this peak reflow
temperature condition or storage and handling requirements may result in either
immediate device failure post-reflow, due to package/die material delamination
("popcorning"), or degraded Temp cycle life performance.
Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life
information on a bar-code label affixed to dry-pack shipping bags. Shelf life, temperature
and humidity storage conditions and re-bake instructions are prominently displayed on a
nearby screen-printed label.
132
89
88
133
176
45
1
44
Figure 2-2. 176-Pin PGF Low-Profile Quad Flatpack (Top View)
Introduction
19
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-3. 176-Pin PGF Low-Profile Quad Flatpack Pin Assignments(1)
PIN NO.
1
SIGNAL NAME
GPIO6
GPIO4
GPIO2
GPIO1
GPIO0
TIM1
PIN NO.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
SIGNAL NAME
HCNTL1
HCNTL0
VSS
PIN NO.
89
SIGNAL NAME
A19
A18
VSS
PIN NO.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
SIGNAL NAME
D16
2
90
D15
3
91
D14
4
HR/W
HDS2
CVDD
HDS1
HRDY
DVDD
CLKOUT
XF
92
A17
A16
DVDD
A15
A14
VSS
D13
5
93
D12
6
94
D11
7
TIM0
95
D10
8
INT0
96
D9
9
CVDD
INT1
97
DVDD
D8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
98
A13
A12
CVDD
A11
A10
A9
INT2
99
D7
DVDD
INT3
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
VSS
C15
D6
NMI/WDTOUT
IACK
VSS
C14
D5
HINT
PVDD
NC(2)
X1
D4
A8
CVDD
D3
CLKR0
DR0
DVDD
A7
D2
FSR0
CLKX0
CVDD
DX0
X2/CLKIN
EMIFCLKS
VSS
A6
D1
A5
D0
VSS
VSS
C13
A4
EMU1/OFF
EMU0
TDO
VSS
FSX0
CLKR1
DR1
C12
A3
C11
A2
C10
CVDD
D31
D30
D29
VSS
FSR1
DX1
C9
TDI
C8
TRST
TCK
TMS
RESET
HPIENA
HD7
CVDD
HD6
HD5
DVDD
HD4
HD3
CVDD
HD2
HD1
VSS
CLKX1
VSS
C7
VSS
FSX1
DR2
ECLKIN
ECLKOUT2
ECLKOUT1
CVDD
C6
D28
D27
D26
CVDD
D25
D24
DVDD
D23
D22
D21
D20
D19
VSS
DX2
CVDD
SP3
SP2
C5
DVDD
SP1
DVDD
C4
SP0
C3
VSS
VSS
SCL
C2
SDA
C1
HC1
C0
HC0
A21
D18
D17
HD0
GPIO7
HCS
A20
(1) CVDD is core VDD, DVDD is I/O VDD, and PVDD is PLL VDD
.
(2) NC = No Connect
20
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
2.2.3 Signal Descriptions
Table 2-4 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2, Pin
Assignments, for exact pin locations based on package type.
Table 2-4. Signal Descriptions
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
Parallel Port — Address Bus
The A[21:18] pins of the Parallel Port serve one of two functions: parallel
general-purpose input/output (PGPIO) signals PGPIO[3:0] or external memory
interface (EMIF) address bus signals EMIF.A[21:18]. The function of the A[21:18]
pins is determined by the state of the GPIO6 pin during reset. The A[21:18] pins are
set to PGPIO[3:0] if GPIO6 is low during reset. The A[21:18] pins are set to
EMIF.A[21:18] if GPIO6 is high during reset. The function of the A[21:18] pins will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
A[21:18]
I/O/Z
The A[21:18] bus includes bus holders to reduce the static power dissipation caused
by floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the bus goes into a high-impedance state, the bus
holders keep the address bus at the logic level that was most recently driven. The
bus holders are enabled at reset and can be enabled/disabled through the External
Bus Control Register (XBCR).
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO[3:0] is selected if GPIO6 is low during reset.
The PGPIO[3:0] signals are configured as inputs after reset.
PGPIO[3:0]
I/O/Z
O/Z
EMIF address bus. EMIF.A[21:18] is selected if GPIO6 is high during reset. The
EMIF.A[21:18] signals are in a high-impedance state during reset and are configured
as outputs after reset with an output value of 0.
EMIF.A[21:18]
(1) I = Input, O = Output, S = Supply, Z = High impedance
(2) Other Pin Characteristics:
A - Internal pullup [always enabled]
B - Internal pulldown [always enabled]
C - Hysteresis input
D - Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].
E - Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)
determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode. If
EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.
F - Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).
G - Pin can be configured as a general-purpose input.
H - Pin can be configured as a general-purpose output.
J - Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].
K - Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].
L - Fail-safe pin
M - Pin is in high-impedance during reset (RESET pin is low)
Introduction
21
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
The A[17:2] pins of the Parallel Port serve one of two functions: host-port interface
(HPI) address bus signals HPI.HA[15:0] or external memory interface (EMIF)
address bus signals EMIF.A[17:2]. The function of the A[17:2] pins is determined by
the state of the GPIO6 pin during reset. The A[17:2] pins are set to HPI.HA[15:0] if
GPIO6 is low during reset. The A[17:2] pins are set to EMIF.A[17:2] if GPIO6 is high
during reset. The function of the A[17:2] pins will be set once the device is taken out
of reset (RESET pin transitions from a low to high state).
A[17:2]
I/O/Z
The A[17:2] bus includes bus holders to reduce the static power dissipation caused
by floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the bus goes into a high-impedance state, the bus
holders keep the address bus at the logic level that was most recently driven. The
bus holders are enabled at reset and can be enabled/disabled through the External
Bus Control Register (XBCR).
C, D, E, F,
M
HPI address bus. HPI.HA[15:0] is selected when GPIO6 is low during reset. The
HPI.HA[15:0] signals are configured as inputs after reset.
The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In
non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit
address bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle
on the data bus consists of one 16-bit data transfer.
HPI.HA[15:0]
EMIF.A[17:2]
I/O/Z
O/Z
EMIF address bus. EMIF.A[17:2] is selected when GPIO6 is high during reset. The
EMIF.A[17:2] signals are in a high-impedance state during reset and are configured
as outputs after reset with an output value of 0.
Parallel Port — Data Bus
The D[31:16] pins of the Parallel Port serve one of two functions: parallel
general-purpose input/output (PGPIO) signals PGPIO[19:4] or external memory
interface (EMIF) data bus signals EMIF.D[31:16]. The function of the D[31:16] pins is
determined by the state of the GPIO6 pin during reset. The D[31:16] pins are set to
PGPIO[19:4] if GPIO6 is low during reset. The D[31:16] pins are set to
EMIF.D[31:16] if GPIO6 is high during reset. The function of the D[31:16] pins will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
D[31:16]
I/O/Z
The D[31:16] bus includes bus holders to reduce the static power dissipation caused
by floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the bus goes into a high-impedance state, the bus
holders keep the data bus at the logic level that was most recently driven. The bus
holders are enabled at reset and can be enabled/disabled through the External Bus
Control Register (XBCR).
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO[19:4] is selected when GPIO6 is low during
reset. The PGPIO[19:4] signals are configured as inputs after reset.
PGPIO[19:4]
I/O/Z
I/O/Z
EMIF data bus. EMIF.D[31:16] is selected when GPIO6 is high during reset. The
EMIF.D[31:16] signals are configured as inputs after reset.
EMIF.D[31:16]
The D[15:0] pins of the Parallel Port serve one of two functions: host-port interface
(HPI) data bus signals HPI.HD[15:0] and external memory interface (EMIF) data bus
signals EMIF.D[15:0]. The function of the D[15:0] pins is determined by the state of
the GPIO6 pin during reset. The D[15:0] pins are set to HPI.HD[15:0] if GPIO6 is low
during reset. The D[15:0] pins are set to EMIF.D[15:0] if GPIO6 is high during reset.
The function of the D[15:0] pins will be set once the device is taken out of reset
(RESET pin transitions from a low to high state).
D[15:0]
I/O/Z
The D[15:0] bus includes bus holders to reduce the static power dissipation caused
by floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the bus goes into a high-impedance state, the bus
holders keep the data bus at the logic level that was most recently driven. The bus
holders are enabled at reset and can be enabled/disabled through the External Bus
Control Register (XBCR).
C, D, E, F,
M
HPI data bus. HPI.HD[15:0] is selected when GPIO6 is low during reset. The
HPI.HD[15:0] signals are configured as inputs after reset.
The HPI will operate in non-multiplexed mode when GPIO6 is low during reset. In
non-multiplexed mode, the HPI uses separate address and data buses: a 16-bit
address bus (HPI.HA[15:0]) and a 16-bit data bus (HPI.HD[15:0]). Each host cycle
on the data bus consists of one 16-bit data transfer.
HPI.HD[15:0]
EMIF.D[15:0]
I/O/Z
I/O/Z
EMIF data bus. EMIF.D[15:0] is selected when GPIO6 is high during reset. The
EMIF.D[15:0] signals are configured as inputs after reset.
22
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
Parallel Port — Control Pins
The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO20 or external memory interface control signal
EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the
state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low
during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high
during reset. The function of the C0 pin will be set once the device is taken out of
reset (RESET pin transitions from a low to high state).
C0
I/O/Z
I/O/Z
Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during
reset. The PGPIO20 signal is configured as an input after reset.
PGPIO20
C, D, E, F,
G, H, M
EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high
during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state
during reset and is set to output after reset with an output value of 1.
The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used
by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory
address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and
synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary
Control Register 1).
EMIF.ARE/SADS/
SDCAS/SRE
O/Z
The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO21 or external memory interface control signal
EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of
the GPIO6 pin during reset. The C1 pin is set to PGPIO21 if GPIO6 is low during
reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset.
The function of the C1 pin will be set once the device is taken out of reset (RESET
pin transitions from a low to high state).
C1
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during
reset. The PGPIO21 signal is configured as an input after reset.
PGPIO21
I/O/Z
O/Z
EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during
reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by
the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory
output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS).
EMIF.AOE/SOE/
SDRAS
The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO22 or external memory interface control signal
EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the
GPIO6 pin during reset. The C2 pin is set to PGPIO22 if GPIO6 is low during reset.
The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The
function of the C2 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C2
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during
reset. The PGPIO22 signal is configured as an input after reset.
PGPIO22
I/O/Z
O/Z
EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during
reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The EMIF.AWE/SWE/SDWE signal serves three different functions when used by
the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory
write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE).
EMIF.AWE/SWE/
SDWE
Introduction
23
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
The C3 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO23 or external memory interface control signal
EMIF.ARDY. The function of the C3 pin is determined by the state of the GPIO6 pin
during reset. The C3 pin is set to PGPIO23 if GPIO6 is low during reset. The C3 pin
is set to EMIF.ARDY if GPIO6 is high during reset. The function of the C3 pin will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
C3
I/O/Z
F, G, H, J Parallel general-purpose I/O. PGPIO23 is selected when GPIO6 is low during
PGPIO23
I/O/Z
I
reset. The PGPIO23 signal is configured as an input after reset.
EMIF data ready pin. EMIF.ARDY is selected when GPIO6 is high during reset.The
EMIF.ARDY signal indicates that an external device is ready for a bus transaction to
be completed. If the device is not ready (EMIF.ARDY is low), the processor extends
the memory access by one cycle and checks EMIF.ARDY again. An internal pullup
is included to disable this feature if not used. The internal pullup can be disabled
through the External Bus Control Register (XBCR).
EMIF.ARDY
The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO24 or external memory interface control signal
EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin
during reset. The C4 pin is set to PGPIO24 if GPIO6 is low during reset. The C4 pin
is set to EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be
C4
C5
C6
I/O/Z
set once the device is taken out of reset (RESET pin transitions from a low to high
C, D, E, F,
state).
G, H, M
Parallel general-purpose I/O. PGPIO24 is selected when GPIO6 is low during
reset. The PGPIO24 signal is configured as an input after reset.
PGPIO24
EMIF.CE0
I/O/Z
O/Z
EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is
high during reset. The EMIF.CE0 signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO25 or external memory interface control signal
EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin
during reset. The C5 pin is set to PGPIO25 if GPIO6 is low during reset. The C5 pin
is set to EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be
I/O/Z
set once the device is taken out of reset (RESET pin transitions from a low to high
C, D, E, F,
state).
G, H, M
Parallel general-purpose I/O. PGPIO25 is selected when GPIO6 is low during
reset. The PGPIO25 signal is configured as an input after reset.
PGPIO25
EMIF.CE1
I/O/Z
O/Z
EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is
high during reset. The EMIF.CE1 signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO26 or external memory interface control signal
EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin
during reset. The C6 pin is set to PGPIO26 if GPIO6 is low during reset. The C6 pin
is set to EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be
I/O/Z
set once the device is taken out of reset (RESET pin transitions from a low to high
C, D, E, F,
state).
G, H, M
Parallel general-purpose I/O. PGPIO26 is selected when GPIO6 is low during
reset. The PGPIO26 signal is configured as an input after reset.
PGPIO26
EMIF.CE2
I/O/Z
O/Z
EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is
high during reset. The EMIF.CE2 signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
24
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
The C7 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO27 or external memory interface control signal
EMIF.CE3. The function of the C7 pin is determined by the state of the GPIO6 pin
during reset. The C7 pin is set to PGPIO27 if GPIO6 is low during reset. The C7 pin
is set to EMIF.CE3 if GPIO6 is high during reset. The function of the C7 pin will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
C7
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO27 is selected when GPIO6 is low during
reset. The PGPIO27 signal is configured as an input after reset.
PGPIO27
EMIF.CE3
I/O/Z
O/Z
EMIF chip-select for memory space CE3. EMIF.CE3 is selected when GPIO6 is
high during reset. The EMIF.CE3 signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The C8 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO28 or external memory interface control signal
EMIF.BE0. The function of the C8 pin is determined by the state of the GPIO6 pin
during reset. The C8 pin is set to PGPIO28 if GPIO6 is low during reset. The C8 pin
is set to EMIF.BE0 if GPIO6 is high during reset. The function of the C8 pin will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
C8
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO28 is selected when GPIO6 is low during
reset. The PGPIO28 signal is configured as an input after reset.
PGPIO28
EMIF.BE0
I/O/Z
O/Z
EMIF byte-enable 0 control. EMIF.BE0 is selected when GPIO6 is high during
reset. The EMIF.BE0 signal is in a high-impedance state during reset and is set to
output after reset with an output value of 1.
The C9 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO29 or external memory interface control signal
EMIF.BE1. The function of the C9 pin is determined by the state of the GPIO6 pin
during reset. The C9 pin is set to PGPIO29 if GPIO6 is low during reset. The C9 pin
is set to EMIF.BE1 if GPIO6 is high during reset. The function of the C9 pin will be
set once the device is taken out of reset (RESET pin transitions from a low to high
state).
C9
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO29 is selected when GPIO6 is low during
reset. The PGPIO29 signal is configured as an input after reset.
PGPIO29
EMIF.BE1
I/O/Z
O/Z
EMIF byte-enable 1 control. EMIF.BE1 is selected when GPIO6 is high during
reset. The EMIF.BE1 signal is in a high-impedance state during reset and is set to
output after reset with an output value of 1.
The C10 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO30 or external memory interface
control signal EMIF.BE2. The function of the C10 pin is determined by the state of
the GPIO6 pin during reset. The C10 pin is set to PGPIO30 if GPIO6 is low during
reset. The C10 pin is set to EMIF.BE2 if GPIO6 is high during reset. The function of
the C10 pin will be set once the device is taken out of reset (RESET pin transitions
from a low to high state).
C10
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO30 is selected when GPIO6 is low during
reset. The PGPIO30 signal is configured as an input after reset.
PGPIO30
EMIF.BE2
I/O/Z
O/Z
EMIF byte-enable 2 control. EMIF.BE2 is selected when GPIO6 is high during
reset. The EMIF.BE2 signal is in a high-impedance state during reset and is set to
output after reset with an output value of 1.
The C11 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO31 or external memory interface
control signal EMIF.BE3. The function of the C11 pin is determined by the state of
the GPIO6 pin during reset. The C11 pin is set to PGPIO31 if GPIO6 is low during
reset. The C11 pin is set to EMIF.BE3 if GPIO6 is high during reset. The function of
the C11 pin will be set once the device is taken out of reset (RESET pin transitions
from a low to high state).
C11
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO31 is selected when GPIO6 is low during
reset. The PGPIO31 signal is configured as an input after reset.
PGPIO31
EMIF.BE3
I/O/Z
O/Z
EMIF byte-enable 3 control. EMIF.BE3 is selected when GPIO6 is high during
reset. The EMIF.BE3 signal is in a high-impedance state during reset and is set to
output after reset with an output value of 1.
Introduction
25
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
The C12 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO32 or external memory interface
control signal EMIF.SDCKE. The function of the C12 pin is determined by the state
of the GPIO6 pin during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during
reset. The C12 pin is set to EMIF.SDCKE if GPIO6 is high during reset. The function
of the C12 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C12
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during
reset. The PGPIO32 signal is configured as an input after reset.
PGPIO32
I/O/Z
O/Z
EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during
reset. The EMIF.SDCKE signal is in a high-impedance state during reset and is set
to output after reset with an output value of 1.
EMIF.SDCKE
The C13 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO33 or external memory interface
control signal EMIF.SOE3. The function of the C13 pin is determined by the state of
the GPIO6 pin during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during
reset. The C13 pin is set to EMIF.SOE3 if GPIO6 is high during reset. The function
of the C13 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C13
I/O/Z
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during
reset. The PGPIO33 signal is configured as an input after reset.
PGPIO33
I/O/Z
O/Z
EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when
GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state
during reset and is set to output after reset with an output value of 1.
The EMIF.SOE3 is intended for glueless FIFO interface.
EMIF.SOE3
The C14 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO34 or external memory interface
control signal EMIF.HOLD. The function of the C14 pin is determined by the state of
the GPIO6 pin during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during
reset. The C14 pin is set to EMIF.HOLD if GPIO6 is high during reset. The function
of the C14 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C14
I/O/Z
F, G, H, J,
M
Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during
reset. The PGPIO34 signal is configured as an input after reset.
PGPIO34
I/O/Z
I
EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset.
EMIF.HOLD is asserted by an external host to request control of the address, data,
and control signals.
EMIF.HOLD
The C15 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO35 or external memory interface
control signal EMIF.HOLDA. The function of the C15 pin is determined by the state
of the GPIO6 pin during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during
reset. The C15 pin is set to EMIF.HOLDA if GPIO6 is high during reset. The function
of the C15 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C15
I/O/Z
C, D, F, G,
H, M
Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during
reset. The PGPIO35 signal is configured as an input after reset.
PGPIO35
I/O/Z
O/Z
EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during
reset. The EMIF.HOLDA signal is in a high-impedance state during reset and is set
to output after reset with an output value of '1'.
EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state
and that the EMIF address, data, and control signals are in a high-impedance state,
allowing the external memory interface to be accessed by other devices.
EMIF.HOLDA
EMIF — Clock Pins
External EMIF input clock. ECLKIN is selected as the input clock to the EMIF
when EMIFCLKS is high.
ECLKIN
I
C, L
26
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
EMIF output clock. ECLKOUT1 outputs the EMIF input clock by default but can be
held low or set to a high-impedance state through the EMIF Global Control
Register 1 (EGCR1).
The ECLKOUT1 pin is always in a high-impedance state during reset. The behavior
of ECLKOUT1 immediately after reset depends on the state of GPIO6 during reset
and EMIFCLKS:
ECLKOUT1
O/Z
E, F, M
•
•
•
•
GPIO6 = 0 and EMIFCLKS =0: ECLKOUT1 is in a high-impendance state.
GPIO6 = 0 and EMIFCLKS =1: ECLKOUT1 toggles at ECLKIN frequency.
GPIO6 = 1 and EMIFCLKS =0: ECLKOUT1 toggles at SYSCLK3 frequency.
GPIO6 = 1 and EMIFCLKS =1: ECLKOUT1 toggles at ECLKIN frequency.
EMIF output clock. ECLKOUT2 can be enabled to output the EMIF input clock
divided by a factor 1, 2, or 4 through the EMIF Global Control Register 2 (EGCR2).
ECLKOUT2 can also be held low or set to a high-impedance state through the
EGCR2 register.
The ECLKOUT2 pin toggles with a clock frequency equal to the EMIF input clock
divided by 4 during reset. The behavior of ECLKOUT2 immediately after reset
depends on the state of GPIO6 during reset and EMIFCLKS:
ECLKOUT2
O/Z
E, F
•
•
GPIO6 = 0 and EMIFCLKS =0: ECLKOUT2 is held low.
GPIO6 = 0 and EMIFCLKS =1: ECLKOUT2 toggles at one-fourth of the ECLKIN
frequency.
•
•
GPIO6 = 1 and EMIFCLKS =0: ECLKOUT2 toggles at one-fourth of the
SYSCLK3 frequency.
GPIO6 = 1 and EMIFCLKS =1: ECLKOUT2 toggles at one-fourth of the ECLKIN
frequency.
EMIF input clock source select. The clock source for the EMIF is determined by
the state of the EMIFCLKS pin. The EMIF uses an internal clock (SYSCLK3) if
EMIFCLKS is low. ECLKIN is used as the clock source if EMIFCLKS is high.
EMIFCLKS
I
C, L
Host Port — Data Bus
The HD[7:0] pins of the Host Port serve one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signals PGPIO[43:36] or host-port interface (HPI)
data bus signals HPI.HD[7:0]. The function of the HD[7:0] pins is determined by the
state of the GPIO6 pin during reset. The HD[7:0] pins are set to PGPIO[43:36] if
GPIO6 is low during reset. The HD[7:0] pins are set to HPI.HD[7:0] if GPIO6 is high
during reset. The function of the HD[7:0] pins will be set once the device is taken out
of reset (RESET pin transitions from a low to high state).
HD[7:0]
I/O/Z
The HD[7:0] bus includes bus holders to reduce the static power dissipation caused
by floating, unused pins. The bus holders also eliminate the need for external bias
resistors on unused pins. When the bus goes into a high-impedance state, the bus
holders keep the address bus at the logic level that was most recently driven. The
bus holders are enabled at reset and can be enabled/disabled through the External
Bus Control Register (XBCR).
C, D, F, G,
H, M
Parallel general-purpose I/O. PGPIO[43:36] is selected when GPIO6 is low during
reset. The PGPIO[43:36] signals are configured as inputs after reset.
PGPIO[43:36]
HPI.HD[7:0]
I/O/Z
I/O/Z
Host data bus. HPI.HD[7:0] is selected when GPIO6 is high during reset. The
HPI.HD[7:0] signals are configured as inputs after reset.
The HPI will operate in mulitplexed mode when GPIO6 is high during reset. In
multiplexed mode, an 8-bit data bus (HPI.HD[7:0]) carries both address and data.
Each host cycle on the bus consists of two consecutive 8-bit transfers.
Introduction
27
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
Host Port — Control Pins
The HC0 pin of the Host Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO44 or host-port interface (HPI) signal HPI.HAS.
The function of the HC0 pin is determined by the state of the GPIO6 pin during
reset. The HC0 pin is set to PGPIO44 if GPIO6 is low during reset. The HC0 pin is
set to HPI.HAS if GPIO6 is high during reset. The function of the HC0 pin will be set
once the device is taken out of reset (RESET pin transitions from a low to high
state).
HC0
I/O/Z
C, F, G, H,
J, M
Parallel general-purpose I/O. PGPIO44 is selected when GPIO6 is low during
reset. The PGPIO44 signal is configured as an input after reset.
PGPIO44
HPI.HAS
I/O/Z
I
Host address strobe. HPI.HAS is selected when GPIO6 is high during reset. The
HPI.HAS signal is configured as an input after reset.
Hosts with multiplexed address and data pins may require HPI.HAS to latch the
address in the HPIA register. HPI.HAS is only available when the HPI is operating in
multiplexed mode.
The HC1 pin of the Host Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO45 or host-port interface (HPI) signal HPI.HBIL.
The function of the HC1 pin is determined by the state of the GPIO6 pin during
reset. The HC1 pin is set to PGPIO45 if GPIO6 is low during reset. The HC1 pin is
set to HPI.HBIL if GPIO6 is high during reset. The function of the HC1 pin will be set
once the device is taken out of reset (RESET pin transitions from a low to high
state).
HC1
I/O/Z
F, G, H, K,
M
Parallel general-purpose I/O. PGPIO45 is selected when GPIO6 is low during
reset. The PGPIO45 signal is configured as an input after reset.
PGPIO45
HPI.HBIL
I/O/Z
I
Host byte identification. HPI.HBIL is selected when GPIO6 is high during reset.
The HPI.HBIL signal is configured as an input after reset.
In multiplexed mode, the host must use HPI.HBIL to identify the first and second
bytes of the host cycle.
HPI Pins
HCNTL0
HCNTL1
HPI access control pins.The four binary states of the HCNTL0 and HCNTL1 pins
F, G, H, J, determine which HPI register is being accessed by the host (HPIC, HPID with
I/O/Z
M
autoincrementing, HPIA, or HPID). The HCNTL0 and HCNTL1 pins are configured
as inputs after reset.
HPI chip-select. HCS must be low for the HPI to be selected by the host. The HCS
C, F, G, H, pin is configured as an input after reset.
HCS
I/O/Z
I/O/Z
I
J, M
A host must not initiate transfer requests until the HPI has been brought out of reset,
see Section 3.8, Host-Port Interface (HPI), for more details.
F, G, H, J, Host read- or write-select. HR/W indicates whether the current access is to be a
HR/W
HDS1
M
read or write operation. The HR/W pin is configured as an input after reset.
Host data strobe pins. The HDS1 and HDS2 pins are used for strobing data in and
out of the HPI. The HDS1 and HDS2 pins are configured as inputs after reset.
A host must not initiate transfer requests until the HPI has been brought out of reset,
see Section 3.8, Host-Port Interface (HPI), for more details.
C, G, H, J
HDS2
HRDY
Host ready (from DSP to host). The HRDY pin informs the host when the HPI is
ready for the next transfer. The HRDY pin is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
O/Z
O/Z
F, J, M
Host interrupt (from DSP to host). The HINT pin is used by the DSP to interrupt
the host. The HINT signal is in a high-impedance state during reset and is set to
output after reset with an output value of 1.
F, G, H, J,
M
HINT
HPI enable. The HPIENA pin must be driven high to enable the HPI for operation. If
the HPIENA pin is low, the HPI will be completely disabled and all HPI output pins
will be in a high-impedance state.
HPIENA
I
I
C, L
If the HPI is not needed, the HPIENA pin can be pulled low.
Interrupt and Reset Pins
Maskable external interrupts. INT0–INT3 are maskable interrupts. They are
enabled through the Interrupt Enable Registers (IER0 and IER1). All maskable
interrupts are globally enabled/disabled through the Interrupt Mode bit (INTM in
ST1_55). INT0–INT3 can be polled and reset via the Interrupt Flag Registers (IFR0
and IFR1). All interrupts are prioritized as shown in Table 3-77, Interrupt Table.
INT[3:0]
C, L
28
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
Non-maskable external interrupt or Watchdog Timer output.The function of this
pin is controlled by the Timer Signal Selection Register (TSSR). By default, the
NMI/WDTOUT pin has the function of the NMI signal.
NMI is an external interrupt that cannot be masked by the Interrupt Enable Registers
(IER0 and IER1). When NMI is activated, the interrupt is always performed.
WDTOUT serves as an input and output pin for the Watchdog Timer.
NMI/WDTOUT
I/O/Z
C, F, J, M
Interrupt acknowledge. IACK indicates the receipt of an interrupt and that the
program counter is fetching the interrupt vector location designated on the address
bus. The IACK pin is set to a value of '1' during reset.
IACK
O/Z
I
F, M
C, L
Device reset. RESET causes the digital signal processor (DSP) to terminate current
program execution. When RESET is brought to a high level, program execution
begins by fetching the reset interrupt service vector at the reset vector address
FFFF00h (IVPD:FFFFh). RESET affects various registers and status bits.
RESET
General-Purpose I/O Pins
General-purpose configurable inputs/outputs. GPIO[7:0] can be individually
configured as inputs or outputs via the GPIO Direction Register (IODIR). Data can
be read from inputs or written to outputs via the GPIO Data Register (IODATA). The
GPIO pins are configured as inputs after reset.
Boot mode selection signals. GPIO[2:0]/BOOTM[2:0] are sampled following reset
to configure the boot mode for the DSP. After the boot is completed, these pins can
be used as general-purpose inputs/outputs.
The GPIO4 pin is also used as an output for handshaking purposes on some of the
boot modes. Although this pin is not involved in boot mode selection, users should
be aware that this pin will become active as an output during the bootload process
and should design accordingly. After the bootload process is complete, the loaded
application may change the function of the GPIO4 pin.
Multiplexed general-purpose input/output pins. The GPIO3 signal is multiplexed
with the CLKX2 signal through the SP0 pin. The function of the SP0 pin is
determined by the state of the GPIO7 pin during reset. The SP0 pin is set to GPIO3
if GPIO7 is low during reset. The SP0 pin is set to CLKX2 if GPIO7 is high during
reset. The function of the SP0 pin will be set once the device is taken out of reset
(RESET pin transitions from a low to high state).
The GPIO5 signal is multiplexed with the FSX2 signal through the SP2 pin. The
function of the SP2 pin is determined by the state of the GPIO7 pin during reset.
The SP2 pin is set to GPIO5 if GPIO7 is low during reset. The SP2 pin is set to
FSX2 if GPIO7 is high during reset. The function of the SP2 pin will be set once the
device is taken out of reset (RESET pin transitions from a low to high state).
Input clock source selection. The CLKMD0 bit of the Clock Mode Control Register
(CLKMD) determines which clock, either OSCOUT or X2/CLKIN, is used as an input
clock source to the DSP. If GPIO4 is low at reset, the CLKMD0 bit of the Clock
Mode Control Register (CLKMD) will be set to '0' and the internal oscillator and the
external crystal will generate an input clock (OSCOUT) for the DSP. If GPIO4 is
high, the CLKMD0 bit will be set to '1' and the input clock will be taken directly from
the X2/CLKIN pin.
GPIO7
GPIO6
GPIO5
GPIO4
I/O/Z
F, G, H, M
GPIO3
GPIO2/BOOTM2
GPIO1/BOOTM1
GPIO0/BOOTM0
An external crystal must be attached to the X1 and X2/CLKIN pins when the internal
oscillator is used to generate a clock to the DSP. Otherwise, when the oscillator is
not used to generate the input clock for the DSP, an externally generated 3.3-V
clock must be applied to the X2/CLKIN pin and the X1 pin must be left unconnected.
Function selection for multiplexed pins. The GPIO6 pin is used to select the
function of the multiplexed signals in the Parallel Port and the Host Port. The EMIF
will be disabled and the HPI will operate in non-multiplexed mode when the GPIO6
pin is low during reset. The EMIF will be enabled and the HPI will operate in
multiplexed mode when the GPIO6 pin is high during reset. The function of the
multiplexed signals will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
The GPIO7 pin is used to select the function of the multiplexed signals of Serial Port
2. The UART will be enabled and McBSP2 will be disabled when GPIO7 is low
during reset. McBSP2 will be enabled and the UART will be disalbed when GPIO7 is
high during reset. The function of the multiplexed signals will be set once the device
is taken out of reset (RESET pin transitions from a low to high state).
External output (latched software-programmable signal). XF is set high by the
BSET XF instruction, set low by BCLR XF instruction, or by loading ST1. XF is used
for signaling other processors in multiprocessor configurations or used as a
general-purpose output pin. The XF pin is set to a value of '1' during reset.
XF
O/Z
F
Introduction
29
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
Oscillator/Clock Pins
Clock output. CLKOUT can be set to reflect the clock of the Fast Peripherals Clock
Group, Slow Peripherals Clock Group, and the External Memory Interface Clock
Group. The CLKOUT pin is set to the internal clock SYSCLK1 during and after reset.
SYSCLK1 is set equal to a divided-by-four CLKIN or OSCOUT (depending on the
state of the GPIO4 pin) during and after reset. SYSCLK1 is used to clock the Fast
Peripheral Clock Group.
CLKOUT
O/Z
F
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN
functions as the clock input.
X2/CLKIN
X1
I
Output pin from the internal oscillator for the crystal. If the internal oscillator is
not used, X1 should be left unconnected.
O
Multichannel Buffered Serial Port Pins (McBSP0 and McBSP1)
C, F, G, H, Receive clock input of McBSP0. The CLKR0 pin is configured as an input after
CLKR0
DR0
I/O/Z
I
M
reset.
L, G
Serial data receive input of McBSP0
Frame synchronization pulse for receive input of McBSP0. The FSR0 pin is
configured as an input after reset.
FSR0
I/O/Z
F, G, H, M
C, F, G, H,
M
CLKX0
DX0
I/O/Z
O/Z
Transmit clock of McBSP0. The CLKX0 pin is configured as an input after reset.
Serial data transmit output of McBSP0. The DX0 pin is in a high-impedance state
during and after reset.
F, H, M
Frame synchronization pulse for transmit output of McBSP0. The FSX0 pin is
configured as an input after reset.
FSX0
I/O/Z
F, G, H, M
Receive clock input of McBSP1. The CLKR1 pin is configured as an input after
reset.
CLKR1
DR1
I/O/Z
I
C, G, H, M
L, G
Serial data receive input of McBSP1
Frame synchronization pulse for receive input of McBSP1. The FSR1 pin is
configured as an input after reset.
FSR1
I/O/Z
F, G, H, M
Serial data transmit output of McBSP1. The DX1 pin is in a high-impedance state
during and after reset.
DX1
O/Z
I/O/Z
I/O/Z
F, H, M
C, F, G, H,
M
CLKX1
FSX1
Transmit clock of McBSP1. The CLKX1 pin is configured as an input after reset.
Frame synchronization pulse for transmit output of McBSP1. The FSX1 pin is
configured as an input after reset.
F, G, H, M
Serial Port 2 (McBSP2/UART) Pins
McBSP2 data receive input
DR2
DX2
I
L, G
McBSP2 data transmit output. The DX2 pin is in a high-impedance state during
O/Z
F, H, M
and after reset.
The SP0 pin of Serial Port 2 serves one of two functions: GPIO3 or CLKX2. The
function of the SP0 pin is determined by the state of the GPIO7 pin during reset.
The SP0 pin is set to GPIO3 if GPIO7 is low during reset. The SP0 pin is set to
CLKX2 if GPIO7 is high during reset. The function of the SP0 pin will be set once
the device is taken out of reset (RESET pin transitions from a low to high state).
SP0
I/O/Z
C, F, M
GPIO3. GPIO3 is selected if GPIO7 is low during reset. The GPIO3 signal is
configured as input after reset.
GPIO3
CLKX2
I/O/Z
I/O/Z
G, H
G, H
McBSP2 transmit clock. CLKX2 is selected if GPIO7 is high during reset. The
CLKX2 signal is configured as input after reset.
The SP1 pin of Serial Port 2 serves one of two functions: UART.TX or CLKR2. The
function of the SP1 pin is determined by the state of the GPIO7 pin during reset.
The SP1 pin is set to UART.TX if GPIO7 is low during reset. The SP1 pin is set to
CLKR2 if GPIO7 is high during reset. The function of the SP1 pin will be set once
the device is taken out of reset (RESET pin transitions from a low to high state).
SP1
I/O/Z
C, F, M
UART transmit data output. UART.TX is selected if GPIO7 is low during reset. The
UART.TX signal outputs a value of 1 during and after reset.
UART.TX
CLKR2
O
McBSP2 receive clock. CLKR2 is selected if GPIO7 is high during reset. The
CLKR2 signal is configured as input after reset.
I/O/Z
G, H
30
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
The SP2 pin of Serial Port 2 serves one of two functions: GPIO5 or FSX2. The
function of the SP2 pin is determined by the state of the GPIO7 pin during reset.
The SP2 pin is set to GPIO5 if GPIO7 is low during reset. The SP2 pin is set to
FSX2 if GPIO7 is high during reset. The function of the SP2 pin will be set once the
device is taken out of reset (RESET pin transitions from a low to high state).
SP2
I/O/Z
F, M
GPIO5. GPIO5 is selected if GPIO7 is low during reset. The GPIO5 signal is
configured as input after reset.
GPIO5
FSX2
I/O/Z
I/O/Z
G, H
G, H
Frame synchronization pulse for transmitter of McBSP2. FSX2 is selected if
GPIO7 is high during reset. The FSX2 signal is configured as input after reset.
The SP3 pin of Serial Port 2 serves one of two functions: UART.RX or FSR2. The
function of the SP3 pin is determined by the state of the GPIO7 pin during reset.
The SP3 pin is set to UART.RX if GPIO7 is low during reset. The SP3 pin is set to
FSR2 if GPIO7 is high during reset. The function of the SP3 pin will be set once the
device is taken out of reset (RESET pin transitions from a low to high state).
SP3
I/O/Z
F, M
G, H
UART.RX
FSR2
I
UART receive data input. UART.RX is selected if GPIO7 is low during reset.
Frame synchronization pulse for receiver of McBSP2. FSR2 is selected if GPIO7
is high during reset. The FSR2 signal is configured as input after reset.
I/O/Z
I2C Pins
SCL
SDA
I/O/Z
I/O/Z
C, F, M
C, F, M
I2C clock bidirectional port. (Open collector I/O)
I2C data bidirectional port. (Open collector I/O)
Timer Pins
Input/Output pin for Timer 0. The TIM0 pin can be configured as an output or an
input via the Timer Signal Selection Register (TSSR). When configured as an
output, the TIM0 pin can signal a pulse or a change of state when the Timer 0 count
TIM0
TIM1
I/O/Z
I/O/Z
F, G, H, M matches its period. When configured as an input, the TIM0 pin can be used to
provide the clock source for Timer 0 (external clock source mode) or it can be used
to start/stop the timer from counting (clock gating mode). This pin can also be used
as general-purpose I/O. The TIM0 pin is configured as an input after reset.
Input/Output pin for Timer 1. The TIM1 pin can be configured as an output or an
input via the Timer Signal Selection Register (TSSR). When configured as an
output, the TIM1 pin can signal a pulse or a change of state when the Timer 1 count
F, G, H, M matches its period. When configured as an input, the TIM1 pin can be used to
provide the clock source for Timer 1 (external clock source mode) or it can be used
to start/stop the timer from counting (clock gating mode). This pin can also be used
as general-purpose I/O. The TIM1 pin is configured as an input after reset.
Supply Pins
VSS
S
S
S
Digital Ground.Dedicated ground for the device.
Digital Power, + VDD. Dedicated power supply for the core CPU.
Digital Power, + VDD. Dedicated power supply for the PLL module.
No Connect
CVDD
PVDD
NC
DVDD
S
Digital Power, + VDD. Dedicated power supply for the I/O pins.
Test Pins
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with
a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and
TDI are clocked into the TAP controller, instruction register, or selected test data
register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
TCK
I
C, J
on the falling edge of TCK. Refer to Section 3.18, Notice Concerning TCK, for
important information regarding this pin.
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is
clocked into the selected register (instruction or data) on a rising edge of TCK.
TDI
I
O/Z
I
J
IEEE standard 1149.1 test data output. The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the
high-impedance state except when the scanning of data is in progress.
TDO
TMS
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial
control input is clocked into the TAP controller on the rising edge of TCK.
J
Introduction
31
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 2-4. Signal Descriptions (continued)
PIN
NAME
MULTIPLEXED
SIGNAL NAME
PIN
OTHER(2)
FUNCTION
TYPE(1)
IEEE standard 1149.1 test reset.TRST, when high, gives the IEEE standard
1149.1 scan system control of the operations of the device. If TRST is not
connected or driven low, the device operates in its functional mode, and the IEEE
standard 1149.1 signals are ignored. Pin has an internal pulldown device.
TRST
I
C, L, K
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the
OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from
the emulator system and is defined as I/O by way of the IEEE standard 1149.1 scan
system.
The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not
connected. Internal pullups have been included for the purpose. If the user chooses
to disable these pullups through the XBCR, external pullup resistors must be added
to these two pins.
EMU0
I/O/Z
J
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used
as an interrupt to or from the emulator system and is defined as I/O by way of IEEE
standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured
as OFF. The EMU1/OFF signal, when active (low), puts all output drivers into the
high-impedance state. Note that OFF is used exclusively for testing and emulation
purposes (not for multiprocessing applications). Therefore, for the OFF condition, the
following apply:
EMU1/OFF
I/O/Z
J
•
•
•
TRST = low,
EMU0 = high,
EMU1/OFF = low
The EMU0 and EMU1/OFF pins must be pulled up when an emulator is not
connected. Internal pullups have been included for the purpose. If the user chooses
to disable these pullups through the XBCR, external pullup resistors must be added
to these two pins.
32
Introduction
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3-1.
TCK
C55x CPU
ECLKIN
TMS
ECLKOUT1
ECLKOUT2
EMIFCLKS
Data
TDI
TDO
Instruction Buffer
Unit (IU)
Program Flow
Unit (PU)
Address Data Flow
Unit (AU)
Emulation Control
Computation
Unit (DU)
TRST
EMU0
EMU1/OFF
Program Address Bus [PAB] (24)
External
Memory
Interface
(EMIF)
Program Data Bus [PB] (32)
Data Read Address Bus B [BAB] (24)
Data Read Bus B [BB] (16)
A[21:2]
D[31:0]
C[15:0]
A[21:2]
D[31:0]
C[15:0]
Parallel
Port MUX
Data Read Address Bus C [CAB] (24)
Data Read Bus C [CB] (16)
Data Read Address Bus D [DAB] (24)
Data Read Bus D [DB] (16)
Data Write Address Bus E [EAB] (24)
Data Write Bus E [EB] (16)
PGPIO[35:0]
PGPIO[45:36]
Data Write Address Bus F [FAB] (24)
Data Write Bus F [FB] (16)
HD[7:0]
Host Port
MUX
Parallel
General−
HC0
HC1
Purpose I/O
Instruction
TIM
Timer
XPORT
DARAM
MPORT
ROM
DPORT
Cache
HA[15:0]
HD[15:0]
HAS
HBIL
X1
X2/CLKIN
CLKOUT
Clock Generator
IPORT
HCNTL0
HCNTL1
HCS
Host−Port
Interface (HPI)
HR/W
Peripheral
Controller
HDS1
Internal Memory
Interface
Power
Management
HDS2
HRDY
HINT
EMIF
DMA
Controller
Timer 3
(DSP/BIOS Timer)
HPIENA
DARAM0
DARAM1
PERI
WDTimer
NMI
General−Purpose
I/O
Muxing
Logic
NMI/WDTOUT
INT3
INT3
McBSP2
TX
UART
RX
Interrupt
Control
I2C
McBSP
RESET
RESET
INT[2:0]
INT[2:0]
SCL
SDA
Serial Port 2 MUX
(A) HD[15:8] are not used when the HPI is operated in
multiplexedmode.
SP0
SP1
SP2
SP3
Figure 3-1. TMS320VC5502 Functional Block Diagram
Functional Overview
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3.1 Memory
The 5502 supports a unified memory map (program and data accesses are made to the same physical
space). The total on-chip memory is 48K words (32K 16-bit words of RAM and 16K 16-bit words of ROM).
3.1.1 On-Chip ROM
TMS320VC5502 incorporates 16K x16-bit of on-chip, one-wait-state maskable ROM that can be mapped
into program memory space. The on-chip ROM is located at the byte address range FF8000h–FFFFFFh
when MPNMC = 0 at reset. When MPNMC = 1 at reset, the on-chip ROM is disabled and not present in
the memory map, and byte address range FF8000h–FFFFFFh is directed to external memory space.
MPNMC is a bit located in the ST3 status register, and its status is determined by the logic level on the
BOOTM[2:0] pins when sampled at reset. If BOOTM[2:0] are set to 00h or 04h at reset, the MPNMC bit is
set to 1 and the on-chip ROM is disabled; otherwise, the MPNMC bit is cleared to 0 and the on-chip ROM
is enabled. These pins are not sampled again until the next hardware reset. The software reset instruction
does not affect the MPNMC bit. Software can be used to set or clear the MPNMC bit.
The ROM can be accessed by the program bus (P) and the two read data buses (C and D). The on-chip
ROM is a two-cycle-per-word memory access, except for the first word access, which requires four cycles.
The standard on-chip ROM contains a bootloader which provides a variety of methods to load application
code automatically after power up or a hardware reset. For more information, see Section 3.1.5, Boot
Configuration. A vector table associated with the bootloader is also contained in the ROM. A boot mode
branch table is included in the ROM which contains hard-coded jumps to the beginning of each boot mode
code section in the bootloader.
A sine look-up table is provided containing 256 values (crossing 360 degrees) expressed in Q15 format.
The standard on-chip ROM layout is shown in Table 3-1.
Table 3-1. On-Chip ROM Layout
STARTING BYTE ADDRESS
FF_8000h
CONTENTS
Bootloader Program
FF_ECAEh
Bootloader Revision Number
Boot Mode Branch Table
Sine Table
FF_ECB0h
FF_ED00h
FF_EF00h
Reserved
FF_FF00h
Interrupt Vector Table
34
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3.1.2 On-Chip Dual-Access RAM (DARAM)
TMS320VC5502 features 32K x 16-bit (64K bytes) of on-chip dual-access RAM. This memory enhances
system performance, since the C55x CPU can access a DARAM block twice per machine cycle. The
DARAM is composed of 8 blocks of 4K x 16-bit each (see Table 3-2). Each block in the DARAM can
support two reads in one cycle, a read and a write in one cycle, or two writes in one cycle. The
dual-access RAM is located in the (byte) address range 000000h-00FFFFh, it can be accessed by the
program, data and DMA buses. The HPI has NO access to the DARAM block when device is in reset.
Table 3-2. DARAM Blocks
BYTE ADDRESS RANGE
000000h – 001FFFh
002000h – 003FFFh
004000h – 005FFFh
006000h – 007FFFh
008000h – 009FFFh
00A000h – 00BFFFh
00C000h – 00DFFFh
00E000h – 00FFFFh
MEMORY BLOCK
DARAM 0
DARAM 1
DARAM 2
DARAM 3
DARAM 4
DARAM 5
DARAM 6
DARAM 7
3.1.3 Instruction Cache
On the TMS320VC5502, instructions may reside in internal memory or external memory. When
instructions reside in external memory, the I-Cache can improve the overall system performance by
buffering the most recent instructions accessed by the CPU.
The 5502 includes a 16K-byte instruction cache, which consists of a single 2-way cache block. The 2-way
cache uses 2-way associative mapping and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit
words per line. In the 2-way cache, each line is identified by a unique tag. The 2-way cache is updated
based on a least-recently-used algorithm.
Control bits in the CPU status register ST3_55 provide the ability to enable, freeze, and flush the cache.
For more information on the instruction cache, see the TMS320VC5501/5502 DSP Instruction Cache
Reference Guide (literature number SPRU630).
Functional Overview
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3.1.4 Memory Map
Byte Address
Byte Address
000000h
000000h
DARAM0
(8K Bytes)
DARAM0
(8K Bytes)
002000h
DARAM1
002000h
DARAM1
(8K Bytes)
(8K Bytes)
004000h
DARAM2
004000h
006000h
008000h
DARAM2
(8K Bytes)
(8K Bytes)
006000h
DARAM3
(8K Bytes)
DARAM3
(8K Bytes)
008000h
DARAM4
DARAM4
(8K Bytes)
(8K Bytes)
00A000h
DARAM5
00A000h
DARAM5
(8K Bytes)
(8K Bytes)
00C000h
DARAM6
00C000h
00E000h
DARAM6
(8K Bytes)
(8K Bytes)
00E000h
DARAM7
DARAM7
(8K Bytes)
(8K Bytes)
010000h
010000h
400000h
External CE0 Space
(A,C)
External CE0 Space
(4M minus 64K Bytes
(A,C)
(4M minus 64K Bytes
)
)
400000h
External CE1 Space
(C)
External CE1 Space
(C)
(4M Bytes
)
(4M Bytes
)
800000h
C00000h
800000h
C00000h
External CE2 Space
(C)
External CE2 Space
(C)
(4M Bytes
)
(4M Bytes
)
External CE3 Space
(B,C)
(4M minus 32K Bytes
)
External CE3 Space
(C)
(4M Bytes
)
FF8000h
ROM
(32K Bytes)
MPNMC = 0
MPNMC = 1
(A)
(B)
(C)
The 64K bytes are the on-chip DARAM block.
The 32K bytes are for on-chip ROM block.
The CE space size shown in the figure represents the maximum addressable memory space for a 32-bit EMIF configuration. The
maximum addressable memory space per CE is reduced when 16- or 8-bit EMIF configurations are used for asynchronous and
SBSRAM memory types. For more detailed information, refer to TMS320VC5501/5502 DSP External Memory Interface (EMIF) Ref-
erence Guide (literature number SPRU621).
Figure 3-2. TMS320VC5502 Memory Map
36
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3.1.5 Boot Configuration
The on-chip bootloader provides a way to transfer application code and tables from an external source to
the on-chip RAM at power up. The 5502 provides several options to download the code to accommodate
varying system requirements. These options include:
•
•
•
•
•
•
•
Host-port interface (HPI) boot, both in multiplexed and non-multiplexed modes
External memory boot (via EMIF) from 16-bit asynchronous memory
Serial port boot (from McBSP0) with 16-bit element length
SPI EPROM boot (from McBSP0) supporting EPROMs with 24-bit addresses
I2C EPROM boot (from I2C) supporting EPROMs larger than 512K bits
UART boot
Direct execution (no boot) from 16- or 32-bit external asynchronous memory
The external pins BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of
BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM2 is shared with GPIO2,
BOOTM1 is shared with GPIO1, and BOOTM0 is shared with GPIO0.
The boot configurations available are summarized in Table 3-3.
Table 3-3. Boot Configuration Selection Via the BOOTM[2:0] Pins
BOOTM[2:0]
000
BOOT PROCESS
Direct execution from 16-bit external asynchronous memory
SPI EPROM boot
001
010
Serial port boot (from McBSP0)
011
External memory boot (via EMIF) from 16-bit asynchronous memory
Direct execution from 32-bit external asynchronous memory
HPI boot
100
101
110
I2C EPROM boot
111
UART boot
3.2 Peripherals
The 5502 includes the following on-chip peripherals:
(1)
•
An external memory interface (EMIF)
–
Supporting a 32-bit interface to asynchronous memory, SDRAM, and SBSRAM
•
A host-port interface (HPI) (1)
–
Configurable to 8 bits (multiplexed mode) or 16 bits (non-multiplexed mode)
•
•
•
•
•
A six-channel direct memory access (DMA) controller
Three multichannel buffered serial ports (McBSPs)
A programmable analog phase-locked loop (APLL) clock generator
General-purpose I/O (GPIO) pins and a dedicated output pin (XF)
Four timers
–
–
–
Two 64-bit general-purpose timers
A programmable watchdog timer
A DSP/BIOS timer
•
An Inter-integrated Circuit (I2C) multi-master and slave interface
(1) The 5502 can be configured as follows:
–
–
32-bit external memory interface with 8-bit (multiplexed) host-port interface
no external memory interface with 16-bit (non-multiplexed) host-port interface
Functional Overview
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
•
A Universal Asynchronous Receiver/Transmitter (UART)
For detailed information on the C55x DSP peripherals, see the following documents:
•
•
•
TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)
TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)
TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide
(literature number SPRU146)
•
•
TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)
TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature
number SPRU613)
•
•
•
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Refer-
ence Guide (literature number SPRU592)
TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number
SPRU621)
TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide
(literature number SPRU597)
3.3 Configurable External Ports and Signals
A number of pins on the 5502 have two functions, a feature that allows system designers to choose an
appropriate media interface for his/her application without the need for a large pin-count package. Three
muxes are included in the 5502 to control the configuration of these dual-function pins: the Parallel Port
Mux, the Host Port Mux, and the Serial Port 2 Mux. The state of these muxes is set at reset based on the
state of the GPIO6 and GPIO7 pins. The External Bus Selection Register (XBSR) reflects the
configuration of these muxes after the 5502 comes out of reset.
3.3.1 Parallel Port Mux
The Parallel Port Mux of the 5502 controls the function of 20 address signals (pins A[21:2]), 32 data
signals (pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two
different modes:
•
Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed
to their corresponding pins on the Parallel Port Mux.
•
Non-multiplexed HPI mode: The HPI is enabled with its 16 address, 16 data, and 9 control signals
routed to their corresponding pins on the Parallel Port Mux. Moreover, 16 control signals, 4 address
signals, and 16 data signals of the Parallel Port Mux that are not needed for HPI operation are set to
general-purpose I/O (PGPIO).
The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low,
the EMIF will be disabled and the HPI will be enabled in non-multiplexed mode: pins A[17:2] are set to
HPI.HA[15:0] and pins D[15:0] are set to HPI.HD[15:0]. All address, data, and control signals in the
Parallel Port Mux not needed by the HPI are set to parallel general-purpose I/O. The Parallel/Host Port
Mux Mode bit field in the External Bus Selection Register (XBSR) will also be set to 0 to reflect the
non-multiplexed HPI mode of the Parallel Port Mux.
If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled:
pins A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF[31:0], and pins C[15:0] are set to their
corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to
reflect the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the
HD[7:0] pins to strobe in address and data information (see Section 3.8, Host-Port Interface (HPI), for
more information on the operation of the HPI in multiplexed and non-multiplexed modes).
Table 3-4 lists the individual routing of the EMIF, PGPIO, and HPI signals to the external parallel address,
data, and control buses.
38
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Table 3-4. TMS320VC5502 Routing of Parallel Port Mux Signals
PARALLEL/HOST PORT MUX MODE = 0
(HPI NON-MULTIPLEX)
PARALLEL/HOST PORT MUX MODE = 1
(FULL EMIF)
PIN
Address Bus
HPI.HA[15:0]
PGPIO[3:0]
Data Bus
A[17:2]
EMIF.A[17:2]
EMIF.A[21:18]
A[21:18]
D[15:0]
HPI.HD[15:0]
PGPIO[19:4]
Control Bus
PGPIO20
EMIF.D[15:0]
EMIF.D[31:16]
D[31:16]
C0
C1
EMIF.ARE/SADS/SDCAS/SRE
EMIF.AOE/SOE/SDRAS
EMIF.AWE/SWE/SDWE
EMIF.ARDY
PGPIO21
C2
PGPIO22
C3
PGPIO23
C4
PGPIO24
EMIF.CE0
C5
PGPIO25
EMIF.CE1
C6
PGPIO26
EMIF.CE2
C7
PGPIO27
EMIF.CE3
C8
PGPIO28
EMIF.BE0
C9
PGPIO29
EMIF.BE1
C10
C11
C12
C13
C14
C15
PGPIO30
EMIF.BE2
PGPIO31
EMIF.BE3
PGPIO32
EMIF.SDCKE
EMIF.SOE3
PGPIO33
PGPIO34
EMIF.HOLD
PGPIO35
EMIF.HOLDA
3.3.2 Host Port Mux
The 5502 Host Port Mux controls the function of 8 data signals (pins HD[7:0]) and 2 control signals (pins
HC0 and HC1). The Host Port Mux supports two different modes:
•
8-bit multiplexed mode: The HPI's 8 data and 2 control signals are routed to their corresponding pins
on the Host Port Mux.
•
Parallel general-purpose I/O mode: All pins on the Host Port Mux are routed to PGPIO. The HPI is
enabled to 16-bit (non-multiplexed) mode, but communicates through the Parallel Port Mux.
The mode of the Host Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the
pins of the Host Port Mux will be set to PGPIO. The HPI will still be enabled, but it will communicate
through the Parallel Port Mux. The Parallel/Host Port Mux Mode bit of the External Bus Control Register
will be set to 0 to reflect the PGPIO mode of the Host Port Mux.
If GPIO6 is high, the HPI will be enabled in 8-bit (multiplexed) mode: pins HD[7:0] are set to HPI.HD[7:0],
and HC0 and HC1 are set to HPI.HAS and HPI.HBIL, respectively. The Parallel/Host Port Mux Mode bit
field in the XBSR will be set to 1 to reflect the HPI multiplexed mode of the Host Port Mux. See
Section 3.8, Host-Port Interface (HPI), for more information on the operation of the HPI in multiplexed and
non-multiplexed modes.
Table 3-5 lists the individual routing of the HPI and PGPIO signals to the Host Port Mux pins.
Functional Overview
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Table 3-5. TMS320VC5502 Routing of Host Port Mux Signals
PARALLEL/HOST PORT MUX MODE = 0
(PGPIO)
PARALLEL/HOST PORT MUX MODE = 1
(8-BIT HPI MULTIPLEXED)
PIN
Data Bus
PGPIO[43:36]
Control Bus
HD[7:0]
HPI.HD[7:0]
HC0
HC1
PGPIO44
PGPIO45
HPI.HAS
HPI.HBIL
3.3.3 Serial Port 2 Mux
The 5502 has three serial ports: McBSP0, McBSP1, and McBSP2, each of which has six signals. The
signals for McBSP0 and McBSP1 are directly routed to pins on the 5502. Four of the pins for McBSP2 are
multiplexed with two pins of the on-chip UART and two pins of the GPIO, the mode of the Serial Port 2
Mux determines which signals are routed to the 5502 pins.
The mode of the Serial Port 2 Mux is determined by the state of the GPIO7 pin at reset. If GPIO7 is low,
the UART is enabled and its RX and TX pins are routed to the SP1 and SP3 pins, respectively. The
GPIO3 and GPIO5 pins are routed to the SP0 and SP2 pins, respectively. In this mode, McBSP2 will be
disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the
Time-Out Control Register is set to 1.
If GPIO7 is high, McBSP2 will be enabled and its CLKX2, CLKR2, FSX2, and FSR2 signals will be routed
to the SP0, SP1, SP2, and SP3 pins, respectively. In this mode, the UART will be disabled and any writes
or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register
is set to 1. GPIO3 and GPIO5 will not be available during this mode of the Serial Port 2 Mux.
Table 3-6 lists the individual routing of the McBSP2, UART, and GPIO signals to the Serial Port 2 Mux
pins.
Table 3-6. TMS320VC5502 Routing of Serial Port 2 Mux Signals
PIN
SP0
SP1
SP2
SP3
SERIAL PORT 2 MUX MODE = 0
SERIAL PORT 2 MUX MODE = 1
GPIO3
UART.TX
GPIO5
CLKX2
CLKR2
FSX2
UART.RX
FSR2
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3.3.4 External Bus Selection Register (XBSR)
The External Bus Selection Register controls the mode of the Parallel Port Mux, Host Port Mux, and the
Serial Port 2 Mux. The Parallel Port Mux can be configured to support the 32-bit EMIF or to support the
HPI in 16-bit (non-multiplexed) mode and parallel general-purpose I/O. The Host Port Mux can be
configured to support the HPI in 8-bit (multiplexed) mode or parallel general-purpose I/O (PGPIO). The
Serial Port 2 Mux can be configured to support either the McBSP2 or the UART and general-purpose I/O.
The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the
GPIO6 pin at reset. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the
32-bit EMIF and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When
GPIO6 is low at reset, the Parallel Port Mux will be configured to support the HPI in 16-bit
(non-multiplexed) mode and parallel general-purpose I/O (PGPIO) and the Host Port Mux will be
configured to support parallel general-purpose I/O. The Paralle/Host Port Mux Mode bit of the XBSR will
(1)
reflect the mode selected for the Parallel and Host Port Muxes.
The XBSR configures the Serial Port 2 Mux based on the state of the GPIO7 pin at reset. When GPIO7 is
high at reset, the Serial Port 2 Mux will be configured to support the McBSP2. When GPIO7 is low at
reset, the Serial Port 2 Mux will be configured to support the UART and general-purpose I/O (PGPIO). The
Serial Port 2 Mux Mode bit of the XBSR will reflect the mode selected for the Serial Port 2 Mux. (1)
The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are
not selected through the External Bus Selection Register. Note that any accesses to disabled modules will
result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.
(1) Modifying the XBSR to change the mode of the Parallel Port Mux, Host Port Mux, and Serial Port 2 Mux after the 5502 has been
brought out of reset is not supported.
15
7
8
Reserved
R, 00000000
4
3
2
1
0
Serial Port 2
Mux Mode
Parallel /Host
Port Mux Mode
Reserved
R, 0000
Reserved(1)
Reserved
R/W, 0
R/W, GPIO7
R, 0
R/W, GPIO6
LEGEND: R = Read, W = Write, n = value at reset
(1) This reserved bit must be kept as zero during any writes to XBSR.
Figure 3-3. External Bus Selection Register Layout (0x6C00)
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Table 3-7. External Bus Selection Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-4
3
ACCESS
R
RESET VALUE
DESCRIPTION
000000000000 Reserved
Reserved
R/W
0
Reserved. This reserved bit must be kept as zero during any writes
to XBSR.
Serial Port 2 Mux
Mode
2
R/W
GPIO7
Serial Port 2 Mux Mode bit. Determines the mode of the third serial
port.
•
•
Serial Port 2 Mux Mode = 0:
The Serial Port 2 Mux is configured to support the UART and
GPIO. In this mode, the UART is enabled and its two signals
are routed to the corresponding pins on the Serial Port 2 Mux.
GPIO3 and GPIO5 are also routed to their corresponding pins
on the Serial Port 2 Mux.
Serial Port 2 Mux Mode = 1:
The Serial Port 2 Mux is configured to support the McBSP2. In
this mode, the McBSP2 is enabled and its six signals are routed
to their corresponding pins on the Serial Port 2 Mux.
Reserved
1
0
R
0
Reserved
Parallel/Host Port
Mux Mode
R/W
GPIO6
Parallel/Host Port Mux Mode bit. Determines the mode of the
Parallel Port Mux and the Host Port Mux.
•
Parallel/Host Port Mux Mode = 0:
The Parallel Port Mux is configured to support the HPI in 16-bit
(non-multiplexed) mode and PGPIO. In this mode, the HPI is
enabled and its 16 address, 16 data, and 9 control signals are
routed to their corresponding pins on the Parallel Port Mux. The
rest of the pins are routed to PGPIO. The EMIF cannot be used
in this mode.
The Host Port Mux is configured to support PGPIO. In this
mode, the Host Port Mux pins will be routed to PGPIO.
•
Parallel/Host Port Mux Mode = 1:
The Parallel Port Mux is configured to support the 32-bit EMIF.
In this mode, the EMIF is enabled and its 20 address, 32 data,
and 16 control signals are routed to their corresponding pins on
the Parallel Port Mux.
The Host Port Mux is configured to support the HPI in 8-bit
(multiplexed) mode. In this mode, the HPI is enabled and its
eight data/address and two control signals are routed to their
corresponding pins on the Host Port Mux.
42
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3.4 Configuration Examples
Figure 3-4 and Figure 3-5 illustrate example configurations for the 5502 based on the state of GPIO6 and
GPIO7 at reset.
32
D[31:0]
X2/CLKIN
Clock
ARDY, HOLD, ECLKIN, EMIFCLKS
EMIF
Generator
CLKOUT, X1
A[21:2], ECLKOUT1, ECLKOUT2,
ARE/SADS/SDCAS/SRE,
AOE/SOE/SDRAS,
AWE/SWE/SDWE, CE[3:0],
BE[3:0], SDCKE, SOE3, HOLDA
TIM0
PGPIO
TIMER0
HD[7:0], HCNTL0, HCNTL1, HCS,
HR/W
HPI
(8-Bit
Multiplexed
Mode)
TIM1
TIMER1
HAS, HBIL, HDS1, HDS2, HPIENA
HINT, HRDY
CLKR0, FSR0, CLKX0, FSX0
McBSP0
McBSP1
McBSP2
UART
DR0
DX0
WD Timer
CLKR1, FSR1, CLKX1, FSX1
TIMER3
(DSP/BIOS
Timer)
DR1
DX1
CLKR2, FSR2, CLKX2, FSX2
GPIO[7:6, 4, 2:0]
XF
DR2
DX2
GPIO
2
SCL, SDA
I C
(A)
NMI/WDTOUT
Interrupt
Control
INT[3:0], RESET
IACK
Shading denotes a peripheral module not available for this configuration.
(A ) The NMI/WDTOUT pin has NMI function by default, but can be set to WDTOUT through the TSSR.
Figure 3-4. Configuration Example A
(GPIO6 = 1 and GPIO7 = 1 at Reset)
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X2/CLKIN
Clock
EMIF
Generator
CLKOUT, X1
46
TIM0
PGPIO
PGPIO[45:0]
TIMER0
HA[15:0], HD[15:0], HCNTL0,
HCNTL1, HCS, HR/W
HPI
(16-Bit
Non-Multiplexed
Mode)
TIM1
TIMER1
HDS1, HDS2, HPIENA
HINT, HRDY
CLKR0, FSR0, CLKX0, FSX0
McBSP0
McBSP1
McBSP2
UART
DR0
DX0
WD Timer
CLKR1, FSR1, CLKX1, FSX1
TIMER3
(DSP/BIOS
Timer)
DR1
DX1
8
GPIO[7:0]
XF
GPIO
RX
TX
2
SCL, SDA
I C
(A)
NMI/WDTOUT
Interrupt
Control
INT[3:0], RESET
IACK
Shading denotes a peripheral module not available for this configuration.
(A ) The NMI/WDTOUT pin has NMI function by default, but can be set to WDTOUT through the TSSR.
Figure 3-5. Configuration Example B
(GPIO6 = 0 and GPIO7 = 0 at Reset)
3.5 Timers
The 5502 has four 64-bit timers: Timer 0, Timer 1, Watchdog Timer (WDT), and Timer 3. The first two
timers, Timer 0 and Timer 1, are mainly used as general-purpose timers. The third timer, the Watchdog
Timer, can be used as either a general-purpose timer or a watchdog timer. The fourth timer is reserved as
a DSP/BIOS counter; users have no access to this timer.
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Each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively.
Timer 0, Timer 1, and the Watchdog Timer are each assigned a pin: TIM0 pin is assigned to Timer 0,
TIM1 is assigned to Timer 1, and NMI/WDTOUT is used by the Watchdog Timer. The input (TIN) or output
(TOUT) signal of Timer 0, Timer 1, and the Watchdog Timer can be connected to their respective pins via
the Timer Signal Selection Register (TSSR).
The DSP/BIOS timer input, output, and interrupt signals are not internally connected. No interrupts are
needed from this timer; therefore, the timer interrupt signal is not internally connected to the CPU interrupt
logic.
The interrupt signal (TINT) of the Watchdog Timer can be internally connected to the NMI, RESET, and
INT3 signals via the TSSR.
Note that the NMI/WDTOUT pin has a dual function: Watchdog Timer pin and NMI input pin. The function
of the NMI/WDTOUT pin can be selected through the TSSR.
For more information on the 5502 timers, see the TMS320VC5501/5502 DSP Timers Reference Guide
(literature number SPRU618).
3.5.1 Timer Interrupts
As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT,
respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of
the DSP (see Figure 3-6). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or
disabled through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting
TINT0 of IER0 to '1' enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for
Timer 1.
TMS320VC5502 DSP
Interrupt Logic
RESET
INT3
NMI
TINT1
TINT0
Timer0
TINT
10
Others
Timer1
TINT
Watchdog
Timer
01
11
10
TINT
IWCON
RESET
INT3
NMI/WDTOUT
Figure 3-6. Timer Interrupts
Functional Overview
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The interrupt signal for the Watchdog Timer can be internally connected to the RESET, INT3, or NMI
signals by setting the IWCON bit of the Timer Signal Selection Register (TSSR) appropriately (see
Figure 3-6). The DSP will be reset once the Watchdog Timer generates an interrupt if the timer interrupt is
connected to RESET (IWCON = '01'). A non-maskable interrupt will be generated if the timer interrupt is
connected to NMI (IWCON = '10'). An external interrupt will be generated when the timer interrupt signal is
connected to INT3 (IWCON = '11'), but only if the INT3 bit of IER0 is set to '1'.
Refer to Section 3.17, Interrupts, for more information on using interrupts.
3.5.2 Timer Pins
The 5502 has one pin for each timer: TIM0 for Timer 0, TIM1 for Timer 1, and NMI/WDTOUT for the
Watchdog Timer. Either the output (TOUT) or input (TIN) signal can be connected to the timer pin (see
Figure 3-7). When the timer pin is configured as an output, the TOUT signal is connected to the pin. The
TIN signal is connected to the pin when the pin is configured as an input. Each pin can be configured as
input or output through the Timer Signal Selection Register (TSSR) (bits TIM0_MODE, TIM1_MODE, and
WDT_MODE).
TMS320VC5502 DSP
TSSR
TIN
TIM0_MODE
Timer0
TOUT
TIM0
TIM1
TIN
TIM1_MODE
WDT_MODE
Timer1
TOUT
TIN
Watchdog
Timer
NMI/WDTOUT
TOUT
Figure 3-7. Timer Pins
When configured as input, the timer pin can be used to source an external clock to the timer. Also, when
the timer pin is configured as input and the timer is running off an internal clock, the timer pin can be used
to start or stop count of the timer (clock gating).
When the timer pin is configured as an output, the timer pin can signal a pulse (pulse mode) or a change
of state (clock mode) when the timer count matches its period.
The NMI/WDTOUT pin has two functions: Watchdog Timer pin or NMI pin. The NMI/WDTOUT_CFG bit of
the TSSR controls the function of this pin. It is possible to configure the NMI/WDTOUT pin as NMI
(NMI/WDTOUT_CFG = '1') and also connect the Watchdog Timer TINT signal to the NMI signal (IWCON
= '10'). In this case, the external NMI signal will be overridden by the TINT signal of the Watchdog Timer,
i.e., applying a signal to the NMI/WDTOUT pin will not generate the non-maskable interrupt NMI.
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Functional Overview
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Fixed-Point Digital Signal Processor
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For all three timers (Timer 0, Timer 1, and the Watchdog Timer), both the TIN and TOUT signals can be
used for general-purpose input/output. The timer pin must be configured for input to use the TIN signal as
general-purpose input/output. The timer pin can be configured as an input by setting the pin mode bit of
the Timer Signal Selection Register (TSSR) to '0'. The TOUT signal can be used as general-purpose
input/output if the timer pin is configured for output. The timer pin can be configured as an output by
setting the pin mode bit of the TSSR to '1'. The GPIO Enable Register (GPEN), GPIO Direction Register
(GPIODIR), and the GPIO Data Register (GPDAT) of each timer can be used to control the state of the
timer pins when used as general-purpose input/output.
3.5.3 Timer Signal Selection Register (TSSR)
The Timer Signal Selection Register (TSSR) controls several pin characteristics for Timer 0, Timer 1, and
the Watchdog Timer. The TSSR can be used to specify whether the pins of Timer 0, Timer 1, and the
Watchdog Timer are inputs or outputs. The TSSR also determines how the interrupt signal of the
Watchdog Timer is connected internally and sets the function for the NMI/WDTOUT pin of the 5502. By
default, all timer pins (TIM0, TIM1, and NMI/WDTOUT) are set as inputs, the interrupt signal of the
Watchdog Timer is not internally connected to anything, and the NMI/WDTOUT pin has the function of the
NMI signal.
15
8
Reserved
R, 00000000
7
6
5
4
3
2
1
0
NMI/WDTOUT_
CFG
Reserved
R, 00
WDT_MODE
TIM1_MODE
R/W, 0
TIM0_MODE
IWCON
R/W, 00
R/W, 0
R/W, 0
R/W, 1
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-8. Timer Signal Selection Register Layout (0x8000)
Table 3-8. Timer Signal Selection Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-6
5
ACCESS
R
RESET VALUE
0000000000
0
DESCRIPTION
Reserved
WDT_MODE
TIM1_MODE
TIM0_MODE
R/W
WDT pin mode
•
•
WDT_MODE = 0: WDTOUT pin is used as the timer input pin.
WDT_MODE = 1: WDTOUT pin is used as the timer output pin.
4
3
R/W
R/W
0
0
TIM1 pin mode
•
•
TIM1_MODE = 0: TIM1 pin is used as the timer input pin.
TIM1_MODE = 1: TIM1 pin is used as the timer output pin.
TIM0 pin mode
•
•
TIM0_MODE = 0: TIM0 pin is used as the timer input pin.
TIM0_MODE = 1: TIM0 pin is used as the timer output pin.
Functional Overview
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Table 3-8. Timer Signal Selection Register Bit Field Description (continued)
BIT NAME
IWCON
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
2:1
R/W
00
Internal WDT output signal connection
•
•
•
•
IWCON = 00:
Internal watchdog timer interrupt (TINT) signal has no internal
connection.
IWCON = 01:
Internal watchdog timer interrupt (TINT) signal has an internal
connection to RESET pin.
IWCON = 10:
Internal watchdog timer interrupt (TINT) signal has an internal
connection to NMI pin.(1)
IWCON = 11:
Internal watchdog timer interrupt (TINT) signal has an internal
connection to INT3 pin.
NMI/WDTOUT_CFG
0
R/W
1
NMI/WDTOUT configuration
•
NMI/WDTOUT_CFG = 0:
NMI/WDTOUT pin is used as the WDTOUT pin.
•
NMI/WDTOUT_CFG = 1:
NMI/WDTOUT pin is used as the NMI input pin.(1)
(1) If NMI/WDTOUT_CFG = 1 and IWCON = 10, only the WDTOUT signal will drive the NMI signal; the external source driving the
NMI/WDTOUT pin will be ignored.
3.6 Universal Asynchronous Receiver/Transmitter (UART)
The UART peripheral is based on the industry-standard TL16C550B asynchronous communications
element, which in turn, is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on
power up (character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550)
mode. This relieves the CPU of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes, including three additional bits of error
status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at
any time. The UART includes control capability and a processor interrupt system that can be configured to
minimize software management of the communications link.
The UART includes a programmable baud rate generator capable of dividing the CPU clock by divisors
from 1 to 65535 and producing a 16× reference clock for the internal transmitter and receiver logic.
The UART pins are multiplexed with the pins of McBSP2. The Serial Port 2 Mux determines which pins
are connected to the SP0, SP1, SP2, and SP3. If GPIO7 is low at reset, the Serial Port 2 Mux Mode bit in
the External Bus Selection Register (XBSR) will be set to 0 to indicate that the UART module is enabled.
In this mode, the TX and RX signals of the UART will be routed to the SP1 and SP3 pins, respectively. If
GPIO7 is high at reset, the Serial Port 2 Mux Mode bit will be set to 1 to indicate that the UART module is
disabled. In this mode, any reads or writes to the UART registers will result in bus errors if the PERITOEN
bit of the Time-Out Control Register is set to 1.
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Fixed-Point Digital Signal Processor
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S
e
l
e
c
t
8
8
Receiver
FIFO
8
Receiver
Shift
Register
8
RX
Data
Bus
Receiver
Buffer
Peripheral
Bus
signal
Buffer
Register
16
Receiver
Timing and
Control
Line
Control
Register
Divisor
Latch (LS)
16
Baud
Generator
Divisor
Latch (MS)
Transmitter
Timing and
Control
Line
Status
Register
8
8
Transmitter
FIFO
S
e
l
e
c
t
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
TX
signal
Modem
Control
Register
8
Control
Logic
Interrupt
Enable
Register
Interrupt/
Event
Control
Logic
8
8
Interrupt to CPU
Event to DMA controller
Interrupt
Identification
Register
Power and
Emulation
Control
FIFO
Register
Control
Register
Figure 3-9. UART Functional Block Diagram
Functional Overview
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3.7 Inter-Integrated Circuit (I2C) Module
The TMS320VC5502 also includes an I2C serial port for control purposes. Features of the I2C port include:
•
•
•
Compatibility with Philips' I2C-Bus Specification, Version 2.1 (January 2000)
Fast mode up to 400 Kbps (no fail-safe I/O buffers)
Noise filters (on the SDA and SCL pins) to suppress noise of 50 ns or less (I2C module clock must be
in the range of 7 MHz to 12 MHz)
•
•
•
•
7-bit and 10-bit device addressing modes
Master (transmit/receive) and slave (transmit/receive) functionality
Events: DMA, interrupt, or polling
Slew-rate limited open-drain output buffers
The I2C module clock must be in the range of 7 MHz to 12 MHz. This is necessary for the proper
operation of the I2C module.
NOTE
For
additional
information,
see
the
TMS320VC5501/5502/5503/5507/5509
DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146).
Figure 3-10 is a block diagram of the I2C module.
2
I C Module
Clock
SYSCLK2
Prescale
From PLL
Clock Generator
I2CPSC
Bit Clock
Generator
Control
SCL
Noise
Filter
Own
2
I C Clock
I2CCLKH
I2CCLKL
I2COAR
I2CSAR
I2CMDR
I2CCNT
Address
Slave
Address
Mode
Transmit
I2CXSR
Data
Count
Transmit
Shift
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIER
Noise
Filter
2
I C Data
Interrupt
Enable
Receive
I2CDRR
Receive
Buffer
Status
I2CSTR
Interrupt
Source
Receive
Shift
I2CRSR
I2CISRC
A. Shading denotes control/status registers.
Figure 3-10. I2C Module Block Diagram
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3.8 Host-Port Interface (HPI)
The 5502 HPI provides an interface to a host with the following features:
•
•
•
•
•
•
16-bit host address bus and 16-bit host data bus (non-multiplexed mode only)
Multiplexed and non-multiplexed modes
Host access to on-chip DARAM (excluding CPU memory-mapped registers)
16-bit address register with autoincrement capability for faster transfers
Multiple address/data strobes provide a glueless interface to a variety of hosts
HRDY signal for handshaking with host
The 5502 HPI can access the entire DARAM space of the 5502 (excluding memory-mapped CPU
registers); however, it does not have access to external memory of the peripheral I/O space. Furthermore,
the HPI cannot access internal DARAM space when the device is in reset. Note that all accesses made
through the HPI are word-addressed.
NOTE
No host access should occur when the HPI is placed in IDLE. The host cannot wake up
the DSP through the DSP_INT bit of the HPIC register when the DSP is in IDLE mode.
The 5502 HPI supports both multiplexed 8-bit and non-multiplexed 16-bit modes. One of these two modes
can be selected via the GPIO6 pin. At reset, if GPIO6 is low, the HPI non-multiplexed 16-bit mode is
enabled and some of the HPI signals can be used as GPIOs. If GPIO6 is high, the HPI can be used in
multiplexed 8-bit mode. Similarly, some of the HPI signals can be used as GPIOs. (See Section 3.3.2,
Host Port Mux, for more information on pin multiplexing for both modes of the HPI.)
When GPIO6 is low at reset, the 5502 HPI will be configured in non-multiplexed mode. In this mode, pins
A[17:2] and pins D[15:0] of the Parallel Port Mux will be set to HPI.HA[15:0] and HPI.HD[15:0],
respectively. In non-multiplexed mode, the host can read/write 16-bit data from the 5502's internal memory
by using the 16-bit address and data bus and the HPI control signals [see the TMS320VC5501/5502 DSP
Host Port Interface (HPI) Reference Guide (literature number SPRU620) for more information on the 5502
HPI]. Note that in this mode, the 5502 EMIF wil be disabled.
When GPIO6 is high at reset, the 5502 HPI will be configured in multiplexed mode. In this mode, pins
HD[7:0], HC0, and HC1 of the Host Port Mux will be set to HPI.HD[7:0], HPI.HAS, and HPI.HBIL,
respectively. In multiplexed mode, the host can only send 8 bits of data at a time through the HPI.HD[7:0]
bus; therefore, some extra steps have to be taken to read/write from the 5502's internal memory [see the
TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620) for
more information on the 5502 HPI]. Note that in this mode, the EMIF is fully enabled.
The 5502 HPI has its own register set, therefore the HINT bit of CPU register ST3_55 is not used for
DSP-to-host interrrupts. The HINT bit in the Host Port Control Register (HPIC) should be used for
DSP-to-host interrupts.
A host must not initiate any transfer requests from the HPI while the HPI is being brought out of reset. As
described in Section 3.10.6, Reset Sequence, the C55x CPU and the peripherals are not brought out of
reset immediately after the RESET pin transitions from low to high. Instead, an internal counter stretches
the reset signal to allow enough time for the internal oscillator to stabilize and also to allow the reset signal
to propagate through different parts of the device. The IACK pin will go low for two CPU clock cycles to
indicate that this internal reset signal has been deasserted. A host must follow one of these two
requirements before initiating transfer requests from the HPI:
1. Keep the HPIENA pin low until the internal reset signal has been deasserted.
2. Keep the HCS, HDS1, and HDS2 pins inactive until the internal reset signal has been deasserted.
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Note that when the HPI bootmode is used, the GPIO4 pin can also be used to determine when the internal
reset signal has been deasserted as this pin is used by the HPI to signal to the host that it is ready to
receive access requests.
3.9 Direct Memory Access (DMA) Controller
The 5502 DMA provides the following features:
•
Four standard ports for the following data resources: two for DARAM, one for Peripherals, and one for
External Memory
•
•
•
•
Six channels, which allow the DMA controller to track the context of six independent DMA channels
Programmable low/high priority for each DMA channel
One interrupt for each DMA channel
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of
selected events.
•
•
Programmable address modification for source and destination addresses
Idle mode that allows the DMA controller to be placed in a low-power (idle) state under software control
The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when
the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode
and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state
automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state
automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL
core should not be in power-down mode for the Auto-wakeup/Idle function to work.]
The 5502 DMA controller allows transfers to be synchronized to selected events. The 5502 supports
16 separate synchronization events and each channel can be tied to separate synchronization event
independent of the other channels. Synchronization events are selected by programming the SYNC field
in the channel-specific DMA Channel Control Register (DMA_CCR).
The 5502 DMA can access all the internal DARAM space as well as all external memory space. The 5502
DMA also has access to the registers for the following peripheral modules: McBSP, UART, GPIO, PGPIO,
and I2C.
3.9.1 DMA Channel 0 Control Register (DMA_CCR0)
The DMA Channel 0 Control Register (DMA_CCR0) bit layouts are shown in Figure 3-11. DMA_CCR1 to
DMA_CCR5 have similar bit layouts. See the TMS320VC5501/5502 DSP Direct Memory Access (DMA)
Controller Reference Guide (literature number SPRU613) for more information on the DMA Channel n
Control Register (n = 0, 1, 2, 3, 4, or 5).
15
14
13
12
11
10
9
8
DSTAMODE
R/W, 00
SRCAMODE
R/W, 00
ENDPROG
WP
REPEAT
AUTOINIT
R/W, 0
R/W, 0
R/W, 0
R/W, 0
0
7
6
5
4
EN
PRIO
FS
SYNC
R/W, 0
R/W, 0
R/W, 0
R/W, 00000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-11. DMA Channel 0 Control Register Layout (0x0C01)
The SYNC field (bits[4:0]) of the DMA_CCR register specifies the event that can initiate the DMA transfer
for the corresponding DMA channel. The five bits allow several configurations as listed in Table 3-9. The
bits are set to zero upon reset. For those synchronization modes with more than one peripheral listed, the
Serial Port 2 Mux Mode bit field of the External Bus Selection Register (XBSR) dictates which peripheral
event is actually connected to the DMA input.
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Table 3-9. Synchronization Control Function
SYNC FIELD IN
DMA_CCR
SYNCHRONIZATION MODE
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
No event synchronized
McBSP 0 Receive Event (REVT0)
McBSP 0 Transmit Event (XEVT0)
Reserved (Do not use this value)
Reserved (Do not use this value)
McBSP1 Receive Event (REVT1)
McBSP1 Transmit Event (XEVT1)
Reserved (Do not use this value)
Reserved (Do not use this value)
Reserved/McBSP Event
01001b
01010b
01011b
01100b
•
•
Serial Port 2 Mux Mode = 0: Reserved
Serial Port 2 Mux Mode = 1: McBSP2 Receive Event (REVT2)
Reserved/McBSP Event
•
•
Serial Port 2 Mux Mode = 0: Reserved
Serial Port 2 Mux Mode = 1: McBSP2 Transmit Event (XEVT2)
Reserved/UART Event
•
•
Serial Port 2 Mux Mode = 0: UART Receive Event (UARTREVT)
Serial Port 2 Mux Mode = 1: Reserved
Reserved/UART Event
•
•
Serial Port 2 Mux Mode = 0: UART Transmit Event (UARTXEVT)
Serial Port 2 Mux Mode = 1: Reserved
01101b
01110b
Timer 0 Event
Timer 1 Event
01111b
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
I2C Receive Event
I2C Transmit Event
Reserved (Do not use these values)
10000b
10001b
10010b
10011b
10100b
Other values
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3.10 System Clock Generator
The TMS320VC5502 includes a flexible clock generator module consisting of a PLL and oscillator, with several dividers so that different clocks
may be generated for different parts of the system (i.e., 55x core, Fast Peripherals, Slow Peripherals, External Memory Interface). Figure 3-12
provides an overview of the system clock generator included in the 5502.
GPIO4 at Reset = 0 −> CLKMD[0] = 0
GPIO4 at Reset = 1 −> CLKMD[0] = 1
GPIO4
CLKOSEL
at Reset
(CLKOUTSR[2:1])
CLKMD
(CLKMD[0])
CLKOUTDIS
(CLKOUTSR[0])
PLLEN
(PLLCSR[0])
CLKOUT
Divider D1
/1,/2,/4
0
SYSCLK1
(Fast Peripherals)
PLLOUT
Divider D0
/1,/2,...,/32
PLL
x2, x3,
ENA
1
1
PLLREF
X2/CLKIN
X1
D1EN (PLLDIV1[15])
Divider D2
OSCOUT
...,x15
OSC
0
ENA
/1,/2,/4
ENA
PWRDN
SYSCLK2
(Slow Peripherals)
D0EN
(PLLDIV0[15])
D2EN (PLLDIV2[15])
Divider D3
OSCPWRDN
(PLLCSR[2])
Divider OD1
/1,/2,...,/32
/1,/2,/4
ENA
SYSCLK3
ENA
(EMIF Internal Clock)
D3EN (PLLDIV3[15])
OD1EN
(OSCDIV1[15])
55x
Core
CLKOUT3
(DSP Core Clock)
CK3SEL (CK3SEL[3:0])
Clock Generator
ECLKIN
1
0
EMIFCLKS
EMIF
ECLKOUT1
ECLKOUT2
/1,/2,/4
Figure 3-12. System Clock Generator
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3.10.1 Input Clock Source
The clock input to the 5502 can be sourced from either an externally generated 3.3-V clock input on the
X2/CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device as shown
in Figure 3-13. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) determines which clock,
either OSCOUT or X2/CLKIN, is used as an input clock source to the DSP. If GPIO4 is low at reset, the
CLKMD0 bit of the Clock Mode Control Register (CLKMD) will be set to '0' and the internal oscillator and
the external crystal will generate the input clock to the DSP. If GPIO4 is high, the CLKMD0 bit will be set
to '1' and the input clock will be taken directly from the X2/CLKIN pin.
The input clock source to the DSP can be directly used to generate the clocks to other parts of the system
(Bypass Mode) or it can be multiplied by a value from 2 to 15 and divided by a value from 1 to 32 to
achieve a desired frequency (PLL Mode). The PLLEN bit of the PLL Control/Status Register (PLLCSR) is
used to select between the PLL and bypass modes of the clock generator.
The clock generated through either the PLL Mode or the Bypass Mode can be further divided down to
generate a clock source for other parts of the system, or Clock Groups. Clock groups allow for lower
power and performance optimization since the frequency of groups with no high-speed requirements can
be set to one-fourth or one-half the frequency of other groups. A description of the different clock groups
included in the 5502 and the procedure for changing the operating frequency for those clock groups are
described later in this section.
3.10.1.1 Internal System Oscillator With External Crystal
The 5502 includes an internal oscillator which can be used in conjunction with an external crystal to
generate the input clock to the DSP. The oscillator requires an external crystal connected across the X1
and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must be applied to the
X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be used as a
clock source to the PLL, the crystal oscillation frequency can be multiplied to generate the input clock to
the different clock groups of the DSP.
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective
series resistance (ESR) as specified in Table 3-10. The connection of the required circuit is shown in
Figure 3-13. Under some conditions, all the components shown are not required. The capacitors, C1 and
C2, should be chosen such that the equation below is satisfied. CL in the equation is the load specified for
the crystal that is also specified in Table 3-10.
C1C2
CL +
(C1 ) C2)
X2/CLKIN
X1
R
S
Crystal
C
1
C
2
Figure 3-13. Internal System Oscillator With External Crystal
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Table 3-10. Recommended Crystal Parameters
MAXIMUM ESR
SPECIFICATIONS (Ω)
MAXIMUM
CSHUNT (pF)
FREQUENCY RANGE (MHz)
CLOAD (pF)
RS (kΩ)
20-15
15-12
12-10
10-8
8-6
40
40
40
60
60
80
10
16
16
18
18
18
7
7
7
7
7
7
0
0
2.8
2.2
8.8
14
6-5
The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum
ESR might seem to meet these specifications. However, it is recommended that crystals with actual
maximum ESR specifications as shown in Table 3-10 be used since this will result in maximum crystal
performance reliability.
The internal oscillator can be set to power-down mode through the use of the OSCPWRDN bit in the PLL
Control/Status Register (PLLCSR). If the internal oscillator and the external crystal are generating the
input clock for the DSP (CLKMD0 = 0), the internal oscillator will be set to power-down mode when the
OSCPWRDN bit is set to 1 and the clock generator is set to its idle mode (CLKIS bit of the IDLE Status
Register (ISTR) becomes 1). If the X2/CLKIN pin is supplying the input clock to the DSP (CLKMD0 = 1),
the internal oscillator will be set to power-down immediately after the OSCPWRDN bit is set to 1.
The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032
reference clock cycles) to allow the oscillator input to become stable after waking up from power-down
state or after reset. If a reset is asserted, program flow will start after all stabilization periods have expired;
this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of
power-down mode, program flow will start immediately after the oscillator stabilization period has
completed. See Section 3.10.6, Reset Sequence, for more details on program flow after reset or after
oscillator power-down. See Section 3.11, Idle Control, for more information on the oscillator power-down
mode.
3.10.1.2 Clock Generation With PLL Disabled (Bypass Mode, Default)
After reset, the PLL multiplier (M1) and its divider (D0) will be bypassed by default and the input clock to
point C in Figure 3-14 will be taken from, depending on the state of the GPIO4 pin after reset, either the
internal oscillator or the X2/CLKIN pin. The PLL can be taken out of bypass mode as described in
Section 3.10.4.1, C55x Subsystem Clock Group.
3.10.1.3 Clock Generation With PLL Enabled (PLL Mode)
When not in bypass mode, the frequency of the input clock can be divided down by a programmable
divider (D0) by any factor from 1 to 32. The output clock of the divider can be multiplied by any factor from
2 to 15 through a programmable multiplier (M1). The divider factor can be set through the PLLDIV0 bit of
the PLL Divider 0 Register. The multiplier factor can be set through the PLLM bits of the PLL Multiplier
Control Register.
There is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the
block labeled "PLL" in Figure 3-12, as well as for the C55x Core clock (CLKOUT3), the Fast Peripherals
clock (SYSCLK1), the Slow Peripherals clock (SYSCLK2), and the EMIF internal clock (SYSCLK3). The
clock generator must not be configured to exceed any of these constraints (certain combinations of
external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 3-11 for
the PLL clock input and output frequency ranges.
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3.10.1.4 Frequency Ranges for Internal Clocks
There are specific minimum and maximum reference clocks for all of the internal clocks. Table 3-11 lists
the minimum and maximum frequencies for the internal clocks of the TMS320VC5502.
Table 3-11. Internal Clocks Frequency Ranges(1)
VC5502-200
VC5502-300
CLOCK SIGNAL
UNIT
MIN
MAX
20
MIN
MAX
20
OSCOUT (CLKMD = 0)
PLLREF (PLLEN = 1)
PLLOUT (PLLEN = 1)
CLKOUT3
5
12
70
–
5
12
70
–
MHz
MHz
MHz
MHz
MHz
MHz
MHz
100
100
200
300
200
300
SYSCLK1
–
150
–
150
SYSCLK2
–
SYSCLK1
SYSCLK1(2)
–
SYSCLK1
SYSCLK1(2)
SYSCLK3
–
–
(1) Also see the electrical specification (timing requirements and switching characteristics parameters) in Section 5.6, Clock Options, of this
data manual.
(2) When an internal clock is used for the EMIF module, the frequency for SYSCLK3 must also be less than or equal to 100 MHz. When an
external clock is used, the maximum frequency of SYSCLK3 can be equal to or less than the frequency of SYSCLK1; however, the
frequency of the clock signal applied to the ECLKIN pin must be less than or equal to 100 MHz.
3.10.2 Clock Groups
The TMS320VC5502 has four clock groups: the C55x Subsystem Clock Group, the Fast Peripherals Clock
Group, the Slow Peripherals Clock Group, and the External Memory Interface Clock Group. Clock groups
allow for lower power and performance optimization since the frequency of groups with no high-speed
requirements can be set to 1/4 or 1/2 the frequency of other groups.
3.10.2.1 C55x Subsystem Clock Group
The C55x Subsystem Clock Group includes the C55x CPU core, internal memory (DARAM and ROM), the
ICACHE, and all CPU-related modules. The input clock to this clock group is taken from the CLKOUT3
signal (as shown in Figure 3-12), the source of which can be controlled through the CLKOUT3 Select
Register (CK3SEL). The different options for the CLKOUT3 signal are intended for test purposes; it is
recommended that the CK3SEL bits of the CK3SEL register be kept at their default value of '1011b' during
normal operation. When operating the clock generator in PLL Mode, the frequency of CLKOUT3 can be
set by adjusting the divider and multiplier values of D0 and M1 through the PLLDIV0 and PLLM registers,
respectively.
3.10.2.2 Fast Peripherals Clock Group
The Fast Peripherals Clock Group includes the DMA, HPI, and the timers. The input clock to this clock
group is taken from the output of divider 1 (D1) (as shown in Figure 3-12). By default, the divider is set to
divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by
modifying the PLLDIV1 bits of the PLL Divider1 Register (PLLDIV1) through software.
3.10.2.3 Slow Peripherals Clock Group
The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken from the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group.
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3.10.2.4 External Memory Interface Clock Group
The External Memory Interface Clock Group includes the External Memory Interface (EMIF) module and
the external data bridge modules. The input clock to this clock group is taken from the output of divider 3
(D3). By default, the divider is set to divide its input clock by four, but the divide value can be changed to
divide-by-1 or divide-by-2 by modifying the PLLDIV3 bits of the PLL Divider3 Register (PLLDIV3) through
software. The clock frequency of the External Memory Interface Clock Group must be equal to or less than
that of the Fast Peripherals Clock Group.
3.10.3 EMIF Input Clock Selection
The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a
specific EMIF frequency is needed. The source for the EMIF clock can be specified through the
EMIFCLKS pin. If EMIFCLKS is low, then the EMIF will be clocked via the same internal clock that feeds
the data bridge module and performance will be optimal. If EMIFCLKS is high, then an external
asynchronous clock, which can be taken up to 100 MHz, will clock the EMIF. The data throughput
performance may be degraded due to synchronization issues when an external clock source is used for
the EMIF.
3.10.4 Changing the Clock Group Frequencies
DSP software can be used to change the clock frequency of each clock group by setting adequate values
in the PLL control registers. Figure 3-14 shows which PLL control registers affect the different portions of
the clock generator. The following sections describe the procedures for changing the frequencies of each
clock group.
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OSCOUT
0
Point A
Point B
Divider
D0
PLL Core
Multiplier M1
Point C
1
0
1
X2/CLKIN
CLKMD0
Divider
D1
SYSCLK1
SYSCLK2
SYSCLK3
Divider
D2
PLLEN
Divider
D3
CLKOUT3
Divider
OD1
PLLCSR
PLLM
PLLDIV0
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV1
CK3SEL
WKEN
Oscillator Power-Down Control
Figure 3-14. Clock Generator Registers
3.10.4.1 C55x Subsystem Clock Group
Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL
Multiplier Register (PLLM) affect the clock of this clock group. The following procedure must be followed to
change or to set the PLL to a specific value:
1. Switch to bypass mode by setting the PLLEN bit to 0.
2. Set the PLL to its reset state by setting the PLLRST bit to 1.
3. Change the PLL setting through the PLLM and PLLDIV0 bits.
4. Wait for 1 µs.
5. Release the PLL from its reset state by setting PLLRST to 0.
6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.
7. Switch back to PLL mode by setting the PLLEN bit to 1.
The frequency of the C55x Subsystem Clock Group can be up to 300 MHz for the TMS320VC5502-300
and up to 200 MHz for the TMS320VC5502-200.
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3.10.4.2 Fast Peripherals Clock Group
Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Fast Peripherals Clock
Group. The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that
makes the frequency for this clock group greater than 150 MHz. There must be no activity in the modules
included in the Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is
recommended that the fast peripheral modules be put in IDLE mode before changing the PLLDIV1 value.
3.10.4.3 Slow Peripherals Clock Group
Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock
Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that
makes the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast
Peripherals Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock
Group when the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules
be put in IDLE mode before changing the PLLDIV2 value.
3.10.4.4 External Memory Interface Clock Group
Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory
Interface Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a
manner that makes the frequency for this clock group greater than 100 MHz or greater than the frequency
of the Fast Peripherals Clock Group, whichever is smaller. If an external clock is used, the clock on the
ECLKIN pin can be up to 100 MHz and the output of divider 3 can be set equal to or lower than the
frequency of the Fast Peripherals Clock Group. There must be no external memory accesses when the
value of PLLDIV3 is being changed, this means that the value of PLLDIV3 cannot be changed by a
program that is being executed from external memory. It is recommended that the EMIF be put in IDLE
mode before changing the PLLDIV3 value.
3.10.5 PLL Control Registers
The 5502 PLL control registers are accessible via the I/O memory map.
Table 3-12. PLL Control Registers
ADDRESS
1C80h
1C82h
1C88h
1C8Ah
1C8Ch
1C8Eh
1C90h
1C92h
1C98h
8400h
REGISTER
PLLCSR
CK3SEL
PLLM
PLLDIV0
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV1
WKEN
CLKOUTSR
CLKMD
8C00h
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3.10.5.1 PLL Control / Status Register (PLLCSR)
15
8
Reserved
R, 00000000
7
6
5
4
3
2
1
0
Reserved
STABLE
LOCK
Reserved
R, 0
PLLRST
OSCPWRDN
PLLPWRDN
PLLEN
R, 0
R, 1
R, 0
R/W, 1
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-15. PLL Control/Status Register Layout (0x1C80)
Table 3-13. PLL Control/Status Register Bit Field Description
BIT NAME
Reserved
STABLE
BIT NO.
15:7
6
ACCESS
RESET VALUE
000000000
1
DESCRIPTION
R
R
Reserved. Reads return 0. Writes have no effect.
Oscillator output stable. This bit indicates if the OSCOUT output has
stabilized.
•
STABLE = 0:
Oscillator output is not yet stable. Oscillator counter is not done
counting 41,032 reference clock cycles.
•
STABLE = 1:
Oscillator output is stable. This is true if any one of the three
cases is true:
a) Oscillator counter has finished counting.
b) Oscillator counter is disabled.
c) Test mode.
LOCK
5
R
0
Lock mode indicator. This bit indicates whether the clock generator
is in its lock mode.
•
LOCK = 0:
The PLL is in the process of getting a phase lock.
•
LOCK = 1:
The clock generator is in the lock mode. The PLL has a phase
lock and the output clock of the PLL has the frequency
determined by the PLLM register and PLLDIV0 register.
Reserved
PLLRST
4
3
R
0
1
Reserved. Reads return 0. Writes have no effect.
Asserts RESET to PLL
R/W
•
•
PLLRST = 0: PLL reset released
PLLRST = 1: PLL reset asserted
OSCPWRDN
2
R/W
0
Sets internal oscillator to power-down mode
•
OSCPWRDN = 0:
Oscillator operational
•
OSCPWRDN = 1:
Oscillator set to power-down mode based on state of CLKMD0
bit of Clock Mode Control Register (CLKMD).
–
When CLKMD0 = 0, the internal oscillator is set to
power-down mode when the clock generator is set to its idle
mode [CLKIS bit of the IDLE Status Register (ISTR)
becomes 1].
–
When CLKMD0 = 1, the internal oscillator is set to
power-down mode immediately after the OSCPWRDN bit is
set to 1.
PLLPWRDN
1
R/W
0
Selects PLL power down
•
•
PLLPWRDN = 0: PLL operational
PLLPWRDN = 1: PLL placed in power-down state
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Table 3-13. PLL Control/Status Register Bit Field Description (continued)
BIT NAME
PLLEN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
0
R/W
0
PLL mode enable. This bit controls the multiplexer before dividers
D1, D2, and D3.
•
PLLEN = 0:
Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3
divided down directly from input reference clock.
•
PLLEN = 1:
PLL mode. Divider D1 and PLL are not bypassed. SYSCLK1
to 3 divided down from PLL output.
3.10.5.2 PLL Multiplier Control Register (PLLM)
15
8
Reserved
R, 00000000
7
5
4
0
Reserved
R, 000
PLLM
R/W, 00000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-16. PLL Multiplier Control Register Layout (0x1C88)
Table 3-14. PLL Multiplier Control Register Bit Field Description
BIT NAME
Reserved
PLLM
BIT NO.
15:5
ACCESS
R
RESET VALUE
00000000000
00000
DESCRIPTION
Reserved. Reads return 0. Writes have no effect.
PLL multiplier-select
4:0
R/W
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PLLM = 00000-00001: Reserved
PLLM = 00010: Times 2
PLLM = 00011: Times 3
PLLM = 00100: Times 4
PLLM = 00101: Times 5
PLLM = 00110: Times 6
PLLM = 00111: Times 7
PLLM = 01000: Times 8
PLLM = 01001: Times 9
PLLM = 01010: Times 10
PLLM = 01011: Times 11
PLLM = 01100: Times 12
PLLM = 01101: Times 13
PLLM = 01110: Times 14
PLLM = 01111: Times 15
PLLM = 10000–11111: Reserved
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3.10.5.3 PLL Divider 0 Register (PLLDIV0) (Prescaler)
This register controls the value of the PLL prescaler (Divider D0).
15
14
8
D0EN
Reserved
R/W, 1
7
R, 0000000
5
4
0
Reserved
R, 000
PLLDIV0
R/W, 00000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-17. PLL Divider 0 Register Layout (0x1C8A)
Table 3-15. PLL Divider 0 Register Bit Field Description
BIT NAME
D0EN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R/W
1
Divider D0 enable
•
•
D0EN = 0: Divider 0 disabled
D0EN = 1: Divider 0 enabled
Reserved
14:5
R
0000000000
Reserved. Reads return 0. Writes have no effect.
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Table 3-15. PLL Divider 0 Register Bit Field Description (continued)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
PLLDIV0
4:0
R/W
00000
Divider D0 ratio
PLLDIV0 = 00000: Divide by 1
PLLDIV0 = 00001: Divide by 2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PLLDIV0 = 00010: Divide by 3
PLLDIV0 = 00011: Divide by 4
PLLDIV0 = 00100: Divide by 5
PLLDIV0 = 00101: Divide by 6
PLLDIV0 = 00110: Divide by 7
PLLDIV0 = 00111: Divide by 8
PLLDIV0 = 01000: Divide by 9
PLLDIV0 = 01001: Divide by 10
PLLDIV0 = 01010: Divide by 11
PLLDIV0 = 01011: Divide by 12
PLLDIV0 = 01100: Divide by 13
PLLDIV0 = 01101: Divide by 14
PLLDIV0 = 01110: Divide by 15
PLLDIV0 = 01111: Divide by 16
PLLDIV0 = 10000: Divide by 17
PLLDIV0 = 10001: Divide by 18
PLLDIV0 = 10010: Divide by 19
PLLDIV0 = 10011: Divide by 20
PLLDIV0 = 10100: Divide by 21
PLLDIV0 = 10101: Divide by 22
PLLDIV0 = 10110: Divide by 23
PLLDIV0 = 10111: Divide by 24
PLLDIV0 = 11000: Divide by 25
PLLDIV0 = 11001: Divide by 26
PLLDIV0 = 11010: Divide by 27
PLLDIV0 = 11011: Divide by 28
PLLDIV0 = 11100: Divide by 29
PLLDIV0 = 11101: Divide by 30
PLLDIV0 = 11110: Divide by 31
PLLDIV0 = 11111: Divide by 32
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3.10.5.4 PLL Divider1 Register (PLLDIV1) for SYSCLK1
This register controls the value of the divider D1 for SYSCLK1. It is in both the BYPASS and PLL paths.
15
14
8
D1EN
Reserved
R/W, 1
7
R, 0000000
5
4
0
Reserved
R, 000
PLLDIV1
R/W, 00011
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-18. PLL Divider 1 Register Layout (0x1C8C)
Table 3-16. PLL Divider 1 Register Bit Field Description
BIT NAME
D1EN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R/W
1
Divider D1 enable
•
•
D1EN = 0: Divider 1 disabled
D1EN = 1: Divider 1 enabled
Reserved
PLLDIV1
14:5
4:0
R
0000000000
00011
Reserved. Reads return 0. Writes have no effect.
Divider D1 ratio (SYSCLK1 divider)
R/W
•
•
•
•
•
PLLDIV1 = 00000: Divide by 1
PLLDIV1 = 00001: Divide by 2
PLLDIV1 = 00010: Reserved
PLLDIV1 = 00011: Divide by 4
PLLDIV1 = 00100–11111: Reserved
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3.10.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2
This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths.
15
14
8
D2EN
Reserved
R/W, 1
7
R, 0000000
5
4
0
Reserved
R, 000
PLLDIV2
R/W, 00011
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-19. PLL Divider 2 Register Layout (0x1C8E)
Table 3-17. PLL Divider 2 Register Bit Field Description
BIT NAME
D2EN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R/W
1
Divider D2 enable
•
•
D2EN = 0: Divider 2 disabled
D2EN = 1: Divider 2 enabled
Reserved
PLLDIV2
14:5
4:0
R
0000000000
00011
Reserved. Reads return 0. Writes have no effect.
Divider D2 ratio (SYSCLK2 divider)
R/W
•
•
•
•
•
PLLDIV2 = 00000: Divide by 1
PLLDIV2 = 00001: Divide by 2
PLLDIV2 = 00010: Reserved
PLLDIV2 = 00011: Divide by 4
PLLDIV2 = 00100–11111: Reserved
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3.10.5.6 PLL Divider3 Register (PLLDIV3) for SYSCLK3
This register controls the value of the divider D3 for SYSCLK3. It is in both the BYPASS and PLL paths.
15
14
8
D3EN
Reserved
R/W, 1
7
R, 0000000
5
4
0
Reserved
R, 000
PLLDIV3
R/W, 00011
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-20. PLL Divider 3 Register Layout (0x1C90)
Table 3-18. PLL Divider 3 Register Bit Field Description
BIT NAME
D3EN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R/W
1
Divider D3 enable
•
•
D3EN = 0: Divider 3 disabled
D3EN = 1: Divider 3 enabled
Reserved
PLLDIV3
14:5
4:0
R
0000000000
00011
Reserved. Reads return 0. Writes have no effect.
Divider D3 ratio (SYSCLK3 divider)
R/W
•
•
•
•
•
PLLDIV3 = 00000: Divide by 1
PLLDIV3 = 00001: Divide by 2
PLLDIV3 = 00010: Reserved
PLLDIV3 = 00011: Divide by 4
PLLDIV3 = 00100–11111: Reserved
3.10.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3
This register controls the value of the divider OD1 for CLKOUT3. It does not go through the PLL path.
15
14
8
OD1EN
Reserved
R/W, 0
7
R, 0000000
5
4
0
Reserved
R, 000
OSCDIV1
R/W, 00000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-21. Oscillator Divider1 Register Layout (0x1C92)
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Table 3-19. Oscillator Divider1 Register Bit Field Description
BIT NAME
OD1EN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
Oscillator divider OD1 enable
15
R/W
0
•
•
OD1EN = 0: Oscillator divider 1 disabled
OD1EN = 1: Oscillator divider 1 enabled
Reserved
OSCDIV1
14:5
4:0
R
0000000000
00000
Reserved. Reads return 0. Writes have no effect.
Divider OD1 ratio (CLKOUT3 divider)
R/W
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
OSCDIV1 = 00000: Divide by 1
OSCDIV1 = 00001: Divide by 2
OSCDIV1 = 00010: Divide by 3
OSCDIV1 = 00011: Divide by 4
OSCDIV1 = 00100: Divide by 5
OSCDIV1 = 00101: Divide by 6
OSCDIV1 = 00110: Divide by 7
OSCDIV1 = 00111: Divide by 8
OSCDIV1 = 01000: Divide by 9
OSCDIV1 = 01001: Divide by 10
OSCDIV1 = 01010: Divide by 11
OSCDIV1 = 01011: Divide by 12
OSCDIV1 = 01100: Divide by 13
OSCDIV1 = 01101: Divide by 14
OSCDIV1 = 01110: Divide by 15
OSCDIV1 = 01111: Divide by 16
OSCDIV1 = 10000: Divide by 17
OSCDIV1 = 10001: Divide by 18
OSCDIV1 = 10010: Divide by 19
OSCDIV1 = 10011: Divide by 20
OSCDIV1 = 10100: Divide by 21
OSCDIV1 = 10101: Divide by 22
OSCDIV1 = 10110: Divide by 23
OSCDIV1 = 10111: Divide by 24
OSCDIV1 = 11000: Divide by 25
OSCDIV1 = 11001: Divide by 26
OSCDIV1 = 11010: Divide by 27
OSCDIV1 = 11011: Divide by 28
OSCDIV1 = 11100: Divide by 29
OSCDIV1 = 11101: Divide by 30
OSCDIV1 = 11110: Divide by 31
OSCDIV1 = 11111: Divide by 32
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3.10.5.8 Oscillator Wakeup Control Register (WKEN)
This register controls whether different events in the system are enabled to wake up the device after
entering OSCPWRDN.
15
8
Reserved
R, 00000000
7
5
4
3
2
1
0
Reserved
R, 000
WKEN4
R/W, 1
WKEN3
WKEN2
WKEN1
WKEN0
R/W, 1
R/W, 1
R/W, 1
R/W, 1
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-22. Oscillator Wakeup Control Register Layout (0x1C98)
Table 3-20. Oscillator Wakeup Control Register Bit Field Description
BIT NAME
Reserved
WKEN4
BIT NO.
15:5
4
ACCESS
R
RESET VALUE
00000000000
1
DESCRIPTION
Reserved. Reads return 0. Writes have no effect.
R/W
Input INT3 can wake up the oscillator when the OSCPWRDN bit in
PLLCSR is asserted to logic 1.
•
WKEN4 = 0:
Wake-up enabled. A low-to-high transition on INT3 wakes up the
oscillator and clears the OSCPWRDN bit.
•
WKEN4 = 1:
Wake-up disabled. A low-to-high transition on INT3 does not wake
up the oscillator.
WKEN3
WKEN2
WKEN1
3
2
1
R/W
R/W
R/W
1
1
1
Input INT2 can wake up the oscillator when the OSCPWRDN bit in
PLLCSR is asserted to logic 1.
•
WKEN3 = 0:
Wake-up enabled. A low-to-high transition on INT2 wakes up the
oscillator and clears the OSCPWRDN bit.
•
WKEN3 = 1:
Wake-up disabled. A low-to-high transition on INT2 does not wake
up the oscillator.
Input INT1 can wake up the oscillator when the OSCPWRDN bit in
PLLCSR is asserted to logic 1.
•
WKEN2 = 0:
Wake-up enabled. A low-to-high transition on INT1 wakes up the
oscillator and clears the OSCPWRDN bit.
•
WKEN2 = 1:
Wake-up disabled. A low-to-high transition on INT1 does not wake
up the oscillator.
Input INT0 can wake up the oscillator when the OSCPWRDN bit in
PLLCSR is asserted to logic 1.
•
WKEN1 = 0:
Wake-up enabled. A low-to-high transition on INT0 wakes up the
oscillator and clears the OSCPWRDN bit.
•
WKEN1 = 1:
Wake-up disabled. A low-to-high transition on INT0 does not wake
up the oscillator.
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Table 3-20. Oscillator Wakeup Control Register Bit Field Description (continued)
BIT NAME
WKEN0
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
0
R/W
1
Input NMI can wake up the oscillator when the OSCPWRDN bit in
PLLCSR is asserted to logic 1.
•
WKEN0 = 0:
Wake-up enabled. A low-to-high transition on NMI wakes up the
oscillator and clears the OSCPWRDN bit.
•
WKEN0 = 1:
Wake-up disabled. A low-to-high transition on NMI does not wake
up the oscillator.
3.10.5.9 CLKOUT3 Select Register (CK3SEL)
This register controls which clock is output onto the CLKOUT3 so that it may be used to test and debug
the PLL (in addition to its normal function of being a direct input clock divider). Modes other than
CK3SEL = 1011 are intended for debug use only and should not be used during normal operation.
15
8
Reserved
R, 00000000
7
4
3
0
Reserved
R, 0000
CK3SEL
R/W, 1011
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-23. CLKOUT3 Select Register Layout (0x1C82)
Table 3-21. CLKOUT3 Select Register Bit Field Description
BIT NAME
Reserved
CK3SEL
BIT NO.
15:4
ACCESS
R
RESET VALUE
000000000000 Reserved. Reads return 0. Writes have no effect.
1011
Output on CLK3SEL pin(1)
DESCRIPTION
3:0
R/W
•
•
•
CK3SEL = 1001: CLKOUT3 becomes point A in Figure 3-14
CK3SEL = 1010: CLKOUT3 becomes point B in Figure 3-14
CK3SEL = 0000-0111: CLKOUT3 becomes oscillator divider output
in Figure 3-14
•
•
CK3SEL = 1011: CLKOUT3 becomes point C in Figure 3-14
CK3SEL = Other: Not supported
(1) The different options for the CLKOUT3 signal are intended for test purposes; it is recommended that the CK3SEL bits of the CK3SEL
register be kept at their default value of '1011b' during normal operation.
3.10.5.10 CLKOUT Selection Register (CLKOUTSR)
As described in Section 3.10.2, Clock Groups, the 5502 has different clock groups, each of which can be
driven by a clock that is different from the CPU clock. The CLKOUT Selection Register determines which
clock signal is reflected on the CLKOUT pin.
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15
8
Reserved
R, 00000000
7
3
2
1
0
Reserved
R, 00000
CLKOSEL
R/W, 01
CLKOUTDIS
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-24. CLKOUT Selection Register Layout (0x8400)
Table 3-22. CLKOUT Selection Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-3
ACCESS
R
RESET VALUE
DESCRIPTION
0000000000000 Reserved
CLKOSEL
2:1
R/W
01
CLKOUT source-select
•
•
•
•
CLKOSEL = 00: Reserved
CLKOSEL = 01: CLKOUT source is SYSCLK1
CLKOSEL = 10: CLKOUT source is SYSCLK2
CLKOSEL = 11: CLKOUT source is SYSCLK3
CLKOUTDIS
0
R/W
0
Disable CLKOUT
•
•
CLKOUTDIS = 0: CLKOUT enabled
CLKOUTDIS = 1: CLKOUT disabled (driving 0)
3.10.5.11 Clock Mode Control Register (CLKMD)
15
8
Reserved
R, 00000000
7
1
0
Reserved
R, 0000000
CLKMD0
R/W, GPIO4
state at reset
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-25. Clock Mode Control Register Layout (0x8C00)
Table 3-23. Clock Mode Control Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-1
0
ACCESS
R
RESET VALUE
DESCRIPTION
000000000000000
Reserved
CLKMD0
R/W
GPIO4 state at reset Clock output source-select
•
•
CLKMD0 = 0: OSCOUT is selected as clock input source
CLKMD0 = 1: X2/CLKIN is selected as clock input source
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3.10.6 Reset Sequence
When RESET is low, the clock generator is in bypass mode with the input clock set to CLKIN or
X2/CLKIN, dependent upon the state of GPIO4. After the RESET pin transitions from low to high, the
following events will occur in the order listed below.
•
GPIO6 and GPIO7 are sampled on the rising edge of the reset signal. The state of GPIO6 and GPIO7
determines the function of the multiplexed pins of the 5502, see Section 3.3, Configurable External
Ports and Signals, for more information on pin multiplexing. The state of GPIO6 and GPIO7 during the
rising edge of reset determines the values for the Parallel/Host Port Mux Mode and the Serial Port 2
Mux Mode bits, respectively, of the External Bus Control Register (XBSR).
•
GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock
Mode Control Register (CLKMD), which in turns, determines the clock source for the DSP. The
CLKMD0 bit selects either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input
clock source for the DSP. If GPIO4 is low at reset, the CLKMD0 bit will be set to 0 and the internal
oscillator and the external crystal generate the input clock for the DSP. If GPIO4 is high, the CLKMD0
bit will be set to 1 and the input clock will be taken directly from the X2/CLKIN pin.
•
•
•
After the reset signal transitions from low to high, the DSP will not be taken out of reset immediately.
Instead, an internal counter will count 41032 clock cycles to allow the internal oscillator to stabilize
(only if GPIO4 was low). The internal counter will also add 70 reference clock cycles to allow the reset
signal to propagate through different parts of the device.
After all internal delay cycles have expired, the IACK pin will go low for two CPU clock cycles to
indicate this internal reset signal has been deasserted. The BOOTM[2:0] pins will be sampled and their
values will be stored in the Boot Mode Register (BOOTM_MODE). The value in the BOOTM_MODE
register will be used by the bootloader to determine the boot mode of the DSP.
Program flow will commence after all internal delay cycles have expired.
The 5502 has internal circuitry that will count down 70 reference clock cycles to allow reset signals to
propagate correctly to all parts of the device after reset (RESET pin goes high). Furthermore, the 5502
also has internal circuitry that will count down 41,032 reference clock cycles to allow the oscillator input to
become stable after waking up from power-down state or reset. If a reset is asserted, program flow will
start after all stabilization periods have expired; this includes the oscillator stabilization period only if
GPIO4 is low at reset. If the oscillator is coming out of power-down mode, program flow will start
immediately after the oscillator stabilization period has completed. Table 3-24 summarizes the number of
reference clock cycles needed before program flow begins.
Table 3-24. Number of Reference Clock Cycles Needed Until Program Flow Begins
CONDITION
Oscillator Not Used (GPIO4 = 1)
Oscillator Used (GPIO4 = 0)
REFERENCE CLOCK CYCLES
70
After Reset
41,102
41,032
After Oscillator Power-Down
All output (O/Z) and input/output (I/O/Z) pins (except for CLKOUT, ECLKOUT2, and XF) will go into
high-impedance mode during reset and will come out of high-impedance mode when the stabilization
periods have expired. All output (O/Z) and input/output (I/O/Z) pins will retain their value when the device
enters a power-down mode such as IDLE3 mode.
3.11 Idle Control
The Idle function is implemented for low power consumption. The Idle function achieves low power
consumption by gating the clock to unused parts of the chip, and/or setting the clock generator (PLL) and
the internal oscillator to a power-down mode.
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3.11.1 Clock Domains
The 5502 provides six clock domains to power-off the main clock to the portions of the device that are not
being used. The six domains are:
•
•
•
•
•
•
CPU Domain
Master Port Domain (includes DMA and HPI modules)
ICACHE
Peripherals Domain
Clock Generator Domain
EMIF Domain
3.11.2 IDLE Procedures
Before entering idle mode (executing the IDLE instruction), the user has first to determine which part of
the system needs to be disabled and then program the Idle Control Register (ICR) accordingly. When the
IDLE instruction is executed, the ICR will be copied into the Idle Status Register (ISTR). The different bits
of the ISTR register will be propagated to disable the chosen domains. Special care has to be taken in
programming the ICR as some IDLE domain combinations are not valid (for example: CPU on and clock
generator off).
3.11.2.1 CPU Domain Idle Procedure
The 5502 CPU can be idled by executing the following procedure.
1. Write '1' to the CPUI bit (bit 0 of ICR).
2. Execute the IDLE instruction.
3. CPU will go to idle state
3.11.2.2 Master Port Domain (DMA/HPI) Idle Procedure
The clock to the DMA module and/or the HPI module will be stopped when the DMA and/or the HPI bit in
the MICR is set to 1 and the MPIS bit in the ISTR becomes 1. The DMA will go into idle immediately if
there is no data transfer taking place. If there is a data transfer taking place, then it will finish the current
transfer and then go into idle. The HPI will go into idle regardless of whether or not there is a data transfer
taking place. Software must confirm that the HPI has no activity before setting it to idle.
The 5502 DMA module and the HPI module can be disabled by executing the following procedure.
1. Write '1' to the DMA bit and/or the HPI bit in MICR.
2. Write '1' to the MPI bit in ICR.
3. Execute the IDLE instruction.
4. DMA and/or HPI go/goes to idle.
3.11.2.3 Peripheral Modules Idle Procedure
The clock to the modules included in the Peripherals Domain will be stopped when their corresponding bit
in the PICR is set to 1 and the PERIS bit in the ISTR becomes 1. Each module in this domain will go into
idle immediately if it has no activity. If the module being set to idle has activity, it will wait until the activity
completes before going into idle.
Each peripheral module can be idled by executing the following procedure.
1. Write '1' to the corresponding bit in PICR for each peripheral to be idled.
2. Write '1' to the PERI bit in ICR.
3. Execute the IDLE instruction.
4. Every peripheral with its corresponding PICR bit set will go to idle.
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3.11.2.4 EMIF Module Idle Procedure
The 5502 EMIF can be idled in one of two ways: through the ICR and through the PICR. The EMIF will go
into idle immediately if there is no data transfer taking place within the DMA. If there is a data transfer
taking place, then the EMIF will wait until the DMA finishes the current transfer and goes into idle before
going into idle itself. Please note that while the EMIF is in idle, the SDRAM refresh function of the EMIF
will not be available.
The 5502 EMIF can be idled through the ICR only when the following modules are set to idle: CPU, I-Port,
ICACHE, DMA, and HPI. To place the EMIF in idle using the ICR, execute the following procedure:
1. Write '1' to the DMA and HPI bits in MICR.
2. Write '1' to the CPUI, MPI, ICACHEI, EMIFI, and IPORTI bits in ICR.
3. Execute the IDLE instruction.
4. EMIF and all modules listed in Step 2 will go to idle.
The 5502 EMIF can also be idled through the PICR. To place the EMIF in idle using the PICR, execute
the following procedure:
1. Write a '1' to the EMIF bit in PICR.
2. Write a '1' to the PERI bit in ICR.
3. Execute IDLE instruction.
4. EMIF will go to IDLE.
3.11.2.5 IDLE2 Mode
In IDLE2 mode, all modules except the CLOCK module are set to idle state. To place the 5502 in IDLE2
mode, perform the following steps.
1. Write a '1' to all peripheral module bits in the PICR.
2. Write a '1' to the HPI and DMA bits in MICR.
3. Write a '1' to all domain bits in the ICR except the CLOCK domain bit (CLKI).
4. Execute the IDLE instruction.
5. All internal clocks will be disabled, the CLOCK module will remain active.
3.11.2.6 IDLE3 Mode
In IDLE3 mode, all modules (including the CLOCK module) are set to idle state. To place the 5502 in
IDLE3 mode, perform the following steps.
1. Clear (i.e., set to '0') the PLLEN bit in PLLCSR to place the PLL in bypass mode.
2. Set the PLLPWRDN and PLLRST bits in PLLCSR to '1'.
3. Write a '1' to all peripheral module bits in PICR (write 0x3FFF to PICR).
4. Write a '1' to the HPI and DMA bits in MICR (write 0x0003 to MICR).
5. Write a '1' to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).
6. Execute the IDLE instruction.
7. PLL core is set to power-down mode and all internal clocks are disabled.
3.11.2.7 IDLE3 Mode With Internal Oscillator Disabled
In this state, all modules (including the CLOCK module) are set to the idle state and the internal oscillator
is set to the power-down mode. This is the lowest power-consuming state that 5502 can be placed under.
1. Clear (i.e., set to '0') the PLLEN bit in PLLCSR to place the PLL in bypass mode.
2. Set the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR to '1'.
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3. Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have
(1)
interrupt 0 (INT0) wake up the oscillator].
4. Write a '1' to all peripheral module bits in the PICR (write 0x3FFF to PICR).
5. Write a '1' to the HPI and DMA bits in MICR (write 0x0003 to MICR).
6. Write a '1' to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).
7. Execute the IDLE instruction.
8. Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal
clocks are disabled.
Note that the internal oscillator can be awakened through an NMI or external interrupt as long as that
event is specified in the Oscillator Wakeup Control Register and, in the case of an external interrupt, the
interrupt is enabled in the CPU’s Interrupt Enable Register.
(1) Maskable external interrupts must be enabled through IER prior to setting the 5502 to IDLE.
3.11.3 Module Behavior at Entering IDLE State
All transactions must be completed before entering the IDLE state. Table 3-25 lists the behavior of each
module before entering the IDLE state.
Table 3-25. Peripheral Behavior at Entering IDLE State
MODULE BEHAVIOR AT ENTERING IDLE STATE
CLOCK DOMAIN
MODULES
(ASSUMING THE IDLE CONTROL IS SET)
CPU
Enter IDLE after CPU stops pipeline.
Interrupt Controller
IDLE Controller
PLL Controller
Enter IDLE after CPU stops.
Enter IDLE after CPU stops.
Enter IDLE after CPU stops.
CPU
Enter IDLE state after current DMA transfer to internal memory, EMIF,
or peripheral, or enter IDLE state immediately if no transfer exists.
DMA has function of Auto-wakeup/Idle with McBSP data transfer during
IDLE.
DMA
Master Port
ICACHE
HPI
Enter IDLE state immediately. Software has to take care of HPI activity.
Enter IDLE state after current data transfer from EMIF or program fetch
from CPU finishes, or enter IDLE state immediately if no transfer and
no access exist.
ICACHE
External Bus Selection Register Enter IDLE after CPU stops.
Timer Signal Selection Register Enter IDLE after CPU stops.
CLKOUT Selection Register
Enter IDLE after CPU stops.
External Bus Control Register Enter IDLE after CPU stops.
Clock Mode Control Register
Timer0/1 and WDT
Enter IDLE after CPU stops.
Enter IDLE state immediately
Enter IDLE state immediately
DSP/BIOS Timer
External Clock and Frame:
Enter IDLE state after current McBSP activity is finished or enter IDLE
state immediately if no activity exists. McBSP has function of
Auto-wakeup/Idle with DMA transfer during IDLE.
Internal Clock and Frame:
Peripheral
MCBSP0/1/2
Enter IDLE state immediately if both transmitter and receiver are in
reset (XRST = 0 and RRST = 0). IDLE state not entered otherwise.
GPIO
I2C
Enter IDLE state immediately.
Enter IDLE state after current I2C activity is finished or enter IDLE state
immediately if no activity exists.
Enter IDLE state after current UART activity is finished or enter IDLE
state immediately if no activity exists.
UART
Parallel GPIO
Enter IDLE state immediately.
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Table 3-25. Peripheral Behavior at Entering IDLE State (continued)
MODULE BEHAVIOR AT ENTERING IDLE STATE
(ASSUMING THE IDLE CONTROL IS SET)
CLOCK DOMAIN
Clock Generator
EMIF
MODULES
PLL divider
PLL core
Oscillator
Enter IDLE state immediately.
Power-down state if set by software before IDLE
Power-down state if set by software before IDLE
Enter IDLE mode after current DMA transfer or enter IDLE mode
immediately if no activity exists.
EMIF
3.11.4 Wake-Up Procedure
It is the user's responsibility to ensure that there exists a valid wake-up procedure before entering idle
mode. Keep in mind that a hardware reset will restore all modules to their active state. All wake-up
procedures are described in the next sections.
3.11.4.1 CPU Domain Wake-up Procedure
The CPU domain can be taken out of idle though an enabled external interrupt or an NMI signal. External
interrupts can be enabled through the use of the IER0 and IER1 registers. Other modules, such as the
EMIF module, will be taken out of idle automatically when the CPU wakes up. Please see the wake-up
procedures for other modules for more information.
3.11.4.2 Master Port Domain (DMA/HPI) Wake-up Procedure
The 5502 DMA module and the HPI module can be taken out of idle simultaneously by executing the
following procedure.
1. Write '0' to the MPI bit in ICR.
2. Execute the IDLE instruction.
3. DMA and HPI wake up.
It is also possible to wake up the DMA and HPI modules individually through the use of the Master Idle
Control Register. To wake up only the DMA or the HPI module, perform the following steps:
1. Write '0' to the DMA bit or the HPI bit in MICR.
2. Selected module wakes up.
3.11.4.3 Peripheral Modules Wake-up Procedure
All 5502 peripherals can be taken out of idle simultaneously by executing the following procedure.
1. Write '0' to the PERI bit in ICR.
2. Execute the IDLE instruction.
3. All idled peripherals wake up.
It is also possible to wake up individual peripherals through the use of the Peripheral Idle Control Register
by executing the following procedure.
1. Write '0' to the idle control bit of peripheral(s) in PICR.
2. Idled peripherals with '0' in PICR wake up.
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3.11.4.4 EMIF Module Wake-up Procedure
If both the CPU and the EMIF are in idle, then the EMIF will come out of idle when the CPU is taken out of
idle. The CPU can be taken out of idle through the use of an NMI or an enabled external interrupt.
External interrupts can be enabled through the IER0 and IER1 registers.
If the CPU is not in idle, then the EMIF can be taken out of idle through either of the following two
procedures:
1. Write '0' to the PERI bit in ICR.
2. Execute the IDLE instruction.
3. All idled peripherals, including the EMIF, wake up.
Or:
1. Write '0' to the EMIF bit in PICR.
2. The EMIF module will wake up.
3.11.4.5 IDLE2 Mode Wake-up Procedure
The 5502 can be taken completely out of IDLE2 mode by executing the following procedure.
1. CPU wakes up from idle through NMI or enabled external interrupt.
2. Write '0' to all bits in the ICR.
3. Execute the IDLE instruction.
4. All internal clocks are enabled and all modules come out of idle.
3.11.4.6 IDLE3 Mode Wake-up Procedure
The 5502 can be taken completely out of IDLE3 mode by executing the following procedure.
1. CPU wakes up from idle through NMI or enabled external interrupt.
2. Write '0' to all bits in the ICR.
3. Execute the IDLE instruction.
4. All internal clocks are enabled and all modules come out of idle.
5. Write '0' to the PLLPWRDN and PLLRST bits in PLLCSR.
6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.
7. Set the PLLEN bit in PLLCSR to '1'.
8. All internal clocks will now come from the PLL core.
NOTE
Step 3 can be modified to only wake up certain modules, see previous sections for more
information on the wake-up procedures for the 5502 modules.
3.11.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure
The internal oscillator of the 5502 will be woken up along with the CLOCK module through an NMI or an
enabled external interrupt. The source (INT0, INT1, INT2, INT3, or NMI) for the wake-up signal can be
selected through the use of the WKEN register. The maskable external interrupts must be enabled
through IER0 and IER1 prior to setting the 5502 to Idle 3 mode.
The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032
reference clock cycles) to allow the oscillator input to become stable after waking up from power-down
state or reset. When waking up from idle mode, program flow will start after the stabilization period of the
oscillator has expired (41032 reference clock cycles).
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To take the 5502 (including the internal oscillator) out of the idle 3 state, execute the following procedure:
1. External interrupt or NMI occurs (as specified in the WKEN register) and program flow begins after
41,032 reference clock cycles.
2. CPU wakes up.
3. Write '0' to all bits in the ICR.
4. Execute the IDLE instruction.
5. All internal clocks are enabled and all modules come out of idle.
6. Write '0' to the PLLPWRDN, PLLRST, and OSCPWRDN bits in PLLCSR.
7. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.
8. Set the PLLEN bit in PLLCSR to '1'.
9. All internal clocks will now come from the PLL core.
NOTE
Step 2 can be modified to only wake up certain modules, see previous sections for more
information on the wake-up procedures for the 5502 modules.
3.11.4.8 Summary of Wake-up Procedures
Table 3-26 summarizes the wake-up procedures.
Table 3-26. Wake-Up Procedures
CLOCK DOMAIN
ISTR VALUE
EXIT FROM IDLE
ICR AFTER WAKE-UP
ISTR AFTER WAKE-UP
STATUS
xxx0xxx0
CPU - ON
Clock Generator - ON
Other - ON/OFF
1. DSP software modifies ICR 1. Modified value
1. Updated to ICR modified
value after "IDLE" instruction
and executes "IDLE" instruc-
2. All "0"
tion
2. All "0"
2. Reset
xxx0xxx1
xxx11111
CPU - OFF
Clock Generator - ON
Other - ON/OFF
1. Unmasked interrupt from ex- 1. Not modified
1. CPUIS,
CLKIS,
and
ternal or on-chip module
EMIFIS/XPORTIS/IPORTIS
are set to "0"
2. All "0"
2. Reset
2. All "0"
CPU - OFF
Clock Generator - OFF
Other - OFF
1. Unmasked interrupt from ex- 1. Not modified
1. CPUIS,
CLKIS,
and
ternal
EMIFIS/XPORTIS/IPORTIS
are set to "0"
2. All "0"
2. Reset
2. All "0"
3.11.5 Auto-Wakeup/Idle Function for McBSP and DMA
The 5502 has an Auto-wakeup/Idle function for McBSP to DMA to on-chip memory data transfers when
the DMA and the McBSP are both set to IDLE. In the case that the McBSP is set to external clock mode
and the McBSP and the DMA are set to idle, the McBSP and the DMA can wake up from IDLE state
automatically if the McBSP gets a new data transfer. The McBSP and the DMA enter the idle state
automatically after data transfer is complete. [The clock generator (PLL) should be active and the PLL
core should not be in power-down mode for the Auto-wakeup/Idle function to work.]
3.11.6 Clock State of Multiplexed Modules
The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are
not selected through the External Bus Selection Register (XBSR). Note that any accesses to disabled
modules will result in a bus error.
78
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3.11.7 IDLE Control and Status Registers
The clock domains are controlled by the IDLE Configuration Register (ICR) that allows the user to place
different parts of the device in Idle mode. The IDLE Status Register (ISTR) reflects the portion of the
device that remains active. The peripheral domain is controlled by the Peripheral IDLE Control Register
(PICR). The Peripheral IDLE Status Register (PISTR) reflects the portion of the peripherals that are in the
IDLE state. The Master IDLE Control Register (MICR) is used to place the HPI and DMA in Idle mode.
The IDLE state of the HPI and DMA is reflected by the Master IDLE Status Register (MISR). The PLL
Control/Status Register (PLLCSR) is used to power down the PLL core when the IDLE instruction is
executed.
The settings in the ICR, PICR, and MICR take effect after the IDLE instruction is executed. For example,
writing xxx000001b into the ICR does not indicate that the CPU domain is in IDLE mode; rather, it
indicates that after the IDLE instruction, the CPU domain will be in IDLE mode. Procedures for placing
portions of the device in Idle mode and taking them out of Idle mode are described in Section 3.11.2 (IDLE
Procedures) and Section 3.11.4 (Wake-Up Procedures), respectively.
Table 3-27. Clock Domain Memory-Mapped Registers
ADDRESS
0x0001
0x0002
0x9400
0x9401
0x9402
0x9403
REGISTER NAME
IDLE Configuration Register (ICR)
IDLE Status Register (ISTR)
Peripheral IDLE Control Register (PICR)
Peripheral IDLE Status Register (PISTR)
Master IDLE Control Register (MICR)
Master IDLE Status Register (MISR)
3.11.7.1 IDLE Configuration Register (ICR)
15
10
9
8
Reserved
CLKEI(1)
IPORTI
R, 000000
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
MPORTI
XPORTI
EMIFI
CLKI
PERI
ICACHEI
MPI
CPUI
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
(1) This bit must be set to '1' when placing the clock generator in idle; otherwise, a bus error interrupt will be generated.
Figure 3-26. IDLE Configuration Register Layout (0x0001)
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Table 3-28. IDLE Configuration Register Bit Field Description
BIT NAME
Reserved
CLKEI
BIT NO.
15-10
9
ACCESS
R
RESET VALUE
DESCRIPTION
000000
0
Reserved
R/W
Extended device clock generator idle control bit. The CLKEI bit must be
set to 1 along with the CLKI bit in order to properly place the device clock
generator in idle.
•
CLKI = 0 and CLKEI = 0:
Device clock generator module remains active after execution of an
IDLE instruction.
•
CLKI = 1 and CLKEI = 1:
Device clock generator is disabled after execution of an IDLE
instruction.
Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1
and executing the IDLE instruction will generate a bus error interrupt if
CLKEI is not set to 1.
Disabling the clock generator provides the lowest level of power reduction
by stopping the system clock. Whenever the clock generator is idled, the
CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits
must be set to 1 in order to ensure a proper power-down mode. A bus
error interrupt will be generated if the idle instruction is executed when
CLKI = 1 and any of these bits are not set to 1.
IPORTI
8
7
R/W
R/W
0
0
IPORT idle control bit. The IPORT is used for all ICACHE transactions.
•
IPORTI = 0:
IPORT remains active after execution of an IDLE instruction
•
IPORTI = 1:
IPORT is disabled after execution of an IDLE instruction
MPORTI
MPORT idle control bit. The MPORT is used for all DMA and HPI
transactions.
•
MPORTI = 0:
MPORT remains active after execution of an IDLE instruction
•
MPORTI = 1:
MPORT is disabled after execution of an IDLE instruction
XPORTI
6
R/W
0
XPORT idle control bit. The XPORT is used for all I/O memory
transactions.
•
XPORTI = 0:
XPORT remains active after execution of an IDLE instruction
•
XPORTI = 1:
XPORT is disabled after execution of an IDLE instruction
EMIFI
CLKI
5
4
R/W
R/W
0
0
External Memory Interface (EMIF) idle control bit
•
EMIFI = 0:
EMIF module remains active after execution of an IDLE instruction
•
EMIFI = 1:
EMIF module is disabled after execution of an IDLE instruction
Device clock generator idle control bit. The CLKEI bit must be set to 1
along with the CLKI bit in order to properly place the device clock
generator in idle.
•
CLKI = 0 and CLKEI = 0:
Device clock generator module remains active after execution of an
IDLE instruction.
•
CLKI = 1 and CLKEI = 1:
Device clock generator is disabled after execution of an IDLE
instruction.
Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1
and executing the IDLE instruction will generate a bus error interrupt if
CLKEI is not set to 1.
Disabling the clock generator provides the lowest level of power reduction
by stopping the system clock. Whenever the clock generator is idled, the
CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits
must be set to 1 in order to ensure a proper power-down mode. A bus
error interrupt will be generated if the idle instruction is executed when
CLKI = 1 and any of these bits are not set to 1.
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Table 3-28. IDLE Configuration Register Bit Field Description (continued)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
PERI
3
R/W
0
Peripheral Idle control bit
•
PERI = 0:
All peripheral modules become/remain active after execution of an
IDLE instruction
•
PERI = 1:
All peripheral modules with 1 in PICR are disabled after execution of
an IDLE instruction
ICACHEI
MPI
2
1
R/W
R/W
0
0
ICACHE idle control bit
•
ICACHEI = 0:
ICACHE module remains active after execution of an IDLE instruction
•
ICACHEI = 1:
ICACHE module is disabled after execution of an IDLE instruction
Master peripheral (DMA and HPI) idle control bit
•
MPI = 0:
DMA and HPI modules remain active after execution of an IDLE
instruction
•
MPI = 1:
DMA and HPI modules are disabled after execution of an IDLE
instruction
CPUI
0
R/W
0
CPU idle control bit
•
CPUI = 0:
CPU module remains active after execution of an IDLE instruction
•
CPUI = 1:
CPU module is disabled after execution of an IDLE instruction
3.11.7.2 IDLE Status Register (ISTR)
15
9
8
Reserved
IPORTIS
R, 0000000
R, 0
7
6
5
4
3
2
1
0
MPORTIS
XPORTIS
EMIFIS
CLKIS
PERIS
ICACHEIS
MPIS
CPUIS
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-27. IDLE Status Register Layout (0x0002)
Table 3-29. IDLE Status Register Bit Field Description
BIT NAME
Reserved
IPORTIS
BIT NO.
15-9
8
ACCESS
RESET VALUE
DESCRIPTION
R
R
0000000
0
Reserved
IPORT idle status bit. The IPORT is used for all ICACHE transactions.
•
•
IPORTIS = 0: IPORT is active
IPORTIS = 1: IPORT is disabled
MPORTIS
XPORTIS
7
6
R
R
0
0
MPORT idle status bit. The MPORT is used for all DMA and HPI
transactions.
•
•
MPORTIS = 0: MPORT is active
MPORTIS = 1: MPORT is disabled
XPORT idle status bit. The XPORT is used for all I/O memory transactions.
•
•
XPORTIS = 0: XPORT is active
XPORTIS = 1: XPORT is disabled
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Table 3-29. IDLE Status Register Bit Field Description (continued)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
EMIFIS
5
R
0
External Memory Interface (EMIF) idle status bit
•
•
EMIFIS = 0: EMIF module is active
EMIFIS = 1: EMIF module is disabled
CLKIS
4
3
2
1
0
R
R
R
R
R
0
0
0
0
0
Device clock generator idle status bit
•
•
CLKIS = 0: Device clock generator module is active
CLKIS = 1: Device clock generator is disabled
PERIS
ICACHEIS
MPIS
Peripheral idle status bit
•
•
PERIS = 0: All peripheral modules are active
PERIS = 1: All peripheral modules are disabled
ICACHE idle status bit
•
•
ICACHEIS = 0: ICACHE module is active
ICACHEIS = 1: ICACHE module is disabled
DMA and HPI idle status bit
•
•
MPIS = 0: DMA and HPI modules are active
MPIS = 1: DMA and HPI modules are disabled
CPUIS
CPU idle status bit
•
•
CPUIS = 0: CPU module is active
CPUIS = 1: CPU module is disabled
3.11.7.3 Peripheral IDLE Control Register (PICR)
15
14
13
12
11
10
9
8
Reserved
R, 00
MISC
EMIF
BIOST
WDT
PIO
URT
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
I2C
ID
IO
SP2
SP1
SP0
TIM1
TIM0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-28. Peripheral IDLE Control Register Layout (0x9400)
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Table 3-30. Peripheral IDLE Control Register Bit Field Description
BIT NAME
Reserved
MISC
BIT NO.
15-14
13(1)
ACCESS
R
RESET VALUE
DESCRIPTION
00
0
Reserved
MISC bit
R/W
•
MISC = 0:
Miscellaneous modules remain active when ISTR.PERIS = 1
and IDLE instruction is executed.
•
MISC = 1:
MIscellaneous module is disabled when ISTR.PERIS = 1 and
IDLE instruction is executed.
Miscellaneous modules include the XBSR, TIMEOUT Error Register,
XBCR, Timer Signal Selection Register, CLKOUT Select Register,
and Clock Mode Control Register.
EMIF
BIOST
WDT
PIO
12(1)
11(1)
10(1)
9(1)
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
EMIF bit
•
EMIF = 0:
EMIF module remains active when ISTR.PERIS = 1 and IDLE
instruction is executed.
•
EMIF = 1:
EMIF module is disabled when ISTR.PERIS = 1 and IDLE
instruction is executed.
BIOS timer bit
•
BIOST = 0:
DSP/BIOS timer remains active when ISTR.PERIS = 1 and the
IDLE instruction is executed.
•
BIOST = 1:
DSP/BIOS timer is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
Watchdog timer bit
•
WDT = 0:
WDT remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
WDT = 1:
WDT is disabled when ISTR.PERIS = 1 and the IDLE instruction
is executed.
Parallel GPIO bit
•
PIO = 0:
Parallel GPIO remains active when ISTR.PERIS = 1 (ISTR.[3])
and the IDLE instruction is executed.
•
PIO = 1:
Parallel GPIO is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
URT
8(1)
UART bit
•
URT = 0:
UART remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
URT = 1:
UART is disabled when ISTR.PERIS = 1 and the IDLE instruc-
tion is executed.
I2C
7(1)
I2C bit
•
I2C = 0:
I2C remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
I2C = 1:
I2C is disabled when ISTR.PERIS = 1 and the IDLE instruction is
executed.
(1) If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and
PICR bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0.
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Table 3-30. Peripheral IDLE Control Register Bit Field Description (continued)
BIT NAME
ID
BIT NO.
6(1)
ACCESS
RESET VALUE
DESCRIPTION
R/W
0
ID bit
•
ID = 0:
ID remains active when ISTR.PERIS = 1 and the IDLE instruc-
tion is executed.
•
ID = 1:
ID is disabled when ISTR.PERIS = 1 and the IDLE instruction is
executed.
IO
5(1)
4(1)
3(1)
2(1)
1(1)
0(1)
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
IO bit
•
IO = 0:
GPIO remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
IO = 1:
GPIO is disabled when ISTR.PERIS = 1 and the IDLE instruction
is executed.
SP2
SP1
SP0
TIM1
TIM0
McBSP2 bit
•
SP2 = 0:
McBSP2 remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
SP2 = 1:
McBSP2 is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
McBSP1 bit
•
SP1 = 0:
McBSP1 remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
SP1 = 1:
McBSP1 is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
McBSP0 bit
•
SP0 = 0:
McBSP0 remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
SP0 = 1:
McBSP0 is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
TIMER1 bit
•
TIM1 = 0:
TIMER1 remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
TIM1 = 1:
TIMER1 is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
TIMER0 bit
•
TIM0 = 0:
TIMER0 remains active when ISTR.PERIS = 1 and the IDLE
instruction is executed.
•
TIM0 = 1:
TIMER0 is disabled when ISTR.PERIS = 1 and the IDLE
instruction is executed.
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3.11.7.4 Peripheral IDLE Status Register (PISTR)
15
14
13
12
11
10
9
8
Reserved
R, 00
MISC
EMIF
BIOST
WDT
PIO
URT
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
7
6
5
4
3
2
1
0
I2C
ID
IO
SP2
SP1
SP0
TIM1
TIM0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
R, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-29. Peripheral IDLE Status Register Layout (0x9401)
Table 3-31. Peripheral IDLE Status Register Bit Field Description
BIT NAME
Reserved
MISC
BIT NO.
15-14
13
ACCESS
RESET VALUE
DESCRIPTION
R
R
00
0
Reserved
MISC bit
•
MISC = 0: Miscellaneous modules are active
•
MISC = 1: Miscellaneous modules are disabled
Miscellaneous modules include the XBSR, TIMEOUT Error Register,
XBCR, Timer Signal Selection Register, CLKOUT Select Register,
and Clock Mode Control Register.
EMIF
BIOST
WDT
PIO
URT
I2C
12
11
10
9
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
EMIF bit
•
•
EMIF = 0: EMIF module is active
EMIF = 1: EMIF module is disabled
BIOS timer bit
•
•
BIOST = 0: DSP/BIOS timer is active
BIOST = 1: DSP/BIOS timer is disabled
Watchdog timer bit
•
•
WDT = 0: WDT is active
WDT = 1: WDT is disabled
Parallel GPIO bit
•
•
PIO = 0: Parallel GPIO is active
PIO = 1: Parallel GPIO is disabled
8
UART bit
•
•
URT = 0: UART is active
URT = 1: UART is disabled
7
I2C bit
•
•
I2C = 0: I2C is active
I2C = 1: I2C is disabled
ID
6
ID bit
•
•
ID = 0: ID is active
ID = 1: ID is disabled
IO
5
IO bit
•
•
IO = 0: GPIO is active
IO = 1: GPIO is disabled
SP2
SP1
4
McBSP2 bit
•
•
SP2 = 0: McBSP2 is active
SP2 = 1: McBSP2 is disabled
3
McBSP1 bit
•
•
SP1 = 0: McBSP1 is active
SP1 = 1: McBSP1 is disabled
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Table 3-31. Peripheral IDLE Status Register Bit Field Description (continued)
BIT NAME
SP0
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
2
R
0
McBSP0 bit
•
•
SP0 = 0: McBSP0 is active
SP0 = 1: McBSP0 is disabled
TIM1
TIM0
1
0
R
R
0
0
TIMER1 bit
•
•
TIM1 = 0: TIMER1 is active
TIM1 = 1: TIMER1 is disabled
TIMER0 bit
•
•
TIM0 = 0: TIMER0 is active
TIM0 = 1: TIMER0 is disabled
3.11.7.5 Master IDLE Control Register (MICR)
15
8
Reserved
R, 00000000
7
2
1
0
Reserved
HPI
DMA
R, 000000
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-30. Master IDLE Control Register Layout (0x9402)
Table 3-32. Master IDLE Control Register Bit Field Description
BIT NAME
Reserved
HPI
BIT NO.
15-2
1
ACCESS
R
RESET VALUE
DESCRIPTION
00000000000000 Reserved
R/W
0
HPI bit
•
•
HPI = 0: HPI remains active when ISTR.MPIS becomes 1
HPI = 1: HPI is disabled when ISTR.MPIS becomes 1
DMA
0
R/W
0
DMA bit
•
•
DMA = 0: DMA remains active when ISTR.MPIS becomes 1
DMA = 1: DMA is disabled when ISTR.MPIS becomes 1
3.11.7.6 Master IDLE Status Register (MISR)
15
8
Reserved
R, 00000000
7
2
1
0
Reserved
HPI
DMA
R, 000000
R, 0
R, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-31. Master IDLE Status Register Layout (0x9403)
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Table 3-33. Master IDLE Status Register Bit Field Description
BIT NAME
BIT NO.
15-2
1
ACCESS
RESET VALUE
00000000000000
0
DESCRIPTION
Reserved
R
R
Reserved
HPI bit
HPI
•
•
HPI = 0: HPI is active
HPI = 1: HPI is in IDLE status
DMA
0
R
0
DMA bit
•
•
DMA = 0: DMA is active
DMA = 1: DMA is in IDLE status
3.12 General-Purpose I/O (GPIO)
The 5502 includes an 8-bit I/O port solely for general-purpose input and output. Several dual-purpose
(multiplexed) pins complement the dedicated GPIO pins. The following sections describe the 8-bit GPIO
port as well as the dual GPIO functions of the Parallel Port Mux and Host Port Mux pins.
3.12.1 General-Purpose I/O Port
The general-purpose I/O port consists of eight individually bit-selectable I/O pins GPIO0 (LSB) through
GPIO7 (MSB). The I/O port is controlled using two registers—IODIR and IODATA—that can be accessed
by the CPU or by the DMA, via the peripheral bus controller. The General-Purpose I/O Direction Register
(IODIR) is mapped at address 0x3400, and the General-Purpose I/O Data Register (IODATA) is mapped
at address 0x3401.
The GPIO3 and GPIO5 pins are multiplexed with the CLKX2 and FSX2 signals through the SP0 and SP2
pins, respectively. The function of the SP0 and SP2 pins is determined by the state of the GPIO7 pin
during reset. The SP0 and SP2 pins are set to GPIO3 and GPIO5, respectively, if GPIO7 is low during
reset. The SP0 and SP2 pins are set to CLKX2 and FSX2, respectively, if GPIO7 is high during reset. The
function of the SP0 and SP2 pins will be set once the device is taken out of reset (RESET pin transitions
from a low to a high state).
Figure 3-32 and Figure 3-33 show the bit layout of IODIR and IODATA, respectively. Table 3-34 and
Table 3-35 describe the bit fields of these registers.
3.12.1.1 General-Purpose I/O Direction Register (IODIR)
15
8
Reserved
R, 00000000
7
6
5
4
3
2
1
0
IO7DIR
IO6DIR
IO5DIR
IO4DIR
R/W, 0
IO3DIR
IO2DIR
IO1DIR
IO0DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-32. GPIO Direction Register Layout (0x3400)
Functional Overview
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Table 3-34. GPIO Direction Register Bit Field Description(1)
BIT NAME
Reserved
IOxDIR
BIT NO.
15-8
ACCESS
R
RESET VALUE
00000000
DESCRIPTION
Reserved
Data direction bits that configure the GPIO pins as inputs or outputs.
7-0
R/W
00000000
•
•
IOxDIR = 0: Configure corresponding GPIO pin as an input
IOxDIR = 1: Configure corresponding GPIO pin as an output
(1) x = value from 0 to 7
3.12.1.2 General-Purpose I/O Data Register (IODATA)
15
8
Reserved
R, 00000000
7
6
5
4
3
2
1
0
IO7D
IO6D
IO5D
IO4D
IO3D
IO2D
IO1D
IO0D
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3-33. GPIO Data Register Layout (0x3401)
Table 3-35. GPIO Data Register Bit Field Description(1)
BIT NAME
Reserved
IOxD
BIT NO.
15-8
ACCESS
R
RESET VALUE
DESCRIPTION
00000000
Reserved
7-0
R/W
Depends on the signal level on Data bits that are used to control the level of the I/O
the corresponding I/O pin
pins configured as outputs and to monitor the level of
the I/O pins configured as inputs.
If IOxDIR = 0, then:
•
IOxD = 0: Corresponding GPIO pin is read as a
low
•
IOxD = 1: Corresponding GPIO pin is read as a
high
If IOxDIR = 1, then:
•
•
IOxD = 0: Set corresponding GPIO pin to low
IOxD = 1: Set corresponding GPIO pin to high
(1) x = value from 0 to 7
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3.12.2 Parallel Port General-Purpose I/O (PGPIO)
Four address pins (A[21:18]), 16 data pins (D[31:16]), 16 control signals (C[15:0]), 8 host data pins
(HD[7:0]), and 2 HPI control pins (HC0, HC1) can be individually enabled as PGPIO when the
Parallel/Host Port Mux Mode bit field of the External Bus Selection Register (XBSR) is cleared for
non-multiplexed HPI mode (see Table 3-36). These pins are controlled by three sets of registers: the
PGPIO enable registers, the PGPIO direction registers, and the PGPIO data registers.
•
•
•
The PGPIO enable registers PGPIOEN0-PGPIOEN2 (see Figure 3-34, Figure 3-37, and Figure 3-40)
determine if the pin serves as PGPIO or if it is placed in high-impedance state.
The PGPIO direction registers PGPIODIR0-PGPIODIR2 (see Figure 3-35, Figure 3-38, and Fig-
ure 3-41) determine if the pin is an input or output.
The PGPIO data registers PGPIODAT0-PGPIODAT2 (see Figure 3-36, Figure 3-39, and Figure 3-42)
store the value read or written externally.
NOTE
The enable registers PGPIOENn cannot override the External Bus Selection Register
(XBSR) setting.
Table 3-36. TMS320VC5502 PGPIO Cross-Reference
PARALLEL/HOST PORT MUX MODE = 0
(HPI NON-MULTIPLEX)
PARALLEL/HOST PORT MUX MODE = 1
(FULL EMIF)
Pin
EMIF Address Bus
PGPIO[3:0]
EMIF Data Bus
PGPIO[19:4]
EMIF Control Bus
PGPIO20
A[21:18]
D[31:16]
EMIF.A[21:18]
EMIF.D[31:16]
C0
C1
EMIF.ARE/SADS/SDCAS/SRE
EMIF.AOE/SOE/SDRAS
EMIF.AWE/SWE/SDWE
EMIF.ARDY
PGPIO21
C2
PGPIO22
C3
PGPIO23
C4
PGPIO24
EMIF.CE0
C5
PGPIO25
EMIF.CE1
C6
PGPIO26
EMIF.CE2
C7
PGPIO27
EMIF.CE3
C8
PGPIO28
EMIF.BE0
C9
PGPIO29
EMIF.BE1
C10
C11
C12
C13
C14
C15
PGPIO30
EMIF.BE2
PGPIO31
EMIF.BE3
PGPIO32
EMIF.SDCKE
EMIF.SOE3
PGPIO33
PGPIO34
EMIF.HOLD
PGPIO35
EMIF.HOLDA
HPI Data Bus
PGPIO[43:36]
HPI Control Bus
PGPIO44
HD[7:0]
HPI.HD[7:0]
HC0
HC1
HPI.HAS
HPI.HBIL
PGPIO45
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3.12.2.1 Parallel GPIO Enable Register 0 (PGPIOEN0)
15
14
13
12
11
10
9
8
IO15EN
IO14EN
IO13EN
IO12EN
IO11EN
IO10EN
IO9EN
IO8EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO7EN
IO6EN
IO5EN
IO4EN
IO3EN
IO2EN
IO1EN
IO0EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-34. Parallel GPIO Enable Register 0 Layout (0x4400)
Table 3-37. Parallel GPIO Enable Register 0 Bit Field Description(1)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
IOxEN
15-0
R/W
0000000000000000 Enable or disable GPIO function of the corresponding I/O pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference.
•
IOxEN = 0:
GPIO function of corresponding signal is disabled, i.e., the pin goes
into a high-impedance state.
•
IOxEN = 1:
GPIO function of corresponding signal is enabled, i.e., the signal
supports its GPIO function.
(1) x = value from 0 to 15
3.12.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0)
15
14
13
12
11
10
9
8
IO15DIR
IO14DIR
IO13DIR
IO12DIR
IO11DIR
IO10DIR
IO9DIR
IO8DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO7DIR
IO6DIR
IO5DIR
IO4DIR
IO3DIR
IO2DIR
IO1DIR
IO0DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-35. Parallel GPIO Direction Register 0 Layout (0x4401)
Table 3-38. Parallel GPIO Direction Register 0 Bit Field Description(1)
BIT NAME
IOxDIR
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15-0
R/W
0000000000000000 Data direction bits that configure corresponding I/O pins either as
inputs or outputs. See Table 3-36, TMS320VC5502 PGPIO
Cross-Reference.
•
•
IOxDIR = 0: Configure corresponding pin as an input.
IOxDIR = 1: Configure corresponding pin as an output.
(1) x = value from 0 to 15
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3.12.2.3 Parallel GPIO Data Register 0 (PGPIODAT0)
15
14
13
12
11
10
9
8
IO15DAT
IO14DAT
IO13DAT
IO12DAT
IO11DAT
IO10DAT
IO9DAT
IO8DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
7
6
5
4
3
2
1
0
IO7DAT
IO6DAT
IO5DAT
IO4DAT
IO3DAT
IO2DAT
IO1DAT
IO0DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3-36. Parallel GPIO Data Register 0 Layout (0x4402)
Table 3-39. Parallel GPIO Data Register 0 Bit Field Description(1)
BIT NAME
IOxDAT
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15-0
R/W
Depends on the signal level on Data bits that are used to control the level of the
the corresponding I/O pin
corresponding I/O pins configured as output pins and to
monitor the level of the corresponding I/O pins configured
as input pins. See Table 3-36, TMS320VC5502 PGPIO
Cross-Reference.
If IOxDIR = 0, then:
•
IOxDAT = 0: Corresponding I/O pin is read as a low
IOxDAT = 1: Corresponding I/O pin is read as a high
•
If IOxDIR = 1, then:
•
•
IOxDAT = 0: Set corresponding I/O pin to low
IOxDAT = 1: Set corresponding I/O pin to high
(1) x = value from 0 to 15
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3.12.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1)
15
14
13
12
11
10
9
8
IO31EN
IO30EN
IO29EN
IO28EN
IO27EN
IO26EN
IO25EN
IO24EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO23EN
IO22EN
IO21EN
IO20EN
IO19EN
IO18EN
IO17EN
IO16EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-37. Parallel GPIO Enable Register 1 Layout (0x4403)
Table 3-40. Parallel GPIO Enable Register 1 Bit Field Description(1)
BIT NAME
IOxEN
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15-0
R/W
0000000000000000 Enable or disable GPIO function of the corresponding I/O pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference.
•
IOxEN = 0:
GPIO function of corresponding signal is disabled, i.e., the pin
goes into a high-impedance state.
•
IOxEN = 1:
GPIO function of corresponding signal is enabled, i.e., the
signal supports its GPIO function.
(1) x = value from 16 to 31
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3.12.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1)
15
14
13
12
11
10
9
8
IO31DIR
IO30DIR
IO29DIR
IO28DIR
IO27DIR
IO26DIR
IO25DIR
IO24DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO23DIR
IO22DIR
IO21DIR
IO20DIR
IO19DIR
IO18DIR
IO17DIR
IO16DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-38. Parallel GPIO Direction Register 1 Layout (0x4404)
Table 3-41. Parallel GPIO Direction Register 1 Bit Field Description(1)
BIT NAME
IOxDIR
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15-0
R/W
0000000000000000 Data direction bits that configure corresponding I/O pins either as
inputs or outputs. See Table 3-36, TMS320VC5502 PGPIO
Cross-Reference.
•
•
IOxDIR = 0: Configure corresponding pin as an input.
IOxDIR = 1: Configure corresponding pin as an output.
(1) x = value from 16 to 31
3.12.2.6 Parallel GPIO Data Register 1 (PGPIODAT1)
15
14
13
12
11
10
9
8
IO31DAT
IO30DAT
IO29DAT
IO28DAT
IO27DAT
R/W, pin
IO26DAT
IO25DAT
IO24DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
7
6
5
4
3
2
1
0
IO23DAT
IO22DAT
IO21DAT
IO20DAT
IO19DAT
IO18DAT
IO17DAT
IO16DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3-39. Parallel GPIO Data Register 1 Layout (0x4405)
Table 3-42. Parallel GPIO Data Register 1 Bit Field Description(1)
BIT NAME
IOxDAT
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15-0
R/W
Depends on the signal level on Data bits used to control the level of the corresponding I/O
the corresponding I/O pin
pins configured as output pins and to monitor the level of
the corresponding I/O pins configured as input pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference.
If IOxDIR = 0, then:
•
IOxDAT = 0: Corresponding I/O pin is read as a low
•
IOxDAT = 1: Corresponding I/O pin is read as a high
If IOxDIR = 1, then:
•
•
IOxDAT = 0: Set corresponding I/O pin to low
IOxDAT = 1: Set corresponding I/O pin to high
(1) x = value from 16 to 31
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3.12.2.7 Parallel GPIO Enable Register 2 (PGPIOEN2)
15
14
13
12
11
10
9
8
Reserved
R/W, 00
IO45EN
IO44EN
IO43EN
IO42EN
IO41EN
IO40EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO39EN
IO38EN
IO37EN
IO36EN
IO35EN
IO34EN
IO33EN
IO32EN
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-40. Parallel GPIO Enable Register 2 Layout (0x4406)
Table 3-43. Parallel GPIO Enable Register 2 Bit Field Description(1)
BIT NAME
Reserved
IOxEN
BIT NO.
15-14
13-0
ACCESS
R/W
RESET VALUE
DESCRIPTION
00
Reserved
R/W
00000000000000 Enable or disable GPIO function of the corresponding I/O pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference.
•
IOxEN = 0:
GPIO function of corresponding signal is disabled, i.e., the pin
goes into a high-impedance state.
•
IOxEN = 1:
GPIO function of corresponding signal is enabled, i.e., the signal
supports its GPIO function.
(1) x = value from 32 to 45
3.12.2.8 Parallel GPIO Direction Register 2 (PGPIODIR2)
15
14
13
12
11
10
9
8
Reserved
R/W, 00
IO45DIR
IO44DIR
IO43DIR
IO42DIR
IO41DIR
IO40DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO39DIR
IO38DIR
IO37DIR
IO36DIR
IO35DIR
IO34DIR
IO33DIR
IO32DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-41. Parallel GPIO Direction Register 2 Layout (0x4407)
Table 3-44. Parallel GPIO Direction Register 2 Bit Field Description(1)
BIT NAME
Reserved
IOxDIR
BIT NO.
15-14
13-0
ACCESS
R/W
RESET VALUE
DESCRIPTION
00
Reserved
R/W
00000000000000 Data direction bits that configure corresponding I/O pins either as
inputs or outputs. See Table 3-36, TMS320VC5502 PGPIO
Cross-Reference.
•
•
IOxDIR = 0: Configure corresponding pin as an input.
IOxDIR = 1: Configure corresponding pin as an output.
(1) x = value from 32 to 45
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3.12.2.9 Parallel GPIO Data Register 2 (PGPIODAT2)
15
14
13
12
11
10
9
8
Reserved
R/W, 00
IO45DAT
IO44DAT
IO43DAT
IO42DAT
IO41DAT
IO40DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
7
6
5
4
3
2
1
0
IO39DAT
R/W, pin
IO38DAT
IO37DAT
IO36DAT
IO35DAT
IO34DAT
IO33DAT
IO32DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3-42. Parallel GPIO Data Register 2 Layout (0x4408)
Table 3-45. Parallel GPIO Data Register 2 Bit Field Description(1)
BIT NAME
Reserved
IOxDAT
BIT NO.
15-14
13-0
ACCESS
R/W
RESET VALUE
DESCRIPTION
00
Reserved
R/W
Depends on the signal level on Data bits used to control the level of the I/O pins
the corresponding I/O pin
configured as output pins, and to monitor the level of the
corresponding I/O pins configured as input pins. See
Table 3-36, TMS320VC5502 PGPIO Cross- Reference.
If IOxDIR = 0, then:
•
IOxDAT = 0: Corresponding I/O pin is read as a low
•
IOxDAT = 1: Corresponding I/O pin is read as a high
If IOxDIR = 1, then:
•
•
IOxDAT = 0: Set corresponding I/O pin to low
IOxDAT = 1: Set corresponding I/O pin to high
(1) x = value from 32 to 45
3.13 External Bus Control Register
The External Bus Control Register is used to disable/enable the bus pullups, pulldowns, and bus holders
of the 5502 pins. Table 3-46 lists which 5502 pins have pullups, pulldowns, and bus holders, and which bit
on the XBCR enables/disables that feature. Please note that for pins with dual functionality (e.g., HC0,
HC1, C0, etc.), the bus holder, pullup, and pulldown feature of each pin can be enabled or disabled
regardless of the function of the pin at the time.
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Table 3-46. Pins With Pullups, Pulldowns, and Bus Holders
XBCR CONTROL BIT
PIN
TCK
FEATURE
Pullup
TDI
Pullup
TEST
TMS
Pullup
TRST
EMU1/OFF
EMU0
NMI/WDTOUT
HC0
Pulldown
Pullup
EMU
WDT
Pullup
Pullup
Pullup
HC1
Pulldown
Pullup
HCNTL0
HCNTL1
HCS
Pullup
Pullup
HC
HD
HR/W
HDS1
HDS2
HRDY
HINT
HD[7:0]
C0
Pullup
Pullup
Pullup
Pullup
Pullup
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Pullup
C1
C2
C3
C4
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Bus Holder
Pullup
C5
C6
C7
PC
C8
C9
C10
C11
C12
C13
C14
C15
Bus Holder
Bus Holder
Bus Holder
PD
PA
D[31:0]
A[21:2]
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3.13.1 External Bus Control Register (XBCR)
15
8
Reserved
R, 00000000
7
6
5
4
3
2
1
0
EMU
TEST
WDT
HC
HD
PC
PD
PA
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-43. External Bus Control Register Layout (0x8800)
Table 3-47. External Bus Control Register Bit Field Description
BIT NAME
Reserved
EMU
BIT NO.
15-8
7
ACCESS
R
RESET VALUE
DESCRIPTION
00000000
0
Reserved
EMU bit
R/W
•
•
EMU = 0: Pullups on EMU1 and EMU0 pins are enabled.
EMU = 1: Pullups on EMU1 and EMU0 pins are disabled.
TEST
6
R/W
0
TEST bit
•
TEST = 0: Pullups/pulldowns on test pins are enabled (does not
include EMU1 and EMU0 pins)
•
TEST = 1: Pullups/pulldowns on test pins are disabled (does not
include EMU1 and EMU0 pins)
WDT
HC
5
4
R/W
R/W
0
0
WDT bit
•
•
WDT = 0: Pullup on NMI/WDTOUT pin is enabled
WDT = 1: Pullup on NMI/WDTOUT pin is disabled
HPI control signal bit
•
HC = 0: Pullups/pulldowns on HPI control pins (HC0 and HC1) are
enabled
•
HC = 1: Pullups/pulldowns on HPI control pins (HC0 and HC1) are
disabled
HD
PC
PD
PA
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
HPI data bus bit
•
•
HD = 0: Bus holders on HPI data bus (pins HD[7:0]) are enabled
HD = 1: Bus holders on HPI data bus (pins HD[7:0]) are disabled
EMIF control signals
•
•
PC = 0: Bus holders and pullups on EMIF control pins are enabled
PC = 1: Bus holders and pullups on EMIF control pins are disabled
EMIF data bus signals
•
•
PD = 0: Bus holders on EMIF data bus (pins D[31:0]) are enabled
PD = 1: Bus holders on EMIF data bus (pins D[31:0]) are disabled
EMIF address bus signals
•
PA = 0: Bus holders on EMIF address bus (pins A[21:2]) are
enabled
•
PA = 1: Bus holders on EMIF address bus (pins A[21:2]) are
disabled
Functional Overview
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3.14 Internal Ports and System Registers
The 5502 includes three internal ports that interface the CPU core with the peripheral modules. Although
these ports cannot be directly controlled by user code, the registers associated with each port can be used
to monitor a number of error conditions that could be generated through illegal operation of the 5502. The
port registers are described in the following sections.
The 5502 also includes two registers that can be used to monitor and control several aspects of the
interface between the CPU and the system-level peripherals, these registers are also described in the
following sections.
3.14.1 XPORT Interface
The XPORT interfaces the CPU core to all peripheral modules. The XPORT will generate bus errors for
invalid accesses to any registers that fall under the ranges shown in Table 3-48. The INTERREN bit of the
XPORT Configuration Register (XCR) controls the bus error feature of the XPORT. The INTERR bit of the
XPORT Bus Error Register (XERR) is set to '1' when an error occurs during an access to a register listed
in Table 3-48. The EBUS and DBUS bits can be used to distinguish whether the error occurred during a
write or read access.
Table 3-48. I/O Addresses Under Scope of XPORT
I/O ADDRESS RANGE
0x0000–0x03FF
0x1400–0x17FF
0x2000–0x23FF
The PERITO bit of the XERR is used to indicate that a CPU, DMA, or HPI access to a disabled/idled
peripheral module has generated a time-out error. The time-out error feature is enabled through the
PERITOEN bit of the Time-Out Control Register (TOCR). A time-out error is generated when 512 clock
cycles pass without a response from the peripheral register.
The XPORT can be placed into idle by setting the XPORTI bit of the Idle Control Register (ICR) and
executing the IDLE instruction. When the XPORT is in idle, it will stop accepting new peripheral module
requests and it will also not check for internal I/O bus errors. If there is a request from the CPU core or a
peripheral module, the XPORT will not respond and hang. The ICR register will generate a bus error if the
XPORT is idled without the CPU or Master Port domains being in idle mode.
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3.14.1.1 XPORT Configuration Register (XCR)
The XPORT Configuration Register bit layout is shown in Figure 3-44 and the bits are described in
Table 3-49.
15
14
8
INTERREN
Reserved
R/W, 1
7
R, 0000000
0
Reserved
R, 00000000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-44. XPORT Configuration Register Layout (0x0100)
Table 3-49. XPORT Configuration Register Bit Field Description
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
INTERREN
15
R/W
1
INTERREN bit
•
INTERREN = 0:
The XPORT will not generate a bus error for invalid accesses to
registers listed in Table 3-48. Note that any invalid accesses to
these registers will hang the pipeline.
•
INTERREN = 1:
The XPORT will generate a bus error for invalid accesses to
registers listed in Table 3-48.(1) Note that when a bus error
occurs, any data returned by the read instruction will not be
valid.
Reserved
14-0
R
000000000000000
Reserved
(1) This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed
in idle without the CPU being in idle.
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3.14.1.2 XPORT Bus Error Register (XERR)
The XPORT Bus Error Register bit layout is shown in Figure 3-45 and the bits are described in
Table 3-50.
15
14
13
12
11
8
INTERR
Reserved
R, 00
PERITO
Reserved
R, 0000
R, 0
7
R, 0
5
4
3
2
0
Reserved
R, 000
EBUS
DBUS
Reserved
R, 000
R, 0
R, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-45. XPORT Bus Error Register Layout (0x0102)
Table 3-50. XPORT Bus Error Register Bit Field Description
BIT NAME
INTERR
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
15
R
0
INTERR bit
•
•
INTERR = 0: No error
INTERR = 1: An error occurred during an access to one of the
registers listed in Table 3-48.
Reserved
PERITO
14–13
12
R
R
00
0
Reserved
PERITO bit
•
•
PERITO = 0: No error
PERITO = 1: A time-out error occurred during an access to a
peripheral register.
Reserved
EBUS
11–5
4
R
R
0000000
0
Reserved
EBUS error bit(1)
•
•
EBUS = 0: No error
EBUS = 1: An error occurred during an EBUS access (write) to
one of the registers listed in Table 3-48.
DBUS
3
R
R
0
DBUS error bit(1)
•
•
DBUS = 0: No error
DBUS = 1: An error occurred during a DBUS access (read) to
one of the registers listed in Table 3-48.
Reserved
2–0
000
Reserved
(1) See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.
3.14.2 DPORT Interface
The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on
the EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write
posting registers, which are freely associated with E and F bus writes, exist within the DPORT and are
used to store the write address and data so that writes can be zero wait state for the CPU. External
memory writes will not generate stalls to the CPU unless the two write posting registers are filled. Write
posting is enabled by setting the WPE bit of the DCR to 1.
The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external
memory has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit
of the Time-Out Control Register (TOCR). This function is not recommended during normal operation of
the 5502.
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The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing
the IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a
request from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate
a bus error if the DPORT is idled without the CPU or Master Port domains being in idle.
3.14.2.1 DPORT Configuration Register (DCR)
The DPORT Configuration Register bit layout is shown in Figure 3-46 and the bits are described in
Table 3-51.
15
8
Reserved
R, 00000000
7
6
0
WPE
Reserved
R, 0000000
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-46. DPORT Configuration Register Layout (0x0200)
Table 3-51. DPORT Configuration Register Bit Field Description(1)
BIT NAME
Reserved
WPE
BIT NO.
15-8
7
ACCESS
R
RESET VALUE
DESCRIPTION
00000000
0
Reserved
Write Posting Enable bit(1)
R/W
•
•
WPE = 0: Write posting disabled
WPE = 1: Write posting enabled
Reserved
6-0
R
0000000
Reserved
(1) Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory.
3.14.2.2 DPORT Bus Error Register (DERR)
The DPORT Bus Error Register bit layout is shown in Figure 3-47 and the bits are described in
Table 3-52.
15
13
12
11
8
Reserved
R, 000
EMIFTO
Reserved
R, 0000
R, 0
7
0
Reserved
R, 0000000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-47. DPORT Bus Error Register Layout (0x0202)
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Table 3-52. DPORT Bus Error Register Bit Field Description
BIT NAME
Reserved
EMIFTO
BIT NO.
15-13
12
ACCESS
RESET VALUE
DESCRIPTION
R
R
000
0
Reserved
EMIFTO bit
•
•
EMIFTO = 0: No error
EMIFTO = 1: Error 1 error
Reserved
11-0
R
000000000000 Reserved
3.14.3 IPORT Interface
The IPORT interfaces the I-Cache to the EMIF module. The ICACHETO bit of the IPORT Bus Error
Register (IERR) can be used to determine if a time-out error has occurred during an ICACHE access to
external memory. The time-out feature is enabled through the EMIFTOEN bit of the Time-Out Control
Register (TOCR).
The IPORT can be placed into idle through the IPORTI bit of the Idle Control Register (ICR) and executing
the IDLE instruction. The IPORT will go into idle when there are no new requests from the ICACHE. When
the IPORT is in idle, it will stop accepting new requests from the CPU, it is important that the program flow
not use external memory in this case. If there are requests from the CPU, the IPORT will not respond and
hang. The ICR register will generate a bus error if the IPORT is idled without the CPU domain being in
idle.
3.14.3.1 IPORT Bus Error Register (IERR)
The IPORT Bus Error Register bit layout is shown in Figure 3-48 and the bits are described in Table 3-53.
15
7
13
12
11
8
Reserved
R, 000
ICACHETO
Reserved
R, 0000
R, 0
0
Reserved
R, 00000000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-48. IPORT Bus Error Register Layout (0x0302)
Table 3-53. IPORT Bus Error Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-13
12
ACCESS
RESET VALUE
DESCRIPTION
R
R
000
0
Reserved
ICACHETO
ICACHETO bit
•
•
ICACHETO = 0: No error
ICACHETO = 1: A time-out error occurred during an ICACHE
access to external memory.
Reserved
11-0
R
000000000000 Reserved
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3.14.4 System Configuration Register (CONFIG)
The System Configuration Register can be used to determine the operational state of the ICACHE. If the
ICACHE is not functioning, the CACHEPRES bit of the CONFIG register will be cleared. If the ICACHE is
functioning normally, this bit will be set.
The System Configuration Register bit layout is shown in Figure 3-49 and the bits are described in
Table 3-54.
15
8
Reserved
R, 10000010
7
6
5
4
3
0
Reserved
R, 00
CACHEPRES
Reserved
RW, 0(1)
Reserved
R, 0000
R, 0
LEGEND: R = Read, W = Write, n = value at reset
(1) This Reserved bit must be kept as zero during any writes to CONFIG.
Figure 3-49. System Configuration Register Layout (0x07FD)
Table 3-54. System Configuration Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-6
5
ACCESS
RESET VALUE
1000001000
0
DESCRIPTION
R
R
Reserved
CACHEPRES
ICACHE present
•
•
CACHEPRES = 0: ICACHE is not functioning
CACHEPRES = 1: ICACHE is enabled and working
Reserved
Reserved
4
R/W
R
0(1)
Reserved
Reserved
3-0
0000
(1) This Reserved bit must be kept as zero during any writes to CONFIG.
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3.14.5 Time-Out Control Register (TOCR)
The Time-Out Control Register can be used to select whether or not a time-out error is generated when
an access to a disabled/idled peripheral module occurs. If the CPU or DMA access a disabled/idle
peripheral module and 512 CPU clock cycles pass without an acknowledgement from the peripheral
module, then a time-out error will be sent to the corresponding module if bit 1 in the Time-Out Control
Register is set. A time-out error will generate a CPU bus error that can be serviced through software by
using the bus error interrupt (BERR) (see Section 3.17, Interrupts, for more information on interrupts). If
the DMA gets a time-out error, it will set the TIMEOUT bit in the DMA Status Register (DMACSR) and
generate
a time-out error that can be serviced through software by the CPU [see the
TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature number
SPRU613) for more information on using this feature of the DMA].
The Time-Out Control Register can also be used to select whether or not a time-out error is generated
when a memory access through the EMIF module stalls for more than 512 CPU clock cycles. It is
recommended that this feature not be used for it can cause unexpected results.
15
8
Reserved
R, 00000000
7
2
1
0
Reserved
R, 000000
EMIFTOEN
PERITOEN
R/W, 0
R/W, 1
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-50. Time-Out Control Register Layout (0x9000)
Table 3-55. Time-Out Control Register Bit Field Description
BIT NAME
Reserved
BIT NO.
15-2
1
ACCESS
R
RESET VALUE
DESCRIPTION
00000000000000 Reserved
EMIFTOEN
R/W
0
EMIF time-out control bit
•
EMIFTOEN = 0: A time-out error is not generated when an EMIF
access stalls for more than 512 CPU clock cycles.
•
EMIFTOEN = 1: A time-out error is generated when an EMIF
access stalls for more than 512 CPU clock cycles.
PERITOEN
0
R/W
1
Peripheral module time-out control bit
•
PERITOEN = 0: A time-out error is not generated when a CPU
access to a disabled/idle peripheral module stalls for more than
512 CPU clock cycles.
•
PERITOEN = 1: A time-out error is generated when a CPU
access to a disabled/idle peripheral module stalls for more than
512 CPU clock cycles.
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3.15 CPU Memory-Mapped Registers
The 5502 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to
4Fh. Table 3-56 provides a list of the CPU memory-mapped registers (MMRs) available. The
corresponding TMS320C54x™ (C54x™) CPU registers are also indicated where applicable.
Table 3-56. CPU Memory-Mapped Registers
C54X
REGISTER
C55X
REGISTER
WORD ADDRESS
(HEX)
C55x REGISTER DESCRIPTION
Interrupt Enable Register 0
BIT FIELD
IER
IFR
-
IER0
IFR0
ST0_55
ST1_55
ST3_55
-
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[31-16]
[39-32]
[15-0]
[31-16]
[39-32]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[7-0]
Interrupt Flag Register 0
Status Register 0
-
Status Register 1
-
Status Register 3
-
Reserved
ST0
ST1
AL
ST0
Status Register 0 (protected address for C54x code)
Status Register 1 (protected address for C54x code)
ST1
AC0L
AC0H
AC0G
AC1L
AC1H
AC1G
T3
AH
AG
BL
Accumulator 0
Accumulator 1
BH
BG
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
BK
BRC
RSA
REA
PMST
XPC
-
Temporary Register 3
TRN0
AR0
Transition Register 0
Auxiliary Register 0
AR1
Auxiliary Register 1
AR2
Auxiliary Register 2
AR3
Auxiliary Register 3
AR4
Auxiliary Register 4
AR5
Auxiliary Register 5
AR6
Auxiliary Register 6
AR7
Auxiliary Register 7
SP
Data Stack Pointer
BK03
BRC0
RSA0L
REA0L
PMST
XPC
-
Circular Buffer Size Register for AR[0-3]
Block Repeat Counter 0
Low Part of Block Repeat Start Address Register 0
Low Part of Block Repeat End Address Register 0
Status Register 3 (protected address for C54x code)
Program Counter Extension Register for C54x code
Reserved
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[31-16]
[39-32]
[15-0]
-
T0
Temporary Register 0
-
T1
Temporary Register 1
-
T2
Temporary Register 2
-
T3
Temporary Register 3
-
AC2L
AC2H
AC2G
CDP
Accumulator 2
-
-
-
Coefficient Data Pointer
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Table 3-56. CPU Memory-Mapped Registers (continued)
C54X
REGISTER
C55X
REGISTER
WORD ADDRESS
(HEX)
C55x REGISTER DESCRIPTION
BIT FIELD
-
-
-
-
AC3L
AC3H
AC3G
DPH
28
29
2A
2B
Accumulator 3
[15-0]
[31-16]
[39-32]
[6-0]
High Part of the Extended Data Page Register
(XDP = DPH:DP)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
Reserved
[6-0]
[6-0]
-
Reserved
DP
Data Page Register
[15-0]
[8-0]
PDP
Peripheral Data Page Register
BK47
BKC
Circular Buffer Size Register for AR[4-7]
Circular Buffer Size Register for CDP
Circular Buffer Start Address Register for AR[0-1]
Circular Buffer Start Address Register for AR[2-3]
Circular Buffer Start Address Register for AR[4-5]
Circular Buffer Start Address Register for AR[6-7]
Circular Buffer Start Address Register for CDP
Data Page Pointer Storage Location for 128-word Data Table
Transition Register 1
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[23-16]
[15-0]
[23-16]
[15-0]
[23-16]
[15-0]
[23-16]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[15-0]
[6-0]
BSA01
BSA23
BSA45
BSA67
BSAC
BIOS
TRN1
BRC1
BRS1
CSR
Block Repeat Counter 1
BRC1 Save Register
Computed Single Repeat Register
Block Repeat Start Address Register 0
RSA0H
RSA0L
REA0H
REA0L
RSA1H
RSA1L
REA1H
REA1L
RPTC
IER1
Block Repeat End Address Register 0
Block Repeat Start Address Register 1
Block Repeat End Address Register 1
Single Repeat Counter
Interrupt Enable Register 1
Interrupt Flag Register 1
Debug Interrupt Enable Register 0
Debug Interrupt Enable Register 0
Interrupt Vector Pointer
Interrupt Vector Pointer
Status Register 2
IFR1
DBIER0
DBIER1
IVPD
IVPH
ST2_55
SSP
System Stack Pointer
SP
Data Stack Pointer
SPH
High Part of the Extended Stack Pointers
(XSP = SPH:SP, XSSP = SPH:SSP)
-
CDPH
4F
High Part of the Extended Coefficient Data Pointer
(XCDP = CDPH:CDP)
[6-0]
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3.16 Peripheral Registers
Each 5502 device has a set of peripheral memory-mapped registers as listed in Table 3-57 through
Table 3-76. Peripheral registers are accessed using the port qualifier. For more information on the use of
the port qualifier, see the TMS320C55x Assembly Language Tools User’s Guide (literature number
SPRU280). Some registers use less than 16 bits. When reading these registers, unused bits are always
read as 0.
The user guides for each peripheral contain detailed information on the operation and the functions of
each of the peripheral registers (see Section 4.2, Documentation Support, for a list of documents
supporting each peripheral).
Table 3-57. Peripheral Bus Controller Configuration Registers
WORD ADDRESS
0x0000
REGISTER NAME
Reserved
DESCRIPTION
RESET VALUE(1)
0x0001
ICR
Idle Configuration Register
0000 0000 0000 0000
0000 0000 0000 0000
0x0002
ISTR
Idle Status Register
0x0003 to 0x000E
0x000F
Reserved
BOOT_MOD
Reserved
Reserved
XCR
Boot Mode Register (read only)
Value of GPIO[2:0] at reset
0x0010
0x0011
0x0100
XPORT Configuration Register
XPORT Bus Error Register
DPORT Configuration Register
DPORT Bus Error Register
IPORT Bus Error Register
System Configuration Register
Time-Out Control Register
1000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1000 0010 0000 0000
0000 0000 0000 0001
0x0102
XERR
0x0200
DCR
0x0202
DERR
0x0302
IERR
0x07FD
CONFIG
TOCR
0x9000
(1) x denotes a "don't care."
Table 3-58. External Memory Interface Registers
WORD ADDRESS
REGISTER NAME
EGCR1
DESCRIPTION
EMIF Global Control Register 1
EMIF Global Control Register 2
EMIF CE1 Space Control Register 1
EMIF CE1 Space Control Register 2
EMIF CE0 Space Control Register 1
EMIF CE0 Space Control Register 2
Reserved
RESET VALUE(1)
0010 0111 0111 1100
0000 0000 0000 1001
1111 1111 0001 1111
1111 1111 1111 1111
1111 1111 0000 0011
1111 1111 1111 1111
0x0800
0x0801
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
0x0808
0x0809
0x080A
0x080B
0x080C
0x080D
EGCR2
CE1_1
CE1_2
CE0_1
CE0_2
Reserved
CE2_1
CE2_2
CE3_1
CE3_2
SDC1
SDC2
EMIF CE2 Space Control Register 1
EMIF CE2 Space Control Register 2
EMIF CE3 Space Control Register 1
EMIF CE3 Space Control Register 2
EMIF SDRAM Control Register 1
EMIF SDRAM Control Register 2
1111 1111 1111 0011
1111 1111 1111 1111
1111 1111 1111 0011
1111 1111 1111 1111
1111 0000 0000 0000
0000 0011 0100 1000
(1) x denotes a "don't care."
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Table 3-58. External Memory Interface Registers (continued)
WORD ADDRESS
0x080E
0x080F
0x0810
0x0811
0x0812
:
REGISTER NAME
SDRC1
DESCRIPTION
EMIF SDRAM Refresh Control Register 1
EMIF SDRAM Refresh Control Register 2
EMIF SDRAM Extension Register 1
EMIF SDRAM Extension Register 2
Reserved
RESET VALUE(1)
1100 0101 1101 1100
0000 0000 0101 1101
0101 1111 1101 1111
0000 0000 0001 0111
SDRC2
SDX1
SDX2
:
0x0821
0x0822
0x0823
0x0824
0x0825
0x0826
0x0827
0x0828
0x0829
0x082A
0x082B
0x082C
:
Reserved
CE1_SC1
CE1_SC2
CE0_SC1
CE0_SC2
EMIF CE1 Secondary Control Register 1
EMIF CE1 Secondary Control Register 2
EMIF CE0 Secondary Control Register 1
EMIF CE0 Secondary Control Register 2
Reserved
0000 0000 0000 0010
0000 0000 0000 0000
0000 0000 0000 0010
0000 0000 0000 0000
Reserved
CE2_SC1
CE2_SC2
CE3_SC1
CE3_SC2
EMIF CE2 Secondary Control Register 1
EMIF CE2 Secondary Control Register 2
EMIF CE3 Secondary Control Register 1
EMIF CE3 Secondary Control Register 2
Reserved
0000 0000 0000 0010
0000 0000 0000 0000
0000 0000 0000 0010
0000 0000 0000 0000
:
0x0839
0x0840
0x0841
Reserved
CESCR1
CESCR2
EMIF CE Size Control Register 1
EMIF CE Size Control Register 2
0000 0000 0000 0000
0000 0000 0000 0000
108
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Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 3-59. DMA Configuration Registers
WORD ADDRESS
REGISTER NAME
DESCRIPTION
GLOBAL REGISTER
RESET VALUE
0x0E00
0x0E01
DMA_GCR(2:0)
DMA_GTCR(3:0)
DMA Global Control Register
DMA Global Timeout Control Register
CHANNEL #0 REGISTERS
000
0000
0x0C00
DMA_CSDP0
DMA Channel 0 Source Destination Parameters
Register
0000 0000 0000 0000
0x0C01
0x0C02
0x0C03
0x0C04
DMA_CCR0(15:0)
DMA_CICR0(5:0)
DMA_CSR0(6:0)
DMA_CSSA_L0
DMA Channel 0 Control Register
DMA Channel 0 Interrupt Control register
DMA Channel 0 Status register
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
DMA Channel 0 Source Start Address, lower bits,
register
Undefined
0x0C05
0x0C06
0x0C07
DMA_CSSA_U0
DMA_CDSA_L0
DMA_CDSA_U0
DMA Channel 0 Source Start Address, upper bits,
register
Undefined
Undefined
Undefined
DMA Channel 0 Source Destination Address, lower
bits, register
DMA Channel 0 Source Destination Address, upper
bits, register
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
DMA_CEN0
DMA_CFN0
DMA_CSFI0
DMA_CSEI0
DMA_CSAC0
DMA_CDAC0
DMA_CDEI0
DMA_CDFI0
DMA Channel 0 Element Number register
DMA Channel 0 Frame Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 0 Source Frame Index register
DMA Channel 0 Source Element Index register
DMA Channel 0 Source Address Counter register
DMA Channel 0 Destination Address Counter register
DMA Channel 0 Destination Element Index register
DMA Channel 0 Destination Frame Index register
CHANNEL #1 REGISTERS
0x0C20
DMA_CSDP1
DMA Channel 1 Source Destination Parameters
Register
0000 0000 0000 0000
0x0C21
0x0C22
0x0C23
0x0C24
DMA_CCR1(15:0)
DMA_CICR1(5:0)
DMA_CSR1(6:0)
DMA_CSSA_L1
DMA Channel 1 Control Register
DMA Channel 1 Interrupt Control register
DMA Channel 1 Status register
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
DMA Channel 1 Source Start Address, lower bits,
register
Undefined
0x0C25
0x0C26
0x0C27
DMA_CSSA_U1
DMA_CDSA_L1
DMA_CDSA_U1
DMA Channel 1 Source Start Address, upper bits,
register
Undefined
Undefined
Undefined
DMA Channel 1 Source Destination Address, lower
bits, register
DMA Channel 1 Source Destination Address, upper
bits, register
0x0C28
0x0C29
0x0C2A
0x0C2B
0x0C2C
0x0C2D
0x0C2E
0x0C2F
DMA_CEN1
DMA_CFN1
DMA_CSFI1
DMA_CSEI1
DMA_CSAC1
DMA_CDAC1
DMA_CDEI1
DMA_CDFI1
DMA Channel 1 Element Number register
DMA Channel 1 Frame Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 1 Source Frame Index register
DMA Channel 1 Source Element Index register
DMA Channel 1 Source Address Counter register
DMA Channel 1 Destination Address Counter register
DMA Channel 1 Destination Element Index register
DMA Channel 1 Destination Frame Index register
CHANNEL #2 REGISTERS
0x0C40
DMA_CSDP2
DMA Channel 2 Source Destination Parameters
Register
0000 0000 0000 0000
Functional Overview
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 3-59. DMA Configuration Registers (continued)
WORD ADDRESS
0x0C41
REGISTER NAME
DMA_CCR2(15:0)
DMA_CICR2(5:0)
DMA_CSR2(6:0)
DMA_CSSA_L2
DESCRIPTION
DMA Channel 2 Control Register
DMA Channel 2 Interrupt Control register
DMA Channel 2 Status register
RESET VALUE
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
0x0C42
0x0C43
0x0C44
DMA Channel 2 Source Start Address, lower bits,
register
Undefined
0x0C45
0x0C46
0x0C47
DMA_CSSA_U2
DMA_CDSA_L2
DMA_CDSA_U2
DMA Channel 2 Source Start Address, upper bits,
register
Undefined
Undefined
Undefined
DMA Channel 2 Source Destination Address, lower
bits, register
DMA Channel 2 Source Destination Address, upper
bits, register
0x0C48
0x0C49
0x0C4A
0x0C4B
0x0C4C
0x0C4D
0x0C4E
0x0C4F
DMA_CEN2
DMA_CFN2
DMA_CSFI2
DMA_CSEI2
DMA_CSAC2
DMA_CDAC2
DMA_CDEI2
DMA_CDFI2
DMA Channel 2 Element Number register
DMA Channel 2 Frame Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 2 Source Frame Index register
DMA Channel 2 Source Element Index register
DMA Channel 2 Source Address Counter register
DMA Channel 2 Destination Address Counter register
DMA Channel 2 Destination Element Index register
DMA Channel 2 Destination Frame Index register
CHANNEL #3 REGISTERS
0x0C60
DMA_CSDP3
DMA Channel 3 Source Destination Parameters
Register
0000 0000 0000 0000
0x0C61
0x0C62
0x0C63
0x0C64
DMA_CCR3(15:0)
DMA_CICR3(5:0)
DMA_CSR3(6:0)
DMA_CSSA_L3
DMA Channel 3 Control Register
DMA Channel 3 Interrupt Control register
DMA Channel 3 Status register
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
DMA Channel 3 Source Start Address, lower bits,
register
Undefined
0x0C65
0x0C66
0x0C67
DMA_CSSA_U3
DMA_CDSA_L3
DMA_CDSA_U3
DMA Channel 3 Source Start Address, upper bits,
register
Undefined
Undefined
Undefined
DMA Channel 3 Source Destination Address, lower
bits, register
DMA Channel 3 Source Destination Address, upper
bits, register
0x0C68
0x0C69
0x0C6A
0x0C6B
0x0C6C
0x0C6D
0x0C6E
0x0C6F
DMA_CEN3
DMA_CFN3
DMA_CSFI3
DMA_CSEI3
DMA_CSAC3
DMA_CDAC3
DMA_CDEI3
DMA_CDFI3
DMA Channel 3 Element Number register
DMA Channel 3 Frame Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 3 Source Frame Index register
DMA Channel 3 Source Element Index register
DMA Channel 3 Source Address Counter register
DMA Channel 3 Destination Address Counter register
DMA Channel 3 Destination Element Index register
DMA Channel 3 Destination Frame Index register
CHANNEL #4 REGISTERS
0x0C80
DMA_CSDP4
DMA Channel 4 Source Destination Parameters
Register
0000 0000 0000 0000
0x0C81
0x0C82
0x0C83
0x0C84
DMA_CCR4(15:0)
DMA_CICR4(5:0)
DMA_CSR4(6:0)
DMA_CSSA_L4
DMA Channel 4 Control Register
DMA Channel 4 Interrupt Control register
DMA Channel 4 Status register
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
DMA Channel 4 Source Start Address, lower bits,
register
Undefined
0x0C85
DMA_CSSA_U4
DMA Channel 4 Source Start Address, upper bits,
register
Undefined
110
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Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 3-59. DMA Configuration Registers (continued)
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE
Undefined
0x0C86
DMA_CDSA_L4
DMA Channel 4 Source Destination Address, lower
bits, register
0x0C87
DMA_CDSA_U4
DMA Channel 4 Source Destination Address, upper
bits, register
Undefined
0x0C88
0x0C89
0x0C8A
0x0C8B
0x0C8C
0x0C8D
0x0C8E
0x0C8F
DMA_CEN4
DMA_CFN4
DMA_CSFI4
DMA_CSEI4
DMA_CSAC4
DMA_CDAC4
DMA_CDEI4
DMA_CDFI4
DMA Channel 4 Element Number register
DMA Channel 4 Frame Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 4 Source Frame Index register
DMA Channel 4 Source Element Index register
DMA Channel 4 Source Address Counter register
DMA Channel 4 destination Address Counter register
DMA Channel 4 Destination Element Index register
DMA Channel 4 Destination Frame Index register
CHANNEL #5 REGISTERS
0x0CA0
DMA_CSDP5
DMA Channel 5 Source Destination Parameters
Register
0000 0000 0000 0000
0x0CA1
0x0CA2
0x0CA3
0x0CA4
DMA_CCR5(15:0)
DMA_CICR5(5:0)
DMA_CSR5(6:0)
DMA_CSSA_L5
DMA Channel 5 Control Register
DMA Channel 5 Interrupt Control register
DMA Channel 5 Status register
0000 0000 0000 0000
0000 0001 1000 0011
00 0000
DMA Channel 5 Source Start Address, lower bits,
register
Undefined
0x0CA5
0x0CA6
0x0CA7
DMA_CSSA_U5
DMA_CDSA_L5
DMA_CDSA_U5
DMA Channel 5 Source Start Address, upper bits,
register
Undefined
Undefined
Undefined
DMA Channel 5 Source Destination Address, lower
bits, register
DMA Channel 5 Source Destination Address, upper
bits, register
0x0CA8
0x0CA9
0x0CAA
0x0CAB
0x0CAC
0x0CAD
0x0CAE
0x0CAF
DMA_CEN5
DMA_CFN5
DMA_CSFI5
DMA_CSEI5
DMA_CSAC5
DMA_CDAC5
DMA_CDEI5
DMA_CDFI5
DMA Channel 5 Element Number register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 5 Frame Number register
DMA Channel 5 Source Frame Index register
DMA Channel 5 Source Element Index register
DMA Channel 5 Source Address Counter register
DMA Channel 5 Destination Address Counter register
DMA Channel 5 Destination Element Index register
DMA Channel 5 Destination Frame Index register
Functional Overview
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Table 3-60. Instruction Cache Registers
WORD ADDRESS
0x1400
REGISTER NAME
DESCRIPTION
ICache Global Control Register
ICGC
0x1401
0x1402
0x1403
ICFLARL
ICFLARH
ICWMC
ICache Flush Line Address Register Low Part
ICache Flush Line Address Register High Part
ICache N-Way Control Register
Table 3-61. Trace FIFO(1)
WORD ADDRESS
REGISTER NAME
DESCRIPTION
Trace Register Discontinuity Section
Trace Register Last PC Section
Trace LPC Offset Register 1
Trace LPC Offset Register 2
Trace Pointer Register
0x2000 - 0x203F
0x2040 - 0x204F
0x2050
TRC00 - TRC63
TRC64 - TRC79
TRC_LPCOFFSET1
TRC_LPCOFFSET2
TRC_PTR
0x2051
0x2052
0x2053
TRC_CNTL
Trace Control Register
0x2054
TRC_ID
Trace ID Register
(1) The Trace FIFO registers are used by the emulator only and do not require any intervention from the user.
Table 3-62. Timer Signal Selection Register
WORD ADDRESS
REGISTER NAME
TSSR
DESCRIPTION
RESET VALUE
0x8000
Timer Signal Selection Register
0000 0000 0000 0000
Table 3-63. Timers
WORD ADDRESS
0x1000
REGISTER NAME
GPTPID1_0
DESCRIPTION
Peripheral ID register 1, Timer #0
Peripheral ID register 2, Timer #0
Emulation Management Register, Timer #0
Timer Clock Speed Register, Timer #0
GPIO Interrupt Control Register, Timer #0
GPIO Enable Register, Timer #0
GPIO Data Register, Timer #0
RESET VALUE
0000 0111 0000 0001
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0x1001
GPTPID2_0
GPTEMU_0
GPTCLK_0
0x1002
0x1003
0x1004
GPTGPINT_0
GPTGPEN_0
GPTGPDAT_0
GPTGPDIR_0
GPTCNT1_0
GPTCNT2_0
GPTCNT3_0
GPTCNT4_0
GPTPRD1_0
GPTPRD2_0
GPTPRD3_0
GPTPRD4_0
GPTCTL1_0
GPTCTL2_0
0x1005
0x1006
0x1007
GPIO Direction Register, Timer #0
Timer Counter 1 Register, Timer #0
Timer Counter 2 Register, Timer #0
Timer Counter 3 Register, Timer #0
Timer Counter 4 Register, Timer #0
Period Register 1, Timer #0
0x1008
0x1009
0x100A
0x100B
0x100C
0x100D
0x100E
0x100F
0x1010
Period Register 2, Timer #0
Period Register 3, Timer #0
Period Register 4, Timer #0
Timer Control Register 1, Timer #0
Timer Control Register 2, Timer #0
0x1011
112
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Table 3-63. Timers (continued)
WORD ADDRESS
0x1012
0x2400
0x2401
0x2402
0x2403
0x2404
0x2405
0x2406
0x2407
0x2408
0x2409
0x240A
0x240B
0x240C
0x240D
0x240E
0x240F
0x2410
0x2411
0x2412
0x4000
0x4001
0x4002
0x4003
0x4004
0x4005
0x4006
0x4007
0x4008
0x4009
0x400A
0x400B
0x400C
0x400D
0x400E
0x400F
0x4010
0x4011
0x4012
0x4014
0x4015
REGISTER NAME
GPTGCTL1_0
GPTPID1_1
GPTPID2_1
GPTEMU_1
GPTCLK_1
GPTGPINT_1
GPTGPEN_1
GPTGPDAT_1
GPTGPDIR_1
GPTCNT1_1
GPTCNT2_1
GPTCNT3_1
GPTCNT4_1
GPTPRD1_1
GPTPRD2_1
GPTPRD3_1
GPTPRD4_1
GPTCTL1_1
GPTCTL2_1
GPTGCTL1_1
WDTPID1
DESCRIPTION
RESET VALUE
Global Timer Control Register 1, Timer #0
Peripheral ID register 1, Timer #1
0000 0000 0000 0000
0000 0111 0000 0001
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0111 0000 0001
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Peripheral ID register 2, Timer #1
Emulation Management Register, Timer #1
Timer Clock Speed Register, Timer #1
GPIO Interrupt Control Register, Timer #1
GPIO Enable Register, Timer #1
GPIO Data Register, Timer #1
GPIO Direction Register, Timer #1
Timer Counter 1 Register, Timer #1
Timer Counter 2 Register, Timer #1
Timer Counter 3 Register, Timer #1
Timer Counter 4 Register, Timer #1
Period Register 1, Timer #1
Period Register 2, Timer #1
Period Register 3, Timer #1
Period Register 4, Timer #1
Timer Control Register 1, Timer #1
Timer Control Register 2, Timer #1
Global Timer Control Register 1, Timer #1
Peripheral ID register 1, Watchdog Timer
Peripheral ID register 2, Watchdog Timer
Emulation Management Register, Watchdog Timer
Timer Clock Speed Register, Watchdog Timer
GPIO Interrupt Control Register, Watchdog Timer
GPIO Enable Register, Watchdog Timer
GPIO Data Register, Watchdog Timer
GPIO Direction Register, Watchdog Timer
Timer Counter 1 Register, Watchdog Timer
Timer Counter 2 Register, Watchdog Timer
Timer Counter 3 Register, Watchdog Timer
Timer Counter 4 Register, Watchdog Timer
Period Register 1, Watchdog Timer
Period Register 2, Watchdog Timer
Period Register 3, Watchdog Timer
Period Register 4, Watchdog Timer
Timer Control Register 1, Watchdog Timer
Timer Control Register 2, Watchdog Timer
Global Timer Control Register 1, Watchdog Timer
WD Timer Control Register 1, Watchdog Timer
WD Timer Control Register 2, Watchdog Timer
WDTPID2
WDTEMU
WDTCLK
WDTGPINT
WDTGPEN
WDTGPDAT
WDTGPDIR
WDTCNT1
WDTCNT2
WDTCNT3
WDTCNT4
WDTPRD1
WDTPRD2
WDTPRD3
WDTPRD4
WDTCTL1
WDTCTL2
WDTGCTL1
WDTWCTL1
WDTWCTL2
Functional Overview
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Table 3-64. Multichannel Serial Port #0
WORD ADDRESS
0x2800
0x2801
0x2802
0x2803
0x2804
0x2805
0x2806
0x2807
0x2808
0x2809
0x280A
0x280B
0x280C
0x280D
0x280E
0x280F
0x2810
0x2811
0x2812
0x2813
0x2814
0x2815
0x2816
0x2817
0x2818
0x2819
0x281A
0x281B
0x281C
0x281D
0x281E
0x281F
REGISTER NAME
DRR1_0
DESCRIPTION
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0001
0010 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #0
DRR2_0
DXR1_0
DXR2_0
SPCR1_0
SPCR2_0
RCR1_0
RCR2_0
XCR1_0
XCR2_0
SRGR1_0
SRGR2_0
MCR1_0
MCR2_0
RCERA_0
RCERB_0
XCERA_0
XCERB_0
PCR0
Data Receive Register 2, McBSP #0
Data Transmit Register 1, McBSP #0
Data Transmit Register 2, McBSP #0
Serial Port Control Register 1, McBSP #0
Serial Port Control Register 2, McBSP #0
Receive Control Register 1, McBSP #0
Receive Control Register 2, McBSP #0
Transmit Control Register 1, McBSP #0
Transmit Control Register 2, McBSP #0
Sample Rate Generator Register 1, McBSP #0
Sample Rate Generator Register 2, McBSP #0
Multichannel Control Register 1, McBSP #0
Multichannel Control Register 2, McBSP #0
Receive Channel Enable Register Partition A, McBSP #0
Receive Channel Enable Register Partition B, McBSP #0
Transmit Channel Enable Register Partition A, McBSP #0
Transmit Channel Enable Register Partition B, McBSP #0
Pin Control Register, McBSP #0
Reserved
RCERC_0
RCERD_0
XCERC_0
XCERD_0
RCERE_0
RCERF_0
XCERE_0
XCERF_0
RCERG_0
RCERH_0
XCERG_0
XCERH_0
Receive Channel Enable Register Partition C, McBSP #0
Receive Channel Enable Register Partition D, McBSP #0
Transmit Channel Enable Register Partition C, McBSP #0
Transmit Channel Enable Register Partition D, McBSP #0
Receive Channel Enable Register Partition E, McBSP #0
Receive Channel Enable Register Partition F, McBSP #0
Transmit Channel Enable Register Partition E, McBSP #0
Transmit Channel Enable Register Partition F, McBSP #0
Receive Channel Enable Register Partition G, McBSP #0
Receive Channel Enable Register Partition H, McBSP #0
Transmit Channel Enable Register Partition G, McBSP #0
Transmit Channel Enable Register Partition H, McBSP #0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
114
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Table 3-65. Multichannel Serial Port #1
WORD ADDRESS
0x2C00
0x2C01
0x2C02
0x2C03
0x2C04
0x2C05
0x2C06
0x2C07
0x2C08
0x2C09
0x2C0A
0x2C0B
0x2C0C
0x2C0D
0x2C0E
0x2C0F
0x2C10
0x2C11
0x2C12
0x2C13
0x2C14
0x2C15
0x2C16
0x2C17
0x2C18
0x2C19
0x2C1A
0x2C1B
0x2C1C
0x2C1D
0x2C1E
0x2C1F
REGISTER NAME
DRR1_1
DESCRIPTION
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0001
0010 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #1
DRR2_1
DXR1_1
DXR2_1
SPCR1_1
SPCR2_1
RCR1_1
RCR2_1
XCR1_1
XCR2_1
SRGR1_1
SRGR2_1
MCR1_1
MCR2_1
RCERA_1
RCERB_1
XCERA_1
XCERB_1
PCR1
Data Receive Register 2, McBSP #1
Data Transmit Register 1, McBSP #1
Data Transmit Register 2, McBSP #1
Serial Port Control Register 1, McBSP #1
Serial Port Control Register 2, McBSP #1
Receive Control Register 1, McBSP #1
Receive Control Register 2, McBSP #1
Transmit Control Register 1, McBSP #1
Transmit Control Register 2, McBSP #1
Sample Rate Generator Register 1, McBSP #1
Sample Rate Generator Register 2, McBSP #1
Multichannel Control Register 1, McBSP #1
Multichannel Control Register 2, McBSP #1
Receive Channel Enable Register Partition A, McBSP #1
Receive Channel Enable Register Partition B, McBSP #1
Transmit Channel Enable Register Partition A, McBSP #1
Transmit Channel Enable Register Partition B, McBSP #1
Pin Control Register, McBSP #1
Reserved
RCERC_1
RCERD_1
XCERC_1
XCERD_1
RCERE_1
RCERF_1
XCERE_1
XCERF_1
RCERG_1
RCERH_1
XCERG_1
XCERH_1
Receive Channel Enable Register Partition C, McBSP #1
Receive Channel Enable Register Partition D, McBSP #1
Transmit Channel Enable Register Partition C, McBSP #1
Transmit Channel Enable Register Partition D, McBSP #1
Receive Channel Enable Register Partition E, McBSP #1
Receive Channel Enable Register Partition F, McBSP #1
Transmit Channel Enable Register Partition E, McBSP #1
Transmit Channel Enable Register Partition F, McBSP #1
Receive Channel Enable Register Partition G, McBSP #1
Receive Channel Enable Register Partition H, McBSP #1
Transmit Channel Enable Register Partition G, McBSP #1
Transmit Channel Enable Register Partition H, McBSP #1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Functional Overview
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Table 3-66. Multichannel Serial Port #2
WORD ADDRESS
0x3000
0x3001
0x3002
0x3003
0x3004
0x3005
0x3006
0x3007
0x3008
0x3009
0x300A
0x300B
0x300C
0x300D
0x300E
0x300F
0x3010
0x3011
0x3012
0x3013
0x3014
0x3015
0x3016
0x3017
0x3018
0x3019
0x301A
0x301B
0x301C
0x301D
0x301E
0x301F
REGISTER NAME
DRR1_2
DESCRIPTION
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0001
0010 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #2
DRR2_2
DXR1_2
DXR2_2
SPCR1_2
SPCR2_2
RCR1_2
RCR2_2
XCR1_2
XCR2_2
SRGR1_2
SRGR2_2
MCR1_2
MCR2_2
RCERA_2
RCERB_2
XCERA_2
XCERB_2
PCR2
Data Receive Register 2, McBSP #2
Data Transmit Register 1, McBSP #2
Data Transmit Register 2, McBSP #2
Serial Port Control Register 1, McBSP #2
Serial Port Control Register 2, McBSP #2
Receive Control Register 1, McBSP #2
Receive Control Register 2, McBSP #2
Transmit Control Register 1, McBSP #2
Transmit Control Register 2, McBSP #2
Sample Rate Generator Register 1, McBSP #2
Sample Rate Generator Register 2, McBSP #2
Multichannel Control Register 1, McBSP #2
Multichannel Control Register 2, McBSP #2
Receive Channel Enable Register Partition A, McBSP #2
Receive Channel Enable Register Partition B, McBSP #2
Transmit Channel Enable Register Partition A, McBSP #2
Transmit Channel Enable Register Partition B, McBSP #2
Pin Control Register, McBSP #2
Reserved
RCERC_2
RCERD_2
XCERC_2
XCERD_2
RCERE_2
RCERF_2
XCERE_2
XCERF_2
RCERG_2
RCERH_2
XCERG_2
XCERH_2
Receive Channel Enable Register Partition C, McBSP #2
Receive Channel Enable Register Partition D, McBSP #2
Transmit Channel Enable Register Partition C, McBSP #2
Transmit Channel Enable Register Partition D, McBSP #2
Receive Channel Enable Register Partition E, McBSP #2
Receive Channel Enable Register Partition F, McBSP #2
Transmit Channel Enable Register Partition E, McBSP #2
Transmit Channel Enable Register Partition F, McBSP #2
Receive Channel Enable Register Partition G, McBSP #2
Receive Channel Enable Register Partition H, McBSP #2
Transmit Channel Enable Register Partition G, McBSP #2
Transmit Channel Enable Register Partition H, McBSP #2
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
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Table 3-67. HPI
WORD ADDRESS
0xA000
REGISTER NAME
PID LSW
DESCRIPTION
RESET VALUE(1)
PID [15:0]
PID [31:16]
—
—
0xA001
PID MSW
0xA002
HPWREMU
Power and Emulation Management Register
Reserved
0000 0000 0000 0000
0xA003
0xA004
HGPIOINT1
HGPIOINT2
HGPIOEN
General-Purpose I/O Interrupt Control Register 1
General-Purpose I/O Interrupt Control Register 2
General-Purpose I/O Enable Register
Reserved
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0xA005
0xA006
0xA007
0xA008
HGPIODIR1
HGPIODAT1
HGPIODIR2
HGPIODAT2
HGPIODIR3
HGPIODAT3
HPIC
General-Purpose I/O Direction Register 1
Reserved
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 1000
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0xA009
0xA00A
General-Purpose I/O Data Register 1
Reserved
0xA00B
0xA00C
General-Purpose I/O Direction Register 2
Reserved
0xA00D
0xA00E
General-Purpose I/O Data Register 2
Reserved
0xA00F
0xA010
General-Purpose I/O Direction Register 3
Reserved
0xA011
0xA012
General-Purpose I/O Data Register 3
Reserved
0xA013 - 0xA017
0xA018
Host Port Control Register
Reserved
0xA019
0xA01A
HPIAW
Host Port Write Address Register
Reserved
0xA01B
0xA01C
HPIAR
Host Port Read Address Register
Reserved
0xA01D - 0xA020
(1) x denotes a "don't care."
Table 3-68. GPIO
WORD ADDRESS
REGISTER NAME
IODIR
IODATA
DESCRIPTION
General-purpose I/O Direction Register
General-purpose I/O Data Register
Parallel GPIO Enable Register 0
Parallel GPIO Direction Register 0
Parallel GPIO Data Register 0
Parallel GPIO Enable Register 1
Parallel GPIO Direction Register 1
Parallel GPIO Data Register 1
Parallel GPIO Enable Register 2
Parallel GPIO Direction Register 2
Parallel GPIO Data Register 2
RESET VALUE(1)
0000 0000 0000 0000
0000 0000 xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0x3400
0x3401
0x4400
0x4401
0x4402
0x4403
0x4404
0x4405
0x4406
0x4407
0x4408
PGPIOEN0
PGPIODIR0
PGPIODAT0
PGPIOEN1
PGPIODIR1
PGPIODAT1
PGPIOEN2
PGPIODIR2
PGPIODAT2
(1) x denotes a "don't care."
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Table 3-69. Device Revision ID
WORD ADDRESS
0x3800 - 0x3803
0x3804
REGISTER NAME
Die ID
DESCRIPTION
Die ID
RESET VALUE(1)
Chip ID (LSW)
Chip ID (MSW)
Sub ID
Defines F# 3LS digits and PG rev
Defines F# 3MS digits
Defines subsytem ID
1001 0100 0110 xxxx
0x3805
0000 0111 0101 0001
0000 0000 0000 0000(2)
0x3806
0x3807
Cat ID
Defines catalog device
0101 0101 0000 0010 (5502h)
(1) x denotes a "don't care."
(2) Denotes single core
Table 3-70. I2C
WORD ADDRESS
REGISTER NAME
I2COAR(2)
I2CIER
DESCRIPTION
I2C Own Address Register
I2C Interrupt Enable Register
I2C Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Source Register
I2C General-Purpose Register (Not supported)
I2C Prescaler Register
RESET VALUE(1)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0100 0001 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0011 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
-
0x3C00
0x3C01
0x3C02
0x3C03
0x3C04
0x3C05
0x3C06
0x3C07
0x3C08
0x3C09
0x3C0A
0x3C0B
0x3C0C
0x3C0D
0x3C0E
-
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CGPIO
I2CPSC
PID1
I2C Peripheral ID Register 1
I2C Peripheral ID Register 2
I2C Transmit Shift Register
I2C Receive Shift Register
PID2
-
I2CXSR
I2CRSR
-
-
-
(1) x denotes a "don't care."
(2) Specifies a unique 5502 I2C address. This register is fully programmable in both 7-bit and 10-bit modes and must be set by the
programmer. When this device is used in conjunction with another I2C device, it must be programmed to the I2C slave address
(01011A2A1A0) allocated by Philips Semiconductor for the 5502 (allocation number: 1946). A2, A1, and A0 are programmable address
bits.
118
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Table 3-71. UART
WORD ADDRESS
REGISTER NAME
URRBR/
DESCRIPTION
RESET VALUE(1)
0x9C00
Receive Buffer Register
Transmit Holding Register
Divisor Latch LSB Register
xxxx xxxx
URTHR/
URDLL(2)
0x9C01
0x9C02
URIER/
Interrupt Enable Register
Divisor Latch MSB Register
0000 0000
URDLM(3)
URIIR/
Interrupt Identification Register
FIFO Control Register
0000 0001
0000 0000
URFCR(4)
0x9C03
0x9C04
0x9C05
0x9C07
0x9C08
0x9C09
0x9C0A
0x9C0B
0x9C0C
URLCR
Line Control Register
0000 0000
URMCR
URLSR
Modem Control Register
Line Status Register
0000 0000
0110 0000
URSCR
URDLL(2)
URDLM(3)
URPID1
URPID2
URPECR
Scratch Register
xxxx xxxx
Divisor Latch LSB Register
Divisor Latch MSB Register
Peripheral ID Register (LSW)
Peripheral ID Register (MSW)
–
–
–
–
Power and Emulation Control Register
0000 0000 0000 0000
(1) x denotes a "don't care."
(2) The registers URRBR, URTHR, and URDLL share one address. URDLL also has a dedicated address. When using the dedicated
address, the DLAB bit can be kept cleared, so that URRBR and URTHR are always selected at the shared address.
•
If DLAB = 0:
Read Only: URRBR
Write Only: URTHR
•
If DLAB = 1:
Read/Write: URDLL
(3) The registers URIER and URDLM share one address. URDLM also has a dedicated address. When using the dedicated address, the
DLAB bit can be kept cleared, so that URIER is always selected at the shared address.
•
If DLAB = 0:
Read/Write: URIER
•
If DLAB = 1:
Read/Write: URDLM
(4) The registers URIIR and URFCR share one address.
•
•
Read Only: URIIR
Write Only: URFCR
Table 3-72. External Bus Selection
WORD ADDRESS
0x6C00
REGISTER NAME
XBSR
XBCR
DESCRIPTION
External Bus Selection Register
External Bus Control Register
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 0000
0x8800
Table 3-73. Clock Mode Register
WORD ADDRESS
REGISTER NAME
CLKMD
DESCRIPTION
RESET VALUE
0x8C00
Clock Mode Control Register
0000 0000 0000 0000
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Table 3-74. CLKOUT Selector Register
WORD ADDRESS
REGISTER NAME
DESCRIPTION
CLKOUT Selection Register
RESET VALUE
0x8400
CLKOUTSR
0000 0000 0000 0010
Table 3-75. Clock Controller Registers
WORD ADDRESS
0x1C80
REGISTER NAME
DESCRIPTION
PLL Control Status Register
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 1011
0000 0000 0000 0000
1000 0000 0000 0000
1000 0000 0000 0011
1000 0000 0000 0011
1000 0000 0000 0011
0000 0000 0000 0000
0000 0000 0000 0000
PLLCSR
CK3SEL
PLLM
0x1C82
CLKOUT3 Select Register
PLL Multiplier Control Register
PLL Divider 0 Register
0x1C88
0x1C8A
PLLDIV0
PLLDIV1
PLLDIV2
PLLDIV3
OSCDIV1
WKEN
0x1C8C
PLL Divider 1 Register
0x1C8E
PLL Divider 2 Register
0x1C90
PLL Divider 3 Register
0x1C92
Oscillator Divider 1 Register
Oscillator Wakeup Control Register
0x1C98
Table 3-76. IDLE Control Registers
WORD ADDRESS
0x9400
REGISTER NAME
DESCRIPTION
Peripheral IDLE Control Register
Peripheral IDLE Status Register
Master IDLE Control Register
Master IDLE Status Register
RESET VALUE
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
PICR
PISTR
MICR
MISR
0x9401
0x9402
0x9403
3.17 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3-77. For
more information on setting up and using interrupts, please refer to the TMS320C55x DSP CPU
Reference Guide (literature number SPRU371).
Table 3-77. Interrupt Table
SOFTWARE
LOCATION
NAME
RESET
(TRAP)
PRIORITY
FUNCTION
(HEX BYTES)
EQUIVALENT
SINT0
0
0
1
Reset (hardware and software)
Nonmaskable interrupt
External interrupt #0
NMI
SINT1
SINT2
SINT3
SINT4
SINT5
SINT6
SINT7
SINT8
SINT9
8
INT0
10
18
20
28
30
38
40
48
3
INT2
5
External interrupt #2
TINT0
RINT0
RINT1
XINT1
LCKINT
DMAC1
6
Timer #0 interrupt
7
McBSP #0 receive interrupt
McBSP #1 receive interrupt
McBSP #1 transmit interrupt
PLL lock interrupt
9
10
11
13
DMA Channel #1 interrupt
120
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Table 3-77. Interrupt Table (continued)
SOFTWARE
(TRAP)
EQUIVALENT
LOCATION
(HEX BYTES)
NAME
PRIORITY
FUNCTION
DSPINT
SINT10
50
58
60
68
70
78
80
88
90
98
A0
A8
B0
B8
C0
C8
D0
D8
E0
E8
F0
F8
14
15
17
18
21
22
4
Interrupt from host
INT3/WDTINT(1)
RINT2
XINT2
DMAC4
DMAC5
INT1
SINT11
SINT12
SINT13
SINT14
SINT15
SINT16
SINT17
SINT18
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
SINT31
External interrupt #3 or Watchdog timer interrupt
McBSP #2 receive interrupt
McBSP #2 transmit interrupt
DMA Channel #4 interrupt
DMA Channel #5 interrupt
External interrupt #1
XINT0
DMAC0
–
8
McBSP #0 transmit interrupt
DMA Channel #0 interrupt
Software interrupt #19
12
16
19
20
23
24
2
DMAC2
DMAC3
TINT1
IIC
DMA Channel #2 interrupt
DMA Channel #3 interrupt
Timer #1 interrupt
I2C interrupt
BERR
DLOG
RTOS
–
Bus Error interrupt
25
26
27
28
29
30
31
Data Log interrupt
Real-time Operating System interrupt
Software interrupt #27
–
Software interrupt #28
–
Software interrupt #29
–
Software interrupt #30
Software interrupt #31
(1) WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.
3.17.1 IFR and IER Registers
The Interrupt Enable Registers (IER0 and IER1) control which interrupts will be masked or enabled during
normal operation. The Interrupt Flag Registers (IFR0 and IFR1) contain flags that indicate interrupts that
are currently pending.
The Debug Interrupt Enable Registers (DBIER0 and DBIER1) are used only when the CPU is halted in the
real-time emulation mode. If the CPU is running in real-time mode, the standard interrupt processing
(IER0/1) is used and DBIER0/1 are ignored.
A maskable interrupt enabled in DBIER0/1 is defined as a time-critical interrupt. When the CPU is halted
in the real-time mode, the only interrupts that are serviced are time-critical interrupts that are also enabled
in an interrupt enable register (IER0 or IER1).
Write the DBIER0/1 to enable or disable time-critical interrupts. To enable an interrupt, set its
corresponding bit. To disable an interrupt, clear its corresponding bit. Initialize these registers before using
the real-time emulation mode.
A DSP hardware reset clears IFR0/1, IER0/1, and DBIER0/1 to 0. A software reset instruction clears
IFR0/1 to 0 but does not affect IER0/1 and DBIER0/1.
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The bit layouts of these registers for each interrupt are shown in Figure 3-51 and Figure 3-52. For more
information on the IER, IFR, and DBIER registers, refer to the TMS320C55x DSP CPU Reference Guide
(literature number SPRU371).
15
14
13
12
11
10
9
8
RINT2/
UART
INT3/
DMAC5
DMAC4
XINT2
DSPINT
DMAC1
Reserved
WDTINT(1)
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
1
R/W, 0
0
7
6
5
4
3
2
XINT1
RINT1
RINT0
TINT0
INT2
INT0
Reserved
R, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
(1) WDTINT is generated only when the WDT interrupt pin is connected to INT3 through the TSSR.
Figure 3-51. IFR0, IER0, DBIFR0, and DBIER0 Registers Layout
15
11
10
9
8
Reserved
R, 0
RTOS
DLOG
BERR
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
I2C
TINT1
DMAC3
DMAC2
INT4
DMAC0
XINT0
INT1
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-52. IFR1, IER1, DBIFR1, and DBIER1 Registers Layout
3.17.2 Interrupt Timing
The external interrupts (NMI and INT) are synchronized to the CPU by way of a two-flip-flop synchronizer.
The interrupt inputs are sampled on falling edges of the CPU clock. A sequence on the interrupt pin of
1-0-0-0 on consecutive cycles is required for an interrupt to be detected. Therefore, the minimum low
pulse duration on the external interrupts on the 5502 is three CPU clock periods.
TIM0, TIM1, WDTOUT, and HPI.HAS can be configured to generate interrupts to the CPU. When they are
used for this function, these pins will generate the interrupt associated with that module, i.e., TIM0 will
generate TINT0, HPI.HAS will generate DSPINT, etc. Three SYSCLK1 clock cycles must be allowed to
pass between consecutive interrupts generated using the HPI.HAS signal; otherwise, the last interrupt will
be ignored(i.e., a sequence of 0-1-1-1-0 on consecutive cycles is required for consecutive interrupts). For
more information on configuring TIM0, TIM1, WDTOUT, and HPI.HAS as interrupt pins, please refer to the
TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for the timer pins and
to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number
SPRU620) for the HPI pin.
3.17.3 Interrupt Acknowledge
The IACK pin is used to indicate the receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated on the address bus. As the CPU fetches the first word or the software
vector, it generates the IACK signal, which clears the appropriate interrupt flag bit. The IACK signal will go
low for a total of one CPU clock pulse and then go high again. For maskable interrupts, note that the CPU
will not jump to an interrupt service routine if the appropriate interrupt enable bit is not set; consequently,
the IACK pin will not go low when the interrupt is generated.
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3.18 Notice Concerning TCK
Under certain conditions, the emulation hardware may corrupt the emulation control state machine or may
cause it to lose synchronization with the emulator software. When emulation commands fail as a result of
the problem, Code Composer Studio™ Integrated Development Environment (IDE) may be unable to start
or it may report errors when interacting with the TMS320C55x™ DSP (for example, when halting the CPU,
reaching a breakpoint, etc.).
This phenomenon is observed when an erroneous clock edge is generated from the TCK signal inside the
C55x™ DSP. This can be caused by several factors, acting independently or cumulatively:
•
•
•
TCK transition times (as measured between 2.4 V and 0.8 V) in excess of 3 ns.
Operating the C55x DSP in a socket, which can aggravate noise or glitches on the TCK input.
Poor signal integrity on the TCK line from reflections or other layout issues.
A TCK edge that can cause this problem might look similar to the one shown in Figure 3-53. A TCK edge
that does not cause the problem looks similar to the one shown in Figure 3-54. The key difference
between the two figures is that Figure 3-54 has a clean and sharp transition whereas Figure 3-53 has a
"knee" in the transition zone. Problematic TCK signals may not have a knee that is as pronounced as the
one in Figure 3-53. Due to the TCK signal amplification inside the chip, any perturbation of the signal can
create erroneous clock edges.
As a result of the faster edge transition, there is increased ringing in Figure 3-54. As long as the ringing
does not cross logic input thresholds (0.8 V for falling edges, and 2.4 V for rising edges), this ringing is
acceptable.
When examining a TCK signal for this issue, either in board simulation or on an actual board, it is very
important to probe the TCK line as close to the DSP input pin as possible. In simulation, it should not be
difficult to probe right at the DSP input. For most physical boards, this means using the via for the TCK
pad on the back side of the board. Similarly, ground for the probe should come from one of the nearby
ground pad vias to minimize EMI noise picked up by the probe.
4
3
2.5 V
2
1
0.6 V
0
-1
15
nanoseconds (ns)
0
5
10
20
Figure 3-53. Bad TCK Transition
Functional Overview
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4
3
2
1
0
2.5 V
0.6 V
-1
0
5
10
15
20
nanoseconds (ns)
Figure 3-54. Good TCK Transition
As the problem may be caused by one or more of the above factors, one or more of the steps outlined
below may be necessary to fix it:
•
•
Avoid using a socket
Ensure the board design achieves rise times and fall times of less than 3 ns with clean monotonic
edges for the TCK signal.
•
For designs where TCK is supplied by the emulation pod, implement noise filtering circuitry on the
target board. A sample circuit is shown in Figure 3-55.
3.3 V
XDS TRST
XDS EMU1
XDS TMS
XDS TDI
1
3
5
7
9
2
4
TMS
TDI
TRST
XDS TDO
XDS TCK RTN
XDS TCK
8
TDO
10
12
14
11
13
XDS EMU0
EMU1/OFF
EMU0
3.3 V
3.3 V
0.1
mF
0.1
mF
R32
33 W
TCK
SN74LVC1G32
SN74LVC1G32
Figure 3-55. Sample Noise Filtering Circuitry
124
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4
Support
4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
4.1.1 Initialization Requirements for Boundary Scan Test
The TMS320VC5502 uses the JTAG port for boundary scan tests, emulation capability and factory test
purposes. To use boundary scan test, the EMU0 and EMU1/OFF pins must be held HIGH through a rising
edge of the TRST signal prior to the first scan. This operation selects the appropriate TAP control for
boundary scan. If at any time during a boundary scan test a rising edge of TRST occurs when EMU0 or
EMU1/OFF are not high, a factory test mode may be selected preventing boundary scan test from being
completed. For this reason, it is recommended that EMU0 and EMU1/OFF be pulled or driven high at all
times during boundary scan test.
4.1.2 Boundary Scan Description Language (BSDL) Model
BSDL models are available on the web in the TMS320VC5502 product folder under the “simulation
models” section.
4.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family of devices from product announcement
through applications development. The following types of documentation are available to support the
design and use of the TMS320C5000™ platform of DSPs:
•
•
•
•
•
Device-specific data sheets
Complete user's guides
Development support tools
Hardware and software application reports
MicroStar BGA™ Packaging Reference Guide (literature number SSYZ015)
TMS320C55x reference documentation that includes, but is not limited to, the following:
•
•
•
•
•
•
•
•
TMS320C55x DSP CPU Reference Guide (literature number SPRU371)
TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374)
TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375)
TMS320C55x DSP Programmer's Guide (literature number SPRU376)
TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280)
TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)
TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)
TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide
(literature number SPRU146)
•
•
TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)
TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (literature
number SPRU613)
•
•
•
•
•
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Refer-
ence Guide (literature number SPRU592)
TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (literature number
SPRU621)
TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide
(literature number SPRU597)
TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number
SPRZ020D or later)
TMS320VC5501/02 Power Consumption Summary Application Report (literature number SPRA993)
Support
125
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
The reference guides describe in detail the TMS320C55x™ DSP products currently available and the
hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com
uniform resource locator (URL).
4.3 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (e.g., TMS320VC5502). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
126
Support
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5
Specifications
5.1 Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5502 DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
5.2 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted)(1)(2)(3)
Supply voltage I/O range, DVDD
Supply voltage core range, CVDD
Input voltage range, VI
–0.3 V to 4.0 V
–0.3 V to 2.0 V
–0.3 V to 4.5 V
–0.3 V to 4.5 V
–40°C to 85°C
–55°C to 150°C
Output voltage range, Vo
Operating case temperature range, TC
Storage temperature range, Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All supply voltage values (core and I/O) are with respect to VSS
.
(3) Figure 5-1 provides the test load circuit values for a 3.3-V device. Measured timing information contained in this data manual is based
on the test load setup and conditions shown in Figure 5-1.
5.3 Recommended Operating Conditions
MIN NOM
MAX UNIT
DVDD
CVDD
PVDD
VSS
Device supply voltage, I/O
Device supply voltage, core
Device supply voltage, PLL
Supply voltage, GND
3.0
1.20
3.0
3.3
1.26
3.3
0
3.6
1.32
3.6
V
V
V
V
Hysteresis inputs
DVDD = 3.0 – 3.6 V
2.2
2
DVDD + 0.3
DVDD + 0.3
0.8
VIH
High-level input voltage, I/O
Low-level input voltage, I/O
V
V
All other inputs
DVDD = 3.0 – 3.6 V
Hysteresis inputs
DVDD = 3.0 – 3.6 V
–0.3
– 0.3
VIL
All other inputs
DVDD = 3.0 – 3.6 V
0.8
IOH
IOL
TC
High-level output current
Low-level output current
Operating case temperature
All outputs
All outputs
–300
1.5
µA
mA
°C
–40
85
Specifications
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5.4 Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted)
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
DVDD = 3.3 ± 0.3 V,
IOH = MAX
IOL = MAX
VOH
VOL
2.4
V
0.4
V
Bus holders enabled
DVDD = MAX,
VO = VSS to DVDD
Output-only or input/output pins
with bus holders
–300
300
Input current for
outputs in high im-
pedance
IIZ
µA
All other output-only or
input/output pins
DVDD = MAX,
VI = VSS to DVDD
–5
–5
5
300
50
DVDD = MAX,
VI = VSS to DVDD
Input pins with internal pulldown
X2/CLKIN
DVDD = MAX,
VI = VSS to DVDD
–50
II
Input current
µA
Pullup enabled
DVDD = MAX,
VI = VSS to DVDD
Input pins with internal pullup
All other input-only pins
–300
–5
5
5
DVDD = MAX,
VI = VSS to DVDD
CVDD = Nominal
CPU clock = 300 MHz
TC = 25°C
IDDC
IDDD
IDDP
CVDD supply current(1)
DVDD supply current(1)
PVDD supply current(1)
239
mA
mA
mA
DVDD = Nominal
CPU clock = 300 MHz
TC = 25°C
39
11
PVDD = Nominal
20-MHz clock input,
APLL mode = x15
Ci
Input capacitance
Output capacitance
3
3
pF
pF
Co
(1) Current draw is highly application-dependent. The power numbers quoted here are for the sample application described in the
TMS320VC5501/02 Power Consumption Summary application report (literature number SPRA993). The spreadsheet provided with the
application report can be used to estimate the power consumption for a particular application. The spreadsheet also contains the current
consumption that can be expected when running the DSP in its idle configurations.
The sample application can be summarized as follows:
•
•
•
Case temperature: 25°C
APLL: 300 MHz
CPU: 85% utilization
–
–
Instruction cache enabled
CLKOUT off
•
EMIF: 75 MHz, 118% utilization, 100% writes, 32 bits, 100% switching
ECLKOUT1 and ECLKOUT2: Off
–
•
•
HPI: 5Mwords/second, 100% utilization, 100% writes, 100% switching
DMA:
–
–
–
–
–
Channel 0: 35% utilization, 32-bit elements, 100% switching (for internal memory to external memory transfers)
Channel 1: 1.56% utilization, 32-bit elements, 100% switching (for internal memory to McBSP0 transfers)
Channel 2: 1.56% utilization, 32-bit elements, 100% switching (for McBSP1 to internal memory transfers)
Channels 3 and 4: 0% utilization (reserved for UART transfers)
Channel 5: 60% utilization (for internal memory to internal memory transfers using Watchdog Timer event)
•
•
•
•
•
•
McBSP0: 25 MHz, 100% utilization, 100% switching
Timer0: 5 MHz, 100% utilization, 100% switching
Timer1: 10 MHz, 100% utilization, 100% switching
WD Timer: 30 MHz, 100% utilization, 100% switching
UART: 9600 baud, 100% utilization
All other peripherals use 0 MHz, 0% utilization
128
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see Note A)
Device Pin
(see Note A)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The
transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data
sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. 3.3-V Test Load Circuit
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in
accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don't care level
Specifications
129
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Fixed-Point Digital Signal Processor
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5.6 Clock Options
This section provides the timing requirements and switching characteristics for the various clock options available
on the 5502.
5.6.1 Internal System Oscillator With External Crystal
The 5502 includes an internal oscillator which can be used in conjunction with an external crystal to generate the
input clock to the DSP. The oscillator requires an external crystal connected across the X1 and X2/CLKIN pins. If
the internal oscillator is not used, an external clock source must be applied to the X2/CLKIN pin and the X1 pin
should be left unconnected. Since the internal oscillator can be used as a clock source to the PLL, the crystal
oscillation frequency can be multiplied to generate the input clock to the different clock groups of the DSP.
GPIO4 is sampled on the rising edge of the reset signal to set the state of the CLKMD0 bit of the Clock Mode
Control Register (CLKMD), which in turns, determines the clock source for the DSP. The CLKMD0 bit selects
either the internal oscillator output (OSCOUT) or the X2/CLKIN pin as the input clock source for the DSP. If
GPIO4 is low at reset, the CLKMD0 bit will be set to '0' and the internal oscillator and the external crystal
generate the input clock for the DSP. If GPIO4 is high, the CLKMD0 bit will be set to '1' and the input clock will
be taken directly from the X2/CLKIN pin.
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series
resistance (ESR) as specified in Table 5-1. The connection of the required circuit is shown in Figure 5-2. Under
some conditions, all the components shown are not required. The capacitors, C1 and C2, should be chosen such
that the equation below is satisfied. CL in the equation is the load specified for the crystal that is also specified in
Table 5-1.
C1C2
CL +
(C1 ) C2)
X2/CLKIN
X1
R
S
Crystal
C
1
C
2
Figure 5-2. Internal System Oscillator With External Crystal
Table 5-1. Recommended Crystal Parameters
MAXIMUM ESR
SPECIFICATIONS (Ω)
MAXIMUM
CSHUNT (pF)
FREQUENCY RANGE (MHz)
CLOAD (pF)
RS (kΩ)
20-15
15–12
12–10
10–8
8–6
40
40
40
60
60
80
10
16
16
18
18
18
7
7
7
7
7
7
0
0
2.8
2.2
8.8
14
6–5
130
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum ESR
might seem to meet these specifications. However, it is recommended that crystals with actual maximum ESR
specifications as shown in Table 5-1 be used since this will result in maximum crystal performance reliability.
5.6.2 Layout Considerations
Since parasitic capacitance, inductance, and resistance can be significant in this and any circuit, good PC board
layout practices should always be observed when planning trace routing to the discrete components used in this
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to
the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible after
routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should be run
between these two signal lines. This also helps to minimize stray capacitance between these two signals.
Specifications
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5.6.3 Clock Generation in Bypass Mode (APLL Disabled)
Table 5-2 and Table 5-3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-3).
Table 5-2. CLKIN in Bypass Mode Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
MAX
MIN
MAX
(2)
(2)
C7 tc(CI)
C8 tf(CI)
Cycle time, CLKIN(1)
Fall time, CLKIN
APLL Synthesis Disabled
20
20
ns
ns
ns
ns
ns
10
10
10
10
C9 tr(CI)
Rise time, CLKIN
C10 tw(CIL)
C11 tw(CIH)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
0.4 * tc(CI)
0.4 * tc(CI)
0.4 * tc(CI)
0.4 * tc(CI)
(1) If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5-1.
(2) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
Table 5-3. CLKOUT in Bypass Mode Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
Cycle time, CLKOUT
UNIT
MIN
TYP
MAX
(1)
(2)
C1 tc(CO)
C3 tf(CO)
C4 tr(CO)
C5 tw(COL)
C6 tw(COH)
20
K * tc(CI)
ns
ns
ns
ns
ns
Fall time, CLKOUT
3
3
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
K * tc(CI) /2 – 1
K * tc(CI) /2 – 1
K * tc(CI) /2 + 1
K * tc(CI) /2 + 1
(1) K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and
SYSCLK1 is set to the CPU clock divided by four, use K = 4.
(2) This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies
approaching 0 Hz.
C9
C8
C10
C11
C7
CLKIN
C6
C3
C4
C1
C5
CLKOUT
(A ) The relationship of CLKIN to CLKOUT depends on the system clock selected to drive CLKOUT. The waveform relationship
shown in this figure is intended to illustrate the timing parameters only and may differ based on configuration.
Figure 5-3. Bypass Mode Clock Timings
132
Specifications
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled)
The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N to
generate the internal CPU clock cycle. The synthesis factor is determined by:
M
D0
N +
where:
•
•
M = the multiply factor set in the PLLM field of the PLL Multiplier Control Register (PLLM)
D0 = the divide factor set in the PLLDIV0 field of the PLL Divider 0 Register (PLLDIV0)
Valid values for M are (multiply by) 2 to 15. Valid values for D0 are (divide by) 1 – 32.
For detailed information on clock generation configuration, see Section 3.10, System Clock Generator.
Table 5-4 and Table 5-5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-4).
Table 5-4. CLKIN in Lock Mode Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
MAX
C7
C8
C9
tc(CI)
tf(CI)
tr(CI)
Cycle time, CLKIN(1)
Fall time, CLKIN
APLL synthesis enabled
10(2)
83.3
10
ns
ns
ns
Rise time, CLKIN
10
(1) If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5-1.
(2) The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is
within the specified range [tc(CO)].
Table 5-5. CLKOUT in Lock Mode Switching Characteristics
VC5502-200
VC5502-300
TYP
K * tc(CI)/N(1)
NO.
PARAMETER
UNIT
MIN
MAX
C1 tc(CO)
C3 tf(CO)
C4 tr(CO)
C5 tw(COL)
C6 tw(COH)
Cycle time, CLKOUT
6.66
14.29
ns
ns
ns
ns
ns
Fall time, CLKOUT
3
3
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
K * tc(CI) /2N – 1
K * tc(CI) /2N – 1
K * tc(CI) /2N + 1
K * tc(CI) /2N + 1
(1) N = Clock frequency synthesis factor. K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when
SYSCLK1 is selected as CLKOUT and SYSCLK1 is set to the CPU clock divided by four, use K = 4.
Specifications
133
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C8
C9
C7
CLKIN
C3
C5
C6
C1
C4
CLKOUT
Bypass Mode
(A ) The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen for the APLL synthesis and on the system
clock selected to drive CLKOUT. The waveform relationship shown in this figure is intended to illustrate the timing parameters only and may
differ based on configuration.
Figure 5-4. External Multiply-by-N Clock Timings
5.6.5 EMIF Clock Options
Table 5-6 through Table 5-8 assume testing over recommended operating conditions (see Figure 5-5 through
Figure 5-7).
Table 5-6. EMIF Timing Requirements for ECLKIN(1)(2)
VC5502-200
VC5502-300
MIN MAX
10 16P ns
NO.
UNIT
E7 tc(EKI)
E8 tw(EKIH)
E9 tw(EKIL)
E10 tt(EKI)
Cycle time, ECLKIN
Pulse duration, ECLKIN high
Pulse duration, ECLKIN low
Transition time, ECLKIN
0.4 * tc(EKI)
ns
ns
ns
0.4 * tc(EKI)
2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIHMIN.
Table 5-7. EMIF Switching Characteristics for ECLKOUT1(1)(2)(3)
VC5502-200
VC5502-300
NO.
PARAMETER
Cycle time, ECLKOUT1
UNIT
MIN
E – 1
MAX
E1
E2
E3
E4
E5
E6
tc(EKO1)
E + 1
EH + 1
EL + 1
1
ns
ns
ns
ns
ns
ns
tw(EKO1H)
tw(EKO1L)
Pulse duration, ECLKOUT1 high
EH – 1
EL – 1
Pulse duration, ECLKOUT1 low
tt(EKO1)
Transition time, ECLKOUT1
td(EKIH-EKO1H)
td(EKIL-EKO1L)
Delay time, ECLKIN high to ECLKOUT1 high
Delay time, ECLKIN low to ECLKOUT1 low
3
3
13
13
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.
134
Specifications
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
E7
E10
E8
ECLKIN
E9
E10
Figure 5-5. ECLKIN Timings for EMIF
ECLKIN
E1
E6
E2
E4
E4
E3
E5
ECLKOUT1
Figure 5-6. ECLKOUT1 Timings for EMIF Module
Table 5-8. EMIF Switching Characteristics for ECLKOUT2(1)(2)
VC5502-200
VC5502-300
NO.
PARAMETER
Cycle time, ECLKOUT2
UNIT
MIN
MAX
NE + 1
0.5NE + 1
0.5NE + 1
1
E11 tc(EKO2)
NE – 1
ns
ns
ns
ns
ns
ns
E12 tw(EKO2H)
E13 tw(EKO2L)
E14 tt(EKO2)
Pulse duration, ECLKOUT2 high
0.5NE – 1
Pulse duration, ECLKOUT2 low
0.5NE – 1
Transition time, ECLKOUT2
E15 td(EKIH-EKO2H)
E16 td(EKIH-EKO2L)
Delay time, ECLKIN high to ECLKOUT2 high
Delay time, ECLKIN high to ECLKOUT2 low
3
3
13
13
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.
N = the EMIF input clock divider; N = 1, 2, or 4.
E16
E15
ECLKIN
E11
E12
E14
E14
E13
ECLKOUT2
Figure 5-7. ECLKOUT2 Timings for EMIF Module
Specifications
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5.7 Memory Timings
5.7.1 Asynchronous Memory Timings
Table 5-9 and Table 5-10 assume testing over recommended operating conditions (see Figure 5-8 and
Figure 5-9).
Table 5-9. Asynchronous Memory Cycle Timing Requirements for ECLKIN(1)(2)
VC5502-200
VC5502-300
NO.
UNIT
MIN
6
MAX
A3
A4
A6
A7
tsu(EDV-AREH)
th(AREH-EDV)
tsu(ARDY-EKO1H)
th(EKO1H-ARDY)
Setup time, EMIF.Dx valid before EMIF.ARE high
Hold time, EMIF.Dx valid after EMIF.ARE high
Setup time, EMIF.ARDY valid before ECLKOUT1 high
Hold time, EMIF.ARDY valid after ECLKOUT1 high
ns
ns
ns
ns
1
3.5
1
(1) To ensure data setup time, simply program the strobe width wide enough. EMIF.ARDY is internally synchronized. The EMIF.ARDY
signal is recognized in the cycle for which the setup and hold time is met. To use EMIF.ARDY as an asynchronous input, the pulse width
of the EMIF.ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIF CE space control registers.
Table 5-10. Asynchronous Memory Cycle Switching Characteristics for ECLKOUT1(1)(2)(3)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
A1
A2
A5
A8
A9
tosu(SELV-AREL)
toh(AREH-SELIV)
td(EKO1H-AREV)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
Output setup time, select signals valid to EMIF.ARE low
Output hold time, EMIF.ARE high to select signals invalid
Delay time, ECLKOUT1 high to EMIF.ARE valid
RS * E – 1.5
ns
ns
ns
ns
ns
ns
RH * E – 1.5
1.5
5
5
Output setup time, select signals valid to EMIF.AWE low
Output hold time, EMIF.AWE high to select signals invalid
Delay time, ECLKOUT1 high to EMIF.AWE valid
WS * E – 1.5
WH * E – 1.5
1.5
A10 td(EKO1H-AWEV)
(1) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIF CE space control registers.
(2) E = ECLKOUT1 period in ns for EMIF.
(3) Select signals for EMIF include: EMIF.CEx, EMIF.BE[3:0], EMIF.A[21:2], and EMIF.AOE; and for EMIF writes, include EMIF.D[31:0].
136
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Setup = 2
Strobe = 3
Not Ready
Hold = 2
ECLKOUT1
EMIF.CEx
A1
A1
A1
A2
A2
A2
EMIF.BE[3:0]
EMIF.A[21:2]
BE
Address
A3
A4
EMIF.D[31:0]
A1
A5
A2
A5
Read Data
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A7
A7
A6
A6
EMIF.ARDY
A. EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals),
EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses.
Figure 5-8. Asynchronous Memory Read Timings
Specifications
137
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Setup = 2
Hold = 2
Strobe = 3
Not Ready
ECLKOUT1
A8
A9
A9
A9
EMIF.CEx
A8
EMIF.BE[3:0]
BE
A8
EMIF.A[21:2]
Address
Write Data
A8
A9
EMIF.D[31:0]
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
A10
A10
EMIF.AWE/SWE/SDWE
(see Note A)
A7
A7
A6
A6
EMIF.ARDY
A. EMIF.AOE/SOE/SDRAS, EMIF.ARE/SADS/SDCAS/SRE, and EMIF.AWE/SWE/SDWE operate as EMIF.AOE (identified under select signals),
EMIF.ARE, and EMIF.AWE, respectively, during asynchronous memory accesses.
Figure 5-9. Asynchronous Memory Write Timings
138
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.7.2 Programmable Synchronous Interface Timings
Table 5-11 and Table 5-12 assume testing over recommended operating conditions (see Figure 5-10 through
Figure 5-12).
Table 5-11. Programmable Synchronous Interface Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
2
MAX
PS6 tsu(EDV-EKOxH)
PS7 th(EKOxH-EDV)
Setup time, read EMIF.Dx valid before ECLKOUTx high
Hold time, read EMIF.Dx valid after ECLKOUTx high
ns
ns
1.5
Table 5-12. Programmable Synchronous Interface Switching Characteristics(1)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
PS1 td(EKOxH-CEV)
PS2 td(EKOxH-BEV)
PS3 td(EKOxH-BEIV)
PS4 td(EKOxH-EAV)
PS5 td(EKOxH-EAIV)
PS8 td(EKOxH-ADSV)
PS9 td(EKOxH-OEV)
PS10 td(EKOxH-EDV)
PS11 td(EKOxH-EDIV)
PS12 td(EKOxH-WEV)
Delay time, ECLKOUTx high to EMIF.CEx valid
Delay time, ECLKOUTx high to EMIF.BEx valid
Delay time, ECLKOUTx high to EMIF.BEx invalid
Delay time, ECLKOUTx high to EMIF.Ax valid
Delay time, ECLKOUTx high to EMIF.Ax invalid
Delay time, ECLKOUTx high to EMIF.SADS/SRE valid
Delay time, ECLKOUTx high to, EMIF.SOE valid
Delay time, ECLKOUTx high to EMIF.Dx valid
Delay time, ECLKOUTx high to EMIF.Dx invalid
Delay time, ECLKOUTx high to EMIF.SWE valid
0.8
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
7
0.8
0.8
0.8
7
7
7
0.8
0.8
7
(1) The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):
•
•
•
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final
command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active
(CEEXT = 1).
•
•
Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with
deselect cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
Specifications
139
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
READ latency = 2
(see Note B)
ECLKOUTx
PS1
PS1
EMIF.CEx
(see Note A)
PS2
BE1
PS3
EMIF.BE[3:0]
EMIF.A[21:2]
EMIF.D[31:0]
BE2
BE3
A3
BE4
PS5
E
PS4
A1
A2
A4
PS6
PS7
Q2
Q1
Q3
Q4
PS8
PS9
PS8
EMIF.ARE/SADS/SDCAS/SRE
(see Note C)
PS9
EMIF.AOE/SOE/SDRAS
(see Note C)
EMIF.AWE/SWE/SDWE
(see Note C)
A. The read latency and the length of EMIF.CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE
Secondary Control Registers (CEx_SC1, CEx_SC2). In the figure, SYNCRL = 2 and CEEXT = 0.
B. The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):
− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
− EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has
been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).
− Functionof EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect
cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).
− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
C. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and
EMIF.SWE, respectively, during programmable synchronous interface accesses.
Figure 5-10. Programmable Synchronous Interface Read Timings (With Read Latency = 2)
140
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
ECLKOUTx
PS1
PS1
PS3
EMIF.CEx
(see Note A)
PS2
BE1
EMIF.BE[3:0]
EMIF.A[21:2]
EMIF.D[31:0]
BE2
A2
BE3
A3
BE4
A4
PS5
PS4
A1
PS10
PS10
Q1
PS11
PS8
Q2
Q3
Q4
PS8
EMIF.ARE/SADS/SDCAS/SRE
(see Note B)
EMIF.AOE/SOE/SDRAS
(see Note B)
PS12
PS12
EMIF.AWE/SWE/SDWE
(see Note B)
A. The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF
CE Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 0 and CEEXT = 0.
B. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and
EMIF.SWE, respectively, during programmable synchronous interface accesses.
Figure 5-11. Programmable Synchronous Interface Write Timings (With Write Latency = 0)
Write Latency = 1
(see Note B)
ECLKOUTx
PS1
PS1
EMIF.CEx
(see Note A)
PS3
PS5
PS2
BE1
EMIF.BE[3:0]
EMIF.A[21:2]
EMIF.D[31:0]
BE2
BE3
A3
BE4
A4
PS4
A1
A2
PS10
PS10
PS11
PS8
Q1
Q2
Q3
Q4
PS8
EMIF.ARE/SADS/SDCAS/SRE
(see Note C)
EMIF.AOE/SOE/SDRAS
(see Note C)
PS12
PS12
EMIF.AWE/SWE/SDWE
(see Note C)
A.
B.
The write latency and the length of EMIF.CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE
Secondary Control Registers (CEx_SC1, CEx_SC2). In this figure, SYNCWL = 1 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):
−Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
−Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
−EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has
been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).
−Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect
cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).
−Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
C. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and
EMIF.SWE, respectively, during programmable synchronous interface accesses.
Figure 5-12. Programmable Synchronous Interface Write Timings (With Write Latency = 1)
Specifications
141
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.7.3 Synchronous DRAM Timings
Table 5-13 and Table 5-14 assume testing over recommended operating conditions (see Figure 5-13 through
Figure 5-20).
Table 5-13. Synchronous DRAM Cycle Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN MAX
SD6 tsu(EDV-EKO1H)
SD7 th(EKO1H-EDV)
Setup time, read EMIF.Dx valid before ECLKOUT1 high
Hold time, read EMIF.Dx valid after ECLKOUT1 high
2
2
ns
ns
Table 5-14. Synchronous DRAM Cycle Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
SD1 td(EKO1H-CEV)
SD2 td(EKO1H-BEV)
SD3 td(EKO1H-BEIV)
SD4 td(EKO1H-EAV)
SD5 td(EKO1H-EAIV)
SD8 td(EKO1H-CASV)
SD9 td(EKO1H-EDV)
SD10 td(EKO1H-EDIV)
SD11 td(EKO1H-WEV)
SD12 td(EKO1H-RASV)
SD13 td(EKO1H-CKEV)
Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid
Delay time, ECLKOUT1 high to EMIF.BEx valid
Delay time, ECLKOUT1 high to EMIF.BEx invalid
Delay time, ECLKOUT1 high to EMIF.Ax valid
Delay time, ECLKOUT1 high to EMIF.Ax invalid
Delay time, ECLKOUT1 high to EMIF.SDCAS valid
Delay time, ECLKOUT1 high to EMIF.Dx valid
Delay time, ECLKOUT1 high to EMIF.Dx invalid
Delay time, ECLKOUT1 high to EMIF.SDWE valid
Delay time, ECLKOUT1 high to EMIF.SDRAS valid
Delay time, ECLKOUT1 high to EMIF.SDCKE valid
0.8
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.8
7
0.8
0.8
7
7
0.8
0.8
0.8
0.8
7
7
7
142
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
READ
ECLKOUT1
EMIF.CEx
SD1
SD1
SD2
BE1
SD3
BE4
EMIF.BE[3:0]
EMIF.A[21:13]
EMIF.A[11:2]
BE2
BE3
SD4
SD5
SD5
SD5
Bank
SD4
Column
SD4
EMIF.A12
SD6
SD7
EMIF.D[31:0]
D1
D2
D3
D4
EMIF.AOE/SOE/SDRAS
(see Note A)
SD8
SD8
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-13. SDRAM Read Command (CAS Latency 3)
WRITE
ECLKOUT1
SD1
SD1
EMIF.CEx
SD2
BE1
SD4
Bank
SD4
Column
SD3
SD2
BE2
EMIF.BE[3:0]
EMIF.A[21:13]
BE3
BE4
SD5
SD5
SD5
SD9
EMIF.A[11:2]
EMIF.A12
SD4
SD9
SD10
EMIF.D[31:0]
D1
D2
D3
D4
EMIF.AOE/SOE/SDRAS
(see Note A)
SD8
SD8
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
SD11
SD11
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-14. SDRAM Write Command
Specifications
143
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
ACTV
ECLKOUT1
SD1
SD4
SD1
EMIF.CEx
EMIF.BE[3:0]
SD5
SD5
SD5
Bank Activate
SD4
EMIF.A[21:13]
EMIF.A[11:2]
Row Address
SD4
Row Address
EMIF.A12
EMIF.D[31:0]
SD12
EMIF.AOE/SOE/SDRAS
(see Note A)
SD12
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-15. SDRAM ACTV Command
DCAB
ECLKOUT1
SD1
SD1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13, 11:2]
SD4
SD5
EMIF.A12
EMIF.D[31:0]
SD12
SD12
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
SD11
SD11
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-16. SDRAM DCAB Command
144
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
DEAC
ECLKOUT1
SD1
SD4
SD1
EMIF.CEx
EMIF.BE[3:0]
SD5
EMIF.A[21:13]
EMIF.A[11:2]
Bank
SD4
SD5
EMIF.A12
EMIF.D[31:0]
SD12
SD11
SD12
SD11
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-17. SDRAM DEAC Command
REFR
ECLKOUT1
SD1
SD1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13, 11:2]
EMIF.A12
EMIF.D[31:0]
SD12
SD12
EMIF.AOE/SOE/SDRAS
(see Note A)
SD8
SD8
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-18. SDRAM REFR Command
Specifications
145
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
MRS
ECLKOUT1
SD1
SD4
SD1
SD5
EMIF.CEx
EMIF.BE[3:0]
MRS value
EMIF.A[21:2]
EMIF.D[31:0]
SD12
SD8
SD12
SD8
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
SD11
SD11
EMIF.AWE/SWE/SDWE
(see Note A)
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-19. SDRAM MRS Command
≥ TRAS cycles
End Self-Refresh
Self Refresh
ECLKOUT1
EMIF.CEx
EMIF.BE[3:0]
EMIF.A[21:13, 11:2]
EMIF.A12
EMIF.D[31:0]
EMIF.AOE/SOE/SDRAS
(see Note A)
EMIF.ARE/SADS/SDCAS/SRE
(see Note A)
EMIF.AWE/SWE/SDWE
(see Note A)
SD13
SD13
EMIF.SDCKE
A. EMIF.ARE/SADS/SDCAS/SRE, EMIF.AWE/SWE/SDWE, and EMIF.AOE/SOE/SDRAS operate as EMIF.SDCAS, EMIF.SDWE, and
EMIF.SDRAS, respectively, during SDRAM accesses.
Figure 5-20. SDRAM Self-Refresh Timings
146
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.8 HOLD/HOLDA Timings
Table 5-15 and Table 5-16 assume testing over recommended operating conditions (see Figure 5-21).
Table 5-15. EMIF.HOLD/HOLDA Timing Requirements(1)
VC5502-200
VC5502-300
MIN MAX
E
NO.
UNIT
H3
toh(HOLDAL-HOLDL)
Hold time, EMIF.HOLD low after EMIF.HOLDA low
ns
(1) E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.
Table 5-16. EMIF.HOLD/HOLDA Switching Characteristics(1)(2)(3)
VC5502-200
VC5502-300
NO.s
PARAMETER
UNIT
MIN
4E
0
MAX
(4)
H1
H2
H4
H5
H6
H7
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
td(HOLDL-EKOHZ)
td(HOLDH-EKOLZ)
Delay time, EMIF.HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to EMIF.HOLDA low
Delay time, EMIF.HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to EMIF.HOLDA high
Delay time, EMIF.HOLD low to ECLKOUTx high impedance
Delay time, EMIF.HOLD high to ECLKOUTx low impedance
ns
ns
ns
ns
ns
ns
2E
7E
2E
0
2E
(4)
4E
2E
7E
(1) E = the EMIF input clock (ECLKIN, CPU/1 clock, CPU1/2 clock, or CPU1/4 clock) period in ns for EMIF.
(2) EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE,
EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE , EMIF.SDCKE, and EMIF.SOE3.
(3) The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2) determine the state of the ECLKOUTx signals during
EMIF.HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance
during Hold mode, as shown in Figure 5-21.
(4) All pending EMIF transactions are allowed to complete before EMIF.HOLDA is asserted. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
H3
EMIF.HOLD
H2
H5
EMIF.HOLDA
H1
H4
H7
EMIF Bus
(see Note A)
5502
ECLKOUTx
ECLKOUTx
H6
A. EMIF Bus consists of: EMIF.CE[3:0], EMIF.BE[3:0], EMIF.D[31:0], EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE,
EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.SDCKE, and EMIF.SOE3.
Figure 5-21. EMIF.HOLD/HOLDA Timings
Specifications
147
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.9 Reset Timings
Table 5-17 and Table 5-18 assume testing over recommended operating conditions (see Figure 5-22).
Table 5-17. Reset Timing Requirements(1)
VC5502-200
VC5502-300
MIN MAX
2P + 5
NO.
R1
UNIT
tw(RSL)
Pulse width, RESET low
ns
(1) P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.
Table 5-18. Reset Switching Characteristics(1)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
R2
R3
R4
R5
R6
R7
td(RSL-EMIFHZ)
td(RSH-EMIFV)
td(RSL-HIGHIV)
td(RSH-HIGHV)
td(RSL-ZHZ)
Delay time, RESET low to EMIF group high impedance(2)
12
ns
ns
ns
ns
ns
ns
GPIO4 = 0 (CLKMOD = 0)
41115P + 21
148P + 22
12
Delay time, RESET high to EMIF group valid(2)
Delay time, RESET low to high group invalid(3)
Delay time, RESET high to high group valid(3)
GPIO4 = 1 (CLKMOD = 1)
GPIO4 = 0 (CLKMOD = 0)
GPIO4 = 1 (CLKMOD = 1)
41044P + 17
77P + 18
10
Delay time, RESET low to Z group high impedance(4)
GPIO4 = 0 (CLKMOD = 0)
GPIO4 = 1 (CLKMOD = 1)
41044P + 18
77P + 19
13
td(RSH-ZV)
Delay time, RESET high to Z group invalid(4)
R8
R9
td(RSL-IOIM)
td(RSL-TGLD)
Delay time, RESET low to Input/Output group switch to input mode(5)
Delay time, RESET low to Toggle group switch to default toggle frequency(6)
ns
ns
11 + 14P
(1) P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.
(2) EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,
EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD,
EMIF.HOLDA, ECLKOUT1. EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only
signals; they are included here simply for completeness.
(3) High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.
(4) Z group: HRDY, HINT, DX2, DX1, DX0
(5) Input/Output group: PGPIO[45:0], HPI.HA[15:0], HPI.HD[15:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, R/W,
HDS1, HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, CLKR2, CLKX2,
FSR2, FSX2, EMU0, EMU1/OFF. Signals in this group switch to input mode with reset.
(6) Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.
148
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
R1
RESET
R3
R5
R2
R4
R6
EMIF Group
(see Note A)
High Group
(see Note B)
R7
Z Group
(see Note C)
R8
R9
Input/Output Group
(see Note D)
Toggle Group
(see Note E)
A. EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,
EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA,
ECLKOUT1.
EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply
for completeness.
B. High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.
C. Z group: HRDY, HINT, DX2, DX1, DX0
D. Input/Output group: PGPIO[45:0], HPI.HA[15:0], HPI.HD[15:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, R/W, HDS1,
HDS2, NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, CLKR2, CLKX2, FSR2, FSX2,
EMU0, EMU1/OFF. Signals in this group switch to input mode with reset.
E. Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.
Figure 5-22. Reset Timings
Specifications
149
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.10 External Interrupt and Interrupt Acknowledge (IACK) Timings
Table 5-19 and Table 5-20 assume testing over recommended operating conditions (see Figure 5-23 and
Figure 5-24).
Table 5-19. External Interrupt and Interrupt Acknowledge Timing Requirements
VC5502-200
VC5502-300
MIN MAX
3P(1)
NO.
UNIT
I1
I2
tw(INTL)A
tw(INTH)A
Pulse width, interrupt low, CPU active
Pulse width, interrupt high, CPU active
ns
ns
1P(1)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
Table 5-20. External Interrupt and Interrupt Acknowledge Switching Characteristics
VC5502-200
VC5502-300
NO.
I3
PARAMETER
UNIT
MIN
MAX
td(COH-IACKV)
Delay time, CLKOUT high to IACK valid(1)
0
8
ns
(1) In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra
delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For
example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of
one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the
CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra
delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the
system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.
I1
INTx, NMI
I2
Figure 5-23. External Interrupt Timings
CLKOUT
I3
I3
IACK
(A ) The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the
CPU clock.
Figure 5-24. External Interrupt Acknowledge Timings
150
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.11 XF Timings
Table 5-21 assumes testing over recommended operating conditions (see Figure 5-25).
Table 5-21. XF Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
0
MAX
Delay time, CLKOUT high to XF high(1)
Delay time, CLKOUT high to XF low(1)
5
6
X1
td(XF)
ns
0
(1) In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra
delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For
example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of
one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the
CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra
delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the
system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.
CLKOUT
X1
XF
(A ) The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the
CPU clock.
Figure 5-25. XF Timings
Specifications
151
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.12 General-Purpose Input/Output (GPIOx) Timings
Table 5-22 and Table 5-23 assume testing over recommended operating conditions(see Figure 5-26).
Table 5-22. GPIO Pins Configured as Inputs Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
5
MAX
G2
G3
tsu(GPIO-COH)
th(COH-GPIO)
Setup time, GPIOx input valid before CLKOUT high(1)
Hold time, GPIOx input valid after CLKOUT high(1)
ns
ns
0
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
Table 5-23. GPIO Pins Configured as Outputs Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
G1
td(COH-GPIO)
Delay time, CLKOUT high to GPIOx output change(1)
0
8
ns
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
CLKOUT
G2
G3
GPIOx
Input Mode
G1
GPIOx
Output Mode
Figure 5-26. General-Purpose Input/Output (GPIOx) Signal Timings
152
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.13 Parallel General-Purpose Input/Output (PGPIOx) Timings
Table 5-24 and Table 5-25 assume testing over recommended operating conditions(see Figure 5-27).
Table 5-24. PGPIO Pins Configured as Inputs Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
6
MAX
PG2 tsu(PGPIO-COH)
PG3 th(COH-PGPIO)
Setup time, PGPIOx input valid before CLKOUT high(1)
Hold time, PGPIOx input valid after CLKOUT high(1)
ns
ns
0
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
Table 5-25. PGPIO Pins Configured as Outputs Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
10
PG1 td(COH-PGPIO)
Delay time, CLKOUT high to PGPIOx output change(1)
0
ns
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
CLKOUT
PG2
PG3
PGPIOx
Input Mode
PG1
PGPIOx
Output Mode
Figure 5-27. Parallel General-Purpose Input/Output (PGPIOx) Signal Timings
Specifications
153
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.14 TIM0/TIM1/WDTOUT Timings
Table 5-26 and Table 5-27 assume testing over recommended operating conditions(see Figure 5-28 and
Figure 5-29).
5.14.1 TIM0/TIM1/WDTOUT Timer Pin Timings
Table 5-26. TIM0/TIM1/WDTOUT Pins Configured as Timer Input Pins Timing Requirements(1)
VC5502-200
VC5502-300
NO.
UNIT
MIN
4P
MAX
T4
T5
tw(TIML)
tw(TIMH)
Pulse width, TIM0/TIM1/WDTOUT low
Pulse width, TIM0/TIM1/WDTOUT high
ns
ns
4P
(1) P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
Table 5-27. TIM0/TIM1/WDTOUT Pins Configured as Timer Output Pins Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
0
MAX
T1
T2
T3
td(COH-TIMH)
td(COH-TIML)
tw(TIM)
Delay time, CLKOUT high to TIM0/TIM1/WDTOUT high(1)
Delay time, CLKOUT high to TIM0/TIM1/WDTOUT low(1)
Pulse duration, TIM0/TIM1/WDTOUT
6
7
ns
ns
ns
0
P(2)
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
(2) P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
T5
T4
TIM0/TIM1/WDTOUT
as Input
Figure 5-28. TIM0/TIM1/WDTOUT Timings When Configured as Timer Input Pins
CLKOUT
T2
T1
TIM0/TIM1/WDTOUT
as Output
T3
Figure 5-29. TIM0/TIM1/WDTOUT Timings When Configured as Timer Output Pins
154
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.14.2 TIM0/TIM1/WDTOUT General-Purpose I/O Timings
Table 5-28 and Table 5-29 assume testing over recommended operating conditions (see Figure 5-30).
Table 5-28. TIM0/TIM1/WDTOUT General-Purpose I/O Timing Requirements(1)
VC5502-200
VC5502-300
NO.
UNIT
MIN
5
MAX
T9
tsu(TIM0GPIO-COH)
Setup time, TIM0-GPIO input mode before CLKOUT high
Hold time, TIM0-GPIO input mode after CLKOUT high
Setup time, TIM1-GPIO input mode before CLKOUT high
Hold time, TIM1-GPIO input mode after CLKOUT high
Setup time, WDTOUT-GPIO input mode before CLKOUT high
Hold time, WDTOUT-GPIO input mode after CLKOUT high
ns
ns
ns
ns
ns
ns
T10 th(COH-TIM0GPIO)
T11 tsu(TIM1GPIO-COH)
T12 th(COH-TIM1GPIO)
T13 tsu(WDTGPIO-COH)
T14 th(COH-WDTGPIO)
0
5
0
5
0
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
Table 5-29. TIM0/TIM1/WDTOUT General-Purpose I/O Switching Characteristics(1)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN MAX
T6
T7
T8
td(COH-TIM0GPIO)
td(COH-TIM1GPIO)
td(COH-WDTGPIO)
Delay time, CLKOUT high to TIM0-GPIO output mode
Delay time, CLKOUT high to TIM1-GPIO output mode
Delay time, CLKOUT high to WDTOUT-GPIO output mode
10
10
10
ns
ns
ns
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
Specifications
155
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
CLKOUT
T9
T10
T12
T14
TIM0 GPIO
Input Mode
T6
TIM0 GPIO
Output Mode
T11
TIM1 GPIO
Input Mode
T7
TIM1 GPIO
Output Mode
T13
WDTOUT GPIO
Input Mode
T8
WDTOUT GPIO
Output Mode
Figure 5-30. TIM0/TIM1/WDTOUT General-Purpose I/O Timings
156
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.14.3 TIM0/TIM1/WDTOUT Interrupt Timings
Table 5-30 assumes testing over recommended operating conditions (see Figure 5-31).
Table 5-30. TIM0/TIM1/WDTOUT Interrupt Timing Requirements(1)(2)
VC5502-200
VC5502-300
NO.
UNIT
MIN MAX
T15 tsu(TIM0L-COH)
T16 th(COH-TIM0L)
T17 tw(TIM0L)
Setup time, TIM0 low(3) before CLKOUT rising edge
Hold time, TIM0 low(3) after CLKOUT rising edge
Pulse width, TIM0 low(3)
Setup time, TIM1 low(3) before CLKOUT rising edge
Hold time, TIM1 low(3) after CLKOUT rising edge
Pulse width, TIM1 low(3)
Setup time, WDTOUT low(3) before CLKOUT rising edge
Hold time, WDTOUT low(3) after CLKOUT rising edge
Pulse width, WDTOUT low(3)
5
0
P
5
0
P
5
0
P
ns
ns
ns
ns
ns
ns
ns
ns
ns
T18 tsu(TIM1L-COH)
T19 th(COH-TIM1L)
T20 tw(TIM1L)
T21 tsu(WDTL-COH)
T22 th(COH-WDTL)
T23 tw(WDTL)
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
(2) P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) An interrupt can be triggered by setting the timer pins high or low, depending on the setting of the TIN1INV bit in the GPIO Interrupt
Control Register (GPINT). Refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for more
information on the interrupt capability of the timer pins.
CLKOUT
T15
T16
T17
TIM0
T18
T19
T20
TIM1
T21
T22
T23
WDTOUT
Figure 5-31. TIM0/TIM1/WDTOUT Interrupt Timings
Specifications
157
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.15 Multichannel Buffered Serial Port (McBSP) Timings
5.15.1 McBSP Transmit and Receive Timings
Table 5-31 and Table 5-32 assume testing over recommended operating conditions (see Figure 5-32 and
Figure 5-33).
Table 5-31. McBSP Transmit and Receive Timing Requirements(1)(2)
VC5502-200
VC5502-300
NO.
UNIT
MIN
2P
MAX
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
ns
ns
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 2
5
5
Fall time, CLKR/X
5
1
1
6
3
1
1
6
5
1
1
6
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
CLKX ext
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
158
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 5-32. McBSP Transmit and Receive Switching Characteristics(1)(2)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
M1 tc(CKRX)
M2 tw(CKRXH)
M3 tw(CKRXL)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
ns
ns
ns
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 1(3) D + 1(3)
C – 1(3) C + 1(3)
–2
4
6
M4 td(CKRH-FRV)
M5 td(CKXH-FXV)
M6 tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
16
–2
4
6
16
–5
1
5
11
Disable time, CLKX high to DX high impedance
following last data bit
6
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
16
6
Delay time, CLKX high to DX valid(4)
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
M7 td(CKXH-DXV)
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
ns
16
2P + 2
2P + 8
0
6
Enable time, CLKX high to DX driven(4)
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
M8 ten(CKXH-DX)
M9 td(FXH-DXV)
M10 ten(FXH-DX)
ns
ns
ns
2P
2P + 6
2
7
Delay time, FSX high to DX valid(4)
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
FSX ext
FSX int
2P + 2
2P + 7
FSX ext
FSX int
0
6
Enable time, FSX high to DX driven(4)
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
FSX ext
FSX int
2P
FSX ext
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) T = CLKRX period = (1 + CLKGDV) * P
C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
(4) See the TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature
number SPRU592) for a description of the DX enable (DXENA) and data delay features of the McBSP.
Specifications
159
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
M1, M11
M2, M12
M13
M3, M12
M4
CLKR
M4
M14
FSR (Int)
M15
M16
FSR (Ext)
M17
M18
DR
Bit (n-1)
M17
(n-2)
(n-3)
(n-2)
(n-4)
(n-3)
(n-2)
(RDATDLY=00b)
M18
DR
Bit (n-1)
(RDATDLY=01b)
M17
M18
DR
Bit (n-1)
(RDATDLY=10b)
Figure 5-32. McBSP Receive Timings
M1, M11
M2, M12
M13
M14
M3, M12
M5
CLKX
M5
FSX (Int)
M19
M20
FSX (Ext)
M9
M7
M10
DX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(XDATDLY=00b)
M7
M8
DX
Bit 1
M6
Bit 0
Bit (n−1)
(XDATDLY=01b)
M7
M8
DX
Bit 1
Bit 0
Bit 2
Bit (n−1)
(n−2)
(XDATDLY=10b)
A. This figure does not include first or last frames. For first frame, no data will be present before frame synchronization.
For last frame, no data will be present after frame synchronization.
Figure 5-33. McBSP Transmit Timings
160
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.15.2 McBSP General-Purpose I/O Timings
Table 5-33 and Table 5-34 assume testing over recommended operating conditions (see Figure 5-34).
Table 5-33. McBSP General-Purpose I/O Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
4
MAX
M22 tsu(MGPIO-COH)
M23 th(COH-MGPIO)
Setup time, MGPIOx input mode before CLKOUT high(1)(2)
Hold time, MGPIOx input mode after CLKOUT high(1)(2)
ns
ns
0
(1) MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
(2) In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as
CLKOUT.
Table 5-34. McBSP General-Purpose I/O Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN
MAX
M21 td(COH-MGPIO)
Delay time, CLKOUT high to MGPIOx output mode(1)(2)
0
6
ns
(1) In this case, CLKOUT reflects SYSCLK2. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK2 as
CLKOUT.
(2) MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
M22
CLKOUT
M21
M23
MGPIO
Input Mode
(see Note A)
MGPIO
Output Mode
(see Note B)
A. MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
B. MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
Figure 5-34. McBSP General-Purpose I/O Timings
Specifications
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5.15.3 McBSP as SPI Master or Slave Timings
Table 5-35 to Table 5-42 assume testing over recommended operating conditions (see Figure 5-35 through
Figure 5-38).
Table 5-35. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)(2)(3)
VC5502-200
VC5502-300
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
13
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(FXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
0 – 5P
9 + 6P
10
ns
ns
ns
ns
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
Table 5-36. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1)(2)(3)(4)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MASTER
SLAVE
MIN
MIN
T – 2
C – 6
–4
MAX
MAX
M24 td(CKXL-FXL)
M25 td(FXL-CKXH)
M26 td(CKXH-DXV)
Delay time, CLKX low to FSX low(5)
Delay time, FSX low to CLKX high(6)
Delay time, CLKX high to DX valid
T + 6
C + 4
6
ns
ns
ns
4P
6P
Disable time, DX high impedance following last data bit from
CLKX low
M27 tdis(CKXL-DXHZ)
C – 2
C +10
ns
Disable time, DX high impedance following last data bit from
FSX high
M28 tdis(FXH-DXHZ)
M29 td(FXL-DXV)
2P + 4 4P + 10
2P + 4 4P + 10
ns
ns
Delay time, FSX low to DX valid
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
(4) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
162
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
M32
M25
M33
LSB
MSB
CLKX
M26
M24
FSX
M28
M27
M29
DX
DR
Bit 0
Bit (n-1)
Bit (n-1)
(n-2)
M31
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
M30
Bit 0
Figure 5-35. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Specifications
163
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Table 5-37. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)(2)(3)
VC5502-200
VC5502-300
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
13
1
MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
0 – 5P
9 + 6P
10
ns
ns
ns
ns
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
Table 5-38. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1)(2)(3)(4)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MASTER
MIN
SLAVE
MIN
MAX
C + 6
T + 4
6
MAX
M34 td(CKXL-FXL)
M35 td(FXL-CKXH)
M36 td(CKXL-DXV)
Delay time, CLKX low to FSX low(5)
Delay time, FSX low to CLKX high(6)
Delay time, CLKX low to DX valid
C – 2
T – 6
–4
ns
ns
ns
4P
3P + 4
2P – 4
6P
4P + 18
4P + 10
Disable time, DX high impedance following last
data bit from CLKX low
M37 tdis(CKXL-DXHZ)
M38 td(FXL-DXV)
–2
10
ns
ns
Delay time, FSX low to DX valid
D – 2
D + 10
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
(4) T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
164
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
M41
M35
M42
LSB
MSB
CLKX
M34
M36
FSX
M38
M37
DX
DR
Bit 0
Bit 0
Bit (n-1)
Bit (n-1)
(n-2)
M40
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
M39
Figure 5-36. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Table 5-39. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)(2)(3)
VC5502-200
VC5502-300
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
13
1
MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
M51 tsu(FXL-CKXL)
M52 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
0 – 5P
9 + 6P
10
ns
ns
ns
ns
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
Table 5-40. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1)(2)(3)(4)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MASTER
MIN
SLAVE
MIN
MAX
T + 6
D + 4
6
MAX
M43 td(CKXH-FXL)
M44 td(FXL-CKXL)
M45 td(CKXL-DXV)
Delay time, CLKX high to FSX low(5)
Delay time, FSX low to CLKX low(6)
Delay time, CLKX low to DX valid
T – 2
D – 6
–4
ns
ns
ns
4P
6P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
(4) T = CLKX period = (1 + CLKGDV) * P
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Specifications
165
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 5-40. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
(continued)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MASTER
MIN
SLAVE
MIN
MAX
MAX
Disable time, DX high impedance following last
data bit from CLKX high
M46 tdis(CKXH-DXHZ)
D – 2
D + 10
ns
Disable time, DX high impedance following last
data bit from FSX high
M47 tdis(FXH-DXHZ)
M48 td(FXL-DXV)
2P + 4
2P – 4
4P + 10
4P + 10
ns
ns
Delay time, FSX low to DX valid
M51
M52
LSB
MSB
CLKX
FSX
M44
M43
M45
M47
M48
M46
DX
DR
Bit 0
Bit (n-1)
M49
(n-2)
M50
(n-2)
(n-3)
(n-3)
(n-4)
Bit 0
Bit (n-1)
(n-4)
Figure 5-37. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
166
Specifications
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Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 5-41. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1)(2)(3)
VC5502-200
VC5502-300
NO.
UNIT
MASTER
SLAVE
MIN
MIN
13
1
MAX
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
0 – 5P
9 + 6P
10
ns
ns
ns
ns
2P
16P
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
Table 5-42. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)(2)(3)(4)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MASTER
MIN
SLAVE
MIN
MAX
D + 6
T + 4
6
MAX
M53 td(CKXH-FXL)
M54 td(FXL-CKXL)
M55 td(CKXH-DXV)
Delay time, CLKX high to FSX low(5)
Delay time, FSX low to CLKX low(6)
Delay time, CLKX high to DX valid
D – 2
T – 6
–4
ns
ns
ns
4P
3P + 4
2P – 4
6P
4P + 18
4P + 10
Disable time, DX high impedance following last
data bit from CLKX high
M56 tdis(CKXH-DXHZ)
M57 td(FXL-DXV)
–2
10
ns
ns
Delay time, FSX low to DX valid
C – 2
C + 10
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(3) McBSP register values required to configure the McBSP as an SPI master and as an SPI slave are listed in the
TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number
SPRU592).
(4) T = CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
(5) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(6) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Specifications
167
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
M60
M54
M61
LSB
MSB
CLKX
M53
M55
FSX
M57
M56
DX
DR
Bit 0
Bit 0
Bit (n-1)
Bit (n-1)
(n-2)
M59
(n-3)
(n-4)
M58
(n-2)
(n-3)
(n-4)
Figure 5-38. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
168
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.16 Host-Port Interface Timings
5.16.1 HPI Read and Write Timings
Table 5-43 and Table 5-44 assume testing over recommended operating conditions (see Figure 5-39 through
Figure 5-44).
Table 5-43. HPI Read and Write Timing Requirements(1)(2)(3)
VC5502-200
VC5502-300
NO.
UNIT
MIN
5
MAX
H9
tsu(HASL-DSL)
th(DSL-HASL)
tsu(HAD-HASL)
th(HASL-HAD)
tw(DSL)
Setup time, HPI.HAS low before DS falling edge
Hold time, HPI.HAS low after DS falling edge
Setup time, HAD valid before HPI.HAS falling edge
Hold time, HAD valid after HPI.HAS falling edge
Pulse duration, DS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
H10
H11
H12
H13
H14
H15
H16
H17
H18
H37
H38
2
5
5
15
2P
5
tw(DSH)
Pulse duration, DS high
tsu(HAD-DSL)
th(DSL-HAD)
tsu(HD-DSH)
th(DSH-HD)
Setup time, HAD valid before DS falling edge
Hold time, HAD valid after DS falling edge
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge
Setup time, HCS low before DS falling edge
Hold time, DS low after HRDY rising edge
5
5
0
tsu(HCSL-DSL)
th(HRDYH-DSL)
0
0
(1) P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
(2) DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0,
HCNTL1, HPI.HBIL, and HR/W.
(3) A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for
more details.
Specifications
169
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Table 5-44. HPI Read and Write Switching Characteristics(1)(2)(3)
VC5502-200
VC5502-300
NO.
PARAMETER
Case 1. HPIC or HPIA read
UNIT
MIN
MAX
5
15
K = 1(5)
K = 2(5)
K = 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
9 * 2H + 20
10 * 2H + 20
11 * 2H + 20
9 * 2H + 20
10 * 2H + 20
11 * 2H + 20
Case 2. HPID read with no
auto-increment(4)
Delay time, DS low to HD
valid
H1 td(DSL-HDV)
ns
Case 3. HPID read with
auto-increment and read
FIFO initially empty(4)
Case 4. HPID read with auto-increment and
data previously prefetched into the read FIFO
5
15
H2 tdis(DSH-HDV)
H3 ten(DSL-HDD)
H4 td(DSL-HRDYL)
H5 td(DSH-HRDYL)
Disable time, HD high-impedance from DS high
Enable time, HD driven from DS low
Delay time, DS low to HRDY low
1
3
4
15
ns
ns
ns
ns
12
Delay time, DS high to HRDY low
12
K = 1(5)
K = 2(5)
K = 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
10 * 2H + 20
11 * 2H + 20
12 * 2H + 20
10 * 2H + 20
11 * 2H + 20
12 * 2H + 20
Case 1. HPID read with no
auto-increment(4)
Delay time, DS low to HRDY
high
H6 td(DSL-HRDYH)
ns
Case 2. HPID read with
auto-increment and read
FIFO initialy empty(4)
H7 td(HDV-HRDYH)
H8 td(COH-HINT)
Delay time, HD valid to HRDY high
Delay time, CLKOUT high to HINT change(6)
0
ns
ns
8
5 * 2H + 20
5 * 2H + 20
5 * 2H + 20
6 * 2H + 20
40 * 2H + 20
40 * 2H + 20
24 * 2H + 20
12
Case 1. HPIA write(4)
K = 1, 2, 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
K = 1(5)
K = 2(5)
K = 4(5)
Delay time, DS high to HRDY
high
H34 td(DSH-HRDYH)
ns
Case 2. HPID write with no
auto-increment(4)
Delay time, DS low to HRDY high for HPIA write and FIFO
not empty(4)
H35 td(DSL-HRDYH)
ns
ns
H36 td(HASL-HRDYL)
Delay time, HPI.HAS low to HRDY low
(1) DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0,
HCNTL1, HPI.HBIL, and HR/W.
(2) H is half the SYSCLK1 clock cycle.
(3) A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for
more details.
(4) Assumes no other DMA or CPU memory activity.
(5) K = divider ratio between CPU clock and SYSCLK1. For example, when SYSCLK1 is set to the CPU clock divided by four, use K = 4.
(6) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
170
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
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SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Read
H13
Write
HCS
H37
H13
H37
H14
HDSx
HR/W
H15
H15
H16
H16
HPI.HA[15:0]
Valid
Valid
H1
H2
H3
HPI.HD[15:0]
(Read)
Read data
H18
H17
HPI.HD[15:0]
(Write)
Write data
H34
H5
H7
H4
H6
HRDY
(A ) Dependingon the type of write or read operation (HPID or HPIC), transitions on HRDY may or may not occur [see the TMS320VC5501/5502
DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)].
Figure 5-39. Non-Multiplexed Read/Write Timings
Specifications
171
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
HCS
HPI.HAS
H12
H12
H11
H11
HCNTL[1:0]
H12
H12
H12
H11
H11
H11
HR/W
H12
H11
HPI.HBIL
H10
H9
H13
H10
H13
H9
H37
H37
H14
DS
H1
H3
H1
H3
H2
H2
HPI.HD[7:0]
H7
H38
H36
H6
HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference
Guide (literature number SPRU620)].
Figure 5-40. Multiplexed Read Timings Using HPI.HAS
172
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
HCS
HPI.HAS
HCNTL[1:0]
HR/W
HPI.HBIL
H13
H16
H16
H15
H15
H37
H37
H14
H13
DS
H3
H1
H3
H1
H2
H2
HPI.HD[7:0]
H38
H4
H7
H6
HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference
Guide (literature number SPRU620)].
Figure 5-41. Multiplexed Read Timings With HPI.HAS Held High
Specifications
173
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
HCS
HPI.HAS
H12
H12
H12
H12
H11
H11
H11
H11
HCNTL[1:0]
H12
H11
HR/W
H12
H11
HPI.HBIL
H9
H10
H10
H9
H37
H14
H37
H13
DS
H13
H18
H18
H17
H17
HPI.HD[7:0]
H34
H35
H34
H5
H36
H5
H38
HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference
Guide (literature number SPRU620)].
Figure 5-42. Multiplexed Write Timings Using HPI.HAS
174
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
HCS
HPI.HAS
HCNTL[1:0]
HR/W
HPI.HBIL
H16
H13
H16
H15
H37
H15
H13
H14
H37
DS
H18
H18
H34
H17
H17
HPI.HD[7:0]
H38
H35
H4
H5
H34
H5
HRDY
(A ) Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on HRDY may or may not occur [see the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference
Guide (literature number SPRU620)].
Figure 5-43. Multiplexed Write Timings With HPI.HAS Held High
CLKOUT
H8
HINT
Figure 5-44. HINT Timings
Specifications
175
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.16.2 HPI General-Purpose I/O Timings
Table 5-45 and Table 5-46 assume testing over recommended operating conditions (see Figure 5-45).
Table 5-45. HPI General-Purpose I/O Timing Requirements(1)
VC5502-200
VC5502-300
NO.
UNIT
MIN
5
MAX
H23 tsu(HAGPIO-COH)
H24 th(COH-HAGPIO)
H25 tsu(HDNMGPIO-COH)
H26 th(COH-HDNMGPIO)
H27 tsu(HDMGPIO-COH)
H28 th(COH-HDMGPIO)
H29 tsu(HCGPIO-COH)
H30 th(COH-HCGPIO)
Setup time, HAGPIO input mode before CLKOUT high(2)
Hold time, HAGPIO input mode after CLKOUT high(2)
Setup time, HDNMGPIO input mode before CLKOUT high(3)
Hold time, HDNMGPIO input mode after CLKOUT high(3)
Setup time, HDMGPIO input mode before CLKOUT high(4)
Hold time, HDMGPIO input mode after CLKOUT high(4)
Setup time, HCGPIO input mode before CLKOUT high(5)
Hold time, HCGPIO input mode after CLKOUT high(5)
ns
ns
ns
ns
ns
ns
ns
ns
0
5
0
5
0
5
0
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
(2) HAGPIO refers to HPI.HA[15:0] configured as general-purpose input.
(3) HDNMGPIO refers to HPI.HD[15:0] configured as general-purpose input during non-multiplexed operation of the HPI.
(4) HDMGPIO refers to HPI.HD[7:0] configured as general-purpose input during multiplexed operation of the HPI.
(5) HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2,
HRDY, and HINT configured as general-purpose input.
Table 5-46. HPI General-Purpose I/O Switching Characteristics(1)
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN MAX
H19 td(COH-HAGPIO)
H20 td(COH-HDNMGPIO)
H21 td(COH-HDMGPIO)
H22 td(COH-HCGPIO)
Delay time, CLKOUT high to HAGPIO output mode(2)
Delay time, CLKOUT high to HDNMGPIO output mode(3)
Delay time, CLKOUT high to HDMGPIO output mode(4)
Delay time, CLKOUT high to HCGPIO output mode(5)
10
10
10
10
ns
ns
ns
ns
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
(2) HAGPIO refers to HPI.HA[15:0] configured as general-purpose output.
(3) HDNMGPIO refers to HPI.HD[15:0] configured as general-purpose output during non-multiplexed operation of the HPI.
(4) HDMGPIO refers to HPI.HD[7:0] configured as general-purpose output during multiplexed operation of the HPI.
(5) HCGPIO refers to HPI.HAS (multiplexed mode only), HPI.HBIL (multiplexed mode only), HCNTL0, HCNTL1, HCS, HR/W, HDS1, HDS2,
HRDY, and HINT configured as general-purpose output.
176
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
CLKOUT
H23
H25
H27
H29
H24
H26
H28
H30
HAGPIO
Input Mode
H19
HAGPIO
Output Mode
HDNMGPIO
Input Mode
H20
HDNMGPIO
Output Mode
HDMGPIO
Input Mode
H21
HDMGPIO
Output Mode
HCGPIO
Input Mode
H22
HCGPIO
Output Mode
Figure 5-45. HPI General-Purpose I/O Timings
Specifications
177
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.16.3 HPI.HAS Interrupt Timings
Table 5-47 assumes testing over recommended operating conditions (see Figure 5-46).
Table 5-47. HPI.HAS Interrupt Timing Requirements(1)
VC5502-200
VC5502-300
NO.
UNIT
MIN MAX
H31 tsu(HASL-COH)
H32 th(COH-HASL)
H33 tw(HASL)
Setup time, HPI.HAS low(2) before CLKOUT rising edge
Hold time, HPI.HAS low(2) after CLKOUT rising edge
Pulse width, HPI.HAS low(2)
5
0
P(3)
ns
ns
ns
(1) In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as
CLKOUT.
(2) An interrupt can be triggered by setting the HPI.HAS signal high or low, depending on the setting of the HAS bit in the General-Purpose
I/O Interrupt Control Register 2 (HPGPIOINT2). Refer to the TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide
(literature number SPRU620) for more information on the interrupt capability of the HPI.HAS signal.
(3) P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
CLKOUT
H31
H32
H33
HPI.HAS
Figure 5-46. HPI.HAS Interrupt Timings
178
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.17 Inter-Integrated Circuit (I2C) Timings
Table 5-48 and Table 5-49 assume testing over recommended operating conditions (see Figure 5-47 and
Figure 5-48).
Table 5-48. I2C Signals (SDA and SCL) Timing Requirements
VC5502-200
VC5502-300
NO.
Standard
Mode
Fast
Mode
UNIT
MIN
MAX
MIN
MAX
IC1 tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low for a repeated START
condition
IC2 tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low for a START and a
repeated START condition
IC3 th(SCLL-SDAL)
µs
IC4 tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(1)
µs
µs
ns
µs
IC5 tw(SCLH)
Pulse duration, SCL high
IC6 tsu(SDA-SCLH)
IC7 th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low For I2C bus™ devices
250
0(2)
0(2) 0.9(3)
Pulse duration, SDA high between STOP and START con-
ditions
IC8 tw(SDAH)
4.7
1.3
µs
(4)
IC9 tr(SDA)
IC10 tr(SCL)
IC11 tf(SDA)
IC12 tf(SCL)
Rise time, SDA
1000 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
ns
pF
(4)
(4)
(4)
Rise time, SCL
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
Fall time, SDA
Fall time, SCL
IC13 tsu(SCLH-SDAH)
IC14 tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.0
0.6
0
50
(4)
IC15 Cb
400
400
(1) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(3) The maximum th(SDA-SCLL) has only to be met if the 5502 I2C operates in master-receiver mode and the slave device does not stretch
the LOW period [tw(SCLL)] of the SCL signal.
(4) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
IC11
IC9
SDA
SCL
IC6
IC8
IC14
IC13
IC4
IC5
IC10
IC1
IC3
IC12
IC3
IC2
IC7
Stop
Start
Repeated
Start
Stop
Figure 5-47. I2C Receive Timings
Specifications
179
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 5-49. I2C Signals (SDA and SCL) Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
Standard
Mode
Fast
UNIT
Mode
MIN
2.5
MIN
MAX
MAX
IC16 tc(SCL)
Cycle time, SCL
10
µs
µs
Delay time, SCL high to SDA low for a repeated START
condition
IC17 td(SCLH-SDAL)
4.7
4
0.6
0.6
Delay time, SDA low to SCL low for a START and a repeated
START condition
IC18 td(SDAL-SCLL)
µs
IC19 tw(SCLL)
IC20 tw(SCLH)
IC21 td(SDA-SCLH)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
Pulse duration, SCL high
Delay time, SDA valid to SCL high
250
100
Valid time, SDA valid after SCL
For I2C bus devices
low
IC22 tv(SCLL-SDAV)
IC23 tw(SDAH)
0
0
µs
µs
Pulse duration, SDA high between STOP and START con-
ditions
4.7
1.3
(1)
IC24 tr(SDA)
IC25 tr(SCL)
IC26 tf(SDA)
IC27 tf(SCL)
IC28 td(SCLH-SDAH)
IC29 Cp
Rise time, SDA
1000 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
pF
(1)
(1)
(1)
Rise time, SCL
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
Fall time, SDA
Fall time, SCL
Delay time, SCL high to SDA high for a STOP condition
Capacitance for each I2C pin
4
0.6
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
IC26
IC24
SDA
IC21
IC23
IC19
IC28
IC20
IC25
SCL
IC16
IC18
IC27
IC18
IC17
IC22
Stop
Start
Repeated
Start
Stop
Figure 5-48. I2C Transmit Timings
180
Specifications
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
5.18 Universal Asynchronous Receiver/Transmitter (UART) Timings
Table 5-50 to Table 5-51 assume testing over recommended operating conditions (see Figure 5-49).
Table 5-50. UART Timing Requirements
VC5502-200
VC5502-300
NO.
UNIT
MIN
MAX
U4 tw(UDB)R
U5 tw(USB)R
Pulse width, receive data bit
Pulse width, receive start bit
0.96U(1)
0.96U(1)
1.05U(1) ns
1.05U(1) ns
(1) U = UART baud time = 1/programmed baud rate
Table 5-51. UART Switching Characteristics
VC5502-200
VC5502-300
NO.
PARAMETER
UNIT
MIN MAX
U1
U2
U3
fbaud
Maximum programmable baud rate
Pulse width, transmit data bit
Pulse width, transmit start bit
5
MHz
ns
tw(UDB)X
tw(USB)X
U – 2(1) U + 2(1)
U – 2(1) U + 2(1)
ns
(1) U = UART baud time = 1/programmed baud rate
U3
Data Bits
Start
Bit
UART.TX
U2
Data Bits
Start
Bit
UART.RX
U4
U5
Figure 5-49. UART Timings
Specifications
181
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
6
Mechanical Data
Some TMX samples were shipped in the GGW package. For more information on the GGW package, see
the TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number
SPRZ020D or later).
TMS320VC5502PGF has completed Temp Cycle reliability qualification testing with no failures through
1500 cycles of –55°C to 125°C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at
220+5/–0°C peak reflow. Exceeding this peak reflow temperature condition or storage and handling
requirements may result in either immediate device failure post-reflow, due to package/die material
delamination (“popcorning”), or degraded Temp cycle life performance.
Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a
bar-code label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions
and re-bake instructions are prominently displayed on a nearby screen-printed label.
6.1 Package Thermal Resistance Characteristics
Table 6-1 and Table 6-2 provide the thermal resistance characteristics for the recommended package
types used on the TMS320VC5502 DSP.
NOTE
Some TMX samples were shipped in the GGW package. For more information on the
GGW package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors
Silicon Errata (literature number SPRZ020D or later).
Table 6-1. Thermal Resistance Characteristics (Ambient)
PACKAGE
R
ΘJA (°C/W)
BOARD TYPE(1)
High-K
High-K
High-K
High-K
Low-K
AIRFLOW (LFM)
94
0
93
150
250
500
0
91
87
(Without thermal vias)
117
114
109
101
39
Low-K
150
250
500
0
GZZ, ZZZ
Low-K
Low-K
High-K
High-K
High-K
High-K
37
150
250
500
(With thermal vias)(2)
36
34
(1) Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package
Thermal Measurements.
(2) Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GZZ and ZZZ
packages:
•
•
An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted.
The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability
Temperature Cycle performance.
•
•
The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be
connected to the ground plane for heat dissipation.
A solid internal plane is preferred for spreading the heat.
Refer to the MicroStar BGA™ Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount,
and reliability considerations.
182
Mechanical Data
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Table 6-1. Thermal Resistance Characteristics (Ambient) (continued)
PACKAGE
RΘJA (°C/W)
BOARD TYPE(1)
AIRFLOW (LFM)
60
52
49
45
104
81
73
64
High-K
0
High-K
150
250
500
0
High-K
High-K
PGF
Low-K
Low-K
150
250
500
Low-K
Low-K
Table 6-2. Thermal Resistance Characteristics (Case)
PACKAGE
RΘJC (°C/W)
BOARD TYPE(1)
GZZ, ZZZ
PGF
22
2s JEDEC Test Card
2s JEDEC Test Card
13.2
(1) Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array Surface Mount Package
Thermal Measurements.
6.2 Packaging Information
PACKAGE
TYPE
PACKAGE
DRAWING
PACKAGE
QTY
ORDERABLE DEVICE
STATUS(1)
PINS
ECO-STATUS(2)
MSL, PEAK TEMP(3)
TMS320VC5502GZZ200
TMS320VC5502GZZ300
TMS320VC5502PGF200
TMS320VC5502PGF300
TMS320VC5502ZZZ200
TMS320VC5502ZZZ300
TMX320VC5502GZZ200
TMX320VC5502GZZ300
TMX320VC5502PGF200
TMX320VC5502PGF300
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
BGA
BGA
GZZ
GZZ
PGF
PGF
ZZZ
ZZZ
GZZ
GZZ
PGF
PGF
201
201
176
176
201
201
201
201
176
176
126
1
N/A
N/A
Level-3-220C-168HR
Level-3-220C-168HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-3-260C-168HR
Level-3-260C-168HR
LQFP
LQFP
BGA
40
1
N/A
N/A
40
126
Green
Green
BGA
BGA
BGA
LQFP
LQFP
(1) The marketing status values are defined as follows:
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
ACTIVE: Active device available for purchase from a TI Authorized Distributor.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does
not recommend using this part in a new design.
LIFEBUY: TI has announced that the device will be discontinued and a lifetime-buy period is in effect.
OBSOLETE: Ti has discontinued production of the device.
(2) Eco-Status Information — Additional details including specific material content can be accessed at
www.ti.com/leadfree.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree.
Mechanical Data
183
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166H–APRIL 2001–REVISED NOVEMBER 2004
Pb-Free: TI defines "Lead (Pb)-Free" or "Pb-Free" to mean RoHS compatible, including a lead concentration
that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified
lead-free soldering processes.Green: TI defines "Green" to mean Lead (Pb)-Free and in addition, uses package
materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product
weight.
Green: TI defines "Green" to mean Lead (Pb)-Free and in addition, uses package materials that do not contain
halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight.
(3)MSL, Peak Temp.— The Moisture Sensitivity Level rating according to the JEDEC industry standard
classifications and peak solder temperature.
The following mechanical package diagram(s) reflect the most current released mechanical data available
for the designated device(s).
184
Mechanical Data
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jul-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320VC5502GZZ200
ACTIVE
BGA MI
CROSTA
R
GZZ
201
126
TBD
SNPB
Level-3-220C-168HR
TMS320VC5502GZZ300
ACTIVE
BGA MI
CROSTA
R
GZZ
201
126
TBD
SNPB
Level-3-220C-168HR
TMS320VC5502PGF200
TMS320VC5502PGF300
TMS320VC5502ZZZ200
ACTIVE
ACTIVE
ACTIVE
LQFP
PGF
PGF
ZZZ
176
176
201
40 Green (RoHS & CU NIPDAU Level-4-260C-72HR
no Sb/Br)
LQFP
40 Green (RoHS & CU NIPDAU Level-4-260C-72HR
no Sb/Br)
BGA MI
CROSTA
R
126 Green (RoHS &
no Sb/Br)
SNAGCU
SNAGCU
Call TI
Level-3-260C-168HR
Level-3-260C-168HR
Call TI
TMS320VC5502ZZZ300
TMX320VC5502GZZ200
TMX320VC5502GZZ300
ACTIVE
BGA MI
CROSTA
R
ZZZ
GZZ
GZZ
201
201
201
126 Green (RoHS &
no Sb/Br)
OBSOLETE BGA MI
TBD
TBD
CROSTA
R
OBSOLETE BGA MI
Call TI
Call TI
CROSTA
R
TMX320VC5502PGF200
TMX320VC5502PGF300
OBSOLETE
OBSOLETE
LQFP
LQFP
PGF
PGF
176
176
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF020A – OCTOBER 1994 – REVISED DECEMBER 1996
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
M
0,08
0,17
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°–7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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