TMS320VC5504_13 [TI]
Fixed-Point Digital Signal Processor;
| 型号： | TMS320VC5504_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processor |
| 文件： | 总128页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5504
Fixed-Point Digital Signal Processor
www.ti.com
SPRS609A–JUNE 2009–REVISED JULY 2009
1 Fixed-Point Digital Signal Processor
1.1 TMS320VC5504 Features
•
•
•
Master/Slave Inter-Integrated Circuit (I2C
Bus™)
•
High-Performance, Low-Power, TMS320C55x™
Fixed-Point Digital Signal Processor
Four Inter-IC Sound (I2S Bus™) for Data
Transport
–
–
–
–
16.67-, 10-ns Instruction Cycle Time
60-, 100-MHz Clock Rate
One/Two Instruction(s) Executed per Cycle
Dual Multipliers [Up to 200 Million
Multiply-Accumulates per Second
(MMACS)]
Device USB Port With Integrated 2.0
High-Speed PHY that Supports:
–
USB 2.0 Full- and High-Speed Device
•
Real-Time Clock (RTC) With Crystal Input, With
Separate Clock Domain, Separate Power
Supply
–
–
Two Arithmetic/Logic Units (ALUs)
Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses
•
•
•
•
Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
–
Fully Software-Compatible With C55x
Devices
Four I/O Isolated Power Supply Domains: RTC
I/O, EMIF I/O, USB PHY, and DVDDIO
–
Industrial Temperature Devices Available
•
256K Bytes Zero-Wait State On-Chip RAM,
Composed of:
Low-Power S/W Programmable Phase-Locked
Loop (PLL) Clock Generator
–
64K Bytes of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
On-Chip ROM Bootloader (RBL) to Boot From
NAND Flash, NOR Flash, SPI EEPROM, or I2C
EEPROM
–
192K Bytes of Single-Access RAM
(SARAM), 24 Blocks of 4K x 16-Bit
•
•
•
•
•
•
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
•
•
128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
16-/8-Bit External Memory Interface (EMIF) with
Glueless Interface to:
–
–
–
8-/16-Bit NAND Flash, 1- and 4-Bit ECC
8-/16-Bit NOR Flash
Asynchronous Static RAM (SRAM)
196-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZCH Suffix)
1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
•
Direct Memory Access (DMA) Controller
–
Four DMA With 4 Channels Each
(16-Channels Total)
1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or
3.3-V I/Os
•
•
•
•
Three 32-Bit General-Purpose Timers
One Selectable as a Watchdog and/or GP
Applications:
–
–
Wireless Audio Devices (e.g., Headsets,
Microphones, Speakerphones, etc.)
Two MultiMedia Card/Secure Digital (MMC/SD)
Interfaces
–
–
–
–
–
–
Echo Cancellation Headphones
Portable Medical Devices
Voice Applications
Industrial Controls
Fingerprint Biometrics
Software Defined Radio
Universal Asynchronous Receiver/Transmitter
(UART)
Serial-Port Interface (SPI) With Four
Chip-Selects
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2009, Texas Instruments Incorporated
TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A–JUNE 2009–REVISED JULY 2009
www.ti.com
1.2 Description
The TMS320VC5504 is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP)
product family and is designed for low-power applications.
The TMS320VC5504 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor
core. The C55x™ DSP architecture achieves high performance and low power through increased
parallelism and total focus on power savings. The CPU supports an internal bus structure that is
composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data
write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the
ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The
TMS320VC5504 also includes four DMA controllers, each with 4 channels, providing data movements for
16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit
data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by
an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize
parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data
Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction
Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the
Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and
Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids
pipeline flushes on execution of conditional instructions.
Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC
Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C
multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.
The VC5504 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM, NOR, NAND, and SRAM. Additional peripherals include: a
high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device
also includes three general-purpose timers with one configurable as a watchdog timer, and a analog
phase-locked loop (APLL) clock generator.
The VC5504 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the
industry’s largest third-party network. Code Composer Studio IDE features code generation tools including
a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and
evaluation modules. The VC5504 is also supported by the C55x DSP Library which features more than 50
foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support
libraries.
2
Fixed-Point Digital Signal Processor
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Fixed-Point Digital Signal Processor
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SPRS609A–JUNE 2009–REVISED JULY 2009
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the VC5504 device.
DSP System
JTAG Interface
C55x™ DSP CPU
Input
Clock(s)
PLL/Clock
Generator
64 KB DARAM
192 KB SARAM
128 KB ROM
Power
Management
Pin
Multiplexing
Switched Central Resource (SCR)
Peripherals
System
Serial Interfaces
I2S
(x4)
GP Timer
(x2)
GP Timer
and/or WD
I2C
SPI
UART
RTC
Connectivity
Program/Data Storage
Interconnect
USB 2.0
PHY (HS)
[DEVICE]
NAND, NOR,
SRAM
DMA
(x4)
MMC/SD
(x2)
Figure 1-1. TMS320VC5504 Functional Block Diagram
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Fixed-Point Digital Signal Processor
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TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A–JUNE 2009–REVISED JULY 2009
www.ti.com
Contents
1
Fixed-Point Digital Signal Processor ................ 1
Temperature (Unless Otherwise Noted) ............ 60
Peripheral Information and Electrical
1.1 TMS320VC5504 Features............................ 1
1.2 Description............................................ 2
1.3 Functional Block Diagram ............................ 3
Revision History ......................................... 5
Device Overview........................................ 11
3.1 Device Characteristics .............................. 11
3.2 C55x CPU ........................................... 12
3.3 Memory Map Summary ............................. 17
3.4 Pin Assignments .................................... 18
3.5 Terminal Functions.................................. 20
3.6 Device Support ...................................... 39
3.7 Documentation Support ............................. 41
Device Configuration .................................. 43
4.1 System Registers.................................... 43
4.2 Power Considerations............................... 44
4.3 Clock Considerations................................ 44
4.4 Boot Sequence...................................... 46
4.5 Configurations at Reset ............................. 49
4.6 Configurations After Reset .......................... 49
4.7 Multiplexed Pin Configurations...................... 53
4.8 Debugging Considerations .......................... 56
Device Operating Conditions ........................ 58
6
Specifications ........................................... 62
6.1 Parameter Information .............................. 62
6.2
Recommended Clock and Control Signal Transition
2
3
Behavior ............................................. 62
6.3 Power Supplies...................................... 63
6.4
External Clock Input From RTC_XI, CLKIN, and
USB_MXI Pins ...................................... 64
6.5 Clock PLLs .......................................... 68
6.6
Direct Memory Access (DMA) Controller............ 71
6.7 Reset ................................................ 72
6.8 Wake-up Events, Interrupts, and XF ................ 76
6.9 External Memory Interface (EMIF) .................. 77
6.10 Multimedia Card/Secure Digital (MMC/SD) ......... 88
6.11 Real-Time Clock (RTC) ............................. 93
4
6.12 Inter-Integrated Circuit (I2C) ........................ 95
6.13 Universal Asynchronous Receiver/Transmitter
(UART) .............................................. 99
6.14 Inter-IC Sound (I2S) ............................... 101
6.15 Serial Port Interface (SPI).......................... 107
6.16 Universal Serial Bus (USB) 2.0 Controller......... 110
6.17 General-Purpose Timers........................... 117
6.18 General-Purpose Input/Output..................... 119
6.19 IEEE 1149.1 JTAG................................. 123
Mechanical Packaging and Orderable
Information............................................. 125
7.1 Thermal Data for ZCH ............................. 125
7.1.1 Packaging Information............................. 125
5
5.1
Absolute Maximum Ratings Over Operating Case
Temperature Range (Unless Otherwise Noted)..... 58
7
5.2 Recommended Operating Conditions............... 59
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
4
Contents
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Fixed-Point Digital Signal Processor
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SPRS609A–JUNE 2009–REVISED JULY 2009
2 Revision History
This data manual revision history highlights the technical changes made to the SPRS609* device-specific
data manual to make it an SPRS609A revision.
Scope: Applicable updates to the TMS320C5000 device family, specifically relating to the
TMS320VC5505 device (Silicon Revisions 1.4) which is now in the production data (PD) stage of
development have been incorporated.
Note: As TMS320VC550x related documentation is released, the ulink references will operate properly. If
the related docs are as yet not released, the ulink will appear to be broken.
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Global
Deleted TIMINT (Timer x Interrupt Register) [1816h, 1856h, and 1896h, respectively] row from the
General-Purpose Timers 0, 1, 2 Registers tables
Section 1.1
TMS320VC5504 Features
•
•
Updated/Changed the "... and Rest of I/O" to " ... and DVDDIO"
Added Low-Power to the S/W Programmable Phase-Locked Loop (PLL) Clock Generator bullet
Section 1.2
Description
•
Updated/Changed "The TMS320VC5504 fixed-point DSP is based on the ..." paragraph
Section 3.1
Table 3-1, Characteristics of the VC5504 Processor:
Device Characteristics
•
•
Updated/Changed the Organization description
Added the Power Characterization rows and supportive data
Section 3.2
C55x CPU
Updated/Changed "The TMS320VC5504 fixed-point digital signal processor (DSP) is based on ..." paragraph
Section 3.2.1
Table 3-2, DARAM Blocks:
On-Chip Dual-Access RAM
(DARAM)
•
•
Moved associated footnote reference to DARAM0
Added missing footnote reference
Section 3.2.5
I/O Memory
•
•
Added "I/O space is separate ..." sentence to first paragraph
Updated/Changed the "Some DMA controllers have access ..." paragraph
Section 3.3
Memory Map Summary
•
•
Updated/Changed "The remainder of the memory map is ..." paragraph
Updated/Changed the "For proper device operation, external ..." paragraph
Section 3.5
Terminal Functions
Table 3-5, Oscillator/PLL Terminal Functions:
•
Updated/Changed the description column for the following signal names: CLKOUT, CLKIN, VDDA_PLL, and
VSSA_PLL
Table 3-6, RTC Terminal Functions:
•
•
Updated/Changed the RTC_CLKOUT description
Updated/Changed the WAKEUP description
Table 3-7, Reset, Interupts, and JTAG Terminal Functions:
•
•
Added a reference for "XDS560 Emulator Technical Reference (literature number: SPRU589)"
Updated/Changed the description column for the following signal names: XF, RESET, TMS, TDO, TDI,
TCK, TRST, EMU1, EMU0, INT1, and INT0
Section 3.5
External Memory Interface (EMIF) Terminal Functions:
Terminal Functions
•
Added reference to the TMS320VC5505/5504 DSP External Memory Interface User's Guide (literature
number: SPRUFO8)
•
•
•
Added EBSR reference to the EM_A[20:15]/GP[26:21] description
Updated/Changed EM_A[20:15]/GP[26:21] description
Deleted "EMIF FUNCTIONAL PINS: ASYNC DEVICE ONLY" title header
Table 3-9, Inter-Integrated Circuit (I2C) Terminal Functions:
•
Added "Per the I2C standard, an external pullup is required on this pin." to both the SCL and SDA signal
name descriptions.
Table 3-10, Inter-IC Sound (I2S0 – I2S3) Terminal Functions:
•
Updated/Changed the description column for the following signal names: I2S0_CLK [L10], I2S0_FS
[M11], I2S1_CLK [M13], I2S1_FS [L14], I2S2_CLK [N10], I2S2_FS [P11], I2S3_CLK [N12], and I2S3_FS
[P13]
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Revision History
5
TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A–JUNE 2009–REVISED JULY 2009
www.ti.com
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Table 3-11, Serial Peripheral Interface (SPI) Terminal Functions:
•
•
Deleted the IPD on the following signal names: SPI_TX [N6] and SPI_RX [P6]
Deleted "The IPD resistor on this pin ..." from the description column on the following signal names:
SPI_TX [N6] and SPI_RX [P6]
•
Deleted "For more detailed information ..." from the description column for the following signal names:
SPI_CS0 [P11], SPI_CLK [N10], SPI_TX [N6], SPI_TX [P12], SPI_RX [P6], and SPI_RX [N11]
Table 3-12, UART Terminal Functions:
•
Deleted "For more detailed information ..." from the description column for the following signal names:
UART_RXD, UART_TXD, UART_CTS, and UART_RTS
Table 3-13, USB2.0 Terminal Functions:
Updated/Changed the description column for the USB_R1 and USB_VSS_REF signal names
Table 3-14, MMC1/SD Terminal Functions:
•
•
Deleted "For more detailed information ..." from the description column for the following signal names:
MMC1_CLK, MMC1_CMD, and MMC1_D[3:0]
Table 3-15, MMC0/SD Terminal Functions:
•
Deleted "For more detailed information ..." from the description column for the following signal names:
MMC0_CLK, MMC0_CMD, and MMC0_D[3:0]
Table 3-16, GPIO Terminal Functions:
•
•
Updated/Changed the description column for the XF signal name
Deleted "For more detailed information ..." from the description column for the following signal names:
GP[0:31]
Table 3-17, Regulators and Power Management Terminal Functions:
•
Updated/Changed the description column for the following signal names: DSP_LDOO, ANA_LDOO,
ANA_LDI, and BG_CAP
Table 3-19, Supply Voltage Terminal Functions:
Updated/Changed the description column for the DVDDIO signal name
Table 3-20, Ground Terminal Functions:
Updated/Changed the description column for the VSSA_ANA signal names
Section 3.6.1, Development Support:
Updated/Changed the DSP/BIOS™ Version from "5.33.04 or later ..." to "5.32.03 or later ..."
Section 4.2, Power Considerations:
Updated/Changed the Analog and USB PHY bullets
Section 4.2.1, LDO Configuration:
Added "can be used to" to the "The VC5504 includes on ..." paragraph
Section 4.2.1.1, Analog LDO:
•
•
Section 3.6
Device Support
•
Section 4
Device Configuration
•
Section 4.2
Power Considerations
•
•
Updated/Changed paragraph
Section 4.3
Clock Considerations
•
•
Updated/Changed "The system clock, which is ..." paragraph
Updated/Changed "The RTC oscillator generates ..." paragraph
Section 4.3.1, Clock Configurations After Device Reset:
•
Added "While the bootloader tries to ..." sentence to end of paragraph
Section 4.4
Boot Sequence
•
•
Updated/Changed the Bootloader process steps
Updated/Changed Figure 4-1, Bootloader Software Architecture
Section 4.4.2
Boot Configuation
•
•
Deleted "Also, at the beginning of the boot process ..." paragraph
Added "At hardware reset, all ..." paragraph to the end of subsection
Section 4.5
Section 4.5.1, Device and Peripheral Configurations at Device Reset:
Configurations at Reset
•
•
Updated/Changed lead-in paragraph
Added "This device also has RESERVED ..." paragraph
Table 4-2, Default Functions Affected by Device Configuration Pins:
Deleted WAKEUP row
Section 4.6, Configurations After Reset:
Updated/Changed paragraph
Section 4.6.1, External Bus Selection Register (EBSR):
Updated/Changed the first paragraph
•
Section 4.6
Configurations After Reset
•
•
6
Revision History
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Fixed-Point Digital Signal Processor
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SPRS609A–JUNE 2009–REVISED JULY 2009
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 4.6.2, EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]:
Updated/Changed the first paragraph
Section 4.6.4, Pull-up/Pull-down Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and 1C19h, respectively]:
Updated/Changed the first paragraph
Section 4.6.5, Output Slew Rate Control Register (OSRCR) [1C16h]:
Deleted "control" for the "The output slew rate control ..." sentence
Section 4.8.1, Pullup/Pulldown Resistors:
•
•
•
Section 4.8
Debugging Considerations
•
•
Updated/Changed "The DSP features internal ..." sentence in the first paragraph
Updated/Changed the "For the configuration pins (listed ..." paragraph
Section 4.8.2, CLKOUT Pin:
•
•
Updated/Changed the "Note: the bootloader ..." paragraph
Updated/Changed the "For more detailed information on the CLKOUT Control ..." paragraph
Section 5
Section 5.1, Absolute Maximum Ratings Over Operating Case Temperature Range:
Device Operating
Conditions
•
•
Updated/Changed the "Input and Output voltage ranges:"
Added Device Operating Life Power-On Hours (POH) rows for Commercial and Industrial temperature
ranges
•
Added associated POH footnote
Section 5
Device Operating
Conditions
Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature:
•
•
Updated/Changed the ISD "Input current shutdown, ANA_LDO" to "ANA_LDO shutdown input current"
Updated/Changed the IILPU input only pin, internal pulldown or pullup disabled MAX value of "±1 µA" to a
MIN and MAX value of "-5 and +5 µA", respectively
•
•
•
•
Added an IIHPD input only pin, internal pulldown or pullup disabled row
Updated/Changed the IIH/IIL , Input current [DC], ALL pins MIN value from "-10" to "-5" µA
Updated/Changed the IIH/IIL , Input current [DC], ALL pins MAX value from "-10" to "-5" µA
Updated/Changed the IOZ, All Pins (except USB) MAX value of "±20 µA" to a MIN and MAX value of "-10
and +10 µA", respectively
Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature:
•
•
•
Updated/Changed the ICDD, Core (CVDD) supply current, CVDD = 1.3 V, DSP clock = 100 MHz TYP value
to "0.22 mW/MHz"
Updated/Changed the ICDD, Core (CVDD) supply current, CVDD = 1.05 V, DSP clock = 60 MHz TYP value
to "0.15 mW/MHz"
Added "Active, " to the TEST CONDITIONS description for both CVDD = 1.3 V and CVDD = 1.05 V
Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature:
•
Added additional Active and Standby power values to the ICDD, Core (CVDD) supply current
Section 6.3, Power Supplies:
Updated/Changed the paragraph
Section 6
Peripheral Information and
Electrical Specifications
•
Section 6.3
Section 6.3.1, Power Supply Sequencing:
Power Supplies
•
•
Updated/Changed the lead-in paragraph
Updated/Changed the power-up sequence requirement steps
Section 6.3.2, Power-Supply Design Considerations:
Updated/Changed the paragraph
Section 6.3.3, Power-Supply Decoupling:
•
•
•
Updated/Changed the first paragraph
Updated/Changed the "... Large bulk caps ..." pargraph value from "100" to "10" µF
Section 6.3.4, LDO Input Decoupling:
Added as new Section
Section 6.3.5, LDO Output Decoupling:
Added as new Section
Section 6.4.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal:
•
•
Section 6.4
External Clock Input From
RTC_XI, CLKIN, and
USB_MXI Pins
•
•
•
Updated/Changed the last sentence in the first paragraph
Updated/Changed the "The crystal should be ..." paragraph
Updated/Changed Figure 6-3, 32.768-kHz RTC Oscillator
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Revision History
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TMS320VC5504
Fixed-Point Digital Signal Processor
SPRS609A–JUNE 2009–REVISED JULY 2009
www.ti.com
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 6.4.2, CLKIN Pin With LVCMOS-Compatible Clock Input (Optional):
•
•
•
Updated/Changed the "A LVCMOS-compatible clock input ..." paragraph
Updated/Changed Figure 6-4, LVCMOS-Compatible Clock Input With RTC Oscillator Enabled
Updated/ChangedFigure 6-5, LVCMOS-Compatible Clock Input With RTC Oscillator Disabled
Section 6.4.3, USB On-Chip Oscillator With External Crystal (Optional):
•
•
Updated/Changed the "The USB on-chip oscillator can ..." paragraph
Updated/Changed the "The crystal should be in fundamental-mode ..." paragraph
Section 6.5
Clock PLLs
Section 6.5.1, PLL Device-Specific Information:
•
•
Updated/Changed the first paragraph
Updated/Changed the , PLLC1 Clock Frequency Ranges
Section 6.5.3
Table 6-3, Timing Requirements for CLKIN:
Added new table
Clock PLL Electrical
Data/Timing (Input and
Output Clocks)
•
Table 6-4, Switching Characteristics Over Recommended Operating Conditions for CLKOUT:
•
•
•
Updated/Changed PARAMETER NO. 4, tt(CLKOUTR) MAX value for CVDD = 1.05 V from "8.33" to "5" ns
Updated/Changed PARAMETER NO. 5, tt(CLKOUTF) MAX value for CVDD = 1.05 V from "8.33" to "5" ns
Added an associated footnote
Section 6.7
Reset
Section 6.7, Reset:
•
•
Updated/Changed the paragraph
Added new Subsections
Section 6.8.1
Table 6-6, Timing Requirements for Interrupts:
Interrupts Electrical
Data/Timing
•
•
•
Updated/Changed PARAMETER NO. 1, tw(INTH) MIN value from "3P" to "2P" ns
Updated/Changed PARAMETER NO. 2, tw(INTL) MIN value from "3P" to "2P" ns
Updated/Changed associated "P = ..." footnote
Table 6-8, Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE:
•
•
•
Updated/Changed PARAMETER NO. 2, td(WKEVTH-CLKGEN) "IDLE3 Mode with ..." descriptions
Deleted PARAMETER NO. 2, td(WKEVTH-CLKGEN) for IDLE3 Mode with SYSCLKDIS = 1; INTx event
Updated/Changed PARAMETER NO. 2, td(WKEVTH-CLKGEN) "IDLE2 Mode; INTx event ..." from "4P" to
"3P" ns
Figure 6-12, Wake-Up From IDLE Timings:
Added "CLKOUT reflects either ..." footnote
Figure 6-13, XF Timings:
Updated/Changed the footnote
Section 6.9.3, EMIF Electrical Data/Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.8/2.5 V and CVDD = 1.05 V,
•
Section 6.8.3
XF Electrical Data/Timing
•
Section 6.9
External Memory Interface DVDDEMIF = 1.8 V:
(EMIF)
•
Updated/Changed the section title
Section 6.9.4, EMIF Electrical Data/Timing CVDD = 1.3 V, DVDDEMIF = 3.3/2.8/2.5 V and CVDD = 1.3 V,
DVDDEMIF = 1.8 V:
•
Updated/Changed the section title
Section 6.10
Multimedia Card/Secure
Digital (MMC/SD)
•
Updated/Changed the first paragraph
Section 6.10.2
MMC/SD Electrical
Data/Timing
Table 6-18, Switching Characteristics Over Recommended Operating Conditions for MMC Output:
•
•
•
Updated/Changed PARAMETER NO. 9, tw(CLKL) MIN value for FAST MODE from "6" to "7" ns
Updated/Changed PARAMETER NO. 10, tw(CLKH) MIN value for FAST MODE from "6" to "7" ns
Updated/Changed PARAMETER NO. 13, twd(MDCLKL-CMDIV) MIN values for both FAST MODE and STD
MODE from "-4.5" to "-4" ns.
•
•
Updated/Changed PARAMETER NO. 15, twd(MDCLKL-DATIV) MIN values for both FAST MODE and STD
MODE from "-4.5" to "-4" ns.
Added the "For MMC/SD, the parametric values ..." footnote
Section 6.11
Real-Time Clock (RTC)
•
•
•
Updated/Changed the first paragraph
Updated/Changed the "Control of the RTC is ..." paragraph
Added two new paragraphs before the "RTC Peripheral Register Description(s) section
8
Revision History
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Fixed-Point Digital Signal Processor
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SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Table 6-21, Timing Requirements for I2C Timings:
Section 6.12.2
I2C Electrical Data/Timing
•
•
Updated/Changed "The I2C pins SDA and SCL do not ..." footnote
Added associated footnote for rise and fall time parameters
Table 6-22, Switching Characteristics for I2C Timings:
•
Added associated footnote for rise and fall time parameters
Section 6.13
•
Updated/Changed the lead-in paragraph
Universal Asynchronous
Receiver/Transmitter
(UART)
Section 6.13.2
UART Electrical
Data/Timing
Table 6-25, Switching Characteristics Over Recommended Operating Conditions for UART Transmit:
•
Updated/Changed PARAMETER NO. 1, f(baud) parameter description
[Receive/Transmit]
Section 6.14
Inter-IC Sound (I2S)
•
Updated/Changed the lead-in sentence in the second paragraph
Section 6.14.2
I2S Electrical Data/Timing
Table 6-30, Timing Requirements for I2S:
Added "[I/O = 3.3 V, 2.8 V, and 2.5 V]" to the table title
Table 6-31, Timing Requirements for I2S [I/O = 1.8 V]:
Added as a new table
Table 6-32, Switching Characteristics Over Recommended Operating Conditions for I2S Output:
•
•
•
•
Added "[I/O = 3.3 V, 2.8 V, and 2.5 V]" to the table title
Updated/Changed PARAMETER NO. 4, tdmax(CLKL-DXV) MAX value for MASTER CVDD = 1.05 V from "19"
to "15" ns
•
•
•
•
•
•
•
Updated/Changed PARAMETER NO. 4, tdmax(CLKL-DXV) MAX value for MASTER CVDD = 1.3 V from "15"
to "14" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKH-DXV) MAX value for MASTER CVDD = 1.05 V from
"19" to "15" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKH-DXV) MAX value for MASTER CVDD = 1.3 V from "15"
to "14" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKL-DXV) MAX value for SLAVE CVDD = 1.05 V from "–" to
"12" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKL-DXV) MAX value for SLAVE CVDD = 1.3 V from "–" to
"12" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKH-DXV) MAX value for SLAVE CVDD = 1.05 V from "–" to
"12" ns
Updated/Changed PARAMETER NO. 4, tdmax(CLKH-DXV) MAX value for SLAVE CVDD = 1.3 V from "–" to
"12" ns
•
•
•
•
Updated/Changed PARAMETER NO. 5, toh(DXV-CLKH) MIN value for SLAVE CVDD = 1.05 V from "–" to "0"
ns
Updated/Changed PARAMETER NO. 5, toh(DXV-CLKH) MIN value for SLAVE CVDD = 1.3 V from "–" to "0"
ns
Updated/Changed PARAMETER NO. 5, toh(DXV-CLKL) MIN value for SLAVE CVDD = 1.05 V from "–" to "0"
ns
Updated/Changed PARAMETER NO. 5, toh(DXV-CLKL) MIN value for SLAVE CVDD = 1.3 V from "–" to "0"
ns
Table 6-33, Switching Characteristics Over Recommended Operating Conditions for I2S Output [I/O = 1.8 V]:
•
Added as a new table
Section 6.16
Universal Serial Bus (USB)
2.0 Controller
•
•
Updated/Changed the "USB 2.0 ..." bullet
Added a new paragraph and bullets
Section 6.16.2
USB2.0 Electrical
Data/Timing
Table 6-38, Switching Characteristics Over Recommended Operating Conditions for USB2.0:
•
•
Deleted the MAX values from PARAMETER NO. 1 and 2 for HIGH SPEED only
Added two footnotes and associated references
Section 6.18
General-Purpose
Input/Output
•
•
Added new "All GPIO pin have ..." bullet
Updated/Changed the "All GPIOs can be ..." bullet
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SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Table 6-44, Timing Requirements for GPIO Inputs:
Updated/Changed the table
Section 6.18.2
GPIO Peripheral
Input/Output Electrical
Data/Timing
•
Figure 6-31, GPIO Port Timing:
Updated/Changed the figure
Table 6-46, Timing Requirements for GPIO Input Latency:
•
Section 6.18.3
GPIO Peripheral Input
Latency Electrical
Data/Timing
•
•
Added new latency table
Deleted Timing Requirements for External Interrupts table
Section 6.19
IEEE 1149.1 JTAG
•
Updated/Changed section paragraphs
10
Revision History
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3 Device Overview
3.1 Device Characteristics
Table 3-1, provides an overview of the TMS320VC5504 DSP. The tables show significant features of the
VC5504 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 3-1. Characteristics of the VC5504 Processor
HARDWARE FEATURES
VC5504
Asynchronous (8/16-bit bus width) SRAM, Flash (NOR, NAND)
2 MMC/SD
Peripherals
External Memory Interface (EMIF)
Flash Cards
Not all peripheral pins are
available at the same time
(for more detail, see the
Device Configurations
section).
Four DMA controllers each with four channels,
for a total of 16 channels
DMA
2 32-Bit General-Purpose (GP) Timers
1 Additional Configurable as a 32-Bit GP Timer and/or a
Watchdog
Timers
UART
1 (with RTS/CTS flow control)
1 with 4 chip selects
SPI
I2C
1 (Master/Slave)
I2S
4 (Two Channel, Full Duplex Communication)
High- and Full-Speed Device
USB 2.0 (Device only)
256 byte read/write buffer, max 50-MHz clock for SD cards,
and signaling for DMA transfers
MMC/SD
Real-Time Clock (RTC)
1 (Crystal Input, Separate Clock Domain and Power Supply)
Up to 26 pins (with 1 Additional General-Purpose Output (XF))
256KB RAM, 128KB ROM
General-Purpose Input/Output Port (GPIO)
Size (Bytes)
•
64KB On-Chip Dual-Access RAM (DARAM)
192KB On-Chip Single-Access RAM (SARAM)
128KB On-Chip Single-Access ROM (SAROM)
On-Chip Memory
Organization
•
•
JTAGID Register
(Value is: 0009_702F)
JTAG BSDL_ID
CPU Frequency
see Figure 6-32
1.05-V Core
60 MHz
100 MHz
MHz
1.3-V Core
1.05-V Core
16.67 ns
Cycle Time
Voltage
ns
1.3-V Core
10 ns
1.05 V (60MHz)
1.3 V (100 MHz)
1.8 V, 2.5 V, 2.8 V, 3.3 V
Core (V)
I/O (V)
Active @ Room Temp 25°C, 75% DMAC +
25% ADD (Typical Sine Wave Data
Switching)
0.15 mW/MHz @ 1.05 V, 60 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Power Characterization
Active @ Room Temp 25°C, 75% DMAC +
25% NOP (Typical Sine Wave Data
Switching)
0.14 mW/MHz @ 1.05 V, 60 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
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Table 3-1. Characteristics of the VC5504 Processor (continued)
HARDWARE FEATURES
Software Programmable Multiplier
10 x 10 mm
VC5504
x4 to x4099 multiplier
196-Pin BGA (ZCH)
0.09 µm
PLL Options
BGA Package
Process Technology
µm
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(1)
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
3.2 C55x CPU
The TMS320VC5504 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation
processor core. The C55x DSP architecture achieves high performance and low power through increased
parallelism and total focus on power savings. The CPU supports an internal bus structure that is
composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read
buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These
buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA
controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional
16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel
activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit
(DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a
128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit
decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instructions calls.
For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide
(literature number SWPU073).
The C55x core of the VC5504 can address 16M bytes of unified data and program space. It also
addresses 64K words of I/O space. The VC5504 includes three types of on-chip memory: 128 KB
read-only memory (ROM), 192 KB single-access random access memory (SARAM), 64 KB dual-access
random access memory (DARAM). The memory map is shown in Figure 3-1.
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3.2.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h – 00FFFFh and is composed of eight blocks of
4K words each (see Table 3-2). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.
Table 3-2. DARAM Blocks
CPU
DMA CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
BYTE ADDRESS RANGE
000000h – 001FFFh
002000h – 003FFFh
004000h – 005FFFh
006000h – 007FFFh
008000h – 009FFFh
00A000h – 00BFFFh
00C000h – 00DFFFh
00E000h – 00FFFFh
0001 0000h – 0001 1FFFh
0001 2000h – 0001 3FFFh
0001 4000h – 0001 5FFFh
0001 6000h – 0001 7FFFh
0001 8000h – 0001 9FFFh
0001 A000h – 0001 BFFFh
0001 C000h – 0001 DFFFh
0001 E000h – 0001 FFFFh
DARAM 0(1)
DARAM 1
DARAM 2
DARAM 3
DARAM 4
DARAM 5
DARAM 6
DARAM 7
(1) The first 192 bytes are reserved for memory-mapped registers (MMRs). See , TMS320VC5504
Memory Map Summary.
3.2.2 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h – 03FFFFh and is composed of 24 blocks of
4K words each (see Table 3-3). Each SARAM block can perform one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed
by the USB DMA bus.
Table 3-3. SARAM Blocks
CPU
DMA/USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
BYTE ADDRESS RANGE
010000h – 011FFFh
012000h – 013FFFh
014000h – 015FFFh
016000h – 017FFFh
018000h – 019FFFh
01A000h – 01BFFFh
01C000h – 01DFFFh
01E000h – 01FFFFh
020000h – 021FFFh
022000h – 023FFFh
024000h – 025FFFh
026000h – 027FFFh
028000h – 029FFFh
02A000h – 02BFFFh
02C000h – 02DFFFh
02E000h – 02FFFFh
030000h – 031FFFh
032000h – 033FFFh
0009 0000h – 0009 1FFFh
0009 2000h – 0009 3FFFh
0009 4000h – 0009 5FFFh
0009 6000h – 0009 7FFFh
0009 8000h – 0009 9FFFh
0009 A000h – 0009 BFFFh
0009 C000h – 0009 DFFFh
0009 E000h – 0009 FFFFh
000A 0000h – 000A 1FFFh
000A 2000h – 000A 3FFFh
000A 4000h – 000A 5FFFh
000A 6000h – 000A 7FFFh
000A 8000h – 000A 9FFFh
000A A000h – 000A BFFFh
000A C000h – 000A DFFFh
000A E000h – 000A FFFFh
000B 0000h – 000B 1FFFh
000B 2000h – 000B 3FFFh
SARAM 0
SARAM 1
SARAM 2
SARAM 3
SARAM 4
SARAM 5
SARAM 6
SARAM 7
SARAM 8
SARAM 9
SARAM 10
SARAM 11
SARAM 12
SARAM 13
SARAM 14
SARAM 15
SARAM 16
SARAM 17
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Table 3-3. SARAM Blocks (continued)
CPU
DMA/USB CONTROLLER
MEMORY BLOCK
BYTE ADDRESS RANGE
034000h – 035FFFh
036000h – 037FFFh
038000h – 039FFFh
03A000h – 03BFFFh
03C000h – 03DFFFh
03E000h – 03FFFFh
040000h – 04FFFFh
BYTE ADDRESS RANGE
000B 4000h – 000B 5FFFh
000B 6000h – 000B 7FFFh
000B 8000h – 000B 9FFFh
000B A000h – 000B BFFFh
000B C000h – 000B DFFFh
000B E000h – 000B FFFFh
000C 0000h – 000C FFFFh
SARAM 18
SARAM 19
SARAM 20
SARAM 21
SARAM 22
SARAM 23
Reserved
3.2.3 On-Chip Read-Only Memory (ROM)
The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be
mapped by software to the external memory or to the internal ROM.
The standard VC5504 device includes a Bootloader program resident in the ROM.
When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range
FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status
register is set through software, the on-chip ROM is disabled and not present in the memory map, and
byte address range FE0000h – FFFFFFh is directed to external memory space. A hardware reset always
clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses.
Each on-chip ROM block is a one cycle per word access memory.
3.2.4 External Memory
The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The
external memory space is divided into four chip select spaces: EMIF CS2 through CS5 space dedicated to
asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called
EMIF_CSx) that is activated during an access to the chip select space.
The external memory interface (EMIF) provides the means for the DSP to access external memories and
other devices including: NOR Flash, NAND Flash, and SRAM. Before accessing external memory, you
must configure the EMIF through its memory-mapped registers.
The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 4
dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pin of the
EMIF can be operated at an independent voltage from the rest of other I/O pins on the device.
For more details on the EMIF, see the TMS320VC5505 Digital Signal Processor (DSP) External Memory
Interface (EMIF) User’s Guide (literature number SPRUFO8).
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3.2.5 I/O Memory
The VC5504 DSP includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals
and system registers used for idle control, status monitoring and system configuration. I/O space is
separate from program/memory space and is accessed with separate instruction opcodes or via the
DMA's.
Table 3-4 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O
space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor
DMA.. For the expanded tables of each peripheral, see Section 6, Peripheral Information and Electrical
Specifications of this document.
Some DMA controllers have access to the I/O-Space memory-mapped registers of the following
peripherals registers: I2C, UART, I2S, MMC/SD, EMIF, and USB.
Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is
not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the
Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2). For more detailed information on the
PRCR (1C05h), PCGCR1 (1C02h), and PCGCR2 (1C03h) registers, see the TMS320VC5505 DSP
System User's Guide (literature number SPRUFP0).
Table 3-4. Peripheral I/O-Space Control Registers
WORD ADDRESS
0x0000 – 0x0004
PERIPHERAL
Idle Control
Reserved
DMA0
0x0005 – 0x000D through 0x0803 – 0x0BFF
0x0C00 – 0x0C7F
0x0C80 – 0x0CFF
Reserved
DMA1
0x0D00 – 0x0D7F
0x0D80 – 0x0DFF
Reserved
DMA2
0x0E00 – 0x0E7F
0x0E80 – 0x0EFF
Reserved
DMA3
0x0F00 – 0x0F7F
0x0F80 – 0x0FFF
Reserved
EMIF
0x1000 – 0x10DD
0x10EE – 0x10FF through 0x1300 – 0x17FF
0x1800 – 0x181F
Reserved
Timer0
0x1820 – 0x183F
Reserved
Timer1
0x1840 – 0x185F
0x1860 – 0x187F
Reserved
Timer2
0x1880 – 0x189F
0x1900 – 0x197F
RTC
0x1980 – 0x19FF
Reserved
I2C
0x1A00 – 0x1A6C
0x1A6D – 0x1AFF
Reserved
UART
0x1B00 – 0x1B1F
0x1B80 – 0x1BFF
Reserved
System Control
Reserved
I2S0
0x1C00 – 0x1CFF
0x1D00 – 0x1FFF through 0x2600 – 0x27FF
0x2800 – 0x2840
0x2900 – 0x2940
I2S1
0x2A00 – 0x2A40
I2S2
0x2B00 – 0x2B40
I2S3
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Table 3-4. Peripheral I/O-Space Control Registers (continued)
WORD ADDRESS
PERIPHERAL
Reserved
0x2C41 – 0x2FFF
0x3000 – 0x300F
0x3010 – 0x39FF
0x3A00 – 0x3A1F
0x3A20 – 0x3AFF
0x3B00 – 0x3B1F
0x3B2F – 0x6FFF
0x7000 – 0x70FF
0x7100 – 0x7FFF
0x8000 – 0xFFFF
SPI
Reserved
MMC/SD0
Reserved
MMC/SD1
Reserved
Analog Control Registers
Reserved
USB
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3.3 Memory Map Summary
The VC5504 provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and
external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two
accesses to a given block during the same cycle. The VC5504 supports 8 blocks of 4K words of
dual-access RAM. The on-chip, single-access RAM allows one access to a given block per cycle. The
VC5504 supports 24 blocks of 4K words of single-access RAM.
The remainder of the memory map is divided into reserved areas, four external spaces, and on-chip ROM.
Each external space has a chip select decode signal (called CS[2:5]) that indicates an access to the
selected space. The external memory interface (EMIF) supports access to asynchronous memories such
as SRAM, NAND, or NOR.
The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the
four DMA controllers, and USB (see Figure 3-1).
CPU BYTE DMA/USB BYTE
ADDRESS(A)
ADDRESS(A)
MEMORY BLOCKS
MMR (Reserved)(B)
BLOCK SIZE
000000h
0001 0000h
0000C0h
010000h
0001 00C0h
0009 0000h
DARAM(D)
64K Minus 192 Bytes
192K Bytes
64K Bytes
SARAM
040000h
050000h
000C 0000h
0100 0000h
Reserved
8M Minus 256K Bytes
Reserved
800000h
C00000h
E00000h
F00000h
0200 0000h
0300 0000h
0400 0000h
0500 0000h
External-CS2 Space(C)
External-CS3 Space(C)
4M Bytes Asynchronous
2M Bytes Asynchronous
External-CS4 Space(C)
External-CS5 Space(C)
1M Bytes Asynchronous
1M Minus 128K Bytes Asynchronous
FE0000h
FFFFFFh
050E 0000h
050F FFFFh
External-CS5 Space(C)
(if MPNMC=1)
128K Bytes Asynchronous (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
ROM
(if MPNMC=0)
A. Address shown represents the first byte address in each block.
B. The first 192 bytes are reserved for memory-mapped registers (MMRs).
C. Out of the four DMA controllers, only DMA controller 3 has access to the external memory space.
D. The USB controller does not have access to DARAM.
Figure 3-1. TMS320VC5504 Memory Map Summar
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3.4 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using software programmable register
settings. For more information on pin muxing, see Section 4.7, Multiplexed Pin Configurations of this
document.
3.4.1 Pin Map (Bottom View)
Figure 3-2 shows the bottom view of the package pin assignments.
I2S2_FS/
GP[19]/
SPI_CS0
I2S2_DX/
GP[27]/
SPI_TX
UART_CTS/ UART_TXD/
GP[29]/
I2S3_FS
EM_DQM1
SPI_RX
SPI_TX
GP[12]
GP[13]
GP[15]
GP[16]
GP[17]
GP[31]/
I2S3_DX
SPI_CS0
SPI_CS1
EM_CS3
EM_D[4]
EM_D[13]
SPI_CS2
DV
DV
DV
DDIO
DDIO
P
N
M
L
DDEMIF
I2S2_CLK/
GP[18]/
SPI_CLK
I2S2_RX/
GP[20]/
SPI_RX
UART_RTS/ UART_RXD/
GP[28]/
I2S3_CLK
EM_A[15]/
GP[21]
RSV13
EM_D[5]
EM_A[10]
GP[14]
GP[30]/
I2S3_RX
SPI_CLK
RSV12
DV
SPI_CS3
EMU1
DDIO
MMC0_D1/ MMC0_CMD/
I2S0_FS/
GP[1]
MMC1_D1/
I2S1_RX/
GP[9]
MMC1_CLK/
I2S1_CLK/
GP[6]
MMC1_D0/
I2S1_DX/
GP[8]
I2S0_RX/
GP[3]
EM_A[14]
EM_A[13]
XF
TCK
TDO
TDI
TRST
MMC0_D0/
I2S0_DX/
GP[2]
MMC0_CLK/
I2S0_CLK/
GP[0]
MMC1_CMD/
I2S1_FS/
GP[7]
MMC0_D3/
GP[5]
MMC0_D2/
GP[4]
MMC1_D3/
GP[11]
EM_D[12]
EM_D[14]
CV
DD
EMU0
TMS
MMC1_D2/
GP[10]
EM_A[12]/
(CLE)
EM_A[11]/
(ALE)
EM_WAIT3
EM_D[6]
DV
V
V
CV
V
DV
V
SS
K
J
DDIO
SS
SS
SS
SS
DD
SS
DDIO
EM_A[20]/
GP[26]
V
USB_VBUS USB_V
USB_DM
USB_DP
EM_A[8]
EM_WE
EM_A[9]
EM_A[7]
EM_D[15]
RSV1
RSV2
DD1P3
SS1P3
DV
V
CV
DD
V
DDEMIF
SS
USB_
USB_
USB_
USB_
V
DDA3P3
EM_WAIT5
USB_V
EM_D[7]
EM_D[0]
DV
DDEMIF
DV
DDEMIF
DV
DDEMIF
V
SS
DV
DDEMIF
CV
DD
H
G
F
V
V
V
SSA1P3
DDA1P3
SSA3P3
EM_A[18]/
GP[24]
EM_A[19]/
GP[25]
EM_WAIT4
USB_V
USB_R1
USB_V
USB_V
USB_V
USB_M12XI USB_M12XO
DDOSC
DDPLL
SSREF
SSPLL
V
SS
VSS
EM_A[17]/
GP[23]
DV
USB_V
USB_LDOO
USB_LDOI
DSP_LDOI
EM_A[6]
EM_D[2]
EM_D[8]
EM_D[10]
EM_CS4
RSV10
EM_D[9]
EM_OE
EM_D[3]
EM_D[11]
RSV15
SSOSC
CVDD
DV
DDRTC
V
SS
V
SS
DDIO
EM_A[16]/
GP[22]
DSP_LDOO
EM_D[1]
WAKEUP
DV
INT1
V
V
V
V
V
V
SS
E
D
C
B
A
EM_A[2]
EM_A[5]
DDEMIF
RESET
INT0
SS
SS
SS
SS
RTC_
CLKOUT
DSP_
LDO_EN
V
EM_WAIT2
RSV6
DSP_LDO_V
RSV3
RSV4
EM_A[3]
EM_A[1]
EM_A[0]
SSA_PLL
V
SS
SS
V
V
CV
DDA_PLL
EM_CS2
DDRTC
EM_A[4]
CLK_SEL
SSRTC
RSV9
RSV8
RSV0
RSV5
V
V
SSA_ANA
EM_BA[1]
EM_DQM0
ANA_LDOI
EM_R/W
RTC_XI
SSA_ANA
BG_CAP
SCL
SDA
EM_BA[0]
RSV11
RTC_XO
V
ANA_LDOO
RSV7
11
DV
EM_CS5
DV
DDEMIF
RSV14
DDA_ANA
CLKOUT
CLKIN
DDEMIF
V
V
SS
SS
1
2
3
4
5
6
7
8
9
10
12
13
14
A. Shading denotes pins not supported on this device. To ensure proper device operation, these pins must be hooked
up properly, see Table 3-17, Regulators and Power Management Terminal Functions.
Figure 3-2. VC5504 Pin Map(A)
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Fixed-Point Digital Signal Processor
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3.5 Terminal Functions
The terminal functions tables (Table 3-5 through Table 3-20) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pins, and debugging
considerations, see the Device Configuration section of this data manual.
For proper device operation, external pullup/pulldown resistors may be required on some pins.
Section 4.8.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are
required.
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Table 3-5. Oscillator/PLL Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap
different clocks within the DSP clock generator. The SRC bits in the CLKOUT
Control Source Register (CCSSR) can be used to specify the CLKOUT pin source.
Additionally, the slew rate of the CLKOUT pin can be controlled by the Output
Slew Rate Control Register (OSRCR) [0x1C16]. For more detailed information on
the CCSSR and OSRCR registers, see the TMS320VC5505 DSP System User's
Guide (literature number: SPRUFP0)
–
CLKOUT
A7
O/Z
DVDDIO
The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55
register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At
reset the CLKOUT pin is enabled until the beginning of the boot sequence, when
the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z).
For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU
Reference Guide (literature number: SWPU073).
Input clock. This signal is used to input an external clock when the 32-KHz on-chip
oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the
CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.
The CLK_SEL pin (C7) selects between the 32-KHz crystal clock or CLKIN.
When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When
CLK_SEL is high, this pin should be driven by an external clock source.
–
CLKIN
A8
I
DVDDIO
If CLK_SEL is high, this pin is used as the reference clock for the clock generator
and during bootup the bootloader bypasses the PLL and assumes the CLKIN
frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With
these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz, the
I2C clock rate at 400 KHz, and UART at 57600 baud.
Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN.
0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator
while CLKIN is ignored.
1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator
drives only the RTC timer.
–
CLK_SEL
C7
I
DVDDIO
This pin is not allowed to change during device operation; it must be tied high or
low at the board.
see Section 5.2,
ROC
VDDA_PLL
VSSA_PLL
C10
D9
PWR
GND
1.3-V Analog PLL power supply for the system clock generator.
Analog PLL ground for the system clock generator.
see Section 5.2,
ROC
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-6. Real-Time Clock (RTC) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
Real-time clock oscillator output. This pin operates at the RTC core voltage,
CVDDRTC, and supports a 32.768-kHz crystal.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC
(see Section 5.2, Recommended Operating Conditions).
–
RTC_XO
RTC_XI
A9
I
CVDDRTC
Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h
– 197Fh) are not accessible.
Real-time clock oscillator input.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC
(see Section 5.2, Recommended Operating Conditions).
–
B9
I
CVDDRTC
Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h
– 197Fh) are not accessible.
Real-time clock output pin. This pin operates at DVDDRTC voltage. The
RTC_CLKOUT pin is enabled/disabled through the RTCCLKOUTEN bit in the RTC
Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is
disabled (high-impedance [Hi-Z]).
–
O/Z
RTC_CLKOUT
WAKEUP
D8
E8
DVDDRTC
The pin is used to WAKEUP the core from idle condition. This pin defaults to an
input at CVDDRTC powerup, but can also be configured as an active-low open-drain
output signal to wakeup an external device from an RTC alarm.
–
I/O/Z
DVDDRTC
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-7. RESET, Interrupts, and JTAG Terminal Functions
SIGNAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
RESET
External Flag Output. XF is used for signaling other processors in
multiprocessor configurations or XF can be used as a fast
general-purpose output pin.
–
XF is set high by the BSET XF instruction and XF is set low by the
BCLR XF instruction or by writing to bit 13 of the ST1_55 register. At
reset, the XF pin will be high. For more information on the ST1_55
register, see the TMS320C55x 3.0 CPU Reference Guide (literature
number: SWPU073).
XF
M8
O/Z
DVDDIO
Device reset. RESET causes the DSP to terminate execution and loads
the program counter with the contents of the reset vector. When
RESET is brought to a high level, the reset vector in ROM at FFFF00h
forces the program execution to branch to the location of the on-chip
ROM bootloader.
IPU
DVDDIO
RESET
D6
I
RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register but will be forced ON when RESET is asserted.
JTAG
[For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number:
SPRU589).]
IEEE standard 1149.1 test mode select. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TMS must be buffered. In this case, the input buffer for TMS
needs pullup resistors connected to DVDDIO to hold these signals at a
IPU
DVDDIO
TMS
L8
I
known value when the emulator is not connected. A resistor value of
4.7 kΩ or greater is suggested. For board design guidelines related to
the emulation header, see the XDS560 Emulator Technical Reference
(literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge
of TCK. TDO is in the high-impedance (Hi-Z) state except when the
scanning of data is in progress.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
If the emulation header is located greater than 6 inches from the
device, TDO must be buffered.
–
TDO
M7
O/Z
DVDDIO
IEEE standard 1149.1 test data input. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TDI must be buffered. In this case, the input buffer for TDI need
pull-up resistors connected to DVDDIO to hold these signals at a known
value when the emulator is not connected. A resistor value of 4.7 kΩ or
greater is suggested.
IPU
DVDDIO
TDI
L7
I
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-7. RESET, Interrupts, and JTAG Terminal Functions (continued)
SIGNAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on test access port (TAP) of
input signals TMS and TDI are clocked into the TAP controller,
instruction register, or selected test data register on the rising edge of
TCK. Changes at the TAP output signal (TDO) occur on the falling
edge of TCK.
IPU
DVDDIO
TCK
M6
I
If the emulation header is located greater than 6 inches from the
device, TCK must be buffered.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IEEE standard 1149.1 reset signal for test and emulation logic. TRST,
when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the
device operates in its functional mode, and the IEEE standard 1149.1
signals are ignored. The VC5504 will not operate properly if this reset
pin is never asserted low.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
It is recommended that an external pulldown resistor be used in
addition to the IPD -- especially if there is a long trace to an emulation
header.
IPD
DVDDIO
TRST
M9
I
Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator
system and is defined as input/output by way of the emulation logic.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
An external pullup to DVDDIO is required to provide a signal rise time of
less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IPU
DVDDIO
EMU1
M5
I/O/Z
Emulator 0 pin. When TRST is driven low and then high, the state of
the EMU0 pin is latched and used to connect the JTAG pins (TCK,
TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when
the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the
latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an
interrupt to or from the emulator system and is defined as input/output
by way of the emulation logic.
An external pullup to DVDDIO is required to provide a signal rise time of
less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
IPU
DVDDIO
EMU0
L6
I/O/Z
EXTERNAL INTERRRUPTS
IPU
DVDDIO
External interrupt inputs (INT1 and INT0). These pins are maskable via
INT1
INT0
E7
C6
I
I
their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt
mode bit. The pins can be polled and reset by their specific Interrupt
Flag Register (IFR1, IFR0).
The IPU resistor on these pins can be enabled or disabled via the
PDINHIBR2 register.
IPU
DVDDIO
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Table 3-8. External Memory Interface (EMIF) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)
Note: When accessing 8-bit Asynchronous memory, pins EM_A[20:0] should be
connected to memory address pins [22:2] and EM_BA[1:0] should be connected to
memory addresss pins [1:0]. For 16-bit Asynchronous memory, pins EM_A[20:0]
should be connected to memory address pins [20:1] and EM_BA[1] should be
connected to memory addresss pin [0]. For more detailed information, see the
TMS320VC5505/5504 DSP External Memory Interface User's Guide (literature
number: SPRUFO8).
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 20.
Mux control via the A20_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
EM_A[20]/GP[26]
EM_A[19]/GP[25]
EM_A[18]/GP[24]
EM_A[17]/GP[23]
EM_A[16]/GP[22]
EM_A[15]/GP[21]
J3
G4
G2
F2
E2
N1
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 19.
Mux control via the A19_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 18.
Mux control via the A18_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 17.
Mux control via the A17_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 16.
Mux control via the A16_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 15.
Mux control via the A15_MODE bit in the EBSR (see Figure 4-2).
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IPD
DVDDEMIF
EM_A[14]
EM_A[13]
M1
L1
I/O/Z
I/O/Z
DVDDEMIF
DVDDEMIF
This pin is the EMIF external address pin 14.
This pin is the EMIF external address pin 13.
This pin is the EMIF external address pin 12. When interfacing with NAND Flash,
this pin also acts as Command Latch Enable (CLE).
EM_A[12]/(CLE)
EM_A[11]/(ALE)
K1
K2
I/O/Z
I/O/Z
DVDDEMIF
DVDDEMIF
This pin is the EMIF external address pin 11. When interfacing with NAND Flash,
this pin also acts as Address Latch Enable (ALE).
EM_A[10]
EM_A[9]
EM_A[8]
EM_A[7]
EM_A[6]
EM_A[5]
EM_A[4]
EM_A[3]
EM_A[2]
EM_A[1]
EM_A[0]
L2
J2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
This pin is the EMIF external address pin 10.
This pin is the EMIF external address pin 9.
This pin is the EMIF external address pin 8.
This pin is the EMIF external address pin 7.
This pin is the EMIF external address pin 6.
This pin is the EMIF external address pin 5.
This pin is the EMIF external address pin 4.
This pin is the EMIF external address pin 3.
This pin is the EMIF external address pin 2.
This pin is the EMIF external address pin 1.
This pin is the EMIF external address pin 0.
J1
H2
F1
D1
C1
D2
E1
C2
B2
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-8. External Memory Interface (EMIF) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
J4
EM_D[15]
EM_D[14]
EM_D[13]
EM_D[12]
EM_D[11]
EM_D[10]
EM_D[9]
EM_D[8]
EM_D[7]
EM_D[6]
EM_D[5]
EM_D[4]
EM_D[3]
EM_D[2]
EM_D[1]
EM_D[0]
K3
K4
L3
C4
D3
F4
E3
H3
K5
M2
L4
I/O/Z
DVDDEMIF
EMIF 16-bit bi-directional bus.
D4
F3
E5
G3
EMIF chip select 5 output for use with asynchronous memories (i.e., NOR flash,
NAND flash, or SRAM).
EM_CS5
EM_CS4
EM_CS3
EM_CS2
A3
C3
M4
C5
O/Z
O/Z
O/Z
O/Z
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
EMIF chip select 4 output for use with asynchronous memories (i.e., NOR flash,
NAND flash, or SRAM).
EMIF NAND chip select 3 output for use with asynchronous memories (i.e., NOR
flash, NAND flash, or SRAM).
EMIF NAND chip select 2 output for use with asynchronous memories (i.e., NOR
flash, NAND flash, or SRAM).
EM_WE
EM_OE
H1
E4
B6
P1
B5
B1
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
EMIF asynchronous memory write enable output
EMIF asynchronous memory read enable output
EMIF asynchronous read/write output
EM_R/W
EM_DQM1
EM_DQM0
EM_BA[1]
EMIF asynchronous data write strobes and byte enables.
EMIF asynchronous bank address
16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device
address [23].
EM_BA[0]
A1
O/Z
DVDDEMIF
8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device
address [0].
EM_WAIT5
EM_WAIT4
EM_WAIT3
EM_WAIT2
H4
G1
K6
D5
I
I
I
I
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
EMIF wait state extension input 5 for EM_CS5
EMIF wait state extension input 4 for EM_CS4
EMIF wait state extension input 3 for EM_CS3
EMIF wait state extension input 2 for EM_CS2
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Table 3-9. Inter-Integrated Circuit (I2C) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
I2C
This pin is the I2C clock output. Per the I2C standard, an external pullup is required
on this pin.
SCL
SDA
B7
B8
I/O/Z
I/O/Z
DVDDIO
DVDDIO
This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup
is required on this pin.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
L9
Interface 0 (I2S0)
This pin is multiplexed between MMC0, I2S0, and GPIO.
For I2S, it is I2S0 transmit data output I2S0_DX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_D0/
I2S0_DX/
GP[2]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For I2S, it is I2S0 clock input/output I2S0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_CLK/
I2S0_CLK/
GP[0]
IPD
I/O/Z
L10
M10
M11
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For I2S, it is I2S0 receive data input I2S0_RX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_D1/
I2S0_RX/
GP[3]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_CMD/
I2S0_FS/
GP[1]
IPD
I/O/Z
For I2S, it is I2S0 frame synchronization input/output I2S0_FS.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
DVDDIO
Interface 1 (I2S1)
This pin is multiplexed between MMC1, I2S1, and GPIO.
For I2S, it is I2S1 transmit data output I2S1_DX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC1_D0/
I2S1_DX/
GP[8]
IPD
I/O/Z
M14
M13
M12
L14
DVDDIO
This pin is multiplexed between MMC1, I2S1, and GPIO.
For I2S, it is I2S1 clock input/output I2S1_CLK.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC1_CLK/
I2S1_CLK/
GP[6]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between MMC1, I2S1, and GPIO.
For I2S, it is I2S1 receive data input I2S1_RX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC1_D1/
I2S1_RX/
GP[9]
IPD
I/O/Z
DVDDIO
This pin is multiplexed betweenn MMC1, I2S2, and GPIO.
For I2S, it is I2S1 frame synchronization input/output I2S1_FS.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC1_CMD/
I2S1_FS/
GP[7]
IPD
I/O/Z
DVDDIO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
P12
N10
N11
P11
Interface 2 (I2S2)
This pin is multiplexed between I2S2, GPIO, and SPI.
For I2S, it is I2S2 transmit data output I2S2_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
I2S2_DX/
GP[27]/
SPI_TX
IPD
I/O/Z
DVDDIO
This pin is multiplexed between I2S2, GPIO, and SPI.
For I2S, it is I2S2 clock input/output I2S2_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
I2S2_CLK/
GP[18]/
SPI_CLK
IPD
I/O/Z
DVDDIO
This pin is multiplexed between I2S2, GPIO, and SPI.
For I2S, it is I2S2 receive data input I2S2_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
I2S2_RX/
GP[20]/
SPI_RX
IPD
I/O/Z
DVDDIO
This pin is multiplexed between I2S2 and GPIO.
I2S2_FS/
GP[19]/
SPI_CS0
IPD
I/O/Z
For I2S, it is I2S2 frame synchronization input/output I2S2_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
DVDDIO
Interface 3 (I2S3)
This pin is multiplexed between UART, GPIO, and I2S3.
For I2S, it is I2S3 transmit data output I2S3_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_TXD/
GP[31]/
I2S3_DX
IPD
I/O/Z
P14
N12
N13
P13
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
For I2S, it is I2S3 clock input/output I2S3_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_RTS/
GP[28]/
I2S3_CLK
IPD
I/O/Z
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
For I2S, it is I2S3 receive data input I2S3_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_RXD/
GP[30]/
I2S3_RX
IPD
I/O/Z
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
UART_CTS/
GP[29]/
I2S3_FS
IPD
I/O/Z
For I2S, it is I2S3 frame synchronization input/output I2S3_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
DVDDIO
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Table 3-11. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
P4
Serial Port Interface (SPI)
SPI_CS0
I/O/Z
I/O/Z
DVDDIO
For SPI, this pin is SPI chip select SPI_CS0.
This pin is multiplexed between I2S2, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
I2S2_FS/
GP[19]/
SPI_CS0
IPD
DVDDIO
P11
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
SPI_CS1
SPI_CS2
SPI_CS3
SPI_CLK
N4
P5
N5
N3
I/O/Z
I/O/Z
I/O/Z
O/Z
DVDDIO
DVDDIO
DVDDIO
DVDDIO
For SPI, this pin is SPI chip select SPI_CS1.
For SPI, this pin is SPI chip select SPI_CS2.
For SPI, this pin is SPI chip select SPI_CS3.
For SPI, this pin is clock output SPI_CLK.
This pin is multiplexed between I2S2, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
I2S2_CLK/
GP[18]/
SPI_CLK
IPD
DVDDIO
N10
N6
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
SPI_TX
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDDIO
For SPI, this pin is SPI transmit data output.
This pin is multiplexed between I2S2, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
I2S2_DX/
GP[27]/
SPI_TX
IPD
DVDDIO
P12
P6
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
SPI_RX
DVDDIO
For SPI this pin is SPI receive data input.
This pin is multiplexed between I2S2, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
I2S2_RX/
GP[20]/
SPI_RX
IPD
DVDDIO
N11
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-12. UART Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
N13
P14
P13
N12
UART
This pin is multiplexed between UART, GPIO, and I2S3.
When used by UART, it is the receive data input UART_RXD.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_RXD/
GP[30]/
I2S3_RX
IPD
I/O/Z
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
In UART mode, it is the transmit data output UART_TXD.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_TXD/
GP[31]/
I2S3_DX
IPD
I/O/Z
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
In UART mode, it is the clear to send input UART_CTS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_CTS/
GP[29]/
I2S3_FS
IPD
I/O/Z
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
In UART mode, it is the ready to send output UART_RTS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
UART_RTS/
GP[28]/
I2S3_CLK
IPD
I/O/Z
DVDDIO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-13. USB2.0 Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
USB 2.0
12-MHz crystal oscillator input.
USB_MXI
USB_MXO
USB_VDDOSC
G13
G14
G12
I
USB_VDDOSC
USB_VDDOSC
When the USB peripheral is not used, USB_MXI should be connected to ground
(VSS).
12-MHz crystal oscillator output.
O
S
When the USB peripheral is not used, USB_MXO should be left unconnected.
3.3-V power supply for USB oscillator.
see
Section 5.2,
ROC
When the USB peripheral is not used, USB_VDDOSC should be connected to ground
(VSS).
see
Section 5.2,
ROC
USB_VSSOSC
USB_VBUS
F11
J12
S
Ground for USB oscillator.
see
Section 5.2,
ROC
USB power detect. 5-V input that signifies that VBUS is connected.
When the USB peripheral is not used, the USB_VBUS signal should be connected
to ground (VSS).
A I/O
USB_DP
USB_DM
H14
J14
A I/O
A I/O
USB_VDDA3P3 USB bi-directional Data Differential signal pair [positive/negative].
When the USB peripheral is not used, the USB_DP and USB_DM signals should
USB_VDDA3P3
both be tied to ground (VSS).
External resistor connect. Reference current output. This must be connected via a
10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as
possible.
USB_R1
G9
A I/O
USB_VDDA3P3
When the USB peripheral is not used, the USB_R1 signal should be connected via
a 10-kΩ resistor to USB_VSSREF
.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-13. USB2.0 Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
When the USB peripheral is not used, the USB_VSSREF signal should be connected
directly to ground (Vss).
see
Section 5.2,
ROC
USB_VSSREF
G10
GND
Analog 3.3 V power supply for USB PHY.
see
Section 5.2,
ROC
USB_VDDA3P3
USB_VSSA3P3
USB_VDDA1P3
USB_VSSA1P3
USB_VDD1P3
H12
H11
H10
H9
S
GND
S
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
connected to ground (VSS).
see
Section 5.2,
ROC
Analog ground for USB PHY.
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
see
Section 5.2,
ROC
When the USB peripheral is not used, the USB_VDDA1P3 signal should be
connected to ground (VSS).
see
Section 5.2,
ROC
GND
S
Analog ground for USB PHY [For high speed sensitive analog circuits].
1.3-V digital core power supply for USB PHY.
see
Section 5.2,
ROC
J13
When the USB peripheral is not used, the USB_VDD1P3 signal should be connected
to ground (VSS).
see
Section 5.2,
ROC
USB_VSS1P3
USB_VDDPLL
USB_VSSPLL
H13
G8
GND
S
Digital core ground for USB phy.
see
Section 5.2,
ROC
3.3 V USB Analog PLL power supply.
When the USB peripheral is not used, the USB_VDDPLL signal should be connected
to ground (VSS).
see
Section 5.2,
ROC
G11
GND
USB Analog PLL ground.
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Table 3-14. MMC1/SD Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
M13
L14
MMC/SD
This pin is multiplexed between MMC1, I2S1, and GPIO.
For MMC/SD, this is the MMC1 data clock output MMC1_CLK.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC1_CLK/
I2S1_CLK/
GP[6]
IPD
DVDDIO
O
This pin is multiplexed between MMC1, I2S1, and GPIO.
MMC1_CMD/
I2S1_FS/
GP[7]
IPD
DVDDIO
For MMC/SD, this is the MMC1 command I/O output MMC1_CMD.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
O
MMC1_D3/
GP[11]
IPD
I/O/Z
L13
K14
DVDDIO
The MMC1_D3 and MMC1_D2 pins are multiplexed between MMC1 and GPIO.
The MMC1_D1 and MMC1_D0 pins are multiplexed between MMC1, I2S1, and
GPIO.
In MMC/SD mode, all these pins are the MMC1 nibble wide bi-directional data bus.
Mux control via the SP1MODE bits in the EBSR.
MMC1_D2/
GP[10]
IPD
I/O/Z
DVDDIO
MMC1_D1/
I2S1_RX/
GP[9]
IPD
I/O/Z
M12
M14
DVDDIO
The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1
register.
MMC1_D0/
I2S1_DX/
GP[8]
IPD
I/O/Z
DVDDIO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-15. MMC0/SD Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
L10
M11
MMC/SD
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_CLK/
I2S0_CLK/
GP[0]
IPD
DVDDIO
For MMC/SD, this is the MMC0 data clock output MMC0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
O
This pin is multiplexed between MMC0, I2S0, and GPIO.
MMC0_CMD/
I2S0_FS/
GP[1]
IPD
DVDDIO
For MMC/SD, this is the MMC0 command I/O output MMC0_CMD.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
O
MMC0_D3/
GP[5]
IPD
I/O/Z
L11
L12
DVDDIO
The MMC0_D3 and MMC0_D2 pins are multiplexed between MMC0 and GPIO.
The MMC0_D1 and MMC0_D0 pins are multiplexed between MMC0, I2S0, and
GPIO.
In MMC/SD mode, these pins are the MMC0 nibble wide bi-directional data bus.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D2/
GP[4]
IPD
I/O/Z
DVDDIO
MMC0_D1/
I2S0_RX/
GP[3]
IPD
I/O/Z
M10
L9
DVDDIO
The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1
register.
MMC0_D0/
I2S0_DX/
GP[2]
IPD
I/O/Z
DVDDIO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-16. GPIO Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
General-Purpose Input/Output
External Flag Output. XF is used for signalling other processors in multiprocessor
configurations or XF can be used as a fast general-purpose output pin.
–
O/Z
XF is set high by the BSET XF instruction and XF is set low by the BCLR XF
instruction or by writing to bit 13 of the ST1_55 register. At reset, the XF pin will be
high. For more information on the ST1_55 register, see the TMS320C55x 3.0 CPU
Reference Guide (literature number: SWPU073).
XF
M8
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For GPIO, it is general-purpose input/output pin 0 (GP[0]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_CLK/
I2S0_CLK/
GP[0]
IPD
I/O/Z
L10
M11
L9
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For GPIO, it is general-purpose input/output pin 1 (GP[1]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_CMD/
I2S0_FS/
GP[1]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For GPIO, it is general-purpose input/output pin 2 (GP[2]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_D0/
I2S0_DX/
GP[2]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between MMC0, I2S0, and GPIO.
For GPIO, it is general-purpose input/output pin 3 (GP[3]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
MMC0_D1/
I2S0_RX/
GP[3]
IPD
I/O/Z
M10
L12
DVDDIO
This pin is multiplexed between MMC0 and GPIO.
MMC0_D2/
GP[4]
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 4 (GP[4]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
DVDDIO
This pin is multiplexed between MMC0 and GPIO.
MMC0_D3/
GP[5]
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 5 (GP[5]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
L11
M13
L14
DVDDIO
This pin is multiplexed between I2S1 and GPIO.
For GPIO, it is general-purpose input/output pin 6 (GP[6]).
Mux control via the SP1MODE bits in the EBSR.
I2S1_CLK/
GP[6]
IPD
I/O/Z
DVDDIO
This pin is multiplexed between I2S1 and GPIO.
I2S1_FS/
GP[7]
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 7 (GP[7]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
DVDDIO
This pin is multiplexed between I2S1 and GPIO.
I2S1_DX/
GP[8]
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 8 (GP[8]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
M14
M12
DVDDIO
This pin is multiplexed between I2S1 and GPIO.
I2S1_RX/
GP[9]
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 9 (GP[9]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
DVDDIO
For GPIO, it is general-purpose input/output pin 10 (GP[10]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
IPD
I/O/Z
GP[10]
GP[11]
GP[12]
K14
L13
P7
DVDDIO
For GPIO, it is general-purpose input/output pin 11 (GP[11]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
IPD
I/O/Z
DVDDIO
For GPIO, it is general-purpose input/output pin 12 (GP[12]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
DVDDIO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-16. GPIO Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
For GPIO, it is general-purpose input/output pin 13 (GP[13]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
N7
DVDDIO
For GPIO, it is general-purpose input/output pin 14 (GP[14]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
N8
P9
DVDDIO
For GPIO, it is general-purpose input/output pin 15 (GP[15]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
DVDDIO
For GPIO, it is general-purpose input/output pin 16 (GP[16]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
N9
DVDDIO
For GPIO, it is general-purpose input/output pin 17 (GP[17]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
P10
N10
DVDDIO
I2S2_CLK/
GP[18]/
SPI_CLK
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
IPD
I/O/Z
DVDDIO
This pin is multiplexed between I2S2 and GPIO.
I2S2_FS/
GP[19]/
SPI_CS0
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
P11
N11
N1
DVDDIO
This pin is multiplexed between I2S2, GPIOand SPI.
I2S2_RX/
GP[20]/
SPI_RX
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
DVDDIO
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 21 (GP[21]).
Mux control via the A15_MODE bit in the EBSR.
IPD
I/O/Z
EM_A[15]/GP[21]
EM_A[16]/GP[22]
EM_A[17]/GP[23]
EM_A[18]/GP[24]
EM_A[19]/GP[25]
EM_A[20]/GP[26]
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 22 (GP[22]).
Mux control via the A16_MODE bit in the EBSR.
IPD
I/O/Z
E2
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 23 (GP[23]).
Mux control via the A17_MODE bit in the EBSR.
IPD
I/O/Z
F2
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 24 (GP[24]).
Mux control via the A18_MODE bit in the EBSR.
IPD
I/O/Z
G2
G4
J3
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 25 (GP[25]).
Mux control via the A19_MODE bit in the EBSR.
IPD
I/O/Z
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 26 (GP[26]).
Mux control via the A20_MODE bit in the EBSR.
IPD
I/O/Z
DVDDIO
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
This pin is multiplexed between I2S2, GPIO, and SPI.
I2S2_DX/
GP[27]/
SPI_TX
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 27 (GP[27]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
P12
N12
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
UART_RTS/
GP[28]/
I2S3_CLK
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 28 (GP[28]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
DVDDIO
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Table 3-16. GPIO Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
This pin is multiplexed between UART, GPIO, and I2S3.
UART_CTS/
GP[29]/
I2S3_FS
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 29 (GP[29]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
P13
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
UART_RXD/
GP[30]/
I2S3_RX
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 30 (GP[30]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
N13
P14
DVDDIO
This pin is multiplexed between UART, GPIO, and I2S3.
UART_TXD/
GP[31]/
I2S3_DX
IPD
I/O/Z
For GPIO, it is general-purpose input/output pin 31 (GP[31]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
DVDDIO
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Table 3-17. Regulators and Power Management Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
Regulators
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be connected to an ~ 1.0 µF decoupling
capacitor to VSS. For more detailed information, see Section 6.3.3, Power-Supply
Decoupling.
DSP_LDOO
DSP_LDOI
E10
F14
S
S
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be connected to the same supply as the
ANA_LDOI pin (B12).
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be tied to ground (VSS). For future device
family pin compatibility, board designs should have this pin layout with a zero-Ω
resistor to ANA_LDOI and a zero-Ω resistor to ground. For VC5504, only the zero-Ω
resistor to ground should be populated.
–
DSP_LDO_EN
DSP_LDO_V
D12
D13
I
ANA_LDOI
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be connected to the same supply as the
ANA_LDOI pin (B12). For future device family pin compatibility, board designs
should have this pin layout with a zero-Ω resistor to ANA_LDOI and a zero-Ω
resistor to ground. For VC5504, only the zero-Ω resistor to ANA_LDOI should be
populated.
–
I
ANA_LDOI
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be left unconnected.
USB_LDOO
USB_LDOI
F12
F13
S
S
[Not supported on this device. Reserved for compatibility with future devices].
For proper device operation, this pin must be connected to the same supply as the
ANA_LDOI pin (B12).
Analog LDO output. This output provides up to 3 mA of current regulated to 1.3 V
(see the ISD parameter in Section 5.3, Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Temperature).
For proper device operation, this pin must be connected to an ~ 1.0 µF decoupling
capacitor to VSS. For more detailed information, see Section 6.3.3, Power-Supply
Decoupling.
ANA_LDOO
A12
S
Analog LDO input. This input pin must be connected to a power supply with a
voltage range of 1.8 V to 3.6 V. It supplies power for the ANA_LDO, the bandgap
reference generator circuits, and is the I/O supply for some input pins.
ANA_LDOI
BG_CAP
B12
B13
S
Bandgap reference filter signal. For proper device operation, this pin needs to be
bypassed with a 0.1 µF capacitor to analog ground (VSSA_ANA).
This external capacitor provides filtering for stable reference voltages & currents
generated by the bandgap circuit. The bandgap produces the references for use by
the System PLL and POR circuits.
O
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-18. Reserved and No Connects Terminal Functions
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
Reserved
Reserved. For proper device operation, this pin must be tied directly to VSS.
–
RSV0
C12
I
ANA_LDOI
RSV1
RSV2
J10
J11
PWR
PWR
Reserved. For proper device operation, this pin must be tied directly to CVDD
.
.
Reserved. For proper device operation, this pin must be tied directly to CVDD
–
RSV3
RSV4
RSV5
D14
C14
C13
I
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
.
.
.
ANA_LDOI
–
I
ANA_LDOI
–
I
ANA_LDOI
RSV6
RSV7
D10
A11
B11
C11
B3
I/O
I/O
VDDA_ANA
VDDA_ANA
VDDA_ANA
VDDA_ANA
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
DVDDEMIF
Reserved. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reseverd. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reseverd. (Leave unconnected, do not connect to power or ground).
Reserved. (Leave unconnected, do not connect to power or ground).
Reseverd. (Leave unconnected, do not connect to power or ground).
RSV8
I/O
RSV9
I/O
RSV10
RSV11
RSV12
RSV13
RSV14
RSV15
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
A4
M3
N2
A6
B4
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-19. Supply Voltage Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
SUPPLY VOLTAGES
F6
H8
J6
1.05-V Digital Core supply voltage (60 MHz)
1.3-V Digital Core supply voltage (100 MHz)
CVDD
PWR
K10
L5
F7
K7
K12
N14
P3
DVDDIO
PWR
1.8-V, 2.5-V, 2.8-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
P8
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 3-19. Supply Voltage Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) OTHER(2)(3)
DESCRIPTION
NO.
A2
A5
E6
F5
G5
H5
H7
J5
DVDDEMIF
PWR
1.8-V, 2.5-V, 2.8-V, or 3.3-V EMIF I/O power supply
P2
C8
CVDDRTC
DVDDRTC
VDDA_ANA
PWR
PWR
PWR
1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply.
1.8-V, 2.5-V, 2.8-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP
pins.
F8
A10
1.3-V supply for power management
Table 3-20. Ground Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
NAME
NO.
A13
A14
D7
D11
E9
E11
E12
E13
E14
F9
VSS
F10
G6
GND
Ground pins
G7
H6
J7
J8
J9
K8
K9
K11
K13
C9
VSS_RTC
VSSA_ANA
VSSA_ANA
GND
GND
Ground pin for RTC digital core and RTC oscillator power supply.
Ground pins for power management (POR & Bandgap circuits)
B10
B14
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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3.6 Device Support
3.6.1 Development Support
TI offers an extensive line of development tools for the TMS320C55x DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320C55x fixed-point DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): Version 3.3 or later
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™ Version 5.32.03 or later), which provides the
basic run-time target software needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the TMS320C55x DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
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Fixed-Point Digital Signal Processor
SPRS609A–JUNE 2009–REVISED JULY 2009
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3.6.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g.,TMS320VC5504ZCH). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCH), and the temperature range (for example, "Blank" is the commercial
temperature range).
Figure 3-3 provides a legend for reading the complete device name for any DSP platform member.
TMX 320 VC 5505
(
)
ZCH
A
PREFIX
TEMPERATURE RANGE
TMX = Experimental device
TMS = Qualified device
Blank = 0 ° C to 70° C, Commercial Temperature
A = –40° C to 85° C, Industrial Temperature
DEVICE FAMILY
PACKAGE TYPE
320 = TMS320™ DSP family
ZCH = 196-pin plastic BGA, with Pb-Free
soldered balls [Green]
TECHNOLOGY
VC = Dual-supply CMOS
SILICON REVISION
Revision 1.4
DEVICE
C55x™ DSP: 5505
5504
Figure 3-3. TMS320VC5504 Device Nomenclature
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3.7 Documentation Support
3.7.1 Related Documentation From Texas Instruments
The following documents describe the TMS320VC5504 DSP. Copies of these documents are available on
the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the VC5504 DSP, related peripherals, and other technical
collateral, is available in the C55x DSP product folder at: www.ti.com/c5000.
SWPU073 TMS320C55x 3.0 CPU Reference Guide. This manual describes the architecture, registers,
and operation of the fixed-point TMS320C55x digital signal processor (DSP) CPU.
SPRU652
TMS320C55x DSP CPU Programmer’s Reference Supplement. This document describes
functional exceptions to the CPU behavior.
SPRUFO0 TMS320VC5505/5504 Digital Signal Processor (DSP) Universal Serial Bus 2.0 (USB)
User's Guide. This document describes the universal serial bus 2.0 (USB) in the
TMS320VC5505/5504 Digital Signal Processor (DSP). The USB controller supports data
throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB
devices.
SPRUFO1 TMS320VC5505/5504 Digital Signal Processor (DSP) Inter-Integrated Circuit (I2C)
Peripheral User's Guide. This document describes the inter-integrated circuit (I2C)
peripheral in the TMS320VC5505/5504 Digital Signal Processor (DSP) device. The I2C
peripheral provides an interface between the device and other devices compliant with Phillips
Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an
I2C-bus. This document assumes the reader is familiar with the I2C-bus specification.
SPRUFO2 TMS320VC5505/5504 Digital Signal Processor (DSP) Timer/Watchdog Timer User's
Guide. This document provides an overview of the three 32-bit timers in the
TMS320VC5505/5504 Digital Signal Processor (DSP) device. The 32-bit timers of the device
are software programmable timers that can be configured as general-purpose (GP) timers.
Timer 2 can be configured as a GP, a Watchdog (WD), or both simultaneously.
SPRUFO3 TMS320VC5505/5504 Digital Signal Processor (DSP) Serial Peripheral Interface (SPI)
User's Guide. This document describes the serial peripheral interface (SPI) in the
TMS320VC5505/5504 Digital Signal Processor (DSP) device. The SPI is a high-speed
synchronous serial input/output port that allows a serial bit stream of programmed length (1
to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI
supports multi-chip operation of up to four SPI slave devices. The SPI can operate as a
master device only.
SPRUFO4 TMS320VC5505/5504 Digital Signal Processor (DSP) General-Purpose Input/Output
(GPIO) User's Guide. This document describes the general-purpose input/output (GPIO) on
the TMS320VC5505/5504 digital signal processor (DSP). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs. When
configured as an input, you can detect the state of an internal register. When configured as
an output you can write to an internal register to control the state driven on the output pin.
SPRUFO5 TMS320VC5505/5504 Digital Signal Processor (DSP) Universal Asynchronous
Receiver/Transmitter (UART) User's Guide. This document describes the universal
asynchronous receiver/transmitter (UART) peripheral in the TMS320VC5505/5504 Digital
Signal Processor (DSP) device. The UART performs serial-to-parallel conversions on data
received from a peripheral device and parallel-to-serial conversion on data received from the
CPU.
SPRUFO6 TMS320VC5505/5504 Digital Signal Processor (DSP) Multimedia Card (MMC)/Secure
Digital (SD) Card Controller User's Guide. This document describes the Multimedia Card
(MMC)/Secure Digital (SD) Card Controller on the TMS320VC5505/5504 Digital Signal
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Processor (DSP) device. The multimedia card (MMC)/secure digital (SD) card is used in a
number of applications to provide removable data storage. The MMC/SD card controller
provides an interface to external MMC and SD cards.
SPRUF07 TMS320VC5505/5504 Digital Signal Processor (DSP) Real-Time Clock (RTC) User's
Guide. This document describes the operation of the Real-Time Clock (RTC) module in the
TMS320VC5505/5504 Digital Signal Processor (DSP) device. The RTC also has the
capability to wake-up the power management and apply power to the rest of the device
through an alarm, periodic interrupt, or external WAKEUP signal.
SPRUFO8 TMS320VC5505/5504 Digital Signal Processor (DSP) External Memory Interface (EMIF)
User's Guide. This document describes the operation of the external memory interface
(EMIF) in the TMS320VC5505/5504 Digital Signal Processor (DSP) device. The purpose of
the EMIF is to provide a means to connect to a variety of external devices.
SPRUFO9 TMS320VC5505/5504 Digital Signal Processor (DSP) Direct Memory Access (DMA)
Controller User's Guide. This document describes the features and operation of the DMA
controller that is available on the TMS320VC5505/5504 Digital Signal Processor (DSP)
device. The DMA controller is used to move data among internal memory, external memory,
and peripherals without intervention from the CPU and in the background of CPU operation.
SPRUGL6 TMS320VC5504 Digital Signal Processor (DSP) System User's Guide. This document
describes various aspects of the TMS320VC5505/5504 digital signal processor (DSP)
including: system memory, device clocking options and operation of the DSP clock
generator, power management features, interrupts, and system control.
SPRUFP4 TMS320VC5505/5504 Digital Signal Processor (DSP) Inter-IC Sound (I2S) Bus User's
Guide. This document describes the features and operation of Inter-IC Sound (I2S) Bus in
the TMS320VC5505/5504 Digital Signal Processor (DSP) device. This peripheral allows
serial transfer of full duplex streaming data, usually streaming audio, between DSP and an
external I2S peripheral device such as an audio codec.
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4 Device Configuration
4.1 System Registers
The system registers are used to configure the device and monitor its status. Brief descriptions of the
various system registers are shown in Table 4-1. For more details on these registers and their bit field
descriptions, see the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).
Table 4-1. Idle Control, Status, and System Registers
CPU WORD
ADDRESS
ACRONYM
COMMENTS
Register Description
0001h
0002h
1C00h
ICR
ISTR
EBSR
Idle Control Register
Idle Status Register
see Section 4.6.1 of this
document.
External Bus Selection Register
1C02h
1C03h
1C04h
1C05h
1C14h
1C16h
1C17h
1C18h
1C19h
1C1Ah
1C1Bh
1C1Ch
1C1Dh
1C26h
1C28h
1C2Eh
1C30h
1C31h
1C32h
1C33h
1C36h
1C37h
1C38h
1C39h
1C3Ah
7004h
PCGCR1
PCGCR2
Peripheral Clock Gating Control Register 1
Peripheral Clock Gating Control Register 2
Peripheral Software Reset Counter Register
Peripheral Reset Control Register
Timer Interrupt Aggregation Flag Register
Output Drive Strength Control Register
Pull-Down Inhibit Register 1
PSRCR
PRCR
TIAFR
ODSCR
PDINHIBR1
PDINHIBR2
PDINHIBR3
DMA0CESR1
DMA0CESR2
DMA1CESR1
DMA1CESR2
ECDR
Pull-Down Inhibit Register 2
Pull-Down Inhibit Register 3
DMA0 Channel Event Source Register 1
DMA0 Channel Event Source Register 2
DMA1 Channel Event Source Register 1
DMA1 Channel Event Source Register 2
EMIF Clock Divider Register
RAMSLPMDCNTLR1
RAMSLPMDCNTLR2
DMAIFR
RAM Sleep Mode Control Register 1
RAM Sleep Mode Control Register 2
DMA Interrupt Flag Register
DMAIER
DMA Interrupt Enable Register
USBSCR
USB System Control Register
ESCR
EMIF System Control Register
DMA2CESR1
DMA2CESR2
DMA3CESR1
DMA3CESR2
CLKSTOP
DMA2 Channel Event Source Register 1
DMA2 Channel Event Source Register 2
DMA3 Channel Event Source Register 1
DMA3 Channel Event Source Register 2
Peripheral Clock Stop Request/Acknowledge Register
USB LDO Control Register
USBLDOCNTL
[Not Supported]
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4.2 Power Considerations
The VC5504 provides several means of managing power consumption.
To minimize power consumption, the VC5504 divides its circuits into eight main isolated supply domains:
•
•
•
•
•
•
•
•
•
ANA_LDOI (LDO and Bandgap Power Supply)
Analog POR and PLL (VDDA_ANA and VDDA_PLL
RTC (CVDD_RTC
Digital Core (CVDD
USB Core (USB_ VDD1P3 and USB_VDDA1P3
USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL
EMIF I/O (DVDDEMIF
RTC I/O (DVDDRTC
Rest of the I/O (DVDDIO
)
)
)
)
)
)
)
)
4.2.1 LDO Configuration
The VC5504 includes one Low-Dropout Regulator (LDO) which can be used to regulate the supply of the
analog PLL.
4.2.1.1 Analog LDO
The ANA_LDOI pin (B12) provides the power to the Analog LDO, the bandgap reference generator, and
some I/O input pins and can range from 1.8 V to 3.6 V. The Bandgap provides accurate voltage and
current references to the POR, LDO, and PLL; therefore, for proper device operation, power must always
be applied to the ANA_LDOI pin. ANA_LDOO is regulated to 1.3 V and can optionally be used to provide
up to 3 mA to the VDDA_ANA (Power Management Voltage Supervisor VDD power input) and VDDA_PLL
(System PLL power input).
4.3 Clock Considerations
The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the 32.768-KHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the
state of the CLK_SEL pin. The CLK_SEL pins is required to be statically tied high or low and cannot
change dynamically after reset.
In addition, the DSP requires a reference clock for USB applications. The USB reference clock is
generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI
and USB_MXO pins.
The USB reference clock is not required if the USB peripheral is not being used. To completely disable the
USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The
USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground.
The RTC oscillator generates a clock when a 32.768-KHz crystal is connected to the RTC_XI and
RTC_XO pins. The 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP.
However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers
(I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management
register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator,
connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 6.4, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.
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4.3.1 Clock Configurations After Device Reset
After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the
system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the
Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN
pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. While
the bootloader tries to boot from the USB (currently not supported), the clock generator will be
programmed to output approximately 36 MHz.
4.3.1.1 Device Clock Frequency
After the boot process is complete, the user is allowed to re-program the system clock generator to bring
the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not).
The user must adhere to various clock requirements when programming the system clock generator. For
more information, see Section 6.5, Clock PLLs.
Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process.
However, this feature must not be used to change the output frequency of the system clock generator
during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling
time. The bootloader register modification feature must not modify the Timer0 registers.
4.3.1.2 Peripheral Clock State
The clock and reset state of each of peripheral is controlled through a set of system registers. The
peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable
peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control
register (PRCR) are used to assert and deassert peripheral reset signals. For more detailed information
on these system registers, see the TMS320VC5505 DSP System User's Guide (literature number
SPRUFP0).
At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP
boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to
determine if it can boot from that peripheral. At that time, the individual peripheral clocks will be enabled
for the query and then disabled again when the bootloader is finished with the peripheral. By the time the
bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR,
except the CPU domain, will be idled.
4.3.1.3 USB Oscillator Control
The USB oscillator is controlled through the USB system control register (USBSCR). To enable the
oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the
USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization
time is 100 µs, typically with a 10 ms maximum (Note: the startup time is highly dependent on the ESR
and capacitive load on the crystal).
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4.4 Boot Sequence
The boot sequence is a process by which the device's memory is loaded with program and data sections
from external flash memory, and by which some of the device's internal registers are programmed with
predetermined values. The boot sequence is started automatically after each device reset. For more
details on device reset, see Section 6.7, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. At reset, the device cycles through different boot modes until a
valid boot signature is found (see Figure 4-1). For more information on the boot modes supported, see
Section 4.4.1, Boot Modes.
The VC5504 Bootloader follows the following steps as shown in Figure 4-1
1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP/MC is 0 by default, so
0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode.
2. Set CLKOUT slew rate control to slow slew rate.
3. Idle all peripherals, MPORT and HWA.
4. If CLK_SEL = 0, the Bootloader powers up the PLL and sets its output frequency to 12.288 MHz (with
a 375x multiplier using VP = 749, VS = 0, input divider disabled, output divide-by-2 enabled, and output
divider enabled with VO = 0). If CLK_SEL = 1, the Bootloader keeps the PLL bypassed.
5. Apply manufacturing trim to the bandgap references.
6. Disable CLKOUT.
7. Set Register Configuration, if present in boot image.
8. Test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
a. Check the first 2 bytes read from boot signature.
b. If the boot signature is not valid, go to step 9.
c. Attempt NOR boot, go to step 17.
9. Test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 8-bit access:
a. Check the first 2 bytes read from boot table for a boot signature match.
b. If the boot signature is not valid, go to step 10.
c. Attempt NAND boot, go to step 17.
10. Test for SPI EEPROM boot on SPI_CS[0] with 500-KHz clock rate and for Parallel Port Mode on
External bus Selection Register set to 5, then set to 6:
a. Check the first 2 bytes read from boot table for a boot signature match.
b. If the boot signature is not valid, go to step 11.
c. Attempt SPI EEPROM boot, go to step 17.
11. Test for I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.
a. Check the first 2 bytes read from boot table for a boot signature match.
b. If the boot signature is not valid, go to step 12.
c. Attempt I2C EEPROM boot, go to step 17.
12. Test for MMC/SD boot --- MMC/SD boot is not supported.
13. Set the PLL output to approximately 36 MHz. If CLK_SEL = 1, CLKIN multiplied by 3x, ; if CLK_SEL =
0, CLKIN is multiplied by 1125x.
14. Test for UART boot --- UART boot is not supported.
15. Test for USB boot --- USB boot is not supported.
16. If the boot signature is not valid, then go back to step 14 and repeat.
17. Enable TIMER0 to start counting 200 ms.
18. Ensure a minimum of 200 ms has elapsed since step 17 before proceeding to execute the bootloaded
code.
19. Jump to the entry point specified in the boot image.
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No
CLK SEL = 1
?
Setup PLL to
x375
Yes
Internal Configuration
Yes
NOR Boot
?
No
Yes
Yes
Yes
NAND Boot
?
No
16-bit SPI
EEPROM
Boot
?
No
Set Register
Configuration
I2C Boot
?
Copy Boot
Image Sections
to System
No
Memory
MMC/SD0 Boot
(Not Supported)
?
Start Timer0 to Count
200 ms
UART Boot
(Not Supported)
?
Has Timer0
Counter Expired
?
No
USB Boot
(Not Supported)
?
Yes
Jump to Stored
Execution Point
Figure 4-1. Bootloader Software Architecture
4.4.1 Boot Modes
The VC5504 DSP supports the following boot modes in the following device order: NOR Flash, NAND
Flash, 16-bit SPI EEPROM, and I2C EEPROM. The boot mode is determined by checking for a valid boot
signature on each supported boot device. The first boot device with a valid boot signature will be used to
load and execute the user code. If none of the supported boot devices have a valid boot signature, the
Bootloader goes into an endless loop checking the unsupported UART and USB boot modes and the
device must be reset to look for another valid boot image in the supported boot modes.
4.4.2 Boot Configuration
After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the
system clock to 12.288 MHz (multiply the 32.768-KHz RTC oscillator clock by 375). If CLK_SEL = 1, the
Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN
pin.
Note:
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•
•
When CLK_SEL =1, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz.
The on-chip Bootloader allows for DSP registers to be configured during the boot process. However,
this feature must not be used to change the output frequency of the system clock generator during the
boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The
bootloader register modification feature must not modify the Timer0 registers.
At hardware reset, all of the peripheral clocks are "off" to conserve power. After hardware reset, the DSP
boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to
determine if it can boot from that peripheral. At that time, the individual peripheral clocks will be enabled
for the query and then disabled again when the bootloader is finished with the peripheral. By the time the
bootloader releases control to the user code, all peripheral clocks will be "off" and all domains in the ICR,
except the CPU domain, will be idled.
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4.5 Configurations at Reset
Some device configurations are determined at reset. The following subsections give more details.
4.5.1 Device and Peripheral Configurations at Device Reset
Table 4-2 summarizes the device boot and configuration pins that are required to be statically tied high,
tied low, or left unconnected during device operation. For proper device operation, a device reset should
be initiated after changing any of these pin functions.
Table 4-2. Default Functions Affected by Device Configuration Pins
CONFIGURATION PINS
SIGNAL NO.
IPU/IPD
FUNCTIONAL DESCRIPTION
DSP_LDO_EN
D12
–
[Not supported on this device. Reserved for
compatibility with future devices]. For proper
device operation, this pin must be connected to
ground (VSS). For future device family pin
compatibility, board designs should have this pin
layout with a zero-Ω resistor to ANA_LDOI and a
zero-Ω resistor to ground. For VC5504, only the
zero-Ω resistor to ground should be populated.
DSP_LDO_V
D13
–
[Not supported on this device. Reserved for
compatibility with future devices]. For proper
device operation, this pin must be connected to
the same supply as the ANA_LDOI pin (B12). For
future device family pin compatibility, board
designs should have this pin layout with a zero-Ω
resistor to ANA_LDOI and a zero-Ω resistor to
ground. For VC5504, only the zero-Ω resistor to
ANA_LDOI should be populated.
CLK_SEL
C7
–
Clock input select.
0 = 32-KHz on-chip oscillator drives the RTC
timer and the DSP clock generator while CLKIN
is ignored.
1 = CLKIN drives the DSP clock generator and
the 32-KHz on-chip oscillator drives only the RTC
timer.
This pin is not allowed to change during device
operation; it must be tied high or low at the
board.
For proper device operation, external pullup/pulldown resistors may be required on these device
configuration pins. For discussion situations where external pullup/pulldown resistors are required, see
Section 4.8.1, Pullup/Pulldown Resistors.
This device also has RESERVED pins that need to be configured correctly for proper device operation
(statically tied high, tied low, or left unconnected at all times). For more details on these pins, see
Table 3-18, Reserved and No Connects Terminal Functions.
4.6 Configurations After Reset
The following sections provide details on configuring the device after reset. Multiplexed pin functions are
selected by software after reset. For more details on multiplexed pin function control, see Section 4.7,
Multiplexed Pin Configurations.
4.6.1 External Bus Selection Register (EBSR)
The External Bus Selection Register (EBSR) determines the mapping of the I2S2, I2S3, UART, SPI, and
GPIO signals to 21 signals of the external parallel port pins. It also determines the mapping of the I2S or
MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is located at port address
0x1C00. Once the bit fields of this register are changed, the routing of the signals takes place on the next
CPU clock cycle.
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Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15]
can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE = 1, the
EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin retains its EMIF
functionality.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register . After the external bus selection register
has been modified, you must reset the peripherals before using them through the Peripheral Software
Reset Counter Register.
After the boot process is complete, the external bus selection register must be modified only once, during
device configuration. Continuously switching the EBSR configuration is not supported.
15
14
12
11
10
9
8
Reserved
R-0
PPMODE
R/W-000
SP1MODE
R/W-00
SP0MODE
R/W-00
7
6
5
4
3
2
1
0
Reserved
R-0
Reserved
R-0
A20_MODE
R/W-0
A19_MODE
R/W-0
A18_MODE
R/W-0
A17_MODE
R/W-0
A16_MODE
R/W-0
A15_MODE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-2. External Bus Selection Register (EBSR) [1C00h]
Table 4-3. EBSR Register Bit Descriptions
BIT
NAME
RESERVED
DESCRIPTION
15
Reserved. Read-only, writes have no effect.
Parallel Port Mode Control Bits. These bits control the pin multiplexing of the SPI, UART, I2S2,
I2S3, and GP[31:27, 20:18] pins on the parallel port. For more details, see , SPI, UART, I2S2, I2S3,
and GP[31:27, 20:18] Pin Multiplexing.
000 = Mode 0
001 = Mode 1 (SPI, GPIO, UART, and I2S2). 7 signals of the SPI module, 6 GPIO signals, 4
signals of the UART module and 4 signals of the I2S2 module are routed to the 21 external signals
of the parallel port.
010 = Mode 2 (GPIO). 8 GPIO are routed to the 21 external signals of the parallel port.
011 = Mode 3 (SPI and I2S3). 4 signals of the SPI module and 4 signals of the I2S3 module are
routed to the 21 external signals of the parallel port.
14:12
PPMODE
100 = Mode 4 (I2S2 and UART). 4 siignals of the I2S2 module and 4 signals of the UART module
are routed to the 21 external signals of the parallel port.
101 = Mode 5 (SPI and UART). 4 signals of the SPI module and 4 signals of the UART module are
routed to the 21 external signals of the parallel port.
110 = Mode 6 (SPI, I2S2, I2S3, and GPIO). 7 signals of the SPI module, 4 signals of the I2S2
module, 4 signals of the I2S3 module, and 6 GPIO are routed to the 21 external signals of the
parallel port.
111 = Reserved.
Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the I2S1 and GPIO pins on
serial port 1. For more details, see Table 4-5, MMC1, I2S1, and GP[11:6] Pin Multiplexing.
00 = Mode 0 (). .
01 = Mode 1 (I2S1 and GP[11:10]). 4 signals of the I2S1 module and 2 GP[11:10] signals are
routed to the 6 external signals of the serial port 1.
11:10
SP1MODE
10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial
port 1.
11 = Reserved.
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Table 4-3. EBSR Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the MMC0, I2S0, and GPIO
pins on serial port 0. For more details, see Section 4.7.1.3, MMC0, I2S0, and GP[5:0] Pin
Multiplexing.
00 = Mode 0 (MMC/SD0). All 6 signals of the MMC/SD0 module are routed to the 6 external signals
of the serial port 0.
9:8
SP0MODE
01 = Mode 1 (I2S0 and GP[5:0]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to
the 6 external signals of the serial port 0.
10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial
port 0.
11 = Reserved.
7
6
RESERVED
RESERVED
Reserved. Read-only, writes have no effect.
Reserved. Read-only, writes have no effect.
A20 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 20 (EM_A[20]) and
general-purpose input/output pin 26 (GP[26]) pin functions.
0 = Pin function is EMIF address pin 20 (EM_A[20]).
5
4
3
A20_MODE
A19_MODE
A18_MODE
1 = Pin function is general-purpose input/output pin 26 (GP[26]).
A19 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 19 (EM_A[19]) and
general-purpose input/output pin 25 (GP[25]) pin functions.
0 = Pin function is EMIF address pin 19 (EM_A[19]).
1 = Pin function is general-purpose input/output pin 25 (GP[25]).
A18 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 18 (EM_A[18]) and
general-purpose input/output pin 24 (GP[24]) pin functions.
0 = Pin function is EMIF address pin 18 (EM_A[18]).
1 = Pin function is general-purpose input/output pin 24 (GP[24]).
A17 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 17 (EM_A[17]) and
general-purpose input/output pin 23 (GP[23]) pin functions. For more details, see Table 4-6,
EM_A[20:16] and GP[26:21] Pin Multiplexing.
0 = Pin function is EMIF address pin 17 (EM_A[17]).
1 = Pin function is general-purpose input/output pin 23 (GP[23]).
2
1
0
A17_MODE
A16_MODE
A15_MODE
A16 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 16 (EM_A[16]) and
general-purpose input/output pin 22 (GP[22]) pin functions. For more details, see Table 4-6,
EM_A[20:16] and GP[26:21] Pin Multiplexing.
0 = Pin function is EMIF address pin 16 (EM_A[16]).
1 = Pin function is general-purpose input/output pin 22 (GP[22]).
A15 Pin Mode Bit. This bit controls the pin mulitplexing of the EMIF address 15 (EM_A[15]) and
general-purpose input/output pin 21 (GP[21]) pin functions. For more details, see Table 4-6,
EM_A[20:16] and GP[26:21] Pin Multiplexing.
0 = Pin function is EMIF address pin 15 (EM_A[15]).
1 = Pin function is general-purpose input/output pin 21 (GP[21]).
4.6.2 EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space.
To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the
"high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the
BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access.
For more detailed information on the use of the BYTEMODE bits, see the EMIF and USB Byte Access
section in the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).
4.6.3 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
After hardware reset, all of the peripheral clocks are "off" to conserve power. Then, the DSP executes the
on-chip bootloader from ROM. As the bootloader executes, it selectively enables the clock of the
peripheral being queried for a valid boot. If a valid boot source is not found, the bootloader disables the
clock to that peripheral and moves on to the next peripheral in the boot order. After the boot process is
complete, the peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be
idled (this includes the MPORT and HWA). The user must enable the clocks to the peripherals and CPU
ports that are going to be used. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are
used to enable and disable the peripheral clocks.
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For more detailed information on PCGCR1 and PCGR2 as well as other clock management features of
the DSP, see the Clock Management section in the TMS320VC5505 DSP System User's Guide (literature
number SPRUFP0).
4.6.4 Pull-up/Pull-down Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and 1C19h,
respectively]
Each internal pullup and pulldown (IPU/IPD) resistor on the VC5504 DSP, except for the IPD on TRST,
can be individually controlled through the IPU/IPD registers (PDINHIBR1 [1C17h] , PDINHIBR2 [1C18h],
and PDINHIBR3 [1C19h]). To minimize power consumption, internal pullup or pulldown resistors should
be disabled in the presence of an external pullup or pulldown resistor or external driver. Section 4.8.1,
Pullup/Pulldown Resistors, describes other situations in which an pullup and pulldown resistors are
required.
For more detailed information on the actual bit fields, see the System Configuration and Control section in
the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).
4.6.5 Output Slew Rate Control Register (OSRCR) [1C16h]
To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF
and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the
device I/O pins to either fast or slow slew rate. The slew rate feature is implemented by staging/delaying
turn-on times of the parallel p-channel drive transistors and parallel n-channel drive transistors of the
output buffer. In the slow slew rate configuration, the delay is longer, but ultimately the same number of
parallel transistors are used to drive the output high or low. Thus, the drive strength is ultimately the same
strength. The slower slew rate control can be used for power savings and has the greatest effect at lower
VDD_IO voltages.
For more detailed information on the actual bit fields, see the System Configuration and Control section in
the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).
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4.7 Multiplexed Pin Configurations
The VC5504 DSP uses pin multiplexing to accommodate a larger number of peripheral functions in the
smallest possible package, providing the ultimate flexibility for end applications. The external bus selection
register (EBSR) controls all the pin multiplexing functions on the device.
4.7.1 Pin Multiplexing Details
This section discusses how to program the external bus selection register (EBSR) to select the desired
peripheral functions and pin muxing. See the individual pin mux sections for pin muxing details for a
specific muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the
peripherals that are affected.
4.7.1.1 SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing [EBSR.PPMODE Bits]
The SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE bit fields
in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see .
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Table 4-4. SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing
EBSR PPMODE BITS(2)
PDINHIBR3
PIN MUX
REGISTER
MODE 1
001
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
SIGNAL NAME
BIT FIELDS(1)
010
011
100
101
110
SPI_CLK
SPI_RX
SPI_TX
SPI_CLK
SPI_RX
–
–
–
–
SPI_CLK
SPI_RX
SPI_TX
GP[12]
–
–
–
–
SPI_TX
–
–
–
–
P2PD
P3PD
P4PD
P5PD
P6PD
P7PD
P8PD
P9PD
P10PD
P11PD
P12PD
P13PD
P14PD
P15PD
GP[12]
GP[12]
–
–
–
–
GP[13]
GP[13]
–
–
–
–
GP[13]
GP[14]
GP[14]
–
–
–
–
–
GP[14]
GP[15]
GP[15]
–
–
–
GP[15]
GP[16]
GP[16]
–
–
–
–
–
–
GP[16]
GP[17]
GP[17]
–
–
SPI_CLK
SPI_CS0
SPI_RX
SPI_TX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
–
GP[17]
I2S2_CLK/GP[18]/SPI_CLK
I2S2_FS/GP[19]/SPI_CS0
I2S2_RX/GP[20]/SPI_RX
I2S2_DX/GP[27]/SPI_TX
UART_RTS/GP[28]/I2S3_CLK
UART_CTS/GP[29]/I2S3_FS
UART_RXD/GP[30]/I2S3_RX
UART_TXD/GP[31]/I2S3_DX
SPI_CS0
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
GP[18]
GP[19]
GP[20]
GP[27]
GP[28]
GP[29]
GP[30]
GP[31]
–
SPI_CLK
SPI_CS0
SPI_RX
SPI_TX
I2S3_CLK
I2S3_FS
I2S3_RX
I2S3_DX
–
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
–
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
I2S3_CLK
I2S3_FS
I2S3_RX
I2S3_DX
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
SPI_CS1
–
–
–
–
SPI_CS2
–
–
–
–
SPI_CS3
–
–
–
–
(1) The pin mux signals names with PDINHIBR3 register bit field references can have the pulldown resistor enabled or disabled via this register.
(2) MODE0 is not supported on the VC5504 device.
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4.7.1.2 MMC1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
The MMC1, I2S1, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see .
Table 4-5. MMC1, I2S1, and GP[11:6] Pin Multiplexing
EBSR SP1MODE BITS
PDINHIBR1
PIN MUX
REGISTER
MODE 0
00
MODE 1
01
MODE 2
10
SIGNAL NAME
BIT FIELDS(1)
S10PD
S11PD
S12PD
S13PD
S14PD
S15PD
MMC1_CLK/I2S1_CLK/GP[6]
MMC1_CMD/I2S1_FS/GP[7]
MMC1_D0/I2S1_DX/GP[8]
MMC1_D1/I2S1_RX/GP[9]
MMC1_D2/GP[10]
MMC1_CLK
MMC1_CMD
MMC1_D0
MMC1_D1
MMC1_D2
MMC1_D3
I2S1_CLK
I2S1_FS
I2S1_DX
I2S1_RX
GP[10]
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
MMC1_D3/GP[11]
GP[11]
(1) The pin mux signals names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this
register.
4.7.1.3 MMC0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The MMC0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-6.
Table 4-6. MMC0, I2S0, and GP[5:0] Pin Multiplexing
EBSR SP0MODE BITS
PDINHIBR1
PIN MUX
REGISTER
MODE 0
00
MODE 1
01
MODE 2
10
SIGNAL NAME
BIT FIELDS(1)
S00PD
S01PD
S02PD
S03PD
S04PD
S05PD
MMC0_CLK/I2S0_CLK/GP[0]
MMC0_CMD/I2S0_FS/GP[1]
MMC0_D0/I2S0_DX/GP[2]
MMC0_D1/I2S0_RX/GP[3]
MMC0_D2/GP[4]
MMC0_CLK
MMC0_CMD
MMC0_D0
MMC0_D1
MMC0_D2
MMC0_D3
I2S0_CLK
I2S0_FS
I2S0_DX
I2S0_RX
GP[4]
GP[0]
GP[1]
GP[2]
GP[3]
GP[4]
GP[5]
MMC0_D3/GP[5]
GP[5]
(1) The pin mux signals names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this
register.
4.7.1.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE,
A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register
(EBSR) register. For more details on the actual pin functions, see Table 4-7.
Table 4-7. EM_A[20:16] and GP[26:21] Pin Multiplexing
Axx_MODE BIT
PIN MUX
SIGNAL NAME
0
1
EM_A[15]/GP[21]
EM_A[16]/GP[22]
EM_A[17]/GP[23]
EM_A[18]/GP[24]
EM_A[19]/GP[25]
EM_A[20]/GP[26]
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
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4.8 Debugging Considerations
4.8.1 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the VC5504 DSP always be at a valid logic level and
not floating. This may be achieved via pullup/pulldown resistors. The DSP features internal pullup (IPU)
and internal pulldown (IPD) resistors on many (all GPIO) pins to eliminate the need, unless otherwise
noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Configuration Pins: An external pullup/pulldown resistor is recommended to set the desired value/state
(see the configuration pins listed in Table 4-2, Default Functions Affected by Device Configuration
Pins). Note that some configuration pins must connected directly to ground or to a specific supply
voltage.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the configuration pins (listed in Table 4-2, Default Functions Affected by Device Configuration Pins), if
they are both routed out and 3-stated (not driven), it is strongly recommended that an external
pullup/pulldown resistor be implemented. In addition, applying external pullup/pulldown resistors on the
configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor
should be disabled through the Pull-up/Pull-down Inhibit Registers (PDINHIBR1/2/3) [1C17h, 1C18h, and
1C19h, respectively] to minimize power consumption.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown (IPU/IPD) resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the configuration pins
while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for
the VC5504 DSP, see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply
Voltage and Operating Temperature.
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For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table in this document.
For more detailed information on the Pull-up/Pull-down Inhibit Registers (PDINHIBR1/2/3), see the System
Configuration and Control section of the TMS320VC5505 DSP System User's Guide (literature number
SPRUFP0).
4.8.2 CLKOUT Pin
For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the
clock generator. The SRC bits of the CLKOUT Control Source Register (CCSSR) can be used to specify
the source for the CLKOUT pin.
Note: the bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register.
For more detailed information on the CLKOUT Control Source Register (CCSSR), see the System Clock
Generator section in the TMS320VC5505 DSP System User's Guide (literature number: SPRUFP0). For
more information on the ST3_55 CPU register, see the TMS320C55x 3.0 CPU Reference Guide (literature
number: SWPU073).
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)(1)
(2)
Supply voltage ranges:
Digital Core (CVDD, CVDDRTC, USB_VDD1P3
)
–0.5 V to 1.7 V
–0.5 V to 4.2 V
I/O, 1.8 V, 2.5 V, 2.8 V, 3.3 V (DVDDIO, DVDDEMIF
,
DVDDRTC) 3.3V USB supplies USB PHY (USB_VDDOSC
,
(2)
USB_VDDPLL, USB_VDDA3P3
)
ANA_LDOI
–0.5 V to 4.2 V
–0.5 V to 1.7 V
–0.5 V to 4.2 V
(2)
Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA
)
Input and Output voltage ranges:
VI I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC
or USB_VDDPLLor USB_VDDA3P3 as supply source
VO I/O, All pins with DVDDIO or DVDDEMIF or
USB_VDDOSCor USB_VDDPLLor USB_VDDA3P3 as supply
source
–0.5 V to 4.2 V
RTC_XI and RTC_XO
VO, BG_CAP
–0.5 V to 1.7 V
–0.5 V to 1.7 V
–0.5 V to 1.7 V
0°C to 70°C
ANA_LDOO
Operating case temperature ranges, Tc:
Storage temperature range, Tstg
Commercial Temperature (default)
Industrial Temperature
(default)
Commercial Temperature(3)
Industrial Temperature(3)
-40°C to 85°C
–65°C to 150°C
100, 000 POH
100, 000 POH
Device Operating Life
Power-On Hours (POH)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) For devices running with CVDD = 1.3 V @ 100 MHz for commercial temperature, the Device Operating Life Power-On Hours are 70, 000
POH of the total POH .
For devices running with CVDD = 1.3 V @ 100 MHz for industrial temperature, the Device Operating Life Power-On Hours are 17, 000
POH of the total POH.
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5.2 Recommended Operating Conditions
MIN
0.998
1.24
0.998
1.24
1.24
1.24
1.24
3.14
2.97
2.52
2.25
1.65
3.14
3.14
1.8
NOM
1.05
1.3
MAX UNIT
60 MHz
1.15
1.43
1.43
1.43
1.43
1.43
1.43
3.46
3.63
3.08
2.75
1.98
3.46
3.46
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CVDD
Supply voltage, Digital Core
100 MHz
32.768 KHz
CVDDRTC
Supply voltage, RTC and RTC OSC
Supply voltage, Digital USB
USB_VDD1P3
USB_VDDA1P3
VDDA_ANA
1.3
1.3
1.3
1.3
3.3
3.3
2.8
2.5
1.8
3.3
3.3
CVDD
Supply voltage, 1.3 V Analog USB
Supply voltage, 1.3 V Pwr Mgmt
Supply voltage, 1.3 V System PLL
Supply voltage, 3.3 V USB PLL
Supply voltage, I/O, 3.3 V
VDDA_PLL
USB_VDDPLL
DVDDIO
DVDDEMIF
DVDDRTC
Supply voltage, I/O, 2.8 V
Supply voltage, I/O, 2.5 V
DVDD
Supply voltage, I/O, 1.8 V
USB_VDDOSC
USB_VDDA3P3
ANA_LDOI
VSS
Supply voltage, I/O, 3.3 V USB OSC
Supply voltage, I/O, 3.3 V Analog USB PHY
Supply voltage, Analog Pwr Mgmt and LDO Input
Supply ground, Digital I/O
VSSRTC
Supply ground, RTC
USB_VSSOSC
USB_VSSPLL
USB_VSSA3P3
USB_VSSA1P3
USB_VSSREF
VSSA_PLL
Supply ground, USB OSC
Supply ground, USB PLL
Supply ground, 3.3 V Analog USB PHY
Supply ground, USB 1.3 V Analog USB PHY
Supply ground, USB Reference Current
Supply ground, System PLL
VSS
0
0
0
V
USB_VSS1P3
VSSA_ANA
Supply ground, 1.3 V Digital USB PHY
Supply ground, Pwr Mgmt
(1)
VIH
High-level input voltage, 3.3, 2.8, 2.5, 1.8 V I/O(2)
Low-level input voltage, 3.3, 2.8, 2.5, 1.8 V I/O(2)
Default
0.7 * DVDD
-0.3
DVDD + 0.3
0.3 * DVDD
V
V
(1)
VIL
0
70
85
°C
°C
(Commercial)
Tc
Operating case temperature
(Industrial)
-40
(1) DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 3.5, Terminal Functions.
(2) The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could polentially draw current when the device is powered
down. Dues to the fact that different voltage devices can be connected to I2C bus, the level of logic 0 (low) and logic 1 (high) are not
fixed and depends on the associated DVDD
.
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full speed: USB_DN and
USB_DP(2)
2.8
USB_VDDA3P3
V
High speed: USB_DN and
USB_DP(2)
VOH
360
0.8 * DVDD
0.0
440
mV
V
High-level output voltage, 3.3, 2.8,
2.5, 1.8 V I/O
IO = IOH
Full speed: USB_DN and
USB_DP(2)
0.3
10
V
High speed: USB_DN and
USB_DP(2)
–10
mV
V
VOL
Low-level output voltage, 3.3, 2.8,
2.5, 1.8V I/O
IO = IOL
0.2 * DVDD
0.4
Low-level output voltage, I2C
pins(3)
VDD > 2 V, IOL = 3 mA
0
V
DVDD = 3.3 V
DVDD = 2.5 V
DVDD = 1.8 V
162
141
122
1.3
mV
mV
mV
V
VHYS
Input hysteresis(4)
VLDO
ISD
ANA_LDOO voltage
1.24
3
1.43
+5
ANA_LDO shutdown current
ANA_LDOI = VMIN
mA
µA
µA
µA
µA
µA
µA
µA
µA
Input only pin, internal pulldown or pullup disabled
DVDD = 3.3 V with internal pullup enabled(6)
DVDD = 2.5 V with internal pullup enabled(6)
DVDD = 1.8 V with internal pullup enabled(6)
Input only pin, internal pulldown or pullup disabled
DVDD = 3.3 V with internal pulldown enabled(6)
DVDD = 2.5 V with internal pulldown enabled(6)
DVDD = 1.8 V with internal pulldown enabled(6)
-5
-59 to -161
-31 to -93
-14 to -44
Input current [DC] (except
WAKEUP, and I2C pins)
(5)
IILPU
-5
+5
+5
52 to 158
27 to 83
11 to 35
Input current [DC] (except
WAKEUP, and I2C pins
(5)
IIHPD
IIH/
VI = VSS to DVDD with internal pullups and pulldowns
disabled.
Input current [DC], ALL pins
High-level output current [DC]
-5
µA
IIL
All Pins (except EMIF, and CLKOUT pins)
-4
-6
-5
-6
-4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
DVDD = 3.3 V
EMIF pins
IOH
DVDD = 1.8 V
DVDD = 3.3 V
CLKOUT pin
DVDD = 1.8 V
All Pins (except USB, EMIF, and CLKOUT pins)
+4
+6
DVDD = 3.3 V
EMIF pins
IOL
Low-level output current [DC]
I/O Off-state output current
DVDD = 1.8 V
+5
DVDD = 3.3 V
CLKOUT pin
+6
DVDD = 1.8 V
+4
(7)
IOZ
All Pins (except USB)
-10
+10
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).
(3) VDD is the voltage to which the I2C bus pullup resistors are connected.
(4) Applies to all input pins except WAKEUP, I2C pins, and USB_MXI.
(5) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(6) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(7) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature
(Unless Otherwise Noted) (continued)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Active, CVDD = 1.3 V, DSP clock = 100 MHz
Room Temp (25 °C), 75% DMAC + 25% ADD
(typical sine wave data switching)
0.22
mW/MHz
Active, CVDD = 1.05 V, DSP clock = 60 MHz
Room Temp (25 °C) , 75% DMAC + 25% ADD
(typical data switching)
0.15
0.22
0.14
0.44
0.26
0.40
0.23
0.28
0.15
0.7
mW/MHz
mW/MHz
mW/MHz
mW
Active, CVDD = 1.3 V, DSP clock = 100 MHz
Room Temp (25 °C), 75% DMAC + 25% NOP
(typical sine wave data switching)
Active, CVDD = 1.05 V, DSP clock = 60 MHz
Room Temp (25 °C) , 75% DMAC + 25% NOP
(typical data switching)
Standby, CVDD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM and SARAM in active
mode
Core (CVDD) supply current
Standby, CVDD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM and SARAM in active
mode
ICDD
mW
Standby, CVDD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
mW
Standby, CVDD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
mW
Standby, CVDD = 1.3 V, Master clock disabled,
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
mW
Standby, CVDD = 1.05 V, Master clock disabled,
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
mW
VDDA_PLL = 1.37 V
Room Temp (25 °C), Phase detector = 170 kHz,
VCO = 120 MHz
Analog PLL (VDDA_PLL) supply
current
1.2
mA
CI
Input capacitance
Output capacitance
4
4
pF
pF
Co
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. 3.3-V Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1 1.8-V, 2.5-V, 2.8-V, and 3.3-V Signal Transition Levels
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 6-2. Rise and Fall Transition Time Voltage Reference Levels
6.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
6.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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6.3 Power Supplies
The VC5504 includes four core voltag-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and
several I/O supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3), as well as several
analog supplies (ANA_LDOI, VDDA_PLL, VDDA_ANA, and USB_VDDPLL). To ensure proper device operation, a
specific power-up sequence must be followed. Some TI power-supply devices include features that
facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features. For more
information regarding TI's power management products and suggested devices to power TI DSPs, visit
www.ti.com/processorpower.
6.3.1 Power-Supply Sequencing
The VC5504 includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and
several I/O supplies including—DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3
For proper device operation, the general power-up sequence requirements can be summarized as
ANA_LDOI and all core-level supplies must come up first, followed by the I/O level supplies. Specifically,
the power-up sequence requirement is:
1. Apply power to the ANA_LDOI, CVDDRTC, CVDD, USB_VDD1P3, USB_VDDA1P3, VDDA_ANA, and VDDA_PLL
.
Note: the Analog LDO output (ANA_LDOO) can be used to power the VDDA_ANA, and VDDA_PLL
supplies.
2. Apply power to I/Os: DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL
.
Core supplies must be powered before I/O supplies. If the I/O supplies are powered before the core
supply, the core signals controlling bi-directional I/Os are in an "undetermined state" and can set some of
the bi-directional I/Os to drive against an external device, causing bus contention. Therefore, the I/O
Supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) should not ramp
above 1.65 V before core supplies (CVDDRTC, CVDD, USB_VDD1P3, USB_VDDA1P3) reach 0.9 V.
If the USB subsystem is not used, the USB Core (USB_VDD1P3, USB_VDDA1P3) and USB PHY and I/O level
supplies (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) can be powered on and off anytime after this
sequence. When powering on these supplies, the USB PHY, USB oscillator, and USB PLL (USB_VDDOSC
USB_VDDA3P3, and USB_VDDPLL) should not ramp above 1.65 V before the USB Core (USB_VDD1P3
USB_VDDA1P3) reaches 0.9 V. When powering off these supplies, the USB Core (USB_VDD1P3
,
,
,
USB_VDDA1P3) should not drop below 0.9 V before the USB PHY, USB oscillator, and USB PLL
(USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL) drop below 1.65 V.
6.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the VC5504 device, the PC board should include separate power planes for core, I/O,
VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with
high-quality low-ESL/ESR capacitors.
6.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as
possible to the VC5504. These caps need to be no more than 1.25 cm maximum distance from the
VC5504 power pins to be effective. Physically smaller caps, such as 0402, are better but need to be
evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest
available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 10 µF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
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As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
On the VC5504 the recommended decoupling capacitance for the DSP core supplies should be 1 µF in
parallel with 0.01-µF capacitor per supply pin.
6.3.4 LDO Input Decoupling
The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.
6.3.5 LDO Output Decoupling
The LDO circuits implement a voltage feedback control system which has been designed to optimize gain
and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO
outputs. For proper device operation, the following external decoupling capacitors should be used:
•
•
•
ANA_LDOO– 1µF
DSP_LDOO – 1µF
USB_LDOO – none required
6.4 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
The VC5504 DSP includes two options to provide an external clock input to the system clock generator:
•
Use the on-chip real-time clock (RTC) oscillator with an external 32.768-kHz crystal connected to the
RTC_XI and RTC_XO pins.
•
Use an external 11.2896-, 12.0-, or 12.288-MHz LVCMOS clock input fed into the CLKIN pin that
operates at the same voltage as the DVDDIO supply (1.8-, 2.5-, 2.8-, or 3.3-V).
The CLK_SEL pin determines which input is used as the clock source for the system clock generator, For
more details, see Section 4.5.1, Device and Peripheral Configurations at Device Reset. The crystal for the
RTC oscillator is not required if CLKIN is used as the system reference clock; however, the RTC must still
be powered. The RTC registers starting at I/O address 1900h will not be accessible without an RTC clock.
This includes the RTC Power Management Register which provides control to the on-chip LDOs and
WAKEUP and RTC_CLKOUT pins. Section 6.4.1, Real-Time Clock (RTC) On-Chip Oscillator With
External Crystal provides more details on using the RTC on-chip oscillator with an external crystal.
Section 6.4.2, CLKIN Pin With LVCMOS-Compatible Clock Input provides details on using an external
LVCMOS-compatible clock input fed into the CLKIN pin.
Additionally, the USB requires a reference clock generated using a dedicated on-chip oscillator with a
12-MHz external crystal connected to the USB_MXI and USB_MXO pins. The USB reference clock is not
required if the USB peripheral is not being used. Section 6.4.3, USB On-Chip Oscillator With External
Crystal provides details on using the USB on-chip oscillator with an external crystal.
6.4.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
The on-chip oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and RTC_XO
pins, along with two load capacitors, as shown in Figure 6-3. The external crystal load capacitors must be
connected only to the RTC oscillator ground pin (VSSRTC). Do not connect to board ground (VSS). Position
the VSS lead on the board between RTC_XI and RTC_XO as a shield to reduce direct capacitance
between RTC_XI and RTC_XO leads on the board. The CVDDRTC pin can be connected to the same
power supply as CVDD , or may be connected to a different supply that meets the recommended operating
conditions (see Section 5.2), if desired.
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RTC_XI
RTC_XO
VSSRTC
CVDDRTC
VSS
CVDD
Crystal
32.768 kHz
C1
C2
0.998-1.43 V
1.05/1.3 V
Figure 6-3. 32.768-kHz RTC Oscillator
The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 6-1. The load capacitors, C1 and C2, are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (RTC_XI and RTC_XO) and to the VSSRTC pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
Table 6-1. Input Requirements for Crystal on the 32.768-kHz RTC Oscillator
PARAMETER
MIN
NOM
MAX
UNIT
Start-up time (from power up until oscillating at stable frequency of
32.768-kHz)(1)
0.2
2
sec
Oscillation frequency
ESR
32.768
kHz
kΩ
100
1.6
1.0
Maximum shunt capacitance
Maximum crystal drive
pF
µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
6.4.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
Note: If CLKIN is not used, the pin must be tied low.
A LVCMOS-compatible clock input of a frequency less than 24 MHz can be fed into the CLKIN pin for use
by the DSP system clock generator. The external connections are shown in Figure 6-4 and Figure 6-5.
The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with a
frequency of 11.2896-, 12.0-, or 12.288-MHz. These frequencies were selected to support boot mode
peripheral speeds of 500 KHz for SPI, 400 KHz for I2C, and 57600 baud for UART (UART is currently not
supported on this device). These clock frequencies are achieved by dividing the CLKIN value by 25 for
SPI, by 32 for I2C, and by 208 for UART. If a faster external clock is input, then these boot modes will run
at faster clock speeds. If the system design utilizes faster peripherals or these boot modes are not used,
CLKIN values higher than 12.288 MHz can be used. Note: the CLKIN pin operates at the same voltage as
the DVDDIO supply (1.8-, 2.5-, 2.8-, or 3.3-V).
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In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and
RTC_XO to ground (VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O
address 1900h will not be accessible. This includes the RTC Power Management Register which provides
control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: the RTC must still be powered
even if the RTC oscillator is disabled.
For more details on the RTC on-chip oscillator, see Section 6.4.1, Real-Time Clock (RTC) On-Chip
Oscillator With External Crystal.
RTC_XI
RTC_XO
VSSRTC
CVDDRTC
VSS
CVDD
CLKIN
Crystal
32.768 kHz
C1
C2
0.998-1.43 V
1.05/1.3 V
Figure 6-4. LVCMOS-Compatible Clock Input With RTC Oscillator Enabled
RTC_XI
CVDDRTC RTC_XO
VSS
VSSRTC
CVDD
CLKIN
0.998-1.43 V
1.05/1.3 V
Figure 6-5. LVCMOS-Compatible Clock Input With RTC Oscillator Disabled
6.4.3 USB On-Chip Oscillator With External Crystal (Optional)
When using the USB, the USB on-chip oscillator requires an external 12-MHz crystal connected across
the USB_MXI and USB_MXO pins, along with two load capacitors, as shown in Figure 6-6. The external
crystal load capacitors must be connected only to the USB oscillator ground pin (USB_VSSOSC). Do not
connect to board ground (VSS). The USB_VDDOSC pin can be connected to the same power supply as
USB_VDDA3P3
.
The USB on-chip oscillator can be permanently disabled, via tie-offs, if the USB peripheral is not being
used. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the
USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also
be connected to ground.
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USB_MXI
USB_MXO
USB_VSSOSC USB_VDDOSC
VSS
USB_VDDA3P3
Crystal
12 MHz
C1
C2
3.3 V
3.3 V
Figure 6-6. 12-MHz USB Oscillator
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The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 6-2. The load capacitors, C1 and C2 are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
Table 6-2. Input Requirements for Crystal on the 12-MHz USB Oscillator
PARAMETER
MIN
NOM
0.100
12
MAX
UNIT
Start-up time (from power up until oscillating at stable frequency of
12 MHz)(1)
10
ms
Oscillation frequency
MHz
Ω
ESR
100
±100
5
(2)Frequency stability
Maximum shunt capacitance
Maximum crystal drive
ppm
pF
330
µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
(2) If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.
6.5 Clock PLLs
The VC5504 DSP uses a software-programmable PLL to generate frequencies required by the CPU,
DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC
on-chip oscillator (as specified through the CLK_SEL pin). The PLL is controlled through the system clock
generator which is discussed in further detail in the TMS320VC5505 DSP System User's Guide (literature
number SPRUFP0).
6.5.1 PLL Device-Specific Information
There is a minimum and maximum operating frequency for CLKIN, PLLOUT, and the system clock
(SYSCLK). The system clock generator must be configured not to exceed any of these constraints
documented in this section (certain combinations of external clock inputs, internal dividers, and PLL
multiply ratios might not be supported). For these constraints see and the Clock Generator (Figure 4) of
the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).
The PLL has a lock time requirements that must be followed. The PLL lock time is the amount of time
needed for the PLL to complete its phase-locking sequence.
For details on the PLL initialization software sequence, see the TMS320VC5505 DSP System User's
Guide (literature number SPRUFP0).
6.5.2 Clock PLL Considerations With External Clock Sources
If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single
clean power supply should power both the VC5504 device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see
Section 6.5.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock
source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 6.5.3, Clock
PLL Electrical Data/Timing (Input and Output Clocks).
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6.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 6-3. Timing Requirements for CLKIN(1)(2)(3) (see Figure 6-7)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
88.577,
83.333,
or
88.577,
83.333,
or
Cycle time, external
clock driven on
CLKIN
1
tc(CLKIN)
16.67
10
ns
81.380
81.380
Pulse width, CLKIN
high
2
3
4
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
0.466 * tc(CLKIN)
0.466 * tc(CLKIN)
0.466 * tc(CLKIN)
0.466 * tc(CLKIN)
ns
ns
ns
Pulse width, CLKIN
low
Transition time,
CLKIN
0.34 * tc(CLKIN)
0.34 * tc(CLKIN)
(1) The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for
CPU operating frequency.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) For more details on the PLL multiplier factors, see the TMS320VC5505 DSP System User's Guide (Literature Number SPRUFP0).
1
4
1
2
CLKIN
3
4
Figure 6-7. CLKIN Timing
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Table 6-4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT(1)(2)
(see Figure 6-8)
CVDD = 1.05 V
CVDD = 1.3 V
NO
.
PARAMETER
UNIT
MIN
P
MAX
MIN
P
MAX
10 ns
1
2
3
4
5
tc(CLKOUT)
tw(CLKOUTH)
tw(CLKOUTL)
tt(CLKOUTR)
tt(CLKOUTF)
Cycle time, CLKOUT
16.67
9.163
9.163
5
Pulse duration, CLKOUT high
Pulse duration, CLKOUT low
Transition time (rise), CLKOUT(3)
Transition time (fall), CLKOUT(3)
7.497
7.497
4.5
4.5
5.5 ns
5.5 ns
5
5
ns
ns
5
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
(3) Transition time is measured with the slew rate set to FAST and DVDDIO = 1.65 V. (For more detailed information, see the Section 4.6.5,
Output Slew Rate Control Register (OSRCR) [1C16h].).
2
5
1
CLKOUT
3
4
Figure 6-8. CLKOUT Timing
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6.6 Direct Memory Access (DMA) Controller
The DMA controller is used to move data among internal memory, external memory, and peripherals
without intervention from the CPU and in the background of CPU operation.
The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four
DMA controllers are identical.
The DMA controller has the following features:
•
•
Operation that is independent of the CPU.
Four channels, which allow the DMA controller to keep track of the context of four independent block
transfers.
•
•
•
Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of
selected events.
An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the
programmed transfer.
A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by
independently turning off their input clocks.
For more details on the DMA controller, see the TMS320VC5505 DSP Direct Memory Access (DMA)
Controller User’s Guide (literature number SPRUFO9).
6.6.1 DMA Channel Synchronization Events
The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP
supports 20 separate synchronization events and each channel can be tied to separate sync events
independent of the other channels. Synchronization events are selected by programming the CHnEVT
field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2). The synchronization
events available to each DMA controller are shown in the TMS320VC5505 DSP System User's Guide
(literature number SPRUFP0).
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6.7 Reset
upports only one type of reset, device reset.
The VC5504 has two main types of reset: hardware reset and software reset.
Hardware reset is responsible for initializing all key states of the device. It occurs whenever the RESET
pin is asserted or when the internal power-on-reset (POR) circuit deasserts an internal signal called
POWERGOOD. VC5504 device's internal POR is a voltage comparator that monitors the DSP_LDOO pin
voltage and generates the internal POWERGOOD signal. POWERGOOD is asserted when the
DSP_LDOO voltage is above a minimum threshold voltage provided by the bandgap. On VC5504, the
voltage comparator circuit is present and active in the POR circuit. The RESET pin and the
POWERGOOD signal are internally combined with a logical AND gate to produce an (active low)
hardware reset (see Figure 6-9, Power-On Reset Timing Requirements and Figure 6-10, Reset Timing
Requirements).
There are two types of software reset: the CPU's software reset instruction and the software control of the
peripheral reset signals. For more information on the CPU's software reset instruction, see the
TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073). For more information on the
peripheral's software reset, see the PSRCR register in the TMS320VC5505 DSP System User's Guide
(literature number: SPRUFP0). In all documentation, all references to "reset" refer to hardware reset. Any
references to software reset will explicitly state software reset.
The RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC core. This
POR monitors the voltage of CVDD_RTC and resets the RTC registers when power is first applied to the
RTC core.
6.7.1 Power-On Reset (POR) Circuits
The VC5504 device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another
for the rest of the chip (MAIN POR).
6.7.1.1 RTC Power-On Reset (POR)
The RTC POR ensures that the flip-flops in the CVDD_RTC power domain have an initial state upon
powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC
time registers need to be initialized with the current time and date when power is first applied.
6.7.1.2 Main Power-On Reset (POR)
The VC5504 device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until
specific voltages have reached predetermined levels. The output of the POR circuit, POWERGOOD, is
held low until the following conditions are satisfied:
•
•
•
ANA_LDOI is powered and the bandgap is active for at least approximately 8 ms
VDD_ANA is powered for at least approximately 4 ms
DSP_LDOO is powered and above a threshold of approximately 900 mV (see Note:)
Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal
is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's
global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global
reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,
see Section 4.4, Boot Sequence.
Note: The DSP_LDO is not supported on VC5504 device, but it's output voltage is still monitored by the
MAIN POR and must reach, and remain, higher than the POR's threshold for the POWERGOOD signal to
be high. The DSP_LDOO pin must be left floating and be properly bypassed as specified in the
DSP_LDOO entry in Table 3-17, Regulators and Power Management Terminal Functions. By leaving this
pin floating, the VC5504's internal circuits provide the necessary voltage above the POR's threshold for
POWERGOOD.
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6.7.1.3 Reset Pin (RESET)
The VC5504 can receive an external reset signal on the RESET pin. As specified above in
Section 6.7.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD
signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the
hardware reset to the chip. The RESET pin may be tied high and the MAIN POR will provide the hardware
reset, or the RESET pin may be externally generated.
Once the internal hardware reset, from the MAIN POR and the RESET pin, goes high, the DSP clock
generator is enabled and the DSP starts the boot sequence. For more information on the boot sequence,
see Section 4.4, Boot Sequence.
6.7.2 Pin Behaviors at Reset
During normal operation, pins are controlled by the respective peripheral selected in the External Bus
Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins
changes and is categorized as follows:
•
High Group: EM_CS4, EM_CS5, EM_CS2, EM_CS3, EM_DQM0, EM_DQM1, EM_OE, EM_WE,
SPI_CS3, RSV15, RSV14, XF
•
•
Low Group: SPI_CLK, EM_R/W, MMC0_CLK/I2S0_CLK/GP[0], MMC1_CLK/I2S1_CLK/GP[6], RSV12
Z
Group: EM_D[15:0], EMU[1:0], SCL, SDA, SPI_RX, SPI_TX, I2S2_RX/GP[20]/SPI_RX,
I2S2_DX/GP[27]/SPI_TX, I2S2_RTS/GP[28]/I2S3_CLK, I2S2_CTS/GP[29]/I2S3_RS,
I2S2_RXD/GP[30]/I2S3_RX, I2S2_TXD/GP[31]/I2S3_DX, GP[12], GP[13], GP[14], GP[15], GP[16],
GP[17],
MMC0_CMD/I2S0_FS/GP[1],
MMC0_D2/GP[4],
I2S2_CLK/GP[18]/SPI_CLK,/I2S2_FS/GP[19]/SPI_CS0,
RTC_CLKOUT,
MMC0_D1/I2S0_RX/GP[3],
MMC1_CMD/I2S1_FS/GP[7],
MMC0_D0/I2S0_DX/GP[2],
MMC0_D3/GP[5],
MMC1_D0/I2S1_DX/GP[8],MMC1_D1/I2S1_RX/GP[9],MMC1_D2/GP[10], MMC1_D3/GP[11], TDO,
WAKEUP
•
•
•
•
•
CLKOUT Group: CLKOUT, SPI_CS1
SYNCH 0→1 Group: SPI_CS0, SPI_CS2, RSV13
SYNCH 1→0 Group: RSV10, RSV11
SYNCH X→1 Group: EM_BA[1:0]
SYNCH X→0 Group: EM_A[20:0]
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6.7.3 Reset Electrical Data/Timing
Table 6-5. Timing Requirements for Reset(1) (see Figure 6-9 and Figure 6-9)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
MAX
MIN
MAX
1
tw(RSTL)
Pulse duration, RESET low
3P
3P
ns
(1) (1)P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock
generator is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
POWERGOOD
(Internal)
RESET
POWERGOOD and RESET
(Internal)
LOW Group
HIGH Group
Z Group
SYNCH X→ 0
Group
SYNCH X→ 1
Group
SYNCH 0→ 1
Group
SYNCH 1→ 0
Group
CLKOUT
64k + 8 clocks if CLK_SEL = 1,
32 + 8 clocks if CLK_SEL = 0
Figure 6-9. Power-On Reset Timing Requirements
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POWERGOOD
(Internal)
RESET
POWERGOOD and RESET
(Internal)
LOW Group
HIGH Group
Z Group
SYNCH X → 0
Group
SYNCH X → 1
Group
SYNCH 0 → 1
Group
SYNCH 1 → 0
Group
CLKOUT
64k + 8 clocks if CLK_SEL = 1,
32 + 8 clocks if CLK_SEL = 0
Figure 6-10. Reset Timing Requirements
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6.8 Wake-up Events, Interrupts, and XF
The VC5504 device has two power down modes: IDLE3, and IDLE2. A wake-up event is required to exit a
power down mode. Depending on the power down mode, the WAKEUP pin, interrupt pins, and internal
interrupts can be used as wake-up events. For more information on the power down modes and their
wake-up events, see the Power Management section of the TMS320VC5504 DSP System User's Guide
(literature number SPRUGL6).
The VC5504 device has a number of interrupts to service the needs of its peripherals. The interrupts can
be selectively enabled or disabled. For more information on the device interrupts, see the Interrupts
section in the TMS320VC5504 DSP System User's Guide (literature number SPRUGL6).
6.8.1 Interrupts Electrical Data/Timing
Table 6-6. Timing Requirements for Interrupts(1) (see Figure 6-11)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
2P
MAX
1
2
tw(INTH)
tw(INTL)
Pulse duration, interrupt high CPU active
Pulse duration, interrupt low CPU active
ns
ns
2P
(1) P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, use P = 10 ns.
1
INTx
2
Figure 6-11. External Interrupt Timings
6.8.2 Wake-Up From IDLE Electrical Data/Timing
Table 6-7. Timing Requirements for Wake-Up From IDLE (see Figure 6-12)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
MAX
1
tw(WKPL)
Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1
10
ns
Table 6-8. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE(1)(2)
(see Figure 6-12)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
UNIT
MIN TYP
MAX
IDLE3 Mode with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL =
1
P
C
ns
ns
td(WKEVTH-
CKLGEN)
Delay time, wake-up event high to CPU
active
2
IDLE3 Mode with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL =
0
(1) P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, P = 10 ns.
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
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Table 6-8. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE
(see Figure 6-12) (continued)
CVDD = 1.05 V
CVDD = 1.3 V
MIN TYP
3P
NO.
PARAMETER
UNIT
MAX
IDLE2 Mode; INTx event
ns
2
CLKOUT
WAKEUP
INTx
1
A. INT[1:0] can only be used as a wake-up event for IDLE3 and IDLE2 modes.
B. RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.
C. Any unmasked interrupt can be used to exit the IDLE2 mode.
D. CLKOUT reflects either the CPU clock, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock
Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 6-12. Wake-Up From IDLE Timings (A)(B)(C)
6.8.3 XF Electrical Data/Timing
Table 6-9. Switching Characteristics Over Recommended Operating Conditions For XF(1)(2)
(see Figure 6-13)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
Delay time, CLKOUT high to XF high
UNIT
MIN
MAX
10.2 ns
1
td(XF)
0
(1) P = 1/SYSCLK clock frequency in ns. For example, when running parts at 100 MHz, P = 10 ns.
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
CLKOUT(A)
1
XF
A. CLKOUT reflects either the CPU clock, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock
Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 6-13. XF Timings
6.9 External Memory Interface (EMIF)
VC5505 supports several memory and external device interfaces, including: NOR Flash, NAND Flash, and
SRAM.
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The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 4 chip selects,
along with memory control signals.
The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External
Bus Selection Register (EBSR). For more detail on the pin muxing, see the Section 4.6.1, External Bus
Selection Register (EBSR). For more information on the VC5505 EMIF, see the TMS320VC5505 DSP
External Memory Interface (EMIF) User's Guide (literature number SPRUFO8).
6.9.1 EMIF Asynchronous Memory Support
The EMIF supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address
lines and four external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIF
(EM_CS[5:2]).
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes
6.9.2 EMIF Peripheral Register Description(s)
Table 6-10 shows the EMIF registers.
For more detailed information on the EMIF and its registers, see the TMS320VC5505 External Memory
Interface (EMIF) User's Guide (literature number SPRUFO8).
Table 6-10. External Memory Interface (EMIF) Peripheral Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1000h
1001h
1004h
1005h
1010h
1011h
1014h
1015h
1018h
1019h
101Ch
101Dh
1040h
1044h
REV
Revision Register
Status Register
STATUS
AWCCR1
AWCCR2
ACS2CR1
ACS2CR2
ACS3CR1
ACS3CR2
ACS4CR1
ACS4CR2
ACS5CR1
ACS5CR2
EIRR
Asynchronous Wait Cycle Configuration Register 1
Asynchronous Wait Cycle Configuration Register 2
Asynchronous CS2 Configuration Register 1
Asynchronous CS2 Configuration Register 2
Asynchronous CS3 Configuration Register 1
Asynchronous CS3 Configuration Register 2
Asynchronous CS4 Configuration Register 1
Asynchronous CS4 Configuration Register 2
Asynchronous CS5 Configuration Register 1
Asynchronous CS5 Configuration Register 2
EMIF Interrupt Raw Register
EIMR
EMIF Interrupt Mask Register
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
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Table 6-10. External Memory Interface (EMIF) Peripheral Registers (continued)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1048h
104Ch
1060h
1064h
1065h
1068h
1069h
1070h
1071h
1074h
1075h
1078h
1079h
107Ch
107Dh
10BCh
10C0h
10C1h
10C4h
10C5h
10C8h
10C9h
10CCh
10CDh
10D0h
10D1h
10D4h
10D5h
10D8h
10D9h
10DCh
10DDh
EIMSR
EIMCR
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
NAND Flash Control Register
NANDFCR
NANDFSR1
NAND Flash Status Register 1
NANDFSR2
NAND Flash Status Register 2
PGMODECTRL1
PGMODECTRL2
NCS2ECC1
Page Mode Control Register 1
Page Mode Control Register 2
NAND Flash CS2 1-Bit ECC Register 1
NAND Flash CS2 1-Bit ECC Register 2
NAND Flash CS3 1-Bit ECC Register 1
NAND Flash CS3 1-Bit ECC Register 2
NAND Flash CS4 1-Bit ECC Register 1
NAND Flash CS4 1-Bit ECC Register 2
NAND Flash CS5 1-Bit ECC Register 1
NAND Flash CS5 1-Bit ECC Register 2
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NCS2ECC2
NCS3ECC1
NCS3ECC2
NCS4ECC1
NCS4ECC2
NCS5ECC1
NCS5ECC2
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NAND4BITECC5
NAND4BITECC6
NAND4BITECC7
NAND4BITECC8
NANDERRADD1
NANDERRADD2
NANDERRADD3
NANDERRADD4
NANDERRVAL1
NANDERRVAL2
NANDERRVAL3
NANDERRVAL4
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Register 5
NAND Flash 4-Bit ECC Register 6
NAND Flash 4-Bit ECC Register 7
NAND Flash 4-Bit ECC Register 8
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Address Register 3
NAND Flash 4-Bit ECC Error Address Register 4
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
NAND Flash 4-Bit ECC Error Value Register 3
NAND Flash 4-Bit ECC Error Value Register 4
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6.9.3 EMIF Electrical Data/Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.8/2.5/1.8 V
Table 6-11. Timing Requirements for EMIF Asynchronous Memory(1) (see Figure 6-14, Figure 6-16, and
Figure 6-17)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
UNIT
MIN NOM MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
14.5
0
ns
ns
ns
14 tsu(EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(2)
4E + 9
WRITES
26 tsu(EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(2)
4E + 9
ns
(1) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of
the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-12. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory(1)(2) (see Figure 6-15 and
Figure 6-17)(3)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
PARAMETER
UNIT
MIN
READS and WRITES
NOM
MAX
1
td(TURNAROUND)
Turn around time
(TA)*E - 9
(TA)*E
(TA)*E + 9
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 9
(RS+RST+RH)*E
(RS+RST+RH)*E + 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E - 9
(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 9
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low width (EW = 0)
(RS)*E-9
(RS)*E
(RS)*E+9
+9
tsu(EMCEL-EMOEL)
-9
0
(RH)*E - 9
(RH)*E
(RH)*E + 9
+9
th(EMOEH-EMCEH)
-9
(RS)*E-9
0
(RS)*E
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E+9
(RH)*E+9
(RS)*E+9
(RH)*E+9
(RST)*E+9
(RST+(EWC*16))*E+9
4E+9
(RH)*E-9
(RH)*E
(RS)*E-9
(RS)*E
(RH)*E-9
(RH)*E
(RST)*E-9
(RST)*E
10
11
tw(EMOEL)
EM_OE active low width (EW = 1)
(RST+(EWC*16))*E-9
4E-9
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E-9
(WS+WST+WH)*E
(WS+WST+WH)*E+9
ns
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E -
9
(WS+WST+WH+(EWC*16))*E +
9
(WS+WST+WH+(EWC*16))*E
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS)*E - 9
-9
(WS)*E
0
(WS)*E + 9
+9
ns
ns
ns
ns
ns
ns
ns
ns
16
17
tsu(EMCSL-EMWEL)
(WH)*E-9
-9
(WH)*E
0
(WH)*E+9
+9
th(EMWEH-EMCSH)
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E-9
(WH)*E-9
(WS)*E-9
(WH)*E-9
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E+9
(WH)*E+9
(WS)*E+9
(WH)*E+9
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles.
These parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers. For more information, see the TMS320VC5505
External Memory Interface (EMIF) User's Guide (literature number SPRUFO8).
(2) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For
example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.
(3) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is
specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. For more information, see the TMS320VC5505 Asynchronous External Memory Interface
(EMIF) User's Guide (literature number SPRUFO8).
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Table 6-12. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (see Figure 6-15 and
Figure 6-17) (continued)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
PARAMETER
UNIT
MIN
NOM
MAX
EM_WE active low width (EW = 0)
(WST)*E-9
(WST)*E
(WST)*E+9
ns
ns
ns
ns
ns
22
tw(EMWEL)
EM_WE active low width (EW = 1)
(WST+(EWC*16))*E-9
3E-9
(WST+(EWC*16))*E
(WST+(EWC*16))*E+9
4E+9
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
4E
(WS)*E
(WH)*E
(WS)*E-9
(WS)*E+9
(WH)*E-9
(WH)*E+9
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6.9.4 EMIF Electrical Data/Timing CVDD = 1.3 V, DVDDEMIF = 3.3/2.8/2.5/1.8 V
Table 6-13. Timing Requirements for EMIF Asynchronous Memory(1) (see Figure 6-14, Figure 6-16, and
Figure 6-17)
CVDD = 1.3 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
UNIT
MIN NOM MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
11
0
ns
ns
ns
14 tsu(EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(2)
4E + 5
WRITES
26 tsu(EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(2)
4E + 5
ns
(1) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of
the EMIF Status register (0x1001h). For example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-14. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory(1)(2)(3) (see Figure 6-14,
Figure 6-16, and Figure 6-17)
CVDD = 1.3 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
PARAMETER
UNIT
MIN
READS and WRITES
NOM
MAX
1
td(TURNAROUND)
Turn around time
(TA)*E - 5
(TA)*E
(TA)*E + 5
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 5
(RS+RST+RH)*E
(RS+RST+RH)*E + 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E - 5
(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 5
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low width (EW = 0)
(RS)*E-5
(RS)*E
(RS)*E+5
+5
tsu(EMCSL-EMOEL)
-5
0
(RH)*E - 5
(RH)*E
(RH)*E + 5
+5
th(EMOEH-EMCSH)
-5
(RS)*E-5
0
(RS)*E
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E+5
(RH)*E+5
(RS)*E+5
(RH)*E+5
(RST)*E+5
(RST+(EWC*16))*E+5
4E+5
(RH)*E-5
(RH)*E
(RS)*E-5
(RS)*E
(RH)*E-5
(RH)*E
(RST)*E-5
(RST)*E
10
11
tw(EMOEL)
EM_OE active low width (EW = 1)
(RST+(EWC*16))*E-5
4E-5
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E-5
(WS+WST+WH)*E
(WS+WST+WH)*E+5
ns
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E -
5
(WS+WST+WH+(EWC*16))*E +
5
(WS+WST+WH+(EWC*16))*E
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS)*E - 5
-5
(WS)*E
0
(WS)*E + 5
+5
ns
ns
ns
ns
ns
ns
ns
ns
16
17
tsu(EMCSL-EMWEL)
(WH)*E-5
-5
(WH)*E
0
(WH)*E+5
+5
th(EMWEH-EMCSH)
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E-5
(WH)*E-5
(WS)*E-5
(WH)*E-5
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E+5
(WH)*E+5
(WS)*E+5
(WH)*E+5
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles.
These parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers. For more information, see the TMS320VC5505
External Memory Interface (EMIF) User's Guide (literature number SPRUFO8).
(2) E = SYSCLK period in ns, if EMIF is set for "full rate" or E = SYSCLK/2 period in ns, if EMIF is set for "half rate" as defined by bit 14 of the EMIF Status register (0x1001h). For
example, when EMIF is set to full rate and SYSCLK is selected and set to 100 MHz, E = 10 ns.
(3) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is
specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. For more information, see the TMS320VC5505 Asynchronous External Memory Interface
(EMIF) User's Guide (literature number SPRUFO8).
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Table 6-14. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory (see Figure 6-14,
Figure 6-16, and Figure 6-17) (continued)
CVDD = 1.3 V
DVDDEMIF = 3.3/2.8/2.5/1.8 V
NO.
PARAMETER
UNIT
MIN
NOM
MAX
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
(WST)*E-5
(WST)*E
(WST)*E+5
ns
ns
ns
ns
ns
22
tw(EMWEL)
(WST+(EWC*16))*E-5
(WST+(EWC*16))*E
(WST+(EWC*16))*E+5
4E+5
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
3E-5
(WS)*E-5
(WH)*E-5
4E
(WS)*E
(WH)*E
(WS)*E+5
(WH)*E+5
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3
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
4
8
5
9
7
6
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 6-14. Asynchronous Memory Read Timing for EMIF
15
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
16
18
20
17
19
21
22
EM_WE
25
24
EM_D[15:0]
EM_OE
Figure 6-15. Asynchronous Memory Write Timing for EMIF
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SETUP
STROBE
Extended Due to EM_WAITx
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
14
11
EM_OE
2
2
EM_WAITx
Asserted
Deasserted
Figure 6-16. EM_WAITx Read Timing Requirements
SETUP
STROBE
Extended Due to EM_WAITx
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
28
25
EM_WE
2
Asserted
2
EM_WAITx
Deasserted
Figure 6-17. EM_WAITx Write Timing Requirements
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6.10 Multimedia Card/Secure Digital (MMC/SD)
The VC5504 includes two MMC/SD controllers which are compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V2.0, and Secure Digital Input Output (SDIO) V3.3 specifications. The
MMC/SD card controller supports these industry standards and assumes the reader is familiar with these
standards.
Each VC5504 MMC/SD Controller has the following features:
•
•
•
•
Multimedia Card/Secure Digital (MMC/SD) protocol support
Programmable clock frequency
512 bit Read/Write FIFO to lower system overhead
Slave DMA transfer capability
The MMC/SD card controller transfers data between the CPU and DMA controller on one side and
MMC/SD card on the other side. The CPU and DMA controller can read/write the data in the card by
accessing the registers in the MMC/SD controller.
The MMC/SD controller on this device, does not support the SPI mode of operation.
For more detailed information, see the TMS320VC5505 DSP Multimedia Card (MMC)/Secure Digital (SD)
Card Controller User's Guide (literature number SPRUFO6).
6.10.1 MMC/SD Peripheral Register Description(s)
Table 6-15 shows the MMC/SD registers. The MMC/SD0 registers start at address 0x3A00.
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Table 6-15. MMC/SD0 Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
3A00h
3A04h
3A08h
3A0Ch
3A10h
3A14h
3A18h
3A1Ch
3A20h
3A24h
3A28h
3A29h
3A2Ch
3A2Dh
3A30h
3A34h
3A38h
3A39h
3A3Ch
3A3Dh
3A40h
3A41h
3A44h
3A45h
3A48h
3A50h
3A64h – 3A70h
3A74h
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive 1 Register
MMC Data Receive 2 Register
MMC Data Transmit 1 Register
MMC Data Transmit 2 Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR1
MMCDRR2
MMCDXR1
MMCDXR2
MMCCMD
MMCARGHL
MMCRSP0
MMCRSP1
MMCRSP2
MMCRSP3
MMCRSP4
MMCRSP5
MMCRSP6
MMCRSP7
MMCDRSP
MMCCIDX
–
MMC Argument Register
MMC Response Register 0
MMC Response Register 1
MMC Response Register 2
MMC Response Register 3
MMC Response Register 4
MMC Response Register 5
MMC Response Register 6
MMC Response Register 7
MMC Data Response Register
MMC Command Index Register
Reserved
MMCFIFOCTL
MMC FIFO Control Register
(1) For more information on MMC/SD0 and its registers, see the TMS320VC5505 DSP Multimedia Card (MMC)/Secure Digital (SD) User's
Guide (literature number SPRUFO6).
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Table 6-16. MMC/SD1 Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
3B00h
3B04h
3B08h
3B0Ch
3B10h
3B14h
3B18h
3B1Ch
3B20h
3B24h
3B28h
3B29h
3B2Ch
3B2Dh
3B30h
3B34h
3B38h
3B39h
3B3Ch
3B3Dh
3B40h
3B41h
3B44h
3B45h
3B48h
3B50h
3B74h
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive 1 Register
MMC Data Receive 2 Register
MMC Data Transmit 1 Register
MMC Data Transmit 2 Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR1
MMCDRR2
MMCDXR1
MMCDXR2
MMCCMD
MMCARGHL
MMCRSP0
MMCRSP1
MMCRSP2
MMCRSP3
MMCRSP4
MMCRSP5
MMCRSP6
MMCRSP7
MMCDRSP
MMCCIDX
MMCFIFOCTL
MMC Argument Register
MMC Response Register 0
MMC Response Register 1
MMC Response Register 2
MMC Response Register 3
MMC Response Register 4
MMC Response Register 5
MMC Response Register 6
MMC Response Register 7
MMC Data Response Register
MMC Command Index Register
MMC FIFO Control Register
(1) For more information on MMC/SD1 and its registers, see the TMS320VC5505 DSP Multimedia Card (MMC)/Secure Digital (SD) User's
Guide (literature number SPRUFO6).
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6.10.2 MMC/SD Electrical Data/Timing
Table 6-17. Timing Requirements for MMC/SD (see Figure 6-18 and Figure 6-21)
CVDD = 1.3 V CVDD = 1.05 V
FAST MODE STD MODE
NO.
UNIT
MIN
3
MAX
MIN
3
MAX
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, MMCx_CMD data input valid before MMCx_CLK high
Hold time, MMCx_CMD data input valid after MMCx_CLK high
Setup time, MMC_Dx data input valid before MMCx_CLK high
Hold time, MMC_Dx data input valid after MMCx_CLK high
ns
ns
ns
ns
3
3
3
3
3
3
Table 6-18. Switching Characteristics Over Recommended Operating Conditions for MMC Output(1) (see
Figure 6-18 and Figure 6-21)
CVDD = 1.3 V CVDD = 1.05 V
NO.
PARAMETER
FAST MODE
STD MODE
UNIT
MIN
0
MAX
50(2)
400
MIN
0
MAX
25(2) MHz
7
8
9
f(CLK)
Operating frequency, MMCx_CLK
Identfication mode frequency, MMCx_CLK
Pulse width, MMCx_CLK low
Pulse width, MMCx_CLK high
Rise time, MMCx_CLK
f(CLK_ID)
tw(CLKL)
0
0
400 kHz
7
10
10
ns
ns
10 tw(CLKH)
11 tr(CLK)
12 tf(CLK)
7
3
3
10
10
ns
ns
ns
ns
ns
ns
Fall time, MMCx_CLK
13 td(MDCLKL-CMDIV) Delay time, MMCx_CLK low to MMC_CMD data output invalid
-4
-4
-4
-4
14 td(MDCLKL-CMDV)
15 td(MDCLKL-DATIV)
16 td(MDCLKL-DATV)
Delay time, MMCx_CLK low to MMC_CMD data output valid
Delay time, MMCx_CLK low to MMC_Dx data output invalid
Delay time, MMCx_CLK low to MMC_Dx data output valid
4
4
5
5
(1) For MMC/SD, the parametric values are measured at DVDDIO = 3.3 V or 2.75 V.
(2) Use this value or SYS_CLK/2 whichever is smaller.
7
9
10
MMCx_CLK
13
14
VALID
MMCx_CMD
Figure 6-18. MMC/SD Host Command Write Timing
9
10
7
MMCx_CLK
MMCx_Dx
4
4
3
3
Start
D0
D1
Dx
End
Figure 6-19. MMC/SD Card Response Timing
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9
10
7
MMCx_CLK
1
2
START
XMIT
MMCx_CMD
Valid
Valid
Valid
END
Figure 6-20. MMC/SD Host Write Timing
7
9
10
MMCx_CLK
MMCx_DAT
16
15
VALID
Figure 6-21. MMC/SD Data Write Timing
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6.11 Real-Time Clock (RTC)
The VC5504 includes a Real-Time Clock (RTC) with its own separated power supply and isolation circuits.
The separate supply and isolation circuits allow the RTC to run while the rest of the VC5504 device (Core
and I/O) is powered off. All RTC registers are preserved (except for RTC Control and RTC Update
Registers) and the counter continues to operate when the device is powered off. The RTC also has the
capability to wakeup the device from idle states via alarms, periodic interrupts, or an external WAKEUP
input. Additionally, the RTC is able to output an alarm or periodic interrupt on the WAKEUP pin to cause
external power management to re-enable power to the DSP Core and I/O.
The VC5504 RTC provides the following features:
•
•
•
•
•
•
•
•
•
•
100-year calendar up to year 2099.
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Millisecond time correction
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
24-hour clock mode
Second, minute, hour, day, or week alarm interrupt
Periodic interrupt: every millisecond, second, minute, hour, or day
Alarm interrupt: precise time of day
Single interrupt to the DSP CPU
32.768-kHz crystal oscillator with frequency calibration
Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 6-19). Note
that any write to these registers will be synchronized to the RTC 32.768-KHz clock; thus, the CPU must
run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two
32.768-KHz clock cycles later. Furthermore, if the RTC Oscillator is disabled, no RTC register can be
written to.
The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain
when power is first applied to the CVDD_RTC power pin. The RTC flops are not reset by the device'sRESET
pin nor the digital core's POR (powergood signal) which monitors the DSP_LDOO voltage.
The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track
of when the DSP boots and whether the RTC time registers have already been initialized to the current
clock time or whether the software needs to go into a routine to prompt the user to set the time/date.
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6.11.1 RTC Peripheral Register Description(s)
Table 6-19 shows the RTC registers.
Table 6-19. Real-Time Clock (RTC) Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1900h
1901h
1904h
1905h
1908h
1909h
190Ch
190Dh
1910h
1911h
1914h
1915h
1918h
1919h
191Ch
191Dh
1920h
1921h
1924h
1928h
192Ch
1930h
1960h
1961h
1964h
1965h
RTCINTEN
RTCUPDATE
RTCMIL
RTC Interrupt Enable Register
RTC Update Register
Milliseconds Register
RTCMILA
Milliseconds Alarm Register
Seconds Register
RTCSEC
RTCSECA
RTCMIN
Seconds Alarm Register
Minutes Register
RTCMINA
RTCHOUR
RTCHOURA
RTCDAY
Minutes Alarm Register
Hours Register
Hours Alarm Register
Days Register
RTCDAYA
RTCMONTH
RTCMONTHA
RTCYEAR
RTCYEARA
RTCINTFL
RTCNOPWR
RTCINTREG
RTCDRIFT
RTCOSC
Days Alarm Register
Months Register
Months Alarm Register
Years Register
Years Alarm Register
RTC Interrupt Flag Register
RTC Lost Power Status Register
RTC Interrupt Register
RTC Compensation Register
RTC Oscillator Register
RTC Power Management Register
RTC LSW Scratch Register 1
RTC MSW Scratch Register 2
RTC LSW Scratch Register 3
RTC MSW Scratch Register 4
RTCPMGT
RTCSCR1
RTCSCR2
RTCSCR3
RTCSCR4
(1) For more information on RTC and its registers, see the TMS320VC5505 Real-Time Clock (RTC) User’s Guide (literature number
SPRUFO7).
6.11.1.1 RTC Electrical Data/Timing
For more detailed information on RTC electrical timings, specifically WAKEUP, see the Section 6.7.3,
Reset Electrical Data/Timing.
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6.12 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between VC5504 and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 2 to 8-bit data to/from the DSP through
the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
•
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)
Noise Filter to Remove Noise 50 ns or Less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller
One Interrupt that can be used by the CPU
Slew-Rate Limited Open-Drain Output Buffers
The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper
operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and
SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the
DSP clock divided by a programmable prescaler.
For more detailed information on the I2C peripheral, see the TMS320VC5505 Inter-Integrated Circuit (I2C)
Module User's Guide (literature number SPRUFP4).
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6.12.1 I2C Peripheral Register Description(s)
Table 6-20 shows the Inter-Integrated Circuit (I2C) registers.
Table 6-20. Inter-Integrated Circuit (I2C) Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1A00h
1A04h
1A08h
1A0Ch
1A10h
1A14h
1A18h
1A1Ch
1A20h
1A24h
1A28h
1A2Ch
1A30h
1A34h
1A38h
ICOAR
ICIMR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICPID1
ICPID2
I2C Peripheral Identification Register 1
I2C Peripheral Identification Register 2
(1) For more information on I2C and its registers, see the TMS320VC5505 Inter-Integrated Circuit (I2C) User’s Guide (literature number
SPRUFO1).
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6.12.2 I2C Electrical Data/Timing
Table 6-21. Timing Requirements for I2C Timings(1) (see Figure 6-22)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
STANDARD
MODE
UNIT
FAST MODE
MIN MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
0.6
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
4
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
0(3) 0.9(4)
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
µs
(6)
9
tr(SDA)
Rise time, SDA(5)
Rise time, SCL(5)
Fall time, SDA(5)
Fall time, SCL(5)
1000 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
ns
pF
(6)
(6)
(6)
10
11
12
13
14
15
tr(SCL)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
tf(SDA)
tf(SCL)
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
50
(6)
Cb
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their VIH cannot go above DVDDIO + 0.3 V).
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) The rise/fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb) and
external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
(6) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
SCL
6
8
14
4
13
5
10
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-22. I2C Receive Timings
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Table 6-22. Switching Characteristics for I2C Timings(1) (see Figure 6-23)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
STANDARD
MODE
UNIT
FAST MODE
MIN MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a repeated START
condition)
td(SCLH-SDAL)
4.7
0.6
0.6
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
td(SDAL-SCLL)
4
µs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SCLH)
tv(SCLL-SDAV)
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
250
0
0.9
µs
Pulse duration, SDA high between STOP and START
conditions
23
tw(SDAH)
4.7
1.3
µs
(1)
24
25
26
27
28
29
tr(SDA)
tr(SCL)
Rise time, SDA(2)
Rise time, SCL(2)
Fall time, SDA(2)
Fall time, SCL(2)
1000 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
pF
(1)
(1)
(1)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
tf(SDA)
tf(SCL)
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) The rise/fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb) and
external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
26
24
SDA
SCL
21
23
19
28
20
25
16
18
27
18
17
22
Stop
Start
Repeated
Start
Stop
Figure 6-23. I2C Transmit Timings
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6.13 Universal Asynchronous Receiver/Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from an external peripheral device and
parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.
The VC5504 has one UART peripheral with the following features:
•
•
Programmable baud rates (frequency pre-scale values from 1 to 65535)
Fully programmable serial interface characteristics:
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no PARITY bit generation and detection
1, 1.5, or 2 STOP bit generation
•
16-byte depth transmitter and receiver FIFOs:
–
–
The UART can be operated with or without the FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
•
•
•
•
•
DMA signaling capability for both received and transmitted data
CPU interrupt capability for both received and transmitted data
False START bit detection
Line break generation and detection
Internal diagnostic capabilities:
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Programmable autoflow control using CTS and RTS signals
6.13.1 UART Peripheral Register Description(s)
Table 6-23 shows the UART registers.
Table 6-23. UART Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1B00h
1B00h
1B02h
1B04h
1B04h
1B06h
1B08h
1B0Ah
1B0Ch
1B0Eh
1B10h
1B12h
1B18h
RBR
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
THR
IER
IIR
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
FCR
LCR
MCR
Modem Control Register
LSR
Line Status Register
MSR
SCR
Modem Status Register
Scratch Register
DLL
Divisor LSB Latch
DLH
Divisor MSB Latch
PWREMU_MGMT
Power and Emulation Management Register
(1) For more information on UART and its registers, see the TMS320VC5505 Universal Asynchronous Receiver/Transmitter (UART) User's
Guide (literature number SPRUFO5).
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6.13.2 UART Electrical Data/Timing [Receive/Transmit]
Table 6-24. Timing Requirements for UART Receive(1) (see Figure 6-24)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
U - 3
U - 3
MAX
MIN
U - 3
U - 3
MAX
U + 3
U + 3
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (UART_RXD) [15/30/100 pF]
Pulse duration, receive start bit [15/30/100 pF]
U + 3
U + 3
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-25. Switching Characteristics Over Recommended Operating Conditions for UART Transmit(1)
(see Figure 6-24)
CVDD = 1.05 V
MIN MAX
CVDD = 1.3 V
MIN MAX
NO.
PARAMETER
UNIT
1
2
3
f(baud)
Maximum programmable bit rate
3.75
U + 3
U + 3
6.25 MHz
Pulse duration, transmit data bit (UART_TXD) [15/30/100
pF]
tw(UTXDB)
tw(UTXSB)
U - 3
U - 3
U - 3
U - 3
U + 3
U + 3
ns
ns
Pulse duration, transmit start bit [15/30/100 pF]
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UART_TXD
Data Bits
5
4
Start
Bit
UART_RXD
Data Bits
Figure 6-24. UART Transmit/Receive Timing
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6.14 Inter-IC Sound (I2S)
The VC5504 I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data,
between the device and an external I2S peripheral device such as an audio codec.
The VC5504 supports 4 independent dual-channel I2S peripherals, each with the following features:
•
•
•
•
•
•
•
•
Full-duplex (transmit and receive) dual-channel communication
Double buffered data registers that allow for continuous data streaming
I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
Ability to sign-extend received data samples for easy use in signal processing algorithms
Programmable polarity for both frame synchronization and bit clocks
Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode
Detection of over-run, under-run, and frame-sync error conditions
6.14.1 I2S Peripheral Register Description(s)
Table 6-26 through Table 6-29 show the I2S0 through I2S3 registers.
For more detailed information on I2S peripheral and its registers, see the TMS320VC5505 Inter-IC Sound
Bus (I2S) User's Guide (literature number SPRUFP4).
Table 6-26. I2S0 Registers
HEX ADDRESS
ACRONYM
REGISTER NAME
RANGE
2800h
2804h
2808h
2809h
280Ch
280Dh
2810h
2814h
2828h
2829h
282Ch
282Dh
I2S0SCTRL
I2S0SRATE
I2S0TXLT0
I2S0TXLT1
I2S0TXRT0
I2S0TXRT1
I2S0INTFL
I2S0 Serializer Control Register
I2S0 Sample Rate Generator Register
I2S0 Transmit Left Data 0 Register
I2S0 Transmit Left Data 1 Register
I2S0 Transmit Right Data 0 Register
I2S0 Transmit Right Data 1 Register
I2S0 Interrupt Flag Register
I2S0INTMASK
I2S0RXLT0
I2S0RXLT1
I2S0RXRT0
I2S0RXRT1
I2S0 Interrupt Mask Register
I2S0 Receive Left Data 0 Register
I2S0 Receive Left Data 1 Register
I2S0 Receive Right Data 0 Register
I2S0 Receive Right Data 1 Register
Table 6-27. I2S1 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2900h
2904h
2908h
2909h
290Ch
290Dh
2910h
2914h
2928h
2929h
292Ch
I2S1SCTRL
I2S1SRATE
I2S1TXLT0
I2S1TXLT1
I2S1TXRT0
I2S1TXRT1
I2S1INTFL
I2S1 Serializer Control Register
I2S1 Sample Rate Generator Register
I2S1 Transmit Left Data 0 Register
I2S1 Transmit Left Data 1 Register
I2S1 Transmit Right Data 0 Register
I2S1 Transmit Right Data 1 Register
I2S1 Interrupt Flag Register
I2S1INTMASK
I2S1RXLT0
I2S1RXLT1
I2S1RXRT0
I2S1 Interrupt Mask Register
I2S1 Receive Left Data 0 Register
I2S1 Receive Left Data 1 Register
I2S1 Receive Right Data 0 Register
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Table 6-27. I2S1 Registers (continued)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
I2S1 Receive Right Data 1 Register
292Dh
I2S1RXRT1
Table 6-28. I2S2 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2A00h
2A04h
2A08h
2A09h
2A0Ch
2A0Dh
2A10h
2A14h
2A28h
2A29h
2A2Ch
2A2Dh
I2S2SCTRL
I2S2SRATE
I2S2TXLT0
I2S2TXLT1
I2S2TXRT0
I2S2TXRT1
I2S2INTFL
I2S2 Serializer Control Register
I2S2 Sample Rate Generator Register
I2S2 Transmit Left Data 0 Register
I2S2 Transmit Left Data 1 Register
I2S2 Transmit Right Data 0 Register
I2S2 Transmit Right Data 1 Register
I2S2 Interrupt Flag Register
I2S2INTMASK
I2S2RXLT0
I2S2RXLT1
I2S2RXRT0
I2S2RXRT1
I2S2 Interrupt Mask Register
I2S2 Receive Left Data 0 Register
I2S2 Receive Left Data 1 Register
I2S2 Receive Right Data 0 Register
I2S2 Receive Right Data 1 Register
Table 6-29. I2S3 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2B00h
2B04h
2B08h
2B09h
2B0Ch
2B0Dh
2B10h
2B14h
2B28h
2B29h
2B2Ch
2B2Dh
I2S3SCTRL
I2S3SRATE
I2S3TXLT0
I2S3TXLT1
I2S3TXRT0
I2S3TXRT1
I2S3INTFL
I2S3 Serializer Control Register
I2S3 Sample Rate Generator Register
I2S3 Transmit Left Data 0 Register
I2S3 Transmit Left Data 1 Register
I2S3 Transmit Right Data 0 Register
I2S3 Transmit Right Data 1 Register
I2S3 Interrupt Flag Register
I2S3INTMASK
I2S3RXLT0
I2S3RXLT1
I2S3RXRT0
I2S3RXRT1
I2S3 Interrupt Mask Register
I2S3 Receive Left Data 0 Register
I2S3 Receive Left Data 1 Register
I2S3 Receive Right Data 0 Register
I2S3 Receive Right Data 1 Register
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6.14.2 I2S Electrical Data/Timing
Table 6-30. Timing Requirements for I2S [I/O = 3.3 V, 2.8 V, and 2.5 V](1) (see Figure 6-25)
MASTER
SLAVE
CVDD = 1.05 V
UN
IT
NO.
CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
CVDD = 1.3 V
MIN MAX
MIN MAX
MIN MAX
40 or
40 or
40 or
40 or
1
tc(CLK)
Cycle time, I2S_CLK
ns
2P(1)(2)
2P(1)(2)
2P(1)(2)
2P(1)(2)
2
3
tw(CLKH)
tw(CLKL)
Pulse duration, I2S_CLK high
Pulse duration, I2S_CLK low
20
20
20
20
20
20
20
20
ns
ns
Setup time, I2S_RX valid before
I2S CLK high (CLKPOL = 0)
tsu(RXV-CLKH)
tsu(RXV-CLKL)
th(CLKH-RXV)
th(CLKL-RXV)
tsu(FSV-CLKH)
tsu(FSV-CLKL)
th(CLKH-FSV)
th(CLKL-FSV)
5
5
7
7
–
–
–
–
5
5
7
7
–
–
–
–
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
2
2
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
2
2
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
15
15
15
15
9
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
Hold time, I2S_FS valid after
I2S_CLK high (CLKPOL = 0)
tw(CLKH)
+
tw(CLKH)
+
0.6(3)
0.6(3)
10
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
tw(CLKL)
+
tw(CLKL)
+
0.6(3)
0.6(3)
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Table 6-31. Timing Requirements for I2S [I/O = 1.8 V](1) (see Figure 6-25)
MASTER
SLAVE
CVDD = 1.05 V CVDD = 1.3 V
UN
IT
NO.
CVDD = 1.05 V
CVDD = 1.3 V
MIN MAX
MIN MAX
MIN MAX
MIN MAX
50 or
40 or
50 or
40 or
1
tc(CLK)
Cycle time, I2S_CLK
ns
2P(1)(2)
2P(1)(2)
2P(1)(2)
2P(1)(2)
2
3
tw(CLKH)
tw(CLKL)
Pulse duration, I2S_CLK high
Pulse duration, I2S_CLK low
25
25
20
20
25
25
20
20
ns
ns
Setup time, I2S_RX valid before
I2S CLK high (CLKPOL = 0)
tsu(RXV-CLKH)
tsu(RXV-CLKL)
th(CLKH-RXV)
th(CLKL-RXV)
tsu(FSV-CLKH)
tsu(FSV-CLKL)
th(CLKH-FSV)
th(CLKL-FSV)
5
5
7
7
–
–
–
–
5
5
7
7
–
–
–
–
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
2
2
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
2
2
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
15
15
15
15
9
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
Hold time, I2S_FS valid after
I2S_CLK high (CLKPOL = 0)
tw(CLKH)
+
tw(CLKH)
+
0.6(3)
0.6(3)
10
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
tw(CLKL)
+
tw(CLKL)
+
0.6(3)
0.6(3)
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Table 6-32. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 V, 2.8 V, or 2.5 V] (see Figure 6-25)
MASTER
SLAVE
NO
.
UN
IT
PARAMETER
CVDD = 1.05 V CVDD = 1.3 V CVDD = 1.05 V CVDD = 1.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
40 or
40 or
40 or
40 or
1
2
tc(CLK)
Cycle time, I2S_CLK
ns
2P(1)(2)
2P(1)(2)
2P(1)(2)
2P(1)(2)
tw(CLKH)
tw(CLKL)
tw(CLKL)
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
Pulse duration, I2S_CLK low (CLKPOL = 1)
Pulse duration, I2S_CLK low (CLKPOL = 0)
Pulse duration, I2S_CLK high (CLKPOL = 1)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
3
4
tdmax(CLKL-
DXV)
Output Delay time, I2S_CLK low to I2S_DX
valid (CLKPOL = 0)
15
15
14
14
12
12
12 ns
12 ns
ns
tdmax(CLKH-
DXV)
Output Delay time, I2S_CLK high to I2S_DX
valid (CLKPOL = 1)
Output Hold time, I2S_CLK high to I2S_DX
invalid (CLKPOL = 0)
toh(DXV-CLKH)
0
0
0
0
0
0
0
0
5
6
toh(DXV-
CLKL)
Output Hold time, I2S_CLK low to I2S_DX
invalid (CLKPOL = 1)
ns
tdmax(CLKL-
FSV)
Delay time, I2S_CLK low to I2S_FS valid
(CLKPOL = 0)
14
14
14
14
–
–
–
–
ns
ns
tdmax(CLKH-
FSV)
Delay time, I2S_CLK high to I2S_FS valid
(CLKPOL = 1)
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
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Table 6-33. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 6-25)
MASTER
SLAVE
NO
.
UN
IT
PARAMETER
CVDD = 1.05 V CVDD = 1.3 V CVDD = 1.05 V CVDD = 1.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
50 or
40 or
50 or
40 or
1
2
tc(CLK)
Cycle time, I2S_CLK
ns
2P(1)(2)
2P(1)(2)
2P(1)(2)
2P(1)(2)
tw(CLKH)
tw(CLKL)
tw(CLKL)
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
Pulse duration, I2S_CLK low (CLKPOL = 1)
Pulse duration, I2S_CLK low (CLKPOL = 0)
Pulse duration, I2S_CLK high (CLKPOL = 1)
25
25
25
25
20
20
20
20
25
25
25
25
20
20
20
20
ns
ns
ns
ns
3
4
tdmax(CLKL-
DXV)
Output Delay time, I2S_CLK low to I2S_DX
valid (CLKPOL = 0)
19
19
14
14
15
15
12 ns
12 ns
ns
tdmax(CLKH-
DXV)
Output Delay time, I2S_CLK high to I2S_DX
valid (CLKPOL = 1)
Output Hold time, I2S_CLK high to I2S_DX
invalid (CLKPOL = 0)
toh(DXV-CLKH)
0
0
0
0
0
0
0
0
5
6
toh(DXV-
CLKL)
Output Hold time, I2S_CLK low to I2S_DX
invalid (CLKPOL = 1)
ns
tdmax(CLKL-
FSV)
Delay time, I2S_CLK low to I2S_FS valid
(CLKPOL = 0)
14
14
14
14
–
–
–
–
ns
ns
tdmax(CLKH-
FSV)
Delay time, I2S_CLK high to I2S_FS valid
(CLKPOL = 1)
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
1
2
3
I2S_CLK
(CLKPOL = 0)
I2S_CLK
(CLKPOL = 1)
6
I2S_FS
(Output, MODE = 1)
10
9
I2S_FS
(Input, MODE = 0)
4
5
8
I2S_DX
I2S_RX
7
Figure 6-25. I2S Input and Output Timings
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6.15 Serial Port Interface (SPI)
The VC5504M serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a
serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The
SPI can operate as a master device only, slave mode is not supported.
The SPI is normally used for communication between the DSP and external peripherals. Typical
applications include an interface to external I/O or peripheral expansion via devices such as shift registers,
display drivers, SPI EEPROMs, and analog-to-digital converters.
The SPI has the following features:
•
•
•
•
•
•
•
•
•
•
Programmable divider for serial data clock generation
Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX)
Programmable data length (1 to 32 bits)
4 external chip select signals
Programmable transfer or frame size (1 to 4096 characters)
Optional interrupt generation on character completion
Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles
Programmable signal polarities
Programmable active clock edge
Internal loopback mode for testing
6.15.1 SPI Peripheral Register Description(s)
Table 6-34 shows the SPI registers.
For more detailed information on the SPI peripheral, see the TMS320VC5505 Serial Port Interface (SPI)
User's Guide (literature number SPRUFO3).
Table 6-34. SPI Module Registers
CPU
WORD
ACRONYM
REGISTER NAME
ADDRESS
3000h
3001h
3002h
3003h
3004h
3005h
3006h
3007h
3008h
3009h
SPICDR
SPICCR
Clock Divider Register
Clock Control Register
SPIDCR1
SPIDCR2
SPICMD1
SPICMD2
SPISTAT1
SPISTAT2
SPIDAT1
SPIDAT2
Device Configuration Register 1
Device Configuration Register 2
Command Register 1
Command Register 2
Status Register 1
Status Register 2
Data Register 1
Data Register 2
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6.15.2 SPI Electrical Data/Timing
Table 6-35. Timing Requirements for SPI input (see Figure 6-26 through Figure 6-29)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
MAX
MIN
MAX
66.4 or
4P(1)(2)
40 or
5
tC(SCLK)
Cycle time, SPI_CLK
ns
4P(1)(2)
6
7
tw(SCLKH)
tw(SCLKL)
Pulse duration, SPI_CLK high
30
30
15
15
15
15
0
19
19
13
13
13
13
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPI_CLK low
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0
Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3
Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 0
Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 1
Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 2
Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 3
8
9
tsu(SRXV-SCLK)
0
0
th(SCLK-SRXV)
0
0
0
0
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
Table 6-36. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 6-26 through Figure 6-29)
CVDD = 1.05 V
MIN
CVDD = 1.3 V
MIN
NO.
PARAMETER
UNIT
MAX
MAX
Delay time, SPI_CLK low to SPI_TX vaild, SPI
Mode 0
8
5
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, SPI_CLK high to SPI_TX vaild, SPI
Mode 1
8
8
8
5
5
5
1
td(SCLK-STXV)
Delay time, SPI_CLK high to SPI_TX vaild, SPI
Mode 2
Delay time, SPI_CLK low to SPI_TX vaild, SPI
Mode 3
Output hold time, SPI_CLK high to SPI_TX invaild,
SPI Mode 0
tw(SCLKH)
-
tw(SCLKH) - 4
4.5
Output hold time, SPI_CLK low to SPI_TX invaild,
SPI Mode 1
tw(SCLKL)
-
tw(SCLKL) - 4
tw(SCLKL) - 4
tw(SCLKH) - 4
4.5
2
toh(SCLK-STXIV)
Output hold time, SPI_CLK low to SPI_TX invaild,
SPI Mode 2
tw(SCLKL)
-
4.5
Output hold time, SPI_CLK high to SPI_TX invaild,
SPI Mode 3
tw(SCLKH)
-
4.5
3
4
td(SPICS-SCLK)
Delay time, SPI_CS active to SPI_CLK active
tC - 8 + D(1)
tC - 8 + D(1) ns
ns
Output hold time, SPI_CS inactive to SPI_CLK
inactive
toh(SCLKI-SPICSI)
0.5tC - 2
0.5tC - 2
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
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5
6
7
SPI_CLK
SPI_TX
1
2
9
Bn-2
Bn-2
Bn-1
B0
B0
B1
B1
SPI_RX
SPI_CS
Bn-1
8
3
4
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 6-26. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
5
6
7
SPI_CLK
SPI_TX
SPI_RX
2
1
3
Bn-2
Bn-2
Bn-1
Bn-1
B0
B1
B1
B1
8
9
4
SPI_CS
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 6-27. SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1)
5
6
7
SPI_CLK
SPI_TX
SPI_RX
1
2
B0
B0
B1
B1
Bn-2
Bn-2
Bn-1
Bn-1
4
8
9
3
SPI_CS
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 6-28. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0)
5
7
6
SPI_CLK
SPI_TX
SPI_RX
SPI_CS
2
1
3
Bn-2
Bn-2
Bn-1
Bn-1
B0
B0
B1
B1
8
9
4
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 6-29. SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1)
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6.16 Universal Serial Bus (USB) 2.0 Controller
The VC5504 USB2.0 peripheral supports the following features:
•
•
•
•
USB 2.0 peripheral at speeds high-speed (480 Mb/s) and full-speed (12 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous asynchronous mode)
4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
Integrated USB 2.0 High Speed PHY
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB2.0 peripheral on this device, does not support:
•
•
•
Host Mode (Peripheral/Device Modes supported only)
On-Chip Charge Pump
On-the-Go (OTG) Mode
For more detailed information on the USB peripheral, see the TMS320VC5505 DSP Universal Serial Bus
2.0 (USB) User's Guide (literature number SPRUFO0).
6.16.1 USB2.0 Peripheral Register Description(s)
Table 6-37 lists of the USB2.0 peripheral registers.
For more detailed information on USB and its registers, see the TMS320VC5505Universal Serial Bus
(USB) User's Guide (literature number SPRUFO0).
Table 6-37. Universal Serial Bus (USB) Registers(1)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
8000h
8001h
8004h
8008h
800Ch
8010h
8011h
8014h
8018h
8019h
801Ch
801Dh
8020h
8021h
8024h
8025h
8028h
8029h
802Ch
802Dh
REVID1
REVID2
Revision Identification Register 1
Revision Identification Register 2
Control Register
CTRLR
STATR
Status Register
EMUR
Emulation Register
MODER1
Mode Register 1
MODER2
Mode Register 2
AUTOREQ
SRPFIXTIME1
SRPFIXTIME2
TEARDOWN1
TEARDOWN2
INTSRCR1
INTSRCR2
INTSETR1
INTSETR2
INTCLRR1
INTCLRR2
INTMSKR1
INTMSKR2
Auto Request Register
SRP Fix Time Register 1
SRP Fix Time Register 2
Teardown Register 1
Teardown Register 2
USB Interrupt Source Register 1
USB Interrupt Source Register 2
USB Interrupt Source Set Register 1
USB Interrupt Source Set Register 2
USB Interrupt Source Clear Register 1
USB Interrupt Source Clear Register 2
USB Interrupt Mask Register 1
USB Interrupt Mask Register 2
(1) Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable
word accesses to the USB registers [see USB System Control Register (USBSCR) [1C32h] section of the TMS320VC5505 DSP System
User's Guide (lilterature number SPRUFP0)] .
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Table 6-37. Universal Serial Bus (USB) Registers (continued)
CPU WORD
ACRONYM
REGISTER DESCRIPTION
ADDRESS
8030h
8031h
8034h
8035h
8038h
8039h
803Ch
8040h
8041h
8050h
8051h
8054h
8055h
8058h
8059h
805Ch
805Dh
INTMSKSETR1
INTMSKSETR2
INTMSKCLRR1
INTMSKCLRR2
INTMASKEDR1
INTMASKEDR2
EOIR
USB Interrupt Mask Set Register 1
USB Interrupt Mask Set Register 2
USB Interrupt Mask Clear Register 1
USB Interrupt Mask Clear Register 2
USB Interrupt Source Masked Register 1
USB Interrupt Source Masked Register 2
USB End of Interrupt Register
INTVECTR1
INTVECTR2
GREP1SZR1
GREP1SZR2
GREP2SZR1
GREP2SZR2
GREP3SZR1
GREP3SZR2
GREP4SZR1
GREP4SZR2
USB Interrupt Vector Register 1
USB Interrupt Vector Register 2
Generic RNDIS EP1Size Register 1
Generic RNDIS EP1Size Register 2
Generic RNDIS EP2 Size Register 1
Generic RNDIS EP2 Size Register 2
Generic RNDIS EP3 Size Register 1
Generic RNDIS EP3 Size Register 2
Generic RNDIS EP4 Size Register 1
Generic RNDIS EP4 Size Register 2
Common USB Registers
8400h
8401h
8404h
8405h
8408h
8409h
840Ch
840Dh
FADDR_POWER
INTRTX
Function Address Register, Power Management Register
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts, Interrupt Enable Register
Frame Number Register
INTRRX
INTRTXE
INTRRXE
INTRUSB_INTRUSBE
FRAME
Index Register for Selecting the Endpoint Status and Control Registers, Register to
Enable the USB 2.0 Test Modes
INDEX_TESTMODE
USB Indexed Registers
8410h
8411h
Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to
select Endpoints 1-4)
TXMAXP_INDX
PERI_CSR0_INDX
PERI_TXCSR_INDX
RXMAXP_INDX
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to
select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select
Endpoints 1-4)
8414h
8415h
8418h
Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to
select Endpoints 1-4)
Control Status Register for Peripheral Receive Endpoint. (Index register set to select
Endpoints 1-4)
PERI_RXCSR_INDX
COUNT0_INDX
Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint
0)
Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select
Endpoints 1- 4)
RXCOUNT_INDX
8419h
841Ch
841Dh
-
-
Reserved
Reserved
CONFIGDATA_INDC
(Upper byte of 841Dh)
Returns details of core configuration. (index register set to select Endpoint 0)
USB FIFO Registers
8420h
8421h
FIFO0R1
FIFO0R2
Transmit and Receive FIFO Register 1 for Endpoint 0
Transmit and Receive FIFO Register 2 for Endpoint 0
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Table 6-37. Universal Serial Bus (USB) Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
8424h
8425h
8428h
8429h
842Ch
842Dh
8430h
8431h
FIFO1R1
FIFO1R2
FIFO2R1
FIFO2R2
FIFO3R1
FIFO3R2
FIFO4R1
FIFO4R2
Transmit and Receive FIFO Register 1 for Endpoint 1
Transmit and Receive FIFO Register 2 for Endpoint 1
Transmit and Receive FIFO Register 1 for Endpoint 2
Transmit and Receive FIFO Register 2 for Endpoint 2
Transmit and Receive FIFO Register 1 for Endpoint 3
Transmit and Receive FIFO Register 2 for Endpoint 3
Transmit and Receive FIFO Register 1 for Endpoint 4
Transmit and Receive FIFO Register 2 for Endpoint 4
Dynamic FIFO Control Registers
8460h
8461h
-
Reserved
Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to
select Endpoints 1-4)
TXFIFOSZ_RXFIFOSZ
8464h
8465h
846Ch
TXFIFOADDR
Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Reserved
RXFIFOADDR
-
Control and Status Register for Endpoint 0
8500h
8501h
8504h
8505h
8508h
8509h
850Ch
-
Reserved
PERI_CSR0
Control Status Register for Peripheral Endpoint 0
-
Reserved
-
Reserved
COUNT0
Number of Received Bytes in Endpoint 0 FIFO
Reserved
-
-
Reserved
CONFIGDATA
(Upper byte of 850Dh)
Returns details of core configuration.
850Dh
Control and Status Register for Endpoint 1
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in the Receiving Endpoint's FIFO
Reserved
8510h
8511h
8514h
8515h
8518h
8519h
851Ch
851Dh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
Control and Status Register for Endpoint 2
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8520h
8521h
8524h
8525h
8528h
8529h
852Ch
852Dh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
Control and Status Register for Endpoint 3
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
8530h
8531h
8534h
TXMAXP
PERI_TXCSR
RXMAXP
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Table 6-37. Universal Serial Bus (USB) Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
8535h
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8538h
RXCOUNT
8539h
-
-
-
853Ch
853Dh
Reserved
Reserved
Control and Status Register for Endpoint 4
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8540h
8541h
8544h
8545h
8548h
8549h
854Ch
854Dh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
CPPI DMA (CMDA) Registers
9000h
9001h
9004h
9008h
9800h
9801h
9808h
9809h
980Ch
980Dh
9810h
9811h
9820h
9821h
9828h
9829h
982Ch
982Dh
9830h
9831h
9840h
9841h
9848h
9849h
984Ch
984Dh
9850h
9851h
9860h
9861h
9868h
-
Reserved
-
Reserved
TDFDQ
CDMA Teardown Free Descriptor Queue Control Register
CDMA Emulation Control Register
DMAEMU
TXGCR1[0]
TXGCR2[0]
RXGCR1[0]
RXGCR2[0]
RXHPCR1A[0]
RXHPCR2A[0]
RXHPCR1B[0]
RXHPCR2B[0]
TXGCR1[1]
TXGCR2[1]
RXGCR1[1]
RXGCR2[1]
RXHPCR1A[1]
RXHPCR2A[1]
RXHPCR1B[1]
RXHPCR2B[1]
TXGCR1[2]
TXGCR2[2]
RXGCR1[2]
RXGCR2[2]
RXHPCR1A[2]
RXHPCR2A[2]
RXHPCR1B[2]
RXHPCR2B[2]
TXGCR1[3]
TXGCR2[3]
RXGCR1[3]
Transmit Channel 0 Global Configuration Register 1
Transmit Channel 0 Global Configuration Register 2
Receive Channel 0 Global Configuration Register 1
Receive Channel 0 Global Configuration Register 2
Receive Channel 0 Host Packet Configuration Register 1 A
Receive Channel 0 Host Packet Configuration Register 2 A
Receive Channel 0 Host Packet Configuration Register 1 B
Receive Channel 0 Host Packet Configuration Register 2 B
Transmit Channel 1 Global Configuration Register 1
Transmit Channel 1 Global Configuration Register 2
Receive Channel 1 Global Configuration Register 1
Receive Channel 1 Global Configuration Register 2
Receive Channel 1 Host Packet Configuration Register 1 A
Receive Channel 1 Host Packet Configuration Register 2 A
Receive Channel 1 Host Packet Configuration Register 1 B
Receive Channel 1 Host Packet Configuration Register 2 B
Transmit Channel 2 Global Configuration Register 1
Transmit Channel 2 Global Configuration Register 2
Receive Channel 2 Global Configuration Register 1
Receive Channel 2 Global Configuration Register 2
Receive Channel 2 Host Packet Configuration Register 1 A
Receive Channel 2 Host Packet Configuration Register 2 A
Receive Channel 2 Host Packet Configuration Register 1 B
Receive Channel 2 Host Packet Configuration Register 2 B
Transmit Channel 3 Global Configuration Register 1
Transmit Channel 3 Global Configuration Register 2
Receive Channel 3 Global Configuration Register 1
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Table 6-37. Universal Serial Bus (USB) Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
9869h
986Ch
RXGCR2[3]
RXHPCR1A[3]
Receive Channel 3 Global Configuration Register 2
Receive Channel 3 Host Packet Configuration Register 1 A
Receive Channel 3 Host Packet Configuration Register 2 A
Receive Channel 3 Host Packet Configuration Register 1 B
Receive Channel 3 Host Packet Configuration Register 2 B
CDMA Scheduler Control Register 1
986Dh
RXHPCR2A[3]
9870h
RXHPCR1B[3]
9871h
RXHPCR2B[3]
A000h
DMA_SCHED_CTRL1
DMA_SCHED_CTRL2
ENTRYLSW[N]
A001h
CDMA Scheduler Control Register 1
A800h + 4 × N
A801h + 4 × N
CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)
CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)
Queue Manager (QMGR) Registers
ENTRYMSW[N]
C000h
C001h
-
-
Reserved
Reserved
C008h
DIVERSION1
DIVERSION2
FDBSC0
Queue Manager Queue Diversion Register 1
C009h
Queue Manager Queue Diversion Register 2
C020h
Queue Manager Free Descriptor/Buffer Starvation Count Register 0
Queue Manager Free Descriptor/Buffer Starvation Count Register 1
Queue Manager Free Descriptor/Buffer Starvation Count Register 2
Queue Manager Free Descriptor/Buffer Starvation Count Register 3
Queue Manager Free Descriptor/Buffer Starvation Count Register 4
Queue Manager Free Descriptor/Buffer Starvation Count Register 5
Queue Manager Free Descriptor/Buffer Starvation Count Register 6
Queue Manager Free Descriptor/Buffer Starvation Count Register 7
Queue Manager Linking RAM Region 0 Base Address Register 1
Queue Manager Linking RAM Region 0 Base Address Register 2
Queue Manager Linking RAM Region 0 Size Register
Reserved
C021h
FDBSC1
C024h
FDBSC2
C025h
FDBSC3
C028h
FDBSC4
C029h
FDBSC5
C02Ch
FDBSC6
C02Dh
FDBSC7
C080h
LRAM0BASE1
LRAM0BASE2
LRAM0SIZE
-
C081h
C084h
C085h
C088h
LRAM1BASE1
LRAM1BASE2
PEND0
Queue Manager Linking RAM Region 1 Base Address Register 1
Queue Manager Linking RAM Region 1 Base Address Register 2
Queue Manager Queue Pending 0
C089h
C090h
C091h
PEND1
Queue Manager Queue Pending 1
C094h
PEND2
Queue Manager Queue Pending 2
C095h
PEND3
Queue Manager Queue Pending 3
C098h
PEND4
Queue Manager Queue Pending 4
C099h
PEND5
Queue Manager Queue Pending 5
D000h + 16 × R
D001h + 16 × R
D004h + 16 × R
D005h + 16 × R
E000h + 16 × N
E001h + 16 × N
E004h + 16 × N
E005h + 16 × N
E008h + 16 × N
E009h + 16 × N
E00Ch + 16 × N
E00Dh + 16 × N
QMEMRBASE1[R]
QMEMRBASE2[R]
QMEMRCTRL1[R]
QMEMRCTRL2[R]
CTRL1A
Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)
Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)
Queue Manager Memory Region R Control Register (R = 0 to 15)
Queue Manager Memory Region R Control Register (R = 0 to 15)
Queue Manager Queue N Control Register 1A (N = 0 to 63)
Queue Manager Queue N Control Register 2A (N = 0 to 63)
Queue Manager Queue N Control Register 1B (N = 0 to 63)
Queue Manager Queue N Control Register 2B (N = 0 to 63)
Queue Manager Queue N Control Register 1C (N = 0 to 63)
Queue Manager Queue N Control Register 2C (N = 0 to 63)
Queue Manager Queue N Control Register 1D (N = 0 to 63)
Queue Manager Queue N Control Register 2D (N = 0 to 63)
CTRL2A
CTRL1B
CTRL2B
CTRL1C
CTRL2C
CTRL1D
CTRL2D
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Table 6-37. Universal Serial Bus (USB) Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
E800h + 16 × N
E801h + 16 × N
E804h + 16 × N
E805h + 16 × N
E808h + 16 × N
E809h + 16 × N
QSTAT1A
QSTAT2A
QSTAT1B
QSTAT2B
QSTAT1C
QSTAT1C
Queue Manager Queue N Status Register 1A (N = 0 to 63)
Queue Manager Queue N Status Register 2A (N = 0 to 63)
Queue Manager Queue N Status Register 1B (N = 0 to 63)
Queue Manager Queue N Status Register 2B (N = 0 to 63)
Queue Manager Queue N Status Register 1C (N = 0 to 63)
Queue Manager Queue N Status Register 2C (N = 0 to 63)
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6.16.2 USB2.0 Electrical Data/Timing
Table 6-38. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-30)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps(1)
UNIT
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
tr(D)
Rise time, USB_DP and USB_DM signals(2)
Fall time, USB_DP and USB_DM signals(2)
Rise/Fall time, matching(3)
Output signal cross-over voltage(2)
Pulse duration, EOP transmitter(4)
Pulse duration, EOP receiver(4)
Data Rate
20
20
ns
ns
%
V
tf(D)
4
3
trfM
90
1.3
160
82
111
2
–
–
–
4
VCRS
tw(EOPT)
tw(EOPR)
t(DRATE)
ZDRV
ZINP
–
7
175
–
ns
ns
8
–
9
12
480 Mb/s
10
11
Driver Output Resistance
40.5
49.5
40.5
-
49.5
-
Ω
Ω
Receiver Input Impedance
100k
(1) For more detailed informaton, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7.
(2) Full Speed and High Speed CL = 50 pF
(3) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(4) Must accept as valid EOP
t t
per - jr
USB_DM
V
90% V
OH
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 6-30. USB2.0 Integrated Transceiver Interface Timing
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6.17 General-Purpose Timers
The VC5504 has three 32-bit software programmable Timers. Each timer can be used as a
general- purpose (GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both.
General-purpose timers are typically used to provide interrupts to the CPU to schedule periodic tasks or a
delayed task. A watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP
timers are 32-bit timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as
a reference clock. These timers can be used to generate periodic interrupts. The Watchdog Timer is a
16-bit counter with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of
a fault condition, such as a non-exiting code loop.
The VC5504 Timers support the following:
•
•
•
32-bit Programmable Countdown Timer
13-bit Prescaler Divider
Timer Modes:
–
–
32-bit General-Purpose Timer
32-bit Watchdog Timer (Timer2 only)
•
•
Auto Reload Option
Generates Single Interrupt to CPU (The interrupt is individually latched to determine which timer
triggered the interrupt.)
•
•
Generates Active Low Pulse to the Hardware Reset (Watchdog only)
Interrupt can be Used for DMA Event
6.17.1 Timers Peripheral Register Description(s)
Table 6-39 through Table 6-42 show the Timer and Watchdog registers.
For more detailed information on the 32-bit General-Purpose Timers, the Watchdog Timer, and their
corresponding registers, see the TMS320VC5505 32-Bit Timer/Watchdog Timer User's Guide (literature
number SPRUFO2).
Table 6-39. Watchdog Timer Registers (Timer2 only)
CPU WORD
ACRONYM
REGISTER DESCRIPTION
ADDRESS
1880h
1882h
1884h
1886h
1888h
188Ah
188Ch
188Eh
WDKCKLK
WDKICK
WDSVLR
WDSVR
WDENLOK
WDEN
Watchdog Kick Lock Register
Watchdog Kick Register
Watchdog Start Value Lock Register
Watchdog Start Value Register
Watchdog Enable Lock Register
Watchdog Enable Register
WDPSLR
WDPS
Watchdog Prescale Lock Register
Watchdog Prescale Register
Table 6-40. General-Purpose Timer 0 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1810h
1812h
1813h
1814h
1815h
TCR
Timer 0 Control Register
Timer 0 Period Register 1
Timer 0 Period Register 2
Timer 0 Counter Register 1
Timer 0 Counter Register 2
TIMPRD1
TIMPRD2
TIMCNT1
TIMCNT2
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Table 6-41. General-Purpose Timer 1 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1850h
1852h
1853h
1854h
1855h
TCR
Timer 1 Control Register
Timer 1 Period Register 1
Timer 1 Period Register 2
Timer 1 Counter Register 1
Timer 1 Counter Register 2
TIMPRD1
TIMPRD2
TIMCNT1
TIMCNT2
Table 6-42. General-Purpose Timer 2 Registers
CPU WPRD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1890h
1892h
1893h
1894h
1895h
TCR
Timer 2 Control Register
Timer 2 Period Register 1
Timer 2 Period Register 2
Timer 2 Counter Register 1
Timer 2 Counter Register 2
TIMPRD1
TIMPRD2
TIMCNT1
TIMCNT2
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6.18 General-Purpose Input/Output
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of the
internal register. The GPIO can also be used to send interrupts to the CPU.
The VC5504 GPIO peripheral supports the following:
•
•
•
•
Up to 26 GPIOs plus 1 general-purpose output (XF)
All GPIO pins have internal pulldowns (IPDs) which can be individually disabled
Output Set/Clear functionality through writing a single output data register
All GPIOs can be configured to generate edge detected interrupts to the CPU on either the rising or
falling edge
VC5504 GPIO pin functions are multiplexed with various other signals. For more detailed information on
what signals are multiplexed with the GPIO and how to configure them, see Section 3.5, Terminal
Functions and Section 4, Device Configuration of this document.
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6.18.1 General-Purpose Input/Output Peripheral Register Description(s)
The external parallel port interface includes a 16-bit general purpose I/O that can be individually
programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained
through a set of I/O memory-mapped registers shown in Table 6-43.
Table 6-43. GPIO Registers(1)
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1C06h
1C07h
1C08h
1C09h
1C0Ah
1C0Bh
1C0Ch
1C0Dh
1C0Eh
1C0Fh
1C10h
1C11h
IODIR1
IODIR2
GPIO Direction Register 1
GPIO Direction Register 2
GPIO Data In Register 1
GPIO Data In Register 2
GPIO Data Out Register 1
GPIO Data Out Register 2
IOINDATA1
IOINDATA2
IODATAOUT1
IODATAOUT2
IOINTEDG1
IOINTEDG2
IOINTEN1
GPIO Interrupt Edge Trigger Enable Register 1
GPIO Interrupt Edge Trigger Enable Register 2
GPIO Interrupt Enable Register 1
IOINTEN2
GPIO Interrupt Enable Register 2
IOINTFLG1
IOINTFLG2
GPIO Interrupt Flag Register 1
GPIO Interrupt Flag Register 2
(1) For more information on the GPIO module and its registers please see the TMS320VC5505 General-Purpose Input/Output (GPIO)
User’s Guide (literature number SPRUFO4).
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6.18.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-44. Timing Requirements for GPIO Inputs(1) (see Figure 6-31)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
MAX
1
2
tw(ACTIVE)
Pulse duration, GPIO input/external interrupt pulse active
Pulse duration, GPIO input/external interrupt pulse inactive
2C(1)(2)
ns
ns
(1)(2)
tw(INACTIVE)
C
(1) The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 6-45. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-31)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
UNIT
MIN
3C(1)(2)
3C(1)(2)
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GP[x] output high
Pulse duration, GP[x] output low
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
2
1
GP[x] Input
(With IOINTEDGy = 0)
2
1
GP[x] Input
(With IOINTEDGy = 1)
4
3
GP[x] Output
Figure 6-31. GPIO Port Timing
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6.18.3 GPIO Peripheral Input Latency Electrical Data/Timing
Table 6-46. Timing Requirements for GPIO Input Latency(1)
CVDD = 1.05 V
CVDD = 1.3 V
NO
.
UNIT
MIN
5
MAX
Polling GPIO_DIN register
cyc
cyc
cyc
1
tL(GPI)
Latency, GP[x] input
Polling GPIO_IFR register
Interrupt Detection
7
8
(1) The pulse width given is sufficient to generate a CPU interrupt. However, if a user wants to have VC5504 recognize the GP[x] input
changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access
the GPIO register through the internal bus.
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6.19 IEEE 1149.1 JTAG
The JTAG interface is used for Boundary-Scan testing and emulation of the VC5504 device.
TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
The VC5504 includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be
asserted upon power up and the device's internal emulation logic will always be properly initialized. It is
also recommended that an external pulldown be added to ensure proper device operation when an
emulation or boundary scan JTAG controller is not connected to the JTAG pins. JTAG controllers from
Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive
TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller,
assert TRST to initialize the device after powerup and externally drive TRST high before attempting any
emulation or boundary scan operations. The VC5504 device will not operate properly if TRST is not
asserted low during powerup.
6.19.1 JTAG ID (JTAGID) Register Description(s)
Table 6-47. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
N/A
JTAGID
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The
register hex value for VC5504 is: 0x0009 702F. For the actual register bit names and their associated bit
field descriptions, see Figure 6-32 and Table 6-48.
31-28
VARIANT (4-Bit)
R-0000
27-12
11-1
0
PART NUMBER (16-Bit)
R-0000 0000 1001 0111
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-32. JTAG ID Register Description - VC5504 Register Value - 0x0009 702F
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Table 6-48. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value. VC5504 value: 0000.
Part Number (16-Bit) value. VC5504 value: 0000 0000 1001 0111.
PART NUMBER
MANUFACTURER Manufacturer (11-Bit) value. VC5504 value: 0000 0010 111.
LSB LSB. This bit is read as a "1" for VC5504.
6.19.2 JTAG Test_port Electrical Data/Timing
Table 6-49. Timing Requirements for JTAG Test Port (see Figure 6-33)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
UNIT
MIN
60
24
24
10
6
MAX
2
3
4
5
6
7
8
tc(TCK)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
tw(TCKH)
Pulse duration, TCK high
tw(TCKL)
Pulse duration, TCK low
tsu(TDIV-TCKH)
tsu(TMSV-TCKH)
th(TCKH-TDIV)
th(TCKH-TDIV)
Setup time, TDI valid before TCK high
Setup time, TMS valid before TCK high
Hold time, TDI valid after TCK high
Hold time, TMS valid after TCK high
4
4
Table 6-50. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-33)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
UNIT
MIN
MAX
1
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
28
ns
2
3
4
TCK
TDO
1
1
7
8
5
6
TDI
TMS
Figure 6-33. JTAG Test-Port Timing
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7 Mechanical Packaging and Orderable Information
The following table(s) show the thermal resistance characteristics for the PBGA–ZCH mechanical
package.
7.1 Thermal Data for ZCH
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCH]
NO.
＝C/W(1)
AIR FLOW
(m/s)(2)
1
2
RΘJC
RΘJB
Junction-to-case
Junction-to-board
1S0P
1S0P
2S2P
1S0P
2S2P
6.74
14.5
13.8
57.0
33.4
N/A
N/A
3
0.00
RΘJA
Junction-to-free air
4
5
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
RΘJMA
Junction-to-moving air
6
7
8
0.09
13.7
9
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
Junction-to-board
PsiJB
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages.
(2) m/s = meters per second
7.1.1 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMX320VC5504DZCH
ACTIVE
NFBGA
ZCH
196
184 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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