TMS32C5517AZCHA20R [TI]
低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC | ZCH | 196 | -40 to 85;型号: | TMS32C5517AZCHA20R |
厂家: | TEXAS INSTRUMENTS |
描述: | 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC | ZCH | 196 | -40 to 85 CD 外围集成电路 |
文件: | 总197页 (文件大小:1730K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TMS320C5517
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
TMS320C5517 定点数字信号处理器
1 器件概述
1.1 特性
1
– 直接存储器存取 (DMA) 控制器
四个 DMA,各配有四条通道
– 三个 32 位通用 (GP) 定时器
• 内核:
•
– 高性能、低功耗 TMS320C55x 定点数字信号处
理器
•
•
•
•
13.33ns 至 5ns 指令周期时间
75MHz 至 200MHz 时钟速率
每个周期执行一条或两条指令
•
•
一个可被选为安全装置或 GP
计时选项,包括外部通用 I/O (GPIO) 时钟输
入
– 两个多媒体卡和安全数字(eMMC,MMC 和
SD)接口
两个乘积累积单元(每秒高达 4.5 亿次乘积累
积运算 [MMACS])
– 具有四芯片选择的串行端口接口 (SPI)
– 主控和受控内部集成电路(I2C 总线)
•
•
两个算术和逻辑单元 (ALU)
三个内部数据或操作数读取总线和两个写入总
线
– 三个用于数据传输的内部集成电路 (IC) 声音(I2S
总线)模块
•
•
与 C55x 器件软件兼容
提供工业温度器件
– 10 位 4 输入逐次逼近 (SAR) ADC
– IEEE-1149.1 (JTAG)
边界扫描兼容
– 320KB 零等待状态片上 RAM:
•
64KB 双访问 RAM (DARAM),
8 块 4K x 16 位
– 多达 26 个 GPIO 引脚(与其它功能多路复用)
• 电源:
•
256KB 单访问 RAM (SARAM),
32 块 4K x 16 位
– 四个内核隔离的电源域:模拟,RTC,CPU 和外
设,以及 USB
– 四个 I/O 隔离电源域:RTC I/O,EMIF
I/O,USB PHY 和 DVDDIO
– 128KB 零等待状态片上 ROM
(4 块 16K x 16 位)
– 紧密耦合快速傅里叶变换 (FFT) 硬件加速器
– 1.05V 内核,1.8V、2.75V 或 3.3V I/O
– 1.3V 内核,1.8V、2.75V 或 3.3V I/O
– 1.4V 内核,1.8V、2.75V 或 3.3V I/O
• 外设:
– 一个带有 16 位复用地址或数据总线的通用主机
端口接口 (UHPI)
• 时钟:
– 具有三芯片选择的主控和受控多通道串行端口接
口 (McSPI)
– 具有晶振输入、独立时钟域和电源的实时时钟
(RTC)
– 主控和受控多通道经缓冲串行端口接口 (McBSP)
– 软件可编程锁相环 (PLL) 时钟发生器
• 引导加载程序:
– 与下列器件有无缝接口连接的 16 位和 8 位外部
存储器接口 (EMIF)
•
8 位或 16 位 NAND 闪存,1 位或 4 位纠错码
(ECC)
8 位和 16 位 NOR 闪存
异步静态 RAM (SRAM)
– 片上 ROM 引导加载程序
•
每个外设均支持不加密启动
• 封装:
– 196 端子无铅塑料 BGA(球栅阵列)封装(后缀
ZCH),0.65mm 间距
•
•
•
SDRAM 或 mSDRAM(1.8,2.75 和 3.3 V)
– 3.84375M x 16 位最大可寻址外部存储器空
间(SDRAM 或 mSDRAM)
– 通用异步收发器 (UART)
– 带有集成型 2.0 高速物理层 (PHY) 的器件 USB
端口,支持:
•
USB 2.0 全速和高速器件
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SPRS727
TMS320C5517
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
www.ti.com.cn
1.2 应用
•
•
数字双向无线电
•
•
音频器件(例如:回声抵消耳机和免提电话或者无
线耳机和麦克风)
低功耗分析应用(例如:语音识别、视觉传感和指
纹识别)
便携式医疗设备
•
语音应用(例如:录音机、免提套件和语音增强子
系统)
1.3 说明
此器件是 TI C5000™ 定点数字信号处理器 (DSP) 产品系列的成员之一,专用于低运行和待机功耗应用。
此器件基于 TMS320C55x DSP 生成 CPU 处理器内核。 C55x DSP 架构通过增加的并行性和重视节能来实
现高性能和低功耗。 CPU 支持一个内部总线结构,此结构包含一条程序总线,一条 32 位读取总线和两条
16 位数据读取总线,两条数据写入总线和专门用于外设和 DMA 操作的附加总线。 这些总线可实现在一个
单周期内执行高达四次 16 位数据读取和两次 16 位数据写入的功能。 此器件还包含四个 DMA 控制器,每
个控制器具有 4 条通道,可在无需 CPU 干预的情况下提供 16 条独立通道的数据传送。 每个 DMA 控制器
在每周期可执行一个 32 位数据传输,此数据传输与 CPU 的运行并行并且不受 CPU 运行的影响。
C55x CPU 提供两个乘积累积 (MAC) 单元,每个单元在一个单周期内能够进行 17 位乘以 17 位乘法以及 32
位加法。 一个中央 40 位算术和逻辑单元 (ALU) 由一个附加 16 位 ALU 提供支持。 ALU 的使用受指令集控
制,从而提供优化并行运行和功耗的能力。 C55x CPU 内的地址单元 (AU) 和数据单元 (DU) 对这些资源进
行管理。
C55x CPU 支持一个可变字节宽度指令集以改进代码密度。 指令单元 (IU) 执行从内部或外部存储器中的 32
位程序取指令并且进行针对程序单元 (PU) 的指令排队。 PU 对指令进行解码,将任务指向地址单元和数据
单元资源,并管理受到完全保护的管线。 跳转预测功能避免了条件指令执行时的管线冲刷。
GPIO 功能与 10 位 SAR ADC 一起为状态、中断以及用于键盘和媒体接口的位 I/O 提供足够的引脚。
通过以下器件为串行媒体提供支持:两个多媒体卡和安全数字(MMC 和 SD)外设、三个内部 IC 声
音(I2S 总线)模块、一个具有四芯片选择的串行端口接口 (SPI)、一个具有三芯片选择主控和受控多通道经
缓冲串行端口接口 (McSPI)、一个多通道串行端口 (McBSP)、一个 I2C 多主控和受控接口以及一个通用异步
收发器 (UART) 接口
该器件的外设集包括一个外部存储器接口 (EMIF),此接口提供到异步存储器的无缝访问,例如
EPROM,NOR,NAND 和 SRAM,以及高速、高密度存储器,例如同步 DRAM (SDRAM) 和移动 SDRAM
(mSDRAM)。
其它外设包括:一个可配置 16 位通用主机端口接口 (UHPI)、一条仅支持器件模式的高速通用串行总线
(USB2.0)、一个实时时钟 (RTC)、三个通用定时器(其中一个可配置为看门狗定时器)和一个模拟锁相环
(APLL) 时钟发生器。
器件还包含一个紧密耦合 FFT 硬件加速器 - 支持 8 至 1024 点(2 的次幂)实值和复值 FFT,三个集成低压
降稳压器 (LDO) - 为器件的各部分供电(需要外部电源的 CVDDRTC 除外):ANA_LDO 为 SAR 和电源管理
电路 (VDDA_ANA) 提供 1.3V 电压,DSP_LDO 为 DSP 内核 (CVDD)(一旦检测到工作频率范围,便可由软件
实时进行选择)提供 1.3V 或 1.05V 电压,USB_LDO 为 USB 内核数字电路 (USB_VDD1P3) 和 PHY 电路
(USB_VDDA1P3) 提供 1.3V 电压。
此器件由业界备受赞誉的 eXpressDSP™、 Code Composer Studio™ 集成开发环境 (IDE)、
DSP/BIOS™、德州仪器 (TI) 的算法标准和一个大型第三方网络提供支持。 Code Composer Studio IDE 提
供的代码生成工具包括一个 C 语言编译器和连接器、 RTDX™、XDS100、 XDS510™、 XDS560™ 仿真
器件驱动程序和评估模块。 此器件也受 C55x DSP 库以及芯片支持库的支持,此库特有超过 50 个基础软件
内核(FIR 滤波器、IIR 滤波器、FFT 和多种数学函数)。
器件信息
封装
部件号
TMS320C5517AZCH20
TMS320C5517AZCHA20
封装尺寸
NFBGA (196)
NFBGA (196)
10.0mm x 10.0mm
10.0mm x 10.0mm
2
器件概述
版权 © 2012–2014, Texas Instruments Incorporated
TMS320C5517
www.ti.com.cn
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
1.4 功能方框图
图 1-1可展示器件的功能框图
DSP System
C55x DSP CPU
JTAG Interface
FFT Hardware
Accelerator
Input
Clocks
PLL/Clock
Generator
64KB DARAM
256KB SARAM
128KB ROM
Power
Management
Pin
Multiplexing
Switched Central Resource (SCR)
Peripherals
Interconnect
App-Spec
Serial Interfaces
I2S
(x3)
10-Bit
DMA
(x4)
I2C
SPI
McSPI
UART
SAR
ADC
McBSP
Connectivity
System
Program/Data Storage
USB 2.0
PHY (HS)
[DEVICE]
NAND, NOR,
SRAM, mSDRAM
MMC/SD
(x2)
GP Timer
(x2)
GP Timer
or WD
LDOs
UHPI
RTC
图 1-1. 功能方框图
版权 © 2012–2014, Texas Instruments Incorporated
器件概述
3
TMS320C5517
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
Terminal Configuration and Functions.............. 8
4.1 Pin Diagram .......................................... 8
4.2 Signal Descriptions ................................... 9
4.3 Pin Multiplexing...................................... 51
4.4 Connections for Unused Signals.................... 55
Specifications ........................................... 56
5.1 Absolute Maximum Ratings......................... 56
5.2 Recommended Operating Conditions............... 57
5.3 Electrical Characteristics ............................ 58
5.4 Handling Ratings.................................... 60
5.5 Thermal Characteristics............................. 60
5.6 Power-On Hours .................................... 60
5.7 Timing and Switching Characteristics ............... 61
Detailed Description.................................. 153
6.1 CPU ................................................ 153
6.2 Memory ............................................ 153
6.3 Identification........................................ 181
6.4 Boot Modes ........................................ 182
Device and Documentation Support.............. 189
7.1 Device Support..................................... 189
7.2 Documentation Support............................ 191
7.3 社区资源 ........................................... 191
7.4 商标 ................................................ 191
7.5 静电放电警告....................................... 191
7.6 Glossary............................................ 191
6
2
3
4
7
8
5
Mechanical Packaging and Orderable
Information............................................. 192
4
内容
版权 © 2012–2014, Texas Instruments Incorporated
TMS320C5517
www.ti.com.cn
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
2 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
本数据手册修订历史记录强调了对之前版本的器件专用数据手册所做的技术更改。
参见
新增内容、修改内容和删除内容
全局
删除了 225MHz 器件信息。
Copyright © 2012–2014, Texas Instruments Incorporated
修订历史记录
5
Submit Documentation Feedback
Product Folder Links: TMS320C5517
TMS320C5517
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
www.ti.com.cn
3 Device Comparison
Table 3-1 provides characteristics of the C5517 processor.
The table shows significant features of the devices, including the capacity of on-chip RAM, the
peripherals, the CPU frequency, and the package type with pin count. For more detailed information on
the actual device part number and maximum device operating frequency, see Section 7.1.2, Device
Nomenclature.
Table 3-1. Characteristics of the Processor
HARDWARE FEATURES
C5517
Asynchronous (8- and 16-bit bus width) SRAM,
Flash (NOR, NAND),
External Memory Interface (EMIF)
SDRAM and Mobile SDRAM (16-bit bus width)(1)
Peripherals
Not all peripheral pins
are available at the
same time (for more
detail, see Section 5).
Four DMA controllers each with four channels,
for a total of 16 channels
DMA
2 32-Bit General-Purpose (GP) Timers
Additional Timer Configurable as
1
a 32-Bit GP Timer or a
Watchdog
Timers
Each timer is capable of selecting its clock source among the
choices of:
•
•
•
External from a GPIO pin
System PLL
12.00 MHz USB oscillator
UART
SPI
1 (with RTS and CTS flow control)
1 with 4 chip selects (Master only)
1 (Master and Slave synchronous serial bus) with 3 chip selects
1 (A configurable 16-bit multiplexed host port interface)
1 (Master and Slave)
McSPI
UHPI
I2C
I2S
3 (Two Channel, Full Duplex Communication)
High- and Full-Speed Device (device mode only, host mode not
supported)
USB 2.0
2 MMC and SD, 256 byte read and write buffer, max 50-MHz clock
for SD cards, and signaling for DMA transfers
MMC and SD
McBSP
1 (with transmit and receive)
ADC (Successive Approximation [SAR])
Real-Time Clock (RTC)
FFT Hardware Accelerator
1 (10-bit, 4-input, 16-µs conversion time)
1 (Crystal Input, Separate Clock Domain and Power Supply)
1 (Supports 8 to 1024-point 16-bit real and complex FFT)
Up to 26 pins (with 1 Additional General-Purpose Output (XF) and 4
General-Purpose Outputs for Use With SAR)
General-Purpose Input/Output Port (GPIO)
•
64KB On-Chip Dual-Access RAM (DARAM)
256KB On-Chip Single-Access RAM (SARAM)
128KB On-Chip Single-Access ROM (SAROM)
On-Chip Memory
Size and Organization
•
•
JTAGID Register
(Value is: 0x0B95 602F)
JTAG BSDL_ID
CPU Frequency
see Figure 6-2
1.05-V Core
1.3-V Core
1.4-V Core
1.05-V Core
1.3-V Core
75 MHz
175 MHz
200 MHz
13.3 ns
MHz
Cycle Time
ns
5.71 ns
(1) For more information on SDRAM devices support, see Section 5.7.6, External Memory Interface (EMIF).
Device Comparison
6
Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5517
TMS320C5517
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ZHCS222C –AUGUST 2012–REVISED APRIL 2014
Table 3-1. Characteristics of the Processor (continued)
HARDWARE FEATURES
C5517
5 ns
1.4-V Core
1.05 V (75 MHz)
1.3 V (175 MHz)
1.4 V (200 MHz)
1.8 V, 2.75 V, 3.3 V
Core (V)
I/O (V)
Voltage
LDOs
1.3 V or 1.05 V, 250 mA max current for the digital core (to be used
only to supply CVDD).
DSP_LDO
Cannot be used to drive CVDD at the 1.4 V (>200 MHz) operating
range.
1.3 V, 4 mA max current for SAR and power management circuits
ANA_LDO
USB_LDO
(to be used only to supply VDDA_ANA
)
1.3 V, 25 mA max current for USB core digital and PHY circuits (to
be used only to supply USB_VDD1P3 and USB_VDDA1P3
TMS320C5517AZCH20
)
Commercial Temperature (default)
Industrial Temperature
Phase Lock Loop
Temperature
TMS320C5517AZCHA20
PLL
1 (Software Programmable PLL)
196-Terminal BGA (ZCH), 0.65-mm Pitch
BGA Package
10 x 10 mm
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(2)
PD
(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2012–2014, Texas Instruments Incorporated
Device Comparison
7
Submit Documentation Feedback
Product Folder Links: TMS320C5517
TMS320C5517
ZHCS222C –AUGUST 2012–REVISED APRIL 2014
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagram
Figure 4-1 shows the bottom view of the package pin assignments.
I2S2_FS/
I2S2_DX/
UART_CTS/ UART_TXD/
UHPI_HD[9]/ UHPI_HD[11]/ UHPI_HD[13]/ UHPI_HD[15]/
SPI_CS0/
UHPI_HCNTL0
EM_DQM1/
UHPI_HBE1
SPI_RX/ GP[12]/
UHPI_HD[0] UHPI_HD[2]
GP[15]/ GP[17]/
UHPI_HD[5] UHPI_HD[7]
SPI_CS2/
UHPI_HR_NW
DV
DV
DV
DDIO
DDIO
P
N
M
L
DDEMIF
GP[19]/
SPI_CS0
GP[27]/
SPI_TX
GP[29]/
I2S3_FS
GP[31]/
I2S3_DX
I2S2_CLK/
I2S2_RX/
UART_RTS/ UART_RXD/
UHPI_HD[8]/ UHPI_HD[10]/ UHPI_HD[12]/ UHPI_HD[14]/
SPI_CLK/
UHPI_HINT
GP[21]/
EM_A[15]
EM_SDCKE/
UHPI_HHWIL
SPI_CS1/
UHPI_HCNTL1
SPI_CS3/
SPI_TX/
GP[13]/
GP[14]/
UHPI_HRDY UHPI_HD[1] UHPI_HD[3] UHPI_HD[4] UHPI_HD[6]
GP[16]/
DV
DDIO
GP[18]/
SPI_CLK
GP[20]/
SPI_RX
GP[28]/
I2S3_CLK
GP[30]/
I2S3_RX
MMC0_D1/ MMC0_CMD/
MMC1_D1/ MMC1_CLK/ MMC1_D0/
McSPI_SOMI/ McSPI_CLK/ McSPI_SIMO/
I2S0_RX/ I2S0_FS/
GP[3]/ GP[1]/
McBSP_DR McBSP_FSX
EMU1
EM_SDCLK
EM_D[12]
EM_D[14]
EM_CS3
EM_D[4]
EM_D[13]
EM_A[14]
EM_A[13]
EM_D[5]
XF
TCK
TDO
TDI
TRST
GP[9]
GP[6]
GP[8]
MMC0_D3/
GP[5]/
McBSP_
MMC0_D0/ MMC0_CLK/
MMC1_CMD/
McSPI_CS0/
GP[7]
MMC0_D2/
GP[4]/
McBSP_FSR
MMC1_D3/
McSPI_CS2/
GP[11]
I2S0_DX/
GP[2]/
I2S0_CLK/
GP[0]/
McBSP_DX McBSP_CLKX
EM_A[10]
CV
EMU0
TMS
DD
CLKR_CLKS
MMC1_D2/
McSPI_CS1/
GP[10]
EM_A[12]/
(CLE)
EM_A[11]/
(ALE)
EM_WAIT3
EM_D[6]
DV
V
V
CV
V
SS
DV
V
SS
K
J
DDIO
SS
SS
SS
SS
DD
DDIO
GP[26]/
EM_A[20]
V
USB_VBUS USB_V
USB_DM
USB_DP
USB_MXO
LDOI
EM_A[8]
EM_WE
EM_A[9]
EM_A[7]
EM_D[15]
RSV1
RSV2
DD1P3
SS1P3
DV
V
CV
DD
V
DDEMIF
DDEMIF
DDEMIF
DDEMIF
SS
USB_
USB_
USB_
USB_
V
DDA3P3
EM_WAIT5
USB_V
EM_D[7]
EM_D[0]
DV
DV
DV
V
SS
DV
CV
DD
H
G
F
DDEMIF
V
V
V
SSA1P3
DDA1P3
SSA3P3
GP[24]/
EM_A[18]
GP[25]/
EM_A[19]
EM_WAIT4
USB_V
USB_R1
USB_V
USB_V
USB_V
DDOSC
USB_MXI
DDPLL
SSREF
SSPLL
V
VSS
SS
GP[23]/
EM_A[17]
DV
USB_V
USB_LDOO
LDOI
EM_A[6]
EM_D[2]
EM_D[8]
EM_D[10]
EM_CS4
EM_D[9]
EM_OE
SSOSC
CVDD
DV
DDRTC
V
SS
V
SS
DDIO
GP[22]/
EM_A[16]
DSP_LDOO
EM_D[1]
WAKEUP
DV
INT1
V
V
V
V
V
SS
V
SS
E
D
C
B
A
EM_A[2]
EM_A[5]
DDEMIF
RESET
INT0
SS
SS
SS
RTC_
CLKOUT
DSP_
LDO_EN
V
SSA_PLL
EM_WAIT2
GPAIN0
RSV16
RSV5
RSV3
RSV4
EM_A[3]
EM_A[1]
EM_A[0]
EM_D[3]
EM_D[11]
V
SS
SS
V
V
CV
DDA_PLL
EM_CS2
DDRTC
EM_A[4]
CLK_SEL
SSRTC
GPAIN3
GPAIN2
RSV0
LDOI
V
V
SSA_ANA
EM_BA[1]
EM_CS0/
UHPI_HDS1
EM_DQM0/
UHPI_HBE0
RTC_XI
SSA_ANA
BG_CAP
EM_R/W
EM_SDCAS/
UHPI_HCS
SCL
SDA
EM_BA[0]
EM_CS1/
UHPI_HDS2
RTC_XO
V
ANA_LDOO
GPAIN1
DV
EM_CS5
DV
EM_SDRAS/
UHPI_HAS
DDA_ANA
CLKOUT
CLKIN
DDEMIF
DDEMIF
V
SS
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to
GP[21] when reset).
Figure 4-1. Pin Diagram
8
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4.2 Signal Descriptions
The signal descriptions tables (Table 4-1 through Table 4-19) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more
information on pin multiplexing, see Section 4.3, Pin Multiplexing.
For proper device operation, external pullup and pulldown resistors may be required on some pins.
Section 5.7.20.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and
pulldown resistors are required.
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4.2.1 Oscillator and PLL
Table 4-1. Oscillator and PLL Signal Descriptions
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap
different clocks within the system clock generator. The CLKOUT_SRC bits in the
CLKOUT Configuration Register (CLKOUTCR) can be used to specify the
CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be
controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16].
The output driver of the CLKOUT pin is enabled and disabled through the
CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin's
output driver is placed in high-impedance (Hi-Z) and the IPD is automatically
enabled. When enabled, the output driver of the pin is enabled and the IPD is
automatically disabled.
IPD
DVDDIO
BH
CLKOUT
A7
O/Z
At reset the CLKOUT pin is enabled until the beginning of the boot sequence, at
which point the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is
disabled (Hi-Z). For more information on the ST3_55 register, see the C55x 3.0
CPU Reference Guide [literature number: SWPU073].
The IPD resistor on this pin is enabled when CLKOUT is in Hi-Z state.
Input clock. This signal is used to input an external clock when the 12-MHz on-
chip USB oscillator is not used as the system clock (CLK_SEL = 1).
To appropriately set the various serial port frequencies during bootloading, the
bootloader ROM code assumes CLKIN is running at the frequency indicated by
the setting (see Section 6.4, Boot Modes, for the supported frequencies and
details about the bootmode).
IPD
DVDDIO
BH
CLKIN
A8
I
The CLK_SEL pin selects the source for the system clock generator, with the
options being the USB oscillator (CLK_SEL=0) or CLKIN (CLK_SEL=1) pins.
When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When
CLK_SEL is high, this pin should be driven by an external clock source.
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD disabled at reset.
Clock input select. This pin selects between the on-chip USB oscillator or CLKIN.
0 = The on-chip USB oscillator is enabled at reset and drives the system clock
generator. The CLKIN is ignored. Also, the USB LDOO is enabled at reset
(USB_LDO_EN=1). The on-chip USB oscillator and USB_LDO cannot be disabled
if CLK_SEL=0.
–
CLK_SEL
C7
I
DVDDIO
BH
1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB
LDO are disabled at reset (USB_LDO_EN=1), but they can be enabled by
software.
This pin is not allowed to change during device operation; it must be tied high or
low at the board.
1.3-V Analog PLL power supply for the system clock generator.
see Section 5.2,
ROC
VDDA_PLL
C10
D9
PWR
GND
This supply pin must not be connected to ANA_LDOO pin. The supply pin must be
externally powered.
see Section 5.2,
ROC
VSSA_PLL
Analog PLL ground for the system clock generator.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
10
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4.2.2 Real-Time Clock (RTC)
Table 4-2. RTC Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME
NO.
Real-time clock oscillator output. This pin operates at the RTC core voltage,
CVDDRTC, and supports a 32.768-kHz crystal.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS).
–
RTC_XO
A9
O/Z
CVDDRTC
DVDDRTC
A voltage must still be applied to CVDDRTC by an external power source (see
Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can
power CVDDRTC
.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
Real-time clock oscillator input.
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS).
–
A voltage must still be applied to CVDDRTC by an external power source (see
Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can
RTC_XI
B9
I
CVDDRTC
DVDDRTC
power CVDDRTC
.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
Real-time clock output pin. This pin operates at DVDDRTC voltage.
–
The RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in
the RTC Power Management Register (RTCPMGT).
RTC_CLKOUT
WAKEUP
D8
E8
O/Z
DVDDRTC
At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]).
The active-high pin is used to WAKEUP the core from idle condition. This pin
defaults to an input at CVDDRTC powerup, but can also be configured as an active-
low open-drain output signal to wakeup an external device from an RTC alarm.
–
I/O/Z
DVDDRTC
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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4.2.3 RESET, Interrupts, and JTAG
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions
SIGNAL
NAME
TYPE(1) (2) OTHER(3) (4)
DESCRIPTION
NO.
RESET
External Flag Output. XF is used for signaling other processors in
multiprocessor configurations or XF can be used as a fast general-
purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the
BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For
more information on the ST1_55 register, see the C55x 3.0 CPU
Reference Guide [literature number: SWPU073].
IPU
DVDDIO
BH
XF
M8
O/Z
For the XF pin's states after reset, see Figure 5-9, BootMode Latching.
XF pin can manually configured as Hi-Z state only in boundary-scan
mode. When this pin is in Hi-Z state, the IPU is enabled.
The IPU on this pin is disabled at reset.
Device reset. RESET causes the DSP to terminate execution and loads
the program counter with the contents of the reset vector. When
RESET is brought to a high level, the reset vector in ROM at FFFF00h
forces the program execution to branch to the location of the on-chip
ROM bootloader.
IPU
DVDDIO
BH
RESET
D6
I
RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h).
The IPU is disabled at reset.
JTAG
For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference [literature number:
SPRU589].
IEEE standard 1149.1 test mode select. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TMS must be buffered. In this case, the input buffer for TMS
needs a pullup resistor connected to DVDDIO to hold the signal at a
known value when the emulator is not connected. A resistor value of
4.7 kΩ or greater is suggested. For board design guidelines related to
the emulation header, see the XDS560 Emulator Technical Reference
[literature number: SPRU589].
IPU
DVDDIO
BH
TMS
L8
I
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
12
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Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)
SIGNAL
TYPE(1) (2) OTHER(3) (4)
DESCRIPTION
NAME
NO.
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge
of TCK. TDO is in the high-impedance (Hi-Z) state except when the
scanning of data is in progress.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
If the emulation header is located greater than 6 inches from the
device, TDO must be buffered.
IPU
DVDDIO
BH
Despite the fact that the IEEE 1149.1 (JTAG) standard defines the TDO
pin as a 3-state output (O/Z), this device has a bidirectional IO-cell. The
bidirectional cell's input buffer is used for non-JTAG production test
purposes. To achieve the lowest power, this input buffer must not be
allowed to float.
TDO
M7
I/O/Z
The IEEE standard defines the pin as tri-stated in the Test-Logic-Reset
state and our device obeys that requirement. Therefore, to achieve the
lowest power the IPU should remain enabled.
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
IEEE standard 1149.1 test data input. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TDI must be buffered. In this case, the input buffer for TDI
needs a pullup resistor connected to DVDDIO to hold this signal at a
known value when the emulator is not connected. A resistor value of
4.7 kΩ or greater is suggested.
IPU
DVDDIO
BH
TDI
L7
I
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on input signals TMS and
TDI are clocked into the TAP controller, instruction register, or selected
test data register on the rising edge of TCK. Changes at the TAP output
signal (TDO) occur on the falling edge of TCK.
If the emulation header is located greater than 6 inches from the
device, TCK must be buffered.
IPU
DVDDIO
BH
TCK
M6
I
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
IEEE standard 1149.1 reset signal for test and emulation logic. TRST,
when high, allows the IEEE standard 1149.1 scan and emulation logic
to take control of the operations of the device. If TRST is not connected
or is driven low, the device operates in its functional mode, and the
IEEE standard 1149.1 signals are ignored. The device will not operate
properly if this reset pin is never asserted low.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
IPD
DVDDIO
BH
TRST
M9
I
It is recommended that an external pulldown resistor be used in
addition to the IPD -- especially if there is a long trace to an emulation
header.
The IPD resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPD is enabled at reset.
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Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)
SIGNAL
NAME
TYPE(1) (2) OTHER(3) (4)
DESCRIPTION
NO.
Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator
system and is defined as input/output by way of the emulation logic.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
An external pullup to DVDDIO is required to provide a signal rise time of
less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
IPU
DVDDIO
BH
EMU1
M5
I/O/Z
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
Emulator 0 pin. When TRST is driven low and then high, the state of
the EMU0 pin is latched and used to connect the JTAG pins (TCK,
TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when
the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the
latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an
interrupt to or from the emulator system and is defined as input/output
by way of the emulation logic.
IPU
DVDDIO
BH
An external pullup to DVDDIO is required to provide a signal rise time of
less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.
EMU0
L6
I/O/Z
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference [literature number: SPRU589].
The IPU resistor on this pin can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is enabled at reset.
EXTERNAL INTERRUPTS
IPU
DVDDIO
BH
External interrupt inputs (INT1 and INT0). These pins are maskable via
INT1
INT0
E7
C6
I
I
their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt
mode bit. The pins can be polled and reset by their specific Interrupt
Flag Register (IFR1, IFR0).
IPU
DVDDIO
BH
The IPU resistor on these pins can be enabled or disabled via the
PUDINHIBR2 (1C18h) register.
The IPU is disabled at reset.
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4.2.4 External Memory Interface (EMIF)
Table 4-4. EMIF Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)
Note: When accessing 8-bit Asynchronous memory:
•
•
Connect EM_A[20:0] to memory address pins [22:2]
Connect EM_BA[1:0] to memory address pins [1:0]
For 16-bit Asynchronous memory:
•
•
Connect EM_A[20:1] to memory address pins [20:1]
Connect EM_BA[1] to memory address pin [0]
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 20.
IPD
DVDDEMIF
BH
Mux control via the A20_MODE bit in the EBSR (see Figure 5-10).
GP[26]/
EM_A[20]
J3
G4
G2
F2
E2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 19.
IPD
DVDDEMIF
BH
Mux control via the A19_MODE bit in the EBSR (see Figure 5-10).
GP[25]/
EM_A[19]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 18.
IPD
DVDDEMIF
BH
Mux control via the A18_MODE bit in the EBSR (see Figure 5-10).
GP[24]/
EM_A[18]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 17.
IPD
DVDDEMIF
BH
Mux control via the A17_MODE bit in the EBSR (see Figure 5-10).
GP[23]/
EM_A[17]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 16.
IPD
DVDDEMIF
BH
Mux control via the A16_MODE bit in the EBSR (see Figure 5-10).
GP[22]/
EM_A[16]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-4. EMIF Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF
external address pin 15.
IPD
DVDDEMIF
BH
Mux control via the A15_MODE bit in the EBSR (see Figure 5-10).
GP[21]/
EM_A[15]
N1
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 14.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
EM_A[14]
EM_A[13]
M1
L1
I/O/Z
I/O/Z
The IPD is disabled at reset.
This pin is the EMIF external address pin 13.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 12. When interfacing with NAND Flash,
this pin also acts as Command Latch Enable (CLE).
IPD
DVDDEMIF
BH
EM_A[12]/
(CLE)
K1
K2
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 11. When interfacing with NAND Flash,
this pin also acts as Address Latch Enable (ALE).
IPD
DVDDEMIF
BH
EM_A[11]/
(ALE)
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 10.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
EM_A[10]
EM_A[9]
EM_A[8]
EM_A[7]
L2
J2
J1
H2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD is disabled at reset.
This pin is the EMIF external address pin 9.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 8.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 7.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
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Table 4-4. EMIF Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is the EMIF external address pin 6.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
EM_A[6]
F1
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD is disabled at reset.
This pin is the EMIF external address pin 5.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
EM_A[5]
EM_A[4]
EM_A[3]
EM_A[2]
EM_A[1]
EM_A[0]
D1
C1
D2
E1
C2
B2
The IPD is disabled at reset.
This pin is the EMIF external address pin 4.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 3.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 2.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 1.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
This pin is the EMIF external address pin 0.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5
(1C4Dh) register.
The IPD is disabled at reset.
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Table 4-4. EMIF Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
J4
EM_D[15]
EM_D[14]
EM_D[13]
EM_D[12]
EM_D[11]
EM_D[10]
EM_D[9]
EM_D[8]
EM_D[7]
EM_D[6]
EM_D[5]
EM_D[4]
EM_D[3]
EM_D[2]
EM_D[1]
EM_D[0]
K3
K4
L3
C4
D3
F4
E3
H3
K5
M2
L4
EMIF 16-bit bidirectional bus.
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR4
(1C4Ch) register.
I/O/Z
The IPD is disabled at reset.
D4
F3
E5
G3
EMIF chip select 5 output for use with asynchronous memories (that is, NOR flash,
NAND flash, or SRAM).
IPD
DVDDEMIF
BH
EM_CS5
EM_CS4
EM_CS3
EM_CS2
A3
C3
M4
C5
O/Z
O/Z
O/Z
O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
EMIF chip select 4 output for use with asynchronous memories (that is, NOR flash,
NAND flash, or SRAM).
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
EMIF NAND chip select 3 output for use with asynchronous memories (that is, NOR
flash, NAND flash, or SRAM).
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
EMIF NAND chip select 2 output for use with asynchronous memories (that is, NOR
flash, NAND flash, or SRAM).
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
EMIF asynchronous memory write enable output
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EM_WE
EM_OE
H1
E4
O/Z
O/Z
The IPD is disabled at reset.
EMIF asynchronous memory read enable output
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
18
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Table 4-4. EMIF Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
EMIF asynchronous read and write output
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EM_R/W
B6
O/Z
The IPD is disabled at reset.
IPD
DVDDEMIF
BH
EM_DQM1/
UHPI_HBE1
These pins are multiplexed between EMIF and UHPI. For EMIF, asynchronous data
write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits.
P1
B5
B1
I/O/Z
I/O/Z
O/Z
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDEMIF
BH
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EM_DQM0/
UHPI_HBE0
The IPD is disabled at reset.
IPD
DVDDEMIF
BH
EMIF asynchronous bank address
EM_BA[1]
EM_BA[0]
16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device
address [23].
8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device
address [0].
IPD
DVDDEMIF
BH
EMIF SDRAM and mSDRAM bank address.
A1
O/Z
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is disabled at reset.
EMIF wait state extension input 5 for EM_CS5
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EM_WAIT5
EM_WAIT4
EM_WAIT3
EM_WAIT2
H4
G1
K6
D5
I
I
I
I
The IPD is enabled at reset.
EMIF wait state extension input 4 for EM_CS4
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is enabled at reset.
EMIF wait state extension input 3 for EM_CS3
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is enabled at reset.
EMIF wait state extension input 2 for EM_CS2
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
The IPD is enabled at reset.
EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
chip select 1 output
IPD
EM_CS1/
UHPI_HDS2
Mux control via the PPMODE bits in the EBSR.
DVDDEMIF
A4
I/O/Z
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
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Table 4-4. EMIF Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
chip select 0 output
IPD
DVDDEMIF
BH
EM_CS0/
UHPI_HDS1
B3
I/O/Z
O/Z
Mux control via the PPMODE bits in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
EMIF SDRAM and mSDRAM clock
IPD
DVDDEMIF
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
EM_SDCLK
M3
N2
The IPD is disabled at reset.
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
clock enable
IPD
DVDDEMIF
BH
EM_SDCKE/
UHPI_HHWIL
Mux control via the PPMODE bits in the EBSR.
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
row address strobe
IPD
DVDDEMIF
BH
EM_SDRAS/
UHPI_HAS
Mux control via the PPMODE bits in the EBSR.
A6
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM
column strobe
IPD
DVDDEMIF
BH
EM_SDCAS/
UHPI_HCS
Mux control via the PPMODE bits in the EBSR.
B4
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
20
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4.2.5 Inter-Integrated Circuit (I2C)
Table 4-5. Inter-Integrated Circuit (I2C) Signal Descriptions
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
I2C
–
This pin is the I2C clock output. Per the I2C standard, an external pullup is required
on this pin.
SCL
SDA
B7
B8
I/O/Z
I/O/Z
DVDDIO
BH
–
This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup
is required on this pin.
DVDDIO
BH
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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4.2.6 Inter-IC Sound (I2S)
Table 4-6. Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
Interface 0 (I2S0)
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For I2S, it is I2S0 transmit data output I2S0_DX.
MMC0_D0/
I2S0_DX/
GP[2]/
IPD
DVDDIO
BH
Mux control via the SP0MODE bits in the EBSR.
L9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_DX
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For I2S, it is I2S0 clock input/output I2S0_CLK.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CLK/
I2S0_CLK/
GP[0]/
IPD
DVDDIO
BH
L10
M10
M11
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_CLKX
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For I2S, it is I2S0 receive data input I2S0_RX.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D1/
I2S0_RX/
GP[3]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_DR
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For I2S, it is I2S0 frame synchronization input/output I2S0_FS.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CMD/
I2S0_FS/
GP[1]/
McBSP_FSX
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
Interface 1 (I2S2)
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
For I2S, it is I2S2 transmit data output I2S2_DX.
Mux control via the PPMODE bits in the EBSR.
I2S2_DX/
UHPI_HD[11]/
GP[27]/
IPD
DVDDIO
BH
P12
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_TX
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-6. Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
For I2S, it is I2S2 clock input/output I2S2_CLK.
Mux control via the PPMODE bits in the EBSR.
I2S2_CLK/
UHPI_HD[8]/
GP[18]/
IPD
DVDDIO
BH
N10
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CLK
The IPD is enabled at reset.
This pin is multiplexed between UHPI, I2S2, GPIO, and SPI.
For I2S, it is I2S2 receive data input I2S2_RX.
Mux control via the PPMODE bits in the EBSR.
I2S2_RX/
UHPI_HD[10]/
GP[20]/
IPD
DVDDIO
BH
N11
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_RX
The IPD is enabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
For I2S, it is I2S2 frame synchronization input/output I2S2_FS.
Mux control via the PPMODE bits in the EBSR.
I2S2_FS/
UHPI_HD[9]/
GP[19]/
IPD
DVDDIO
BH
P11
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CS0
The IPD is enabled at reset.
Interface 2 (I2S3)
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For I2S, it is I2S3 transmit data output I2S3_DX.
Mux control via the PPMODE bits in the EBSR.
UART_TXD/
UHPI_HD[15]/
GP[31]/
IPD
DVDDIO
BH
P14
N12
N13
P13
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_DX
The IPD is disabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For I2S, it is I2S3 clock input/output I2S3_CLK.
Mux control via the PPMODE bits in the EBSR.
UART_RTS/
UHPI_HD[12]/
GP[28]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_CLK
The IPD is disabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For I2S, it is I2S3 receive data input I2S3_RX.
Mux control via the PPMODE bits in the EBSR.
UART_RXD/
UHPI_HD[14]/
GP[30]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_RX
The IPD is enabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For I2S, it is I2S3 frame synchronization input/output I2S3_FS.
Mux control via the PPMODE bits in the EBSR.
UART_CTS/
UHPI_HD[13]/
GP[29]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_FS
The IPD is enabled at reset.
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4.2.7 Multichannel Buffered Serial Port (McBSP)
Table 4-7. McBSP Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
McBSP
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For McBSP, this is the McBSP transmit clock, McBSP_CLKX.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CLK/
I2S0_CLK/
GP[0]/
IPD
DVDDIO
BH
L10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
McBSP_CLKX
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For McBSP, this is the McBSP transmit frame sync, McBSP_FSX.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CMD/
I2S0_FS/
GP[1]/
McBSP_FSX
IPD
DVDDIO
BH
M11
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For McBSP, this is the McBSP transmit data , McBSP_DX.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D0/
I2S0_DX/
GP[2]/
IPD
DVDDIO
BH
L9
McBSP_DX
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.
For McBSP, this is the McBSP receive data, McBSP_RX.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D1/
I2S0_RX/
GP[3]/
IPD
DVDDIO
BH
M10
McBSP_DR
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, McBSP and GPIO.
For McBSP, this is the McBSP receive frame sync, McBSP_FSR.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D2/
GP[4]/
McBSP_FSR
IPD
DVDDIO
BH
L12
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
24
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Table 4-7. McBSP Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between MMC0, McBSP and GPIO.
For McBSP, this is the McBSP receive clock, McBSP_CLKR or the McBSP sample
rate generator clock input, McBSP_CLKS. The bit 15 of EBSR register determines
this port to be McBSP_CLKR or McBSP_CLKS.
MMC0_D3/
GP[5]/
McBSP_CLKR_
CLKS
IPD
DVDDIO
BH
L11
I/O/Z
Mux control via the SP0MODE bits in the EBSR.
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
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4.2.8 Multichannel Serial Port Interface (McSPI)
Table 4-8. McSPI Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
McSPI
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI data clock, McSPI_CLK.
Mux control via the SP1MODE bits in the EBSR.
MMC1_CLK/
McSPI_CLK/
GP[6]
IPD
DVDDIO
BH
M13
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI chip select 0 signal, McSPI_CS0.
Mux control via the SP1MODE bits in the EBSR.
MMC1_CMD/
McSPI_CS0/
GP[7]
IPD
DVDDIO
BH
L14
M14
M12
K14
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI data, McSPI_SIMO (Slave Input Master Output).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D0/
McSPI_SIMO/
GP[8]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI data, McSPI_SOMI (Slave Output Master Input).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D1/
McSPI_SOMI/
GP[9]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI chip select 1 signal, McSPI_CS1.
Mux control via the SP1MODE bits in the EBSR.
MMC1_D2/
McSPI_CS1/
GP[10]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-8. McSPI Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between MMC1, McSPI and GPIO.
For McSPI, this is the McSPI chip select 2 signal, McSPI_CS2.
Mux control via the SP1MODE bits in the EBSR.
MMC1_D3/
McSPI_CS2/
GP[11]
IPD
DVDDIO
BH
L13
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
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4.2.9 Serial Peripheral Interface (SPI)
Table 4-9. SPI Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
Serial Port Interface (SPI)
This pin is multiplexed between UHPI and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
IPD
DVDDIO
BH
SPI_CS0/
UHPI_HCNTL0
P4
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
I2S2_FS/
UHPI_HD[9]/
GP[19]/
IPD
DVDDIO
BH
P11
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CS0
The IPD is enabled at reset.
This pin is multiplexed between SPI and UHPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS1.
IPD
DVDDIO
BH
SPI_CS1/
UHPI_HCNTL1
N4
P5
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
For SPI, this pin is SPI chip select SPI_CS2.
IPD
DVDDIO
BH
SPI_CS2/
UHPI_HR_NW
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS3.
IPD
DVDDIO
BH
SPI_CS3/
UHPI_HRDY
N5
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
IPD
DVDDIO
BH
SPI_CLK /
UHPI_HINT
N3
O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-9. SPI Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
I2S2_CLK/
UHPI_HD[8]/
GP[18]/
IPD
DVDDIO
BH
N10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CLK
The IPD is enabled at reset.
This pin is multiplexed between UHPI and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
IPD
DVDDIO
BH
SPI_TX /
UHPI_HD[1]
N6
P12
P6
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
I2S2_DX/
UHPI_HD[11]/
GP[27]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_TX
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
IPD
DVDDIO
BH
SPI_RX/
UHPI_HD[0]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
I2S2_RX/
UHPI_HD[10]/
GP[20]/
IPD
DVDDIO
BH
N11
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_RX
The IPD is enabled at reset.
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4.2.10 Universal Asynchronous Receiver and Transmitter (UART)
Table 4-10. UART Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME(5)
NO.
UART
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
When used by UART, it is the receive data input UART_RXD.
Mux control via the PPMODE bits in the EBSR.
UART_RXD/
UHPI_HD[14]/
GP[30]/
IPD
DVDDIO
BH
N13
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_RX
The IPD is enabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
In UART mode, it is the transmit data output UART_TXD.
Mux control via the PPMODE bits in the EBSR.
UART_TXD/
UHPI_HD[15]/
GP[31]/
IPD
DVDDIO
BH
P14
P13
N12
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_DX
The IPD is disabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
In UART mode, it is the clear to send input UART_CTS.
Mux control via the PPMODE bits in the EBSR.
UART_CTS/
UHPI_HD[13]/
GP[29]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_FS
The IPD is enabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
In UART mode, it is the ready to send output UART_RTS.
Mux control via the PPMODE bits in the EBSR.
UART_RTS/
UHPI_HD[12]/
GP[28]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_CLK
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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4.2.11 Universal Serial Bus (USB) 2.0
Table 4-11. USB2.0 Signal Descriptions
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
USB 2.0
12-MHz crystal oscillator input used for the USB subsystem and optionally for the
system clock generator.
If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock
source for the system clock generator. In this configuration (CLK_SEL=0), the USB
oscillator cannot be disabled.
If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as
the source for the system clock generator. In this configuration (CLK_SEL=1), the
USB oscillator can be enabled or disabled via software.
USB_MXI
G13
I
USB_VDDOSC
When using an external 12-MHz oscillator, the external oscillator clock signal should
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO is left unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
12-MHz crystal oscillator output used for the USB subsystem and optionally for the
system clock generator.
If CLK_SEL=0, the USB oscillator is enabled at reset and is used as the clock
source for the system clock generator. In this configuration (CLK_SEL=0), the USB
oscillator cannot be disabled.
If CLK_SEL=1, the USB oscillator is disabled at reset and the CLKIN pin is used as
the source for the system clock generator. In this configuration (CLK_SEL=1), the
USB oscillator can be enabled or disabled via software.
USB_MXO
G14
O
USB_VDDOSC
When using an external 12-MHz oscillator, the external oscillator clock signal should
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO is left unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
3.3-V power supply for USB oscillator.
see
Section 5.2,
ROC
USB_VDDOSC
G12
F11
S
S
When the USB peripheral is not used, USB_VDDOSC should be connected to ground
(VSS).
Ground for USB oscillator. When using a 12-MHz crystal, this pin is a local ground
for the crystal and must not be connected to the board ground (See Figure 5-11).
see
Section 5.2,
ROC
When using an external 12-MHz oscillator, the external oscillator clock signal should
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO is left unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
USB_VSSOSC
USB power detect. 5-V input that signifies that VBUS is connected.
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
USB_VBUS
J12
A
When the USB peripheral is not used, the USB_VBUS signal should be connected
to ground (VSS).
USB_DP
USB_DM
H14
J14
A I/O
A I/O
USB_VDDA3P3 USB bidirectional Data Differential signal pair [positive and negative].
When the USB peripheral is not used, the USB_DP and USB_DM signals should
USB_VDDA3P3
both be tied to ground (VSS).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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Table 4-11. USB2.0 Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
External resistor connect. Reference current output. This pin must be connected via
a 10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as
possible.
USB_R1
G9
A I/O
GND
USB_VDDA3P3
When the USB peripheral is not used, the USB_R1 signal should be connected via
a 10-kΩ resistor to USB_VSSREF
.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
see
Section 5.2,
ROC
USB_VSSREF
G10
When the USB peripheral is not used, the USB_VSSREF signal should be connected
directly to ground (Vss).
Analog 3.3 V power supply for USB PHY.
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
USB_VDDA3P3
USB_VSSA3P3
USB_VDDA1P3
USB_VSSA1P3
USB_VDD1P3
USB_VSS1P3
H12
H11
H10
H9
S
GND
S
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
connected to ground (VSS).
see
Section 5.2,
ROC
Analog ground for USB PHY.
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VDDA1P3 signal should be
connected to ground (VSS).
see
Section 5.2,
ROC
GND
S
Analog ground for USB PHY [For high speed sensitive analog circuits].
1.3-V digital core power supply for USB PHY.
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
J13
H13
When the USB peripheral is not used, the USB_VDD1P3 signal should be connected
to ground (VSS).
see
Section 5.2,
ROC
GND
Digital core ground for USB PHY.
3.3 V USB Analog PLL power supply.
Care should be taken to prevent noise on this supply. Consider using a ferrite bead
if the power supply for this pin is shared with digital logic. See the Filtering
Techniques Application Report [literature number: SCAA048] for more information.
see
Section 5.2,
ROC
USB_VDDPLL
G8
S
When the USB peripheral is not used, the USB_VDDPLL signal should be connected
to ground (VSS).
see
Section 5.2,
ROC
USB_VSSPLL
G11
GND
USB Analog PLL ground.
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4.2.12 Universal Host-Port Interface (UHPI)
Table 4-12. UHPI Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4) DESCRIPTION
This pin is multiplexed between SPI and UHPI.
(2)
NO.
For UHPI, this pin is UHPI host interrupt, UHPI_HINT.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_CLK/
UHPI_HINT
N3
O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
For UHPI, this pin is UHPI access control, UHPI_HCNTL0.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_CS0/
UHPI_HCNTL0
P4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
For UHPI, this pin is UHPI access control, UHPI_HCNTL1.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_CS1/
UHPI_HCNTL1
N4
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
For UHPI this pin is UHPI read and write, UHPI_HR_NW.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_CS2/
UHPI_HR_NW
P5
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between SPI and UHPI.
For UHPI, this pin is the UHPI ready, UHPI_HRDY.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_CS3/
UHPI_HRDY
N5
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
UART_TXD/
UHPI_HD[15]/
GP[31]/
IPD
DVDDIO
BH
P14
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
I2S3_DX
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-12. UHPI Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4) DESCRIPTION
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
(2)
NO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
UART_RXD/
UHPI_HD[14]/
GP[30]/
IPD
DVDDIO
BH
N13
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
I2S3_RX
The IPD is enabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
UART_CTS/
UHPI_HD[13]/
GP[29]/
IPD
DVDDIO
BH
P13
N12
P12
N11
P11
N10
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
I2S3_FS
The IPD is enabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
UART_RTS/
UHPI_HD[12]/
GP[28]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
I2S3_CLK
The IPD is disabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
I2S2_DX/
UHPI_HD[11]/
GP[27]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
SPI_TX
The IPD is disabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
I2S2_RX/
UHPI_HD[10]/
GP[20]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
SPI_RX
The IPD is enabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
I2S2_FS/
UHPI_HD[9]/
GP[19]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
SPI_CS0
The IPD is enabled at reset.
This pin is multiplexed between UHPI, UART, SPI, I2S, and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
I2S2_CLK/
UHPI_HD[8]/
GP[18]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
SPI_CLK
The IPD is enabled at reset.
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Table 4-12. UHPI Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4) DESCRIPTION
This pin is multiplexed between UHPI and GPIO.
(2)
NO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[17]/
UHPI_HD[7]
P10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[16]/
UHPI_HD[6]
N9
P9
N8
N7
P7
N6
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[15]/
UHPI_HD[5]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[14]/
UHPI_HD[4]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[13]/
UHPI_HD[3]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and GPIO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[12]/
UHPI_HD[2]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
This pin is multiplexed between UHPI and SPI.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_TX/
UHPI_HD[1]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
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Table 4-12. UHPI Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4) DESCRIPTION
This pin is multiplexed between UHPI and SPI.
(2)
NO.
For UHPI, this pin is the UHPI data bus, UHPI_HD[15:0].
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
SPI_RX/
UHPI_HD[0]
P6
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3 (1C19h)
register.
The IPD is enabled at reset.
IPD
DVDDIO
BH
EM_DQM1/
UHPI_HBE1
These two pins are multiplexed between UHPI and SDRAM.
For UHPI, these two pins are UHPI Byte Enables, UHPI_HBE[1:0].
Mux control via the PPMODE bits in the EBSR.
P1
B5
I/O/Z
I/O/Z
IPD
DVDDIO
BH
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6
(1C4Fh) register.
EM_DQM0/
UHPI_HBE0
The IPD is disabled at reset.
IPD
DVDDIO
BH
EM_CS1/
UHPI_HDS2
These two pins are multiplexed between UHPI and SDRAM.
For UHPI, these two pins are UHPI data strobe pins, UHPI_HDS[2:1].
Mux control via the PPMODE bits in the EBSR.
A4
B3
I/O/Z
I/O/Z
IPD
DVDDIO
BH
EM_CS0/
UHPI_HDS1
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR7
(1C50h) register.
The IPD is disabled at reset.
This pin is multiplexed between UHPI and SDRAM.
For UHPI, this pin is Half-word Identification control input pin, UHPI_HHWIL.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
EM_SDCKE/
UHPI_HHWIL
N2
A6
B4
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between UHPI and SDRAM.
For UHPI, this pin is address strobe pin, UHPI_HAS.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
EM_SDRAS/
UHPI_HAS
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
This pin is multiplexed between UHPI and SDRAM.
For UHPI, this pin is chip select pin, UHPI_HCS.
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
EM_SDCAS/
UHPI_HCS
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7 (1C50h)
register.
The IPD is disabled at reset.
36
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4.2.13 MultiMedia Card (MMC)
Table 4-13. MMC1 and SD Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
MMC and SD
This pin is multiplexed between MMC1, McSPI, and GPIO.
For MMC and SD, this is the MMC1 data clock output MMC1_CLK.
Mux control via the SP1MODE bits in the EBSR.
MMC1_CLK/
McSPI_CLK/
GP[6]
IPD
DVDDIO
BH
M13
O
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For MMC and SD, this is the MMC1 command I/O output MMC1_CMD.
Mux control via the SP1MODE bits in the EBSR.
MMC1_CMD/
McSPI_CS0/
GP[7]
IPD
DVDDIO
BH
L14
O
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
MMC1_D3/
McSPI_CS2/
GP[11]
IPD
DVDDIO
BH
L13
K14
M12
M14
I/O/Z
I/O/Z
I/O/Z
I/O/Z
These pins are multiplexed between MMC1, McSPI, and GPIO.
MMC1_D2/
McSPI_CS1/
GP[10]
IPD
DVDDIO
BH
In MMC and SD mode, all these pins are the MMC1 nibble wide bidirectional data
bus.
Mux control via the SP1MODE bits in the EBSR.
MMC1_D1/
McSPI_SOMI/
GP[9]
IPD
DVDDIO
BH
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
MMC1_D0/
McSPI_SIMO/
GP[8]
IPD
DVDDIO
BH
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-14. MMC0 and SD Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
MMC and SD
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For MMC and SD, this is the MMC0 data clock output MMC0_CLK.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CLK/
I2S0_CLK/
GP[0]/
IPD
DVDDIO
BH
L10
O
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_CLKX
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For MMC and SD, this is the MMC0 command I/O output MMC0_CMD.
Mux control via the SP0MODE bits in the EBSR.
MMC0_CMD/
I2S0_FS/
GP[1]/
McBSP_FSX
IPD
DVDDIO
BH
M11
O
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
MMC0_D3/
GP[5]/
McBSP_CLKR_
CLKS
IPD
DVDDIO
BH
L11
L12
M10
I/O/Z
I/O/Z
I/O/Z
These pins are multiplexed between MMC0, I2S0, McBSP and GPIO
In MMC and SD mode, these pins are the MMC0 nibble wide bidirectional data bus.
Mux control via the SP0MODE bits in the EBSR.
MMC0_D2/
GP[4]/
McBSP_FSR
IPD
DVDDIO
BH
MMC0_D1/
I2S0_RX/
GP[3]/
IPD
DVDDIO
BH
The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_DR
The IPD is disabled at reset.
MMC0_D0/
I2S0_DX/
GP[2]/
IPD
DVDDIO
BH
L9
I/O/Z
McBSP_DX
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
38
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4.2.14 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
Table 4-15. 10-Bit SAR ADC Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME
NO.
SAR ADC
GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed
internally into ADC Channels 0, 1, and 2. GPAIN0 can also be used as a general-
purpose open-drain output. This pin is unique among the GPAIN pins in that it is the
only pin that is 3.6 V-tolerant to support measuring a battery voltage. GPAIN0 can
accommodate input voltages from 0 V to 3.6 V; although, the ADC is unable to
accept signals greater than VDDA_ANA without clamping. ADC Channel 1 is capable
of switching in an internal resistor divider that has a divide ratio of approximately 1/8.
GPAIN0
D10
I/O
VDDA_ANA
GPAIN1: General -Purpose Output and Analog Input pin 1. This pin is connected to
ADC Channel 3. GPAIN1 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN1 can accommodate input
voltages from 0 V to VDDA_ANA
.
GPAIN1
A11
I/O
VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip power-on reset (POR)
resetting the chip.
GPAIN2: General -Purpose Output and Analog Input pin 2. This pin is connected to
ADC Channel 4. GPAIN2 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN2 can accommodate input
voltages from 0 V to VDDA_ANA
.
GPAIN2
B11
I/O
VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip POR resetting the chip.
GPAIN3: General -Purpose Output and Analog Input pin 3. This pin is connected to
ADC Channel 5. GPAIN3 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN3 can accommodate input
voltages from 0 V to VDDA_ANA
.
GPAIN3
C11
I/O
VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3.2, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip POR resetting the chip.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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4.2.15 General-Purpose Input and Output (GPIO)
Table 4-16. GPIO Signal Descriptions
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
General-Purpose Input/Output
External Flag Output. XF is used for signaling other processors in multiprocessor
configurations or XF can be used as a fast general-purpose output pin.
XF is set high by the BSET XF instruction and XF is set low by the BCLR XF
instruction or by writing to bit 13 of the ST1_55 register. For more information on the
ST1_55 register, see the C55x 3.0 CPU Reference Guide [literature number:
SWPU073].
IPU
DVDDIO
BH
XF
M8
O/Z
For the XF pin's states after reset, see Figure 5-9, BootMode Latching.
XF pin can manually configured as Hi-Z state only in boundary-scan mode. When
this pin is in Hi-Z state, the IPU is enabled.
The IPU on this pin is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 0 (GP[0]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_CLK/
I2S0_CLK/
GP[0]/
IPD
DVDDIO
BH
L10
M11
L9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_CLKX
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 1 (GP[1]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_CMD/
I2S0_FS/
GP[1]/
McBSP_FSX
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 2 (GP[2]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_D0/
I2S0_DX/
GP[2]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_DX
The IPD is disabled at reset.
This pin is multiplexed between MMC0, I2S0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 3 (GP[3]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_D1/
I2S0_RX/
GP[3]/
IPD
DVDDIO
BH
M10
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
McBSP_DR
The IPD is disabled at reset.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).
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Table 4-16. GPIO Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between MMC0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 4 (GP[4]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_D2/
GP[4]/
McBSP_FSR
IPD
DVDDIO
BH
L12
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC0, McBSP, and GPIO.
For GPIO, it is general-purpose input/output pin 5 (GP[5]).
Mux control via the SP0MODE bits in the EBSR.
MMC0_D3/
GP[5]/
McBSP_CLKR_
CLKS
IPD
DVDDIO
BH
L11
M13
L14
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 6 (GP[6]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_CLK/
McSPI_CLK/
GP[6]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 7 (GP[7]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_CMD/
McSPI_CS0/
GP[7]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 8 (GP[8]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D0/
McSPI_SIMO/
GP[8]
IPD
DVDDIO
BH
M14
M12
K14
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 9 (GP[9]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D1/
McSPI_SOMI/
GP[9]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 10 (GP[10]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D2/
McSPI_CS1/
GP[10]
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
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Table 4-16. GPIO Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between MMC1, McSPI, and GPIO.
For GPIO, it is general-purpose input/output pin 11 (GP[11]).
Mux control via the SP1MODE bits in the EBSR.
MMC1_D3/
McSPI_CS2/
GP[11]
IPD
DVDDIO
BH
L13
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1
(1C17h) register.
The IPD is disabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 12 (GP[12]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[12]/
UHPI_HD[2]
P7
N7
N8
P9
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 13 (GP[13]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[13]/
UHPI_HD[3]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 14 (GP[14]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[14]/
UHPI_HD[4]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 15 (GP[15]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[15]/
UHPI_HD[5]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 16 (GP[16]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[16]/
UHPI_HD[6]
N9
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
This pin is multiplexed between GPIO and UHPI.
For GPIO, it is general-purpose input/output pin 17 (GP[17]).
Mux control via the PPMODE bits in the EBSR.
IPD
DVDDIO
BH
GP[17]/
UHPI_HD[7]
P10
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
The IPD is enabled at reset.
42
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Table 4-16. GPIO Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
Mux control via the PPMODE bits in the EBSR.
I2S2_CLK/
UHPI_HD[8]/
GP[18]/
IPD
DVDDIO
BH
N10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CLK
The IPD is enabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO and SPI.
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
Mux control via the PPMODE bits in the EBSR.
I2S2_FS/
UHPI_HD[9]/
GP[19]/
IPD
DVDDIO
BH
P11
N11
N1
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_CS0
The IPD is enabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO and SPI.
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
Mux control via the PPMODE bits in the EBSR.
I2S2_RX/
UHPI_HD[10]/
GP[20]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_RX
The IPD is enabled at reset.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 21 (GP[21]).
Mux control via the A15_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[21]/
EM_A[15]
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 22 (GP[22]).
Mux control via the A16_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[22]/
EM_A[16]
E2
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 23 (GP[23]).
Mux control via the A17_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[23]/
EM_A[17]
F2
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 24 (GP[24]).
Mux control via the A18_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[24]/
EM_A[18]
G2
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
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Table 4-16. GPIO Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME(5)
OTHER(3) (4)
DESCRIPTION
(2)
NO.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 25 (GP[25]).
Mux control via the A19_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[25]/
EM_A[19]
G4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between EMIF and GPIO.
For GPIO, it is general-purpose input/output pin 26 (GP[26]).
Mux control via the A20_MODE bit in the EBSR.
IPD
DVDDEMIF
BH
GP[26]/
EM_A[20]
J3
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2
(1C18h) register.
The IPD is disabled at reset.
This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.
For GPIO, it is general-purpose input/output pin 27 (GP[27]).
Mux control via the PPMODE bits in the EBSR.
I2S2_DX/
UHPI_HD[11]/
GP[27]/
IPD
DVDDIO
BH
P12
N12
P13
N13
P14
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
SPI_TX
The IPD is disabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 28 (GP[28]).
Mux control via the PPMODE bits in the EBSR.
UART_RTS/
UHPI_HD[12]/
GP[28]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_CLK
The IPD is disabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 29 (GP[29]).
Mux control via the PPMODE bits in the EBSR.
UART_CTS/
UHPI_HD[13]/
GP[29]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_FS
The IPD is enabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 30 (GP[30]).
Mux control via the PPMODE bits in the EBSR.
UART_RXD/
UHPI_HD[14]/
GP[30]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_RX
The IPD is enabled at reset.
This pin is multiplexed between UART, UHPI, GPIO, and I2S3.
For GPIO, it is general-purpose input/output pin 31 (GP[31]).
Mux control via the PPMODE bits in the EBSR.
UART_TXD/
UHPI_HD[15]/
GP[31]/
IPD
DVDDIO
BH
The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3
(1C19h) register.
I2S3_DX
The IPD is disabled at reset.
44
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4.2.16 Regulators and Power Management
Table 4-17. Regulators and Power Management Signal Descriptions
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
Regulators
DSP_LDO output. When enabled, this output provides a regulated 1.3 V or 1.05 V
output and up to 250 mA of current (see the ISD parameter in Section 5.3.2,
Electrical Characteristics).
The DSP_LDO is intended to supply current to the digital core circuits only (CVDD
but not to CVDDRTC or external devices. For proper device operation, the external
decoupling capacitor of this pin should be 5µF 10µF. For more detailed
)
DSP_LDOO
E10
S
~
information, see Section 5.7.2.5, Power-Supply Decoupling.
When disabled, this pin is in the high-impedance (Hi-Z) state.
LDO inputs. For proper device operation, LDOI must always be powered. The LDOI
pins must be connected to the same power supply source with a voltage range of
1.8 V to 3.6 V. These pins supply power to the internal LDOs, the bandgap
reference generator circuits, and serve as the I/O supply for some input pins.
F14,
F13,
B12
LDOI
S
DSP_LDO enable input. This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal POR monitors the DSP_LDOO pin voltage
and generates the internal POWERGOOD signal.
–
DSP_LDO_EN
D12
I
1 = DSP_LDO is disabled. The internal POR voltage monitoring is also disabled.
The internal POWERGOOD signal is forced high and the external reset signal on
the RESET pin (D6) is the only source of the device reset. Note, the device's
internal reset signal is generated as the logical AND of the RESET pin and the
internal POWERGOOD signal.
LDOI
USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of
current (see the ISD parameter in Section 5.3.2, Electrical Characteristics).
For proper device operation, this pin must be connected to a 1 µF ~ 2 µF decoupling
capacitor to VSS. For more detailed information, see Section 5.7.2.5, Power-Supply
Decoupling. This LDO is intended to supply power to the USB_VDD1P3
,
USB_VDDA1P3 pins but not to CVDDRTC or external devices.
USB_LDOO
F12
S
Note: The reset state of the register that enables and disables the USB_LDO is
dependent on the setting of CLK_SEL pin at reset.
If CLK_SEL is high, the USB_LDO is disabled at reset but can be enabled by
software.
If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1) at reset and cannot
be disabled by software. (See Section 5.7.2.1.1.2.1 LDO Control for details.)
ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of
current (see the ISD parameter in Section 5.3.2, Electrical Characteristics).
For proper device operation, this pin must be connected to an ~ 1.0 µF decoupling
capacitor to VSS. For more detailed information, see Section 5.7.2.5, Power-Supply
Decoupling. This LDO is intended to supply power to the VDDA_ANA pin but not to
VDDA_PLL, CVDDRTC or external devices.
ANA_LDOO
A12
S
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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Table 4-17. Regulators and Power Management Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
Bandgap reference filter signal. For proper device operation, this pin needs to be
bypassed with a 0.1 µF capacitor to analog ground (VSSA_ANA).
BG_CAP provides a settling time of 200 ms that must elapse before executing
bootloader code. The settling time time is used by Timer0.
BG_CAP
B13
A, O
This external capacitor provides filtering for stable reference voltages and currents
generated by the bandgap circuit. The bandgap produces the references for use by
the SAR and POR circuits.
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4.2.17 Supply Voltage
Table 4-18. Supply Voltage Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME
NO.
SUPPLY VOLTAGES
F6
H8
J6
1.05-V Digital Core supply voltage (75 MHz)
1.3-V Digital Core supply voltage (175 MHz)
1.4-V Digital Core supply voltage (200 MHz)
PWR
CVDD
K10
L5
F7
K7
K12
N14
P3
P8
A2
A5
E6
F5
DVDDIO
PWR
1.8-V, 2.75-V, or 3.3-V I/O power supply for non-EMIF and non-RTC I/Os
DVDDIO must always be powered for proper operation.
1.8-V, 2.75-V, or 3.3-V EMIF I/O power supply
DVDDEMIF must always be powered for proper operation. GP[26:21] are used for
boot mode configuration.
DVDDEMIF
G5
PWR
H5
H7
J5
P2
1.05-V RTC digital core and RTC oscillator power supply.
CVDDRTC
C8
F8
PWR
PWR
Note: The CVDDRTC pin must always be powered by an external power source even
though RTC is not used. None of the on-chip LDOs can power CVDDRTC
.
1.8-V, 2.75-V, or 3.3-V I/O power supply for peripheral pins.
DVDDRTC
DVDDRTC can be tied to ground (VSS) when RTC_CLKOUT and WAKEUP pins are
not used permanently. In this case, the WAKEUP pin must be configured as output
by software. (See Table 5-1, RTCPMGT Register Bit Descriptions.)
1.3-V Analog PLL power supply for the system clock generator.
Care should be taken to prevent noise on this supply. Consider using a ferrite bead
if the power supply for this pin is shared with digital logic. See the Filtering
Techniques Application Report [literature number: SCAA048] for more information.
see
Section 5.2,
ROC
VDDA_PLL
C10
PWR
This signal cannot be powered from the ANA_LDOO pin. It must be powered
externally.
3.3 V USB Analog PLL power supply.
Care should be taken to prevent noise on this supply. Consider using a ferrite bead
if the power supply for this pin is shared with digital logic. See the Filtering
Techniques Application Report [literature number: SCAA048] for more information.
see
Section 5.2,
ROC
USB_VDDPLL
G8
S
When the USB peripheral is not used, the USB_VDDPLL signal should be connected
to ground (VSS).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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Table 4-18. Supply Voltage Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
1.3-V digital core power supply for USB PHY.
(2)
NO.
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
USB_VDD1P3
USB_VDDA1P3
USB_VDDA3P3
J13
S
S
S
When the USB peripheral is not used, the USB_VDD1P3 signal should be connected
to ground (VSS).
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
H10
H12
When the USB peripheral is not used, the USB_VDDA1P3 signal should be
connected to ground (VSS).
Analog 3.3 V power supply for USB PHY.
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.2, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VDDA3P3 signal should be
connected to ground (VSS).
3.3-V power supply for USB oscillator.
see
Section 5.2,
ROC
USB_VDDOSC
G12
A10
S
When the USB peripheral is not used, USB_VDDOSC should be connected to
ground (VSS).
1.3-V supply for power management and 10-bit SAR ADC
This signal can be powered from the ANA_LDOO pin.
VDDA_ANA
PWR
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4.2.18 Ground
Table 4-19. Ground Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME
NO.
A13
A14
D7
D11
E9
E11
E12
E13
E14
F9
VSS
GND
Ground pins
F10
G6
G7
H6
J7
J8
J9
K8
K9
K11
K13
Ground for RTC oscillator. When using a 32.768-kHz crystal, this pin is a local
ground for the crystal and must not be connected to the board ground (See
Figure 5-13 and Figure 5-16). When not using RTC and the crystal is not populated
on the board, this pin is connected to the board ground.
VSSRTC
C9
GND
see
Section 5.2,
ROC
VSSA_PLL
D9
G11
H13
H9
GND
GND
GND
GND
GND
GND
Analog PLL ground for the system clock generator.
USB Analog PLL ground.
see
Section 5.2,
ROC
USB_VSSPLL
USB_VSS1P3
USB_VSSA1P3
USB_VSSA3P3
USB_VSSOSC
see
Section 5.2,
ROC
Digital core ground for USB PHY.
see
Section 5.2,
ROC
Analog ground for USB PHY [For high speed sensitive analog circuits].
Analog ground for USB PHY.
see
Section 5.2,
ROC
H11
F11
see
Section 5.2,
ROC
Ground for USB oscillator.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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Table 4-19. Ground Signal Descriptions (continued)
TYPE(1)
SIGNAL
NAME
OTHER(3) (4)
DESCRIPTION
(2)
NO.
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
see
Section 5.2,
ROC
USB_VSSREF
G10
GND
GND
When the USB peripheral is not used, the USB_VSSREF signal should be connected
directly to ground (Vss).
B10
B14
Analog ground pins for power management (POR and Bandgap circuits) and 10-bit
SAR ADC
VSSA_ANA
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4.3 Pin Multiplexing
Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. The external bus selection register (EBSR) controls all the pin multiplexing
functions on the device.
This section discusses how to program the external bus selection register (EBSR) to select the desired
peripheral functions and pin muxing. See the individual subsections for muxing details for a specific
muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the peripherals
that are affected.
4.3.1 UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits]
The UHPI, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the PPMODE
bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual pin
functions, see Table 4-20.
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Table 4-20. UHPI, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing
EBSR PPMODE BITS
MODE 3
MODE 0
000
MODE 1
MODE 2
010
MODE 4
100
MODE 5
101
MODE 6
110
PULLUP and PULLDOWN
CONTROL REGISTER BIT
PIN NUMBER
001
(Reset
Default)
011
PUDINHIBR7 (0x1C50) Bit 12
PUDINHIBR3 (0x1C19) Bit 0
PUDINHIBR3 (0x1C19) Bit 1
PUDINHIBR3 (0x1C19) Bit 2
PUDINHIBR3 (0x1C19) Bit 3
PUDINHIBR3 (0x1C19) Bit 4
PUDINHIBR3 (0x1C19) Bit 5
PUDINHIBR3 (0x1C19) Bit 6
PUDINHIBR3 (0x1C19) Bit 7
PUDINHIBR3 (0x1C19) Bit 8
PUDINHIBR3 (0x1C19) Bit 9
PUDINHIBR3 (0x1C19) Bit 10
PUDINHIBR3 (0x1C19) Bit 11
PUDINHIBR3 (0x1C19) Bit 12
PUDINHIBR3 (0x1C19) Bit 13
PUDINHIBR3 (0x1C19) Bit 14
PUDINHIBR3 (0x1C19) Bit 15
PUDINHIBR7 (0x1C50) Bit 8
PUDINHIBR7 (0x1C50) Bit 9
PUDINHIBR7 (0x1C50) Bit 10
PUDINHIBR7 (0x1C50) Bit 11
PUDINHIBR6 (0x1C4F) Bit 7
PUDINHIBR6 (0x1C4F) Bit 8
PUDINHIBR7 (0x1C50) Bit 3
PUDINHIBR7 (0x1C50) Bit 2
PUDINHIBR7 (0x1C50) Bit 4
PUDINHIBR7 (0x1C50) Bit 5
PUDINHIBR7 (0x1C50) Bit 1
N3
P6
N6
P7
N7
N8
P9
N9
UHPI_HINT
UHPI_HD[0]
UHPI_HD[1]
UHPI_HD[2]
UHPI_HD[3]
UHPI_HD[4]
UHPI_HD[5]
UHPI_HD[6]
UHPI_HD[7]
UHPI_HD[8]
UHPI_HD[9]
UHPI_HD[10]
UHPI_HD[11]
UHPI_HD[12]
UHPI_HD[13]
UHPI_HD[14]
UHPI_HD[15]
UHPI_HCNTL0
UHPI_HCNTL1
UHPI_HR_NW
UHPI_HRDY
UHPI_HBE0
UHPI_HBE1
UHPI_HAS
SPI_CLK
SPI_RX
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GP[18]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI_CLK
SPI_CS0
SPI_RX
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2S2_CLK
I2S2_FS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI_CLK
SPI_CLK
SPI_RX
SPI_TX
SPI_TX
GP[12]
GP[12]
GP[13]
GP[13]
GP[14]
GP[14]
GP[15]
GP[15]
GP[16]
GP[16]
P10
N10
P11
N11
P12
N12
P13
N13
P14
P4
GP[17]
GP[17]
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
UART_RTS
UART_CTS
UART_RXD
UART_TXD
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
EM_DQM0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
EM_CS1
EM_SDCKE
I2S2_CLK
I2S2_FS
I2S2_RX
I2S2_DX
I2S3_CLK
I2S3_FS
I2S3_RX
I2S3_DX
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
EM_D1M0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
EM_CS1
EM_SDCKE
GP[19]
SPI_CS0
GP[20]
I2S2_RX
SPI_RX
GP[27]
SPI_TX
I2S2_DX
SPI_TX
GP[28]
I2S3_CLK
I2S3_FS
UART_RTS
UART_CTS
UART_RXD
UART_TXD
Reserved
Reserved
Reserved
Reserved
EM_DQM0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
UART_RTS
UART_CTS
UART_RXD
UART_TXD
Reserved
Reserved
Reserved
Reserved
EM_DQM0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
GP[29]
GP[30]
I2S3_RX
I2S3_DX
Reserved
Reserved
Reserved
Reserved
EM_DQM0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
EM_CS1
EM_SDCKE
GP[31]
Reserved
Reserved
Reserved
Reserved
EM_DQM0
EM_DQM1
EM_SDRAS
EM_SDCAS
EM_CS0
EM_CS1
EM_SDCKE
N4
P5
N5
B5
P1
A6
B4
UHPI_HCS
B3
UHPI_HDS1
UHPI_HDS2
UHPI_HHWIL
A4
EM_CS1
EM_CS1
N2
EM_SDCKE
EM_SDCKE
52
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4.3.2 MMC1, McSPI, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
The MMC1, McSPI, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-21.
Table 4-21. MMC1, McSPI, and GP[11:6] Pin Multiplexing
EBSR SP1MODE BITS
PUDINHIBR1
MODE 0
MODE 1
MODE 2
10
REGISTER
PIN NUMBER
BIT(1)
00
01
(Reset Default)
Bit 8
Bit 9
M13
L14
M14
M12
K14
L13
MMC1_CLK
MMC1_CMD
MMC1_D0
MMC1_D1
MMC1_D2
MMC1_D3
McSPI_CLK
McSPI_CS0
McSPI_SIMO
McSPI_SOMI
McSPI_CS1
McSPI_CS2
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
Bit 10
Bit 11
Bit 12
Bit 13
(1) The pin names with PUDINHIBR1 (1C17h) register bit field references can have the pulldown register enabled or disabled via this
register. Pin 0 on serial port 1 corresponds to bit 8, pin 1 to bit 9, and so on up to pin 5 which corresponds to bit 13.
4.3.3 MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The MMC0, I2S0, McBSP, and GPIO signal muxing is determined by the value of the SP0MODE bit fields
in the External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-22.
Table 4-22. MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing
EBSR SP0MODE BITS
PUDINHIBR1
MODE 0
MODE 1
MODE 2
MODE 3
11
REGISTER
PIN NUMBER
BIT(1)
00
01
10
(Reset Default)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
L10
M11
L9
MMC0_CLK
MMC0_CMD
MMC0_D0
MMC0_D1
MMC0_D2
MMC0_D3
I2S0_CLK
I2S0_FS
I2S0_DX
I2S0_RX
GP[4]
GP[0]
GP[1]
GP[2]
GP[3]
GP[4]
GP[5]
McBSP_CLKX
McBSP_FSX
McBSP_DX
M10
L12
L11
McBSP_DR
McBSP_FSR
McBSP_CLKR_CLKS(2)
GP[5]
(1) The pin names with PUDINHIBR1 (1C17h) register bit field references can have the pulldown register enabled or disabled via this
register. Pin 0 on serial port 0 corresponds to bit 0, pin 1 to bit 1, and so on up to pin 5 which corresponds to bit 5.
(2) Bit 15 of the EBSR register determines this port to be McBSP_CLKR or McBSP_CLKS.
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4.3.4 EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE,
A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register
(EBSR) register. For more details on the actual pin functions, see Table 4-23.
Table 4-23. EM_A[20:16] and GP[26:21] Pin Multiplexing
PUDINHIBR2
REGISTER
BIT(1)
Axx_MODE BIT
PIN NUMBER
0
1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
N1
E2
F2
G2
G4
J3
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
(1) The pin names with PUDINHIBR2 (1C18h) register bit field references can have the pulldown register enabled or disabled via this
register.
54
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4.4 Connections for Unused Signals
Table 4-24 lists the signals that are reserved or are not connected on this device.
Table 4-24. Reserved and No Connects Signal Descriptions
TYPE(1)
SIGNAL
OTHER(3) (4)
DESCRIPTION
(2)
NAME
NO.
Reserved
Reserved. For proper device operation, this pin must be tied directly to VSS.
–
RSV0
C12
I
LDOI
RSV1
RSV2
J10
J11
PWR
PWR
Reserved. For proper device operation, this pin must be tied directly to CVDD
.
.
Reserved. For proper device operation, this pin must be tied directly to CVDD
–
RSV3
RSV4
RSV5
RSV16
D14
C14
C13
D13
I
I
I
I
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
Reserved. For proper device operation, this pin must be tied directly to VSS
.
.
.
.
LDOI
–
LDOI
–
LDOI
–
LDOI
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.
Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.
(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
(4) Specifies the operating I/O supply voltage for each signal
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5 Specifications
For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature.
5.1 Absolute Maximum Ratings
Over Operating Case Temperature Range (Unless Otherwise Noted)(1)
(2)
Supply voltage ranges:
Digital Core (CVDD, CVDDRTC, USB_VDD1P3
)
–0.5 V to 1.7 V
–0.5 V to 4.2 V
I/O, 1.8 V, 2.75 V, 3.3 V (DVDDIO, DVDDEMIF, DVDDRTC) 3.3V
USB supplies USB PHY (USB_VDDOSC, USB_VDDPLL
,
(2)
USB_VDDA3P3
)
LDOI
–0.5 V to 4.2 V
–0.5 V to 1.7 V
–0.5 V to 4.2 V
(2)
Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA
)
Input and Output voltage ranges:
VI I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC or
USB_VDDPLL or USB_VDDA3P3 as supply source
VO I/O, All pins with DVDDIO or DVDDEMIF or USB_VDDOSC or
USB_VDDPLLor USB_VDDA3P3 as supply source
–0.5 V to 4.2 V
RTC_XI and RTC_XO
–0.5 V to 1.7 V
–0.5 V to 4.2 V
–0.5 V to 1.7 V
–0.5 V to 1.7 V
–0.5 V to 1.7 V
0 V to 5.5 V
VI and VO, GPAIN[0]
VI and VO, GPAIN[3:1]
VO, BG_CAP
ANA_LDOO, DSP_LDOO, and USB_LDOO
USB_VBUS Input
Operating case temperature ranges, Tc:
Commercial Temperature (default)
Industrial Temperature
-10°C to 70°C
-40°C to 85°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
56
Specifications
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5.2 Recommended Operating Conditions
MIN
NOM
MAX UNIT
75 MHz
0.998
1.05
1.15
1.43
V
V
Supply voltage, Digital Core
CVDD
175 MHz
1.24
1.3
1.4
Slew rate < 200 µs for full swing
200 MHz
1.33
0.998
1.24
1.24
1.24
1.24
2.97
2.97
2.48
1.65
2.97
2.97
1.8
1.47
CVDD
1.43
1.43
1.43
1.43
3.63
3.63
3.02
1.98
3.63
3.63
3.6
V
V
V
V
V
V
V
V
V
V
V
V
V
CVDDRTC
Supply voltage, RTC and RTC OSC
Supply voltage, Digital USB
32.768 kHz
USB_VDD1P3
USB_VDDA1P3
VDDA_ANA
1.3
1.3
1.3
1.3
3.3
3.3
2.75
1.8
3.3
3.3
Core Supplies
Supply voltage, 1.3 V Analog USB
Supply voltage, 1.3 V SAR and Pwr Mgmt
Supply voltage, System PLL
VDDA_PLL
USB_VDDPLL
Supply voltage, 3.3 V USB PLL
Supply voltage, I/O, 3.3 V
DVDDIO
DVDDEMIF
DVDDRTC
Supply voltage, I/O, 2.75 V
Supply voltage, I/O, 1.8 V
I/O Supplies
USB_VDDOSC
USB_VDDA3P3
LDOI
Supply voltage, I/O, 3.3 V USB OSC
Supply voltage, I/O, 3.3 V Analog USB PHY
Supply voltage, Analog Pwr Mgmt and LDO Inputs
Supply ground, Digital I/O
VSS
VSSRTC
Supply ground, RTC
USB_VSSOSC
USB_VSSPLL
USB_VSSA3P3
USB_VSSA1P3
USB_VSSREF
VSSA_PLL
Supply ground, USB OSC
Supply ground, USB PLL
Supply ground, 3.3 V Analog USB PHY
Supply ground, USB 1.3 V Analog USB PHY
Supply ground, USB Reference Current
Supply ground, System PLL
GND
0
0
0
V
USB_VSS1P3
VSSA_ANA
Supply ground, 1.3 V Digital USB PHY
Supply ground, SAR and Pwr Mgmt
High-level input voltage, 3.3, 2.75, 1.8 V I/O (except
(1)
VIH
0.7 * DVDD
-0.3
DVDD + 0.3
0.3 * DVDD
V
V
(2)
GPAIN[3:0] pins)
Low-level input voltage, 3.3, 2.75, 1.8 V I/O (except
GPAIN[3:0] pins)
(1)
VIL
(2)
Input voltage, GPAIN0 pin(3)
Input voltage, GPAIN[3:1] pins
Commercial
-0.3
-0.3
3.6
V
V
VIN
VDDA_ANA + 0.3
-10
70
°C
(default)
Tc
Operating case temperature
Industrial
-40
0
85
75
°C
1.05 V
DSP Operating Frequency (SYSCLK)
1.3 V
MHz
MHz
MHz
FSYSCLK
0
175
200
1.4 V
0
(1) DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions.
(2) The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DVDDIO is powered
down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0
(low) and logic 1 (high) are not fixed and depend on DVDDIO
(3) The GNDON bit in the SARPINCTRL register should be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the
SARCTRL register, when VIN greater than VDDA_ANA
.
.
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5.3 Electrical Characteristics
5.3.1 Power Consumption
NOTE
Power consumption on this device depends on several operating parameters such as operating
voltage, operating frequency, and temperature. Power consumption also varies by end applications
that determine the overall processor, CPU, and peripheral activity. For more specific power
consumption details, see Estimating Power Consumption on the TMS320C5517 Digital Signal
Processor [literature number SPRABV3]. This document includes a spreadsheet for estimating
power based on parameters that closely resemble the end application to generate a realistic
estimate of power consumption on this device based on use-case and operating conditions.
5.3.2 Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Full speed: USB_DN and
USB_DP(2)
2.8
USB_VDDA3P3
V
High speed: USB_DN and
USB_DP(2)
360
440
mV
V
VOH
High-level output voltage, 3.3,
2.75, 1.8 V I/O (except
GPAIN[3:0] pins)
IO = IOH
IO = IOH
0.8 * DVDD
High-level output voltage,
GPAIN[3:1] pins
0.8 * VDDA_ANA
V
V
Full speed: USB_DN and
USB_DP(2)
0.0
0.3
10
High speed: USB_DN and
USB_DP(2)
–10
mV
Low-level output voltage, 3.3,
2.75, 1.8V I/O (except I2C and
GPAIN[3:0] pins)
VOL
IO = IOL
0.2 * DVDD
V
Low-level output voltage, I2C
pins(3)
VDD > 2 V, IOL = 3 mA
IO = IOL
0
0.4
V
V
Low-level output voltage,
GPAIN[3:0] pins
0.2 * VDDA_ANA
DVDD = 3.3 V
DVDD = 1.8 V
162
122
1.3
mV
mV
V
VHYS
Input hysteresis(4)
USB_LDOO voltage
ANA_LDOO voltage
1.24
1.24
1.24
0.998
250
4
1.43
1.43
1.43
1.15
1.3
V
VLDO
DSP_LDO_V bit in the LDOCNTL register = 1
DSP_LDO_V bit in the LDOCNTL register = 0
LDOI = VMIN
1.3
V
DSP_LDOO voltage
1.05
V
DSP_LDO shutdown current(5)
ANA_LDO shutdown current(5)
USB_LDO shutdown current(5)
mA
mA
mA
µA
ISD
LDOI = VMIN
LDOI = VMIN
25
Input only pin, internal pulldown or pullup disabled
–5
+5
Input current [DC] (except
WAKEUP, I2C, and GPAIN[3:0]
pins)
–59 to
–161
(6)(7)
IILPU
DVDD = 3.3 V with internal pullup enabled(8)
DVDD = 1.8 V with internal pullup enabled(8)
µA
µA
–14 to –44
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).
(3) VDD is the voltage to which the I2C bus pullup resistors are connected.
(4) Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0], RTC_XI, and USB_MXI.
(5) ISD is the amount of current the LDO is ensured to deliver before shutting down to protect itself.
(6) II applies to input-only pins and bidirectional pins. For input-only pins, II indicates the input leakage current. For bidirectional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(7) When CVDD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior
When Core Power (CVDD) is Down.
(8) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
58
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Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
Input only pin, internal pulldown or pullup disabled
DVDD = 3.3 V with internal pulldown enabled(8)
DVDD = 1.8 V with internal pulldown enabled(8)
–5
+5
Input current [DC] (except
WAKEUP, I2C, and GPAIN[3:0]
pins)
(6)(7)
IIHPD
52 to 158
11 to 35
µA
µA
IIH
IIL
/
VI = VSS to DVDD with internal pullups and
pulldowns disabled.
Input current [DC], ALL pins
–5
–4
+5
µA
(7)
All Pins (except USB, EMIF, CLKOUT, and
GPAIN[3:0] pins)
mA
DVDD = 3.3 V
EMIF pins
–6
–5
–6
–4
mA
mA
mA
mA
DVDD = 1.8 V
DVDD = 3.3 V
CLKOUT pin
(7)
IOH
High-level output current [DC]
DVDD = 1.8 V
DVDD = VDDA_ANA
1.3 V,
=
–4
mA
GPAIN[3:1] pins
External Regulator(9)
(GPAIN0 is open-drain
and cannot drive high)
DVDD = VDDA_ANA
1.3 V,
=
–100
µA
Internal Regulator(9)
All Pins (except USB, EMIF, CLKOUT, and
GPAIN[3:0] pins)
+4
mA
DVDD = 3.3 V
EMIF pins
+6
+5
+6
+4
mA
mA
mA
mA
DVDD = 1.8 V
DVDD = 3.3 V
CLKOUT pin
(7)
IOL
Low-level output current [DC]
DVDD = 1.8 V
DVDD = VDDA_ANA
1.3 V, external regulator
=
+4
+4
mA
mA
GPAIN[3:0]
DVDD = VDDA_ANA
1.3 V, internal
regulator(9)
=
All Pins (except USB and GPAIN[3:0])
GPAIN[3:0] pins
–10
–10
+10
+10
2.2
µA
µA
(10)
IOZ
I/O Off-state output current
Supply voltage, I/O, 3.3 V
Supply voltage, I/O, 2.75 V
Supply voltage, I/O, 1.8 V
Supply voltage, I/O, 3.3 V
Supply voltage, I/O, 2.75 V
Supply voltage, I/O, 1.8 V
VDDA_PLL = 1.3 V
mA
mA
mA
mA
mA
mA
Bus Holder pull low current when
CVDD is powered "OFF"
(11)
IOLBH
1.6
0.72
–1.3
–0.97
–0.46
Bus Holder pull high current
when CVDD is powered "OFF"
(11)
IOHBH
0.93
1.23
1.54
Room Temp, Phase detector = 12 MHz, VCO =
125 MHz
VDDA_PLL = 1.3 V
Analog PLL (VDDA_PLL) supply
current
I
mA
Room Temp, Phase detector = 12 MHz, VCO =
175 MHz
VDDA_PLL = 1.3 V
Room Temp, Phase detector = 12 MHz, VCO =
200 MHz
VDDA_ANA = 1.3 V, SAR clock = 2 MHz, Temp
(70 °C)
SAR Analog (VDDA_ANA) supply
current
1
mA
CI
Input capacitance
Output capacitance
4
4
pF
pF
Co
(9) When the ANA_LDO supplies VDDA_ANA, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving
high). The ISD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL
through VDDA_PLL and the SAR through VDDA_ANA
.
(10) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pullups
and pulldowns.
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5.4 Handling Ratings
MIN
–65
0
MAX
150
UNIT
ºC
V
Tstg
Storage temperature range (default)
Electrostatic Discharge Human Body Model (HBM)(2)
>1000
>250
(ESD) Stress Voltage(1)
Charged Device Model (CDM)(3)
0
V
(1) ESD to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device.
(2) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if the necessary
precautions are taken. Pins listed as 1000 V may actually have higher performance.
(3) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
Section 5.5 shows the thermal resistance characteristics for the PBGA–ZCH mechanical package.
5.5 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
°C/W(1)
AIR FLOW
(m/s)(2)
1
2
RTJC
RTJB
Junction-to-case
Junction-to-board
1S0P
1S0P
2S2P
1S0P
2S2P
6.74
14.5
13.8
57.0
33.4
N/A
N/A
3
0.00
RTJA
Junction-to-free air
4
5
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
0.00
0.50
1.00
2.00
3.00
RTJMA
Junction-to-moving air
6
7
8
0.09
13.7
9
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
Junction-to-board
PsiJB
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages.
(2) m/s = meters per second
5.6 Power-On Hours
Over Operating Case Temperature Range (Unless Otherwise Noted)
Device Operating Life
DSP Operating Frequency
(SYSCLK): ≤200 MHz
Commercial
Industrial
-10 to 70°C
-40 to 85°C
100,000
POH(2)
Power-On Hours (POH)(1)
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms
and conditions for TI semiconductor products.
(2) POH = 100,000 when the Maximum Core Supply Voltages are limited to 105% of the Nominal Core Supply Voltages (For details on the
Core Supplies, see Section 5.2, Recommended Operating Conditions).
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5.7 Timing and Switching Characteristics
5.7.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. 3.3-V Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.7.1.1 1.8-V, 2.75-V, and 3.3-V Signal Transition Levels
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 5-2. Rise and Fall Transition Time Voltage Reference Levels
5.7.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
5.7.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routing. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing and decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report [literature number SPRA839]. If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
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5.7.2 Power Supplies
5.7.2.1 Power Considerations
The device provides several means of managing power consumption.
To minimize power consumption, the device divides its circuits into nine main isolated supply domains:
•
•
•
LDOI (LDOs and Bandgap Power Supply)
Analog POR, SAR, and PLL (VDDA_ANA and VDDA_PLL
)
RTC Core (CVDDRTC) — Note: CVDDRTC must always be powered by an external power source. None
of the on-chip LDOs can be used to power CVDDRTC
Digital Core (CVDD
USB Core (USB_VDD1P3 and USB_VDDA1P3
USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL
EMIF I/O (DVDDEMIF
RTC I/O (DVDDRTC
Rest of the I/O (DVDDIO
.
•
•
•
•
•
•
)
)
)
)
)
)
5.7.2.1.1 LDO Configuration
The device includes three Low-Dropout Regulators (LDOs) which can be used to regulate the power
supplies of the SAR ADC and Power Management (ANA_LDO), Digital Core (DSP_LDO), and USB Core
(USB_LDO).
These LDOs are controlled by a combination of pin configuration and register settings. For more detailed
information see the following sections.
5.7.2.1.1.1 LDO Inputs
The LDOI pins (B12, F13, F14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the
bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap
provides accurate voltage and current references to the POR, LDOs, PLL, and SAR; therefore, for proper
device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.
5.7.2.1.1.2 LDO Outputs
The ANA_LDOO pin (A12) is the output of the internal ANA_LDO and can provide regulated 1.3 V power
of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA pin to
provide a regulated 1.3 V to the 10-bit SAR ADC and Power Management Circuits. VDDA_ANA may be
powered by this LDO output, which is recommended, to take advantage of the device's power
management techniques, or by an external power supply. The ANA_LDO cannot be disabled individually
(see Section 5.7.2.1.1.2.1, LDO Control).
The DSP_LDOO pin (E10) is the output of the internal DSP_LDO and provides software-selectable
regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be
connected, on the board, to the CVDD pins. In this configuration, the DSP_LDO_EN pin should be tied to
the board VSS, thus enabling the DSP_LDO.
Optionally, the CVDD pins may be powered by an external power supply. In this configuration the
DSP_LDO_EN pin should be tied (high) to LDOI, disabling DSP_LDO.
The DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the
DSP_LDO_EN pin description in Table 4-17, Regulators and Power Management Signal Descriptions).
When the DSP_LDO is disabled, its output pin is in a high-impedance state.
The LDOs cannot supply power to CVDDRTC, which requires an external power source because CVDDRTC
must always be on for proper operation.
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NOTE
DSP_LDO can only provide a regulated 1.05 V or 1.3 V. When the DSP Core (CVDD
)
requires 1.4 V, an external supply is required to supply 1.4 V to the DSP Core (CVDD) and
the DSP_LDO_EN pin should be tied to LDOI.
The USB_LDOO pin (F12) is the output of the internal USB_LDO and provides regulated 1.3 V, software-
switchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the
board, to the USB_VDD1P3 and USB_VDDA1P3 pins to provide power to portions of the USB. Optionally, the
USB_VDD1P3 and USB_VDDA1P3 may be powered by an external power supply and the USB_LDO can be
left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.
5.7.2.1.1.2.1 LDO Control
All three LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the
LDO_PD bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism,
the only way to re-enable them is by cycling power to the CVDDRTC pin.
ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above.
Otherwise, it is always enabled.
DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in
Section 5.7.2.1.1.2, LDO Outputs. The DSP_LDO can also be dynamically enabled and disabled via the
BG_PD and the LDO_PD mechanism described above. The DSP_LDO can change its output voltage
dynamically by software via the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). The
DSP_LDO output voltage is set to 1.3 V at reset.
USB_LDO: The reset state of the USB_LDO is dependent on the setting of CLK_SEL pin. If CLK_SEL is
high, the USB_LDO is disabled but can be independently and dynamically enabled or disabled by
software via the USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). If CLK_SEL is low, the USB
LDO is enabled at reset and can never be disabled. This is to ensure the USB oscillator has power when
it is the source of the system clock.
Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.
Figure 5-3. RTC Power Management Register (RTCPMGT) [1930h]
15
7
14
13
12
11
10
9
8
0
Reserved
R-0
6
5
4
3
2
1
Reserved
WU_DOUT
R/W-1
WU_DIR
BG_PD
LDO_PD
RTCCLKOUTE
N
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-1. RTCPMGT Register Bit Descriptions
Bit
Name
Description
15:5
Reserved
Reserved. Read-only, writes have no effect.
Wakeup output, active low, open-drain.
0 = WAKEUP pin driven low.
4
WU_DOUT
1 = WAKEUP pin is in high-impedance (Hi-Z).
Wakeup pin direction control.
0 = WAKEUP pin configured as a input.
1 = WAKEUP pin configured as a output.
3
WU_DIR
Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is
configured as an output, is an open-drain that is active low and should be externally pulled-up via a
10-kΩ resistor to DVDDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to
wake the device up from idle modes.
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Table 5-1. RTCPMGT Register Bit Descriptions (continued)
Bit
Name
Description
Bandgap, on-chip LDOs, and the analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR,
and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal
LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD
and LDO_PD power-down mechanisms should not be used.
2
BG_PD
After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-
enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about
100 msec to charge the external 0.1 uF capacitor via the internal 326-kΩ resistor.
0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled.
1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
On-chip LDOs and Analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog
POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to
the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power-
down mechanisms should not be used.
1
0
LDO_PD
After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP
pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a
faster wake-up time with the expense power consumption of the Bandgap reference.
0 = On-chip LDOs and Analog POR are enabled.
1 = On-chip LDOs and Analog POR are disabled (shutdown).
Clockout output enable bit.
RTCCLKOUTEN 0 = Clock output disabled.
1 = Clock output enabled.
Figure 5-4. LDO Control Register (LDOCNTL) [7004h]
15
14
6
13
12
11
10
9
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
R-0
DSP_LDO_V
R/W-0
USB_LDO_EN
R/W-CLK_SEL
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-2. LDOCNTL Register Bit Descriptions
Bit
Name
Description
15:2
Reserved
Reserved. Read-only, writes have no effect.
DSP_LDO voltage select bit.
1
DSP_LDO_V
0 = DSP_LDOO is regulated to 1.3 V.
1 = DSP_LDOO is regulated to 1.05 V.
USB_LDO enable bit.
The reset state of this bit is dependent on the setting of CLK_SEL pin at reset.
If CLK_SEL is high, the USB_LDO is disabled (USB_LEO_EN = 0).
If CLK_SEL is low, the USB LDO is enabled (USB_LDO_EN=1).
0
USB_LDO_EN
0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.
1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.
Note: When CLK_SEL = 0, this bit will not be able to be set to 0 and the USB_LDO will stay
enabled.
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Table 5-3. LDO Controls Matrix
RTCPMGT Register
(0x1930)
LDOCNTL Register
(0x7004)
DSP_LDO_EN
(Pin D12)
CLK_SEL
(Pin C7)
ANA_LDO
DSP_LDO
USB_LDO
BG_PD Bit
LDO_PD Bit
USB_LDO_EN Bit
1
Don't Care
Don't Care
Don't Care
Don't Care
Low
0
0
0
0
1
1
1
1
1
1
OFF
OFF
ON
OFF
OFF
ON
ON
ON
Don't Care
1
Don't Care
0
0
Don't Care
ON
0
0
Don't Care
High
ON
OFF
OFF
OFF
ON
ON
1
Don't Care
Don't Care
Don't Care
Don't Care
Low
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
Don't Care
1
0
0
0
0
Don't Care
0
0
0
0
0
0
1
1
High
ON
OFF
ON
Low
ON
High
ON
OFF
ON
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5.7.2.2 Power-Supply Sequencing
The device includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3), and
several I/O supplies including—DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3
.
Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track
and Slow-Start and Enable features. For more information regarding TI's power management products
and suggested devices to power TI DSPs, visit www.ti.com/processorpower.
The device does not require a specific power-up sequence. However, if the DSP_LDO is disabled
(DSP_LDO_EN = high) and an external regulator supplies power to the CPU Core (CVDD), the external
reset signal (RESET) must be held asserted until all of the supply voltages reach their valid operating
ranges.
Note: the external reset signal on the RESET pin must be held low until all of the power supplies reach
their operating voltage conditions.
The I/O design allows either the core supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3) or the I/O
supplies (DVDDIO, DVDDEMIF, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3) to be powered up for an indefinite
period of time while the other supply is not powered if the following constraints are met:
1. All maximum ratings and recommended operating conditions are satisfied.
2. All warnings about exposure to maximum rated and recommended conditions, particularly junction
temperature are satisfied. These apply to power transitions as well as normal operation.
3. Bus contention while core supplies are powered must be limited to 100 hours over the projected
lifetime of the device.
4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings.
If the USB subsystem is used, the subsystem must be powered up in the following sequence:
1. USB_VDDA1P3 and USB_VDD1P3
2. USB_VDDA3P3
3. USB_VBUS
If the USB subsystem is not used, the following can be powered off:
•
USB Core
–
–
USB_VDD1P3
USB_VDDA1P3
•
USB PHY and I/O Level Supplies
–
–
–
USB_VDDOSC
USB_VDDA3P3
USB_VDDPLL
A supply bus is powered up when the voltage is within the recommended operating range. The supply bus
is powered down when the voltage is below that range, either stable or while in transition.
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5.7.2.3 Digital I/O Behavior When Core Power (CVDD) is Down
With some exceptions (listed below), all digital I/O pins on the device have special features to allow
powering down of the Digital Core Domain (CVDD) without causing I/O contentions or floating inputs at the
pins (see Figure 5-5). The device asserts the internal signal called HHV high when power has been
removed from the Digital Core Domain (CVDD). Asserting the internal HHV signal causes the following
conditions to occur in any order:
•
•
•
All output pin strong drivers to go to the high-impedance (Hi-Z) state
Weak bus holders to be enabled to hold the pin at a valid high or low
The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled
The exception pins that do not have this special feature are:
•
Pins driven by the CVDDRTC Power Domain [This power domain is "Always On"; therefore, the pins
driven by CVDDRTC do not need these special features]:
–
RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
•
•
USB Pins:
–
USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
Pins for the Analog Block:
–
GPAIN[3:0], DSP_LDO_EN, and BG_CAP
DVDD
Y
A
PAD
hhvgz
HHV
GZ
OR
HHV
PI
hhvpi
OR
HHV
Figure 5-5. Bus Holder I/O Circuit
NOTE
Figure 5-5 shows both a pullup and pulldown but pins only have one, not both.
PI = Pullup and Pulldown Inhibit
GZ = Output Enable (active low)
HHV = Described in Section 5.7.2.3
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5.7.2.4 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the device, the PC board should include separate power planes for core, I/O,
VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with
high–quality low–ESL and ESR capacitors.
5.7.2.5 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as
possible to the device. These caps need to be no more than 1.25 cm maximum distance from the device
power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated
from a yield and manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest
available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 10 µF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
The recommended decoupling capacitance for the DSP core supplies should be 1 µF in parallel with 0.01-
µF capacitor per supply pin.
5.7.2.6 LDO Input Decoupling
The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.
5.7.2.7 LDO Output Decoupling
The LDO circuits implement a voltage feedback control system which has been designed to optimize gain
and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO
outputs. For proper device operation, the following external decoupling capacitors should be used when
the on-chip LDOs are enabled:
•
•
•
ANA_LDOO– 1µF
DSP_LDOO – 5µF ~ 10µF
USB_LDOO – 1µF ~ 2µF
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5.7.3 Reset
The device has two main types of reset: hardware reset and software reset.
Hardware reset is responsible for initializing all key states of the device. The hardware reset occurs
whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit deasserts an
internal signal called POWERGOOD. The device's internal POR is a voltage comparator that monitors the
DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled
externally by the DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a
minimum threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is
high), the internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is
immediately set high. The RESET pin and the POWERGOOD signal are internally combined with a logical
AND gate to produce an (active low) hardware reset (see Figure 5-6, Power-On Reset Timing
Requirements and Figure 5-7, Reset Timing Requirements).
There are two types of software reset: the CPU's software reset instruction and the software control of the
peripheral reset signals. For more information on the CPU's software reset instruction, see the C55x CPU
3.0 CPU Reference Guide [literature number: SWPU073]. In all the device documentation, all references
to "reset" refer to hardware reset. Any references to software reset will explicitly state software reset.
The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC
core. This POR monitors the voltage of CVDDRTC and resets the RTC registers when power is first applied
to the RTC core.
5.7.3.1 Power-On Reset (POR) Circuits
The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the
rest of the chip (MAIN POR).
5.7.3.1.1 RTC Power-On Reset (POR)
The RTC POR ensures that the flip-flops in the CVDDRTC power domain have an initial state upon
powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC
time registers need to be initialized with the current time and date when power is first applied.
5.7.3.1.2 Main Power-On Reset (POR)
The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific
voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the
DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions
are satisfied:
•
•
•
LDOI is powered and the bandgap is active for at least approximately 8 ms
VDD_ANA is powered for at least approximately 4 ms
DSP_LDOO is above a threshold of approximately 950 mV (see the following Note:)
Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after
POWERGOOD signal is set high.
Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal
is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's
global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global
reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,
see Section 6.4.1, Boot Sequence.
When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is
de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole
source of hardware reset.
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5.7.3.1.3 Reset Pin (RESET)
The device can receive an external reset signal on the RESET pin. As specified above in
Section 5.7.3.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD
signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the
hardware reset to the chip. The RESET pin may be tied high and the MAIN POR can provide the
hardware reset in case DSP_LDO is enabled (DSP_LDO_EN = 0), but an external hardware reset must
be provided via the RESET pin when the DSP_LDO is disabled (DSP_LDO_EN = 1).
Once the hardware reset is applied, the system clock generator is enabled and the DSP starts the boot
sequence. For more information on the boot sequence, see Section 6.4.1, Boot Sequence.
5.7.3.2 Pin Behavior at Reset
All pins are in Hi-Z state when RESET is applied, and pins are held in Hi-Z state for the first two clock
cycles after RESET is de-asserted (set to high).
During normal operation, pins are controlled by the respective peripheral selected in the External Bus
Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins
changes and is categorized as follows:
Z, High Group: EM_CS2, EM_CS3, EM_CS4, EM_CS5, EM_DQM0/UHPI_HBE0,
EM_DQM1/UHPI_HBE1, EM_OE, EM_SDCAS/UHPI_HCS, EM_SDRAS/UHPI_HAS, EM_WE, XF
•
•
•
Z, Low Group: SPI_CLK/UHPI_HINT, I2S2_DX/UHPI_HD[11]/GP[27]/SPI_TX, EM_R/W,
MMC0_CLK/I2S0_CLK/GP[0]/McBSP_CLKX, MMC1_CLK/McSPI_CLK/GP[6], EM_SDCLK
Z Group: EM_D[0:15], GP[21:26]/EM_A[15:20], GP[12:17]/UHPI_HD[2:7], EM_WAIT2, EM_WAIT3,
EM_WAIT4, EM_WAIT5, EMU0, EMU1, SCL, SDA, TDO, USB_MXO, WAKEUP, RTC_CLKOUT
I2S2_CLK/UHPI_HD[8]/GP[18]/SPI_CLK, I2S2_FS/UHPI_HD[9]/GP[19]/SPI_CS0,
I2S2_RX/UHPI_HD[10]/GP[20]/SPI_RX
MMC0_CMD/I2S0_FS/GP[1]/McBSP_FSX, MMC0_D0/I2S0_DX/GP[2]/McBSP_DX,
MMC0_D1/I2S0_RX/GP[3]/McBSP_DR, MMC0_D2/GP[4]/McBSP_FSR,
MMC0_D3/GP[5]/McBSP_CLKR_CLKS
MMC1_CMD/McSPI_CS0/GP[7], MMC1_D0/McSPI_SIMO/GP[8], MMC1_D1/McSPI_SOMI/GP[9],
MMC1_D2/McSPI_CS1/GP[10], MMC1_D3/McSPI_CS2/GP[11]
UART_CTS/UHPI_HD[13]/GP[29]/I2S3_FS, UART_RXD/UHPI_HD[14]/GP[30]/I2S3_RX,
SPI_TX/UHPI_HD[1], SPI_RX/UHPI_HD[0]
Z, CLKOUT Group: CLKOUT
•
•
•
•
•
Z Group - Analog: GPAIN0, GPAIN1, GPAIN2, GPAIN3
Z, SYNCH 0→1 Group: EM_SDCKE/UHPI_HHWIL
Z, SYNCH 1→0 Group: EM_CS0/UHPI_HDS1, EM_CS1/UHPI_HDS2
Z, SYNCH22 0→1 Group: SPI_CS0/UHPI_HCNTL0, SPI_CS1/UHPI_HCNTL1,
SPI_CS2/UHPI_HR_NW, SPI_CS3/UHPI_HRDY
Z, SYNCH X→1 Group: EM_BA[0], EM_BA[1], UART_RTS/UHPI_HD[12]/GP[28]/I2S3_CLK,
UART_TXD/UHPI_HD[15]/GP[31]/I2S3_DX
•
•
Z, SYNCH X→0 Group: EM_A[0:10], EM_A[11]/(ALE), EM_A[12]/(CLE), EM_A[13], EM_A[14]
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5.7.3.3 Reset Electrical Data and Timing
Table 5-4. Timing Requirements for Reset(1) (see Figure 5-6 and Figure 5-7)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO.
UNIT
MIN
MAX
MIN
MAX
1
tw(RSTL)
Pulse duration, RESET low
3P
3P
ns
(1) P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator
is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
For a description of IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual
[literature number SPRUH16].
POWERGOOD
(internal)
RESETN
(POWERGOOD &&
RESETN)
(internal)
1
2
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
Z
Z
Z
Z
Z
Z
Z,Low Group
Z,High Group
Z Group
Z,Synch X->0
Group
Z,Synch X->1
Group
Z,Synch 0->1
Group
Z
Z
Z
Z,Synch 1->0
Group
Z,Synch22 0->1
Group
CLKOUT
22 clocks
65535 clocks if CLK_SEL=1,
131071 clocks if CLK_SEL=0
Figure 5-6. Reset Timing When DSP_LDO_EN = 0
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POWERGOOD
(internal)
RESETN
(POWERGOOD &&
RESETN)
(internal)
1
2
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
Z
Z,Low Group
Z,High Group
Z
Z
Z
Z
Z
Z Group
Z,Synch X->0
Group
Z,Synch X->1
Group
Z,Synch 0->1
Group
Z
Z
Z
Z,Synch 1->0
Group
Z,Synch22 0->1
Group
CLKOUT
22 clocks
65535 clocks if CLK_SEL=1,
131071 clocks if CLK_SEL=0
Figure 5-7. Reset Timing When DSP_LDO_EN = 1
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5.7.3.4 Configurations at Reset
Some device configurations are determined at reset. The following subsections give more details.
5.7.3.4.1 Device and Peripheral Configurations at Device Reset
Table 5-5 summarizes the device boot and configuration pins that are required to be statically tied high,
tied low, or left unconnected during device operation. For proper device operation, a device reset should
be initiated after changing any of these pin functions.
Table 5-5. Default Functions Affected by Device Configuration Pins
CONFIGURATION PINS
SIGNAL NO.
IPU and IPD
FUNCTIONAL DESCRIPTION
DSP_LDO enable input.
DSP_LDO_EN
D12
–
This signal is not intended to be dynamically
switched.
0 = DSP_LDO is enabled. The internal DSP LDO
is enabled to regulate power on the DSP_LDOO
pin at either 1.3 V or 1.05 V according to the
LDO_DSP_V bit in the LDOCNTL register, see
Figure 5-4). At power-on-reset, the internal POR
monitors the DSP_LDOO pin voltage and
generates the internal POWERGOOD signal
when the DSP_LDO voltage is above a minimum
threshold voltage. The internal device reset is
generated by the AND of POWERGOOD and the
RESET pin.
1 = DSP_LDO is disabled and the DSP_LDOO
pin is in high-impedance (Hi-Z). The internal
voltage monitoring on the DSP_LDOO is
bypassed and the internal POWERGOOD signal
is immediately set high. The RESET pin (D6) will
act as the sole reset source for the device. If an
external power supply is used to provide power to
CVDD, then DSP_LDO_EN should be tied to
LDOI, DSP_LDOO should be left unconnected,
and the RESET pin must be asserted
appropriately for device initialization after
powerup.
Note: to pullup this pin, connect it to the same
supply as LDOI pins.
CLK_SEL
C7
–
Clock input select.
0 = The on-chip USB oscillator is enabled and
drives the system clock generator. Also, the USB
LDOO is enabled at reset (USB_LDO_EN=1). In
this configuration, CLKIN must be tied to GND.
1 = CLKIN drives the system clock generator.
The on-chip USB oscillator and USB_LDO are
disabled at reset (USB_LDO_EN=0) but can be
enabled by software
This pin is not allowed to change during device
operation; it must be tied to DVDDIO or GND at
the board.
For proper device operation, external pullup and pulldown resistors may be required on these device
configuration pins. For discussion on situations where external pullup and pulldown resistors are required,
see Section 5.7.20.1.1, Pullup and Pulldown Resistors.
This device also has RESERVED pins that need to be configured correctly for proper device operation
(statically tied high, tied low, or left unconnected at all times). For more details on these pins, see Table 4-
24, Reserved and No Connects Signal Descriptions.
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5.7.3.4.2 BootMode Implementation and Requirements
The EM_A[20:15]/GP[26:21] pins are used to latch the bootmode, as defined in Table 6-34. These pins
are defined as GPIO function at reset and they are in input state. Therefore these pins can be driven to
the desired bootmode terminations at reset. Approximately 10 system cycles after the rising edge of the
RESET pin, the state on these pins will be latched into registers readable by the DSP at IO-space address
0x1C5A.
As the bootloader code starts executing, it reads the latched value in the bootmode register and uses that
value to determine from which peripheral or method to boot. In any case where the ASYNC modes
(except for NAND) are used as the source data for bootloading (for example, bootload from external NOR
flash to internal memory), the bootloader routine in ROM will change the EM_A[20:15] or GP[26:21] pins
from GPIO mode to EMIF mode by writing to the EBSR (0x1C00). When this occurs, no signal contentions
must be on the EM_A[20:15] or GP[26:21] pins. Passive static terminations by external pullup or pulldown
resistors should also be considered.
Note: Bootloading directly to external peripherals on the EMIF is not supported because the EMIF clock is
turned off before jumping to bootloaded code.
The bootloader must enable the EMIF function on these pins in order to increase the address reach from
15-bits (EM_A[14:0] 32 kW) to the full 21-bits (EM_A[20:0] 2 MW). The bootloader does not have to
enable the EMIF mode on the EM_A[20:15] or GP[26:21] pins for the following external memory types:
NAND: Uses the EM_D[15:0] pins for both address and data and command signaling.
SDRAM: Uses column and row addressing using no more than 11 bits of EM_A pins
The following image contains two BootMode termination scenarios. Other options are also possible.
74
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1.8V/2.75V/3.3V
DVDD_EMIF
A[20]
A[19]
EM_A[20]/GP[26]
EM_A[19]/GP[25]
EM_A[18]/GP[24]
EM_A[17]/GP[23]
EM_A[16]/GP[22]
EM_A[15]/GP[21]
EM_[14:0]
A[18]
NOR
Flash
A[17]
DSP
A[16]
A[15]
A[14:0]
XF
VSS
1.8V/2.75V/3.3V
DVDD_EMIF
A[20]
A[19]
EM_A[20]/GP[26]
EM_A[19]/GP[25]
EM_A[18]/GP[24]
EM_A[17]/GP[23]
EM_A[16]/GP[22]
EM_A[15]/GP[21]
EM_[14:0]
A[18]
NOR
Flash
A[17]
DSP
A[16]
A[15]
A[14:0]
XF
VSS
OE
External control logic
Figure 5-8. BootMode Termination Scenarios
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1
2
3 4 6 7 8 9 10
5
System Clock
RESET
Bootmode
[5:0]
latched from
GP[26:21]
Hi-Z
Hi-Z
XF
CLKOUT
EM_A[20:15]/
GP[26:21]
GPIO input mode
(externally driven with desired bootmode)
EMIF A[20:15] (output mode)
Hi-Z
time allowed fro external
device to get off the bus
65535 clocks if CLK_SEL=1,
131071 clocks id CLK_SEL=0
A. DSP changes the pin mode to EMIF Address (outputs) only if needed for the selected bootmode.
Figure 5-9. BootMode Latching
5.7.3.5 Configurations After Reset
The following sections provide details on configuring the device after reset. Multiplexed pin functions are
selected by software after reset. For more details on multiplexed pin function control, see Section 4.3, Pin
Multiplexing.
5.7.3.5.1 External Bus Selection Register (EBSR)
The External Bus Selection Register (EBSR) determines the mapping of the UHPI, I2S2, I2S3, UART,
SPI, McBSP, McSPI, and GPIO signals to 28 signals of the external parallel port pins. The EBSR also
determines the mapping of the I2S, McBSP, McSPI, GPIO, or MMC and SD ports to serial port 0 pins and
serial port 1 pins. The EBSR register is located at IO-space 0x1C00. Once the bit fields of this register are
changed, the routing of the signals takes place on the next CPU clock cycle.
In addition, the EBSR controls the function of the upper bits of the EMIF address bus. Pins EM_A[20:15]
or GP[26:21] can be individually configured as GPIO pins through the Axx_MODE bits. When Axx_MODE
= 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin has EMIF
address output functionality.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register
has been modified, you must reset the peripherals before using them through the Peripheral Software
Reset Counter Register.
Figure 5-10. External Bus Selection Register (EBSR) [1C00h]
15
14
6
13
12
11
10
9
8
McBSP_CLKS
Selection
PPMODE
SP1MODE
R/W-00
SP0MODE
R/W-00
R/W-0
7
R/W-001
5
4
3
2
1
0
Reserved
R-0
A20_MODE
R/W-1
A19_MODE
R/W-1
A18_MODE
R/W-1
A17_MODE
R/W-1
A16_MODE
R/W-1
A15_MODE
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 5-6. EBSR Register Field Descriptions
Bit
Field
Description
McBSP_CLKS Selection
McBSP_CLKS
Selection
0 = McBSP_CLKR signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when
SP0MODE=3
15
1 = McBSP_CLKS signal is routed to MMC0_D3/GP[5]/McBSPCLKR_CLKS (L11) when
SP0MODE=3
Parallel Port Mode Control Bits. These bits control the pin multiplexing of the UHPI, SPI, UART,
I2S2, I2S3, and GP[31:27, 20:12] pins on the parallel port. For more details, see Table 4-20.
000 = Mode 0 (16-bit UHPI bus). All 28 signals of the UHPI bus module are routed to the 28
external signals of the parallel port. Note: SDRAM control signals are multiplexed with UHPI bus
control signals. In this mode, UHPI bus signals are routed to the control ports, so SDRAM cannot
be accessible.
001 = Mode 1 (SPI, GPIO, UART, I2S2, and SDRAM). 7 signals of the SPI module, 6 GPIO
signals, 4 signals of the UART module, 4 signals of the I2S2 module, and 7 SDRAM control signals
are routed to the 28 external signals of the parallel port.
010 = Mode 2 (GPIO and SDRAM). 8 GPIO and 7 SDRAM control signals are routed to the 28
external signals of the parallel port.
14:12
PPMODE
011 = Mode 3 (SPI, I2S3, and SDRAM). 4 signals of the SPI module, 4 signals of the I2S3 module,
and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
100 = Mode 4 (I2S2, UART, and SDRAM). 4 signals of the I2S2 module, 4 signals of the UART
module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
101 = Mode 5 (SPI, UART, and SDRAM). 4 signals of the SPI module, 4 signals of the UART
module, and 7 SDRAM control signals are routed to the 28 external signals of the parallel port.
110 = Mode 6 (SPI, I2S2, I2S3, GPIO, and SDRAM). 7 signals of the SPI module, 4 signals of the
I2S2 module, 4 signals of the I2S3 module, 6 GPIO, and 7 SDRAM control signals are routed to the
28 external signals of the parallel port.
111 = Reserved.
Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the MMC1, McSPI, and
GPIO pins on serial port 1. For more details, see Table 4-21.
00 = Mode 0 (MMC1 and SD1). All 6 signals of the MMC1 and SD1 module are routed to the 6
external signals of the serial port 1.
11:10
SP1MODE
01 = Mode 1 (McSPI). 6 signals of the McSPI module signals are routed to the 6 external signals of
the serial port 1.
10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial
port 1.
11 = Reserved.
Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the MMC0, I2S0, McBSP,
and GPIO pins on serial port 0. For more details, see Section 4.3.3.
00 = Mode 0 (MMC0 and SD0). All 6 signals of the MMC0 and SD0 module are routed to the 6
external signals of the serial port 0.
9:8
7-6
SP0MODE
Reserved
01 = Mode 1 (I2S0 and GP[5:4]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to
the 6 external signals of the serial port 0.
10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial
port 0.
11 = Mode 3 (McBSP). 6 signals of the McBSP module are routed to the 6 external signal port 0.
Reserved. Read-only, writes have no effect.
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Table 5-6. EBSR Register Field Descriptions (continued)
Bit
Field
Description
A20 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 20 (EM_A[20]) and
general-purpose input/output pin 26 (GP[26]) pin functions.
0 = Pin function is EMIF address pin 20 (EM_A[20]).
5
A20_MODE
1 = Pin function is general-purpose input/output pin 26 (GP[26]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
A19 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 19 (EM_A[19]) and
general-purpose input/output pin 25 (GP[25]) pin functions.
0 = Pin function is EMIF address pin 19 (EM_A[19]).
4
A19_MODE
1 = Pin function is general-purpose input/output pin 25 (GP[25]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
A18 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 18 (EM_A[18]) and
general-purpose input/output pin 24 (GP[24]) pin functions.
0 = Pin function is EMIF address pin 18 (EM_A[18]).
3
A18_MODE
1 = Pin function is general-purpose input/output pin 24 (GP[24]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
A17 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 17 (EM_A[17]) and
general-purpose input/output pin 23 (GP[23]) pin functions. For more details, see Table 4-22,
MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing.
0 = Pin function is EMIF address pin 17 (EM_A[17]).
2
A17_MODE
A16_MODE
A15_MODE
1 = Pin function is general-purpose input/output pin 23 (GP[23]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
A16 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 16 (EM_A[16]) and
general-purpose input/output pin 22 (GP[22]) pin functions. For more details, see Table 4-22,
MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing.
0 = Pin function is EMIF address pin 16 (EM_A[16]).
1
1 = Pin function is general-purpose input/output pin 22 (GP[22]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
A15 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 15 (EM_A[15]) and
general-purpose input/output pin 21 (GP[21]) pin functions. For more details, see Table 4-22,
MMC0, I2S0, McBSP, and GP[5:0] Pin Multiplexing.
0 = Pin function is EMIF address pin 15 (EM_A[15]).
0
1 = Pin function is general-purpose input/output pin 21 (GP[21]).
This is the default mode at reset and the pin is configured as an Input.
Approximately 10 cycles after the rising edge of RESET, the state on this pin is latched into the
BootMode register to specify the boot method.
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5.7.3.5.2 LDO Control Register [7004h]
When the DSP_LDO is enabled by the DSP_LDO_EN pin being tied low, the DSP_LDOO voltage is set
by the DSP_LDO_V bit in this register. The reset state of this bit causes the DSP_LDOO output to be set
to 1.3 V at boot. The DSP_LDOO voltage can be programmed to be either 1.05 V or 1.3 V via the
DSP_LDO_V bit (bit 1) in the LDO Control Register (LDOCNTL).
At reset, the USB_LDO state is dependent on the CLK_SEL pin. At reset, if CLK_SEL is high
(CLK_SEL=1), the USB LDO is disabled but can be enabled via the USBLDOEN bit (bit 0) in the
LDOCNTL register. If CLK_SEL is low (CLK_SEL=0), the USB LDO is enabled and cannot be disabled.
For more detailed information on the LDOs, see Section 5.7.2.1.1, LDO Configuration.
5.7.3.5.3 EMIF and USB System Control Registers (ESCR and USBSCR) [1C33h and 1C32h]
After reset, by default, the CPU performs 16-bit accesses to the EMIF and USB registers and data space.
To perform 8-bit accesses to the EMIF data space, the user must set the BYTEMODE bits to 01b for the
"high byte" or 10b for the "low byte" in the EMIF System Control Register (ESCR). Similarly, the
BYTEMODE bits in the USB System Control Register (USBSCR) must also be configured for byte access.
5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
After hardware reset, the DSP executes the on-chip bootloader from ROM. Depending on the BootMode
used, the bootloader may leave the PCGCR1 and the PCGCR2 registers in various states. This is also
true of the ICR and the ISR registers.
Programmers should always verify the state of these registers and appropriately set them. Their states
after boot loading are not determined by their reset conditions.
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5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7) [1C17h, 1C18h, 1C19h,
1C4Ch, 1C4Dh, 1C4Fh, and 1C50h, respectively]
Each internal pullup and pulldown (IPU and IPD) resistor on the device can be individually controlled
through the IPU and IPD registers (PUDINHIBR1 [1C17h] , PUDINHIBR2 [1C18h], PUDINHIBR3 [1C19h],
PUDINHIBR4 [1C4Ch], PUDINHIBR5 [1C4Dh], PUDINHIBR6 [1C4Fh], and PUDINHIBR7 [1C50h]). To
minimize power consumption, internal pullup or pulldown resistors should be disabled in the presence of
an external pullup or pulldown resistor or external driver. Most internal pullups and pulldowns are enabled
at reset to help ensure no pins are left floating. Section 5.7.20.1.1, Pullup and Pulldown Resistors,
describes other situations in which an pullup and pulldown resistors are required.
When CVDD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-
holder will be enabled. For more detailed information, see Section 5.7.2.3, Digital I/O Behavior When Core
Power (CVDD) is Down.
5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]
To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF
and CLKOUT output pins. The output slew rate control register (OSRCR) is used to set a subset of the
device I/O pins, namely CLKOUT and EMIF pins, to either fast or slow slew rate. The slew rate feature is
implemented by staging and delaying turn-on times of the parallel p-channel drive transistors and parallel
n-channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but
ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive
strength is ultimately the same. The slower slew rate control can be used for power savings and has the
greatest effect at lower DVDDIO and DVDDEMIF voltages.
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5.7.4 Clock Specifications
5.7.4.1 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
5.7.4.2 Clock Considerations
The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the on-chip USB oscillator. The selection of the input reference clock is based on the state of the
CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot change
dynamically after reset.
If CLK_SEL=0 at reset, the on-chip USB oscillator is selected as the source of the system clock generator
and the USB PLL as well. In this configuration, the on-chip USB oscillator cannot be turned off.
If CLK_SEL=1 at reset, the external clock via the CLKIN pin will be used as the source of the system clock
generator and the on-chip USB oscillator is used only for the USB PLL input. In this configuration, the on-
chip USB oscillator can be turned off if the USB peripheral is not being used.
In addition, the DSP requires a reference clock for the real-time clock (RTC). The RTC reference clock is
generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the
RTC_XI and RTC_XO pins.
The 32.768-kHz crystal can be disabled if the RTC peripheral is not being used. However, when the RTC
oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range
1900h – 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT)
which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin
to CVDDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 5.7.4.3.3, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.
5.7.4.2.1 Clock Configurations After Device Reset
After reset, the on-chip Bootloader programs the system clock generator based on the value of
EM_A[20:15] or GP[26:21], which are latched into the BootMode[5:0] bits in the BootMode register
([1C34h]) at reset. (See Section 6.4, Boot Modes, for details.)
5.7.4.2.1.1 Device Clock Frequency
After the boot process is complete, the user is allowed to re-program the system clock generator to bring
the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not).
The user must adhere to various clock requirements when programming the system clock generator. For
more information, see Section 5.7.4.3, Clock PLLs.
Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process.
However, this feature must not be used to change the output frequency of the system clock generator
during the boot process. The bootloader also uses Timer0 to calculate the settling time of BG_CAP until
executing bootloader code. The bootloader register modification feature must not modify the Timer0
registers.
5.7.4.2.1.2 Peripheral Clock State
The clock and reset state of each of peripheral is controlled through a set of system registers. The
peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable
peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control
register (PRCR) are used to assert and de-assert peripheral reset signals.
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After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the
bootloader chooses a peripheral or method to boot from based on the value of BootMode[5:0] bits in the
BootMode register ([1C34h]) and queries the peripheral to determine if it can boot from that peripheral. At
that time, the individual peripheral clock will be enabled for the query and then disabled again when the
bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all
peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled.
5.7.4.2.1.3 USB Oscillator Control
At reset, if CLK_SEL = 0, the on-chip USB oscillator is enabled and is used as the clock source of the
system clock generator. Since the USB oscillator is the system's clock source, it is not possible to disable
the USB oscillator when CLK_SEL = 0.
When CLK_SEL = 1, the USB Oscillator is disabled at reset but can be enabled or disabled by writing to
the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and
USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before
proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 µs, with a 10
ms maximum. (Note: The startup time is highly dependent on the ESR and capacitive load on the crystal.)
5.7.4.3 PLLs
The device DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA,
and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the USB on-chip
oscillator (as specified through the CLK_SEL pin).
5.7.4.3.1 PLL Device-Specific Information
There is a minimum and maximum operating frequency for CLKIN, PLLIN, and the system clock
(SYSCLK). The system clock generator must be configured not to exceed any of these constraints
documented in this section (certain combinations of external clock inputs, internal dividers, and PLL
multiply ratios are not supported).
Table 5-7. PLL Clock Frequency Ranges
CVDD = 1.05 V
VDDA_PLL = 1.3 V
CVDD = 1.3 V
VDDA_PLL = 1.3 V
CVDD = 1.4 V
VDDA_PLL = 1.3 V
CLOCK SIGNAL
NAME
UNIT
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
11.2896,
12.0,
12.288,
16.8,
or
11.2896,
12.0,
12.288,
16.8,
or
11.2896,
12.0,
12.288,
16.8,
or
CLKIN(1)
MHz
19.2
19.2
19.2
PLLIN
1.7
60
6.79
120
1.7
60
6.79
120
1.7
60
6.79 MHz
120
PLLOUT
VCO Output(2)
(before output
divider OD and
OD2)
125
0
625
125
0
625
125
0
625 MHz
200 MHz
SYSCLK
75
4
175
4
PLL_LOCKTIME
4
ms
(1) These CLKIN values are used when the CLK_SEL pin = 1.
(2) To use less PLL power, ensure VCO max is close to the SYSCLK max.
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The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time
needed for the PLL to complete its phase-locking sequence.
5.7.4.3.2 Clock PLL Considerations With External Clock Sources
If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single
clean power supply should power both the device and the external clock oscillator circuit. The minimum
CLKIN rise and fall times should also be observed. For the input clock timing requirements, see
Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
Rise and fall times, duty cycles (high and low pulse durations), and the load capacitance of the external
clock source must meet the device requirements in this data manual (see Section 5.3.2, Electrical
Characteristics, and Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
The device DSP includes two options to provide an external clock input to the system clock generator:
•
Use the on-chip USB oscillator with an external 12-MHz crystal connected to the USB_MXO and
USB_MXI pins.
•
Use an external LVCMOS clock input fed into the CLKIN pin that operates at the same voltage as the
DVDDIO supply (1.8-, 2.75-, or 3.3-V).
The CLK_SEL pin determines which input is used as the clock source for the system clock generator. For
more details, see Section 5.7.3.4.1.
If CLK_SEL = 0 at reset, the on-chip USB oscillator is used as the source of the system clock generator
and the USB PLL as well.
If CLK_SEL= 1 at reset, the external LVCMOS clock input fed into the CLKIN pin will be used as the
source of the system clock generator and the on-chip USB oscillator is used only for the USB PLL source.
In this configuration, the on-chip USB oscillator can be turned off if the USB peripheral is not being used.
Additionally, the DSP requires a reference clock for the on-chip real time clock (RTC). The RTC reference
clock is generated using a dedicated on-chip oscillator with a 32.768-kHz external crystal connected to the
RTC_XI and RTC_XO pins. The crystal for the RTC oscillator is not required if the RTC is not used,
however the RTC must still be powered by an external power source. None of the on-chip LDOs can
power CVDDRTC. The RTC registers starting at I/O address 1900h will not be accessible without an RTC
clock. This includes the RTC Power Management Register which provides control to the on-chip LDOs
and WAKEUP and RTC_CLKOUT pins. Section 5.7.4.3.3.2, Real-Time Clock (RTC) On-Chip Oscillator
With External Crystal, provides more details on using the RTC on-chip oscillator with an external crystal.
5.7.4.3.3.1 USB On-Chip Oscillator With External Crystal
The USB on-chip oscillator requires an external 12-MHz crystal connected across the USB_MXI and
USB_MXO pins, along with two load capacitors, as shown in Figure 5-11. The external crystal load
capacitors must be connected only to the USB oscillator ground pin (USB_VSSOSC). Do not connect to
board ground (VSS). The USB_VDDOSC pin can be connected to the same power supply as USB_VDDA3P3
.
If the external clock input via the CLKIN pin is used as the source of the system clock generator
(CLK_SEL =1 at reset) and the USB peripheral is not being used, then the on-chip USB oscillator can be
permanently disabled. To permanently disable the USB oscillator, connect the USB_MXI pin to ground
(VSS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and
USB_VSSOSC) should also be connected to ground, as shown in Figure 5-12.
When using an external 12-MHz oscillator, the external oscillator clock signal should be connected to the
USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see
Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the
USB_VSSOSC signal is connected to board ground (VSS).
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USB_MXI
USB_MXO
USB_VSSOSC USB_VDDOSC
VSS
USB_VDDA3P3
Crystal
12 MHz
C1
C2
3.3 V
3.3 V
Figure 5-11. 12-MHz USB Oscillator
USB_MXI
USB_MXO
USB_VSSOSC USB_VDDOSC
VSS
USB_VDDA3P3
Figure 5-12. Connections when USB Oscillator is Permanently Disabled
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-8. The load capacitors, C1 and C2 are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
Table 5-8. Input Requirements for Crystal on the 12-MHz USB Oscillator
PARAMETER
MIN
NOM
0.100
12
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency of 12 MHz)(1)
10
Oscillation frequency
ESR
MHz
kΩ
100
±100
5
(2)
Frequency stability
ppm
pF
Maximum shunt capacitance
Maximum crystal drive
330
µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
(2) If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.
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5.7.4.3.3.2 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
The on-chip RTC oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and
RTC_XO pins, along with two load capacitors, as shown in Figure 5-13. The external crystal load
capacitors must be connected only to the RTC oscillator ground pin (VSSRTC). Do not connect to board
ground (VSS). Position the VSS lead on the board between RTC_XI and RTC_XO as a shield to reduce
direct capacitance between RTC_XI and RTC_XO leads on the board. The CVDDRTC pin can be connected
to the same power supply as CVDD, or may be connected to a different supply that meets the
recommended operating conditions (see Section 5.2, Recommended Operating Conditions), if desired.
RTC_XI
RTC_XO
VSSRTC
CVDDRTC
VSS
CVDD
Crystal
32.768 kHz
C1
C2
0.998-CVDD
V
1.05/1.3/1.4 V
Figure 5-13. 32.768-kHz RTC Oscillator
The RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and RTC_XO to ground
(VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will
not be accessible. This includes the RTC Power Management Register which provides control to the on-
chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered even if the RTC
oscillator is disabled.
RTC_XI
CVDDRTC
RTC_XO
VSS
V SSRTC
0.998–CVDD
V
Figure 5-14. Connections when RTC Oscillator is Permanently Disabled
The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-9. The load capacitors, C1 and C2, are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (RTC_XI and RTC_XO) and to the VSSRTC pin.
C C
1
2
C
=
L
C
+ C
2
(
)
1
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Table 5-9. Input Requirements for Crystal on the 32.768-kHz RTC Oscillator
PARAMETER
MIN
NOM
MAX
UNIT
sec
kHz
kΩ
Start-up time (from power up until oscillating at stable frequency of 32.768-kHz)(1)
0.2
2
Oscillation frequency
ESR
32.768
100
1.6
1.0
Maximum shunt capacitance
Maximum crystal drive
pF
µW
(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.
5.7.4.3.3.3 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
Note: If CLKIN is not used, the pin must be tied low.
A LVCMOS-compatible clock can be fed into the CLKIN pin for use by the DSP system clock generator.
The external connections are shown in Figure 5-15 and Figure 5-16. The bootloader assumes that the
CLKIN pin is connected to the LVCMOS-compatible clock source with a frequency of 11.2896, 12.0,
12.288, 16.8, or 19.2 MHz based on the value of BootMode[5:4] bits at reset. (See Section 6.4, Boot
Mode, for details.) Note: The CLKIN pin operates at the same voltage as the DVDDIO supply (1.8, 2.75, or
3.3 V).
In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and
RTC_XO to ground (VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O
address 1900h will not be accessible. This includes the RTC Power Management Register which provides
control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC must still be powered
by an external power source even if the RTC oscillator is disabled. None of the on-chip LDOs can power
CVDDRTC
.
USB_MXI
USB_MXO USB_VSSOSC USB_VDDOSC
VSS
USB_VDDA3P3
CLKIN
Crystal
12 MHz
C1
C2
3.3 V
3.3 V
Figure 5-15. LVCMOS-Compatible Clock Input With USB Oscillator Enabled
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USB_MXI
USB_MXO
USB_VSSOSC
USB_VDDOSC
VSS
USB_VDDA3P3
CLKIN
Figure 5-16. LVCMOS-Compatible Clock Input With USB Oscillator Disabled
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5.7.4.4 Input and Output Clocks Electrical Data and Timing
Table 5-10. Timing Requirements for CLKIN(1) (2) (see Figure 5-17)
CVDD = 1.05/1.3/1.4 V
NO.
UNIT
MAX
MIN
NOM
11.2896
12.0,
12.288,
16.8,
or
1
2
tc(CLKIN)
Cycle time, external clock driven on CLKIN
Pulse duration, CLKIN high
MHz
19.2
0.466 *
tc(CLKIN)
tw(CLKINH)
ns
ns
0.466 *
tc(CLKIN)
3
4
tw(CLKINL)
tt(CLKIN)
Pulse duration, CLKIN low
Transition time, CLKIN
4
ns
(1) The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for
CPU operating frequency.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1
4
1
2
CLKIN
3
4
Figure 5-17. CLKIN Timing
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 3.3/2.75 V](1) (2)
(see Figure 5-18)
CVDD = 1.05/1.3/1.4 V
VDDA_PLL = 1.3 V
NO.
PARAMETER
UNIT
MIN
MAX
1
2
tc(CLKOUT)
Cycle time, CLKOUT
10
ns
ns
0.466 *
tc(CLKOUT)
tw(CLKOUTH)
Pulse duration, CLKOUT high
0.466 *
tc(CLKOUT)
3
tw(CLKOUTL)
Pulse duration, CLKOUT low
ns
4
5
tt(CLKOUTR)
tt(CLKOUTF)
Transition time (rise), CLKOUT
Transition time (fall), CLKOUT
5
5
ns
ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
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Table 5-12. Switching Characteristics Over Recommended Operating Conditions for CLKOUT
[I/O = 1.8 V](1) (2)
(see Figure 5-18)
CVDD = 1.05/1.3/1.4 V
VDDA_PLL = 1.3 V
NO.
PARAMETER
UNIT
MIN
MAX
1
2
tc(CLKOUT)
Cycle time, CLKOUT
20
ns
ns
0.466 *
tc(CLKOUT)
tw(CLKOUTH)
Pulse duration, CLKOUT high
0.466 *
tc(CLKOUT)
3
tw(CLKOUTL)
Pulse duration, CLKOUT low
ns
4
5
tt(CLKOUTR)
tt(CLKOUTF)
Transition time (rise), CLKOUT
Transition time (fall), CLKOUT
5
5
ns
ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
2
5
1
CLKOUT
3
4
Figure 5-18. CLKOUT Timing
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5.7.4.5 Wake-up Events, Interrupts, and XF
The device has a number of interrupts to service the needs of its peripherals. The interrupts can be
selectively enabled or disabled.
5.7.4.5.1 Interrupts Electrical Data and Timing
Table 5-13. Timing Requirements for Interrupts(1) (see Figure 5-19)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
MIN
2P
MAX
1
2
tw(INTH)
tw(INTL)
Pulse duration, interrupt high CPU active
Pulse duration, interrupt low CPU active
ns
ns
2P
(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the
CPU core is clocked at 175 MHz, use P = 5.71 ns.
1
INTx
2
Figure 5-19. External Interrupt Timings
5.7.4.5.2 Wake-Up From IDLE Electrical Data and Timing
Table 5-14. Timing Requirements for Wake-Up From IDLE (see Figure 5-20)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
MIN
MAX
1
tw(WKPL)
Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1
30.5
μs
Table 5-15. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE(1)(2)(3)(4) (see Figure 5-20)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
PARAMETER
UNIT
MIN TYP
MAX
IDLE3 Mode(5) with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL = 1
D
ns
td(WKEVTH-C
KLGEN)
Delay time, WAKEUP pulse
complete to CPU active
2
IDLE3 Mode(5) with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL = 0
C
ns
ns
IDLE2 Mode(5); INTx event
3P
(1) D = 1/ External Clock Frequency (CLKIN).
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
(3) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(4) Assumes the internal LDOs are used with a 0.1uF bandgap capacitor.
(5) For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor Technical
Reference Manual [literature number SPRUH16].
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2
CLKOUT
1
WAKEUP
INTx
A. INT[1:0]
can
only
be
used
as
a
wake-up
event
for
IDLE3
and
IDLE2
modes.
For a description of IDLE2 and IDLE3 mode, see the System chapter in the TMS320C5517 Digital Signal Processor
Technical Reference Manual [literature number SPRUH16].
B. RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.
C. Any unmasked interrupt can be used to exit the IDLE2 mode.
D. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT
Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-20. Wake-Up From IDLE Timings
5.7.4.5.3 XF Electrical Data and Timing
Table 5-16. Switching Characteristics Over Recommended Operating Conditions For XF(1) (2)
(see Figure 5-21)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
PARAMETER
UNIT
MIN
MAX
10.2 ns
1
td(XF)
Delay time, CLKOUT high to XF high
0
(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) C = 1/RTCCLK= 30.5 µs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
CLKOUT(A)
1
XF
A. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLOCKOUT
Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-21. XF Timings
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5.7.5 Direct Memory Access (DMA) Controller
The DMA controller is used to move data among internal memory, external memory, and peripherals
without intervention from the CPU and in the background of CPU operation.
The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four
DMA controllers are identical.
The DMA controller has the following features:
•
•
Operation that is independent of the CPU.
Four channels, which allow the DMA controller to keep track of the context of four independent block
transfers.
•
•
•
•
Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of
selected events.
An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the
programmed transfer.
Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU
intervention.
A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by
independently turning off their input clocks.
5.7.5.1 DMA Channel Synchronization Events
The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP
supports 20 separate synchronization events and each channel can be tied to separate sync events
independent of the other channels. Synchronization events are selected by programming the CHnEVT
field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).
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5.7.6 External Memory Interface (EMIF)
The device supports several memories and external device interfaces, including: NOR Flash, NAND
Flash, SRAM, Non-Mobile SDRAM, and Mobile SDRAM (mSDRAM).
Note: The device can support non-mobile SDRAM under certain circumstances. The device also always
uses mobile SDRAM initialization, but it is able to support SDRAM memories that ignore the BA0 and BA1
pins for the 'load mode register' command. During the mobile SDRAM initialization, the device issues the
'load mode register' initialization command to two different addresses that differ in only the BA0 and BA1
address bits. These registers are the Extended Mode register and the Mode register. The Extended mode
register exists only in mSDRAM and not in non-mSDRAM. If a non-mobile SDRAM memory ignores bits
BA0 and BA1, the second loaded register value overwrites the first, leaving the desired value in the Mode
register and the non-mobile SDRAM will work with the device.
The EMIF provides an 8-bit or 16-bit data bus, an address bus width up to 21 bits, and 6 chip selects,
along with memory control signals.
The EM_A[20:15] address signals are multiplexed with the GPIO peripheral and controlled by the External
Bus Selection Register (EBSR). For more detail on the pin muxing, see Section 5.7.3.5.1, External Bus
Selection Register (EBSR).
5.7.6.1 EMIF Asynchronous Memory Support
The EMIF supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIF data bus can be configured for both 8- or 16-bit width. The device supports up to 21 address
lines and four external wait and interrupt inputs. Up to four asynchronous chip selects are supported by
EMIF (EM_CS[5:2]).
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
Data bus width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes
Each chip select shares the following programmable attribute: Extended Wait Option with Programmable
Timeout.
5.7.6.2 EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported
The EMIF supports 16-bit non-mobile and mobile single data rate (SDR) SDRAM in addition to the
asynchronous memories listed in Section 5.7.6.1, EMIF Asynchronous Memory Support. The supported
SDRAM and mobile SDRAM configurations are:
•
•
•
•
•
•
One, two, and four bank SDRAM and mSDRAM devices
Supports devices with eight, nine, ten, and eleven column addresses
CAS latency of two or three clock cycles
16-bit data-bus width
3.3-, 2.75-, and 1.8 -V LVCMOS interface that is separate from the rest of the chip I/Os.
One (EM_CS0) or two (EM_CS[1:0]) chip selects
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Additionally, the SDRAM and mSDRAM interface of EMIF supports placing the SDRAM and mSDRAM in
"Self-Refresh" and "Powerdown Modes". Self-Refresh mode allows the SDRAM and mSDRAM to be put
into a low-power state while still retaining memory contents; since the SDRAM and mSDRAM will continue
to refresh itself even without clocks from the DSP. Powerdown mode achieves even lower power, except
the DSP must periodically wake the SDRAM and mSDRAM up and issue refreshes if data retention is
required. To achieve the lowest power consumption, the SDRAM and mSDRAM interface has configurable
slew rate on the EMIF pins.
The device has limitations to the clock frequency on the EM_SDCLK pin based on the CVDD and
DVDDEMIF
:
•
The clock frequency on the EM_SDCLK pin can be configured either as SYSCLK (DSP operating
frequency) or SYSCLK/2 via bit 0 of the ECDR Register (1C26h).
•
When CVDD = 1.3 V or 1.4 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the
EM_SDCLK pin is limited to 100 MHz (EM_SDCLK = 100 MHz). Therefore, if SYSCLK ≤ 100 MHz, the
EM_SDCLK can be configured either as SYSCLK or SYSCLK/2. If SYSCLK > 100 MHz, the
EM_SDCLK must be configured as SYSCLK/2 and ≤ 100 MHz.
•
•
When CVDD =1.05 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin
is limited to 75 MHz (EM_SDCLK = 75 MHz). Therefore, if SYSCLK ≤ 75 MHz, the EM_SDCLK can be
configured as either SYSCLK or SYSCLK/2. If SYSCLK > 75 MHz, the EM_SDCLK must be configured
as SYSCLK/2 and ≤ 75 MHz.
When DVDDEMIF = 1.8 V, regardless of the CVDD voltage, the clock frequency on the EM_SDCLK pin
must be configured as SYSCLK/2 and ≤ 50 MHz.
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5.7.6.3 EMIF Electrical Data and Timing CVDD = 1.05 V, DVDDEMIF = 3.3/2.75/1.8 V
Table 5-17. Timing Requirements for EMIF SDRAM and mSDRAM Interface(1) (see Figure 5-22 and
Figure 5-23)
CVDD = 1.05 V
CVDD = 1.05 V
DVDDEMIF = 1.8 V
DVDDEMIF
=
NO.
UNIT
3.3/2.75 V
MIN MAX
MIN
MAX
Input setup time, read data valid on EM_D[15:0] before
EM_SDCLK rising
19 tsu(DV-CLKH)
20 th(CLKH-DIV)
4.07
2.1
5.86
ns
ns
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
rising
2.6
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
Table 5-18. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM and
mSDRAM Interface(1)(2) (see Figure 5-22 and Figure 5-23)
CVDD = 1.05 V
CVDD = 1.05 V
DVDDEMIF = 3.3/2.75 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
1
2
tc(CLK)
tw(CLK)
Cycle time, EMIF clock EM_SDCLK
13.33(3)
20(4)
ns
ns
Pulse duration, EMIF clock EM_SDCLK high
or low
6.67
10
Delay time, EM_SDCLK rising to
EMA_CS[1:0] valid
3
5
7
9
td(CLKH-CSV)
td(CLKH-DQMV)
td(CLKH-AV)
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
10.67
10.67
10.67
10.67
10.67
10.67
10.67
10.67
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
13.46
13.46
13.46
13.46
13.46
13.46
13.46
13.46
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, EM_SDCLK rising to
EM_DQM[1:0] valid
Delay time, EM_SDCLK rising to EM_A[20:0]
and EM_BA[1:0] valid
Delay time, EM_SDCLK rising to EM_D[15:0]
valid
td(CLKH-DV)
Delay time, EM_SDCLK rising to EM_SDRAS
valid
11 td(CLKH-RASV)
13 td(CLKH-CASV)
15 td(CLKH-WEV)
21 td(CLKH-CKEV)
Delay time, EM_SDCLK rising to EM_SDCAS
valid
Delay time, EM_SDCLK rising to EM_WE
valid
Delay time, EM_SDCLK rising to EM_SDCKE
valid
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively. For more detail on the
EM_SDCLK speed see Section 5.7.6.2, EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported.
(3) When CVDD = 1.05 V, and DVDDEMIF = 3.3 V or 2.75 V, the max clock frequency on the EM_SDCLK pin is limited to 75 MHz
(EM_SDCLK = 75 MHz). For more information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical
Reference Manual [literature number SPRUH16].
(4) When DVDDEMIF = 1.8 V, the max clock frequency on the EM_SDCLK pin is limited to 50 MHz (EM_SDCLK = 50 MHz). For more
information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number
SPRUH16].
Table 5-19. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (see Figure 5-24,
Figure 5-26, and Figure 5-27)
CVDD = 1.05 V
DVDDEMIF = 1.8 V
NO.
UNIT
MIN
NOM
MAX
READS and WRITES
2
tw(EM_WAIT)
Pulse duration, EM_WAITx assertion and deassertion
2E
ns
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
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Table 5-19. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (see Figure 5-24,
Figure 5-26, and Figure 5-27) (continued)
CVDD = 1.05 V
DVDDEMIF = 1.8 V
NO.
UNIT
MIN
NOM
MAX
READS
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
18
0
ns
ns
ns
14 tsu (EMOEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 18
WRITES
28 tsu (EMWEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 18
ns
(3) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-26 and Figure 5-27 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-20. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (see
Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.75 V
NO.
UNIT
MIN NOM MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
Hold time, EM_D[15:0] valid after EM_OE high
17
0
ns
ns
ns
14 tsu (EMOEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 17
WRITES
28 tsu (EMWEL-EMWAIT) Setup time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 17
ns
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
(3) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-26 and Figure 5-27 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 5-21. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (3) (see
Figure 5-25 and Figure 5-27)(4)
CVDD = 1.05 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 18
(TA)*E
(TA)*E + 18
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 18
(RS+RST+RH+(EWC*16))*E - 18
(RS)*E - 11
(RS+RST+RH)*E
(RS+RST+RH)*E + 18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 18
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low pulse (EW = 0)
(RS)*E
(RS)*E + 11
+11
tsu(EMCEL-EMOEL)
-11
0
(RH)*E - 11
(RH)*E
(RH)*E + 11
+11
th(EMOEH-EMCEH)
-11
0
(RS)*E
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E - 11
(RS)*E + 11
(RH)*E + 18
(RS)*E + 11
(RH)*E + 18
(RST)*E + 18
(RST+(EWC*16))*E + 11
4E + 18
(RH)*E - 18
(RH)*E
(RS)*E - 11
(RS)*E
(RH)*E - 18
(RH)*E
(RST)*E - 18
(RST)*E
10
11
tw(EMOEL)
EM_OE active low pulse (EW = 1)
(RST+(EWC*16))*E - 18
4E - 18
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E - 18
(WS+WST+WH)*E
(WS+WST+WH)*E + 18
ns
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E +
18
(WS+WST+WH+(EWC*16))*E - 18
(WS+WST+WH+(EWC*16))*E
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS)*E - 18
-18
(WS)*E
0
(WS)*E + 18
+18
ns
ns
ns
ns
ns
ns
ns
ns
16
17
tsu(EMCSL-EMWEL)
(WH)*E - 11
-11
(WH)*E
0
(WH)*E + 11
+11
th(EMWEH-EMCSH)
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E - 11
(WH)*E - 11
(WS)*E - 11
(WH)*E - 11
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E + 11
(WH)*E + 11
(WS)*E + 11
(WH)*E + 11
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
(3) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
(4) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Table 5-21. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (3) (see
Figure 5-25 and Figure 5-27)(4) (continued)
CVDD = 1.05 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
EM_WE active low pulse (EW = 0)
(WST)*E - 18
(WST)*E
(WST)*E + 18
ns
ns
ns
ns
ns
22
tw(EMWEL)
EM_WE active low pulse (EW = 1)
(WST+(EWC*16))*E - 18
3E - 18
(WST+(EWC*16))*E
(WST+(EWC*16))*E + 18
4E + 18
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
4E
(WS)*E
(WH)*E
(WS)*E - 18
(WS)*E + 18
(WH)*E - 11
(WH)*E + 11
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Table 5-22. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (3)
(see Figure 5-25 and Figure 5-27)(4)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.75 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 17
(TA)*E
(TA)*E + 17
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 17
(RS+RST+RH)*E
(RS+RST+RH)*E + 17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E - 17
(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 17
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low pulse (EW = 0)
(RS)*E - 9
-9
(RS)*E
(RS)*E + 9
+9
tsu(EMCEL-EMOEL)
0
(RH)*E - 9
(RH)*E
(RH)*E + 9
+9
th(EMOEH-EMCEH)
-9
0
(RS)*E
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E - 9
(RS)*E + 9
(RH)*E + 17
(RS)*E + 9
(RH)*E + 17
(RST)*E + 17
(RST+(EWC*16))*E + 9
4E + 17
(RH)*E - 17
(RS)*E - 9
(RH)*E
(RS)*E
(RH)*E - 17
(RST)*E - 17
(RST+(EWC*16))*E - 17
4E - 17
(RH)*E
(RST)*E
10
11
tw(EMOEL)
EM_OE active low pulse (EW = 1)
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E - 17
(WS+WST+WH)*E
(WS+WST+WH)*E + 17
ns
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E +
17
(WS+WST+WH+(EWC*16))*E - 17
(WS+WST+WH+(EWC*16))*E
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS)*E - 17
-17
(WS)*E
0
(WS)*E + 17
+17
ns
ns
ns
ns
ns
ns
ns
ns
16
17
tsu(EMCSL-EMWEL)
(WH)*E - 9
-9
(WH)*E
0
(WH)*E + 9
+9
th(EMWEH-EMCSH)
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E - 9
(WH)*E - 9
(WS)*E - 9
(WH)*E - 9
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E + 9
(WH)*E + 9
(WS)*E + 9
(WH)*E + 9
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
(3) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
(4) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Table 5-22. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (3)
(see Figure 5-25 and Figure 5-27)(4) (continued)
CVDD = 1.05 V
DVDDEMIF = 3.3/2.75 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
EM_WE active low pulse (EW = 0)
(WST)*E - 17
(WST)*E
(WST)*E + 17
ns
ns
ns
ns
ns
22
tw(EMWEL)
EM_WE active low pulse (EW = 1)
(WST+(EWC*16))*E - 17
3E - 17
(WST+(EWC*16))*E
(WST+(EWC*16))*E + 17
4E + 17
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
4E
(WS)*E
(WH)*E
(WS)*E - 17
(WS)*E + 17
(WH)*E - 9
(WH)*E + 9
100
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5.7.6.4 EMIF Electrical Data and Timing CVDD = 1.3/1.4 V, DVDDEMIF = 3.3/2.75/1.8 V
Table 5-23. Timing Requirements for EMIF SDRAM and mSDRAM Interface(1) (see Figure 5-22 and
Figure 5-23)
CVDD = 1.3/1.4 V
CVDD = 1.3/1.4 V
DVDDEMIF = 1.8 V
DVDDEMIF
=
NO.
UNIT
3.3/2.75 V
MIN MAX
MIN
MAX
Input setup time, read data valid on EM_D[15:0] before
EM_SDCLK rising
19 tsu(DV-CLKH)
20 th(CLKH-DIV)
4.07
2.1
3.28
ns
ns
Input hold time, read data valid on EM_D[15:0] after EM_SDCLK
rising
3.1
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
Table 5-24. Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM and
mSDRAM Interface(1)(2) (see Figure 5-22 and Figure 5-23)
CVDD = 1.3/1.4 V
DVDDEMIF = 3.3/2.75 V
CVDD = 1.3/1.4 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
1
2
tc(CLK)
tw(CLK)
Cycle time, EMIF clock EM_SDCLK
10(3)
20(4)
ns
ns
Pulse duration, EMIF clock EM_SDCLK high
or low
5
10
Delay time, EM_SDCLK rising to
EMA_CS[1:0] valid
3
5
7
9
td(CLKH-CSV)
td(CLKH-DQMV)
td(CLKH-AV)
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
7.88
7.88
7.88
7.88
7.88
7.88
7.88
7.88
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
10.67
10.67
10.67
10.67
10.67
10.67
10.67
10.67
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, EM_SDCLK rising to
EM_DQM[1:0] valid
Delay time, EM_SDCLK rising to EM_A[20:0]
and EM_BA[1:0] valid
Delay time, EM_SDCLK rising to EM_D[15:0]
valid
td(CLKH-DV)
Delay time, EM_SDCLK rising to EM_SDRAS
valid
11 td(CLKH-RASV)
13 td(CLKH-CASV)
15 td(CLKH-WEV)
21 td(CLKH-CKEV)
Delay time, EM_SDCLK rising to EM_SDCAS
valid
Delay time, EM_SDCLK rising to EM_WE
valid
Delay time, EM_SDCLK rising to EM_SDCKE
valid
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively. For more detail on the
EM_SDCLK speed see Section 5.7.6.2, EMIF Non-Mobile and Mobile Synchronous DRAM Memory Supported.
(3) The maximum clock frequency on the EM_SDCLK pin is limited to 100 MHz (EM_SDCLK = 100 MHz). For more information, see the
EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number SPRUH16].
(4) When DVDDEMIF = 1.8 V, the max clock frequency on the EM_SDCLK pin is limited to 50 MHz (EM_SDCLK = 50 MHz). For more
information, see the EMIF chapter in the TMS320C5517 Digital Signal Processor Technical Reference Manual [literature number
SPRUH16].
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Table 5-25. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (see Figure 5-24,
Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
DVDDEMIF = 1.8 V
NO.
UNIT
MIN
NOM
MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
11
0
ns
ns
ns
Hold time, EM_D[15:0] valid after EM_OE high
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 10
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 10
ns
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 100 MHz, E = 13.33 or 10 ns, respectively.
(3) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-26 and Figure 5-27 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
102
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Table 5-26. Timing Requirements for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (see
Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
DVDDEMIF = 3.3/2.75 V
NO.
UNIT
MIN NOM MAX
READS and WRITES
Pulse duration, EM_WAITx assertion and deassertion
READS
2
tw(EM_WAIT)
2E
ns
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
Setup time, EM_D[15:0] valid before EM_OE high
11
0
ns
ns
ns
Hold time, EM_D[15:0] valid after EM_OE high
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 9
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAITx asserted before end of Strobe Phase(3)
4E + 9
ns
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 200 MHz, E = 13.33 or 5 ns, respectively.
(3) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 5-26 and Figure 5-27 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 5-27. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (3) (4)
(see Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 10
(TA)*E
(TA)*E + 10
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 10
(RS+RST+RH)*E
(RS+RST+RH)*E + 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E - 10
(RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*E + 10
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low pulse (EW = 0)
(RS)*E - 4
-4
(RS)*E
(RS)*E + 4
+4
tsu(EMCSL-EMOEL)
0
(RH)*E - 4
(RH)*E
(RH)*E + 4
th(EMOEH-EMCSH)
-4
0
(RS)*E
+4
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E - 4
(RS)*E + 4
(RH)*E - 10
(RS)*E - 4
(RH)*E
(RH)*E + 10
(RS)*E + 4
(RS)*E
(RH)*E - 10
(RST)*E - 10
(RST+(EWC*16))*E - 10
4E - 10
(RH)*E
(RH)*E + 10
(RST)*E + 10
(RST+(EWC*16))*E + 10
4E + 10
(RST)*E
10
11
tw(EMOEL)
EM_OE active low pulse (EW = 1)
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E - 10
(WS+WST+WH)*E
(WS+WST+WH)*E + 10
ns
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E +
10
(WS+WST+WH+(EWC*16))*E - 10
(WS+WST+WH+(EWC*16))*E
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
(WS)*E - 10
-10
(WS)*E
0
(WS)*E +10
+10
ns
ns
ns
ns
ns
ns
ns
ns
16
17
tsu(EMCSL-EMWEL)
(WH)*E - 4
-4
(WH)*E
0
(WH)*E + 4
+4
th(EMWEH-EMCSH)
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E - 4
(WH)*E - 4
(WS)*E - 4
(WH)*E - 4
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E + 4
(WH)*E + 4
(WS)*E + 4
(WH)*E + 4
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
(3) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 200 MHz, E = 13.33 or 5 ns, respectively.
(4) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
104
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Table 5-27. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 1.8 V(1)(2) (3) (4)
(see Figure 5-24, Figure 5-26, and Figure 5-27) (continued)
CVDD = 1.3/1.4 V
DVDDEMIF = 1.8 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
EM_WE active low pulse (EW = 0)
(WST)*E - 10
(WST)*E
(WST)*E + 10
ns
ns
ns
ns
ns
22
tw(EMWEL)
EM_WE active low pulse (EW = 1)
(WST+(EWC*16))*E - 10
3E - 10
(WST+(EWC*16))*E
(WST+(EWC*16))*E + 10
4E + 10
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
4E
(WS)*E
(WH)*E
(WS)*E - 10
(WS)*E + 10
(WH)*E - 4
(WH)*E + 4
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Table 5-28. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (3)
(4) (see Figure 5-24, Figure 5-26, and Figure 5-27)
CVDD = 1.3/1.4 V
DVDDEMIF = 3.3/2.75 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 9
(TA)*E
(TA)*E + 9
ns
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 9
(RS+RST+RH)*E
(RS+RST+RH)*E + 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
5
tc(EMRCYCLE)
EMIF read cycle time (EW = 1)
(RS+RST+RH+(EWC*16))*E - 9
(RS+RST+RH+(EWC*16))*E
(RS+RST+RH+(EWC*16))*E + 9
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_OE high to EM_CE[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[20:0] invalid
EM_OE active low pulse (EW = 0)
(RS)*E - 4
(RS)*E
(RS)*E + 4
+4
tsu(EMCSL-EMOEL)
-4
0
(RH)*E - 4
(RH)*E
(RH)*E + 4
+4
th(EMOEH-EMCSH)
-4
(RS)*E - 4
0
(RS)*E
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E + 4
(RH)*E + 9
(RS)*E + 4
(RH)*E + 9
(RST)*E + 9
(RST+(EWC*16))*E + 9
4E + 9
(RH)*E - 9
(RH)*E
(RS)*E - 4
(RS)*E
(RH)*E - 9
(RH)*E
(RST)*E - 9
(RST)*E
10
11
tw(EMOEL)
EM_OE active low pulse (EW = 1)
(RST+(EWC*16))*E - 9
4E - 9
(RST+(EWC*16))*E
4E
td(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E - 9
(WS+WST+WH+(EWC*16))*E - 9
(WS)*E - 9
(WS+WST+WH)*E
(WS+WST+WH)*E + 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
16
17
tc(EMWCYCLE)
EMIF write cycle time (EW = 1)
(WS+WST+WH+(EWC*16))*E (WS+WST+WH+(EWC*16))*E + 9
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low (SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high (SS = 1)
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[20:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[20:0] invalid
EM_WE active low pulse (EW = 0)
(WS)*E
(WS)*E +9
+9
tsu(EMCSL-EMWEL)
-9
0
(WH)*E
(WH)*E - 4
(WH)*E + 4
+4
th(EMWEH-EMCSH)
-4
0
18
19
20
21
tsu(EMBAV-EMWEL)
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
th(EMWEH-EMAIV)
(WS)*E - 4
(WS)*E
(WS)*E + 4
(WH)*E + 4
(WS)*E + 4
(WH)*E + 4
(WST)*E + 9
(WST+(EWC*16))*E + 9
(WH)*E - 4
(WH)*E
(WS)*E - 4
(WS)*E
(WH)*E - 4
(WH)*E
(WST)*E - 9
(WST)*E
22
tw(EMWEL)
EM_WE active low pulse (EW = 1)
(WST+(EWC*16))*E - 9
(WST+(EWC*16))*E
(1) Timing parameters are obtained with 10pF loading on the EMIF pins.
(2) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Configuration and Asynchronous Wait Cycle Configuration Registers.
(3) E = SYSCLK period in ns. For example, when SYSCLK is set to 75 or 200 MHz, E = 13.33 or 5 ns, respectively.
(4) EWC = external wait cycles determined by EM_WAITx input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Table 5-28. Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous Memory, DVDDEMIF = 3.3/2.75 V(1)(2) (3)
(4) (see Figure 5-24, Figure 5-26, and Figure 5-27) (continued)
CVDD = 1.3/1.4 V
DVDDEMIF = 3.3/2.75 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
23
24
25
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
th(EMWEH-EMDIV)
Delay time from EM_WAITx deasserted to EM_WE high
Output setup time, EM_D[15:0] valid to EM_WE low
Output hold time, EM_WE high to EM_D[15:0] invalid
3E - 9
(WS)*E - 9
(WH)*E - 4
4E
(WS)*E
(WH)*E
4E + 9
(WS)*E + 9
(WH)*E + 4
ns
ns
ns
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1
BASIC mSDRAM
WRITE OPERATION
2
2
EM_SDCLK
EM_CS[1:0]
EM_DQM[1:0]
EM_BA[1:0]
EM_A[20:0]
3
5
7
7
9
3
5
7
7
9
EM_D[15:0]
EM_SDRAS
EM_SDCAS
EM_WE
11
11
13
15
15
Figure 5-22. EMIF Basic SDRAM and mSDRAM Write Operation
1
BASIC mSDRAM
READ OPERATION
2
2
EM_SDCLK
EM_CS[1:0]
EM_DQM[1:0]
EM_BA[1:0]
EM_A[20:0]
3
5
7
7
3
5
7
7
19
20
2 EM_CLK Delay
17
17
EM_D[15:0]
EM_SDRAS
11
11
13
13
EM_SDCAS
EM_WE
Figure 5-23. EMIF Basic SDRAM and mSDRAM Read Operation
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3
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
4
8
5
9
7
6
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 5-24. Asynchronous Memory Read Timing for EMIF
15
1
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
16
18
20
17
19
21
22
EM_WE
25
24
EM_D[15:0]
EM_OE
Figure 5-25. Asynchronous Memory Write Timing for EMIF
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SETUP
STROBE
Extended Due to EM_WAITx
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
14
11
EM_OE
2
2
EM_WAITx
Asserted
Deasserted
Figure 5-26. EM_WAITx Read Timing Requirements
SETUP
STROBE
Extended Due to EM_WAITx
STROBE HOLD
EM_CS[5:2]
EM_BA[1:0]
EM_A[20:0]
EM_D[15:0]
28
25
EM_WE
2
Asserted
2
EM_WAITx
Deasserted
Figure 5-27. EM_WAITx Write Timing Requirements
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5.7.7 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of the
internal register. External input clocks on certain GPIOs can also be used to drive the timers on this
device. The GPIO can also be used to send interrupts to the CPU.
The GPIO peripheral supports the following:
•
•
•
Up to 26 GPIOs plus 1 general-purpose output (XF and 4 Special-Purpose Outputs for Use With SAR)
The 26 GPIO pins have internal pulldowns (IPDs) which can be individually disabled
The 26 GPIOs can be configured to generate edge detected interrupts to the CPU on either the rising
or falling edge
The device GPIO pin functions are multiplexed with various other signals. For more detailed information
on what signals are multiplexed with the GPIO and how to configure them, see Section 4.2, Signal
Descriptions and Section 4.3, Pin Multiplexing of this document.
5.7.7.1 GPIO Peripheral Input/Output Electrical Data and Timing
Table 5-29. Timing Requirements for GPIO Inputs(1) (see Figure 5-28)
CVDD = 1.05 V
CVDD = 1.3 V/1.4
NO.
UNIT
V
MIN
MAX
1
2
tw(ACTIVE)
Pulse duration, GPIO input/external interrupt pulse active
Pulse duration, GPIO input/external interrupt pulse inactive
2C(1)(2)
C(1)(2)
ns
ns
tw(INACTIVE)
(1) The pulse duration given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-28)
CVDD = 1.05 V
CVDD = 1.3 V/1.4 V
NO.
PARAMETER
UNIT
MIN
3C(1)(2)
3C(1)(2)
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GP[x] output high
Pulse duration, GP[x] output low
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
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2
2
1
1
GP[x] Input
(With IOINTEDGy = 0)
GP[x] Input
(With IOINTEDGy = 1)
4
3
GP[x] Output
Figure 5-28. GPIO Port Timing
5.7.7.2 GPIO Peripheral Input Latency Electrical Data and Timing
Table 5-31. Timing Requirements for GPIO Input Latency(1)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
MIN
5
MAX
Polling GPIO_DIN register
cyc
cyc
cyc
1
tL(GPI) Latency, GP[x] input
Polling GPIO_IFR register
Interrupt Detection
7
8
(1) The pulse duration given is sufficient to generate a CPU interrupt. However, if a user wants to have the device recognize the GP[x] input
changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access
the GPIO register through the internal bus.
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5.7.8 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between the device and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit and receive 2 to 8-bit data to and from the DSP
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
•
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Version 2.1 (January 2000)
Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)
Noise Filter to Remove Noise 50 ns or Less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit and Receive) and Slave (Transmit and Receive) Functionality
One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller
One Interrupt that can be used by the CPU
Slew-Rate Limited Open-Drain Output Buffers
The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper
operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and
SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the
DSP clock divided by a programmable prescaler.
5.7.8.1 I2C Electrical Data and Timing
Table 5-32. Timing Requirements for I2C Timings(1) (see Figure 5-29)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
STANDARD
MODE
FAST MODE
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
3
th(SCLL-SDAL)
µs
4
5
6
7
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
100(2)
µs
µs
ns
µs
tsu(SDAV-SCLH) Setup time, SDA valid before SCL high
250
0(3)
th(SDA-SCLL)
Hold time, SDA valid after SCL low
0(3) 0.9(4)
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
µs
(6)
(6)
9
tr(SDA)
tr(SCL)
Rise time, SDA(5)
Rise time, SCL(5)
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300
300
ns
ns
10
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their VIH cannot go above DVDDIO + 0.3 V).
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)= 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load ©b)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
(6) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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Table 5-32. Timing Requirements for I2C Timings(1) (see Figure 5-29) (continued)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
MAX
STANDARD
MODE
FAST MODE
MIN
MAX
MIN
(6)
(6)
11
12
13
14
15
tf(SDA)
tf(SCL)
Fall time, SDA(5)
Fall time, SCL(5)
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
ns
ns
µs
ns
pF
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
4
0.6
0
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
(6)
Cb
400
400
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
Figure 5-29. I2C Receive Timings
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Table 5-33. Switching Characteristics for I2C Timings(1) (see Figure 5-30)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
PARAMETER
UNIT
STANDARD
MODE
FAST MODE
MIN
MAX
MIN
MAX
16
17
tc(SCL)
td(SCLH-SDAL)
td(SDAL-SCLL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a repeated START
condition)
4.7
4
0.6
0.6
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
18
µs
19
20
21
22
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
100
0
µs
µs
ns
µs
td(SDAV-SCLH) Delay time, SDA valid to SCL high
250
0
tv(SCLL-SDAV)
Valid time, SDA valid after SCL low
0.9
Pulse duration, SDA high between STOP and START
conditions
23
tw(SDAH)
4.7
1.3
µs
Rise time, SDA(2)
Rise time, SCL(2)
Fall time, SDA(2)
Fall time, SCL(2)
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
µs
pF
(1)
(1)
(1)
(1)
24
25
26
27
28
29
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
Cp Capacitance for each I2C pin
4
0.6
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load ©b)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
26
24
SDA
SCL
21
23
19
28
20
25
16
18
27
18
17
22
Stop
Start
Repeated
Start
Stop
Figure 5-30. I2C Transmit Timings
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5.7.9 Inter-IC Sound (I2S)
The device I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data, between
the device and an external I2S peripheral device such as an audio codec.
The device supports three independent dual-channel I2S peripherals, each with the following features:
•
•
•
•
•
•
•
•
Full-duplex (transmit and receive) dual-channel communication
Double buffered data registers that allow for continuous data streaming
I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
Ability to sign-extend received data samples for easy use in signal processing algorithms
Programmable polarity for both frame synchronization and bit clocks
Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode
Detection of over-run, under-run, and frame-sync error conditions
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5.7.9.1 Inter-IC Sound (I2S) Electrical Data and Timing
Table 5-34. Timing Requirements for I2S [I/O = 3.3 and 2.75 V](1) (see Figure 5-31)
MASTER
CVDD = 1.05 V
MIN MAX
2P(1)(2)
P(1)(2)
P(1)(2)
SLAVE
NO.
CVDD = 1.3/1.4 V
MIN MAX
2P(1)(2)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
MIN MAX
UNIT
MIN MAX
1
2
3
tc(CLK)
Cycle time, I2S_CLK
2P(1)(2)
P(1)(2)
P(1)(2)
2P(1)(2)
P(1)(2)
P(1)(2)
ns
ns
ns
tw(CLKH)
tw(CLKL)
Pulse duration, I2S_CLK high
Pulse duration, I2S_CLK low
P(1)(2)
P(1)(2)
Setup time, I2S_RX valid before I2S CLK high
(CLKPOL = 0)
tsu(RXV-CLKH)
tsu(RXV-CLKL)
th(CLKH-RXV)
th(CLKL-RXV)
tsu(FSV-CLKH)
tsu(FSV-CLKL)
th(CLKH-FSV)
th(CLKL-FSV)
5
5
3
3
–
–
–
–
3
3
3
3
–
–
–
–
5
3
3
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Setup time, I2S_RX valid before I2S_CLK low
(CLKPOL = 1)
5
Hold time, I2S_RX valid after I2S_CLK high
(CLKPOL = 0)
3
3
Hold time, I2S_RX valid after I2S_CLK low
(CLKPOL = 1)
3
12.5
3
Setup time, I2S_FS valid before I2S_CLK high
(CLKPOL = 0)
6.5
6.5
9
Setup time, I2S_FS valid before I2S_CLK low
(CLKPOL = 1)
12.5
Hold time, I2S_FS valid after I2S_CLK high
(CLKPOL = 0)
tw(CLKH) + 0.7(3)
tw(CLKL) + 0.7(3)
tw(CLKH) + 0.7(3)
tw(CLKL) + 0.7(3)
10
Hold time, I2S_FS valid after I2S_CLK low
(CLKPOL = 1)
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Table 5-35. Timing Requirements for I2S [I/O = 1.8 V](1) (see Figure 5-31)
MASTER
SLAVE
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
CVDD = 1.05 V
MIN
2P(1) (2)
P(1) (2)
CVDD = 1.3/1.4 V
UNIT
MIN
2P(1) (2)
P(1) (2)
P(1) (2)
MAX
MIN
2P(1) (2)
P(1) (2)
P(1) (2)
MAX
MAX
MIN
2P(1) (2)
P(1) (2)
P(1) (2)
MAX
1
2
3
tc(CLK)
Cycle time, I2S_CLK
ns
ns
ns
tw(CLKH)
tw(CLKL)
Pulse duration, I2S_CLK high
Pulse duration, I2S_CLK low
P(1) (2)
Setup time, I2S_RX valid before I2S CLK
high (CLKPOL = 0)
tsu(RXV-CLKH)
tsu(RXV-CLKL)
th(CLKH-RXV)
th(CLKL-RXV)
tsu(FSV-CLKH)
tsu(FSV-CLKL)
th(CLKH-FSV)
th(CLKL-FSV)
5
5
3
3
–
–
–
–
3
3
3
3
–
–
–
–
5
5
3.5
3.5
3
ns
ns
ns
ns
ns
ns
ns
ns
7
8
Setup time, I2S_RX valid before I2S_CLK
low (CLKPOL = 1)
Hold time, I2S_RX valid after I2S_CLK high
(CLKPOL = 0)
3
Hold time, I2S_RX valid after I2S_CLK low
(CLKPOL = 1)
3
3
Setup time, I2S_FS valid before I2S_CLK
high (CLKPOL = 0)
12.5
12.5
15
15
9
Setup time, I2S_FS valid before I2S_CLK
low (CLKPOL = 1)
Hold time, I2S_FS valid after I2S_CLK high
(CLKPOL = 0)
tw(CLKH)
+
tw(CLKH)
+
0.7(3)
0.71(3)
10
Hold time, I2S_FS valid after I2S_CLK low
(CLKPOL = 1)
tw(CLKL)
+
tw(CLKL)
+
0.7(3)
0.71(3)
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Table 5-36. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 and 2.75 V] (see Figure 5-31)
MASTER
SLAVE
CVDD = 1.05 V CVDD = 1.3/1.4 V
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
tc(CLK)
Cycle time, I2S_CLK
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
3
4
5
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
tdmax(CLKL-DXV)
tdmax(CLKH-DXV)
tdmax(CLKL-FSV)
tdmax(CLKH-FSV)
Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0)
Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1)
Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0)
Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1)
14.5
11
14.5
11
0
14.5
7
0
11
5
0
14.5
–
0
11
–
-2
-1.74
-1.74
-2
7
5
–
–
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
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Table 5-37. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-31)
MASTER
CVDD = 1.05 V CVDD = 1.3/1.4 V
MIN MAX MIN MAX
50 or 40 or
SLAVE
CVDD = 1.05 V CVDD = 1.3/1.4 V
MIN MAX MIN MAX
50 or 40 or
NO.
PARAMETER
UNIT
1
2
tc(CLK)
Cycle time, I2S_CLK
ns
2P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
2P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
2P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
2P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
P(1) (2)
0
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
ns
ns
ns
ns
ns
ns
ns
ns
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
3
4
5
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
tdmax(CLKL-DXV)
tdmax(CLKH-DXV)
tdmax(CLKL-FSV)
tdmax(CLKH-FSV)
Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0)
Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1)
Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0)
Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1)
17.7
14.5
17.7
14.5
0
17.7
7
0
14.5
5
0
17.7
–
0
14.5
–
-2
-2
-2
7
-2
5
–
–
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
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1
3
2
I2S_CLK
(CLKPOL = 0)
I2S_CLK
(CLKPOL = 1)
5
I2S_FS
(Output, MODE = 1)
9
10
I2S_FS
(Input, MODE = 0)
4
I2S_DX
I2S_RX
7
8
Figure 5-31. I2S Input and Output Timings
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5.7.10 Multichannel Serial Port Interface (McSPI)
The multichannel SPI (McSPI) is a master and slave synchronous serial bus. McSPI allows a duplex,
synchronous, serial communication to SPI-compliant external devices (slaves and masters).
The McSPI instances include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths ranging from 4 to 32 bits
Up to three master channels or single channel in slave mode
Master multichannel mode:
–
–
–
–
Full duplex and half duplex
Transmit-only and receive-only and transmit-and-receive modes
Flexible I/O port controls per channel
Two direct memory access (DMA) requests (read and write) per channel
•
•
•
•
•
•
Single interrupt line for multiple interrupt source events
Power management through wake-up capabilities
Enable the addition of a programmable start-bit for SPI transfer per channel (start-bit mode)
Support start-bit write command
128-bytes built-in FIFO available for a single channel
Force CS mode for continuous transfers
5.7.10.1 McSPI Electrical Data and Timing
The multichannel SPI is a master and slave synchronous serial bus.
The following tables assume testing over the recommended operating conditions.
5.7.10.1.1 McSPI in Slave Mode
Table 5-38. McSPI Interface Timing Requirements – Slave Mode
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SS2 tsu(SIMOV-CLKAE)
SS3 th(SIMOV-CLKAE)
SS4 tsu(CS0V-CLKFE)
SS5 th(CS0I-CLKLE)
Setup time, McSPI_SIMO valid before McSPI_CLK
active edge
4
3
ns
ns
ns
ns
Hold time, McSPI_SIMO valid after McSPI_CLK
active edge
3.8
6.9
6.9
2.8
6.9
6.9
Setup time, McSPI_CS0 valid before McSPI_CLK
first edge
Hold time, McSPI_CS0 invalid after McSPI_CLK last
edge
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Table 5-39. McSPI Interface Switching Characteristics — Slave Mode [I/O = 3.3 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
22
SS0
Clock period
14
MHz
ns
SS1 tw(CLK)
SS6
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1)
0.55*P(1)
Output Delay time, McSPI_CLK active edge to
McSPI_SOMI valid
0
31
15
15
0
19
ns
SS7
SS7
Delay time, McSPI_CSn active edge to McSPIn_SOMI
shifted, Mode 0
8.7
8.7
ns
ns
Delay time, McSPI_CSn active edge to McSPIn_SOMI
shifted, Mode 2
(1) P = McSPI_CLK clock period.
Table 5-40. McSPI Interface Switching Characteristics — Slave Mode [I/O = 2.75 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
19
SS0
Clock period
12
MHz
ns
SS1 tw(CLK)
SS6
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1)
0.55*P(1)
Output Delay time, McSPI_CLK active edge to
McSPI_SOMI valid
0
36
0
22.5
ns
SS7
Delay time, McSPI_CSn active edge to Modes 0 and 2
McSPIn_SOMI shifted
15
12
ns
(1) P = McSPI_CLK clock period.
Table 5-41. McSPI Interface Switching Characteristics — Slave Mode [I/O = 1.8 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
18
SS0
Clock period
12
MHz
ns
SS1 tw(CLK)
SS6
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1)
0.55*P(1)
Output Delay time, McSPI_CLK active edge to
McSPI_SOMI valid
0
36
0
24
ns
SS7
Delay time, McSPI_CSn active edge to Modes 0 and 2
McSPIn_SOMI shifted
17
15
ns
(1) P = McSPI_CLK clock period.
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Mode 0 and 2
McSPI_CS0(EPOL=1)
SS0
SS1
SS4
SS5
McSPI_CLK(POL=0)
McSPI_CLK(POL=1)
SS0
SS1
SS2
SS3
Bit n-1
SS7
Bit n-1
McSPI_SIMO
McSPI_SOMI
Bit n-2
SS6
Bit n-3
Bit n-4
Bit n-4
Bit 0
Bit n-2
Bit n-3
Bit 0
Mode 1 and 3
McSPI_CS0(EPOL=1)
McSPI_CLK(POL=0)
McSPI_CLK(POL=1)
SS0
SS1
SS0
SS1
SS4
SS5
SS3
SS2
Bit n-1
SS6
Bit n-1
McSPI_SIMO
McSPI_SOMI
Bit n-2
Bit n-2
Bit n-3
Bit 1
Bit 0
Bit 0
Bit n-3
Bit 1
Figure 5-32. McSPI Interface — Transmit and Receive in Slave Mode
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5.7.10.1.2 McSPI in Master Mode
The following tables assume testing over the recommended operating conditions (see Figure 5-33).
Table 5-42. McSPI Interface Timing Requirements – Master Mode [I/O = 3.3, 2.75 V]
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SM2
SM3
Setup time, McSPI_SOMI valid before McSPI_CLK
active edge
4
3
ns
ns
Hold time, McSPI_SOMI valid after McSPI_CLK active
edge
3.8
2.8
Table 5-43. McSPI Interface Timing Requirements – Master Mode [I/O = 1.8 V]
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SM2
SM3
Setup time, McSPI_SOMI valid before McSPI_CLK
active edge
7.5
3
ns
ns
Hold time, McSPI_SOMI valid after McSPI_CLK active
edge
3.8
2.8
Table 5-44. McSPI Interface Switching Characteristics – Master Mode [I/O = 3.3 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SM0
SM1
SM4
Clock period
22
42
MHz
ns
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1) 0.55*P(1)
Delay time, McSPI_CLK active edge to
McSPI_SIMO valid
0
18
10
-1
8.9
ns
SM5
SM6
SM7
Delay time, McSPI_CSx active to
McSPI_CLK first edge
Modes
0–3
3.1
3.1
3.1
3.1
ns
ns
ns
Delay time, McSPI_CLK last edge to
McSPI_CSx inactive
Modes
0–3
Delay time, McSPI_CSx active edge to Modes 0
6
McSPI_SIMO shifted
and 2
(1) P = McSPI_CLK clock period
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Table 5-45. McSPI Interface Switching Characteristics – Master Mode [I/O = 2.75 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SM0
SM1
SM4
Clock period
22
38
MHz
ns
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1) 0.55*P(1)
Delay time, McSPI_CLK active edge to McSPI_SIMO
valid
0
18
10
-1
10
ns
SM5
SM6
SM7
Delay time, McSPI_CSx active to
McSPI_CLK first edge
Modes 0–3
3.1
3.1
3.1
3.1
ns
ns
ns
Delay time, McSPI_CLK last edge to
McSPI_CSx inactive
Modes 0–3
Delay time, McSPI_CSx active edge to Modes 0
McSPI_SIMO shifted and 2
6
(1) P = McSPI_CLK clock period
Table 5-46. McSPI Interface Switching Characteristics – Master Mode [I/O = 1.8 V]
NO.
PARAMETER
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
MAX
MIN
MAX
SM0
SM1
SM4
Clock period
19
38
MHz
ns
Pulse duration, McSPI_CLK high or low
0.45*P(1) 0.55*P(1) 0.45*P(1) 0.55*P(1)
Delay time, McSPI_CLK active edge to
McSPI_SIMO valid
0
18.5
-1
10
ns
SM5
SM6
SM7
Delay time, McSPI_CSx active to
McSPI_CLK first edge
Modes 0–3
Modes 0–3
2.75
2.75
3
ns
ns
ns
Delay time, McSPI_CLK last edge to
McSPI_CSx inactive
3
Delay time, McSPI_CSx active edge to Modes 0
11
5
McSPI_SIMO shifted
and 2
(1) P = McSPI_CLK clock period
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Mode 0 and 2
McSPI_CSx(EPOL=1)
McSPI_CLK(POL=0)
McSPI_CLK(POL=1)
McSPI_SIMO
SM0
SM1
SM5
SM6
SM0
SM1
SM7
SM4
Bit n-2
Bit n-1
SM2
Bit n-3
Bit n-4
Bit n-4
Bit 0
SM3
Bit n-1
McSPI_SOMI
Bit n-2
Bit n-3
Bit 0
Mode 1 and 3
McSPI_CSx(EPOL=1)
SM0
SM1
McSPI_CLK(POL=0)
SM0
SM1
SM5
SM6
McSPI_CLK(POL=1)
McSPI_SIMO
SM4
Bit n-1
SM2
Bit n-2
Bit n-3
Bit 1
Bit 1
Bit 0
SM3
McSPI_SOMI
Bit n-1
Bit n-2
Bit n-3
Bit 0
Figure 5-33. McSPI Interface — Transmit and Receive in Master Mode
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5.7.11 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
•
External shift clock or an internal, programmable frequency shift clock for data transfer
Transmit and Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it
more tolerant to DMA latency
If the internal clock is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 3 or greater.
5.7.11.1 McBSP Electrical Data and Timing
Table 5-47. Timing Requirements for McBSP, DVDDIO 1.8 V (see Figure 5-34)
CVDD = 1.05 V
DVDDIO 1.8 V
MAX
CVDD = 1.3/1.4 V
NO.
UNIT
MIN
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
15
9
ns
ns
Pulse duration, CLKR/X high or CLKR/X
low
P-1(1)
P-1(1)
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
29.5
3.5
4.5
4.5
18.5
2.5
-4
29.5
3.5
4.5
4.5
18.5
2.5
-4
Setup time, external FSR high before
CLKR low
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
ns
ns
ns
ns
ns
ns
Hold time, external FSR high after CLKR
low
7
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
8
5.5
26.5
7.5
0.5
2.5
5.5
26.5
7.5
0.5
2.5
Setup time, external FSX high before
CLKX low
10
11
Hold time, external FSX high after CLKX
low
(1) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 5-48. Timing Requirements for McBSP,
DVDDIO 3.3/2.75 V (see Figure 5-34)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO.
DVDDIO 3.3/2.75 V
UNIT
MIN
MAX
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
18
9
ns
ns
Pulse duration, CLKR/X high or CLKR/X
low
P-1(1)
P-1(1)
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
24
4
24
4
Setup time, external FSR high before
CLKR low
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
ns
ns
ns
ns
ns
ns
4
4
Hold time, external FSR high after CLKR
low
5
5
22.5
2.5
-3
6
22.5
2.5
-3
6
7
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
8
23
7
23
7
Setup time, external FSX high before
CLKX low
10
11
2
2
Hold time, external FSX high after CLKX
low
3
3
(1) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 5-49. Switching Characteristics Over Recommended Operating Conditions for McBSP,
DVDDIO 1.8 V
(see Figure 5-34)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO.
PARAMETER
DVDDIO 1.8 V
UNIT
MIN
5.5
MAX
MIN
5.5
MAX
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
2
3
td(CKSH-CKRXH)
tc(CKRX)
25
25
ns
ns
ns
Cycle time, CLKR/X
CLKR/X int
15
9
Pulse duration, CLKR/X high or
CLKR/X low
tw(CKRX)
CLKR/X int
C+2(1)
C+2(1)
Delay time, CLKR high to internal
FSR valid
4
9
td(CKRH-FRV)
td(CKXH-FXV)
CLKR int
-6.5
6
-6.5
6
ns
ns
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
-2
4
1
23
-2
4
1
23
Delay time, CLKX high to internal
FSX valid
-5
3
-5
3
Disable time, DX high impedance
following last data bit from CLKX high
12
13
tdis(CKXH-DXHZ)
ns
ns
3
24.5
4
3
24.5
4
-4.5
3.5
-4
-4.5
3.5
-4
td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
25.5
4
25.5
4
14
td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-2
3
-2
3
(1) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse duration = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse duration = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
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Table 5-50. Switching Characteristics Over Recommended Operating Conditions for McBSP,
DVDDIO 3.3/2.75 V
(see Figure 5-34)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO.
PARAMETER
DVDDIO 3.3/2.75 V
UNIT
MIN
4.25
18
MAX
MIN
4.5
MAX
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
2
3
td(CKSH-CKRXH)
tc(CKRX)
24
24
ns
ns
ns
Cycle time, CLKR/X
CLKR/X int
9
Pulse duration, CLKR/X high or
CLKR/X low
tw(CKRX)
CLKR/X int
C-2(1)
C-2(1)
Delay time, CLKR high to internal
FSR valid
4
9
td(CKRH-FRV)
td(CKXH-FXV)
CLKR int
-4
8
-4
8
ns
ns
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
-2
3.5
-2.5
3
2
20
4
-2
3.5
-2.5
-3
2
20
4
Delay time, CLKX high to internal
FSX valid
Disable time, DX high impedance
following last data bit from CLKX high
12
13
tdis(CKXH-DXHZ)
ns
ns
21
5
21
5
-2.5
3
-2.5
3
td(CKXH-DXV)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
22.5
4
22.5
4
-1.5
-1.5
14
td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
-1.5
3.5
-1.5
3.5
(1) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse duration = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse duration = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
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CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
(A)
13
14
13
(A)
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
B. McBSP_CLKS and McBSP_CLKR are shared on the same pin. See Table 4-7, Multichannel Buffered Serial Ports
(McBSP) Signal Descriptions, for how each is selected.
Figure 5-34. McBSP Timing
Table 5-51. Timing Requirements for FSR When GSYNC = 1 (see Figure 5-35)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO.
DVDDIO 3.3/2.75/1.8 V
UNIT
MIN
5
MAX
MIN
5
MAX
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
4
4
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 5-35. FSR Timing When GSYNC = 1
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5.7.12 Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC)
The device includes two MMC and SD controllers which are compliant with eMMC V4.3, MMC V3.31,
Secure Digital Part 1 Physical Layer Specification V2.0, and Secure Digital Input Output (SDIO) V2.0
specifications. The MMC and SD card controller supports these industry standards and assumes the
reader is familiar with these standards.
Each MMC and SD Controller in the device has the following features:
•
•
•
•
Multimedia Card and Secure Digital (eMMC, MMC, SD, and SDHC) protocol support
Programmable clock frequency
256-bit Read and Write FIFO to lower system overhead
Slave DMA transfer capability
The MMC and SD card controller transfers data between the CPU and DMA controller on one side and
MMC and SD card on the other side. The CPU and DMA controller can read and write the data in the card
by accessing the registers in the MMC and SD controller.
The MMC and SD controller on this device, does not support the SPI mode of operation.
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5.7.12.1 MMC and SD Electrical Data and Timing
Table 5-52. Timing Requirements for MMC and SD (see Figure 5-36 and Figure 5-39)
CVDD = 1.3/1.4 V CVDD = 1.05 V
FAST MODE STD MODE
NO
.
UNIT
MIN
3
MAX
MIN
3
MAX
1
2
3
4
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, MMCx_CMD data input valid before MMCx_CLK high
Hold time, MMCx_CMD data input valid after MMCx_CLK high
Setup time, MMC_Dx data input valid before MMCx_CLK high
Hold time, MMC_Dx data input valid after MMCx_CLK high
ns
ns
ns
ns
3
3
3
3.1
3
3
Table 5-53. Switching Characteristics Over Recommended Operating Conditions for MMC Output(1) (see
Figure 5-36 and Figure 5-39)
CVDD = 1.3/1.4 V CVDD = 1.05 V
FAST MODE STD MODE
NO
.
PARAMETER
UNIT
MIN
0
MAX
50(2)
MIN
0
MAX
25(2) MHz
7
8
9
f(CLK)
Operating frequency, MMCx_CLK
Identification mode frequency, MMCx_CLK
Pulse duration, MMCx_CLK low
Pulse duration, MMCx_CLK high
Rise time, MMCx_CLK
f(CLK_ID)
tw(CLKL)
0
400
0
400 kHz
7
10
10
ns
ns
10 tw(CLKH)
11 tr(CLK)
12 tf(CLK)
7
3
3
3
3
ns
ns
ns
ns
ns
ns
Fall time, MMCx_CLK
13 td(MDCLKL-CMDIV) Delay time, MMCx_CLK low to MMC_CMD data output invalid
14 td(MDCLKL-CMDV) Delay time, MMCx_CLK low to MMC_CMD data output valid
15 td(MDCLKL-DATIV) Delay time, MMCx_CLK low to MMC_Dx data output invalid
-4.53
-4.53
-4.77
-4.77
4.1
4.1
5.4
5.4
16 td(MDCLKL-DATV)
Delay time, MMCx_CLK low to MMC_Dx data output valid
(1) For MMC and SD, the parametric values are measured at DVDDIO = 3.3 V and 2.75 V.
(2) Use this value or SYS_CLK/2 whichever is smaller.
7
9
10
MMCx_CLK
13
14
VALID
MMCx_CMD
Figure 5-36. MMC and SD Host Command Write Timing
9
10
7
MMCx_CLK
MMCx_Dx
4
4
3
Start
3
D0
D1
Dx
End
Figure 5-37. MMC and SD Card Response Timing
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9
10
7
MMCx_CLK
MMCx_CMD
1
2
START
XMIT
Valid
Valid
Valid
END
Figure 5-38. MMC and SD Host Write Timing
7
9
10
MMCx_CLK
MMCx_DAT
16
15
VALID
Figure 5-39. MMC and SD Data Write Timing
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5.7.13 Real-Time Clock (RTC)
The device includes a Real-Time Clock (RTC) with its own separate power supply and isolation circuits.
The RTC has the capability to wake up the device from idle states via alarms, periodic interrupts, or an
external WAKEUP input.
To prevent unintentional access to the RTC registers, gate-keeper registers must be programmed with a
specific signature—0x95A4_F1E0—before changing the RTC registers.
Note: The RTC Core (CVDDRTC) must be powered by an external power source even though RTC is not
used. None of the on-chip LDOs can power CVDDRTC
.
The device RTC provides the following features:
•
•
100-year calendar up to year 2099.
Counts milliseconds, seconds, minutes, hours, day of the week, date, month, and year with leap year
compensation
•
•
•
•
•
•
•
•
•
Millisecond time correction
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
24-hour clock mode
Second, minute, hour, or day alarm interrupt
Periodic interrupt: every millisecond, second, minute, hour, or day
Alarm interrupt: precise time of day
Single interrupt to the DSP CPU
32.768-kHz crystal oscillator with frequency calibration
Bidirectional IO pin that can be set up as:
–
–
Input for an external device to wake up the DSP
Output to wake up an external device
Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 6-19). Note
that any write to these registers will be synchronized to the RTC 32.768-kHz clock; thus, the CPU must
run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two 32.768-
kHz clock cycles later.
Furthermore, three conditions must be met to write to the RTC registers:
1. The RTC oscillator must be enabled.
2. A 1 must be written to the RTC system control register (RSCR) to bring the RTC out of isolation.
3. The gate-keeper registers (RGKR_LSW and RGKR_MSW) must contain the key 0x95A4_F1E0.
If these conditions are not met, the RTC remains isolated and protected from power glitches.
For more information, see the Static Power Management section of the TMS320C5517 Digital Signal
Processor Technical Reference Manual [literature number SPRUH16].
The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain
when power is first applied to the CVDDRTC power pin. The RTC flops are not reset by the device's RESET
pin nor the digital core's POR (powergood signal).
The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track
of when the DSP boots and whether the RTC time registers have already been initialized to the current
clock time or whether the software needs to go into a routine to prompt the user to set the time and date.
5.7.13.1 RTC Electrical Data and Timing
For more detailed information on RTC electrical timings, specifically WAKEUP, see Section 5.7.3.3, Reset
Electrical Data and Timing.
136
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5.7.14 SAR ADC (10-Bit)
The device includes a 10-bit SAR ADC using a switched capacitor architecture which converts an analog
input signal to a digital value at a maximum rate of 62.5-k samples per second (ksps) for use by the DSP.
This SAR module supports six channels that are connected to four general purpose analog pins (GPAIN
[3:0]) which can be used as general purpose outputs.
The device SAR supports the following features:
•
•
•
•
•
Up to 62.5 ksps (2-MHz clock with 32 cycles per conversion)
Single conversion and continuous back-to-back conversion modes
Interrupt driven or polling conversion or DMA event generation
Internal configurable bandgap reference voltages of 1 V or 0.8 V; or external Vref of VDDA_ANA
One 3.6-V Tolerant analog input (GPAIN0) with internal voltage division for conversion of battery
voltage
•
•
Software controlled power down
Individually configurable general-purpose digital outputs
5.7.14.1 SAR ADC Electrical Data and Timing
Table 5-54. Switching Characteristics Over Recommended Operating Conditions for ADC Characteristics
CVDD = 1.4 V
CVDD = 1.3 V
CVDD = 1.05 V
NO.
PARAMETER
UNIT
MIN
TYP
MAX
2
1
3
4
5
6
7
8
9
tC(SCLC)
td(CONV)
SDNL
SINL
Cycle time, ADC internal conversion clock
Delay time, ADC conversion time
Static differential non-linearity error (DNL measured for 9 bits)
Static integral non-linearity error
MHz
ns
32tC(SCLC)
±0.6
±1
LSB
LSB
LSB
LSB
MΩ
dB
Zset
Zero-scale offset error (INL measured for 9 bits)
Full-scale offset error
2
2
Fset
Analog input impedance
1
Signal-to-noise ratio
54
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5.7.15 Serial Port Interface (SPI)
The device serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a
serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The
SPI can operate as a master device only, slave mode is not supported. Note: The SPI is not supported by
the device DMA controller, so DMA cannot be used in transferring data between the SPI and the on-chip
RAM.
The SPI is normally used for communication between the DSP and external peripherals. Typical
applications include an interface to external I/O or peripheral expansion via devices such as shift registers,
display drivers, SPI EEPROMs, and analog-to-digital converters.
The SPI has the following features:
•
•
•
•
•
•
•
•
•
•
•
Programmable divider for serial data clock generation
Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX)
Programmable data length (1 to 32 bits)
4 external chip select signals
Programmable transfer or frame size (1 to 4096 characters)
Optional interrupt generation on character completion
Optional interrupt generation on frame completion
Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles
Programmable signal polarities
Programmable active clock edge
Internal loopback mode for testing
5.7.15.1 SPI Electrical Data and Timing
Table 5-55. Timing Requirements for SPI Inputs (see Figure 5-40 through Figure 5-43)
CVDD = 1.3/1.4
CVDD = 1.05 V
V
NO.
UNIT
MIN
4P(1)(2)
30
MAX
MIN
4P(1)(2)
MAX
4
5
6
tC(SCLK)
tw(SCLKH)
tw(SCLKL)
Cycle time, SPI_CLK
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPI_CLK high
19
Pulse duration, SPI_CLK low
30
19
Setup time, SPI_RX valid before SPI_CLK high
Setup time, SPI_RX valid before SPI_CLK low
Hold time, SPI_RX valid after SPI_CLK high
Hold time, SPI_RX valid after SPI_CLK low
Modes 0, 2, and 3
Mode 1
16.1
16.1
0
13.9
13.9
0
tsu(SRXV-
SCLK)
7
8
Modes 0 and 3
Modes 1 and 2
th(SCLK-SRXV)
0
0
(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
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Table 5-56. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs [I/O =
2.75 and 3.3 V]
(see Figure 5-40 through Figure 5-43)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO
.
UNI
T
PARAMETER
MIN
-4.2
-4.2
MAX
MIN
-4.9
-4.9
MAX
Delay time, SPI_CLK low to SPI_TX valid
Delay time, SPI_CLK high to SPI_TX valid
Modes 0 and 3
Modes 1 and 2
8.9
8.9
5.3 ns
5.3 ns
1
td(SCLK-STXV)
tc - 8 +
D(1)
tc - 8 +
D(1)
2
3
td(SPICS-SCLK) Delay time, SPI_CS active to SPI_CLK active
toh(SCLKI-
ns
ns
0.5tc -
1.9
0.5tc -
1.9
Output hold time, SPI_CS inactive to SPI_CLK inactive
SPICSI)
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
Table 5-57. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs [I/O =
1.8 V]
(see Figure 5-40 through Figure 5-43)
CVDD = 1.05 V
CVDD = 1.3/1.4 V
NO
.
UNI
T
PARAMETER
MIN
-6.7
-6.7
MAX
MIN
-6.7
-6.7
MAX
Delay time, SPI_CLK low to SPI_TX valid
Delay time, SPI_CLK high to SPI_TX valid
Modes 0 and 3
Modes 1 and 2
8.9
8.9
5.8 ns
5.8 ns
1
td(SCLK-STXV)
tc - 9.2 +
D(1)
tc - 8 +
D(1)
2
3
td(SPICS-SCLK) Delay time, SPI_CS active to SPI_CLK active
toh(SCLKI-
ns
ns
0.5tc -
1.9
0.5tc -
1.9
Output hold time, SPI_CS inactive to SPI_CLK inactive
SPICSI)
(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
4
5
6
SPI_CLK
SPI_TX
1
Bn-2
Bn-2
Bn-1
Bn-1
B0
B0
B1
B1
SPI_RX
SPI_CS
7
8
2
3
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-40. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
4
5
6
SPI_CLK
SPI_TX
SPI_RX
1
2
Bn-2
Bn-2
Bn-1
Bn-1
B0
B1
B1
B1
7
8
3
SPI_CS
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-41. SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1)
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4
5
6
SPI_CLK
1
B0
B0
B1
B1
Bn-2
Bn-2
Bn-1
Bn-1
SPI_TX
SPI_RX
3
7
8
2
SPI_CS
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-42. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0)
4
6
5
SPI_CLK
SPI_TX
SPI_RX
SPI_CS
1
2
Bn-2
Bn-2
Bn-1
Bn-1
B0
B0
B1
B1
7
8
3
A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.
B. Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-43. SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1)
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5.7.16 Timers
The device has three 32-bit software programmable Timers. Each timer can be used as a general-
purpose (GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both. General-
purpose timers are typically used to provide interrupts to the CPU to schedule periodic tasks or a delayed
task. A watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP timers are 32-
bit timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as a reference
clock. These timers can be used to generate periodic interrupts. The Watchdog Timer is a 16-bit counter
with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
The device Timers support the following:
•
•
•
32-bit Programmable Countdown Timer
13-bit Prescaler Divider
Timer Modes:
–
–
32-bit General-Purpose Timer
32-bit Watchdog Timer (Timer2 only)
•
•
Auto Reload Option
Generates a single interrupt to the CPU, which can be configured as a timer interrupt (TINT) or as a
non-maskable interrupt (NMI). The interrupt is individually latched to determine which timer triggered
the interrupt.
•
•
Generates an active low pulse to the hardware reset (Watchdog only)
Interrupt can be used for DMA Event
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5.7.17 Universal Asynchronous Receiver and Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from an external peripheral device and
parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.
The device has one UART peripheral with the following features:
•
•
Programmable baud rates (frequency pre-scale values from 1 to 65535)
Fully programmable serial interface characteristics:
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no PARITY bit generation and detection
1, 1.5, or 2 STOP bit generation
•
16-byte depth transmitter and receiver FIFOs:
–
–
The UART can be operated with or without the FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
•
•
•
•
•
DMA signaling capability for both received and transmitted data
CPU interrupt capability for both received and transmitted data
False START bit detection
Line break generation and detection
Internal diagnostic capabilities:
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Programmable autoflow control using CTS and RTS signals
5.7.17.1 UART Electrical Data and Timing [Receive and Transmit]
Table 5-58. Timing Requirements for UART Receive(1)(2) (see Figure 5-44)
CVDD = 1.05/1.3/1.4 V
NO.
UNIT
MIN
U - 3.5
U - 3.5
MAX
U + 3
U + 3
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (UART_RXD) [15/30 pF]
Pulse duration, receive start bit [15/30 pF]
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
(2) These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 1.8 V.
Table 5-59. Switching Characteristics Over Recommended Operating Conditions
for UART Transmit(1) (2)
(see Figure 5-44)
CVDD = 1.05/1.3/1.4 V
NO.
PARAMETER
UNIT
MIN
MAX
fmax/16
1
2
3
f(baud)
Maximum programmable bit rate
MHz
ns
tw(UTXDB)
tw(UTXSB)
Pulse duration, transmit data bit (UART_TXD) [15/30 pF]
Pulse duration, transmit start bit [15/30 pF]
U - 3.5
U - 3.5
U + 4
U + 4
ns
(1) U = UART baud time = 1/programmed baud rate.
(2) These parametric values are measured at DVDDIO = 3.3 V, 2.75 V, and 1.8 V.
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3
2
Start
Bit
UART_TXD
Data Bits
5
4
Start
Bit
UART_RXD
Data Bits
Figure 5-44. UART Transmit and Receive Timing
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5.7.18 Universal Host-Port Interface (UHPI)
The device includes a user-configurable 16-bit universal host-port interface (UHPI16). The UHPI provides
a parallel port interface through which an external host processor can directly access the processor's
resources (configuration and program and data memories). The external host device is asynchronous to
the CPU clock and functions as a master to the UHPI interface. The UHPI enables a host device and the
processor to exchange information via internal memory. Dedicated address (UHPIA) and data (UHPID)
registers within the UHPI provide the data path between the external host interface and the processor
resources. A UHPI control register (UHPIC) is available to the host and the CPU for various configuration
and interrupt functions.
5.7.18.1 UHPI Electrical Data and Timing
Table 5-60. Timing Requirements for Host-Port Interface, DVDDIO = 3.3/2.75 V
DVDDIO = 3.3/2.75 V
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
6.5
3
MAX
MIN
5
MAX
1
2
3
tsu(SELV-HSTBL) Setup time, select signals(1) valid before HSTROBE low
ns
ns
ns
th(HSTBL-SELV)
tw(HSTBL)
Hold time, select signals(1) valid after HSTROBE low
2
Pulse duration, HSTROBE active low
19
17
Pulse duration, HSTROBE inactive high between consecutive
accesses
4
tw(HSTBH)
2P(2)
2P(2)
ns
11 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
7.8
3.3
5
ns
ns
12 th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2.5
Hold time, HSTROBE high after UHPI_HRDY high. HSTROBE
13 th(HRDYL-HSTBH) should not be inactivated until UHPI_HRDY is active (high);
otherwise, UHPI writes will not complete properly.
2
2
ns
(1) Select signals include: UHPI_HCNTL[1:0], UHPI_HR_NW and UHPI_HHWIL.
(2) P = SYSCLK period in ns. For example, when the CPU core is clocked at 200 MHz, P = 5 ns.
Table 5-61. Timing Requirements for Host-Port Interface, DVDDIO = 1.8 V
DVDDIO = 1.8 V
NO.
CVDD = 1.05 V
CVDD = 1.3/1.4 V
UNIT
MIN
7.3
3
MAX
MIN
5
MAX
1
2
3
tsu(SELV-HSTBL) Setup time, select signals(1) valid before HSTROBE low
ns
ns
ns
th(HSTBL-SELV)
tw(HSTBL)
Hold time, select signals(1) valid after HSTROBE low
2
Pulse duration, HSTROBE active low
24
19
Pulse duration, HSTROBE inactive high between consecutive
accesses
4
tw(HSTBH)
2P(2)
2P(2)
ns
11 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high
8.6
3.3
5
ns
ns
12 th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2.5
Hold time, HSTROBE high after UHPI_HRDY high. HSTROBE
13 th(HRDYL-HSTBH) should not be inactivated until UHPI_HRDY is active (high);
otherwise, UHPI writes will not complete properly.
2
2
ns
(1) Select signals include: UHPI_HCNTL[1:0], UHPI_HR_NW and UHPI_HHWIL.
(2) P = SYSCLK period in ns. For example, when the CPU core is clocked at 200 MHz, P = 5 ns.
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Table 5-62. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface,
DVDDIO = 3.3/2.75 V
DVDDIO = 3.3/2.75 V
CVDD = 1.05
V
CVDD
1.3/1.4 V
=
NO.
PARAMETER
UNIT
MIN
MAX
MIN MAX
For UHPI Write, UHPI_HRDY can go
low (not ready) for these UHPI Write
conditions; otherwise, UHPI_HRDY
stays high (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
For UHPI Read, UHPI_HRDY can go
low (not ready) for these UHPI Read
conditions:
Case 1: UHPID read (with auto-
increment) and data not in Read FIFO
(can only happen to first half-word of
HPID access)
Delay time, HSTROBE low to
UHPI_HRDY valid
5
td(HSTBL-HRDYV)
0
22.3
0
15.5
ns
Case 2: First half-word access of HPID
Read without auto-increment
For UHPI Read, UHPI_HRDY stays
high (ready) for these UHPI Read
conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without auto-
increment and data is already in Read
FIFO (always applies to second half-
word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6
7
ten(HSTBL-HDLZ)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDHZ)
Enable time, UHPI_HD driven from HSTROBE low
Delay time, UHPI_HRDY high to HD valid
1.5
1.5
1.5
1.5
ns
ns
ns
ns
0
1.1
8
Output hold time, UHPI_HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
14
24.3
15.8
For UHPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is already
in Read FIFO
Delay time, HSTROBE low to
HD valid
15
td(HSTBL-HDV)
24.3
15.8
ns
Case 3: Second half-word of HPID
read with or without auto-increment
For UHPI Write, UHPI_HRDY can go
low (not ready) for these UHPI Write
conditions; otherwise, UHPI_HRDY
stays high (ready):
Case 1: HPID write when Write FIFO is
full (can happen to either half-word)
Case 2: HPIA write (can happen to
either half-word)
Delay time, HSTROBE high to
UHPI_HRDY valid
18
td(HSTBH-HRDYV)
24.3
15.8
ns
Case 3: HPID write without auto-
increment (only happens to second
half-word)
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Table 5-63. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface,
DVDDIO = 1.8 V
DVDDIO = 1.8 V
CVDD = 1.05
V
CVDD
1.3/1.4 V
=
NO.
PARAMETER
UNIT
MIN
MAX
MIN MAX
For UHPI Write, UHPI_HRDY can go
low (not ready) for these UHPI Write
conditions; otherwise, UHPI_HRDY
stays high (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second
half-word)
Case 4: HPIA write and Write FIFO not
empty
For UHPI Read, UHPI_HRDY can go
low (not ready) for these UHPI Read
conditions:
Case 1: UHPID read (with auto-
increment) and data not in Read FIFO
(can only happen to first half-word of
HPID access)
Delay time, HSTROBE low to
UHPI_HRDY valid
5
td(HSTBL-HRDYV)
0
26.5
0
19
ns
Case 2: First half-word access of HPID
Read without auto-increment
For UHPI Read, UHPI_HRDY stays
high (ready) for these UHPI Read
conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without auto-
increment and data is already in Read
FIFO (always applies to second half-
word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
6
7
ten(HSTBL-HDLZ)
td(HRDYL-HDV)
toh(HSTBH-HDV)
tdis(HSTBH-HDHZ)
Enable time, UHPI_HD driven from HSTROBE low
Delay time, UHPI_HRDY high to HD valid
1.5
1.5
1.5
1.5
ns
ns
ns
ns
1.1
1.1
8
Output hold time, UHPI_HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
14
26.8
20.5
For UHPI Read. Applies to conditions
where data is already residing in HPID
or FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is already
in Read FIFO
Delay time, HSTROBE low to
HD valid
15
td(HSTBL-HDV)
26.8
20.5
ns
Case 3: Second half-word of HPID
read with or without auto-increment
For UHPI Write, UHPI_HRDY can go
low (not ready) for these UHPI Write
conditions; otherwise, UHPI_HRDY
stays high (ready):
Case 1: HPID write when Write FIFO is
full (can happen to either half-word)
Case 2: HPIA write (can happen to
either half-word)
Delay time, HSTROBE high to
UHPI_HRDY valid
18
td(HSTBH-HRDYV)
26.5
19
ns
Case 3: HPID write without auto-
increment (only happens to second
half-word)
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UHPI_HCS
(D)
UHPI_HAS
2
2
1
1
1
1
1
1
UHPI_HCNTL[1:0]
UHPI_HR_NW
UHPI_HHWIL
2
2
2
2
4
3
3
(A)(C)
HSTROBE
15
15
14
14
8
6
8
6
UHPI_HD[15:0]
(output)
13
7
1st Half-Word
2nd Half-Word
5
(B)
UHPI_HRDY
A. HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1
XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
For more information on the UHPI peripheral, see the UHPI chapter in the TMS320C5517 Technical Reference
Manual [literature number SPRUH16].
C. Typical UHPI_HCS behavior is reflected when HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2.
UHPI_HCS timing requirements are reflected by parameters for HSTROBE.
D. For proper UHPI operation, UHPI_HAS must be pulled up via an external resistor.
Figure 5-45. UHPI Read Timing (UHPI_HAS Not Used, Tied High)
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UHPI_HCS
(D)
UHPI_HAS
1
1
1
1
2
2
2
UHPI_HCNTL[1:0]
1
2
UHPI_HR_NW
1
2
2
3
UHPI_HHWIL
3
4
(A)(C)
HSTROBE
11
11
12
12
UHPI_HD[15:0]
(input)
1st Half-Word
2nd Half-Word
18
5
18
13
13
5
(B)
UHPI_HRDY
A. HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1
XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
For more information on the UHPI peripheral, see the UHPI chapter in the TMs320C5517 Technical Reference
Manual [literature number SPRUH16].
C. Typical UHPI_HCS behavior is reflected when HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2.
UHPI_HCS timing requirements are reflected by parameters for HSTROBE.
D. For proper UHPI operation, UHPI_HAS must be pulled up via an external resistor.
Figure 5-46. UHPI Write Timing (UHPI_HAS Not Used, Tied High)
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5.7.19 Universal Serial Bus (USB) 2.0 Controller
The device USB2.0 peripheral supports the following features:
•
•
•
•
USB2.0 peripheral at speeds high-speed (480Mb/s) and full-speed (12Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous mode)
4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable size
•
•
Integrated USB2.0 High Speed PHY
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB2.0 peripheral on this device, does not support:
•
•
•
Host Mode (Peripheral and Device Modes supported only)
On-Chip Charge Pump
On-the-Go (OTG) Mode
5.7.19.1 USB 2.0 Electrical Data and Timing
Table 5-64. Switching Characteristics Over Recommended Operating Conditions for USB 2.0 (see
Figure 5-47)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
PARAMETER
UNIT
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps(1)
MIN
4
MAX
MIN
0.5
0.5
–
MAX
1
2
tr(D)
Rise time, USB_DP and USB_DM signals(2)
Fall time, USB_DP and USB_DM signals(2)
Rise and Fall time, matching(3)
Output signal cross-over voltage(2)
Pulse duration, EOP transmitter(4)
Pulse duration, EOP receiver(4)
Data Rate
20
20
ns
ns
%
V
tf(D)
4
3
trfM
90
1.3
160
82
111
2
–
–
–
4
VCRS
tw(EOPT)
tw(EOPR)
t(DRATE)
ZDRV
ZINP
–
7
175
–
ns
ns
8
–
9
12
480 Mb/s
10
11
Driver Output Resistance
40.5
49.5
40.5
-
49.5
-
Ω
Ω
Receiver Input Impedance
100k
(1) For more detailed information, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7.
(2) Full Speed and High Speed CL = 50 pF
(3) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(4) Must accept as valid EOP
t t
per - jr
USB_DM
V
90% V
OH
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 5-47. USB2.0 Integrated Transceiver Interface Timing
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5.7.20 Emulation and Debug
5.7.20.1 Debugging Considerations
5.7.20.1.1 Pullup and Pulldown Resistors
Proper board design should ensure that input pins to the DSP are always at a valid logic level and not
floating. This may be achieved via pullup and pulldown resistors. The DSP features internal pullup (IPU)
and internal pulldown (IPD) resistors on many pins to eliminate the need, unless otherwise noted, for
external pullup and pulldown resistors.
An external pullup and pulldown resistor may need to be used in the following situations:
•
•
•
Configuration Pins: An external pullup and pulldown resistor is recommended to set the desired value
or state (see the configuration pins listed in Table 5-5, Default Functions Affected by Device
Configuration Pins). Note that some configuration pins must be connected directly to ground or to a
specific supply voltage.
Input Pins (I, I/O, I/O/Z): They are required to be driven at all times. To achieve the lowest power, input
pins must not be allowed to float. When they are configured as input or tri-stated, and not driven to a
known state, they may cause an excessive IO-supply current. Prevent this current by externally
terminating it or enabling IPD and IPU, if applicable.
Other Input Pins: If the IPU and IPD does not match the desired value or state, use an external pullup
and pulldown resistor to pull the signal to the opposite rail.
For the configuration pins (listed in Table 5-5, Default Functions Affected by Device Configuration Pins), if
they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup and
pulldown resistor be implemented. In addition, applying external pullup and pulldown resistors on the
configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.
When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor
should be disabled through the Pullup and Pulldown Inhibit Registers (PUDINHIBR1, 2, 3, 4, 5, 6, and 7)
to minimize power consumption.
Tips for choosing an external pullup and pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown (IPU and IPD) resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup and pulldown resistor with the largest possible value; but, which can still ensure that the
net will reach the target pulled value when maximum current from all devices on the net is flowing
through the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup and pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU and IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU and IPD on the configuration pins
while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
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For more detailed information on input current (II), and the low- and high-level input voltages (VIL and VIH)
for the device DSP, see Section 5.3.2, Electrical Characteristics.
For the internal pullup and pulldown resistors for all device pins, see the peripheral and system-specific
signal descriptions table in this document.
5.7.20.1.2 Bus Holders
The device has special I/O bus-holder structures to ensure pins are not left floating when CVDD power is
removed while I/O power is applied. When CVDD is "ON", the bus-holders are disabled and the internal
pullups or pulldowns, if applicable, function normally. But when CVDD is "OFF" and the I/O supply is "ON",
the bus-holders become enabled and any applicable internal pullups and pulldowns are disabled.
The bus-holders are weak drivers on the pin and, for as long as CVDD is "OFF" and I/O power is "ON",
they hold the last state on the pin. If an external device is strongly driving the device I/O pin to the
opposite state then the bus-holder will flip state to match the external driver and DC current will stop.
This bus-holder feature prevents unnecessary power consumption when CVDD is "OFF"and I/O supply is
"ON". For example, current caused by undriven pins (input buffer oscillation) or DC current flowing through
pullups or pulldowns.
If external pullup or pulldown resistors are implemented, then care should be taken that those pullup and
pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to
flip state to match the state of the external pullup or pulldown. Otherwise, DC current will flow
unnecessarily. When CVDD power is applied, the bus holders are disabled (for further details on bus
holders, see Section 5.7.2.3, Digital I/O Behavior When Core Power (CVDD) is Down).
5.7.20.1.3 CLKOUT Pin
For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the
clock generator. The SRC bits of the CLKOUT Configuration Register (CLKOUTCR) can be used to
specify the source for the CLKOUT pin.
Note: The bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register.
For more information on the ST3_55 CPU register, see the C55x 3.0 CPU Reference Guide (literature
number: SWPU073).
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5.7.21 IEEE 1149.1 JTAG
The JTAG interface is used for Boundary-Scan testing and emulation of the device.
TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
The device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be
asserted upon power up and the device's internal emulation logic will always be properly initialized. An
external pulldown should also be added to ensure proper device operation when an emulation or
boundary scan JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas
Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST
high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert
TRST to initialize the device after powerup and externally drive TRST high before attempting any
emulation or boundary scan operations. The device will not operate properly if TRST is not asserted low
during powerup.
5.7.21.1 JTAG Test_port Electrical Data and Timing
Table 5-65. Timing Requirements for JTAG Test Port (see Figure 5-48)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
UNIT
MIN
60
24
24
10
6
MAX
2
3
4
5
6
7
8
tc(TCK)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
tw(TCKH)
Pulse duration, TCK high
tw(TCKL)
Pulse duration, TCK low
tsu(TDIV-TCKH)
tsu(TMSV-TCKH)
th(TCKH-TDIV)
th(TCKH-TDIV)
Setup time, TDI valid before TCK high
Setup time, TMS valid before TCK high
Hold time, TDI valid after TCK high
Hold time, TMS valid after TCK high
5
4
Table 5-66. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-48)
CVDD = 1.05 V
CVDD = 1.3 V
CVDD = 1.4 V
NO.
PARAMETER
UNIT
MIN
MAX
1
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
30.5
ns
2
3
4
TCK
TDO
1
1
7
8
5
6
TDI
TMS
Figure 5-48. JTAG Test-Port Timing
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6 Detailed Description
6.1 CPU
This fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation processor core.
The C55x DSP architecture achieves high performance and low power through increased parallelism and
total focus on power savings. The CPU supports an internal bus structure that is composed of one
program bus, three data read buses (one 32-bit data read bus and two 16-bit data read buses), two 16-bit
data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the
ability to perform up to four data reads and two data writes in a single cycle. Each DMA controller can
perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an
additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize
parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data
Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a
128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit
decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.
For more detailed information on the CPU, see the C55x CPU 3.0 CPU Reference Guide [literature
number SWPU073].
The C55x core of the device can address 16M bytes of unified data and program space. The core also
addresses 64K words of I/O space and includes three types of on-chip memory: 128 KB read-only
memory (ROM), 256 KB single-access random access memory (SARAM), 64 KB dual-access random
access memory (DARAM). The memory map is shown in Figure 6-1 .
6.2 Memory
6.2.1 Internal Memory
6.2.1.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h - 00FFFFh and is composed of eight blocks of
4K words each (see Table 6-1). Each DARAM block can support two accesses per cycle (two reads, two
writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.
Table 6-1. DARAM Blocks
CPU
DMA CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
BYTE ADDRESS RANGE
000000h – 001FFFh
002000h – 003FFFh
004000h – 005FFFh
006000h – 007FFFh
008000h – 009FFFh
00A000h – 00BFFFh
00C000h – 00DFFFh
00E000h – 00FFFFh
0001 0000h – 0001 1FFFh
0001 2000h – 0001 3FFFh
0001 4000h – 0001 5FFFh
0001 6000h – 0001 7FFFh
0001 8000h – 0001 9FFFh
0001 A000h – 0001 BFFFh
0001 C000h – 0001 DFFFh
0001 E000h – 0001 FFFFh
DARAM 0(1)
DARAM 1
DARAM 2
DARAM 3
DARAM 4
DARAM 5
DARAM 6
DARAM 7
(1) The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 6-1 , Memory Map
Summary.
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6.2.1.2 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of
4K words each (see Table 6-2). Each SARAM block can support one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed
by the USB DMA buses.
Table 6-2. SARAM Blocks
CPU
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
BYTE ADDRESS RANGE
010000h - 011FFFh
012000h - 013FFFh
014000h - 015FFFh
016000h - 017FFFh
018000h - 019FFFh
01A000h - 01BFFFh
01C000h - 01DFFFh
01E000h - 01FFFFh
020000h - 021FFFh
022000h - 023FFFh
024000h - 025FFFh
026000h - 027FFFh
028000h - 029FFFh
02A000h - 02BFFFh
02C000h - 02DFFFh
02E000h - 02FFFFh
030000h - 031FFFh
032000h - 033FFFh
034000h - 035FFFh
036000h - 037FFFh
038000h - 039FFFh
03A000h - 03BFFFh
03C000h - 03DFFFh
03E000h - 03FFFFh
040000h – 041FFFh
042000h – 043FFFh
044000h – 045FFFh
046000h – 047FFFh
048000h – 049FFFh
04A000h – 04BFFFh
04C000h – 04DFFFh
04E000h – 04FFFFh
0009 0000h – 0009 1FFFh
0009 2000h – 0009 3FFFh
0009 4000h – 0009 5FFFh
0009 6000h – 0009 7FFFh
0009 8000h – 0009 9FFFh
0009 A000h – 0009 BFFFh
0009 C000h – 0009 DFFFh
0009 E000h – 0009 FFFFh
000A 0000h – 000A 1FFFh
000A 2000h – 000A 3FFFh
000A 4000h – 000A 5FFFh
000A 6000h – 000A 7FFFh
000A 8000h – 000A 9FFFh
000A A000h – 000A BFFFh
000A C000h – 000A DFFFh
000A E000h – 000A FFFFh
000B 0000h – 000B 1FFFh
000B 2000h – 000B 3FFFh
000B 4000h – 000B 5FFFh
000B 6000h – 000B 7FFFh
000B 8000h – 000B 9FFFh
000B A000h – 000B BFFFh
000B C000h – 000B DFFFh
000B E000h – 000B FFFFh
000C 0000h – 000C 1FFFh
000C 2000h – 000C 3FFFh
000C 4000h – 000C 5FFFh
000C 6000h – 000C 7FFFh
000C 8000h – 000C 9FFFh
000C A000h – 000C BFFFh
000C C000h – 000C DFFFh
000C E000h – 000C FFFFh
SARAM 0
SARAM 1
SARAM 2
SARAM 3
SARAM 4
SARAM 5
SARAM 6
SARAM 7
SARAM 8
SARAM 9
SARAM 10
SARAM 11
SARAM 12
SARAM 13
SARAM 14
SARAM 15
SARAM 16
SARAM 17
SARAM 18
SARAM 19
SARAM 20
SARAM 21
SARAM 22
SARAM 23
SARAM 24
SARAM 25
SARAM 26
SARAM 27
SARAM 28
SARAM 29
SARAM 30
SARAM 31(1)
(1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot
process is complete, this memory space can be used.
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6.2.1.3 On-Chip Read-Only Memory (ROM)
The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K bytes of ROM. Each on-chip ROM block can
support one read per cycle. The ROM address space can be mapped by software to the EMIF external
memory or to the internal ROM.
The standard device includes a Bootloader program resident in the ROM.
When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range
FE0000h – FFFFFFh is used for the on-chip ROM. When the MPNMC bit field of the ST3 status register is
set through software, the on-chip ROM is disabled and not present in the memory map, and byte address
range FE0000h – FFFFFFh is directed to the EMIF's external memory space on EM_CS5. A hardware
reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the
software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the CPU
program and data buses.
6.2.1.4 I/O Memory
The device includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and
system registers used for idle control, status monitoring and system configuration. I/O space is separate
from program and memory space and is accessed with separate instruction opcodes or via the DMA's.
Table 6-3 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O
space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor
DMA. For the expanded tables of each peripheral, see Section 6.2.4, Register Map.
Some of the DMA controllers have access to the I/O-Space memory-mapped registers of the following
peripherals registers: I2C, UART, I2S, MMC and SD, EMIF, McBSP, McSPI, USB, and SAR ADC.
Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is
not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the
Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).
Table 6-3. Peripheral I/O-Space Control Registers
WORD ADDRESS
0x0000 – 0x0004
0x0005 – 0x0BFF
0x0C00 – 0x0C7F
0x0C80 – 0x0CFF
0x0D00 – 0x0D7F
0x0D80 – 0x0DFF
0x0E00 – 0x0E7F
0x0E80 – 0x0EFF
0x0F00 – 0x0F7F
0x0F80 – 0x0FFF
0x1000 – 0x10DD
0x10DE – 0x17FF
0x1800 – 0x181F
0x1820 – 0x183F
0x1840 – 0x185F
0x1860 – 0x187F
0x1880 – 0x189F
0x18A0 – 0x18FF
0x1900 – 0x197F
PERIPHERAL
Idle Control
Reserved
DMA0
Reserved
DMA1
Reserved
DMA2
Reserved
DMA3
Reserved
EMIF
Reserved
Timer0
Reserved
Timer1
Reserved
Timer2
Reserved
RTC
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Table 6-3. Peripheral I/O-Space Control Registers (continued)
WORD ADDRESS
PERIPHERAL
Reserved
I2C
0x1980 – 0x19FF
0x1A00 – 0x1A6C
0x1A6D – 0x1AFF
0x1B00 – 0x1B1F
0x1B20 – 0x1BFF
0x1C00 – 0x1CFF
0x1D00 – 0x1FFF through 0x2600 – 0x27FF
0x2800 – 0x2840
Reserved
UART
Reserved
System Control
Reserved
I2S0
0x2841 – 0x29FF
0x2A00 – 0x2A40
0x2A41 – 0x2AFF
0x2B00 – 0x2B40
0x2B41 – 0x2DFF
0x2E00 – 0x2E81
0x2E82 – 0x2FFF
0x3000 – 0x300F
0x3010 – 0x33FF
0x3400 – 0x3749
Reserved
I2S2
Reserved
I2S3
Reserved
UHPI
Reserved
SPI
Reserved
McSPI
0x3750 –0x39FF
Reserved
MMC0 and SD0
Reserved
MMC1 and SD1
Reserved
McBSP
0x3A00 – 0x3A7F
0x3A80 – 0x3AFF
0x3B00 – 0x3B7F
0x3B80 – 0x3FFF
0x4000 – 0x407F
0x4080 – 0x5FFF
0x6000 – 0x60FF
0x6100 – 0x6FFF
0x7000 – 0x70FF
0x7100 – 0x7FFF
0x8000 – 0xFFFF
Reserved
McBSP DMA
Reserved
SAR and Analog Control Registers
Reserved
USB
6.2.2 External Memory
The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The
external memory space is divided into five chip select spaces: one dedicated to SDRAM and mobile
SDRAM (EMIF CS0 or CS[1:0] space), and the remainder (EMIF CS2 through CS5 space) dedicated to
asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called
EM_CSx) that is activated during an access to the chip select space.
The external memory interface (EMIF) provides the means for the DSP to access external memories and
other devices including: mobile single data rate (SDR) synchronous dynamic RAM (SDRAM and
mSDRAM), NOR Flash, NAND Flash, and asynchronous static RAM (SRAM). Before accessing external
memory, you must configure the EMIF through its memory-mapped registers.
The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 5
dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pins of the
EMIF can be operated at an independent voltage from the other I/O pins on the device.
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6.2.3 Memory Map
The device provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and
external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two
accesses to a given block during the same cycle. There are 8 blocks of 8K bytes of dual-access RAM.
The on-chip, single-access RAM allows one access to a given block per cycle. In addition, there are 32
blocks of 8K bytes of single-access RAM.
The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each external
space has a chip select decode signal (called EM_CS0, EM_CS[2:5]) that indicates an access to the
selected space. The external memory interface (EMIF) supports access to asynchronous memories such
as SRAM, NAND, or NOR and Flash, and mobile single data rate (mSDR) and single data rate (SDR)
SDRAM.
The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the
four DMA controllers, the UHPI, and the CDMA of USB (see Figure 6-1). However, only the UHPI and
USB CDMA can access the SARAM.
CPU BYTE
DMA/USB
ADDRESS(A) BYTE ADDRESS(A)
MEMORY BLOCKS
MMR (Reserved)(B)
BLOCK SIZE
000000h
0000C0h
0001 0000h
0001 00C0h
DARAM(D)
SARAM
64K Minus 192 Bytes
010000h
050000h
0009 0000h
0100 0000h
256K Bytes
External-CS0 Space(C)(E)
8M Minus 320K Bytes SDRAM/mSDRAM
800000h
C00000h
E00000h
F00000h
0200 0000h
0300 0000h
0400 0000h
0500 0000h
External-CS2 Space(C)
External-CS3 Space(C)
4M Bytes Asynchronous
2M Bytes Asynchronous
External-CS4 Space(C)
External-CS5 Space(C)
1M Bytes Asynchronous
1M Minus 128K Bytes Asynchronous
FE0000h
FFFFFFh
050E 0000h
050F FFFFh
External-CS5 Space(C)
(if MPNMC=1)
128K Bytes Asynchronous (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
ROM
(if MPNMC=0)
A. Address shown represents the first byte address in each block.
B. The first 192 bytes are reserved for memory-mapped registers (MMRs).
C. Out of the four DMA controllers, only DMA controller 3 has access to the external memory space.
D. The USB controller and UHPI do not have access to DARAM.
E. The CS0 space can be accessed by CS0 only or by CS0 and CS1.
Figure 6-1. Memory Map
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6.2.4 Register Map
6.2.4.1 DMA Peripheral Register Description
The following tables show the registers associated with the four direct memory access (DMA) controllers.
Table 6-4. System Registers Related to the DMA Controllers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1C30h
1C31h
1C1Ah
1C1Bh
1C1Ch
1C1Dh
1C36h
1C37h
1C38h
1C39h
DMAIFR
DMA Interrupt Flag Register
DMAIER
DMA Interrupt Enable Register
DMA0CESRL
DMA0CESRU
DMA1CESRL
DMA1CESRU
DMA2CESRL
DMA2CESRU
DMA3CESRL
DMA3CESRU
DMA0 Channel Event Source Register Lower
DMA0 Channel Event Source Register Upper
DMA1 Channel Event Source Register Lower
DMA1 Channel Event Source Register Upper
DMA2 Channel Event Source Register Lower
DMA2 Channel Event Source Register Upper
DMA3 Channel Event Source Register Lower
DMA3 Channel Event Source Register Upper
Table 6-5. DMA Controller 0 (DMA0) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
0C00h
0C01h
0C02h
0C03h
0C04h
0C05h
0C20h
0C21h
0C22h
0C23h
0C24h
0C25h
0C40h
0C41h
0C42h
0C43h
0C44h
0C45h
0C60h
0C61h
0C62h
0C63h
0C64h
0C65h
DMACH0SSAL
DMACH0SSAU
DMACH0DSAL
DMACH0DSAU
DMACH0TCRL
DMACH0TCRU
DMACH1SSAL
DMACH1SSAU
DMACH1DSAL
DMACH1DSAU
DMACH1TCRL
DMACH1TCRU
DMACH2SSAL
DMACH2SSAU
DMACH2DSAL
DMACH2DSAU
DMACH2TCRL
DMACH2TCRU
DMACH3SSAL
DMACH3SSAU
DMACH3DSAL
DMACH3DSAU
DMACH3TCRL
DMACH3TCRU
Channel 0 Source Start Address Register Lower
Channel 0 Source Start Address Register Upper
Channel 0 Destination Start Address Register Lower
Channel 0 Destination Start Address Register Upper
Channel 0 Transfer Control Register Lower
Channel 0 Transfer Control Register Upper
Channel 1 Source Start Address Register Lower
Channel 1 Source Start Address Register Upper
Channel 1 Destination Start Address Register Lower
Channel 1 Destination Start Address Register Upper
Channel 1 Transfer Control Register Lower
Channel 1 Transfer Control Register Upper
Channel 2 Source Start Address Register Lower
Channel 2 Source Start Address Register Upper
Channel 2 Destination Start Address Register Lower
Channel 2 Destination Start Address Register Upper
Channel 2 Transfer Control Register Lower
Channel 2 Transfer Control Register Upper
Channel 3 Source Start Address Register Lower
Channel 3 Source Start Address Register Upper
Channel 3 Destination Start Address Register Lower
Channel 3 Destination Start Address Register Upper
Channel 3 Transfer Control Register Lower
Channel 3 Transfer Control Register Upper
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Table 6-6. DMA Controller 1 (DMA1) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
0D00h
0D01h
0D02h
0D03h
0D04h
0D05h
0D20h
0D21h
0D22h
0D23h
0D24h
0D25h
0D40h
0D41h
0D42h
0D43h
0D44h
0D45h
0D60h
0D61h
0D62h
0D63h
0D64h
0D65h
DMACH0SSAL
DMACH0SSAU
DMACH0DSAL
DMACH0DSAU
DMACH0TCRL
DMACH0TCRU
DMACH1SSAL
DMACH1SSAU
DMACH1DSAL
DMACH1DSAU
DMACH1TCRL
DMACH1TCRU
DMACH2SSAL
DMACH2SSAU
DMACH2DSAL
DMACH2DSAU
DMACH2TCRL
DMACH2TCRU
DMACH3SSAL
DMACH3SSAU
DMACH3DSAL
DMACH3DSAU
DMACH3TCRL
DMACH3TCRU
Channel 0 Source Start Address Register Lower
Channel 0 Source Start Address Register Upper
Channel 0 Destination Start Address Register Lower
Channel 0 Destination Start Address Register Upper
Channel 0 Transfer Control Register Lower
Channel 0 Transfer Control Register Upper
Channel 1 Source Start Address Register Lower
Channel 1 Source Start Address Register Upper
Channel 1 Destination Start Address Register Lower
Channel 1 Destination Start Address Register Upper
Channel 1 Transfer Control Register Lower
Channel 1 Transfer Control Register Upper
Channel 2 Source Start Address Register Lower
Channel 2 Source Start Address Register Upper
Channel 2 Destination Start Address Register Lower
Channel 2 Destination Start Address Register Upper
Channel 2 Transfer Control Register Lower
Channel 2 Transfer Control Register Upper
Channel 3 Source Start Address Register Lower
Channel 3 Source Start Address Register Upper
Channel 3 Destination Start Address Register Lower
Channel 3 Destination Start Address Register Upper
Channel 3 Transfer Control Register Lower
Channel 3 Transfer Control Register Upper
Table 6-7. DMA Controller 2 (DMA2) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
0E00h
0E01h
0E02h
0E03h
0E04h
0E05h
0E20h
0E21h
0E22h
0E23h
0E24h
0E25h
0E40h
0E41h
0E42h
0E43h
0E44h
0E45h
DMACH0SSAL
DMACH0SSAU
DMACH0DSAL
DMACH0DSAU
DMACH0TCRL
DMACH0TCRU
DMACH1SSAL
DMACH1SSAU
DMACH1DSAL
DMACH1DSAU
DMACH1TCRL
DMACH1TCRU
DMACH2SSAL
DMACH2SSAU
DMACH2DSAL
DMACH2DSAU
DMACH2TCRL
DMACH2TCRU
Channel 0 Source Start Address Register Lower
Channel 0 Source Start Address Register Upper
Channel 0 Destination Start Address Register Lower
Channel 0 Destination Start Address Register Upper
Channel 0 Transfer Control Register Lower
Channel 0 Transfer Control Register Upper
Channel 1 Source Start Address Register Lower
Channel 1 Source Start Address Register Upper
Channel 1 Destination Start Address Register Lower
Channel 1 Destination Start Address Register Upper
Channel 1 Transfer Control Register Lower
Channel 1 Transfer Control Register Upper
Channel 2 Source Start Address Register Lower
Channel 2 Source Start Address Register Upper
Channel 2 Destination Start Address Register Lower
Channel 2 Destination Start Address Register Upper
Channel 2 Transfer Control Register Lower
Channel 2 Transfer Control Register Upper
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Table 6-7. DMA Controller 2 (DMA2) Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
0E60h
0E61h
0E62h
0E63h
0E64h
0E65h
DMACH3SSAL
DMACH3SSAU
DMACH3DSAL
DMACH3DSAU
DMACH3TCRL
DMACH3TCRU
Channel 3 Source Start Address Register Lower
Channel 3 Source Start Address Register Upper
Channel 3 Destination Start Address Register Lower
Channel 3 Destination Start Address Register Upper
Channel 3 Transfer Control Register Lower
Channel 3 Transfer Control Register Upper
Table 6-8. DMA Controller 3 (DMA3) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
0F00h
0F01h
0F02h
0F03h
0F04h
0F05h
0F20h
0F21h
0F22h
0F23h
0F24h
0F25h
0F40h
0F41h
0F42h
0F43h
0F44h
0F45h
0F60h
0F61h
0F62h
0F63h
0F64h
0F65h
DMACH0SSAL
DMACH0SSAU
DMACH0DSAL
DMACH0DSAU
DMACH0TCRL
DMACH0TCRU
DMACH1SSAL
DMACH1SSAU
DMACH1DSAL
DMACH1DSAU
DMACH1TCRL
DMACH1TCRU
DMACH2SSAL
DMACH2SSAU
DMACH2DSAL
DMACH2DSAU
DMACH2TCRL
DMACH2TCRU
DMACH3SSAL
DMACH3SSAU
DMACH3DSAL
DMACH3DSAU
DMACH3TCRL
DMACH3TCRU
Channel 0 Source Start Address Register Lower
Channel 0 Source Start Address Register Upper
Channel 0 Destination Start Address Register Lower
Channel 0 Destination Start Address Register Upper
Channel 0 Transfer Control Register Lower
Channel 0 Transfer Control Register Upper
Channel 1 Source Start Address Register Lower
Channel 1 Source Start Address Register Upper
Channel 1 Destination Start Address Register Lower
Channel 1 Destination Start Address Register Upper
Channel 1 Transfer Control Register Lower
Channel 1 Transfer Control Register Upper
Channel 2 Source Start Address Register Lower
Channel 2 Source Start Address Register Upper
Channel 2 Destination Start Address Register Lower
Channel 2 Destination Start Address Register Upper
Channel 2 Transfer Control Register Lower
Channel 2 Transfer Control Register Upper
Channel 3 Source Start Address Register Lower
Channel 3 Source Start Address Register Upper
Channel 3 Destination Start Address Register Lower
Channel 3 Destination Start Address Register Upper
Channel 3 Transfer Control Register Lower
Channel 3 Transfer Control Register Upper
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6.2.4.2 EMIF Peripheral Register Description
Table 6-9 shows the EMIF registers.
Table 6-9. External Memory Interface (EMIF) Peripheral Registers(1)
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1000h
1001h
1004h
1005h
1008h
1009h
100Ch
1010h
1011h
1014h
1015h
1018h
1019h
101Ch
101Dh
1020h
1021h
103Ch
1040h
1044h
1048h
104Ch
1060h
1064h
1065h
1068h
1069h
1070h
1071h
1074h
1075h
1078h
1079h
107Ch
107Dh
10BCh
10C0h
10C1h
10C4h
10C5h
10C8h
10C9h
REV
STATUS
Revision Register
Status Register
AWCCR1
Asynchronous Wait Cycle Configuration Register 1
Asynchronous Wait Cycle Configuration Register 2
SDRAM and mSDRAM Configuration Register 1
SDRAM and mSDRAM Configuration Register 2
SDRAM and mSDRAM Refresh Control Register
Asynchronous CS2 Configuration Register 1
Asynchronous CS2 Configuration Register 2
Asynchronous CS3 Configuration Register 1
Asynchronous CS3 Configuration Register 2
Asynchronous CS4 Configuration Register 1
Asynchronous CS4 Configuration Register 2
Asynchronous CS5 Configuration Register 1
Asynchronous CS5 Configuration Register 2
SDRAM and mSDRAM Timing Register 1
SDRAM and mSDRAM Timing Register 2
SDRAM and mSDRAM Self Refresh Exit Timing Register
EMIF Interrupt Raw Register
AWCCR2
SDCR1
SDCR2
SDRCR
ACS2CR1
ACS2CR2
ACS3CR1
ACS3CR2
ACS4CR1
ACS4CR2
ACS5CR1
ACS5CR2
SDTIMR1
SDTIMR2
SDSRETR
EIRR
EIMR
EMIF Interrupt Mask Register
EIMSR
EMIF Interrupt Mask Set Register
EIMCR
EMIF Interrupt Mask Clear Register
NANDFCR
NANDFSR1
NANDFSR2
PAGEMODCTRL1
PAGEMODCTRL2
NCS2ECC1
NCS2ECC2
NCS3ECC1
NCS3ECC2
NCS4ECC1
NCS4ECC2
NCS5ECC1
NCS5ECC2
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
NAND4BITECC4
NAND4BITECC5
NAND4BITECC6
NAND Flash Control Register
NAND Flash Status Register 1
NAND Flash Status Register 2
Page Mode Control Register 1
Page Mode Control Register 2
NAND Flash CS2 1-Bit ECC Register 1
NAND Flash CS2 1-Bit ECC Register 2
NAND Flash CS3 1-Bit ECC Register 1
NAND Flash CS3 1-Bit ECC Register 2
NAND Flash CS4 1-Bit ECC Register 1
NAND Flash CS4 1-Bit ECC Register 2
NAND Flash CS5 1-Bit ECC Register 1
NAND Flash CS5 1-Bit ECC Register 2
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Register 5
NAND Flash 4-Bit ECC Register 6
(1) Before reading or writing to the EMIF registers, be sure to set the BYTEMODE bits to 00b in the EMIF system control register to enable
word accesses to the EMIF registers.
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Table 6-9. External Memory Interface (EMIF) Peripheral Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
10CCh
10CDh
10D0h
10D1h
10D4h
10D5h
10D8h
10D9h
10DCh
10DDh
NAND4BITECC7
NAND4BITECC8
NANDERRADD1
NANDERRADD2
NANDERRADD3
NANDERRADD4
NANDERRVAL1
NANDERRVAL2
NANDERRVAL3
NANDERRVAL4
NAND Flash 4-Bit ECC Register 7
NAND Flash 4-Bit ECC Register 8
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Address Register 3
NAND Flash 4-Bit ECC Error Address Register 4
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
NAND Flash 4-Bit ECC Error Value Register 3
NAND Flash 4-Bit ECC Error Value Register 4
6.2.4.3 GPIO Peripheral Register Description
The external parallel port interface includes a 16-bit general purpose I/O that can be individually
programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained
through a set of I/O memory-mapped registers shown in Table 6-10.
Table 6-10. GPIO Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1C06h
1C07h
1C08h
1C09h
1C0Ah
1C0Bh
1C0Ch
1C0Dh
1C0Eh
1C0Fh
1C10h
1C11h
IODIR1
IODIR2
GPIO Direction Register 1
GPIO Direction Register 2
GPIO Data In Register 1
GPIO Data In Register 2
GPIO Data Out Register 1
GPIO Data Out Register 2
IOINDATA1
IOINDATA2
IODATAOUT1
IODATAOUT2
IOINTEDG1
IOINTEDG2
IOINTEN1
GPIO Interrupt Edge Trigger Enable Register 1
GPIO Interrupt Edge Trigger Enable Register 2
GPIO Interrupt Enable Register 1
IOINTEN2
GPIO Interrupt Enable Register 2
IOINTFLG1
IOINTFLG2
GPIO Interrupt Flag Register 1
GPIO Interrupt Flag Register 2
162
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6.2.4.4 I2C Peripheral Register Description
Table 6-11 shows the Inter-Integrated Circuit (I2C) registers.
Table 6-11. Inter-Integrated Circuit (I2C) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1A00h
1A04h
1A08h
1A0Ch
1A10h
1A14h
1A18h
1A1Ch
1A20h
1A24h
1A28h
1A2Ch
1A30h
1A34h
1A38h
ICOAR
ICIMR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICPID1
ICPID2
I2C Peripheral Identification Register 1
I2C Peripheral Identification Register 2
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6.2.4.5 I2S Peripheral Register Description
Table 6-12 through Table 6-14 show the I2S0, I2S2, and I2S3 registers.
Table 6-12. I2S0 Registers
CPU WORD
ACRONYM
REGISTER NAME
ADDRESS
2800h
2804h
2808h
2809h
280Ch
280Dh
2810h
2814h
2828h
2829h
282Ch
282Dh
I2S0SCTRL
I2S0SRATE
I2S0TXLT1
I2S0TXLT2
I2S0TXRT1
I2S0TXRT2
I2S0INTFL
I2S0 Serializer Control Register
I2S0 Sample Rate Generator Register
I2S0 Transmit Left Data Register 1
I2S0 Transmit Left Data Register 2
I2S0 Transmit Right Data Register 1
I2S0 Transmit Right Data Register 2
I2S0 Interrupt Flag Register
I2S0INTMASK
I2S0RXLT1
I2S0RXLT2
I2S0RXRT1
I2S0RXRT2
I2S0 Interrupt Mask Register
I2S0 Receive Left Data Register 1
I2S0 Receive Left Data Register 2
I2S0 Receive Right Data Register 1
I2S0 Receive Right Data Register 2
Table 6-13. I2S2 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
2A00h
2A04h
2A08h
2A09h
2A0Ch
2A0Dh
2A10h
2A14h
2A28h
2A29h
2A2Ch
2A2Dh
I2S2SCTRL
I2S2SRATE
I2S2TXLT1
I2S2TXLT2
I2S2TXRT1
I2S2TXRT2
I2S2INTFL
I2S2 Serializer Control Register
I2S2 Sample Rate Generator Register
I2S2 Transmit Left Data Register 1
I2S2 Transmit Left Data Register 2
I2S2 Transmit Right Data Register 1
I2S2 Transmit Right Data Register 2
I2S2 Interrupt Flag Register
I2S2INTMASK
I2S2RXLT1
I2S2RXLT2
I2S2RXRT1
I2S2RXRT2
I2S2 Interrupt Mask Register
I2S2 Receive Left Data Register 1
I2S2 Receive Left Data Register 2
I2S2 Receive Right Data Register 1
I2S2 Receive Right Data Register 2
Table 6-14. I2S3 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
2B00h
2B04h
2B08h
2B09h
2B0Ch
2B0Dh
2B10h
2B14h
2B28h
2B29h
2B2Ch
I2S3SCTRL
I2S3SRATE
I2S3TXLT1
I2S3TXLT2
I2S3TXRT1
I2S3TXRT2
I2S3INTFL
I2S3 Serializer Control Register
I2S3 Sample Rate Generator Register
I2S3 Transmit Left Data Register 1
I2S3 Transmit Left Data Register 2
I2S3 Transmit Right Data Register 1
I2S3 Transmit Right Data Register 2
I2S3 Interrupt Flag Register
I2S3INTMASK
I2S3RXLT1
I2S3RXLT2
I2S3RXRT1
I2S3 Interrupt Mask Register
I2S3 Receive Left Data Register 1
I2S3 Receive Left Data Register 2
I2S3 Receive Right Data Register 1
164
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Table 6-14. I2S3 Registers (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
2B2Dh
I2S3RXRT2
I2S3 Receive Right Data Register 2
6.2.4.6 McBSP Peripheral Register Descriptions
Table 6-15 shows the McBSP peripheral registers.
Table 6-15. McBSP Module Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
4000h
4001h
4004h
4005h
4008h
4009h
400Ch
400Dh
4010h
4011h
4014h
4015h
4018h
4019h
401Ch
401Dh
4020h
4021h
4024h
4025h
4028h
4029h
402Ch
402Dh
4030h
4031h
4034h
4035h
4038h
4039h
403Ch
403Dh
DRRL
DRRU
DXRL
Data Receive Register Lower
Data Receive Register Upper
Data Transmit Register Lower
Data Transmit Register Upper
Serial Port Control Register Lower
Serial Port Control Register Upper
Receive Control Register Lower
Receive Control Register Upper
Transmit Control Register Lower
Transmit Control Register Upper
DXRU
SPCRL
SPCRU
RCRL
RCRU
XCRL
XCRU
SRGRL
Sample Rate Generator Register Lower
Sample Rate Generator Register Upper
Multichannel Control Register Lower
Multichannel Control Register Upper
SRGRU
MCRL
MCRU
RCERA
RCERB
XCERA
XCERB
PCRL
Enhanced Receive Channel Enable Register Partition A
Enhanced Receive Channel Enable Register Partition B
Enhanced Transmit Channel Enable Register Partition A
Enhanced Transmit Channel Enable Register Partition B
Pin Control Register Lower
PCRU
Pin Control Register Upper
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
Enhanced Receive Channel Enable Register Partition C
Enhanced Receive Channel Enable Register Partition D
Enhanced Transmit Channel Enable Register Partition C
Enhanced Transmit Channel Enable Register Partition D
Enhanced Receive Channel Enable Register Partition E
Enhanced Receive Channel Enable Register Partition F
Enhanced Transmit Channel Enable Register Partition E
Enhanced Transmit Channel Enable Register Partition F
Enhanced Receive Channel Enable Register Partition G
Enhanced Receive Channel Enable Register Partition H
Enhanced Transmit Channel Enable Register Partition G
Enhanced Transmit Channel Enable Register Partition H
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6.2.4.7 McSPI Peripheral Register Descriptions
Table 6-16 shows the McSPI peripheral registers.
Table 6-16. McSPI Module Registers
CPU WORD
ADDRESS
ACRONYM
REVISIONL
REGISTER NAME
3500h
3510h
3514h
3518h
3519h
351Ch
351Dh
3520h
3528h
352Ch
352Dh
3530h
3534h
3538h
3539h
353Ch
353Dh
3540h
3541h
3544h
3548h
354Ch
354Dh
3550h
3551h
3554h
3555h
3558h
355Ch
3560h
3561h
3564h
3565h
357Ch
357Dh
3580h
3581h
35A0h
35A1h
Revision Register Lower
SYSCONFIGL
SYSSTATUSL
IRQSTATUSL
IRQSTATUSU
IRQENABLEL
IRQENABLEU
WAKEUPENABLEL
MODULCTRLL
CH0CONFL
CH0CONFU
CH0STATL
CH0CTRLL
CH0TXL
System Configuration Register Lower
System Status Register Lower
Interrupt Status Register Lower
Interrupt Status Register Upper
Interrupt Enable Register Lower
Interrupt Enable Register Upper
Wakeup Enable Register Lower
Module Control Register Lower
Channel 0 Configuration Register Lower
Channel 0 Configuration Register Upper
Channel 0 Status Register Lower
Channel 0 Control Register Lower
Channel 0 Transmitter Register Lower
Channel 0 Transmitter Register Upper
Channel 0 Receiver Register Lower
Channel 0 Receiver Register Upper
Channel 1 Configuration Register Lower
Channel 1 Configuration Register Upper
Channel 1 Status Register Lower
CH0TXU
CH0RXL
CH0RXU
CH1CONFL
CH1CONFU
CH1STATL
CH1CTRLL
CH1TXL
Channel 1 Control Register Lower
Channel 1 Transmitter Register Lower
Channel 1 Transmitter Register Upper
Channel 1 Receiver Register Lower
Channel 1 Receiver Register Upper
Channel 2 Configuration Register Lower
Channel 2 Configuration Register Upper
Channel 2 Status Register Lower
CH1TXU
CH1RXL
CH1RXU
CH2CONFL
CH2CONFU
CH2STATL
CH2CTRLL
CH2TXL
Channel 2 Control Register Lower
Channel 2 Transmitter Register Lower
Channel 2 Transmitter Register Upper
Channel 2 Receiver Register Lower
Channel 2 Receiver Register Upper
Transfer Levels Register Lower
CH2TXU
CH2RXL
CH2RXU
XFERLEVELL
XFERLEVELU
DAFTXL
Transfer Levels Register Upper
DMA Address Aligned FIFO Transmitter Register Lower
DMA Address Aligned FIFO Transmitter Register Upper
DMA Address Aligned FIFO Receiver Register Lower
DMA Address Aligned FIFO Receiver Register Upper
DAFTXU
DAFRXL
DAFRXU
166
Detailed Description
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6.2.4.8 MMC and SD Peripheral Register Description
Table 6-17 and Table 6-18 show the MMC and SD registers. The MMC0 and SD0 registers start at
address 0x3A00 and the MMC1 and SD1 registers start at address 0x3B00.
Table 6-17. MMC0 and SD0 Registers
CPU WORD
ACRONYM
REGISTER NAME
ADDRESS
3A00h
3A04h
3A08h
3A0Ch
3A10h
3A14h
3A18h
3A1Ch
3A20h
3A24h
3A28h
3A29h
3A2Ch
3A2Dh
3A30h
3A31h
3A34h
3A35h
3A38h
3A39h
3A3Ch
3A3Dh
3A40h
3A41h
3A44h
3A45h
3A48h
3A50h
3A64h
3A68h
3A6Ch
3A70h
3A74h
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register Lower
MMC Data Receive Register Upper
MMC Data Transmit Register Lower
MMC Data Transmit Register Upper
MMC Command Register Lower
MMC Command Register Upper
MMC Argument Register Lower
MMC Argument Register Upper
MMC Response Register 0
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRRL
MMCDRRU
MMCDXRL
MMCDXRU
MMCCMDL
MMCCMDU
MMCARGL
MMCARGU
MMCRSP0
MMCRSP1
MMCRSP2
MMCRSP3
MMCRSP4
MMCRSP5
MMCRSP6
MMCRSP7
MMCDRSP
MMCCIDX
SDIOCTL
MMC Response Register 1
MMC Response Register 2
MMC Response Register 3
MMC Response Register 4
MMC Response Register 5
MMC Response Register 6
MMC Response Register 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
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Table 6-18. MMC1 and SD1 Registers
CPU WORD
ACRONYM
ADDRESS
REGISTER NAME
3B00h
3B04h
3B08h
3B0Ch
3B10h
3B14h
3B18h
3B1Ch
3B20h
3B24h
3B28h
3B29h
3B2Ch
3B2Dh
3B30h
3B31h
3B34h
3B35h
3B38h
3B39h
3B3Ch
3B3Dh
3B40h
3B41h
3B44h
3B45h
3B48h
3B50h
3B64h
3B68h
3B6Ch
3B70h
3B74h
MMCCTL
MMCCLK
MMC Control Register
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register Lower
MMC Data Receive Register Upper
MMC Data Transmit Register Lower
MMC Data Transmit Register Upper
MMC Command Register Lower
MMC Command Register Upper
MMC Argument Register Lower
MMC Argument Register Upper
MMC Response Register 0
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRRL
MMCDRRU
MMCDXRL
MMCDXRU
MMCCMDL
MMCCMDU
MMCARGL
MMCARGU
MMCRSP0
MMCRSP1
MMCRSP2
MMCRSP3
MMCRSP4
MMCRSP5
MMCRSP6
MMCRSP7
MMCDRSP
MMCCIDX
SDIOCTL
MMC Response Register 1
MMC Response Register 2
MMC Response Register 3
MMC Response Register 4
MMC Response Register 5
MMC Response Register 6
MMC Response Register 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
168
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6.2.4.9 RTC Peripheral Register Description
Table 6-19 shows the RTC registers.
Table 6-19. Real-Time Clock (RTC) Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1900h
1901h
1904h
1905h
1908h
1909h
190Ch
190Dh
1910h
1911h
1914h
1915h
1918h
1919h
191Ch
191Dh
1920h
1921h
1924h
1928h
192Ch
1930h
1960h
1961h
1964h
1965h
196Ch
196Dh
RTCINTEN
RTCUPDATE
RTCMIL
RTC Interrupt Enable Register
RTC Update Register
Milliseconds Register
RTCMILA
Milliseconds Alarm Register
Seconds Register
RTCSEC
RTCSECA
RTCMIN
Seconds Alarm Register
Minutes Register
RTCMINA
RTCHOUR
RTCHOURA
RTCDAY
Minutes Alarm Register
Hours Register
Hours Alarm Register
Days Register
RTCDAYA
RTCMONTH
RTCMONTHA
RTCYEAR
RTCYEARA
RTCINTFL
RTCNOPWR
RTCINTREG
RTCDRIFT
RTCOSC
Days Alarm Register
Months Register
Months Alarm Register
Years Register
Years Alarm Register
RTC Interrupt Flag Register
RTC Lost Power Status Register
RTC Interrupt Register
RTC Compensation Register
RTC Oscillator Register
RTC Power Management Register
RTC LSW Scratch Register 1
RTC MSW Scratch Register 2
RTC LSW Scratch Register 3
RTC MSW Scratch Register 4
RTC LSW Gate-Keeper Register
RTC MSW Gate-Keeper Register
RTCPMGT
RTCSCR1
RTCSCR2
RTCSCR3
RTCSCR4
RGKR_LSW
RGKR_MSW
6.2.4.10 SAR ADC Peripheral Register Description
Table 6-20 shows the SAR ADC peripheral registers.
Table 6-20. SAR Analog Control Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
7012h
7014h
7016h
7018h
701Ah
SARCTRL
SARDATA
SAR A/D Control Register
SAR A/D Data Register
SARCLKCTRL
SARPINCTRL
SARGPOCTRL
SAR A/D Clock Control Register
SAR A/D Reference and Pin Control Register
SAR A/D GPO Control Register
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6.2.4.11 SPI Peripheral Register Descriptions
Table 6-21 shows the SPI registers.
Table 6-21. SPI Module Registers
CPU
WORD
ACRONYM
REGISTER NAME
ADDRESS
3000h
3001h
3002h
3003h
3004h
3005h
3006h
3007h
3008h
3009h
SPICDR
SPICCR
Clock Divider Register
Clock Control Register
SPIDCR1
SPIDCR2
SPICMD1
SPICMD2
SPISTAT1
SPISTAT2
SPIDAT1
SPIDAT2
Device Configuration Register 1
Device Configuration Register 2
Command Register 1
Command Register 2
Status Register 1
Status Register 2
Data Register 1
Data Register 2
170
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6.2.4.12 System Registers
The system registers are used to configure the device and monitor its status. Brief descriptions of the
various system registers are shown in Table 6-22.
Table 6-22. Idle Control, Status, and System Registers
CPU WORD
ADDRESS
ACRONYM
COMMENTS
Register Description
Idle Control Register
0001h
0002h
1C00h
ICR
ISTR
EBSR
Idle Status Register
see Section 5.7.3.5.1 of this
document.
External Bus Selection Register
1C02h
1C03h
1C04h
1C05h
1C14h
1C15h
1C16h
1C17h
1C18h
1C19h
1C1Ah
1C1Bh
1C1Ch
1C1Dh
1C1Eh
1C1Fh
1C20h
1C21h
1C22h
1C23h
1C24h
1C26h
1C27h
1C28h
1C2Ah
1C2Bh
1C2Ch
1C2Dh
1C2Eh
1C2Fh
1C30h
1C31h
1C32h
1C33h
1C34h
1C36h
1C37h
1C38h
1C39h
PCGCR1
PCGCR2
Peripheral Clock Gating Control Register 1
Peripheral Clock Gating Control Register 2
Peripheral Software Reset Counter Register
Peripheral Reset Control Register
Timer Interrupt Aggregation Flag Register
McSPI Interrupt Aggregation Flag Register
Output Slew Rate Control Register
Pullup and Pulldown Inhibit Register 1
Pullup and Pulldown Inhibit Register 2
Pullup and Pulldown Inhibit Register 3
DMA0 Channel Event Source Register 1
DMA0 Channel Event Source Register 2
DMA1 Channel Event Source Register 1
DMA1 Channel Event Source Register 2
Clock Configuration Register 1
PSRCR
PRCR
TIAFR
MSIAFR
OSRCR
PUDINHIBR1
PUDINHIBR2
PUDINHIBR3
DMA0CESR1
DMA0CESR2
DMA1CESR1
DMA1CESR2
CCR1
CCR2
Clock Configuration Register 2
PMR
PLL Multiplier Register
PICR
PLL Input Control Register
PCR
PLL Control Register
PODCR
PLL Output Divider Control Register
CLKOUT Configuration Register
CLKOUTCR
ECDR
EMIF Clock Divider Register
RSCR
RTC System Control Register
RAMSLPMDCNTLR1
RAMSLPMDCNTLR2
RAMSLPMDCNTLR3
RAMSLPMDCNTLR4
RAMSLPMDCNTLR5
PLLSSCR1
PLLSSCR2
DMAIFR
RAM Sleep Mode Control Register 1
RAM Sleep Mode Control Register 2
RAM Sleep Mode Control Register 3
RAM Sleep Mode Control Register 4
RAM Sleep Mode Control Register 5
PLL Spread Spectrum Control Register 1
PLL Spread Spectrum Control Register 2
DMA Interrupt Flag Aggregation Register
DMA Interrupt Enable Register
DMAIER
USBSCR
USB System Control Register
ESCR
EMIF System Control Register
BMR
BootMode Register
DMA2CESR1
DMA2CESR2
DMA3CESR1
DMA3CESR2
DMA2 Channel Event Source Register 1
DMA2 Channel Event Source Register 2
DMA3 Channel Event Source Register 1
DMA3 Channel Event Source Register 2
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Table 6-22. Idle Control, Status, and System Registers (continued)
CPU WORD
ADDRESS
ACRONYM
COMMENTS
Register Description
1C3Ah
CLKSTOP1
CLKSTOP2
Peripheral Clock Stop Request and Acknowledge Register
1
1C3Bh
Peripheral Clock Stop Request and Acknowledge Register
2
1C3Ch
1C3Dh
1C3Eh
1C40h
1C41h
1C42h
1C43h
1C44h
1C45h
1C46h
1C47h
1C4Ch
1C4Dh
1C4Eh
1C4Fh
1C50h
1C58h
1C59h
7004h
MSPIFCDR
MSIAER
McSPI Reference Clock Divider Register
McSPI Aggregation Interrupt Mask Register
Timer Interrupt Selection Register
Die ID Register 0
TISR
DIEIDR0
DIEIDR1
Die ID Register 1
DIEIDR2
Die ID Register 2
DIEIDR3
Die ID Register 3
DIEIDR4
Die ID Register 4
DIEIDR5
Die ID Register 5
DIEIDR6
Die ID Register 6
DIEIDR7
Die ID Register 7
PUDINHIBR4
PUDINHIBR5
UHPICR
Pullup and Pulldown Inhibit Register 4
Pullup and Pulldown Inhibit Register 5
UHPI Configuration Register
Pullup and Pulldown Inhibit Register 6
Pullup and Pulldown Inhibit Register 7
JTAG ID Code LSW Register
JTAG ID Code MSW Register
PUDINHIBR6
PUDINHIBR7
JTAGIDLSW
JTAGIDMSW
LDOCNTL
see Section 5.7.2.1.1.2.1 of
this document.
LDO Control Register
172
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6.2.4.13 Timers Peripheral Register Description
Table 6-23 through Table 6-26 show the Timer and Watchdog registers.
Table 6-23. Watchdog Timer Registers (Timer2 only)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1880h
1882h
1884h
1886h
1888h
188Ah
188Ch
188Eh
WDKCKLK
WDKICK
WDSVLR
WDSVR
WDENLOK
WDEN
Watchdog Kick Lock Register
Watchdog Kick Register
Watchdog Start Value Lock Register
Watchdog Start Value Register
Watchdog Enable Lock Register
Watchdog Enable Register
WDPSLR
WDPS
Watchdog Prescaler Lock Register
Watchdog Prescaler Register
Table 6-24. General-Purpose Timer 0 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1810h
1812h
1813h
1814h
1815h
1816h
T0CR
Timer 0 Control Register
TIM0PRD1
TIM0PRD2
TIM0CNT1
TIM0CNT2
T0INSR
Timer 0 Period Register 1
Timer 0 Period Register 2
Timer 0 Counter Register 1
Timer 0 Counter Register 2
Timer 0 Input Selection Register
Table 6-25. General-Purpose Timer 1 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1850h
1852h
1853h
1854h
1855h
1856h
T1CR
Timer 1 Control Register
TIM1PRD1
TIM1PRD2
TIM1CNT1
TIM1CNT2
T1INSR
Timer 1 Period Register 1
Timer 1 Period Register 2
Timer 1 Counter Register 1
Timer 1 Counter Register 2
Timer 1 Input Selection Register
Table 6-26. General-Purpose Timer 2 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1890h
1892h
1893h
1894h
1895h
1896h
T2CR
Timer 2 Control Register
TIM2PRD1
TIM2PRD2
TIM2CNT1
TIM2CNT2
T2INSR
Timer 2 Period Register 1
Timer 2 Period Register 2
Timer 2 Counter Register 1
Timer 2 Counter Register 2
Timer 2 Input Selection Register
Table 6-27. Timer Interrupt Selection Register
CPU WORD
ADDRESS
ACRONYM
TISR
REGISTER DESCRIPTION
1C3Eh
Timer Interrupt Selection Register
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6.2.4.14 UART Peripheral Register Description
Table 6-28 shows the UART registers.
Table 6-28. UART Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER NAME
1B00h
1B00h
1B02h
1B04h
1B04h
1B06h
1B08h
1B0Ah
1B0Eh
1B10h
1B12h
1B18h
RBR
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
THR
IER
IIR
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
FCR
LCR
MCR
Modem Control Register
LSR
SCR
Line Status Register
Scratch Register
DLL
Divisor LSB Latch
DLH
Divisor MSB Latch
PWREMU_MGMT
Power and Emulation Management Register
174
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6.2.4.15 UHPI Peripheral Register Descriptions
Table 6-29 shows the UHPI peripheral registers.
Table 6-29. UHPI Module Registers
CPU
WORD
ACRONYM
REGISTER NAME
ADDRESS
2E00h
2E01h
2E04h
2E08h
2E09h
2E0Ch
2E0Dh
2E10h
2E11h
2E14h
2E15h
2E18h
2E19h
2E1Ch
2E1Dh
2E20h
2E21h
2E24h
2E25h
2E30h
2E34h
2E35h
2E38h
2E39h
PIDL
PIDU
PWREMU_MGMT Power Management and Emulation Register
Peripheral Identification Register Lower
Peripheral Identification Register Upper
GPINT_CTRLL
GPINT_CTRLU
GPIO_ENL
GPINT Control Register Lower
GPINT Control Register Upper
GPIO Enable Register Lower
GPIO_ENU
GPIO_DIR1L
GPIO_DIR1U
GPIO_DAT1L
GPIO_DAT1U
GPIO_DIR2L
GPIO_DIR2U
GPIO_DAT2L
GPIO_DAT2U
GPIO_DIR3L
GPIO_DIR3U
GPIO_DAT3L
GPIO_DAT3U
UHPICL
GPIO Enable Register Upper
GPIO Direction Register 1 Lower
GPIO Direction Register 1 Upper
GPIO Data Register 1 Lower
GPIO Data Register 1 Upper
GPIO Direction Register 2 Lower
GPIO Direction Register 2 Upper
GPIO Data Register 2 Lower
GPIO Data Register 2 Upper
GPIO Direction Register 3 Lower
GPIO Direction Register 3 Upper
GPIO Data Register 3 Lower
GPIO Data Register 3 Upper
Universal Host-Port Interface Control Register
Universal Host-Port Interface Write Address Register Lower
Universal Host-Port Interface Write Address Register Upper
Universal Host-Port Interface Read Address Register Lower
Universal Host-Port Interface Read Address Register Upper
UHPIAWL
UHPIAWU
UHPIARL
UHPIARU
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6.2.4.16 USB2.0 Peripheral Register Descriptions
Table 6-30 lists of the USB2.0 peripheral registers.
Table 6-30. Universal Serial Bus (USB) Registers(1)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Revision Identification Register 1
8000h
8001h
8004h
800Ch
8010h
8011h
8014h
801Ch
801Dh
8020h
8021h
8024h
8025h
8028h
8029h
802Ch
802Dh
8030h
8031h
8034h
8035h
8038h
8039h
803Ch
8040h
8041h
8050h
8051h
8054h
8055h
8058h
8059h
805Ch
805Dh
REVID1
REVID2
Revision Identification Register 2
Control Register
CTRLR
EMUR
Emulation Register
MODE1
Mode Register 1
MODE2
Mode Register 2
AUTOREQ
TEARDOWN1
TEARDOWN2
INTSRCR1
INTSRCR2
INTSETR1
Auto Request Register
Teardown Register 1
Teardown Register 2
USB Interrupt Source Register 1
USB Interrupt Source Register 2
USB Interrupt Source Set Register 1
USB Interrupt Source Set Register 2
USB Interrupt Source Clear Register 1
USB Interrupt Source Clear Register 2
USB Interrupt Mask Register 1
USB Interrupt Mask Register 2
USB Interrupt Mask Set Register 1
USB Interrupt Mask Set Register 2
USB Interrupt Mask Clear Register 1
USB Interrupt Mask Clear Register 2
USB Interrupt Source Masked Register 1
USB Interrupt Source Masked Register 2
USB End of Interrupt Register
USB Interrupt Vector Register 1
USB Interrupt Vector Register 2
Generic RNDIS EP1Size Register 1
Generic RNDIS EP1Size Register 2
Generic RNDIS EP2 Size Register 1
Generic RNDIS EP2 Size Register 2
Generic RNDIS EP3 Size Register 1
Generic RNDIS EP3 Size Register 2
Generic RNDIS EP4 Size Register 1
Generic RNDIS EP4 Size Register 2
INTSETR2
INTCLRR1
INTCLRR2
INTMSKR1
INTMSKR2
INTMSKSETR1
INTMSKSETR2
INTMSKCLRR1
INTMSKCLRR2
INTMASKEDR1
INTMASKEDR2
EOIR
INTVECTR1
INTVECTR2
GREP1SZR1
GREP1SZR2
GREP2SZR1
GREP2SZR2
GREP3SZR1
GREP3SZR2
GREP4SZR1
GREP4SZR2
(1) Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable
word accesses to the USB registers .
176
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Table 6-30. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Common USB Registers
8401h
8402h
8405h
8406h
8409h
840Ah
840Dh
840Eh
FADDR_POWER
INTRTX
Function Address Register, Power Management Register
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
INTRRX
INTRTXE
INTRRXE
Interrupt Enable Register for INTRRX
INTRUSB_INTRUSBE
FRAME
Interrupt Register for Common USB Interrupts, Interrupt Enable Register
Frame Number Register
Index Register for Selecting the Endpoint Status and Control Registers, Register to
Enable the USB 2.0 Test Modes
INDEX_TESTMODE
USB Indexed Registers
8411h
8412h
Maximum Packet Size for Peripheral and Host Transmit Endpoint. (Index register set
to select Endpoints 1-4)
TXMAXP_INDX
PERI_CSR0_INDX
PERI_TXCSR_INDX
RXMAXP_INDX
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to
select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select
Endpoints 1-4)
8415h
8416h
8419h
Maximum Packet Size for Peripheral and Host Receive Endpoint. (Index register set
to select Endpoints 1-4)
Control Status Register for Peripheral Receive Endpoint. (Index register set to select
Endpoints 1-4)
PERI_RXCSR_INDX
COUNT0_INDX
Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint
0)
Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select
Endpoints 1- 4)
RXCOUNT_INDX
841Ah
841Dh
841Eh
-
-
Reserved
Reserved
CONFIGDATA_INDC
(Upper byte of 841Eh)
Returns details of core configuration. (index register set to select Endpoint 0)
USB FIFO Registers
8421h
8422h
8425h
8426h
8429h
842Ah
842Dh
842Eh
8431h
8432h
FIFO0R1
FIFO0R2
FIFO1R1
FIFO1R2
FIFO2R1
FIFO2R2
FIFO3R1
FIFO3R2
FIFO4R1
FIFO4R2
Transmit and Receive FIFO Register 1 for Endpoint 0
Transmit and Receive FIFO Register 2 for Endpoint 0
Transmit and Receive FIFO Register 1 for Endpoint 1
Transmit and Receive FIFO Register 2 for Endpoint 1
Transmit and Receive FIFO Register 1 for Endpoint 2
Transmit and Receive FIFO Register 2 for Endpoint 2
Transmit and Receive FIFO Register 1 for Endpoint 3
Transmit and Receive FIFO Register 2 for Endpoint 3
Transmit and Receive FIFO Register 1 for Endpoint 4
Transmit and Receive FIFO Register 2 for Endpoint 4
Dynamic FIFO Control Registers
8461h
8462h
-
Reserved
Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to
select Endpoints 1-4)
TXFIFOSZ_RXFIFOSZ
8465h
8466h
846Dh
TXFIFOADDR
RXFIFOADDR
Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Hardware Version Register (See TMS320C5517 Digital Signal Processor Technical
Reference Manual [SPRUH16].)
HWVERS
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Table 6-30. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Control and Status Register for Endpoint 0
8501h
8502h
8505h
8506h
8509h
850Ah
850Dh
-
Reserved
PERI_CSR0
Control Status Register for Peripheral Endpoint 0
-
Reserved
-
Reserved
COUNT0
Number of Received Bytes in Endpoint 0 FIFO
Reserved
-
-
Reserved
CONFIGDATA
(Upper byte of 850Eh)
Returns details of core configuration.
850Eh
Control and Status Register for Endpoint 1
8511h
8512h
8515h
8516h
8519h
851Ah
851Dh
851Eh
TXMAXP
Maximum Packet Size for Peripheral and Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in the Receiving Endpoint's FIFO
Reserved
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
Control and Status Register for Endpoint 2
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8521h
8522h
8525h
8526h
8529h
852Ah
852Dh
852Eh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
Control and Status Register for Endpoint 3
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8531h
8532h
8535h
8536h
8539h
853Ah
853Dh
853Eh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
Control and Status Register for Endpoint 4
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
8541h
8542h
8545h
8546h
8549h
854Ah
854Dh
854Eh
TXMAXP
PERI_TXCSR
RXMAXP
PERI_RXCSR
RXCOUNT
-
-
-
Reserved
Reserved
178
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Table 6-30. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
CPPI DMA (CMDA) Registers
9000h
9001h
9004h
9008h
9800h
9801h
9808h
9809h
980Ch
980Dh
9810h
9811h
9820h
9821h
9828h
9829h
982Ch
982Dh
9830h
9831h
9840h
9841h
9848h
9849h
984Ch
984Dh
9850h
9851h
9860h
9861h
9868h
9869h
986Ch
986Dh
9870h
9871h
A000h
A001h
A800h + 4 × N
A801h + 4 × N
DMAREVID1
DMAREVID2
TDFDQ
CDMA Revision Identification Register 1
CDMA Revision Identification Register 2
CDMA Teardown Free Descriptor Queue Control Register
CDMA Emulation Control Register
DMAEMU
TXGCR1[0]
Transmit Channel 0 Global Configuration Register 1
Transmit Channel 0 Global Configuration Register 2
Receive Channel 0 Global Configuration Register 1
Receive Channel 0 Global Configuration Register 2
Receive Channel 0 Host Packet Configuration Register 1 A
Receive Channel 0 Host Packet Configuration Register 2 A
Receive Channel 0 Host Packet Configuration Register 1 B
Receive Channel 0 Host Packet Configuration Register 2 B
Transmit Channel 1 Global Configuration Register 1
Transmit Channel 1 Global Configuration Register 2
Receive Channel 1 Global Configuration Register 1
Receive Channel 1 Global Configuration Register 2
Receive Channel 1 Host Packet Configuration Register 1 A
Receive Channel 1 Host Packet Configuration Register 2 A
Receive Channel 1 Host Packet Configuration Register 1 B
Receive Channel 1 Host Packet Configuration Register 2 B
Transmit Channel 2 Global Configuration Register 1
Transmit Channel 2 Global Configuration Register 2
Receive Channel 2 Global Configuration Register 1
Receive Channel 2 Global Configuration Register 2
Receive Channel 2 Host Packet Configuration Register 1 A
Receive Channel 2 Host Packet Configuration Register 2 A
Receive Channel 2 Host Packet Configuration Register 1 B
Receive Channel 2 Host Packet Configuration Register 2 B
Transmit Channel 3 Global Configuration Register 1
Transmit Channel 3 Global Configuration Register 2
Receive Channel 3 Global Configuration Register 1
Receive Channel 3 Global Configuration Register 2
Receive Channel 3 Host Packet Configuration Register 1 A
Receive Channel 3 Host Packet Configuration Register 2 A
Receive Channel 3 Host Packet Configuration Register 1 B
Receive Channel 3 Host Packet Configuration Register 2 B
CDMA Scheduler Control Register 1
TXGCR2[0]
RXGCR1[0]
RXGCR2[0]
RXHPCR1A[0]
RXHPCR2A[0]
RXHPCR1B[0]
RXHPCR2B[0]
TXGCR1[1]
TXGCR2[1]
RXGCR1[1]
RXGCR2[1]
RXHPCR1A[1]
RXHPCR2A[1]
RXHPCR1B[1]
RXHPCR2B[1]
TXGCR1[2]
TXGCR2[2]
RXGCR1[2]
RXGCR2[2]
RXHPCR1A[2]
RXHPCR2A[2]
RXHPCR1B[2]
RXHPCR2B[2]
TXGCR1[3]
TXGCR2[3]
RXGCR1[3]
RXGCR2[3]
RXHPCR1A[3]
RXHPCR2A[3]
RXHPCR1B[3]
RXHPCR2B[3]
DMA_SCHED_CTRL1
DMA_SCHED_CTRL2
ENTRYLSW[N]
ENTRYMSW[N]
CDMA Scheduler Control Register 1
CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)
CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)
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Table 6-30. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Queue Manager (QMGR) Registers
C000h
C001h
QMGRREVID1
QMGRREVID2
DIVERSION1
DIVERSION2
FDBSC0
Queue Manager Revision Identification Register 1
Queue Manager Revision Identification Register 2
Queue Manager Queue Diversion Register 1
C008h
C009h
Queue Manager Queue Diversion Register 2
C020h
Queue Manager Free Descriptor and Buffer Starvation Count Register 0
Queue Manager Free Descriptor and Buffer Starvation Count Register 1
Queue Manager Free Descriptor and Buffer Starvation Count Register 2
Queue Manager Free Descriptor and Buffer Starvation Count Register 3
Queue Manager Free Descriptor and Buffer Starvation Count Register 4
Queue Manager Free Descriptor and Buffer Starvation Count Register 5
Queue Manager Free Descriptor and Buffer Starvation Count Register 6
Queue Manager Free Descriptor and Buffer Starvation Count Register 7
Queue Manager Linking RAM Region 0 Base Address Register 1
Queue Manager Linking RAM Region 0 Base Address Register 2
Queue Manager Linking RAM Region 0 Size Register
Reserved
C021h
FDBSC1
C024h
FDBSC2
C025h
FDBSC3
C028h
FDBSC4
C029h
FDBSC5
C02Ch
FDBSC6
C02Dh
FDBSC7
C080h
LRAM0BASE1
LRAM0BASE2
LRAM0SIZE
-
C081h
C084h
C085h
C088h
LRAM1BASE1
LRAM1BASE2
PEND0
Queue Manager Linking RAM Region 1 Base Address Register 1
Queue Manager Linking RAM Region 1 Base Address Register 2
Queue Manager Queue Pending 0
C089h
C090h
C091h
PEND1
Queue Manager Queue Pending 1
C094h
PEND2
Queue Manager Queue Pending 2
C095h
PEND3
Queue Manager Queue Pending 3
C098h
PEND4
Queue Manager Queue Pending 4
C099h
PEND5
Queue Manager Queue Pending 5
D000h + 16 × R
D001h + 16 × R
D004h + 16 × R
D005h + 16 × R
E000h + 16 × N
E001h + 16 × N
E004h + 16 × N
E005h + 16 × N
E008h + 16 × N
E009h + 16 × N
E00Ch + 16 × N
E00Dh + 16 × N
E800h + 16 × N
E801h + 16 × N
E804h + 16 × N
E805h + 16 × N
E808h + 16 × N
E809h + 16 × N
QMEMRBASE1[R]
QMEMRBASE2[R]
QMEMRCTRL1[R]
QMEMRCTRL2[R]
CTRL1A
Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)
Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)
Queue Manager Memory Region R Control Register 1 (R = 0 to 15)
Queue Manager Memory Region R Control Register 2 (R = 0 to 15)
Queue Manager Queue N Control Register 1A (N = 0 to 63)
Queue Manager Queue N Control Register 2A (N = 0 to 63)
Queue Manager Queue N Control Register 1B (N = 0 to 63)
Queue Manager Queue N Control Register 2B (N = 0 to 63)
Queue Manager Queue N Control Register 1C (N = 0 to 63)
Queue Manager Queue N Control Register 2C (N = 0 to 63)
Queue Manager Queue N Control Register 1D (N = 0 to 63)
Queue Manager Queue N Control Register 2D (N = 0 to 63)
Queue Manager Queue N Status Register 1A (N = 0 to 63)
Queue Manager Queue N Status Register 2A (N = 0 to 63)
Queue Manager Queue N Status Register 1B (N = 0 to 63)
Queue Manager Queue N Status Register 2B (N = 0 to 63)
Queue Manager Queue N Status Register 1C (N = 0 to 63)
Queue Manager Queue N Status Register 2C (N = 0 to 63)
CTRL2A
CTRL1B
CTRL2B
CTRL1C
CTRL2C
CTRL1D
CTRL2D
QSTAT1A
QSTAT2A
QSTAT1B
QSTAT2B
QSTAT1C
QSTAT2C
180
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6.3 Identification
6.3.1 JTAG Identification
Table 6-31. JTAG Identification Register
REGISTER NAME
CPU WORD ADDRESS
ACRONYM
JTAGID
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
N/A
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG and Device ID. The
register hex value for the device is: 0x0B95 602F. For the actual register bit names and their associated
bit field descriptions, see Figure 6-2 and Table 6-32.
31-28
VARIANT (4-Bit)
R-0000
27-12
11-1
0
PART NUMBER (16-Bit)
R-1011 1001 0101 0110
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-2. JTAG ID Register Description - Register Value - 0x0B95 602F
Table 6-32. JTAG Identification Register Selection Bit Descriptions
BIT
31:28
27:12
11:1
0
NAME
DESCRIPTION
VARIANT
Variant (4-Bit) value: 0000
Part Number (16-Bit) value: 1011 1001 0101 0110
PART NUMBER
MANUFACTURER Manufacturer (11-Bit) value: 0000 0010 111
LSB LSB. This bit is read as a "1".
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6.4 Boot Modes
The device supports the following boot modes:
•
•
•
•
•
•
•
•
•
NOR Flash
NAND Flash
SPI 16- and 24-bit EEPROM or Flash
I2C 16-bit EEPROM
eMMC Controller/MMC/SD/SDHC Card
USB
UART
McSPI
UHPI
The boot mode or method is determined by checking the value of the BootMode[5:0] bits in the BootMode
register ([1C34h]) and the CLKSELSTAT bit in the CCR2 register ([1C1Fh]), which reflect the
configurations of the EM_A[20:15] or GP[26:21] pins and CLK_SEL pin at reset. See Section 5.7.3.4.2,
BootMode Implementation and Requirements.
Figure 6-3. BootMode Register [1C34h]
15
11
10
5
4
0
Reserved
R-0
BootMode[5:0]
Reserved
R-0
R-EM_A[20:15]/GP[26:21]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-33. BootMode Register Field Descriptions
Bit
Name
Description
15:11
Reserved
Reserved
Read-only bits that reflect the latched state of the EM_A[20:19] or GP[26:25] pins on the 10th clock
edge after RESET pin goes high.(1) The Bootloader reads this register value to determine the
frequency of the clock input to the system clock generator. The bootloader requires this frequency
to appropriately program the system clock generator and other peripheral clock dividers.
00:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 11.2896 MHz via the CLK_IN pin
01:
10:9
BootMode[5:4]
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 12.00 MHz or 12.288 MHz via the CLK_IN pin
10:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 16.8 MHz via the CLK_IN pin
11:
CLK_SEL = 0: 12 MHz via the on-chip USB oscillator
CLK_SEL = 1: 19.2 MHz via the CLK_IN pin
(1) The RESET pin is asynchronous to the selected system clock (CLKIN or USB_OSC). The pin could be 10, 11, or even 12 clock cycles
after the rising edge of RESETN due to possible metastability.
182
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Table 6-33. BootMode Register Field Descriptions (continued)
Bit
Name
Description
Read-only bits that reflect the latched state of the EM_A[18:15] or GP[24:21] pins on the first clock
edge after RESET pin goes high. The Bootloader determines boot mode based on this value.
0000: Boot mode: 16-bit NOR flash data boot, system clock generator is in bypass mode.
0001: Boot mode: 16-bit or 8-bit NAND flash data boot, system clock generator is in bypass mode.
0010: Boot mode: UART 9600 baud boot, system clock generator output = input clock x 3
0011: Boot mode: UART 57600 baud boot, system clock generator output = input clock x 3
0100: Boot mode: UART 115200 baud boot, system clock generator output = input clock x 3
0101: Boot mode: SPI 16-bit or 24-bit address Boot (SPI_CLK < 1 MHz), system clock generator
output = input clock x 3
0110: Boot mode: SPI 16-bit or 24-bit address Boot (SPI_CLK < 10 MHz), system clock generator
output = input clock x 3
0111: Polling Mode 2: Check for valid boot image from peripherals in the following order: NOR,
NAND, SPI, I2C, SD/SDHC/MMC/eMMC Controller 0, McSPI, and UART/USB (infinite retry).(2)
8:5
BootMode[3:0]
1000: Boot mode: I2C 16-bit address Boot, 400 kHz, system clock generator is in bypass mode.
1001: Boot mode: SD or SDHC, MMC, or eMMC Controller 0 card boot, system clock generator is
in bypass mode
1010: Boot mode: SD or SDHC, MMC, or eMMC Controller 1 card boot, system clock generator is
in bypass mode
1011: Polling Mode 1: Check for valid boot image from peripherals in the following order: NOR,
NAND, SPI, I2C, SD/SDHC/MMC/eMMC Controller 0, SD/SDHC/MMC/eMMC Controller 1, and
UART/USB (infinite retry).(2)
1100: Boot mode: UHPI 16-bit multiplexed mode boot, system clock generator output = input clock
x 3
1101: Boot mode: McSPI 24-bit address serial flash at 10-MHz mode
1110: Boot mode: McSPI 24-bit address serial flash at 40-MHz mode
1111: Boot mode: USB boot, system clock generator output = input clock x 3
Reserved
4:0
Reserved
(2) If MMCx_CMD is low, the bootloader continues to check for a valid boot image in the card controller. MMCx_CMD must be high or
toggle in order to move from the card controller to the next peripheral for a valid boot image.
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Figure 6-4. Clock Configuration Register 2 (CCR2) [1C1Fh]
15
6
5
4
3
2
1
0
Reserved
R-0
Reserved
R-x
Reserved
R/W-0
CLKSELSTAT
R-0
Reserved
R-0
SYSCLKSEL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -x = value undetermined
Table 6-34. Clock Configuration Register 2 (CCR2) Field Descriptions
BIT
15:6
5:4
3
NAME
VALUE
DESCRIPTION
RESERVED
RESERVED
RESERVED
0
0
0
Reserved
Reserved
Reserved. This bit must be written to 0.
CLK_SEL pin status bit. This reflects the state of the CLK_SEL pin.
CLK_SEL pin is low (USB Oscillator clock selected).
CLK_SEL pin is high (CLKIN input clock selected).
Reserved. This bit must be written to 0.
2
1
CLKSELSTAT
RESERVED
0
1h
0
System clock source select bit. This bit is used to select between the two main clocking modes
for the DSP: bypass and PLL mode.
In bypass mode, the system clock generator is bypassed and the system clock is set to either
CLKIN or the USB oscillator output (as determined by the CLKSEL pin).
0
SYSCLKSEL
In PLL mode, the system clock is set to the output of the system clock generator.
Bypass mode is selected.
0
1
PLL mode is selected.
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6.4.1 Invocation Sequence
The boot sequence is a process by which the device's on-chip memory is loaded with program and data
sections from an external image file (in flash memory, for example). The boot sequence also allows,
optionally, for some of the device's internal registers to be programmed with predetermined values. The
boot sequence is started automatically after each device reset. For more details on device reset, see
Section 5.7.3, Reset.
This device can boot from EMIF, UART, SPI, I2C, eMMC, MMC, SD, SDHC, UHPI, McSPI, or USB
interface. For a complete description of the boot options, see Using the TMS320C5517 Bootloader
[literature number SPRABP1].
The peripheral interface that the device boots from is determined by the configuration of the EM_A[20:15]
or GP[26:21] pins at reset. The values of EM_A[20:15] or GP[26:21] are latched at reset into the
BootMode[5:0] bits in the BootMode register (1C34h) and the Bootloader reads the bits to determine a
peripheral interface for booting.
The on-chip Bootloader allows the DSP registers to be configured during the boot process, if the optional
register configuration section is present in the boot image. For more information on the boot modes
supported, see Section 6.4, Boot Modes.
See Figure 6-5, Boot Timing, and the notes at the bottom of the figure, for an illustration of the boot
sequence.
POWERGOOD
(internal)
(3)
(1)
RESETN
(2)
(POWERGOOD &&
RESETN)
(internal)
CLKIN or
USB_Osc
System Reset
(internal)
(DSP & Periphs)
22 clocks
65535 clocks if CLK_SEL=1,
131071 clocks if CLK_SEL=0
(1) Enter the boot sequence described in boot sequence Step 1.
(2) The maximum wait time from reset between (1) and (2) until the reset is released is 20 ms.
(3) The bootloaded code starts. The best-case time is 200 ms from the start of the boot sequence (see note 2) due to the BG_CAP
settling time in Step 18. The worst-case time is the loading time for the bootloaded code when it exceeds 200 ms.
Figure 6-5. Boot Timing
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The device bootloader follows the following steps:
1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP or MC is 0 by default, so
0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode. The input clock is assumed to be
in the range of 11.2896–19.2 MHz.
2. Set CLKOUT slew rate control to slow slew rate.
3. Idle all peripherals and HWA.
4. Apply manufacturing trim to the bandgap references.
5. Disable CLKOUT.
6. The Bootloader configures the system clock generator based on boot mode (see Section 6.4, Boot
Modes, for details on boot mode) and enables TIMER0 to count the settling time of BG_CAP.
Bootloader will try this main loop infinitely if it cannot get the correct boot signature.
[Main Loop]
7. If McSPI boot, test for 24-bit McSPI flash boot on SPI_CS[0] using a clock-rate close to, but not over,
10 MHz, or a clock-rate close to, but not over, 40 MHz based on the boot mode. Set Serial Port 1
Mode on the External Bus Selection Register to 1:
(a) Check the first two bytes read from the boot table for a boot signature match using 24-bit address
mode.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt McSPI Serial Memory boot and go to step 19.
8. If UHPI boot, the external host has to communicate in 16-bit multiplexed mode:
Note: The bootloader sets up the UHPI slave to handshake with an external UHPI master.
(a) The external host power up the device and must wait for the settling time of BG_CAP to elapse
before executing the next step.
(b) The bootloader waits for the external host to finish transferring the data.
(c) External Host writes to device on-chip memory. The code or data sections are directly loaded to
the desired locations on device by the external host.
(d) External Host interrupts the device through the DSP_INT in the UHPIC register after code transfer
complete.
(e) Bootloader branches to the entry point. The entry point is located in the last block of SARAM, word
addresses 0x27FFA and 0x27FFB. To ensure data integrity, the external host writes two 16-bit
signatures in 0x27FFC and 0x27FFD with respective values of 0x1234 and 0xABCD. If the
address of the entry point is in DARAM space or incorrect signatures are detected in 0x27FFC and
0x27FFD, go to step 18.
(f) Go to step 19.
9. If NOR boot, test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
Note: The booatloader requires NOR flash that supports a reset command (0xF0 on data).
(a) Check the first 2 bytes read from boot signature.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt NOR boot and go to step 19.
10. If NAND boot, test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
(a) Check the first 2 bytes read from boot table for a boot signature match. If the boot signature is not
valid, read the first 2 bytes again using 8-bit access on all asynchronous CS spaces (EM_CS[2:5])
(b) If the boot signature is still not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt NAND boot and go to step 19.
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11. If SPI boot, test for 16- and 24-bit SPI EEPROM or Flash boot on SPI_CS[0] using a clock-rate close
to, but not over, 1 MHz, or a clock-rate close to, but not over, 10 MHz based on the boot mode. Set
Parallel Port Mode on the External Bus Selection Register to 5, then set to 6:
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode.
(c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 18.
(d) Set Register Configuration, if present in boot image.
(e) Attempt SPI Serial Memory boot and go to step 19.
12. If I2C boot, test for 16-bit I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt I2C EEPROM boot and go to step 19.
13. If eMMC, MMC, SD, or SDHC Controller 0 boot, program SD0 and search for the filename
“bootimg.bin" under the first partition’s root directory. For SD or SDHC, the device must comply with
SD/SDHC specification v1.1 or v2.0 for FAT16 or FAT32 using SD or SDHC unsecure mode.
If eMMC, the bootloader will check the boot partition for a bootable image before checking the root
directory for "bootimg.bin". For eMMC or MMC, the device must comply with eMMC/MMC specification
v4.3 for FAT32 using eMMC or MMC nonencrypted mode.
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt eMMC, MMC, SD, or SDHC boot and go to step 19.
14. If eMMC, MMC, SD, or SDHC Controller 1 boot, program SD1 and search for the filename
“bootimg.bin" under the first partition’s root directory. For SD or SDHC, the device must comply with
SD/SDHC specification v1.1 or v2.0 for FAT16 or FAT32 using SD or SDHC unsecure mode.
If eMMC, the bootloader will check the boot partition for a bootable image before checking the root
directory for "bootimg.bin". For eMMC or MMC the device must comply with eMMC/MMC specification
v4.3 for FAT32 using eMMC or MMC nonencrypted mode.
Note: Do not boot from eMMC if no valid image is present. Booting from eMMC without a valid image
will put the card into an inactive state.
(a) Check the first two bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, go to step 18.
(c) Set Register Configuration, if present in boot image.
(d) Attempt eMMC, MMC, SD, or SDHC boot and go to step 19.
15. If UART boot, set PLL to multiply the input clock by 3 and adjust TIMER0 for the settling time of
BG_CAP. Program UART with 9600-, 57600-, or 115200-baud based on boot mode, 8-bit data, odd
parity, one stop-bit, and auto flow control using CTS or RTS:
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, return to the beginning of step 15.
(c) Attempt UART boot and go to step 19.
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16. If USB boot, set PLL to multiply the input clock by 3 and adjust TIMER0 for the settling time of
BG_CAP. Use USB on endpoint 1. The device has vendor-ID 0x0451 and product-ID 0x9010 and uses
Bulk Endpoint 1 OUT to receive the boot image from the USB host:
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, return to the beginning of step 16.
(c) Attempt USB boot and go to step 19.
17. If polling mode, there is a fixed order of supported boot devices on which a valid image is checked.
–
Polling Mode 1:
(a) NOR
(b) NAND
(c) SPI
(d) I2C
(e) SD/SDHC, MMC/eMMC Controller 0 (see note below)
(f) SD/SDHC, MMC/eMMC Controller 1 (see note below)
(g) UART/USB
–
Polling Mode 2:
(a) NOR
(b) NAND
(c) SPI
(d) I2C
(e) SD/SDHC, MMC/eMMC Controller 0 (see note below)
(f) McSPI
(g) UART/USB
The first device with a valid boot image is used to load and execute user code. If none of these
devices has a valid boot image, the bootloader modifies the CPU clock setup as follows:
–
If CLK_SEL=0, the bootloader powers up the PLL and sets its frequency to 36 MHz (12 MHz
multiplied by 3).
–
If CLK_SEL=1, the bootloader powers up the PLL and sets it to multiply CLKIN by 3.
This change in the CPU clock setup is required to meet the minimum frequency needed by the USB
module. After the CPU clock setup changes, the bootloader enters an endless loop and checks for
data received on the UART/USB. If a valid boot image is received, the image is used to load and
execute user code. If no valid boot image is received, the bootloader continues to monitor the boot
devices. If the time since the trim setup exceeds 200 ms during this endless loop, the bootloader re-
enables the low-voltage detection circuit to ensure the circuit is not disabled for an extended period.
Note: If MMCx_CMD is low, the bootloader continues to check for a valid boot image in the card
controller. MMCx_CMD must be high or toggle in order to move from the card controller to the next
peripheral for a valid boot image.
18. If the boot signature is not valid, toggle XF when the retry count reaches 100.
19. Copy the boot image sections to system memory. Then set the XF port low to indicate that boot-up is
complete. Ensure the settling time of BG_CAP has elapsed since step 6 before proceeding to execute
the bootloaded code.
20. Jump to the specified entry point.
6.4.2 DSP Resources Used By the Bootloader
The Bootloader uses SARAM block 31 for the storing of temporary data. This block of memory is reserved
during the boot process. However, after the boot process is complete, it can be used by the user
application.
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7 Device and Documentation Support
7.1 Device Support
7.1.1 Development Support
TI offers an extensive line of development tools for the TMS320C55x DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio Integrated Development Environment (IDE).
The following products support development of TMS320C55x fixed-point DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): Version 5.5.0 or later
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS Version 5.33 or later), which provides the basic
run-time target software needed to support any DSP application.
Hardware Development Tools:
Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the TMS320C55x DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
7.1.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320C5517AZCHA20). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX or TMDX) through fully qualified
production devices or tools (TMS or TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCH), and the temperature range (for example, "Blank" is the commercial
temperature range).
Figure 7-1 provides a legend for reading the complete device name for any DSP platform member.
A
TMS 320
C
5517
ZCH
20
PREFIX
DEVICE MAXIMUM OPERATING FREQUENCY
TMX = Experimental device
TMS = Qualified device
20 = 75 MHz at 1.05 V, 175 MHz at 1.3 V, 200 MHz at 1.4 V
DEVICE FAMILY
TEMPERATURE RANGE
320 = TMS320™ DSP family
Blank = –10° C to 70° C, Commercial Temperature
A = –40° C to 85° C, Industrial Temperature
TECHNOLOGY
C = Dual-supply CMOS
PACKAGE TYPE
DEVICE
ZCH = 196-pin plastic BGA, with Pb-Free
soldered balls [Green]
C55x™ DSP: 5517
SILICON REVISION
A = Revision 2.1
A. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com)
Figure 7-1. Device Nomenclature
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7.2 Documentation Support
7.2.1 Related Documentation
The following documents describe the DSP. To access the documents, click the literature number (e.g.,
SPRUH16) or wiki link.
The current documentation that describes the DSP, related peripherals, and other technical collateral, is
available in the product folder at www.ti.com.
SPRUH16 TMS320C5517 Digital Signal Processor Technical Reference Manual. Collection of
documents providing detailed information on the device including system control, FFT
implementation, and memory access. Detailed information on the device as well as a
functional description of the peripherals supported is also included.
SPRZ383
TMS320C5517 Fixed-Point Digital Signal Processor Silicon Errata. Describes the known
exceptions to the functional specifications for this device.
SPRABP1 Using the TMS320C5517 Bootloader. Describes features of the on-chip ROM for this
device, as well as descriptions of how to interface with possible boot devices and generating
a boot image to store on an external device.
SWPU073 TMS320C55x DSP v3.x CPU Reference Guide. Describes more detailed information on the
C55x CPU.
Wiki
C5505/15/35 Schematic Checklist. Describes recommendations for the device applicable to
unused pins, clocking, power, reset, and peripherals. Description also includes critical
connections, DDR2 routing checklist, and debug considerations, and more.
7.3 社区资源
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术
规范和标准且不一定反映 TI 的观点;请见 TI 的使用条款。
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在
e2e.ti.com 中,您可以咨询问题、共享知识、探索思路,在同领域工程师的帮助下解决问题。
德州仪器 (TI) 嵌入式处理器维基网站 德州仪器 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发
人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体
知识的创新和增长。
7.4 商标
C5000, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, XDS510, XDS560, XDS, E2E are
trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
7.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
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8 Mechanical Packaging and Orderable Information
The following packaging information and addendum reflect the most current data available for the
designated device. This data is subject to change without notice and without revision of this document.
192
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PACKAGE OPTION ADDENDUM
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7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320C5517AZCH20
TMS320C5517AZCHA20
TMS32C5517AZCHA20R
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
NFBGA
ZCH
ZCH
ZCH
196
196
196
184
184
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-10 to 70
-40 to 85
-40 to 85
17AZCH20
Call TI
Call TI
17AZCHA20
17AZCHA20
1000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
TMS320C5517AZCH20
ZCH
ZCH
NFBGA
NFBGA
196
196
184
184
8 x 23
8 x 23
150
150
315 135.9 7620 13.4
315 135.9 7620 13.4
10.1 19.65
10.1 19.65
TMS320C5517AZCHA2
0
Pack Materials-Page 1
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