TMS34020APCM40 [TI]
GRAPHICS PROCESSORS; 图形处理器
| 型号： | TMS34020APCM40 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GRAPHICS PROCESSORS |
| 文件： | 总82页 (文件大小：1356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
145-PIN GB PACKAGE
(TOP VIEW)
• Instruction Cycle Time
– 100 ns . . . TMS34020A-40
– 125 ns . . . TMS34020-32
– 125 ns . . . TMS34020A-32
A B C D E F G H J K L M N P R
1
2
3
• Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
4
5
6
7
8
• Second-Generation Graphics Processor
– Object Code Compatible With the
TMS34010
– Enhanced Instruction Set
– Optimized Graphics Instructions
– TMS34082 Graphics Floating-Point
Interface
9
10
11
12
13
14
15
• Pixel Processing, XY Addressing, and
Window Checking Built into the Instruction
Set
• Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and 6 Arithmetic
Pixel-Processing Options (Raster-Ops)
144-PIN PCM QUAD FLAT PACKAGE
(TOP VIEW)
• 512-Byte LRU On-Chip Instruction Cache
108
73
72
• Optimized DRAM/VRAM Interface
– Page-Mode for Burst Memory Operations
up to 40 Megabytes per Second
– Dynamic Bus Sizing
109
(16-Bit and 32-Bit Transfers)
– Byte-Oriented CAS Strobes
• Flexible Host Processor Interface
– Supports Host Transfers at up to
20 Megabytes per Second
– Direct Access to All of the TMS34020
Address Space
– Implicit Addressing
– Prefetch for Enhanced Read Access
• Flexible Multiprocessor Interface
• Programmable CRT Control
– Composite Sync Mode
– Separate Sync Mode
– Synchronization to External Sync
144
37
36
1
• Direct Support for Special Features of
1M VRAMs
– Load Write Mask
– Load Color Mask
– Block Write
– Write Using the Write Mask
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
description
The TMS34020 and the TMS34020A graphics processors are the second generation of an advanced
high-performance CMOS 32-bit microprocessor optimized for graphics display systems. With a built-in
instruction cache, the ability to simultaneously access memory and registers, and an instruction set designed
to expedite raster graphics operations, the TMS34020 and TMS34020A provide user-programmable control of
the CRT interface as well as the memory interface (both standard DRAM and multiport video RAM). The
4-gigabit (512-megabyte) physical address space is addressable on bit boundaries using variable-width data
fields (1 to 32 bits). Additional graphics addressing modes support 1-, 2-, 4-, 8-, 16- and 32-bit wide pixels.
The information contained in this data sheet is applicable to both the TMS34020 and the TMS34020A, except
that pertaining to clock stretch, which begins on page 21. Use of the term TMS34020 shall refer to both devices
except where noted.
architecture
The TMS34020 is a CMOS 32-bit processor with hardware support for graphics operations such as PixBlts
(raster ops) and curve-drawing algorithms. Also included is a complete set of general-purpose instructions with
addressing modes tuned to support high-level languages. In addition to its ability to address a large external
memory range, the TMS34020 contains 30 general-purpose 32-bit registers, a hardware stack pointer, and a
512-byte instruction cache. On-chip functions include 64 programmable I/O registers that control CRT timing,
input/output control, and parameters required by some instructions. The TMS34020 directly interfaces to
dynamic RAMs and video RAMs and generates raster control signals. The TMS34020 can be configured to
operate as a standalone processor, or it can be used as a graphics engine with a host system. The host interface
provides a generalized communication port for any standard host processor. The TMS34020 also
accommodates a multiprocessing or direct memory access (DMA) environment through the request/grant
interface protocols. Virtual memory systems are supported through bus-fault detection and instruction
continuation.
The TMS34020 provides single-cycle execution of general-purpose instructions and most common integer
arithmetic and Boolean operations from its instruction cache. Additionally, the TMS34020 incorporates a
hardware barrel shifter that provides a single-state bidirectional shift-and-rotate function for 1 to 32 bits.
The local-memory controller is designed to optimize memory-access operations. It also supports pipeline
memory-write operations of variable-sized fields and allows memory access and instruction execution in
parallel.
The TMS34020 graphics processing hardware supports pixel and pixel-array processing capabilities for both
monochrome and color systems at a variety of pixel sizes. The hardware incorporates two-operand and
three-operand raster operations with Boolean and arithmetic operations, XY addressing, window clipping,
window-checking operations, 1 to n bits-per-pixel transforms, transparency, and plane masking. The
architecture further supports operations on single pixels (PIXT instructions) or on two-dimensional arrays of
arbitrary size (PixBlts).
The TMS34020’s flexible graphics processing capabilities allow software-based graphics algorithms without
sacrificing performance. These algorithms include clipping to arbitrary window size, custom incremental curve
drawing, two-operand raster operations, and masked two-operand raster operations.
The TMS34020 provides for extensions to the basic architecture through the coprocessor interface. Special
instructions and cycle timings are included to enhance data flow to coprocessors, such as the TMS34082
floating-point unit, without requiring the coprocessor to decode the instruction stream, generate system
addresses, or move data for the coprocessor through the TMS34020.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
pin assignments – GBL pin-grid-array package
PIN NO.
A1
FUNCTION
PIN NO.
C9
FUNCTION
RCA8
PIN NO.
J1
FUNCTION
EMU0
GI
PIN NO.
N15
P1
FUNCTION
V
SS
LAD17
A2
ALTCH
CBLNK/VBLNK
HSYNC
C10
C11
C12
C13
C14
C15
D1
RCA12
LAD30
J2
V
CC
A3
J3
EMU1
LAD4
P2
HWRITE
HCS
A4
V
V
J13
J14
J15
K1
P3
SS
SS
CC
A5
TR/QE
V
CC
P4
HA30
HA27
HA24
HA22
HA18
HA14
HA13
HA10
HA7
A6
RCA2
V
LAD5
EMU2
RESET
LINT2
P5
A7
RCA3
LAD26
RAS
P6
A8
V
CC
K2
P7
A9
RCA6
RCA7
RCA10
SCLK
D2
CAS2
K3
P8
A10
A11
A12
A13
A14
A15
B1
D3
V
SS
K13
K14
K15
L1
V
SS
P9
†
D4
NC
LAD3
LAD20
LINT1
CAMD
LRDY
LAD1
P10
P11
P12
P13
P14
P15
R1
D13
D14
D15
E1
LAD28
LAD11
LAD10
R1
LAD15
LAD29
L2
HA5
V
SS
L3
HBS0
LAD0
HREAD
HA31
HA28
HA26
HA23
HA20
HA19
HA17
HA16
HA15
HA11
HA9
CAS3
WE
E2
V
CC
L13
L14
L15
M1
B2
E3
CAS1
LAD27
LAD25
LAD9
HRDY
R0
LAD2
B3
V
SS
E13
E14
E15
F1
LAD19
BUSFLT
PGMD
VCLK
R2
B4
CSYNC/HBLNK
VSYNC
RCA0
R3
B5
M2
R4
B6
M3
R5
B7
RCA1
F2
M13
M14
M15
N1
V
SS
R6
B8
RCA5
F3
V
SS
LAD16
LAD18
SIZE16
R7
B9
RCA9
F13
F14
F15
G1
LAD24
LAD8
R8
B10
B11
B12
B13
B14
B15
C1
RCA11
LAD31
R9
V
SS
N2
V
R10
R11
R12
R13
R14
R15
CC
CLKIN
LAD14
HINT
HOE
N3
V
CC
G2
N4
V
SS
LAD13
LAD12
CAS0
G3
HDST
LAD7
N5
HA29
HA25
HA21
HA8
G13
G14
G15
H1
N6
HBS3
V
SS
N7
V
SS
C2
V
CC
LAD23
LCLK1
EMU3
LCLK2
LAD22
LAD21
LAD6
N8
V
SS
SS
C3
DDOUT
DDIN
N9
V
C4
H2
N10
N11
N12
N13
N14
HA12
HA6
C5
V
SS
H3
C6
SF
H13
H14
H15
HBS2
HBS1
C7
RCA4
C8
V
SS
V
CC
†
User must leave pin D4 unconnected. It is provided for device orientation purposes only.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
pin assignments – PCM quad flat package
PIN NO.
1
FUNCTION
PIN NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
FUNCTION
PIN NO.
73
FUNCTION
PIN NO.
109
110
111
FUNCTION
V
SS
V
SS
V
SS
V
SS
2
V
CC
HCS
HA31
HA30
HA29
HA28
HA27
HA26
HA25
HA24
HA23
HA22
HA21
HA20
HA19
HA18
HA17
74
V
CC
V
CC
3
CAS3
CAS2
CAS1
CAS0
75
LAD0
LAD16
LAD1
LAD29
LAD14
LAD30
LAD15
LAD31
SCLK
4
76
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
5
77
6
78
LAD17
LAD2
7
V
CC
RAS
79
8
80
LAD18
9
V
SS
81
V
SS
RCA12
RCA11
RCA10
RCA9
RCA8
RCA7
RCA6
RCA5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R0
R1
82
LAD3
83
LAD19
HOE
84
V
CC
HOST
HRDY
HINT
85
LAD4
LAD20
LAD5
86
87
EMU3
LCLK1
LCLK2
EMU1
EMU0
EMU2
GI
88
LAD21
LAD6
89
V
CC
V
V
90
LAD22
LAD7
V
SS
SS
91
RCA4
RCA3
SS
HA16
HA15
HA14
HA13
HA12
HA11
HA10
HA9
92
LAD23
93
V
V
RCA2
SS
94
RCA1
SS
RESET
LINT2
LINT1
CAMD
BUSFLT
SIZE16
PGMD
LRDY
95
LAD8
LAD24
LAD9
RCA0
96
SF
97
TR/QE
98
LAD25
LAD10
LAD26
LAD11
LAD27
VSYNC
HSYNC
CBLNK/VBLNK
CSYNC/HBLNK
99
HA8
100
101
102
103
104
105
106
107
108
HA7
HA6
V
V
SS
V
V
HA5
V
CC
CC
SS
HBS3
HBS2
HBS1
HBS0
LAD12
LAD28
ALTCH
DDIN
CC
VCLK
CLKIN
V
DDOUT
WE
SS
LAD13
HWRITE
HREAD
V
SS
V
SS
V
SS
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Terminal Functions
LOCAL MEMORY INTERFACE
NAME
ALTCH
I/O
DESCRIPTION
O
Addresslatch. The high-to-low transitions of ALTCH can be used to capture the address and status present of the LAD
signals. A transparent latch (such as a 74ALS373) maintains the current address and status as long as ALTCH remains
low.
BUSFLT
DDIN
I
Bus fault. External logic asserts BUSFLT high to the TMS34020 to indicate that an error or fault has occurred on the
current bus cycle. BUSFLT is also used with LRDY to generate externally requested bus cycle retries so that the entire
memory address is presented again on the LAD pins. In emulation mode, BUSFLT is used for write-protecting mapped
memory (by disabling CAS outputs for the current cycle).
O
O
Data bus direction in enable. This active-high output is used to drive the active-high output-enables on bidirectional
transceivers (such as the 74ALS623). The transceivers buffer data input and output on the LAD0–LAD31 pins when
the TMS34020 is interfaced to several memories.
DDOUT
Data bus direction output-enable. This active-low signal drives the active-low output-enables on bidirectional
transceivers (such as the 74ALS623). The transceivers buffer data input and output on the LAD0–LAD31 pins.
LAD0–LAD31
I/O 32-bit multiplexed local address/data bus. At the beginning of a memory cycle, the word address is output on
LAD4–LAD31 and the cycle status is output on LAD0–LAD3. After the address is presented, LAD0–LAD31 are used
for transferring data within the TMS34020 system. LAD0 is the LSB and LAD31 is the MSB.
LRDY
I
Local ready. External circuitry drives this signal low to inhibit the TMS34020 from completing a local-memory cycle it
has initiated. While LRDY remains low, the TMS34020 will wait unless the TMS34020 loses bus priority or is given an
external RETRY request (through the BUSFLT signal). Wait states are generated in increments of one full LCLK1 cycle.
LRDY can be driven low to extend local-memory read and write cycles, VRAM serial-data-register transfer cycles, and
DRAM refresh cycles. During internal cycles, the TMS34020 ignores LRDY.
PGMD
I
I
Page mode. The memory decode logic asserts this signal low if the currently addressed memory supports burst
(page-mode) accesses. Burst accesses occur as a series of CAS cycles for a single RAS cycle to memory. LRDY is
used with BUSFLT to describe the cycle termination status for a memory cycle. PGMD is also used in emulation mode
for mapping memory.
SIZE16
Bus size. The memory decode logic can pull this signal low if the currently addressed memory or port supports only
16-bit transfers. SIZE16 can also be used to determine which 16 bits of the data bus are used for a data transfer.
In emulation mode, SIZE16 is used to select the size of mapped memory.
DRAM AND VRAM CONTROL
CAMD
I
Column-address mode. This input dynamically shifts the column address on the RCA0–RCA12 bus to allow the
mixing of DRAM and VRAM address matrices using the same multiplexed address RCA0–RCA12 signals.
CAS0–CAS3
RAS
O
O
O
4 column-address strobes. The CAS outputs drive the CAS inputs of DRAMs and VRAMs. These signals strobe the
column address on RCA0–RCA12 to the memory. The four CAS strobes provide byte-write access to the memory.
Row-address strobe. The RAS output drives the RAS inputs of DRAMs and VRAMs. This signal strobes the row
address on RCA0–RCA12 to memory.
RCA0–RCA12
13 multiplexed row-address/column-address signals. At the beginning of a memory-access cycle, the row address
for DRAMs is present on RCA0–RCA12. The row address contains the most significant address bits for the memory.
As the cycle progresses, the memory column address is placed on RCA0–RCA12. The addresses that are actually
output during row and column times depend on the memory configuration (set by RCM0 and RCM1 in the CONFIG
register) and the state of CAMD during the access. RCA0 is the LSB and RCA12 is the MSB.
SF
O
O
O
Special-function pin. This is the special-function signal to 1M VRAMs that allows the use of block write, load write
mask, load color mask, and write using write mask. This signal is also used to differentiate instructions and addresses
for the coprocessor as part of the coprocessor interface.
TR/QE
WE
Transfer/output-enable. This signal drives the TR/QE input of VRAMs. During a local-memory read cycle, TR/QE
functions as an active-low output-enable to gate from memory to LAD0–LAD31. During special VRAM function cycles,
TR/QE controls the type of cycle that is performed.
Write-enable. The active low WE output drives the WE inputs of DRAMs and VRAMs. WE can also be used as the
active-low write-enable to static memories and other devices connected to the TMS34020 local interface. During a
local-memoryread cycle, WE remains inactive high while CAS is strobed active low. During a local-memory write cycle,
WE is strobed active low before CAS is. During VRAM serial-data-register transfer cycles, the state of WE at the falling
edge of RAS controls the direction of the transfer.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Terminal Functions (Continued)
NAME
I/O
DESCRIPTION
HOST INTERFACE
HA5–HA31
I
27 host-address input signals. A host can access a long word by placing the address on these lines. HA5–HA31
correspond to the LAD5–LAD31 signals that output the address to the local memory.
HBS0–HBS3
HCS
I
I
4 host byte selects. The byte selects identify which bytes within the long word are being selected.
Host chip select. A host drives this signal low to latch the current host address present on HA5–HA31 and the host
byte selects on HBS0–HBS3. This signal also enables host access cycles to the TMS34020 I/O registers or local
memory. During the low-to-high transition of RESET, the level on the HCS input determines whether the TMS34020
is halted (HCS is high for host-present mode) or whether it begins executing its reset service routine (HCS is low
for self-bootstrap mode).
HDST
O
Host data-latch strobe. The rising edge of this signal latches data from the TMS34020 local address space to the
external host data latch on host read accesses. It can be used in conjunction with HRDY to indicate that data is valid
in the external data latch.
HINT
HOE
O
O
Host Interrupt. This signal allows the TMS34020 to interrupt a host by setting the INTOUT bit in the HSTCTLL I/O
register. This signal can also be used to interrupt the host if a BUSFLT or RETRY occurs due to a host-access cycle.
Host data-latch output-enable. This signal enables data from host data latches to the TMS34020 local address
space on host-write cycles. HOE can be used in conjunction with HRDY to indicate data has been written to memory
from the external data latch.
HRDY
O
Host ready. This signal is normally low and goes high to indicate that the TMS34020 is ready to complete a
host-initiated read or write cycle. If the TMS34020 is ready to accept the access request, HRDY is driven high and
thehost proceeds with the access. A host can use HRDY logically combined with HDST and HOEtodeterminewhen
the local bus-access cycles have completed.
HREAD
I
I
Host read strobe. This signal is driven low during a read request from a host processor. This notifies the TMS34020
that the host is requesting access to the I/O registers or to local memory. HREAD should not be asserted at the same
time that HWRITE is asserted.
HWRITE
Host write strobe. This signal is driven low to indicate a write request by a host processor. This notifies the
TMS34020 that a write request is pending. The rising edge of HWRITE is used to indicate that the host has latched
data to be written in the external data transceivers. HWRITE should not be asserted at the same time HREAD is
asserted.
SYSTEM CONTROL
CLKIN
I
O
I
Clock input. This system input clock generates the LCLK1 and LCLK2 outputs, to which all processor functions in
the TMS34020 are synchronous. A separate asynchronous input clock (VCLK) controls the video timing and video
registers.
LCLK1, LCLK2
LINT1, LINT2
Local output clocks. These two clocks are 90 degrees out of phase with each other. They provide convenient
synchronouscontrolofexternalcircuitrytotheinternaltiming. AllsignalsoutputfromtheTMS34020(excepttheCRT
timing signals) are synchronous to these clocks.
Local interrupt requests. Interrupts from external devices are transmitted to the TMS34020 on LINT1 and LINT2.
Each local interrupt signal activates the request for one of two interrupt-request levels. An external device generates
an interrupt request by driving the appropriate interrupt-request pin to its active-low state. The signal should remain
low until the TMS34020 recognizes it. These signals can be applied asynchronously to the TMS34020; they are
synchronized internally before use.
RESET
I
System reset. During normal operation, RESET is driven low to reset the TMS34020. When RESET is asserted
low, the TMS34020’s internal registers are set to an initial known state and all output and bidirectional pins are driven
either to inactive levels or to the high-impedance state. The TMS34020’s behavior following reset depends on the
level of the HCS input just before the low-to-high transition of RESET. If HCS is low, the TMS34020 begins executing
the instructions pointed to by the reset vector. If HCS is high, the TMS34020 is halted until a host processor writes
a 0 to the HLT bit in the HSTCTLL register.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Terminal Functions (Continued)
NAME
I/O
DESCRIPTION
POWER
Nominal 5-volt power supply inputs. 9 pins.
Electrical ground inputs. 17 pins.
EMULATION CONTROL
†
V
V
I
I
CC
†
SS
EMU0–EMU2
EMU3
I
Emulation pins 0–2.
Emulation pin 3.
O
MULTIPROCESSOR INTERFACE
GI
I
Bus grant input. External bus artitration logic drives GI low to enable the TMS34020 to gain access to the
local-memory bus. The TMS34020 must release the bus if GI is high so that another device can access the bus.
R1, R0
O
Bus request and control. These two signals indicate a request for use of the bus in a multiprocessor system; they
are decoded as shown below:
R1 R0
Bus Request Type
0
0
1
1
0
1
0
1
High-priority bus request
Bus-cycle termination
Low-priority bus request
No bus request pending
A high-priority bus request provides for VRAM serial-data-register transfer cycles (midline or blanked), DRAM
refresh(when12ormorerefreshcyclesarepending), orahost-initiatedaccess. Theexternalarbitrationlogicshould
grant the request as soon as possible by asserting GI low.
A low-priority bus request is used to provide for CPU-requested access and DRAM refresh (when less than 12
refresh cycles are pending).
Bus-cycle termination status is provided so that the arbitration logic can determine that the device currently
accessing the bus is completing an access and other devices can compete for the next bus cycle. A no bus request
pending status is output when the currently active device does not require the bus on subsequent cycles.
VIDEO INTERFACE
CBLNK / VBLNK
CSYNC / HBLNK
O
Composite blanking/vertical blanking. You can program this signal to select one of two blanking functions:
Composite blanking for blanking the display during both horizontal and vertical retrace periods in
composite-sync-video mode.
Vertical blanking for blanking the display during vertical retrace in separate-sync-video mode.
Immediately following reset, this signal is configured as a CBLNK output.
I/O
Composite sync/horizontal blanking. You can program this signal to select one of two functions.
Composite sync (either input or output as set by a control bit in the DPYCTL register) in composite-sync-video
mode:
Input: Extracts HSYNC and VSYNC from externally generated horizontal sync pulses.
Output: Generates active-low composite-sync pulses from either externally generated HSYNC and VSYNC
signals or signals generated by the TMS34020’s on-chip video timers.
Horizontal blank (output only) for blanking the display during horizontal retrace in separate-sync-video mode.
Immediately following reset, this signal is configured as a CSYNC input.
†
For proper TMS34020 operation, all V
CC
and V
pins must be connected externally.
SS
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Terminal Functions (Continued)
VIDEO INTERFACE
DESCRIPTION
NAME
HSYNC
I/O
I/O
Horizontal sync. HSYNC is the horizontal sync signal that controls external video circuitry. You can program this
signal to be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, HSYNC is the active-low horizontal-sync signal generated by the TMS34020’s on-chip video
timers.
Asaninput, HSYNCsynchronizestheTMS34020video-controlregisterstoexternallygeneratedhorizontal-sync
pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this allows for any external
pipelining of signals.
Immediately following reset, HSYNC is configured as an input.
SCLK
I
Serial data clock. This signal is the same as the signal that drives VRAM serial data registers. This allows the
TMS34020to track the VRAM serial dataregistercount, providingserial-register-transferandmidline-reloadcycles.
(SCLKcanbeasynchronoustoVCLK;however, ittypicallyhasafrequencythatisamultipleoftheVCLKfrequency).
VCLK
I
Video clock. This clock is derived from a multiple of the video system’s dotclock and is used internally to drive the
video timing logic.
VSYNC
I/O
Vertical sync. VSYNC is the vertical sync signal that controls external video circuitry. You can program this signal
to be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, VSYNC is the active-low vertical-sync signal generated by the TMS34020’s on-chip video timers.
As an input, VSYNC synchronizes the TMS34020 video-control registers to externally generated vertical-sync
pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any external
pipelining of signals.
Immediately following reset, VSYNC is configured as an input.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
functional block diagram
Buffer/
Page-mode
Register
32
13
27
LAD0 – LAD31
RCA0–RCA12
Host
Address
Latch
HA5–HA31
4
HBS0–HBS3
MUX
DDIN
HCS
HREAD
HWRITE
HINT
HRDY
HDST
Bus
I/O
PC
ST
Control
DDOUT
RAS
Regs
Cache
Host
4
Interface
Register
File A
LRU
CAS0 – CAS3
DRAM/
VRAM
Interface
WE
HOE
Register
File B
TR/QE
ALTCH
SF
GI
R0
R1
Multi-
Processor
Interface
Decode
SP
Local
PGMD
SIZE16
LRDY
BUSFLT
CAMD
Memory
and
EMU0
EMU1
EMU2
EMU3
Bus
Interface
Bus
Emulation
Interface
Timing
ALU
VSYNC
HSYNC
CSYNC/HBLNK
CBLNK/VBLNK
VCLK
CLKIN
LCLK1
LCLK2
Microcontrol ROM
System
Clocks
Barrel
Shifter
Video
Timing
and
Control
Reset and Interrupts
SCLK
RESET, LINT1,
LINT2
3
architecture (continued)
register files
Boolean, arithmetic, pixel-processing, byte, and field-move instructions operate on data within the
general-purpose register files. The TMS34020 contains two register files of fifteen 32-bit registers and a system
stack pointer (SP). The SP is addressed in both register file A and register file B as a sixteenth register. Transfers
between registers and memory are facilitated via a complete set of field-move instructions with selectable field
sizes.
The 15 general-purpose registers in register file A are used for high-level language support and
assembly-language programming. The 15 registers in register file B are dedicated to special functions during
PixBlts and other pixel operations but can be used as general-purpose registers at other times.
stack pointer (SP)
The stack pointer is a dedicated 32-bit internal register that points to the top of the system stack.
program counter (PC)
The TMS34020’s 32-bit program counter register points to the next instruction-stream word to be fetched. Since
instruction words are aligned to 16-bit boundaries, the four LSBs of the PC are always zero.
instruction cache
An on-chip cache contains 512 bytes of RAM and provides unimpeded access to instructions. The cache
operates automatically and is transparent to software. The cache is divided into four 128-byte segments.
Associated with each segment is a 22-bit segment start address register (SSA) to identify the addresses in
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
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memory corresponding to the current contents of the cache segment. Each cache segment is further partitioned
into eight subsegments of four long words (32 bits) each. Each subsegment has associated with it a present
(P) flag to indicate whether the subsegment contains valid data.
ThecacheisloadedonlywhenaninstructionrequestedbytheexecutionsectionoftheTMS34020isnotalready
contained within the cache. A least-recently-used (LRU) algorithm determines which of the four segments of
the cache is overwritten with new data. For this purpose, an internal four-by-two LRU stack keeps track of cache
usage. Although the cache is loaded so as to always fill a subsegment completely, not all eight subsegments
within a segment are necessarily filled (this is dependent upon the instruction stream).
status register
Thestatusregister(ST)isaspecial-purpose32-bitregisterdedicatedtostatuscodessetbytheresultsofimplicit
and explicit compare operations and parameters used to specify the length and behavior of fields 0 and 1.
In addition, during an interrupt, the IX bit in the ST placed on the stack provides indication that execution of an
interruptible instruction (PIXBLT, FILL or LINE) was halted to service the interrupt.
The single-step bit causes a TRAP to the single-step vector (located at address FFFF FBE0h) after the
execution of one instruction when the bit is set high. Normal program execution occurs when the bit is set low.
fields, bytes, words, long words, pixels, and pixel arrays
The TMS34020 outputs a 28-bit address on LAD4–LAD31, which is valid at the falling edge of ALTCH. The most
significant 27 bits (LAD5–LAD31) define a 32-bit long word of physical memory; logically, however, the
TMS34020viewsmemorydataasfieldsaddressableatthebitlevel. Theleastsignificantbitofthe28-bitaddress
(LAD4) is used to select the odd or even word when accessing 16-bit memories (indicated by SIZE16 asserted
low). Primitive data types supported by the TMS34020 include bytes, words, long words, pixels, two
independent fields of from 1 to 32 bits, and user-defined pixel arrays.
Words and long words, respectively, refer to 16- and 32-bit values that are aligned on 32-bit boundaries.
The two independent fields are referenced as field 0 and field 1. The attributes of these fields (field size and sign
extension within a register) are defined in the status register as FS0, FE0, FS1, and FE1. Fields 0 and 1 are
specified independently to be signed or unsigned and from 1 to 32 bits in length. Bytes are special 8-bit cases
of the field data type, while pixels are 1, 2, 4, 8, 16, or 32 bits in length. In general, fields (including bytes) can
start and terminate on arbitrary bit boundaries; however, pixels must pack evenly into 32-bit long words.
pixel operations
Pixel arrays are two-dimensional data types of user-defined width, length, pixel depth (number of bits per pixel),
andpitch(distancebetweenrows). Apixelorpixelarraycanbeaccessedbymeansofeitheritsmemoryaddress
or its XY coordinates. Transfers of individual pixels or pixel blocks are influenced by the pixel-processing,
transparency, window-checking, plane-masking, pixel-masking, or corner-adjustment operations selected. For
further information, see the TMS34020 User’s Guide, literature number SPVU019.
transparency
Transparencyisamechanismthatallowssurroundingpixelsinanarraytobespecifiedasinvisible. Thisisuseful
for ensuring that only the object and not the rectangle surrounding it are written to the display. The TMS34020
provides four transparency modes:
•
•
•
•
No transparency.
Transparency on result equal zero.
Transparency on source equal COLOR0.
Transparency on destination equal COLOR0.
Refer to the TMS34020 User’s Guide for more information.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
I/O registers
The TMS34020 contains an on-chip block of sixty-four 16-bit locations (mapped into the TMS34020’s memory
address space) that are used for I/O control registers. Eight of these are used by the host interface logic and
are not available to the user. Forty-seven I/O registers control parameters necessary to configure the operation
and report status of the following interfaces:
•
•
•
•
•
•
Host interface.
Local memory.
Video timing.
Screen refresh.
External interrupts.
Internal interrupts.
host interface registers
The host interface registers (HSTDATA, HSTADRL, HSTADRH, HSTCTLL, and HSTCTLH) are provided to
facilitate communications between the TMS34020 and a host processor and maintain compatibility with the
TMS34010. The registers are mapped into five of the I/O locations accessible to the TMS34020.
Two of these registers (HSTCTLL and HSTCTLH) are used to provide control by the host. This control consists
of passing of interrupt requests, flushing the instruction cache, halting the TMS34020, transmitting a
nonmaskableinterruptrequesttotheTMS34020, enablingemulationinterrupts, andsettinghost-accessmodes
and configurations.
The other three registers are simple read/write registers to allow the TMS34020 software to leave addresses
for the host at a known location and allow compatibility with some TMS34010 software.
memory interface control registers
Some of the I/O registers are used to control various local memory interface functions, including:
•
•
•
•
•
Frequency of DRAM refresh cycles.
Masking (read/write protection) of individual color planes.
DRAM row/column addressing configuration.
Accessing mode (big endian/little endian).
Bus fault and retry recovery.
video timing and screen refresh
Twenty-eight I/O registers are dedicated to video timing and screen refresh functions. The TMS34020 can be
configured to drive composite sync or separate sync displays.
In composite mode, the TMS34020 can be set to extract VSYNC and HSYNC from an external CSYNC, or it
can be used to generate CSYNC from separate VSYNC and HSYNC inputs. Internally, the TMS34020 can be
set to preset the horizontal and vertical counts on receipt of an external sync signal. This allows compensation
for any combination of internal and external delays that occur in the video synchronization process. The
HCOUNT register is loaded from SETHCNT by an external HSYNC, VCOUNT is loaded from SETVCNT on an
external VSYNC, and an external CSYNC loads both HCOUNT and VCOUNT from SETHCNT and SETVCNT,
respectively.
The TMS34020 directly supports multiport video RAMs (VRAMs) by generating the serial data register transfer
cycles necessary to refresh the display. The memory locations from which the display information is taken, as
well as the number of horizontal scan lines displayed between serial data register transfer cycles, are
programmable.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
The TMS34020 supports various display resolutions and either interlaced or noninterlaced video. The
TMS34020 can optionally be programmed to synchronize to externally generated sync signals so that images
created by the TMS34020 may be superimposed upon images created externally. The external sync mode can
also be used to synchronize the video signals generated by two or more TMS34020s in a multiple-TMS34020
graphics system.
CPU control registers
Five of the I/O registers (CONVDP, CONVMP, CONVSP, CONTROL, and PSIZE) provide CPU control to
configure the TMS34020 for operation with specific characteristics. These characteristics include pitches for
pixel transfers, window-checking mode, Boolean or arithmetic pixel-processing operation, transparency mode,
PixBlt direction control, and pixel size.
interrupt interface registers
Two dedicated I/O registers (INTENB and INTPEND) monitor and mask interrupt requests to the TMS34020,
including two externally generated interrupts and three internally generated interrupts. An internal interrupt
request can be generated on one of the following conditions.
•
Window violation: an attempt has been made to write a pixel to a location inside or outside a specified
window boundary.
•
•
•
•
Host interrupt: the host processor has set the interrupt-request bit in the host control register.
Display interrupt: a specified horizontal line in the frame has been displayed on the screen.
Bus fault.
Single-step emulator.
A nonmaskable interrupt occurs when the host processor sets a control bit in the host interface register (NMI
in HSTCTLH). The host-initiated interrupt is associated with a mode bit (NMIM in HSTCTLH) that enables and
disables saving of the processor state on the stack when the interrupt occurs. This is useful if the host wishes
to use the host interrupt before releasing the TMS34020 to execute instructions (i.e., before the stack pointer
is initialized). The TMS34020 reset function is controlled by a dedicated pin.
memory controller/local memory interface
The memory controller manages the TMS34020’s interface to the local memory and automatically performs the
bit alignment and masking necessary to access data located at arbitrary bit boundaries within memory. The
memory controller operates autonomously with respect to the CPU. It has a write queue one field (1 to 32 bits)
deep that permits it to complete the memory cycles necessary to insert a field into memory without delaying the
execution of subsequent instructions. Only when a second memory operation is required before completion of
the first operation is the TMS34020 forced to defer execution of the subsequent instruction.
The TMS34020 directly interfaces to standard dynamic RAMs and, in particular, to standard video RAMs such
as the TMS44C251 multiport VRAMs. The TMS34020 memory interface consists of the local address/data bus
(LAD), the DRAM row/column address (RCA) bus, and associated control signals. The currently selected word
address (28 bits) and status (4 bits) are multiplexed with data on the LAD bus. The RCA bus allows direct
connection to address/address multiplexed DRAMs from 64K to 16M. Refresh for DRAMs is supported by
CAS-before-RAS refresh cycles.
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
32
BIT 2 –1
(Last Bit in Memory)
ADDRESS
FFFFFFF0h
Interrupt Vectors and
Extended Trap Vectors
68 Words
444 Words
65024 Words
FFFFFBC0h
FFFFFBB0h
Reserved for Interrupt Vectors
and Extended Trap Vectors
FFFFE000h
FFFFDFF0h
General Use and
Extended Trap Vectors
FFF0000h
FFEFFFF0h
26
2
–66560 Words
General Use
(67 042 304 Words)
C0004000h
C0003FF0h
512 Words
Reserved for System I/O
Reserved for I/O Registers
I/O Registers
C0002000h
C0001FF0h
448 Words
64 Words
C0000400h
C00003F0h
C0000000h
BFFFFFF0h
26
(3 × 2 ) –64K
General Use
(201 261 056 Words)
00100000h
000FFFF0h
General Use and Extended
Trap Vectors
64K Words
00000000h
Bit 0
16
(First Bit in Memory)
Figure 1. Memory Map
reset
Reset puts the TMS34020 into a known initial state. This state is entered when the input signal at the RESET
pin is asserted low. While RESET remains asserted, all outputs are in a known state, no DRAM refresh cycles
take place, and no screen refresh cycles are performed.
The state of the HCS input on the CLKIN cycle before the low-to-high transition of the RESET signal determines
whether the TMS34020 will be halted or begin executing instructions. The TMS34020 may be in one of two
modes, host-present or self-bootstrap mode.
1. Host-Present Mode. If HCS is high at the end of reset, TMS34020 instruction execution halts and remains
halted until the host clears the HLT (halt) bit in HSTCTLH (host control register). Following reset, the RAS
cycles required to initialize the dynamic RAMs are performed automatically by the GSP memory control
logic. The host may request a memory access after the eight RAS initialization cycles have completed. The
TMS34020 automatically performs DRAM refresh cycles at regular intervals; although the TMS34020
remains halted until the host clears the HLT bit. Only then does TMS34020 fetch the level-0 vector address
from location FFFFFFE0h and begin executing the reset service routine.
2. Self-Bootstrap Mode. If HCS is low at the end of reset, the TMS34020 first performs eight refresh cycles
to initialize the DRAMs. Immediately following the eight refresh cycles, the GSP fetches the level-0 vector
address from location FFFFFFE0h, and begins executing the reset service routine.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
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At the time the TMS34020 fetches the level-0 vector address (the reset vector), the least significant four bits
(bit-address part) are used to load configuration data that establishes the initial condition of the big endian/little
endian mode and the current RCA bus configuration bits in the CONFIG register as described in the I/O register
section.
Unlike other interrupts and software traps, reset does not save the previous ST or PC values (this can also occur
on host-initiated nonmaskable interrupts if the NMIM bit in HSTCTLH is set to a 1), since the value of the stack
pointer just before a reset is generally not valid, and saving these values on the stack could contaminate valid
memory locations. A TRAP 0 instruction, which uses the same vector address as reset, similarly does not save
the ST or PC values.
asserting reset
A reset is initiated by asserting the RESET input pin to its active-low level. To reset the TMS34020 at power up,
RESET must remain low for a minimum of 40 local clock periods (LCLK1 and LCLK2) after power levels have
become stable. At times other than power up, the TMS34020 may be reset by holding RESET low for a minimum
of four local clock periods; the GSP will enter an internal reset state for 34 local clock cycles. While in the internal
reset state and RESET is high, memory refresh cycles occur.
reset and multiprocessor synchronization
The synchronization of multiple TMS34020s sharing a local memory is done using the RESET input. In systems
where the multiprocessor interface is used to control the access to a common memory, the processors must
be synchronized. Synchronization is achieved by taking RESET high within a specific interval relative to CLKIN.
This may be done by using CLKIN to clock RESET as received by the TMS34020s. All TMS34020s to be
synchronized should use the same CLKIN and RESET inputs. All of the local memory and bus control signals
should be connected in parallel (without buffers) between the processors. After power up, the processors are
not necessarily synchronized with respect to the particular quarter cycle in progress. The rising edge of RESET
is used to set the TMS34020 to a particular quarter cycle by adding Q1 cycles. All TMS34020s in a
multiprocessor environment operate on the same quarter cycle within 10 quarter cycles after the rising edge
of RESET.
reset and DRAM/VRAM initialization
The TMS34020 drives its RAS signal inactive (high) as long as RESET remains low. The specifications for
certain DRAM and VRAM devices require that the RAS signal be driven inactive for 1 millisecond after power
isstabletoprovidetheproperconditionsfortheDRAMs. Typically, eightRAScyclesarealsorequiredtoinitialize
the DRAMs for proper operation. In general, holding RESET low for t microseconds ensures that RAS remains
high initially for t–(10t ) microseconds. The TMS34020 memory controller automatically inserts the required
Q
eight RAS cycles after all resets (after power up or after the internal reset state) by issuing CAS-before-RAS
refresh cycles before it allows the CPU access to memory. A host must delay requests to memory until the
initialization cycles have had sufficient time to complete. Immediately following reset, the TMS34020 is set to
perform a refresh sequence every eight cycles.
At times other than power up, to maintain the memory in DRAMs and do a reset, the RESET pulse must not
exceed the maximum refresh interval of the DRAMs minus the time for the TMS34020 to refresh the memories.
On reset, the TMS34020 is set to do a refresh cycle every eight local clock periods. A 32-MHz (CLKIN) system
with one (refresh) bank of D/VRAM would be completely refreshed in one-sixteenth of the total memory refresh
interval. The reset pulse then should not exceed about fifteen-sixteenths of the total refresh interval required
by the DRAMs to maintain memory integrity.
If the RESET signal remains low longer than the maximum refresh interval specified for the memory, the
previous contents of the local memory may not be valid after the reset.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
initial state following reset
While the RESET pin is asserted low (or while in the internal reset state), the TMS34020’s output and
bidirectional pins are forced to the states below.
INITIAL STATE OF PINS FOLLOWING A RESET (WITH GI LOW)
BIDIRECTIONAL DRIVEN TO
OUTPUTS DRIVEN HIGH
OUTPUTS DRIVEN LOW
HIGH-IMPEDANCE
RAS
HRDY
VSYNC
CAS0–CAS3
WE
CBLNK/VBLNK
DDIN
HSYNC
CSYNC/HBLNK
LAD0–LAD31
TR/QE
DDOUT
ALTCH
HINT
R0
R1
HOE
HDST
EMU3
RCA0–RCA12
SF
NOTE: If GI is high, then all GI-controlled pins will be in the high-impedance state. The GI-controlled pins are RAS, CAS0–CAS3, WE, TR/QE,
DDOUT, DDIN, ALTCH, HOE, HDST, RCA0–RCA12, LAD0–LAD31, and SF.
Immediately following reset, all I/O registers are cleared (set to 0000), with the exception of the HLT bit in the
HSTCTLH register. The HLT bit is set to 1 if the HCS pin is high just prior to the low-to-high transition of RESET;
otherwise, it is set to 0.
Just prior to the execution of the first instruction in the reset routine, the TMS34020’s internal registers are in
the following states:
•
•
•
General-purpose register files A and B are uninitialized.
The ST is set to 0000 0010h.
The PC contains the most significant 28 bits of the vector fetched from memory address FFFF FFE0h
(the least significant four bits of the PC are set to zero).
•
•
The BEN bit in the I/O register CONFIG is set to the least significant bit read from the vector fetched from
memory address FFFF FFE0h.
The CBP, RCM0, and RCM1 bits in the I/O register CONFIG are set to the corresponding bits read from
the vector fetched from memory address FFFF FFE0h. The configuration-byte-protect bit (CBP) can be
set high to prevent further modification of the lower eight bits of the I/O register CONFIG.
The state of the instruction cache at this time is as follows:
•
•
The SSA (segment start address) registers are uninitialized.
The LRU (least-recently-used) stack is set to the initial sequence 0, 1, 2, 3, where 0 occupies the
most-recently-used position and 3 occupies the least-recently-used position.
•
All P (present) flags are cleared to 0s.
15
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TMS34020, TMS34020A
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local memory and DRAM/VRAM interface
The TMS34020 local memory interface consists of an address/data multiplexed bus on which address and data
are transmitted. The associated control signals support memory widths of 16 or 32 bits, burst (page-mode)
accesses, local-memory wait states, and optional external data bus buffers. The TMS34020 DRAM/VRAM
interface consists of an address/address multiplexed bus and the control signals to interface directly to both
DRAMs and VRAMs. The local-memory interface and the DRAM/VRAM interface are interrelated and therefore
considered together for this description. At the beginning of a typical memory cycle, the address and status of
the current cycle are output on the LAD bus, while the row address is output on the row/column address (RCA)
bus. ALTCH and RAS are used to latch the address/status and row address, respectively, on these two buses.
The LAD bus is then used to transfer data to or from the memory while the RCA bus is set to the column address
for the memory. LAD31 is the most significant bit of the address or data.
LAD During the Address Cycle
5
4
3
0
31
ADDRESS
W
STS
ADDRESS — Memory address (select for 128M 32-bit long words)
W = 0
W = 1
STS
— Access to lower 16-bit word (even-addressed word or 32-bit boundary)
— Access to upper 16-bit word (odd-addressed word)
— Bus cycle status code
The address output on the row/column address (RCA) lines is determined by the row/column mode bits (RCM0
and RCM1 in the I/O register CONFIG) and the state of the column address mode pin (CAMD) during each
memory cycle. The CAMD signal is sampled on the internal Q4 clock phase, which allows CAMD to be
generated by static logic wired to the local address/data (LAD) bus.
BASIC MEMORY ROW/COLUMN ACCESS MODES
RCM1
RCM0 VRAM MODE ADDRS
BANKS
CAMD SUPPORT MATRICES
64K × 16, 64K × 32, 256K × 16, 256K × 32, 1M × 16, 1M × 32
2564K × 16, 256K × 32, 1M × 16, 1M × 32, 4M × 32
1M × 16, 1M × 32, 4M × 16, 4M × 32
0
0
1
1
0
1
0
1
64K × N
256K × N
1M × N
8
9
16
8
10
11
4
4M × N
2
4M × 16, 4M × 32, 16M × 32
VRAM Mode = basic size of VRAM addressing supported with CAMD = 0.
Addrs = number of RCA signals required to provide row/column addressing.
Banks = number of possible interleaved 32-bit wide memory spaces.
CAMD Support = possible sizes and configurations of DRAMs that may be supported within the basic VRAM mode.
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
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The following table illustrates the actual logical address bits output on each of the RCA lines during row and
column intervals for each of the four VRAM modes and states of CAMD:
ROW TIME
256K
COLUMN TIME
CAMD = 1
RCA BIT
64K
1M
4M
CAMD = 0
64K
23
22
13
12
11
10
9
256K
26
14
13
12
11
10
9
1M
15
14
13
12
11
10
9
4M
28
14
13
12
11
10
9
12
11
10
9
24
23
22
21
20
19
18
17
16
15
14
13
12
25
24
23
22
21
20
19
18
17
16
15
14
13
26
25
24
23
22
21
20
19
18
17
16
15
14
27
26
25
24
23
22
21
20
19
18
17
16
15
16
15
14
13
12
11
10
9
8
7
6
5
8
8
8
8
4
8
7
7
7
7
3
7
6
6
6
6
2
6
5
5
5
5
1
5
4
4
4
4
0
4
4
4
4
16
In 64K mode with CAMD=0, any eight adjacent RCA0–RCA12 pins output 16 contiguous logical address bits.
The eight most significant addresses are output during row-address time, while the least significant addresses
are output during column-address time. Logical addresses 12 through 16 are output twice during a memory
cycle (during both RAS and CAS falling edges) but at different pins. This allows a variety of VRAM memory
organizations and decoding schemes to be used. When CAMD = 1, the addresses output during
column-address time are changed such that a new logical address mapping occurs, allowing connection of the
RCA signals directly to 256K or 1M DRAMs.
Similarly, for each of the other VRAM modes, direct connection is provided for other DRAM modes requiring
larger matrices than the configuration mode. The following table gives examples of the connections using this
feature.
CONNECTIONS TO RCA FOR CAMD = 1
RCA
12
11
10
9
64K
256K
1M
4M
1M × 32
1M × 16
1M × 32
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × 16
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × 32
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × NN
4M × 16
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
16M × 32
1M × 32
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × NN
1M × 16
256K × 32
256K × NN
256K × NN
256K × NN
256K × NN
256K × NN
256K × NN
256K × NN
256K × NN
256K × 16
8
7
6
5
4
3
2
1
0
16M × 32
NOTE: NN is used for either 16-bit (× 16) or 32-bit (× 32) memory connections.
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
status codes
Status codes are output on LAD0–LAD3 at the time of the falling edge of ALTCH and may be used to determine
the type of cycle that is being initiated. The following table lists the codes and their respective meanings.
CODE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
STATUS
TYPE
Coprocessor Code
Emulator Operation
Host Cycle
Other
(00XX)
DRAM Refresh
Video-generated DRAM Serial Register Transfer
CPU-generated VRAM Serial Register Transfer
Write Mask Load
VRAM
(01XX)
Color Latch Load
Data Access
Cache Fill
Instruction Fetch
Interrupt Vector Fetch
Bus Locked Operation
Pixel Operation
CPU
(1XXX)
Block Write
Reserved
dynamic bus sizing
The TMS34020 supports dynamic bus sizing between 16 and 32 bits on any local memory access. Any
port/memory that is only 16 bits wide must assert SIZE16 low during Q1 (to be valid at the start of Q2) of the
bus cycle accessing the even memory word (LAD4 = 0) corresponding to its address.The TMS34020 then
performs another memory access to the next 16-bit (odd) word in memory. The TMS34020 samples the SIZE16
pin at the start of Q2 in the second cycle (access to odd word address) to determine to which half of the LAD
bus the port or memory is aligned. If the port is on LAD0–LAD15, the SIZE16 input should be low during the
second cycle access (odd word); otherwise, if the port is on LAD16–LAD31, the SIZE16 input must be high at
this time. The TMS34020 always performs two memory cycles to access the 16-bit wide memories, even when
attempting only a 16-bit transfer.
The TMS34020 outputs the four CAS strobes and LAD bus initially aligned for a 32-bit bus. If the memory is 16
bits wide, the two most significant CAS strobes are swapped with the two least significant strobes when it
accesses the second word, and the halves of the LAD bus are also swapped; therefore, 16-bit memories need
to respond only to the two CAS strobes corresponding to the upper or lower 16 bits of the LAD bus to which they
are connected.
Note that devices connected to LAD0–LAD15 transfer the least significant word during the first cycle and the
most significant word during the second cycle. Data accesses on LAD16–LAD31 transfer the most significant
word first, then the least significant word.
The second memory cycle forced by the SIZE16 pin is performed as a page-mode access if PGMD was low
during the first access. A read-write cycle to 16-bit page-mode memory requires five bus cycles that occur as
address, read0, read1, write0, write1. If a 16-bit transfer is interrupted due to a bus fault, the restart causes the
entire access to be restarted.
For memory that supports page-mode accesses (PGMD low), SIZE16 is sampled during each access to
memory. If SIZE16 is high on the even-word access, then a 32-bit transfer occurs over LAD0–LAD31. If SIZE16
is low on the even-word access (16-bit wide memory), then it is sampled again on the odd-word access to
determine to which half of the LAD bus the memory is connected (low for connection to LAD0–LAD15 or high
for connection to LAD16–LAD31).
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
special 1M VRAM cycles
The TMS34020 provides control for special-function VRAM cycles that are available in the 1M devices. These
cycles are obtained by the appropriate timing control of the SF, CAS, TR/QE, and WE pins of the VRAMs at the
falling edge of RAS. The cycles include:
•
•
•
•
•
•
Load write mask.
Load color mask.
Block write (no mask).
Block write (current mask).
Write using mask.
Alternate write transfer.
In addition, other special modes can be implemented by using external logic.
multiprocessor arbitration
The multiprocessor interface allows multiple processors to operate in a system sharing the same local memory.
The use of the grant in (GI) and the priority request signals (R0 and R1) allows a flexible method of passing
control from one processor to another. The control scheme allows local memory cycles to occur back-to-back,
even when passing control from on TMS34020 to another. Synchronization of multiple TMS34020s in a system
occurs at reset with the rising edge of RESET meeting the setup and hold requirements to CLKIN, so all
TMS34020s are certain to respond to the RESET during the same quarter cycle. RESET is not required to be
synchronous to CLKIN, except to allow synchronization of multiple TMS34020s in a system.
The GI priority for multiprocessing environments is determined by arbitration logic external to the TMS34020.
If GI goes inactive (high), the TMS34020 releases the bus on the next available cycle boundary. If the cycle in
progress has not successfully completed, the TMS34020 restarts the cycle upon regaining control of the bus.
Normally, if the TMS34020 asserts both R0 and R1 low, it should be given the control of the bus by the arbitrator.
host interface
The TMS34020 host interface allows the local memory to be mapped into the host address space. The
TMS34020 acts as a DRAM controller for the host. The address for the host access is latched within the
TMS34020; however, the data for the access is transferred via external transceivers. The host selects the
address of a 32-bit long word for an access using the 27 host-address lines, HA5–HA31. If the host desires byte
addressability, it can select the active bytes for the access by using HBS0–HBS3. The TMS34020 always reads
32 bits from memory; however, on host writes, it uses the host byte selects to enable CAS0–CAS3 to memory.
The address and byte selects are latched at the falling edge of HCS within the TMS34020. The host indicates
a read or write by asserting HREAD or HWRITE (as appropriate) either before or after HCS. HREAD and
HWRITE must never be asserted at the same time.
The TMS34020 responds to a host-read request by latching the requested data in the external latches and
providing HRDY to the host, indicating that the read cycle is completing. The rising edge of HDST with HRDY
high indicates data is latched in the external transceivers.
The host indicates that a write to a particular location is required by providing the address and asserting the
HWRITE signal. The host must maintain both HCS and HWRITE asserted until valid data is in the transceivers.
(The rising edge of HOE with HRDY high indicates that the data previously stored in the external transceivers
has been written to memory.) Typically, the rising edge of HWRITE is used to strobe the data into the latches
and signal the TMS34020 that the write access can start. The TMS34020 uses its byte-write capability to write
only to the selected bytes.
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
The TMS34020 always accesses the required location as latched at the falling edge of HCS; however, in order
to increase the data rate, a look-ahead mechanism is implemented. The HINC (host increment enable) and
HPFW (host prefetch after write enable) bits in the host control register (HSTCTLH) must be appropriately set
to make optimum use of this feature. These bits provide four modes of operation as indicated in the following
table:
HINC
HPFW
HOST ACCESS MODE
RANDOM/SAME
DESCRIPTION
No increment, no prefech
0
0
1
1
0
1
0
1
RANDOM/SAME
BLOCK
No increment, no prefetch
Increment after read or write, prefetch after read
Increment after write, prefetch after write
READ/MODIFY/WRITE
WhentheTMS34020isprogrammedforblock-modeorread/modify/writeaccesses, thehostcanstilldorandom
accesses because the TMS34020 always uses the address provided at the falling edge of HCS; however, there
is a prefetch to the next sequential address. The prefetch occurs after reads in block mode and after writes in
read/modify/write mode. The TMS34020 compares the address latched by HCS on host reads to see if it is the
same as that of the last prefetched data. If the addresses match, data is not reaccessed, but HRDY is set high
to indicate that the data is presently available.
dynamic bus sizing on host accesses
If the host makes a read access to a 16-bit-wide memory, the TMS34020 automatically does the second cycle
required to read the rest of the 32-bit word (even if the host did not require a 32-bit cycle). The external logic
must comprehend the sense of SIZE16 or the CAS strobes during the accesses in order to route the data into
the proper external host data transceivers. The TMS34020 uses the host byte selects (HBS0–HBS3) to enable
the CAS strobes when doing a host write.
coprocessor interface
Support for coprocessors is provided through special instructions and bus cycles that allow communication with
the coprocessor. A coprocessor may be register-based, depending on the TMS34020 to do all address
calculations, or it may operate as its own bus controller, using the multiprocessor arbitration scheme. Five basic
cycles are provided for direct communication and control of coprocessors.
1. TMS34020 to coprocessor.
2. Coprocessor to TMS34020.
3. Move memory to coprocessor.
4. Move coprocessor to memory.
5. Coprocessor internal command.
The first four of these cycles provide for command of the coprocessor in addition to the movement of parameters
to and from the coprocessor. In this manner, parameters can be sent to the coprocessor and operated upon
without an explicit coprocessor command cycle.
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
instruction set
The TMS34020 instruction set can be divided into five categories:
1. Graphics instructions.
2. Coprocessor instructions.
3. Move instructions.
4. General-purpose instructions.
5. Program control and context switching.
Specialized graphics instructions manipulate pixel data that is accessed via memory addresses or XY
coordinates. These instructions include graphics operations, such as array and raster ops, pixel processing,
windowing, plane masking, pixel masking, and transparency. Coprocessor instructions allow for the control and
data flow to and from coprocessors that reside in the system. Move instructions comprehend the bit-addressing
and field operations, which manipulate fields of data using linear addressing for transfer to and from memory
and the register file. General purpose instructions provide a complete set of arithmetic and Boolean operations
on the register file, as well as general program control and data processing. Program control and context
switching instructions allow the user to control flow and to save and restore information using instructions with
both register-direct and absolute operands.
clock stretch
The TMS34020A supports a clock stretching mechanism, which is described in outline below.
With advances in semiconductor manufacturing, new versions of the TMS34020A can be made, each
supporting a higher CLKIN frequency. The increase in CLKIN frequency means that the TMS34020A machine
cycles execute more quickly, with a consequent increase in code execution speed. However, there comes a
point when, as the machine cycle time becomes shorter, the local memory control signals begin to violateDRAM
and VRAM timing parameters for certain types of memory access.
The clock-stretch mechanism allows the TMS34020A to slow down and execute those critical local memory
cycles, while still benefiting from the accelerated processing allowed by higher CLKIN frequencies during
noncritical memory access cycles.
Exact timing issues will vary from system to system, reflecting differences in bus buffering, etc., but broadly
speaking the clock-stretch mechanism allows the system designer to interface to slower (and hence cheaper
and more available) memory devices than the designer could use if no stretch mechanism were available.
A normal, unstretched machine cycle consists of four quarter cycles, Q1, Q2, Q3, and Q4. A stretched cycle
consists of five quarter cycles Q1, Q2, Q3, and Q4a, and Q4b.
When clock-stretch mode is enabled, the fourth machine quarter cycle may be stretched to twice its original
length. This stretching takes place only when the TMS34020A attempts certain types of memory cycle.
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Normal Sequence
Normal Cycle
Normal Cycle
Q1
Q2
Q3
Q4a Q4b
Q1
Q2
Q3
Q4
Possible New Sequence
Normal Cycle
Stretched Cycle
The stretch is achieved by holding the internal TMS34020A clocks in the Q4 state for an extra quarter cycle so
all the device outputs remain unchanged during Q4a and Q4b. The TMS34020A stretches only certain machine
cycles so that the execution of code is not slowed unnecessarily.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
enabling clock stretch
Clock-stretch mode is enabled and disabled via a bit in the CONFIG register (C00001A0h).
31
7
6
5
4
3
2
1
0
C
S
E
Loaded at Reset from Reset Vector
Protected Byte
CONFIG register C00001A0h
CSE = 0: Disable stretch mode (normal operation)
CSE = 1: Enable stretch mode
Bit 4 of the CONFIG register is the clock-stretch-enable mode bit. A 0 in this bit will disable stretch mode and
a 1 in this bit will enable stretch mode. The bit is cleared during reset; i.e., stretch mode is disabled by default.
When stretch mode is enabled, the following machine cycles are stretched:
1. All address cycles of all memory access sequences.
2. Read data cycles in read-modify-write sequences.
Notes:
a) The host default cycle shown on page 8-49 of the TMS34020User’sGuide is not stretched because
it is not a true address cycle; i.e., RAS, etc., do not go low.
b) The CPU default cycle, which is similar to the host default cycle in that RAS, etc., do not go low, is
also not stretched.
c) Clock-stretch mode disregards the page-mode input, so that read data cycles in nonpage-mode
read-modify-write sequences are stretched, even though there are no timing constraints that re-
quire a stretch.
d) All other memory subcycles are not stretched, even if the TMS34020A is running with the CSE bit
set to 1.
The advantage of this implementation of clock-stretch mode is that the TMS34020A can execute code at
maximum speed, slowing down only during certain parts of memory access sequences.
It is important to remember that a stretched cycle is 25% longer than a normal cycle, and that the TMS34020A
(with the exception of the video logic, which is clocked independently by VCLK) will effectively slow down during
such a stretched cycle.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
The following are examples of stretch-mode memory operations.
two 32-bit nonpage-mode reads
ADDR
READ
ADDR
READ
Stretch Mode Disabled
4
1
1
2
2
3
4
4
1
4
2
3
4
1
4
2
3
4
1
4
2
3
ADDR
3
READ
ADDR
3
READ
Stretch Mode Enabled
1
2
3
1
2
4
1
2
3
4
Stretch
Stretch
one 32-bit page-mode read-modify-write
ADDR
READ
WRITE
Stretch Mode Disabled
Stretch Mode Enabled
1
1
2
2
3
4
4
1
4
2
3
2
4
1
4
2
3
4
ADDR
3
READ
3
WRITE
1
4
1
2
3
4
Stretch
Stretch
three 32-bit page-mode reads
ADDR
READ
READ
READ
Stretch Mode Disabled
Stretch Mode Enabled
1
1
2
2
3
4
4
1
4
2
3
4
1
4
2
3
4
1
4
2
3
4
ADDR
3
READ
READ
READ
1
2
3
1
2
3
1
2
3
4
Stretch
The stretched cycles are designed to accommodate worst-case 32-bit page-mode accesses, so during some
nonpage-mode memory accesses, stretches that are not essential may be generated. For example:
one 32-bit nonpage-mode read-write
ADDR
READ
ADDR
WRITE
Stretch Mode Disabled
Stretch Mode Enabled
1
1
2
2
3
4
4
1
4
2
3
2
4
1
4
2
3
4
2
1
2
3
4
1
ADDR
3
READ
3
ADDR
3
WRITE
1
4
1
4
4
2
3
4
Stretch
Stretch
Stretch
Stretches are inserted in read-modify-write accesses to help ease bus turn-around timings. In the above
example, the second stretch is not needed to help these timings because the read/write turn-around has the
whole of the address cycle to evaluate.
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
a clock-stretch timing example, TMS34020A-40 and 100-ns VRAMs
This example analyzes a memory interface timing parameter. It shows that the clock stretch mechanism can
be used to allow the TMS34020A-40 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
1. TMS34020A-40, which has a 40-MHz clock input frequency and hence a 100-ns cycle time, so
t
= 25 ns. Timing parameters are taken from the TMS34020 data sheet.
Q
2. TMS44C251-10 256K × 4 bit VRAM. Timing parameters are taken from the appropriate section in
the Texas Instruments MOS Memory Data Book, 1989.
row address hold data after RAS low, t
h(ADV-REL)
Without clock stretch
TMS44C251 t
Row address hold time after RAS low.
Min = 15 ns
Min = t – 5 ns = 20 ns.
h(RA)
TMS34020A Parameter 88 Hold time, row address valid after RAS low.
Q
If RAS is passed through a PAL with a delay of 7 ns then t
This violates the 15 ns minimum.
seen by the VRAM is 20 ns – 7 ns = 13 ns.
h(RA)
With clock stretch
TMS34020A Parameter 88 Hold time, row address valid after RAS low.
Min = 2t – 5 ns = 45 ns.
Q
With the same 7-ns PAL delay, the VRAM sees t
minimum of 15 ns.
as 45 ns – 7ns = 38 ns, which does not violate the VRAM
h(RA)
cycle timing examples
The following figures show examples of many of the basic cycles that the TMS34020 uses for memory access,
VRAM control, multiprocessor bus control, and coprocessor communication. These figures should not be used
todeterminespecificsignaltimings, butcanbeusedtoseesignalrelationshipsforthevariouscycles. Q4phases
that could be stretched are marked with a * on the diagrams. The conditions required for the stretch are:
1. The design uses a TMS34020A
2. The CONFIG register’s CSE bit is set to 1
3. The TMS34020A is doing either:
a) Any address cycle, or
b) A read data cycle in a read-modify-write sequence.
The following remarks apply to memory timing in general. A row address is output on RCA0–RCA12 at the start
of a cycle, along with the full address and status on LAD0–LAD31. These remain valid until after the fall of
ALTCH and RAS. The column address is then output on RCA0–RCA12, and LAD0–LAD31 are set to read or
write data for the memory access. During a write, the data and WE are set valid prior to the falling edge of CAS;
the data remains valid until after WE and CAS have returned high.
Large memory configurations may require external buffering of the address and data lines. The DDIN and
DDOUT signals coordinate these external buffers with the LAD bus.
PAL is a trademark of Advanced Micro Devices, Inc.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Standard Memory Read Cycle
Data Transfer
Page-Mode Read
Data Transfer
Subcycle
Address Subcycle
Subcycle
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
GI
Address
LAD (TMS34020)
LAD (Memory)
CAMD
Data
Data
2nd Column
Row
1st Column
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTES: A. LAD (TMS34020): Output to the LAD bus by the TMS34020.
LAD (memory): Output to the LAD bus by the memory.
B. LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle accesses to 32-bit-wide memory space.
Figure 2. Local Memory Read Cycle Timing (With Page Mode)
During the address output to the LAD bus by the TMS34020, the least significant four bits (LAD0–LAD2)contain
a bus status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports page-mode
operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without inserting wait
states. DDOUT returns high after the initial address output on LAD (during Q4), indicating that a memory read
cycle is about to take place.
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Address Subcycle
Q1 Q2 Q3 Q4*
Wait State
Q2 Q3
Read Transfer
Q4
Q1
Q4
Q1
Q2
Q3
Q4
Q1
LCLCK1
LCLCK2
GI
Address
LAD (TMS34020)
LAD (Memory)
CAMD
RCA
Data
Row
Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTES: A. LAD (TMS34020): Output to the LAD bus by the TMS34020. LAD (memory): Output to the LAD bus by the memory.
B. Although they are not internally sampled, PGMD and SIZE16 must be held at a valid level at the start of each Q2 until the LRDY
is sampled high.
Figure 3. Local Memory Read Cycle Timing (Without Page Mode, With One Wait State)
LRDY low at the start of the first Q2 after RAS low indicates that the memory requires the addition of wait states.
LRDY high at the next Q2 indicates the cycle can continue without inserting more wait states. PGMD high at
the start of Q2 where LRDY is sampled high indicates that this memory does not support page-mode operation.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Standard Memory Write Cycle
Data Transfer
Page-Mode Write
Data Transfer
Subcycle
Address Subcycle
Subcycle
Q4*
Q4 Q1 Q2 Q3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK1
LCLCK2
GI
LAD
Address
Data Out 1
1st Column
Data Out 2
CAMD
RCA
Row
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTE A: LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle accesses to 32-bit-wide memory space.
Figure 4. Local Memory Write Cycle Timing (With Page Mode)
During the address output to the LAD bus by the TMS34020, the least significant four bits (LAD0–LAD3)contain
a bus-status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports page-mode
operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without inserting wait
states.
DDOUT remains low after the initial address output on LAD (during Q4 after RAS goes low), indicating that a
memory write cycle is about to take place.
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Standard Memory Write Cycle
Data Transfer
Page-Mode Write
Data Transfer
Subcycle
Address Subcycle
Subcycle
Q4
Q1
Q2
Q3 Q4*
Q1
Q2 Q3 Q4* Q1
Q2
Q3
Q4
Q1
LCLCK1
LCLCK2
GI
Address
Data Out
LAD (TMS34020)
LAD (Memory)
CAMD
Data
Row
Column
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 5. Local Memory Read/Modify/Write Cycle Timing
The read/modify/write cycle is used when inserting a field into memory that crosses byte boundaries. This cycle
is actually performed as a read access followed by a page-mode write cycle.
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Refresh Status
CAS-Before-RAS
Refresh End
Q4 Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLCK1
LCLCK2
GI
LAD
Refresh Pseudo-Address
Refresh Psuedo-Address
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 6. Refresh Cycle Timing
Therefreshpseudo-addressoutputtoRCA0–RCA12andLAD0–LAD31comesfromthe16-bitrefreshaddress
register(I/OregisterC000 01F0h)thatisincrementedaftereachrefreshcycle. The16bitsofaddressareplaced
on LAD16–LAD31; all other LAD bus lines will be zero. The logical addresses on RCA0–RCA12 corresponding
to LAD16–LAD31 also output the address from the refresh-address register.
Although PGMD and SIZE16 are ignored during a refresh cycle, they should be held at valid levels. LRDY and
BUSFLT are not sampled until the start of the first Q2 cycle after RAS has gone low.
If a refresh cycle is aborted due to a high-priority bus request (assuming LRDY is low at Q2 after RAS low), a
bus fault, or an external retry, then the count of refreshes pending is not decremented and the same
pseudo-address is reissued when the refresh is restarted.
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Data Transfer
Subcycle
Data Transfer
Subcycle
Address Subcycle
Q2 Q3 Q4*
Q4
Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLCK1
LCLCK2
GI
Low Address
High Address
Low
Hi
LAD0 – LAD15
LAD16 – LAD31
CAMD
RCA
Row
Column (S=0)
Column (S=1)
ALTCH
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTE A: RCA0 may be used to determine accesses to odd or even words because it outputs the least significant bit of the word address during
the column-address time (except in 4M-mode with CAMD = 1).
Figure 7. Dynamic Bus Sizing, Read Cycle
When SIZE16 is selected low, the TMS34020 performs a second cycle to read (or write) the remaining 16 bits
of the word. Reads always access all 32 bits (all CAS strobes are active). Internally, the TMS34020 latches both
the high and the low words obtained on the first read cycle. The sense of SIZE16 on the second (odd-word)
access is used to determine which half of the bus is to be sampled to replace the data word latched during the
first cycle.
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Data Transfer
Subcycle
Data Transfer
Subcycle
Address Subcycle
Q1 Q2 Q3 Q4*
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLCK1
LCLCK2
GI
LAD0 – LAD15
LAD16 – LAD31
CAMD
RCA
Low Address
High Address
Data Low
Data High
Data High
Data Low
Row
Column (S=0)
Column (S=1)
ALTCH
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 8. Dynamic Bus Sizing, Write Cycle
Write accesses to 16-bit memory are performed by swapping the data on upper and lower words of the LAD
bus and exchanging data on CAS0 and CAS1 for data on CAS2 and CAS3, respectively. This is illustrated in
the above example where the TMS34020 is writing the upper 24 bits (LAD8–LAD31) of data to memory. During
the first cycle, data is placed on LAD0–LAD31 as in a normal write. The sampling of SIZE16 low during the first
access indicates that this is 16-bit-wide memory, so the TMS34020 swaps data on the upper and lower halves
of the LAD bus. Notice that during the first cycle CAS0 is inactive (since this byte was not selected) and during
the second cycle CAS2 is inactive due to the exchange of CAS0 for CAS2 and CAS1 for CAS3.
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Write to the PMASK I/O Register
Q2 Q3 Q4* Q1 Q2 Q3
Load-Write-Mask Cycle
Q3 Q4* Q1 Q2
Q4
Q1
Q4
Q1
Q2
Q3
Q4
Q1
GI
LAD
PMASK Address
PMASK Row
PMASK Data
Zero Address
Not PMASK Data
CAMD
RCA
PMASK Column
All-Zero Address
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 9. Load Write Mask Cycle
Thisspecial1MVRAMcontrolcycleisexecutedwhentheVENbitintheCONFIGI/OregisterissetandPMASKL
and/or PMASKH are written. This cycle is indicated by CAS, WE, TR/QE, and SF high at the falling edge of RAS
and SF low at the falling edge of CAS. As the plane mask is copied to the PMASK register(s), it is also output
on the LAD bus to be written to a special register on the VRAM that is used in subsequent cycles requiring a
write mask. During the address portion of the cycle, the status on LAD0–LAD3 indicates a write-mask load is
being performed (status code = 0110). Although CAMD, PGMD, and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
GI
LAD
Zero Address
Color Register Data
CAMD
RCA
All-Zero Address
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 10. Load-Color-Latch Cycle
This special 1M VRAM control cycle is generated by the VLCOL instruction and is indicated by CAS, WE,
TR/QE, and SF high at the falling edge of RAS and SF high at the falling edge of CAS. The data in the COLOR1
register is output on LAD to be written to a special register on the VRAM that is used in subsequent cycles
requiringacolorlatch. Duringtheaddressportionofthecycle, thestatusonLAD0–LAD3indicatesacolor-mask
load is being performed (status code = 0111). Although CAMD, PGMD, and SIZE16 are ignored on this cycle,
they should be held at valid levels as shown.
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
Data Out 1
1st Column
Data Out 2
CAMD
RCA
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 11. Block-Write Cycle Without Mask
This special 1M VRAM control cycle is performed when a VBLT or VFILL instruction is executed and PMASKL
and PMASKH are set to zero. It is indicated by CAS, WE, TR/QE high and SF low at the falling edge of RAS,
and by SF high at the falling edge of CAS. The data on LAD is used as an address mask, and the data stored
in the color latch is written to the VRAM. The address selects chosen by the two least significant bits of the
column addresses within the VRAM are replaced with the four DQ bits latched on the falling edge of CAS. A logic
1 on each bit enables that nibble to be written, while a logic 0 disables the write from occurring. This cycle allows
up to 16 bits to be written into each VRAM (four adjacent nibbles, each set to the value in the color latch) for
a total of 128 bits. During the address portion of the cycle, the status on LAD0–LAD3 indicates a block write
is being performed (status code = 1110). SIZE16 can be used with this cycle, but external multiplex logic is
required to map the data correctly to appropriate memories.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
Data Out 1
1st Column
Data Out 2
CAMD
RCA
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 12. Block-Write Cycle With Mask
This special 1M VRAM control cycle is performed when a VBLT or VFILL instruction is executed and PMASKL
and PMASKH are set to nonzero. It is indicated by CAS, TR/QE, and SF high and WE low at the falling edge
of RAS, and by SF high at the falling edge of CAS. The data on LAD is used as an address mask, and the data
stored in the color latch is written to the VRAM, just as in the block-write cycle without mask, except that the data
in the write mask is used to enable the bits from the color latch that are written to memory. This cycle allows up
to 16 bits to be written into each VRAM (four adjacent nibbles, each set to the value in the color latch as enabled
by the write mask) for a total of 128 bits. During the address portion of the cycle, the status on LAD0–LAD3
indicates a block write is being performed (status code = 1110). SIZE16 can be used with this cycle, but external
multiplex logic is required to map the data correctly to appropriate memories.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
Data Out 1
1st Column
Data Out 2
CAMD
RCA
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 13. Write Cycle Using Mask
This special 1M VRAM control cycle is performed when the PMASKL and PMASKH registers are set to nonzero,
the CST bit in DPYCTL is cleared, the VEN bit in CONFIG is set, and the byte-aligned pixel-write instruction is
executed. This cycle is indicated by CAS, TR/QE, and SF high and WE low at the falling edge of RAS, and by
SF low at the falling edge of CAS. The data on LAD is written to memory just as a normal DRAM write, except
that data in the write mask is used to enable the DQ bits that are written to memory. During the address portion
of the cycle, the status on LAD0–LAD3 indicates that a pixel operation is being performed (status code = 1101).
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Address
Subcycle
Wait
State
Cycle
Completion
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
CAMD
RCA
Tap Point
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 14. Memory-to-Serial-Data-Register Cycle (VRAM Read Transfer)
This VRAM cycle is issued in any of three ways:
1. Pixel operation instruction with the CST bit in DPYCTL set.
2. Horizontal blank reload cycle requested by the video-control logic with the VCE bit in DPYCTL cleared.
3. Video timeout due to SCOUNT match with the value in MLRNXT and the VCE and SSV bits in DPYCTL
cleared.
This cycle is indicated by TR/QE and SF low and CAS and WE high at the time RAS goes low. The timing of
the low-to-high transition of TR/QE is dependent upon the timing of SCLK when doing a midline reload cycle.
During the address portion of the cycle, the status on LAD0–LAD3 indicates either a video-initiated VRAM
memory-to-register transfer (status code = 0100) or a CPU-initiated VRAM memory-to-register transfer
(status code = 0101).
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
CAMD
RCA
Tap Point
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 15. Memory-to-Split-Serial-Data-Register Cycle (VRAM Split-Register Read Transfer)
This VRAM cycle is performed when a video timeout due to a match of the MLRNXT register occurs, the VCE
bit in DPYCTL is cleared, and the SSV bit in DPYCTL is set. This cycle is indicated by TR/QE low and CAS, SF,
and WE high at the time RAS goes low. The timing of the low-to-high transition of TR/QE is not dependent upon
the timing of SCLK because there is not as great a timing constraint to position the cycle as in midline reload.
During the address portion of the cycle, the status on LAD0–LAD3 indicates a video-initiated VRAM
memory-to-register transfer (status code = 0100). Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
CAMD
RCA
Tap Point
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 16. Serial-Data-Register-to-Memory Cycle (VRAM Write Transfer, Pseudo-Write Transfer)
This VRAM cycle is performed when a horizontal blank reload is requested by the video-control logic and the
VCE bit and the SRE bit in DPYCTL are both set. This cycle is indicated by TR/QE, WE and SF low and CAS
high at the time RAS goes low. The SOE pin of the VRAMs is used to select between write transfer and
pseudo-write transfer cycles (SOE must be generated by logic external to the TMS34020). During the address
portion of the cycle, the status on LAD0–LAD3 indicates that a video-initiated VRAM register-to-memory
transfer (status code = 0100) is being performed. Although PGMD and SIZE16 are ignored on this cycle, they
should be held at valid levels as shown.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
GI
LAD
Address
Row
CAMD
RCA
Tap Point
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 17. Serial-Data-Register-to-Memory Cycle (VRAM Alternate-Write Transfer)
This VRAM cycle is performed when a pixel-write instruction is executed with the CST bit in DPYCTL set. This
cycle is indicated by TR/QE and WE low, and SF and CAS high at the time RAS goes low. This cycle does not
require the use of the SOE pin of the VRAM and does not affect the status of the serial I/O pins. During the
address portion of the cycle, the status on LAD0–LAD3 indicates that a CPU-initiated VRAM
register-to-memory transfer (status code = 0101) is being performed. Although PGMD and SIZE16 are ignored
on this cycle, they should be held at valid levels as shown.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Host-Default
Cycle
Beginning
of Cycle
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
LCLK1
LCLK2
LAD
HI-Z
GI
R0
R1
CAMD
RCA
HI-Z
Row
SF
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSFLT
HOE
HI-Z
HI-Z
HDST
Figure 18. Multiprocessor Interface Timing (High-Impedance Signals)
Transition points are shown for R0 and R1 to indicate where they occur relative to the other signals.
This example indicates that the TMS34020 has control of the bus, yields control, and then regains control. The
TMS34020 regains bus mastership as soon as its GI pin is driven active (low). R0 and R1 could be outputting
any of the codes with the exception of the access-termination code. The bus arbitration logic must control the
timing of GI to all of the processors requiring the bus.
It is recommended that TMS34020A clock stretch not be used in multiprocessor systems.
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
GSP1 Read
3 4 1 2
GSP2 Write
3 4 1 2
GSP1 Read With Wait
3 4 1 2 3 4 1
Bus Idle
2 3 4
1
2
3
4
1
2
3
4
1
2
2
3
4
1
1
GI
R0
R1
RAS
CAS
WE
GSP1
TR/QE
DDIN
DDOUT
ALTCH
LRDY
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
ALTCH
GI
R0
R1
RAS
CAS
WE
GSP2
TR/QE
DDIN
DDOUT
Figure 19. Multiprocessor Interface Timing (Passing Control)
Two TMS34020s use the multiprocessor interface to pass control of local memory from one to the other. GSP1
completes a read cycle to the local memory and, although desiring another read, loses the bus to GSP2, which
doesasinglewritecycle(perhapsahost-writeaccess). GSP1thenregainscontrolandcompletesthereadcycle
(shown with a single wait state). Since no further memory-access requests are present, GSP1 maintains control
of the bus and holds all of the local-memory control signals at their inactive levels. LRDY is a common input to
both GSP1 and GSP2.
The host cycle timing diagrams shown in this data sheet are only a sample. If you want more information, see
the TMS34020 User’s Guide.
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
HA/HBS
HCS
HREAD
HWRITE
HRDY
DATA
(out)
Previous Read
Valid
Local-Memory Host Read Cycle
Q4 Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4 Q1
HOE
HDST
LAD
GI
CAMD
RCA
Row
Column
SF
ALACH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
*See clock stretch, page 21.
NOTE A: HRDY goes high at the start of Q2; however, data is not strobed into the external latches until the start of Q4 by HDST going high.
Figure 20. Host Read Cycle (Random/Same Accesses, not From TMS34020 I/O Registers)
Thehost-accessrequestissynchronizedtotheTMS34020atthebeginningofQ4sothatthelocalmemorycycle
can begin in Q1. If the external host-access request occurs after the setup time requirement before Q4, the
request is not considered until the next Q4 cycle. In order to provide back-to-back accesses as indicated in this
example, the host must remove HCS on receipt of HRDY and reassert it before Q4 (it may also remove and
reassert HREAD with HCS).
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
HA/HBS
HCS
HREAD
HWRITE
HRDY
DATA
(out)
Previous Read
1st Read Valid
2nd
Local-Memory Host Read Cycle
Local-Memory Host Prefetch Cycle
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
HOE
HDST
LAD
1st Address
2nd Address
GI
CAMD
RCA
Row
Column
Row
Column
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
*See clock stretch, page 21.
Figure 21. Back-to-Back Host Read Cycles With Implicit Addressing; HREAD as Strobe
Thehost-accessrequestissynchronizedtotheTMS34020atthebeginningofQ4sothatthelocalmemorycycle
may begin in Q1.
In block mode (prefetch after read), the TMS34020 automatically initiates sequential read accesses as soon
as the host deasserts the current read request. In this example, the host reads a location and must wait for the
first access to complete. When the host removes HREAD, indicating the end of the first read, the TMS34020
starts to prefetch the next sequential location. When the host makes the next request, the TMS34020 has
prefetched the data so that the host reads with no delay. While in block mode, the TMS34020 continues to
prefetch data for the host read each time the host removes either HREAD or HCS. If the address present and
latched at the falling edge of HCS matches the previously prefetched address, the HRDY signal is asserted high
so that the host can read with no delay.
In read/modify/write mode (prefetch after write), the TMS34020 initiates the read access as soon as the current
write request is deasserted.
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
HA/HBS
HCS
HREAD
HWRITE
HRDY
DATA
(out)
Prevoius Read
Valid
Local-Memory Host Read I/O Cycle
Q4 Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4 Q1
HOE
HDST
LAD
I/O Data
GI
CAMD
RCA
Row
Column
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
*See clock stretch, page 21.
Figure 22. Host Read Cycle From TMS34020 I/O Registers
The host read of the TMS34020 I/O registers suppresses the generation of TR/QE and CAS so that data is read
fromtheTMS34020ratherthanfrommemory. DDOUTisenabledsothatdataCANflowthroughexternalbuffers
on the LAD bus to the host data latches. The TMS34020 I/O registers may be accessed in any of the host access
modes (random/same, block, or read/modify/write).
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
HA/HBS
HCS
HREAD
HWRITE
HRDY
DATA
(in)
1 st write valid
DATA
(out)
previous read
Local-Memory Host Write Cycle
valid
Local-Memory Host Prefetch
Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4
Q4
Q1
Q2
Q3 Q4* Q1 Q2
Q3
Q4
Q1
HOE
HDST
LAD
1st Address
2nd Address
GI
CAMD
RCA
Row
Column
Row
Column
SF
ALTCH
RAS
CAS
WE
TR/QE
DDIN
DDOUT
LRDY
SIZE16
PGMD
BUSERR
R0
R1
*See clock stretch, page 21.
NOTE A: HRDYgoeshighatthestartofQ2;however, thememorycyclewritingdatatomemoryisnotcompleteduntilthestartofQ4whenALTCH,
CAS, and HOE return high. The host must not strobe new data into the external latch until just after the start of Q4.
Figure 23. Host Write Cycle Back-to-Back With Prefetch of Next Word and Implicit Addressing; HREAD
and HWRITE Used as Strobes
The TMS34020 provides HRDY as soon as it recognizes the host write cycle (if no other host write cycle is in
progress), allowing the host to latch the data in the external data latches. The host then attempts a second write
but does not get an immediate HRDY because the TMS34020 is still writing the first data to memory. As soon
as the memory write completes, HRDY goes high so that the host can latch the new data. The TMS34020 then
writes the second data while the host continues other processing. The host access request is synchronized to
the TMS34020 at the beginning of Q4 so that the local memory cycle can begin in Q1. If the external host access
request occurs after the setup time requirement before Q4, the request is not considered until the next Q4 cycle.
During a host write cycle DDIN is active so that if the write is to the TMS34020 I/O registers, the data can be
required within the GSP.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
CLKIN
RESET
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q3
Q4
Q1
Q2
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q3
Q4
Q1
Q1
Q4
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q2
Q2
Q2
Q2
Case 1
LCLK1
LCLK2
Case 2
LCLK1
LCLK2
Case 3
LCLK1
LCLK2
Case 4
LCLK1
LCLK2
NOTE A: No timing dependencies of LCLK1 and LCLK2 relative to CLKIN or RESET are to be implied from this figure.
Figure 24. Synchronization of Multiple TMS34020s
Although RESET is not normally required to be synchronous to CLKIN, in order to facilitate synchronization of
multiple TMS34020s in a system, the rising edge of RESET must meet the setup and hold requirements to
CLKIN so that all GSPs are certain to respond to the RESET on the same quarter cycle. The four possible
conditions for the state of the TMS34020 at the time RESET goes high are shown above. Quarter cycle 1 is
extended accordingly to provide synchronization of the GSPs. All TMS34020s to be synchronized must share
a common CLKIN and RESET. Within 10 CLKIN cycles after RESET goes high, all GSPs will be synchronized
to the same quarter cycle through the extension of Q1 cycles.
It is recommended that TMS34020A stretch mode not be used in multiprocessor systems.
47
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Command
Data Transfer
Data Transfer
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
GI
Command
Operand 1
Operand 2
LAD (TMS34020)
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
NOTE A: LAD (TMS34020): Output to the LAD bus by the TMS34020
Command:
Operand n:
Coprocessor ID, instruction and status code present on LAD
Data to or from the coprocessor
Figure 25. Transfer TMS34020 Register(s) to Coprocessor (One or Two 32-Bit Values)
This timing example is like a memory write cycle, except that RAS and SF are high.
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Command
Q2 Q3
Data Transfer
Data Transfer
Q4
Q1
Q4
Q1 Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
GI
LAD (TMS34020)
Command
LAD (Coprocessor)
Operand 1
Operand 2
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
NOTE A: LAD (TMS34020):
LAD (coprocessor):
Command:
Output to the LAD bus by the TMS34020
Output to the LAD bus by the coprocessor
Coprocessor ID, instruction and status code present on LAD
Data to or from the coprocessor
Operand n:
Figure 26. Transfer Coprocessor Register to TMS34020 (One or Two 32-Bit Values)
This timing example is like a memory write cycle, except that RAS and SF are high.
49
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GRAPHICS PROCESSORS
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Command Cycle
Address
Q2 Q3 Q4* Q1
Data Tansfer
Data Transfer
Q4
Q1
Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1
LCLK1
LCLK2
GI
LAD
(TMS34020)
Command
Address
LAD
(memory)
Data 1
Data 2
CAMD
RCA
Row
1st Column
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTES: A. LAD (TMS34020):
LAD (memory):
Output to the LAD bus by the TMS34020
Output to the LAD bus by the memory
Command:
Address:
Coprocessor ID, instruction and status code present on LAD
Memory address for the data transfer, with coprocessor status code
Data n:
Data to or from the coprocessor (number of values transferred depends on a value in a register or count in
the instruction)
B. All coprocessor cycles are implemented as 32-bit operations; therefore SIZE16 should be high during these cycles.
Figure 27. Transfer Memory to Coprocessor Register(s)
Data transfer from memory to a coprocessor requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer. The coprocessor can place status
information on the LAD bus during the initialization cycle for the TMS34020. Two types of
memory-to-coprocessor instructions are supported: one provides a count (from 1 to 32) of data to be moved
in the instruction; the other specifies a register in the TMS34020 to be used for the count. Both instructions
specify a register to be used as an index into memory. The index may be post-incremented or pre-decremented
on each transfer cycle.
50
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
Command Cycle
Address
Spacer
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4* Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Data Tansfer
Data Transfer
Q2 Q3 Q4
LCLK1
LCLK2
GI
LAD
(TMS34020)
Command
Address
LAD
Coprocessor)
Status
Data 1
Data 2
CAMD
RCA
Row
1st Column
2nd Column
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
NOTES: A. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
B. LAD (TMS34020): Output to the LAD bus by the TMS34020
LAD (coprocessor): Output to the LAD bus by the coprocessor
Command:
Address:
Data n:
Coprocessor ID, instruction and status code present on LAD
Memory address for the data transfer, with coprocessor status code
Data from the coprocessor (number of values transferred depends on a count in the instruction)
Optional coprocessor status register output to LAD bus
Status:
Figure 28. Transfer Coprocessor Register(s) to Memory (ALTCH High During Data Transfer)
Data transfer from a coprocessor to memory requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer. The coprocessor can place status
information on the LAD bus during the initialization cycle for the TMS34020. The memory cycle includes a dead
cycle to enable the TMS34020 to take the LAD bus drivers to the high-impedance state before the coprocessor
activates its LAD bus drivers to the memory. Two types of memory-to-coprocessor instructions are supported.
Both provide a count (from 1 to 32) of data to be moved in the instruction. Both also specify a register to be used
as an index into memory. One uses this index register with a post-increment and the other uses it with a
pre-decrement after each transfer cycle.
51
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Command Cycle
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
LCLK1
LCLK2
GI
LAD
(TMS34020)
Command
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
NOTES: A. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
B. LAD (TMS34020):
command:
Output to the LAD bus by the TMS34020
Coprocessor ID, instruction and status code present on LAD
C. Although the coprocessor internal command never requires the use of page mode cycles, PGMD should be held at a valid level
during the start of Q2 after ALTCH has gone low.
Figure 29. Coprocessor Internal Operation Command Cycle
This timing example is like a memory write cycle, except that RAS and SF are high.
A coprocessor internal command assumes no transfer of operands or results but causes the coprocessor to
execute some internal function. The coprocessor can place status information on the LAD bus during the cycle
for the TMS34020.
52
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
†
absolute maximum ratings over operating free-air temperature range (see Note 1)
Maximum supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Off-state output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2 V to 7 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 10°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to V
.
SS
recommended operating conditions
MIN
4.75
0
NOM
MAX
5.25
UNIT
V
V
V
Supply voltage
Supply voltage
5
0
CC
‡
0
+ 0.3
+ 0.3
0.8
V
SS
All input pins except CLKIN
CLKIN only
2
V
V
CC
V
IH
HIgh-level input voltage
V
3
CC
V
IL
Low-level input voltage
– 0.3
V
I
I
High-level output current
Low-level output current
Operating free-air temperature
Operating case temperature
400
2
µA
mA
°C
°C
OH
OL
T
TMS34020AGBL40
TMS34020APCM40
0
0
70
A
T
85
C
‡
Take care to provide a minimum inductance path between the V
SS
pins and system ground in order to minimize noise on V .
SS
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
§
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= MIN,
= MAX,
= MAX,
= MAX,
I
I
= MAX
= MIN
2.6
OH
CC
CC
CC
CC
OH
Low-level output voltage
0.6
20
V
OL
OL
V
= 2.8 V
= 0.6 V
O
O
I
O
Output current, leakage (high-impedance)
µA
V
– 20
±20
260
¶
I
I
Input current, leakage (All input pins except EMU0–EMU2 )
V = V
to V
CC
µA
mA
pF
I
I
SS
= MAX
Supply current
V
CC
CC
C
C
Input capacitance
Output capacitance
10
10
i
pF
o
§
¶
All typical values are at V
5 V, T = 25° C.
A
CC =
EMU0–EMU2 will not be connected in a typical configuration. Nominal pullup current will be 500 µA.
NOTE 2: HDST and HOE (output pins) have internal pullup resistors that allow high logic levels to be maintained when the TMS34020 is not
actually driving these pins.
53
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TMS34020, TMS34020A
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SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
signal transition levels
2 V
0.8 V
Figure 30. TTL-Level Inputs
For a high-to-low transition on a TTL-compatible input signal, the level at which the input is said to be no longer
high is 2 V, and the level at which the input is said to be low is 0.8 V. For a low-to-high transition, the level at which
the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is
2 V.
2.6 V
2 V
0.8 V
0.6 V
Figure 31. TTL-Level Outputs
TTL-level outputs are driven to a minimum logic-high level of 2.6 V and to a maximum logic-low level of 0.6 V.
Forahigh-to-lowtransitiononaTTL-compatibleoutputsignal, thelevelatwhichtheoutputissaidtobenolonger
high is 2 V, and the level at which the output is said to be low is 0.8 V. For a low-to-high transition, the level at
which the output is said to be no longer low is 0.8 V, and the level at which the output is said to be high is 2 V.
Timing parameters 12a and 13a do not follow these conventions. They are measured at a 1.5-V level.
test measurement
The test load circuit shown in Figure 32 represents the programmable load of the tester pin electronics, which
are used to verify timing parameters of TMS34020 output signals.
I
OL
Test
Point
From Output
Under Test
V
LOAD
C
LOAD
I
OH
Where:
I
I
V
= 2 mA (all outputs)
= 400 µA (all outputs)
OL
OH
= 1.5 V
LOAD
C
= 65 pF typical load circuit distributed capacitance
LOAD
Figure 32. Test Load Circuit
54
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TMS34020, TMS34020A
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PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
HA5–HA31 and HBS0–HBS3
GI
GI
AD
AL
BC
LAD0–LAD31 and RCA0–RCA12
ALTCH
Any of the bus control input signals
LA
LAD0–LAD31
LINT LINT1, LINT2
OE
HOE
(LRDY, PGMD, SIZE16, or BUSFLT)
CE
CK
CAS0–CAS3
LCLK1 and LCLK2
LCLK1
LCLK2
CLKIN
CAMD
HCS
RC
RD
RE
RQ
RS
RY
RCA0–RCA12
HREAD
RAS
R0 or R1
RESET
CK1
CK2
CKI
CM
CS
HRDY
CT
Any of the bus control output signals
(ALTCH, CAS0–CAS3, RAS, WE,
TR/QE, HOE, or HDST)
DDIN
S
HSYNC, VSYNC, or CSYNC
EMU3
SCLK
SF
SC
SCK
SF
DI
DO
EM
HI
DDOUT
EMU0, EMU1, EMU2
HINT
HSYNC, VSYNC, CSYNC/HBLNK, or
CBLNK/VBLNK
SG
ST
TR
VCK
WR
Any output signal
HDST
TR/QE
VCLK
HS
HWRITE
Lowercase subscripts and their meaning are:
a
c
d
h
su
t
access time
cycle time (period)
delay time
hold time
setup time
transition time
pulse duration (width)
w
The following letters and symbols and their meaning are:
H
L
NV
V
Z
↑
↓
D
High
Low
s = 0 For (i) TMS34020
(ii) TMS34020A, if CSE bit in CONFIG register is
set to 0
(iii) TMS34020A, if CSE bit in CONFIG register is set to
1 and the cycle is not stretched. See page 21.
Not valid
Valid
High impedance
No longer low
No longer high
Driven
s = t
For TMS34020A, if CSE bit in CONFIG register is set to 1
and the cycle is stretched. See page 21.
Q
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TMS34020, TMS34020A
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PARAMETER MEASUREMENT INFORMATION
general notes on timing parameters
The period of the local clocks (LCLK1 and LCLK2) is four times the period of the input clock (CLKIN).
The quarter cycle time (t ) that appears in the following tables is one quarter of a local output clock period, or
Q
equal to the input clock period, t
.
c(CKI)
All output signals from the TMS34020 are derived from an internal clock such that all output transitions for a
given quarter cycle occur with a minimum of skewing relative to each other. In the timing diagrams, the
transitions of all output signals are shown with respect to the local clocks (LCLK1 and LCLK2). The local clock
edge used as a reference occurs one internal clock cycle before the transition specified.
The signal combinations shown in the timing parameters are for timing reference only; they do not necessarily
represent actual cycles. For actual cycle descriptions, please refer to the cycle timings section of this
specification.
56
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PARAMETER MEASUREMENT INFORMATION
CLKIN and RESET timing requirements
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Period of CLKIN (t
)
31.25
10
50
25
8
50
ns
ns
ns
ns
ns
ns
c(CKI)
Q
Pulse duration, CLKIN high
w(CKIH)
w(CKIL)
Pulse duration, CLKIN low
10
8
†
2
‡
10
‡
4
†
5
†
2
‡
10
‡
4
†
5
Transition time, CLKIN
t(CKI)
Hold time, RESET low after CLKIN high
Setup time, RESET high to CLKIN↑
h(CKI-RSL)
su(RSH-CKI)
§
§
§
§
Pulse
duration,
RESET low
Initial reset during power up
Reset during active operation
160t – 40
Q
160t – 40
Q
7
t
ns
w(RSL)
16t – 40
Q
16t – 40
Q
Setup time of HCS low to RESET high to configure
self-bootstrap mode
8
9
t
t
t
8t +55
8t +55
ns
ns
ns
su(CSL-RSH)
d(CS-RSH)
w(CSL)
Q
Q
Delay from HCS↑ to RESET high to configure self-
bootstrap mode
¶
4t – 50
¶
4t – 50
Q
Q
Pulse duration, HCS low to configure GSP in self-
bootstrap mode
10
4t +55
Q
4t +55
Q
†
‡
§
These values are based on computer simulation and are not tested.
These timings are required only to synchronize the TMS34020 to a particular quarter cycle.
The initial reset pulse on power up must remain valid until all internal states have been initialized. Resets applied after the TMS34020 has been
initializedneedtobepresentonlylongenoughtoberecognizedbytheinternallogic;theinternallogicwillmaintainaninternalresetuntilallinternal
states have been initialized (34 LCLK1 cycles).
¶
Parameter 9 is the maximum amount by which the RESET low-to-high transition can be delayed after the start of the HCS low-to-high transition
and still assure that the TMS34020 is configured to run in the self-bootstrap mode (HLT bit = 0) following the end of reset.
1
4
3
4
2
CLKIN
RESET
6
5
7
8
9
10
HCS
Figure 33. CLKIN and RESET Timing Requirements
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PARAMETER MEASUREMENT INFORMATION
local bus timing: output clocks
’34020-32
’34020A-32
’34020A-40
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
†
†
11
12
12a
13
13a
14
15
16
17
18
19
20
21
22
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Period of local clocks LCLK1, LCLK2
Pulse duration, local clock high
4t
+ s
2t –15
4t
+ s
2t –13.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(LCK)
c(CKI)
c(CKI)
w(LCKH)
Q
Q
‡
‡
2t –7
Q
Pulse duration, LCLK1 high
2t –10
w(CK1H)
Q
Pulse duration, local clock low
2t –15+ s
2t –13.5+ s
Q
w(LCKL)
Q
‡
Pulse duration, LCLK1 low
2t –10+ s
2t –7+ s
Q
w(CK1L)
Q
Transition time, LCLK1 or LCLK2
Hold time, LCLK2 low after LCLK1 high
Hold time, LCLK1 high after LCLK2 high
Hold time, LCLK2 high after LCLK1 low
Hold time, LCLK1 low after LCLK2 low
Hold time, LCLK2 high after LCLK1 high
Hold time, LCLK1 low after LCLK2 high
Hold time, LCLK2 low after LCLK1 low
Hold time, LCLK1 high after LCLK2 low
15
13.5
t(LCK)
t
Q
t
Q
t
Q
–15
–15
–15
t
Q
t
Q
t
Q
–13.5
–13.5
–13.5
h(CK1H-CK2L)
h(CK2H-CK1H)
h(CK1L-CK2H)
h(CK2L-CK1L)
h(CK1H-CK2H)
h(CK2H-CK1L)
h(CK1L-CK2L)
h(CK2L-CK1H)
t
–15+ s
t –13.5+ s
Q
Q
3t –15
3t –13.5
Q
Q
3t –15+ s
3t –13.5+ s
Q
Q
3t –15+ s
3t –13.5+ s
Q
Q
3t –15+ s
3t –13.5+ s
Q
Q
†
‡
This is a functional minimum and is not tested. This parameter may also be specified as 4t
These parameters are specified with 1.5-V timing levels (parameters 12 and 13 are specified with standard timing voltage levels as detailed on
page 54).
.
Q
Q1
Q2
11
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
14
12
14
13
LCLK1
12a
19
13a
20
21
15
22
16
11
17
14
18
12
14
13
LCLK2
*See clock stretch, page 21.
NOTE A: Although LCLK1 and LCLK2 are derived from CLKIN, no timing relationship between CLKIN and the local clocks is to be assumed,
except the period of the local clocks is four times the period of CLKIN.
Figure 34. Local Bus Timing: Output Clocks
58
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TMS34020, TMS34020A
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PARAMETER MEASUREMENT INFORMATION
†
output signal characteristics
The following general parameters are common to all output signals from the TMS34020 unless otherwise
specifically given. In the minimum and maximum values given, n is an integral number of quarter cycles.
’34020-32
’34020A-40
’34020A-32
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
Hold time, LCLKx to output signal not valid
t
– 15
t – 13.5
Q
ns
h(CKx-SGNV)
Q
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
t
t
+15
t
+13.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time, LCLKx start of transi-
tion to output signal valid
Q
Q
d(CKx-SGV)
Slow: LAD, RCA, SF
+22
t
+20
Q
Q
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
nt –15
nt –13.5
Q
Q
Hold time, output signal valid to
output signal not valid
‡
‡
t
t
t
t
t
h(SG1V-SG2NV)
d(SG2NV-SG1V)
t(SG)
Slow: LAD, RCA, SF
nt –22
nt –20
Q
Q
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
nt +15
Q
nt +13.5
Q
Delay time, output signal started
transition to output signal valid
Slow: LAD, RCA, SF
nt +22
Q
nt +20
Q
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
15
22
13.5
20
Output signal transition time
Slow: LAD, RCA, SF
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
nt –15
nt –13.5
Q
Q
Pulse duration, output signal high
Pulse duration, output signal low
w(SGH)
Slow: LAD, RCA, SF
nt –22
nt –20
Q
Q
Fast: RAS, CAS, ALTCH,
TR/QE, DDOUT, DDIN,
EMU3, HOE, R0, R1,
HDST, WE
nt –15
nt –13.5
Q
Q
w(SGL)
Slow: LAD, RCA, SF
nt –22
nt –20
Q
Q
†
‡
Also refer to Figure 35 on following page.
For parameters on this page specifying minimum or maximum times between two output signals, the word “fast” or “slow” in column 2 refers to
the signal with a subscript of 1, regardless of the other signal. For example, if you are using the spec “t ”, use the slow value if the
h(SG2NV-SG1V)
signal becoming valid (SG ) is RCA, LAD, or SF; use the fast value otherwise. The pin referred to as SG does not determine fast or slow signal
1
2
time.
59
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Q
Q
Q
Q
Z*
W*
X*
Y*
(see Note A)
LCLKx
t
t
d(CKx-SGV)
t
d(CKx-SGV)
h(CKx-SGNV)
t
w(SGH)
t
SIGNAL a
t
t(SG)
h(CKx-SGNV)
t
d(SGNV-SGV)
t
t(SG)
t
d(SGNV-SGV)
t
h(SGV-SGNV)
h(SGV-SGNV)
t
t
w(SGL)
SIGNAL b
t
h(SGV-SGNV)
t
d(SGNV-SGV)
*See clock stretch, page 21.
indicates the point at which the signal has attained a valid level.
NOTE A: Any of these quarter phases could be 2t if they are stretched. See clock stretch, page 21.
Q
Figure 35. Output Signal Characteristics
All timing parameters relative to the circled points on the diagram have a fast and a slow value. Determine which
value to use for any parameter by the name of the signal that has the circle on it.
example of how to use the general output signal characteristics
Assume a system is using a TMS34020-32. Determine the maximum time from the start of the falling edge of
ALTCH to the time when data must be valid on the LAD bus for a local memory write cycle.
From the local memory write cycle diagram on page 27, the time from the falling edge of ALTCH to valid data
on the LAD bus is roughly Q3 + Q4; i.e., 2t . A more precise value can be obtained by using the table of output
Q
signal characteristics.
The parameter of interest is t
. Note that in the diagram above, there are two representations of
d(SGNV-SGV)
t
that relate SIGNALa and SIGNALb (the third representation of this parameter relates SIGNALb to
d(SGNV-SGV)
itself and is not useful in this example). Let SIGNALa represent ALTCH because ALTCH is making a transition
first. Let SIGNALb represent the LAD bus. By definition, the signal becoming valid (SGV) determines whether
the fast value or the slow value from the table is used. On the diagram, the SGV points are marked with a circle.
In this case, for parameter t
, SGV is the LAD bus. LAD is in the slow group, so the maximum value
d(SGNV-SGV)
fort
isnt +22.Thevaluefornis2fromtheanalysisofthediagramonpage27.Thus,themaximum
d(SGNV-SGV)
Q
time from the start of the falling edge of ALTCH to the time when data must be valid on the LAD bus for a local
memory write cycle is 2t + 22 ns.
Q
60
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GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
host interface timing requirements (see Figure 36 and Note 3)
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
12
12
28
28
28
28
28
18
18
18
MAX
MIN
10
10
25
25
25
25
25
15
15
15
MAX
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time of address prior to HCS↓
Hold time of address after HCS low
Pulse duration of HCS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(AV-CS↓)
h(CSL-AV)
w(CSH)
Pulse duration of HREAD high
w(RDH)
Pulse duration of HWRITE high
w(WRH)
Setup time, HREAD high to HWRITE↓
Setup time, HWRITE high to HREAD↓
Pulse duration of HREAD low
su(RDH-WR↓)
su(WRH-RD↓)
w(RDL)
Pulse duration of HWRITE low
w(WRL)
Setup time, HCS low to HWRITE↑
su(CSL-WR↑)
su(RDL-CK2↓)
su(WRH-CK2↓)
h(CK2↓-RDH)
h(CK2↓-WRL)
su(RDH-CK2↓)
su(CSL-RD↑)
†
†
‡
‡
†
†
‡
‡
Setup time, later of HCS low or HREAD low to LCLK2↓
Setup time, later of HWRITE high or HCS high to LCLK2↓
Hold time, HREAD high after LCLK2↓
Hold time, HWRITE low after LCLK2↓
Setup time, HREAD high to LCLK2↓, prefetch read mode
Setup time, HCS low to HREAD↑
30
30
0
25
25
0
0
0
†§
30
†§
25
18
15
†
‡
§
Setup time to insure recognition of input on this clock edge.
Hold time required to assure response on next clock edge. These values are based on computer simulation and are not tested.
WhentheTMS34020issetforblockreads, usethedeassertionofHREADtorequestalocalmemorycycleatthenextsequentialaddresslocation.
NOTE 3: Although HCS, HREAD, and HWRITE can be totally asynchronous to the TMS34020, cycle responses to the signals are determined
by local memory cycles.
HA0–HA27
HBS0–HBS
3
23
25
24
HCS
32
26
38
30
HREAD
28
31
29
27
HWRITE
LCLK2
35
34
37
36
33
Figure 36. Host Interface Timing Requirements
61
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PARAMETER MEASUREMENT INFORMATION
host interface timing responses (random read cycle) (see Figure 37)
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
†
30
†
25
33
39
t
t
Setup time, later of HCS low or HREAD low to LCLK2↓
ns
ns
su(RDL-CK2↓)
Delay time from LCLK1↑ to HRDY high (end of read
cycle)
t
Q
+20
20
t
Q
+18
18
d(CK1↑-RYH)
Delay time from earlier of HREAD or HCS high to HRDY
low
40
t
ns
d(RDH-RYL)
41
42
43
44
50
t
t
t
t
t
Delay time from LCLK2↓ to HDST low
Delay time from LCLK1↓ to HDST high
Setup time of HDST low to HRDY↑
t
Q
+15+ s
t
Q
+13.5+ s
ns
ns
ns
ns
ns
d(CK2↓-STL)
d(CK1↓-STH)
su(STL-RY↑)
d(RY↑-STH)
h(STH-CTV)
t
Q
+15
t +13.5
Q
t
Q
–15
0
t
Q
–13.5
– 2
Delay time from HRDY↑ to HDST high
Hold time, CAS, TR/QE, DDIN valid after HDST high
2t +15
Q
2t +13.5
Q
†
Setup time to insure recognition of input on this clock edge.
Q4* Q1 Q2
Q3
Q4*
Q1
39
Q2
Q3
Q4*
LCLK1
LCLK2
HCS/HREAD
HRDY
33
33
26
40
41
42
44
43
HDST
50
CAS
TR/QE
DDIN
*See clock stretch, page 21.
Figure 37. Host Interface Timing Responses (Random Read Cycle)
62
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
host interface timing (block read cycle) (see Figure 38 and Note 3)
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
Setup time, HREAD high to LCLK2↓, prefetch read
mode
†
30
†
25
37
39
40
t
t
t
ns
ns
ns
su(RDH-CK2↓)
d(CK1↑-RYH)
d(RDH-RYL)
Delay time from LCLK1↑ to HRDY high
t
Q
+20
20
t
Q
+18
18
Delay time from earlier of HREAD or HCS high to
HRDY low
41
42
43
44
t
t
t
t
Delay time from LCLK2↓ to HDST low
Delay time from LCLK1↓ to HDST high
Setup time of HDST low to HRDY↑
Delay time from HRDY↑ to HDST high
t
Q
+15+ s
t +13.5+ s
Q
ns
ns
ns
ns
d(CK2↓-STL)
d(CK1↓-STH)
su(STL-RY↑)
d(RY↑-STH)
t
Q
+15
t +13.5
Q
t
Q
– 15
t –13.5
Q
2t +15
Q
2t +13.5
Q
DelaytimefromlaterofHREAD or HCS low to HRDY
high after prefetch
45
t
25
20
ns
d(RDL-RYH)
†
Setup time to insure recognition of input on this clock edge. When the TMS34020 is set for block reads, the deassertion of HREAD is used to
request a local memory cycle at the next sequential address location.
NOTE 3. Although HCS, HREAD, and HWRITE can be totally asynchronous to the TMS34020, cycle responses to the signals are determined
by local memory cycles.
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
LCLK1
LCLK2
HCS
37
37
26
26
39
30
HREAD
HRDY
40
40
42
45
43
41
44
HDST
*See clock stretch, page 21.
Figure 38. Host Interface Timing (Block Read Cycle)
63
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TMS34020, TMS34020A
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PARAMETER MEASUREMENT INFORMATION
host interface timing responses (write cycle) (see Figure 39)
’34020-32
’34020A-32
’34020A-40
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
Delay time from later of HCS or HWRITE low to HRDY
high (TMS34020 ready)
46
47
t
t
25
20
ns
ns
d(WRL-RYH)
Delay time from earlier of HCS or HWRITE high to HRDY
low (end of write)
25
20
d(WRH-RYL)
48
49
39
b
t
t
t
t
t
Delay time from LCLK2↓ to HOE low
Delay time from LCLK1↓ to HOE high
Delay time from LCLK1↑ to HRDY high
Hold time, CAS valid high after HOE valid low
Delay time from HRDY↑ to HOE high
t
Q
+15+ s
t +13.5+ s
Q
ns
ns
ns
d(CK2↓-OEL)
d(CK1↓-OEH)
d(CK1↑-RYH)
h(CEH-OEL)
d(RY↑-OEH)
t
t
+15
+20
t
Q
t
+13.5
Q
+18
Q
Q
t
Q
– 10
t
Q
– 7
51
2t +15
Q
2t +13.5
Q
ns
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
LCLK1
LCLK2
34
34
47
27
31
HCS
HWRITE
39
47
HRDY
HOE
49
46
48
51
b
CAS
*See clock stretch, page 21.
Figure 39. Host Interface Timing Responses (Write Cycle)
64
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
local bus timing: bus control inputs (see Figure 40)
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
MAX
3t –45
MIN
MAX
3t –37
†
52
53
t
t
Access time, CAMD valid after address valid on LAD
ns
ns
a(CMV-LAV)
Q
Q
Hold time, CAMD valid after address no longer valid on
LAD
†
0
0
h(LANV-CMV)
Access time, control valid (LRDY, PGMD, SIZE16,
BUSFLT) after ALTCH low
†
54
55
56
t
t
t
3t –35+ s
Q
3t –27+ s
Q
ns
ns
ns
a(BCV-ALL)
Hold time, control (LRDY, PGMD, SIZE16, BUSFLT)
valid after LCLK2 high
†
0
0
h(CK2H-BCV)
Setup time, SIZE16, LRDY, PGMD, BUSFLT valid be-
fore LCLK2↑
†
20
15
su(BCV-CK2↑)
†
CAMD, LRDY, PGMD, SIZE16, and BUSFLT are synchronous inputs. The specified setup, access, and hold times must be met for proper device
operation.
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
LCLK1
LCLK2
LAD
Address
52
53
CAMD
Valid
55
ALTCH
54
LRDY
Valid
PGMD
Valid
56
55
Valid
SIZE16
Valid
Valid
BUSFLT
*See clock stretch, page 21.
Figure 40. Local Bus Timing: Bus Control Inputs
65
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
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PARAMETER MEASUREMENT INFORMATION
local bus timing: bus control inputs (see Figure 41)
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
57
58
t
t
Delay time, ALTCH low after LCLK2↑
Delay time, ALTCH high after LCLK1↓
t
+15
+15
t
+13.5
+13.5
ns
ns
d(CK2↑-ALL)
Q
Q
Q
Q
t
t
d(CK1↓-ALH)
Delay time, LAD0–LAD31 address valid after
LCLK1↑
59
60
61
t
t
t
t
Q
+22
t
Q
+20
ns
ns
ns
d(CK1↑-LAV)
h(LAV-CK2L)
d(CTNV-LAD)
Hold time, LAD0–LAD31 address valid after
LCLK2 low
t
–15+ s
t –12+ s
Q
Q
Delay time, LAD0–LAD31 driven after earlier
of DDIN↓ or CAS↑ or TR/QE↑
†
0
†
2
t
Q
–5+ s
t –5+ s
Q
Hold time, LAD0–LAD31 read data valid after
earlier of DDIN low or RAS, CAS, or TR/QE
high
62
t
ns
h(LAV-CTV)
Delay time, LAD0–LAD31 data valid after
LCLK2↓ (write)
63
64
65
66
67
t
t
t
t
t
t
+22+ s
t
+20+ s
ns
ns
ns
ns
ns
d(CK2↓-LAV)
h(CK2L-LAV)
d(CK1↑-RCV)
d(CK2↓-RCV)
h(RCV-CK2L)
Q
Q
Hold time, LAD0–LAD31 data valid after
LCLK2 low (write)
t
t
–15
t –13.5
Q
Q
Delay time, RCA0–RCA12 row address valid
after LCLK1↑
t
Q
+22
t +20
Q
Delay time, RCA0–RCA12 column address
valid after LCLK2↓
t
+22+ s
t
+20+ s
Q
Q
Hold time, RCA0–RCA12 address valid after
LCLK2 low
–15
t
Q
–12
Q
68
69
70
71
72
t
t
t
t
t
Delay time, DDIN high after LCLK1↑
Delay time, DDIN low after LCLK1↓
Delay time, DDOUT low after LCLK1↑
Delay time, DDOUT high after LCLK1↓
Delay time, DDOUT low after LCLK2↓
t
t
t
t
+15
+15
+15
+15
t
t
t
t
+13.5
+13.5
+13.5
+13.5
ns
ns
ns
ns
ns
d(CK1↑-DIH)
d(CK1↓-DIL)
d(CK1↑-DOL)
d(CK1↓-DOH)
d(CK2↓-DOL)
Q
Q
Q
Q
Q
Q
Q
Q
t
Q
+15+ s
t
Q
+13.5+ s
Setup time, LAD0–LAD31 data valid before
ALTCH↓
73
74
75
e
t
t
t
t
t
t
–16
t
Q
–13
ns
ns
ns
ns
ns
su(LAV-AL↓)
en(DAV-DIH)
dis(DAV-DIL)
h(REL-RCV)
h(CEL-RCV)
Q
Enable time, data valid after DDIN high
(see Note 4)
2t –20
2t –17
Q
Q
Disable time, data high-impedance after DDIN
low (see Note 4)
t
–12+ s
t –10+ s
Q
Q
Hold time, RAS valid low after column address
valid
3t – 22
Q
3t – 12
Q
Hold time, CAS valid low after column address
valid
f
3t – 22
Q
3t – 12
Q
Hold time, WE valid low after column address
valid
g
h
t
t
4t – 22 + s
4t – 18 + s
ns
ns
h(WEH-RCV)
Q
Q
Hold time, LAD data valid after WE valid high
t
Q
– 15
t
Q
– 12
h(LAV-WEH)
†
These values are derived from characterization data and are not tested.
NOTE 4: DDIN is used to control LAD bus buffers between the TMS34020 and local memory. Parameter 74 references the time for these data
buffers to go from the high-impedance state to an active level. Parameter 75 references the time for the buffers to go from an active level
to the high-impedance state.
66
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PARAMETER MEASUREMENT INFORMATION
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
57
63
58
ALTCH
73
64
60
59
Address/Status
66
Data In
Data Out
LAD0–LAD31
75
67
74
67
66
65
67
Row
1st Column
69
2nd Column
RCA0–RCA12
DDIN
62
68
72
71
70
71
DDOUT
RAS
99a
e
f
CAS
61
TR/QE
h
g
WE
*See clock stretch, page 21.
Figure 41. Local Bus Timing: Bus Control Inputs
67
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
local bus timing: RAS, CAS0–CAS3, WE, TR/QE, and SF
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
Hold time, LAD0–LAD31 read data
valid after earlier of DDIN, LCLK2 low
or RAS, CAS, or TR/QE high
62
t
0
2
ns
h(LAV-CTV)
76
77
78
79
80
81
82
83
84
85
t
t
t
t
t
t
t
t
t
t
Delay time, RAS low after LCLK1↓
Delay time, RAS high after LCLK1↓
Delay time, CAS low after LCLK1↑
Delay time, CAS high after LCLK1↓
Delay time, WE low after LCLK2↓
Delay time, WE high after LCLK1↓
Delay time, TR/QE low after LCLK2↓
Delay time, TR/QE high after LCLK1↓
Delay time, SF valid after LCLK1↑
Delay time, SF valid after LCLK2↓
t
+12+ s
t
+10+ s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CK1↓-REL)
d(CK1↓-REH)
d(CK1↑-CEL)
d(CK1↓-CEH)
d(CK2↓-WEL)
d(CK1↓-WEH)
d(CK2↓-TRL)
d(CK1↓-TRH)
d(CK1↑-SFV)
d(CK2↓-SFV)
Q
Q
t
Q
t
Q
t
Q
+12
+12
+12
t
Q
t
Q
t
Q
+10
+10
+10
t
t
+15+ s
t
t
+13.5+ s
Q
Q
t
Q
+15
t
Q
+ 15
+15+ s
+13.5+ s
Q
Q
t
t
+15
+22
t
+13.5
Q
Q
t
+20
Q
Q
t
Q
+22+ s
t
Q
+20+ s
Delay time, SF high-impedance after
LCLK2↓
†
†
86
87
88
89
90
t
t
t
t
t
t
Q
+22
t +20
Q
ns
ns
ns
ns
ns
d(CK2↓-SFZ)
Setup time, row address valid before
RAS↓
‡
2t – 22
2t – 20
su(ADV-RE↓)
Q
Q
Holdtime, rowaddressvalidafterRAS
low
‡
t
– 5+ s
t – 5+ s
Q
h(ADV-REL)
Q
Setup time, column address valid
before CAS↓
t
– 22
– 15
t
Q
– 20
su(RCV-CE↓)
Q
Hold time, column address valid after
CAS high
t
Q
t
Q
– 13.5
h(RCV-CEH)
Setup time, write data valid before
CAS↓
91
92
t
t
t
t
– 22
– 15
t
– 20
ns
ns
su(CAV-CE↓)
Q
Q
Hold time, write data valid after CAS↑
t
– 13.5
h(CAV-CE↑)
Q
Q
Access time, data in valid after RAS
low (assuming maximum transition
time)
93
t
4t – 8+ s
Q
4t – 8+ s
Q
ns
a(LAV-REL)
94
95
t
t
Access time, data in valid after CAS↓
2t – 8
2t –8
ns
ns
a(LAV-CEL)
Q
Q
Access time, data in valid after column
address valid
3t – 17
Q
3t – 2
Q
a(LAV-RCV)
Access time, data in valid after
address valid on LAD bus
96
97
t
t
6t – 17 + s
Q
6t – 17 + s
Q
ns
ns
a(LAV-LAV)
Setup time, write low before CAS↓
(on write cycles)
t
Q
–15
t –13.5
Q
su(WEL-CE↓)
98
t
t
Pulse duration of RAS high
Pulse duration of RAS low
4t – 12+ s
4t – 10+ s
ns
ns
w(REH)
Q
Q
§¶
§¶
4nt – 4+ s′
Q
99a
4nt – 12+ s′
w(REL)
Q
†
‡
§
¶
These values are derived from characterization data and are not tested.
Parameters 87 and 88 also apply to WE, TR/QE, and SF relative to RAS.
s′ is 2t since both the address cycle and the read data cycle of a read-modify-write will be stretched. See clock stretch, page 21.
Q
n = number of GSP data cycles in in the memory access.
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
local bus timing: RAS, CAS0–CAS3, WE, TR/QE, and SF
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
4nt –12+ s
MAX
MIN
4nt –4+ s
MAX
†
†
99b
100
101
102
t
t
t
t
Pulse duration of RAS low
Pulse duration of CAS high
Pulse duration of CAS low
Delay time RAS low to CAS↑
ns
ns
ns
ns
w(REL)
Q
Q
2t –12
Q
2t –10
Q
w(CEH)
2t –8
Q
2t –8
Q
w(CEL)
4t –12+ s
Q
4t –4+ s
Q
d(REL-CE↑)
Hold time, RAS valid low after column address
valid
e
t
3t – 22
Q
3t – 12
Q
ns
h(REL-RCV)
Hold time, CAS valid low after column address
valid
f
t
t
3t – 22
3t – 12
ns
ns
h(CEL-RCV)
Q
Q
h
Hold time, LAD data valid after WE valid high
t
Q
– 15
t
Q
– 12
h(LAV1-WEH)
†
n = number of GSP data cycles in in the memory access.
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
RAS
76
77
98
e
99b
87
88
93
Row
1st Column
2nd Column
RCA
95
90
62
89
LAD (READ)
Address/Status
96
Address/Status
Data In 1
Data In 2
f
62
LAD (WRITE)
1st Data Out
2nd Data Out
92
79
94
79
78
91
100
102a
101
81
CAS0–CAS3
WE
80
h
h
81
83
97
83
82
85
TR/QE
SF
84
86
ALTCH
*See clock stretch, page 21.
Figure 42. Local Bus Timing: RAS, CAS0–CAS3, WE, TR/QE, and SF
70
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
CAS-before-RAS refresh: RAS and CAS0–CAS3
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
76
77
t
t
t
t
t
t
t
t
Delay time, RAS low after LCLK1↓
Delay time, RAS high after LCLK1↓
Delay time, CAS low after LCLK1↑
Delay time, CAS high after LCLK1↓
Delay time, RAS low to CAS↑
Delay time, RAS low to CAS↑
Delay time, CAS low to RAS↓
Delay time, RAS high to CAS↓
t
Q
t
Q
t
Q
t
Q
+12
+12
+12
+12
t
Q
t
Q
t
Q
t
Q
+10
+10
+10
+10
ns
ns
ns
ns
ns
ns
ns
ns
d(CK1↓-REL)
d(CK1↓-REH)
d(CK1↑-CEL)
d(CK1↓-CEH)
d(REL-CE↑)
d(REL-CE↑)
d(CEL-RE↓)
d(REH-CE↓)
78
79
102a
102b
103
104
4t –12+ s
4t – 4+ s
Q
Q
4t –12
Q
4t – 4
Q
2t –15
Q
2t – 13.5
Q
2t –15+ s
Q
2t –13.5+ s
Q
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
LCLK1
LCLK2
RAS
76
77
79
78
103
104
102b
CAS
ALTCH
Refresh Pseudo-Address
Refresh Pseudo-Address
LAD
RCA
DDOUT
*See clock stretch, page 21.
NOTE A: ALTCH, LAD, RCA, and DDOUT are shown for reference only.
Figure 43. CAS-Before-RAS Refresh: RAS and CAS0–CAS3
The refresh pseudo-address present on LAD0–LAD31 is the output from the 16-bit refresh address register (I/O
register located at C000 01F0h) on LAD16–LAD31. LAD0–LAD3 have the refresh status code
(status code = 0011), and LAD4–LAD15 are held low.
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
multiprocessor interface timing: GI, ALTCH, RAS, R0 and R1 (see Figure 44)
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
MAX
2t –40
MIN
MAX
2t –30
Access time, GI valid after R0 and R1 valid
(see Notes 5 and 6)
105
j
t
t
ns
ns
a(GIV-RQV)
Q
Q
Setup time, GI valid before LCLK1 no longer low
(see Note 6)
40
0
35
0
su(GIV-CK1↑)
106
107
108
t
t
t
Hold time, GI valid after LCLK1↑ (see Note 5)
Delay time, LCLK2↑ to R0 or R1 valid
ns
ns
ns
h(CK1↑-GIV)
d(CK2↑-RQV)
d(CK2H-RQNV)
t
Q
+15
t +13.5
Q
Delay time, LCLK2 high to R0 or R1 no longer valid
t
Q
–15
t
Q
–13.5
NOTES: 5. These timings must be met to insure that the GI input is recognized on this clock cycle.
6. It is required that either specification j or specification 105 be observed for the multiprocessor interface to function correctly. It is not
necessary for both to be met.
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
LCLK1
LCLK2
R0–R1
GI
j
107
108
Valid
106
105
Valid
*See clock stretch, page 21.
Figure 44. Multiprocessor Interface Timing: GI, ALTCH, RAS, R0 and R1
72
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
multiprocessor interface timing: high-impedance signals
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
+22
84
86
t
t
Delay time, SF valid after LCLK1↑
t
Q
t +20
Q
ns
ns
d(CK1↑-SFV)
†
†
Delay time, SF high-impedance after LCLK2↓
t
t
+ 22+ s
t + 20 + s
Q
d(CK2↓-SFZ)
Q
Delay time, LAD and RCA high-impedance after
LCLK2↓
†
†
109
110
111
t
t
t
+ 22+ s
t
Q
+20 + s
ns
ns
ns
d(CK2↓-ADZ)
d(CK1↑-ADV)
d(CK1↑-CTZ)
Q
Delay time, LAD and RCA valid after LCLK1↑
t
Q
+22
t +20
Q
Delay time, ALTCH, RAS, CAS, WE, TR/QE, HOE,
and HDST high-impedance after LCLK1↑
†
+15
†
+13.5
Q
t
Q
t
Delay time, ALTCH, RAS, CAS, WE, TR/QE, HOE,
and HDST high-impedance after LCLK2↓
112
t
t
t
+15+ s
t +13.5+ s
Q
ns
d(CK2↓-CTH)
Q
†
+15
†
113
114
115
116
t
t
t
t
Delay time, DDIN high-impedance after LCLK↑
Delay time, DDIN low after LCLK2↓
t
Q
t
Q
+13.5
ns
ns
ns
ns
d(CK1↑-DIZ)
d(CK2↓-DIL)
d(CK2↓-DOZ)
d(CK2↓-DOH)
+15+ s
t
Q
+13.5+ s
Q
†
†
t +13.5 + s
Q
Delay time, DDOUT high-impedance after LCLK2↓
Delay time, DDOUT high after LCLK2↓
t
+15+s
Q
t
Q
+ 15+ s
t +13.5+ s
Q
†
These values are derived from characterization data and are not tested.
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
LCLK1
LCLK2
GI
R0–R1
109
110
LAD0–LAD31,
RCA0 – RCA12
HI–Z
HI–Z
HI–Z
HI–Z
HI–Z
112
111
ALTCH, RAS,
CAS, WE,
TR/QE, HOE, HDST
84
86
SF
114
116
113
DDIN
115
DDOUT
*See clock stretch, page 21.
Figure 45. Multiprocessor Interface Timing: High-Impedance Signals
74
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
video shift clock timing: SCLK
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
35
MAX
50
MIN
25
MAX
50
117
118
119
120
t
t
t
t
Period of video serial clock SCLK
Pulse duration of SCLK high
ns
ns
ns
ns
c(SCK)
12
10
w(SCKH)
w(SCKL)
t(SCK)
Pulse duration of SCLK low
12
10
†
2
†
5
†
2
†
5
Transition time (rise and fall) of SCLK
†
This value is determined through computer simulation and is not tested.
117
120
118
120
119
SCLK
Figure 46. Video Shift Clock Timing: SCLK
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
video interface timing: VCLK and video outputs
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
62.5
28
MAX
100
MIN
62.5
28
MAX
100
123
124
125
126
t
t
t
t
Period of video input clock VCLK
Pulse duration of VCLK high
ns
ns
ns
ns
c(VCK)
w(VCKH)
w(VCKL)
t(VCK)
Pulse duration of VCLK low
28
28
†
2
†
5
†
2
†
5
Transition time (rise and fall) of VCLK
Delay time, VCLK low to HSYNC, VSYNC, CSYNC/VBLNK or
CBLNK/VBLNK low
127
128
129
130
t
t
t
t
40
40
40
40
ns
ns
ns
ns
d(VCKL-HSL)
d(VCKL-HSH)
h(VCK↓-HS↓)
h(VCK↓-HS↑)
Delay time, VCLK low to HSYNC, VSYNC, CSYNC/HBLNK, or
CBLNK/VBLNK high
Hold time, VCLK↓ to HSYNC, VSYNC, CSYNC/HBLNK, or
CBLNK/VBLNK↓
†
†
†
†
0
0
Hold time, VCLK↓ to HSYNC, VSYNC, CSYNC/HBLNK, or
CBLNK/VBLNK↑
0
0
†
This value is determined through computer simulation and is not tested.
123
124
126
125
126
VCLK
127
128
HSYNC
129
VSYNC
CSYNC/HBLNK
CBLNK/VBLNK
(OUTPUTS)
130
Figure 47. Video Interface Timing: VCLK and Video Outputs
76
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
video interface timing: external sync inputs (see Note 7)
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
20
MAX
MIN
20
MAX
131
132
133
t
t
t
Setup time, HSYNC, VSYNC, CSYNC low to VCLK↑
Setup time, HSYNC, VSYNC, CSYNC high to VCLK↑
Hold time, HSYNC, VSYNC, CSYNC valid after VCLK high
ns
ns
ns
su(SL-VCK↑)
su(SH-VCK↑)
h(VCKH-SV)
20
20
20
20
NOTE 7: Setup and hold times on asynchronous inputs are required only to assure recognition at indicated clock edges.
A
B
C
D
VCLK
133
131
133
HSYNC
VSYNC
132
CSYNC
(INPUTS)
(see Note A)
NOTES: A. Ifthefallingedgeofthesyncsignaloccursmorethant
(see Note B)
afterVCLKedgeAandatleastt
beforeedgeB,the
beforeedgeD,the
h(VCKH-SV)
su(SL-VCKH↑)
su(SH-VCKH↑)
transition will be detected at edge B instead of edge A.
B. Iftherisingedgeofthesyncsignaloccursmorethant
afterVCLKedgeCandatleastt
h(VCKH-SV)
transition will be detected at edge D instead of edge C.
Figure 48. Video Interface Timing: External Sync Inputs
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
interrupt timing: LINT1 and LINT2
’34020-32
’34020A-32
’34020A-40
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
†
†
134
135
t
t
Setup time, LINT1 or LINT2 low before LCLK2↑
t
Q
+45
t +40
Q
ns
ns
su(LINTL-CK2↑)
‡
‡
Pulse duration of LINT1 or LINT2 low
8t
Q
8t
Q
w(LINTL)
†
‡
Although LINT1 and LINT2 can be asynchronous to the TMS34020, this setup insures recognition of the interrupt on this clock edge.
This pulse duration minimum insures that the interrupt is recognized by internal logic; however, the level must be maintained until it has been
acknowledged by the interrupt service routine.
LCLK1
LCLK2
134
LINT1
LINT2
135
Figure 49. Interrupt Timing: LINT1 and LINT2
host interrupt timing: HINT
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
25
136
t
Delay time, LCLK1↑ to HINT valid
ns
d(CK1↑-HINTV)
LCLK1
136
LCLK2
HINT
136
Figure 50. Host Interrupt Timing: HINT
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
emulator interface timing
’34020-32
’34020A-32
’34020A-40
NO.
PARAMETER
UNIT
MIN
30
0
MAX
MIN
25
0
MAX
137
138
139
140
t
t
t
t
Setup time, EMU0–EMU2 valid to LCLK1↑
Hold time, EMU0–EMU2 valid after LCLK1↑
Delay time, EMU3 valid after LCLK1 low
Hold time, LCLK2 high before EMU3 not valid
ns
ns
ns
ns
su(EMV-CK1↑)
h(EMV-CK1↑)
d(CK1L-SCV)
h(CK2H-SCNV)
25
20
t
Q
–15
t
Q
–13.5
LCLK1
LCLK2
137
138
137
138
EMU0–EMU2
EMU3
139
139
140
Figure 51. Emulator Interface Timing
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
MECHANICAL DATA
GB/S-CPGA-P145
CERAMIC PIN GRID ARRAY PACKAGE, CAVITY UP
1.590 (40,38)
SQ
1.400 (35,56) TYP
1.560 (39,62)
R
P
N
M
L
K
J
H
G
F
Extra Pin
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0.080 (2,03)
SQ
0.060 (1,53)
0.090 (2,28)
0.070 (1,79)
0.016 (0,41) TYP
0.055 (1,39)
0.045 (1,15)
3 Places
0.140 (3,55)
0.120 (3,05)
DIA TYP
DIA TYP
0.100 (2,54) TYP
0.020 (0,51)
0.016 (0,41)
4040114-11/A–10/93
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Index mark may appear on top or bottom depending on package vendor.
D. Pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within
0.051 (0,38) radius relative to the center of the ceramic.
E. This is a hermetically sealed ceramic package with metal and gold-plated pins.
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
MECHANICAL DATA
PCM/S-PQFP-G***
PLASTIC QUAD FLATPACK
144-PIN SHOWN
0,65 TYP
73
0,38
0,22
108
72
109
NO. OF PINS***
A
22,75 TYP
25,35 TYP
144
160
144
37
0,16 TYP
3,67
3,17
1
36
A
28,10
27,90
SQ
SQ
0,25 MIN
31,45
30,95
0°–7°
0,95
0,65
Seating Plane
0,10
4,07 MAX
4040024/A–10/93
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-108.
D. The 144PCM is identical to 160PCM except for 4 leads per corner are removed.
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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