TMS3705DDRQ1 [TI]

LF 阅读器 IC | D | 16 | -40 to 85;


型号：	TMS3705DDRQ1
厂家：	TEXAS INSTRUMENTS
描述：	LF 阅读器 IC \| D \| 16 \| -40 to 85 电信光电二极管电信集成电路
文件：	总23页 (文件大小：493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS3705

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11-07-22-003 – SCBS881B –JANUARY 2010–REVISED APRIL 2010

TRANSPONDER BASE STATION IC

Check for Samples: TMS3705

FEATURES

•

Base Station IC for TI-RFid™ RF Identification

Systems

•

Short-Circuit Protection

Diagnosis

•

Drives Antenna

Sleep-Mode Supply Current: 0.2 mA

Designed for Automotive Requirements

16-Pin SOIC (D) Package

Sends Modulated Data to Antenna

Detects and Demodulates Transponder

Response (FSK)

DESCRIPTION

The transponder base station IC is used to drive the antenna of a TI-RFid™ transponder system, to send data

modulated on the antenna signal, and to detect and demodulate the response of the transponder. The response

of the transponder is a FSK signal (frequency shift keyed). The high or low bits are coded in two different

high-frequency signals (134.2 kHz for low bits and 123 kHz for high bits, nominal). The transponder induces

these signals in the antenna coil according an internally stored code. The energy the transponder needs to send

out the data is stored in a charge capacitor in the transponder. The antenna field charges this capacitor in a

preceding charge phase. The IC has an interface to an external microcontroller.

There are two configurations for the clock supply to both the microcontroller and the base station IC:

1. Microcontroller and base station IC are supplied with a clock signal derived from only one resonator: The

resonator is attached to the microcontroller. The base station IC is supplied with a clock signal driven by the

digital clock output of the microcontroller. The clock frequency is either 4 MHz or 2 MHz depending on the

selected microcontroller type.

2. Both the microcontroller and the base station have their own resonator.

The base station IC has a PLL on-chip that generates a clock frequency of 16 MHz for internal clock supply only.

The TMS3705BDRG4 is optimized for higher communication data rates and therefore works without frequency

measurement during the write phase.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

TMS3705AG4

TMS3705BG4

TMS3705A1DRG4

–40°C to 85°C

SOIC – D

Reel of 2500

TMS3705BDRG4

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS3705

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D PACKAGE

(TOP VIEW)

SENSE

SFB

TXCT

F_SEL

SCIO

D_TST

A_TST

ANT1

VSSA

ANT2

VDDA

VSS/VSSB

OSC1

OSC2

VDD

NC – No connection

TERMINAL FUNCTIONS

TERMINAL

NO. NAME

TYPE

DESCRIPTION

SENSE

SFB

Analog input

Input of the RF amplifier

Analog output Output of the RF amplifier

Digital output Test output for digital signals

Analog output Test output for analog signals

D_TST

A_TST

ANT1

VSSA

ANT2

VDDA

VDD

Driver output

Supply input

Driver output

Supply input

Antenna output 1

Ground for the full bridge drivers

Antenna output 2

Voltage supply for the full bridge drivers

Voltage supply for non-power blocks

OSC2

OSC1

VSS/VSSB

Analog output Oscillator output

Analog input

Supply input

Oscillator input

Ground for non-power blocks and PLL

Not connected

SCIO

Digital output Data output to the microcontroller

F_SEL

TXCT

Digital input

Control input for frequency selection (default value is high)

Control input from the microcontroller (default value is high)

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FUNCTIONAL BLOCK DIAGRAM

VDD

SCI

Encoder

Digital Demodulator

Limiter

Diagnosis

Transponder

Resonance-Frequency

Measurement

A_TST

SCIO

Bandpass

10k

Power-On

Reset

SFB

RF Amplifier

Control Logic

With

Mode Control Register

TXCT

Vref

SENSE

D_TST

Full Bridge

F_SEL

OSC2

PLL

VDDA

ANT1

Predrivers

Controlled

Frequency Divider

ANT2

VSSA

OSC1

VSS

VSSB

Power Supply

The device is supplied with 5 V by an external voltage regulator via two supply pins, one for providing the driver

current for the antenna and for supplying the analog part in front of the digital demodulator and one for supplying

the other blocks.

The power supply supplies a power-on reset that brings the control logic into idle mode as soon as the supply

voltage drops under a certain value.

In sleep mode the sum of both supply currents is reduced to 0.2 mA. The base station device falls into sleep

mode 100 ms after TXCT has changed to high. When TXCT changes to low or is low, the base station IC

immediately goes into and remains in normal operation.

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Oscillator

The oscillator generates the clock of the base station IC of which all timing signals are derived. Between its input

and output a crystal or ceramic resonator is connected that oscillates at a typical frequency of 4 MHz. If a digital

clock signal with a frequency of 4 MHz or 2 MHz is supplied to pin OSC1, the signal can be used to generate the

internal operation frequency of 16 MHz.

The oscillator block contains a PLL that generates the internal clock frequency of 16 MHz from the input clock

signal. The PLL multiplies the input clock frequency depending on the logic state of the input pin F_SEL by a

factor of 4 (F_SEL is high) or by a factor of 8 (F_SEL is low).

In sleep mode the oscillator is switched off.

Predrivers

The predrivers generate the signals for the four power transistors of the full bridge using the carrier frequency

generated by the frequency divider. The gate signals of the p-channel power transistors (active low) have the

same width (±1 cycle of the 16 MHz clock), the delay between one p-channel MOSFET being switched off and

the other one being switched on is defined to be 12 cycles of the 16 MHz clock. In write mode the first activation

of a gate signal after a bit pause is synchronized to the received transponder signal by a phase shift of 18°.

Full Bridge

The full bridge drives the antenna current at the carrier frequency during the charge phase and the active time of

the write phase. The minimal load resistance the full bridge sees between its outputs in normal operation at the

resonance frequency of the antenna is 43.3 Ω. When the full bridge is not active, the two driver outputs are

switched to ground.

Both outputs of the full bridge are protected independently against short-circuits to ground.

In case of an occurring short-circuit, the full bridge is switched off in less than 10 µs in order to avoid a drop of

the supply voltage. After a delay time of less than 10 ms the full bridge is switched on again to test if the

short-circuit is still there. An overcurrent due to a resistive short to ground that is higher than the maximum

current in normal operation but lower than the current threshold for overcurrent protection does not need to be

considered.

RF Amplifier

The RF amplifier is an operational amplifier with a fixed internal voltage reference and a voltage gain of 5 defined

by external resistors. It has a high gain-bandwidth product of at least 2 MHz in order to show a phase shift of less

than 16° for the desired signal and to give the possibility to use it as a low-pass filter by adapting additional

external components.

The input signal of the RF amplifier is DC coupled to the antenna. The amplitude of the output signal of the RF

amplifier is higher than 5 mV peak-to-peak.

Band-Pass Filter and Limiter

The band-pass filter provides amplification and filtering without external components. The lower cut-off frequency

is about a factor of 2 lower than the average signal frequency of 130 kHz, the higher cut-off frequency is about a

factor of 2 higher than 130 kHz.

The limiter converts the analog sine-wave signal to a digital signal. It provides a hysteresis depending on the

minimal amplitude of its input signal. The duty cycle of its digital output signal is between 40% and 60%. The

band-pass filter and the limiter together have a high gain of at least 1000.

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Diagnosis

The diagnosis is carried out during the charge phase to detect whether the full bridge and the antenna are

working. When the full bridge drives the antenna, the voltage across the coil exceeds the supply voltage so that

the voltage at the input of the RF amplifier is clamped by the ESD-protection diodes. For diagnosis, the SENSE

pin is loaded on-chip with a switchable resistor to ground so that the internal switchable resistor and the external

SENSE resistor form a voltage divider, while the internal resistor is switched off in read mode. When the voltage

drop across the internal resistor exceeds a certain value, the diagnosis block passes the frequency of its input

signal to the digital demodulator. The frequency of the diagnosis signal is accepted, if eight subsequent time can

be detected, all with their counter state within the range of 112 to 125, during the diagnosis time (at most 0.1

ms). The output signal is used during the charge phase only else it is ignored.

When the short-circuit protection switches off one of the full-bridge drivers, the diagnosis also indicates an

improper operation of the antenna by sending the same diagnostic byte to the microcontroller as for the other

failure mode.

During diagnosis, the antenna drivers are active. In synchronous mode the antenna drivers remain active up to 1

ms after the diagnosis is performed, without any respect to the logic state of the signal at TXCT (thus enabling

the microcontroller to clock out the diagnosis byte).

Power-On Reset

The power-on reset generates an internal reset signal to allow the control logic to start up in the defined way.

Frequency Divider

The frequency divider is a programmable divider that generates the carrier frequency for the full-bridge antenna

drivers. The default value for the division factor is the value 119 needed to provide the nominal carrier frequency

of 134.45 kHz generated from 16 MHz. The resolution for programming the division factor is one divider step that

corresponds to a frequency shift of about 1.1 kHz. The different division factors needed to cover the range of

frequencies for meeting the resonance frequency of the transponder are 114 to 124.

Digital Demodulator

The input signal of the digital demodulator comes from the limiter and is frequency-coded according to the high-

and low-bit sequence of the transmitted transponder code. The frequency of the input signal is measured by

counting the oscillation clock for the time period of the input signal. As the high-bit and low-bit frequencies are

specified with wide tolerances, the demodulator is designed to distinguish the high-bit and the low-bit frequency

by the shift between the two frequencies and not by the absolute values. The threshold between the high-bit and

the low-bit frequency is defined to be 6.5 kHz lower than the measured low-bit frequency and has a hysteresis of

±0.55 kHz.

The demodulator is controlled by the control logic. After the charge phase (that is during read or write phase) it

measures the time period of its input signal and waits for the transponder resonance-frequency measurement to

determine the counter state for the threshold between high-bit and low-bit frequency. Then the demodulator waits

for the occurrence of the start bit. For that purpose, the results of the comparisons between the measured time

periods and the threshold are shifted in a 12-bit shift register. The detection of the start bit comes into effect

when the contents of the shift register matches a specific pattern, indicating 8 subsequent periods below the

threshold immediately followed by 4 subsequent periods above the threshold. A 2-period digital filter is inserted in

front of the 12-bit shift register to make a start bit detection possible in case of a non-monotonous progression of

the time periods during a transition from low- to high-bit frequency.

The bit stream detected by the input stage of the digital demodulator passes a digital filter before being

evaluated. After demodulation, the serial bit flow received from the transponder is buffered byte-wise before

being sent to the microcontroller by SCI encoding.

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Transponder Resonance-Frequency Measurement

During the pre-bit reception phase, the bits the transponder transmits show the low-bit frequency, which is the

resonance frequency of the transponder. The time periods of the pre-bits are evaluated by the demodulator

counter. Based on the counter states, an algorithm is implemented that guarantees a correct measurement of the

transponder’s resonance frequency:

1. A time period of the low-bit frequency has a counter state between 112 and 125.

2. The measurement of the low-bit frequency (the average of eight subsequent counter states) is accepted

during the write mode, when the eight time periods have counter states in the defined range. The

measurement during write mode is started with the falling edge at TXCT using the fixed delay time at which

end the full bridge is switched on again.

3. The counter state of the measured low-bit frequency results in the average counter state of an accepted

measurement and can be used to update the register of the programmable frequency divider.

4. The measurement of the low-bit frequency (the average of eight subsequent counter states) is accepted

during the read mode, when the eight time periods have counter states in the defined range. The start of the

measurement during read mode is delayed in order to use a stable input signal for the measurement.

5. The threshold to distinguish between high-bit and low-bit frequency is calculated to be by a value of 5 or 7

(see hysteresis in threshold) higher than the counter state of the measured low-bit frequency.

SCI Encoder

An SCI encoder performs the data transmission to the microcontroller. As the transmission rate of the

transponder is lower than the SCI transmission rate, the serial bit flow received from the transponder is buffered

after demodulation and before SCI encoding.

The SCI encoder uses an 8-bit shift register to send the received data byte-wise (least significant bit first) to the

microcontroller with a transmission rate of 15.625 kbaud (±1.5 %), one start bit (high) and one stop bit (low), but

no parity bit (asynchronous mode indicated by the SYNC bit of the mode control register permanently low). The

data bits at the SCIO output are inverted with respect to the corresponding bits sent by the transponder.

The transmission starts after the reception of the start bit. The start byte detection is initialized with the first rising

edge. Typical values for the start byte are 81_H or 01_H (at SCIO). The start byte is the first byte to be sent to

the microcontroller. The transmission stops and the base station returns to idle state when TXCT becomes low or

20 ms after the beginning of the read phase. TXCT remains low for at least 128 µs to stop the read phase and

less than 900 µs to avoid starting the next transmission cycle.

The SCI encoder also sends the diagnostic byte 2 ms after beginning of the charge phase. In case of a normal

operation of the antenna, the diagnostic byte AF_H is sent. If no antenna oscillation can be measured or if at

least one of the full-bridge drivers is switched off due to a detected short-circuit, the diagnostic byte FF_H is sent

to indicate the failure mode.

The SCI encoder can be switched into a synchronous data transmission mode by setting the mode control

transmitted. The microcontroller can receive the eight bits at SCIO when sending the eight clock signals (falling

edge means active) for the synchronous data transmission via pin TXCT to the SCI encoder.

Control Logic

The control logic is the core of the TMS3705 circuit. It contains a sequencer or a state machine that controls the

global operations of the base station (see Figure 1). This block has a default mode configuration but can also be

controlled by the microcontroller via the TXCT serial input pin to change the configuration and to control the

programmable frequency divider. For that purpose a mode control register is implemented in this module that can

be written by the microcontroller.

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Power-

SLEEP

Approx. 2 ms after

TXCT goes low⁽⁴⁾

after approx. 2 ms

after approx. 100 ms

IDLE

TXCT is low

TXCT goes high

before 96ms

0.9 ms after TXCT goes low⁽²⁾

or approx. 4 ms after start of Receive

phase if no start bit is detected

or otherwise approx. 20 ms after

start of Receive phase

MCR Programming:

(3)

Write bits into

Mode Control Register

(5)

MCR bits received

RECEIVE Phase:

DIAGNOSIS Phase:

Frequency measurement

Transponder signal

demodulation

Start of Charge Phase

Perform diagnosis

FAIL

Data output to mC after

reception of start byte

Send diag. byte approx.

2 ms after leaving Idle state

(1)

Diag. byte sent

TXCT remains high for 1.6 ms

WRITE Phase⁽⁶⁾:

CHARGE Phase:

TXCT goes high

Start of write phase

Frequency measurement

Program phase

Charge phase continues

Notes :

⁽¹⁾In SCI synchronous mode, this transition always occurs approx. 3 ms after leaving Idle state (diag. byte transmission

should be completed before).

(2)

ms.

A falling edge on TXCT interrupts the Receive phase after a delay of 0.9 ms. TXCT must remain low for at least 128

If TXCT is still low after the 0.9 ms delay, the basestation will go to Idle and directly to the Diagnosis phase one clock

cycle later (Dotted line⁽³⁾).No MCR can be written, noly default mode is fully supported in this case.

Otherwise, if TXCT returns to high and remains high during the delay, the basestation will stay in Idle and wait for TXCT

to go low (this will start properly a new MCR programming) or wait for 100 ms to go to Sleep.

(2)

⁽³⁾This transition only occurs in a special case (see note

)

⁽⁴⁾A falling edge on TXCT interrupts the Sleep state. Only default mode is fully supported when starting an operation

from Sleep with only one falling edge on TXCT (because of the 2 m s delay). For a proper M CR programming, TXCT has

to return to high and remain high during this delay.

(5)

Idle mode is the next state in case of undefined sataes ('fail safe state machine')

(6)

Frequency measurement only available for TMS3705A1DRG4

Figure 1. Operational State Diagram for the Control Logic

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The default mode is a read-only mode that uses the default frequency as the carrier frequency for the full bridge.

Therefore the mode control register does not need to be written (it is filled with low states), and the

communication sequence between microcontroller and base station starts with TXCT being low for a fixed time to

initiate the charge phase. When TXCT becomes high again, the module enters the read phase and the data

transmission via the SCIO pin to the microcontroller starts.

There is another read-only mode that differs from the default mode only in the writing of the mode control register

before the start of the charge phase. The way that the mode control register is filled and the meaning of its

contents is described below.

The write-read mode starts with the programming of the mode control register. Then the charge phase starts with

TXCT being low for a fixed time. When TXCT becomes high again, the write phase begins in which the data are

transmitted from the microcontroller to the transponder via the TXCT pin, the control logic, the predrivers, and the

full bridge by amplitude modulation of 100% with a fixed delay time. After the write phase TXCT goes low again

to start another charge or program phase. When TXCT becomes high again, the read phase begins.

The contents of the mode control register define the mode and the way that the carrier frequency generated by

the frequency divider is selected in order to meet the transponder resonance frequency as good as possible.

Table 1. Mode Control Register (7-Bit Register)

BIT

RESET

VALUE

DESCRIPTION

NAME

NO.

START_BIT

Bit 0

START_BIT = 0

DATA_BIT[4:1] = 0000

DATA_BIT[4:1] = 1111

DATA_BIT[4:1] = 0001

DATA_BIT[4:1] = 0010

...

The start bit is always low and does not need to be stored.

Microcontroller selects division factor 119

Division factor is adapted automatically⁽¹⁾

Microcontroller selects division factor 114

Microcontroller selects division factor 115

...

DATA_BIT1

DATA_BIT2

DATA_BIT3

DATA_BIT4

SCI_SYNC

RX_AFC

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

DATA_BIT[4:1] = 0110

...

Microcontroller selects division factor 119

...

DATA_BIT[4:1] = 1011

SCI_SYNC = 0

SCI_SYNC = 1

RX_AFC = 0

Microcontroller selects division factor 124

Asynchronous data transmission to the microcontroller

Synchronous data transmission to the microcontroller

Demodulator threshold is adapted automatically

Demodulator threshold is defined by DATA_BIT[4:1]

No further test bytes

RX_AFC = 1

TEST_BIT = 0

TEST_BIT

TEST_BIT = 1

Further test byte follows for special test modes

(1) Only available for TMS3705A1DRG4

The TMS3705A1DRG4 can adjust the carrier frequency to the transponder resonance frequency automatically by

giving the counter state of the transponder resonance-frequency measurement directly to the frequency divider

by setting the first four bits in high state. This setting is not available for TMS3705BDRG4. The other

combinations of the first four bits allow the microcontroller to select the default carrier frequency or to use

another frequency. The division factor can be selected to be between 114 and 124.

Some bits for testability reasons can be added. The default value of these test bits for normal operation is low.

Especially the bit 7 called TEST_BIT is Low for normal operation; otherwise the base station may enter one of

the test modes.

The control logic also controls the demodulator, the SCI encoder, the diagnosis, and especially the transmission

of the diagnosis byte during the charge phase.

The state diagram in Figure 1 shows the general behavior of the state machine (note that the state blocks drawn

can contain more than one state). All given times are measured from the moment when the state is entered if not

specified otherwise.

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Test Pins

The IC has an analog test pin A_TST for the analog part of the receiver. The digital output pin D_TST is used for

testing the internal logic. Both pins need not be connected in the application.

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

V_DD

Supply voltage range

VDD, VSS/VSSB, VDDA, VSSA

OSC1, OSC2

–0.3 V to 7 V

V_OSC

V_inout

I_inout

V_ANT

I_ANT

Voltage range

–0.3 V to (V_DD+ 0.3) V

–5 mA to 5 mA

Voltage range

SCIO, TXCT, F_SEL, D_TST

ANT1, ANT2

Overload clamping current

Output voltage

–0.3 V to (V_DD+ 0.3) V

–1.1 A to 1.1 A

Output peak current

ANT1, ANT2

V_analog

I_SENSE

I_SFB

Voltage range

SENSE, SFB, A_TST

SFB

–0.3 V to (V_DD+ 0.3) V

–5 mA to 5 mA

SENSE input current

Input current in case of overvoltage

Operating ambient temperature

Storage temperature range

Thermal resistance, junction to free air

Total power dissipation at T_A= 85°C

ESD protection (MIL STD 883)

–5 mA to 5 mA

T_A

–40°C to 85°C

T_stg

–55°C to 150°C

130°C/W

R_qJA

P_D

0.5 W

V_ESD

–2000 V to 2000 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

V_DD

f_osc

V_IH

Supply voltage

VDD, VSS/VSSB, VDDA, VSSA

OSC1, OSC2

4.5

5.5

MHz

Oscillator frequency

High-level input voltage

F_SEL, TXCT, OSC1

TXCT, OSC1

0.7 V_DD

0.3 V_DD

0.2 V_DD

V_IL

Low-level input voltage

F_SEL

I_OH

I_OL

High-level output current

Low-level output current

SCIO, D_TST

–1

SCIO, D_TST

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ELECTRICAL CHARACTERISTICS

V_DD= 4.5 V to 5.5 V, f_osc= 4 MHz, F_SEL = high, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Power Supply (VDD, VSS/VSSB, VDDA, VSSA)

Sum of supply currents in charge phase,

without antenna load

I_DD

Supply current

Sum of supply currents in sleep mode, without

I/O currents

I_SLEEP

Supply current, sleep mode

0.015

0.2

Oscillator (OSC1, OSC2)

g_osc

C_in

Transconductance

f_osc= 4 MHz, 0.5 V_ppat OSC1

0.5

mA/V

Input capacitance at OSC1⁽¹⁾

Output capacitance at OSC2⁽¹⁾

C_out

Logic Inputs (TXCT, F_SEL, OSC1)

R_pullupPullup resistance

Logic Outputs (SCIO, D_TST)

TXCT

120

500

kΩ

F_SEL

V_OH

V_OL

High-level output voltage

Low-level output voltage

0.8 V_DD

0.2 V_DD

Full-Bridge Outputs (ANT1, ANT2)

Full bridge n-channel and p-channel MOSFETs

at driver current I_ant= 50 mA

ΣR_{ds_on}

Sum of drain-source resistances

Ω

Duty cycle

p-channel MOSFETs of full bridge

Symmetry of pulse widths for the

p-channel MOSFETs of full bridge

t_on1/t_on2

I_oc

104.5

Threshold for overcurrent

protection

220

0.25

1100

µs

Switch-off time of overcurrent

protection

t_oc

Short to ground with 3 Ω

Delay for switching on the full

bridge after an overcurrent

t_doc

2.05

2.1

µA

I_leak

Leakage current

Analog Module (SENSE, SFB, A_TST)

I_SENSE

Input current

SENSE, In charge phase

–2

V_DCREF

V_DD

DC reference voltage of RF

amplifier, related to VDD

9.25

At 500 kHz with external components to

achieve a voltage gain of minimum 4-mV_ppand

5-mV_ppinput signal

Gain-bandwidth product of RF

amplifier

GBW

f_O

MHz

At 134 kHz with external components to

achieve a voltage gain of 5-mV_ppand 20-mV_pp

input signal

Phase shift of RF amplifier

Peak-to-peak input voltage of band

pass at which the limiter

At 134 kHz (corresponds to a minimal total gain

of 1000)

V_sfb

comparator should toggle⁽²⁾

Lower cut-off frequency of

band-pass filter⁽³⁾

f_low

160

270

100 kHz

500 kHz

Higher cut-off frequency of

band-pass filter⁽³⁾

f_high

ΔV_hys

A_TST pin used as input, D_TST pin as output,

Offset level determined by bandpass stage

Hysteresis of limiter

135

(1) Specified by design

(2) Specified by design; functional test done for input voltage of 90 mV_pp

(3) BP filter tested at three different frequencies: f_mid=134 kHz and gain > 30 db; f_low= 24 kHz, f_high= 500 kHz and attenuation < –3 dB

(reference = measured gain at f_mid= 134 kHz).

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ELECTRICAL CHARACTERISTICS (continued)

V_DD= 4.5 V to 5.5 V, f_osc= 4 MHz, F_SEL = high, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Diagnosis (SENSE)

Current threshold for operating

antenna⁽⁴⁾

I_diag

240

µA

Phase-Locked Loop (D_TST)

f_pll

PLL frequency

15.984

16.0166 MHz

Δf/f_pll

Jitter of the PLL frequency

Power-On Reset (POR)

V_{por_r}

V_{por_f}

POR threshold voltage, rising

POR threshold voltage, falling

V_DDrising with low slope

V_DDfalling with low slope

1.9

1.3

3.5

2.6

(4) Internal resistance switched on and much lower than external SENSE resistance.

SWITCHING CHARACTERISTICS

V_DD= 4.5 V to 5.5 V, f_osc= 4 MHz, F_SEL = high, over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

From start of the oscillator after

power-on or waking up until reaching

the idle mode (see Figure 2, Figure 3,

Figure 4)

t_{init min}Time for TXCT high to initialize a new transmission

2.05

2.2

Delay between leaving idle mode and start of

diagnosis byte at SCIO

Normal operation (see Figure 2,

Figure 3, Figure 4)

t_diag

2.12

Delay between end of charge or end of program and

start of transponder data transmit on SCIO

t_R

See Figure 2, Figure 3, Figure 4)

t_off

Write pulse pause

See Figure 6

0.1

µs

t_dwrite

t_mcr

t_sci

Signal delay on TXCT for controlling the full bridge

NRZ bit duration for mode control register

NRZ bit duration on SCIO

Write mode

128

135

See Figure 5

121

Asynchronous mode (see Figure 7)

Synchronous mode

t_dstop

Low signal delay on TXCT to stop

128

800

t_{t_sync}Total TXCT time for reading data on SCIO

t_syncTXCT period for shifting data on SCIO

t_{L_sync}Low phase on TXCT

t_readyData ready for output after SCIO goes high

Synchronous mode (see Figure 8)

Synchronous mode (seeFigure 8)

Synchronous mode (see Figure 8)

900

100

t_sync– 2

127

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11-07-22-003 – SCBS881B –JANUARY 2010–REVISED APRIL 2010

TIMING DIAGRAMS

TxCT

SCIO

Diag

byte

Start

byte

data bytes

t_init

t_ch

t_R

t_diag

M.C.W. CHARGE

PHASE

RESPONSE

Init. transmission

Figure 2. Default Mode (Read Only, No Writing Into Mode Control Register)

TxCT

SCIO

Diag

byte

Start

byte

data bytes

t_init

t_ch

t_R

t_diag

M.C.W. CHARGE

PHASE

RESPONSE

Init. transmission

Figure 3. Read-Only Mode (Writing Into Mode Control Register)

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TIMING DIAGRAMS (continued)

TxCT

SCIO

Diag

byte

Start

byte

data bytes

t_init

t_ch

t_prog

t_R

t_diag

M.C.W. CHARGE

PHASE

WRITE

PROG.

RESPONSE

Init. transmission

NOTE: M.C.W.: Mode control write (to write into the mode control register)

PROG.: Program phase of transponder

Figure 4. Write/Read Mode (Writing Into Mode Control Register)

TxCT

t_init

t_mcrt_mcr

PHASE

CHARGE

Low Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start Bit

Test Bit

Init. transmission

End transmission

Figure 5. Mode Control Write Protocol (NRZ Coding)

TXCT

PHASE

Figure 6. Transponder Write Protocol

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11-07-22-003 – SCBS881B –JANUARY 2010–REVISED APRIL 2010

TIMING DIAGRAMS (continued)

LSB

MSB

SCIO

Start

bit

Stop

bit

t_sci

Figure 7. Transmission on SCIO in Asynchronous Mode (NRZ Coding)

LSB

MSB

SCIO

TxCT

Stop

“bit”

Byte

ready

t_readyt_sync

t_sync

t_{t_sync}

t_{L_sync}

reads data

shift data

Figure 8. Transmission on SCIO in Synchronous Mode (NRZ Coding)

(For Diagnosis Byte and Data Bytes)

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APPLICATION INFORMATION

Application Diagram

TXCT Input

SENSE

SFB

TXCT

F_SEL

SCIO

SCIO Output

D_TST

A_TST

ANT1

VSSA

ANT2

VDDA

TMS3705

VSS

Antenna

OSC1

OSC2

VDD

4 MHz

5 V

Ground

Figure 9. Application Diagram

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11-07-22-003 – SCBS881B –JANUARY 2010–REVISED APRIL 2010

REVISION HISTORY

Revision

SCBS881

SCBS881A

Comments

Initial release

Add parameter values for "Full-Bridge Outputs (ANT1, ANT2)" section in Electrical Characteristics (page 10)

Add TMS3705BDRG4 orderable part number (page 1)

Add information specific to TMS3705B (page 7 and 8)

SCBS881B

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Dec-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TMS3705A1DRG4

TMS3705BDRG4

ACTIVE

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Call Local Sales Office

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Purchase Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Oct-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMS3705A1DRG4

SOIC

2500

330.0

16.4

6.5

10.3

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Oct-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC 16

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

TMS3705A1DRG4

2500

Pack Materials-Page 2

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TMS3705DDRQ1 [TI]

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