TMS416100P-70DJ [TI]
16MX1 FAST PAGE DRAM, 70ns, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24;
| 型号： | TMS416100P-70DJ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16MX1 FAST PAGE DRAM, 70ns, PDSO24, 0.300 INCH, PLASTIC, SOJ-26/24 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总25页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
DJ PACKAGE
(TOP VIEW)
DGA PACKAGE
(TOP VIEW)
This data sheet is applicable to all
TMS416100/Ps symbolized with Revision “B”
and subsequent revisions as described on
page 24.
1
2
3
4
5
6
26
25
24
23
22
21
1
2
3
4
5
6
26
25
24
23
22
21
V
V
SS
Q
V
V
SS
Q
CC
D
CC
D
• Organization . . . 16 777 216 × 1
• Single 5-V Power Supply (±10% Tolerance)
NC
W
NC
CAS
NC
A9
NC
W
NC
CAS
NC
A9
RAS
A11
RAS
A11
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
t
t
t
CYCLE
(MIN)
RAC
CAC
AA
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
8
19
18
17
16
15
14
A10
A0
A1
A2
A3
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
(MAX)
60 ns
70 ns
80 ns
(MAX)
15 ns
18 ns
20 ns
(MAX)
30 ns
35 ns
40 ns
9
9
’416100-60
’416100-70
’416100-80
110 ns
10
11
12
13
10
11
12
13
130 ns
150 ns
• Enhanced Page Mode Operation for Faster
V
V
V
V
CC
SS
Memory Access
CC
SS
• CAS-Before-RAS Refresh
• Long Refresh Period
– 4096 Cycle Refresh in 64 ms
(TMS416100)
PIN NOMENCLATURE
A0–A11
CAS
D
Address Inputs
Column-Address Strobe
Data In
– 256 ms for Extended Refresh Version
(TMS416100P)
Q
NC
RAS
Data Out
• 3-State Unlatched Output
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
• Low Power Dissipation (TMS416100P Only)
– 500-µA CMOS Standby Current
– 500-µA Self-Refresh Current
– 500-µA Extended Refresh Battery Backup
Current
V
V
W
CC
SS
• All Inputs, Outputs and Clocks Are TTL
Compatible
• Operating Free-Air Temperature Range:
0°C to 70°C
description
The TMS416100/P series are high-speed, 16777216-bit dynamic random-access memories, organized as
16777216 words of one bit each. The TMS416100P series feature self refresh and extended refresh. They
employ state-of-the-art EPIC (Enhanced Performance Implanted CMOS) technology for high performance,
reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All inputs, outputs, and clocks
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS416100/P are offered in 300-mil 24/26-lead plastic surface-mount SOJ packages (DJ suffix) and
24/26-lead plastic small-outline packages (DGA suffix). All packages are characterized for operation from 0°C
to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
†
logic symbol
RAM 16384K × 1
30D12/21D0
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
10
11
12
15
16
17
18
19
0
A
16383K
21
8
6
A11
31D23/21D11
C30 [ROW]
G33 [REFRESH ROW]
5
RAS
CAS
34 [PWR DWN]
C31 [COL]
G34
&
23
33C32
34 EN
4
2
W
D
33, 31D
A, 32D
27
A
Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DJ and DGA packages.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
functional block diagram
RAS
CAS
W
Timing and Control
10
A0
A1
Column Decode
Sense Amplifiers
256K Array
4
2
Column-
Address
Buffers
Data
In
Reg.
4
256K Array
A11
D
Q
I/O
Buffers
1 of 4
Selection
Data
Out
Reg.
64
Row-
12
Address
Buffers
2
256K Array
12
operation
enhanced page mode
Enhancedpage-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that can be accessed is determined by t
, the maximum RAS-low time.
RASP
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the addresses and enables the output. This feature allows the TMS416100/P to operate at a higher data
bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid
rather than when CAS transitions low. This performance improvement is referred to as enhanced page mode.
Valid column address can be presented immediately after row-address hold time has been satisfied, usually well
in advance of the falling edge of CAS. In this case, data is obtained after t
max (access time from CAS low),
CAC
ift max(accesstimefromcolumnaddress)andt
havebeensatisfied.Intheeventthatthecolumnaddress
AA
RAC
for the next cycle is valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of t
or t
.
CPA
CAC
address (A0–A11)
Twenty-four address bits are required to decode 1 of 16777216 storage cell locations. Twelve row-address bits
are set up on inputs A0 through A11 and latched during a normal access and during RAS-only refresh as the
device requires 4096 refresh cycles. Twelve column-address bits are set up on inputs A0–A11 and latched onto
the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer as well as latching the address bits into the column-address buffer.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting common
I/O operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-writecycle, CAS is already low and the data is strobed in by W with setup and hold times referenced
to this signal.
data out (Q)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series74TTLloads. Theoutputisinthehigh-impedance(floating)stateuntilCASisbroughtlow. Inareadcycle,
the output becomes valid at the latest occurrence of t
CAS going high returns it to the high-impedance state.
, t , t
, or t
and remains valid while CAS is low.
RAC AA CAC
CPA
refresh
Arefreshoperationmustbeperformedatleastonceevery64mstoretaindata. Thiscanbeachievedbystrobing
each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed by holding CAS at V after a read operation and cycling RAS after
IL
a specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden refresh cycle. An internal address provides the refresh address
during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter t
) and
CSR
holding it low after RAS falls (see parameter t
). For successive CAS-before-RAS refresh cycles, CAS
CHR
remains low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
A low-power battery-backup refresh mode that requires less than 500 µA refresh current is available on the
TMS416100P. Data integrity is maintained using CAS-before-RAS refresh with a period of 62.5 µs while holding
RAS low for less than 1 µs. To minimize current consumption, all input levels need to be at CMOS levels
(V ≤ 0.2 V, V ≤ V
– 0.2 V).
IL
IH
CC
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full V level is achieved. These eight initialization cycles need to include at least one refresh
CC
(RAS-only or CAS-before-RAS) cycle.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
self refresh (TMS416100P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RASand CAS
are brought high to satisfy t
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
CHS
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel
read or write on subsequent cycles. While in the test mode, any data sequence can be performed. The device
exitsthetestmodeifaCAS-before-RAS(CBR)refreshcyclewithWheldhighoraRAS-onlyrefresh(ROR)cycle
is performed.
The device is configured as 1024K × 16 bits with a 16-bit parallel read-and-write data path in the test mode.
Column addresses A0, A1, A10, and A11 are not used. During a read cycle, all 16 bits of the internal data bus
are compared. If all bits are in the same data state, the output pin goes high. If one or more bits disagree, the
output pin goes low. Test time is reduced by a factor of 16, compared to normal memory mode.
Entry
Cycle
Test-Mode Cycle
Exit
Cycle
Normal
Mode
RAS
CAS
W
NOTE: The states of W, data input, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
†
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
T
Supply voltage
4.5
2.4
–1
0
5
5.5
6.5
0.8
70
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’416100-60
’416100-70
’416100-80
’416100P-60
’416100P-70
’416100P-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN MAX
MIN MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
0.4
2.4
0.4
V
V
OH
OH
= 4.2 mA
0.4
± 10
± 10
OL
OL
V = 0 V to 6.5 V
I
All other pins = 0 V to V
†
I
I
Input current (leakage)
± 10
± 10
± 10
± 10
µA
µA
I
CC
†
Output current (leakage)
V
= 0 V to V , CAS high
CC
O
O
Read- or write-cycle
current
(see Notes 3 and 5)
I
I
I
V
= 5.5 V,
Minimum cycle
80
2
70
2
60
2
mA
mA
CC1
CC
After 1 memory cycle,
RAS and CAS high,
V
IH
= 2.4 V (TTL)
Standby current
CC2
CC3
After 1 memory cycle,
RAS and CAS high,
’416100
1
1
1
mA
’416100P
500
500
500
µA
V
IH
= V
– 0.2 V (CMOS)
CC
Average refresh current
(RAS-only or CBR)
RAS cycling, CAS high (RAS-only);
RAS low after CAS low (CBR)
80
70
60
mA
†
(see Notes 3 and 5)
Average page current
(see Notes 4 and 5)
I
I
RAS low,
CAS cycling
70
60
50
mA
CC4
†
Self-refresh current
(’416100P only)
CAS and RAS < 0.2 V,
Measured after t
500
500
500
µA
CC6
min
RASS
CAS = V ,
IL
Standby current,
output enable
RAS = V
IH
Data out = enabled
,
I
5
5
5
mA
CC7
†
(see Note 5)
t
V
= 62.5 µs,
t
≤ 1 µs,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
Extended-refresh battery
backup (’416100P only)
CC
IH
I
500
500
500
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
Minimum cycle, V
= 5.5 V
NOTES: 3. Measured with a maximum of one address change while RAS = V
CC
IL
4. Measured with a maximum of one address change while CAS = V
5. Measured with no load connected
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
C
Input capacitance, address inputs
Input capacitance, data inputs
Input capacitance, strobe inputs
Input capacitance, write-enable input
Output capacitance
5
5
7
7
7
i(A)
i(D)
i(RC)
i(W)
o
pF
pF
pF
pF
NOTE 6:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’416100-60
’416100-70
’416100-80
’416100P-60
’416100P-70
’416100P-80
PARAMETER
UNIT
MIN
MAX MIN
MAX MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
30
15
35
60
35
18
40
70
ns
ns
ns
ns
ns
ns
ns
AA
20
CAC
CPA
RAC
CLZ
OH
Access time from column precharge
Access time from RAS low
45
80
CAS to output in low-impedance state
Output disable time, start of CAS high
Output disable time after CAS high (see Note 7)
0
3
0
0
3
0
0
3
0
15
18
20
OFF
NOTE 7:
t
is specified when the output is no longer driven.
OFF
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’416100-60
’416100-70
’416100-80
’416100P-60
’416100P-70
’416100P-80
UNIT
MIN
110
130
40
MAX
MIN
130
153
45
MAX
MIN
150
175
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 8)
Cycle time, read-write (see Note 8)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
RWC
PC
Cycle time, page-mode read or write (see Notes 8 and 9)
Cycle time, page-mode read-write (see Note 8)
Pulse duration, page-mode, RAS low (see Note 10)
Pulse duration, nonpage-mode, RAS low (see Note 10)
Pulse duration, CAS low (see Note 11)
Pulse duration, CAS high
60
68
75
PRWC
RASP
RAS
CAS
CP
60 100 000
70 100 000
80 100 000
60 10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
15 10 000
10
40
10
0
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 12)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
0
0
0
RCS
CWL
RWL
WCS
Setup time, W low before CAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high before RAS low
(CAS-before-RAS refresh only)
t
10
10
10
ns
WRP
t
t
t
t
t
t
t
Setup time, W low before RAS low (test mode only)
Hold time, column address after CAS low
Hold time, data (see Note 12)
10
10
10
10
0
10
15
15
10
0
10
15
15
10
0
ns
ns
ns
ns
ns
ns
ns
WTS
CAH
DH
Hold time, row address after RAS low
RAH
RCH
RRH
WCH
Hold time, W high after CAS high (see Note 13)
Hold time, W high after RAS high (see Note 13)
Hold time, W low after CAS low (early-write operation only)
0
0
0
10
15
15
Hold time, W high after RAS low
(CAS-before-RAS refresh only)
t
10
10
10
ns
WRH
t
t
t
Hold time, W low after RAS low (test mode only)
Hold time, RAS high from CAS precharge
10
35
10
40
10
45
ns
ns
ns
WTH
RHCP
CHS
Hold time, CAS low after RAS high (self refresh)
– 50
– 50
– 50
NOTES: 8. All cycle times assume t = 5 ns.
T
ASC
9. To assure t
min, t
should be greater than or equal to t .
CP
PC
10. In a read-write cycle, t
11. In a read-write cycle, t
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
12. Referenced to the later of CAS or W in write operations
13. Either t or t must be satisfied for a read cycle.
RRH
RCH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’416100-60
’416100-70
’416100-80
’416100P-60
’416100P-70
’416100P-80
UNIT
MIN
30
10
5
MAX
MIN
35
10
5
MAX
MIN
40
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, column address to W low (read-write operation only)
Delay time, RAS low to CAS high (CAS-before-RAS refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ms
ms
ns
AWD
CHR
CRP
CSH
CSR
CWD
RAD
RAL
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
Delay time, CAS low to W low (read-write operation only)
Delay time, RAS low to column address (see Note 14)
Delay time, column address to RAS high
15
15
30
30
20
0
18
15
35
35
20
0
20
15
40
40
20
0
30
45
35
52
40
60
Delay time, column address to CAS high
CAL
Delay time, RAS low to CAS low (see Note 14)
Delay time, RAS high to CAS low
RCD
RPC
RSH
RWD
CPW
RASS
RPS
TAA
Delay time, CAS low to RAS high
15
60
35
100
110
35
40
65
18
70
40
100
130
40
45
75
20
80
45
100
150
45
50
85
Delay time, RAS low to W low (read-write operation only)
Delay time, W low after CAS precharge (read-write operation only)
Pulse duration, self-refresh entry from RAS low
Pulse duration, RAS precharge after self refresh
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RAS (test mode)
TCPA
TRAC
’416100
64
256
30
64
256
30
64
256
30
t
Refresh time interval
’416100P
REF
t
T
Transition time
3
3
3
NOTE 14: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
V
CC
= 5 V
R
= 218 Ω
R
R
= 828 Ω
L
1
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
= 295 Ω
L
2
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
Figure 2. Load Circuits
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
CP
t
RAD
t
ASC
t
RAH
t
t
CAL
RAL
Row
Column
Don’t Care
A0 – A11
t
RCS
t
RRH
t
RCH
t
CAH
W
Q
Don’t Care
Don’t Care
t
CAC
t
OFF
t
AA
Valid Data Out
Hi-Z
(see Note A)
CLZ
t
t
RAC
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 3. Read-Cycle Timing
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
CAS
t
RCD
t
t
CRP
t
CSH
t
ASR
t
CP
t
ASC
t
CAL
t
RAL
t
RAH
t
CAH
A0 – A11
Row
Column
Don’t Care
t
CWL
t
RAD
t
RWL
t
WCH
t
WCS
W
Don’t Care
Don’t Care
t
WP
t
DH
t
DS
D
Q
Valid Data
Don’t Care
Hi-Z
Figure 4. Early-Write-Cycle Timing
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CAS
t
CSH
t
CAS
ASR
t
CP
t
ASC
t
t
CAL
RAL
t
RAH
t
CAH
A0 – A11
Row
Column
Don’t Care
t
CWL
t
RAD
t
RWL
W
Don’t Care
Don’t Care
t
WP
t
DS
t
DH
D
Q
Don’t Care
Valid Data
Don’t Care
OFF
t
t
CLZ
t
OH
Not Valid
Figure 5. Write-Cycle Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
t
RP
T
t
t
CRP
RCD
t
CAS
t
ASR
t
CP
t
RAH
t
CAH
t
RAD
t
T
t
ASC
A0 – A11
Row
t
Column
Don’t Care
CWL
t
RCS
t
RWL
t
AWD
t
WP
W
Don’t Care
t
CWD
t
RWD
t
DS
D
Q
Don’t Care
Valid In
Don’t Care
t
CLZ
(see Note A)
t
t
OFF
DH
Hi-Z
Valid Out
t
CAC
AA
t
t
RAC
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
t
t
CRP
PC
RCD
t
t
t
CSH
RSH
CP
t
CAS
CAS
t
RAH
t
t
CAL
CAH
t
ASR
t
t
ASC
RAL
A0 – A11
Row
Column
Column
Don’t Care
†
t
t
AA
RRH
t
RCH
t
RCS
†
t
W
CAC
†
t
RAD
t
CPA
t
CAC
t
AA
t
OFF
t
RAC
t
CLZ
Valid
Out
Valid
Out
Q
(see Note A)
dependent.
†
Access time is t
, t , or t
CPA CAC AA
NOTE A: Output can go from 3-state to an invalid data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
RHCP
t
PC
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
ASC
t
RAH
t
CP
t
RAL
t
CAH
t
ASR
t
CAL
Row
Column
Column
Don’t Care
A0 – A11
t
RAD
t
CWL
t
CWL
t
t
RWL
WP
Don’t Care
Don’t Care
Don’t Care
W
(see Note A)
(see Note A)
t
DH
DH
(see Note A)
t
t
DS
t
DS
(see Note A)
Valid
In
Valid Data In
Don’t Care
D
Q
Hi-Z
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RHCP
RAS
t
CSH
t
RSH
t
PRWC
t
RCD
t
t
CRP
CP
t
CAS
CAS
t
RAH
t
ASC
t
RAD
t
t
ASR
CAH
A0 – A11
Row
Column
Column
Don’t Care
t
t
CPW
CWD
t
RCS
t
CWL
t
AWD
t
WP
t
RWL
t
RWD
W
D
t
DS
t
DH
Don’t Care
Valid
Don’t Care
CAC
Valid
Don’t Care
t
t
CPA
t
AA
t
OFF
t
RAC
t
CLZ
(see Note A)
(see Note A)
Valid
Out
Valid Out
Q
NOTES: A. Output can go from 3-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
t
CRP
RP
t
CRP
t
T
t
RPC
Don’t Care
Don’t Care
t
RAH
t
ASR
Row
Don’t Care
Row
A0 – A11
Don’t Care
W
Don’t Care
Hi-Z
D
Q
Figure 10. RAS-Only-Refresh-Cycle Timing
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WRP
t
WRH
W
A0 – A11
D
Don’t Care
Don’t Care
Q
Hi-Z
Figure 11. Automatic (CAS-Before-RAS) Refresh-Cycle Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
RP
Refresh Cycle
Memory Cycle
t
t
RP
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
A0 – A11
t
WRH
t
t
t
RRH
WRH
WRH
t
t
t
WRP
RCS
t
WRP
WRP
W
D
t
CAC
AA
t
Don’t Care
t
RAC
t
OFF
t
CLZ
Valid Data
Q
Figure 12. Hidden-Refresh-Cycle (Read) Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
ASC
t
t
RAH
t
ASR
A0–A11
Row
Col
Don’t Care
t
t
WRH
RRH
t
t
WCS
WRP
t
WP
W
t
WCH
t
DH
t
DS
D
Q
Don’t Care
Hi-Z
Figure 13. Hidden-Refresh-Cycle (Write) Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RASS
RAS
CAS
t
t
RPC
RPS
t
CSR
t
CHS
t
CP
A0–A11
W
Don’t Care
Don’t Care
Don’t Care
OE
t
OFF
DQ1–DQ4
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WTH
t
WTS
Don’t Care
W
A0 – A11
D
Don’t Care
Don’t Care
Hi-Z
Q
Figure 15. Test-Mode-Entry-Cycle Timing
t
RC
t
RP
t
RAS
RAS
t
RPC
t
CSR
t
CHR
t
T
CAS
t
WRP
W
Don’t Care
Don’t Care
t
WRH
A0–A11
Don’t Care
t
OFF
Hi-Z
Don’t Care
Q
Figure 16. Test-Mode-Exit-Cycle (CAS-Before-RAS Refresh Cycle) Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
MECHANICAL DATA
DJ–24/26 LEAD PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
R–PDSO–J24/26
0.680 (17,27)
0.670 (17,02)
26
14
0.305 (7,75) 0.340 (8,64)
0.295 (7,49)
0.330 (8,38)
1
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.275 (6,99)
0.260 (6,60)
0.148 (3,76)
0.128 (3,25)
0.050 (1,27) TYP
NOTES: A. All linear dimensions are in inches (millimeters).
B. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
MECHANICAL DATA
DGA–24/26 LEAD PLASTIC THIN SMALL-OUTLINE PACKAGE
R–PDSO–G24/26
‡
17, 25 (0.679)
17, 04 (0.671)
26 25 24 23 22 21
19 18 17 16 15 14
†
7, 72 (0.304)
7, 52 (0.296)
9, 42 (0.371)
9, 02 (0.355)
Index
1
2
3
4
5
6
8
9
10 11 12 13
1,20 (0.047) MAX
0, 21 (0.008)
0, 12 (0.005)
0, 15 (0.006)
0, 05 (0.002)
0, 60 (0.024)
0, 40 (0.016)
0° to 5°
1,27 (0.050) TYP
8,20
(0.323)
TYP
0, 51 (0.020)
0, 31 (0.012)
†
‡
Plastic body width does not include mold protrusion. Maximum mold protrusion is 0,25 ( 0.010) per side from the edge of the package bottom.
Plastic body length does not include mold protrusion. Maximum mold protrusion is 0,15 (0.006) per side from the edge of the package bottom.
NOTE A: All linear dimensions are in millimeters and parenthetically in inches.
device symbolization
TI
P
-SS
Speed (-60, -70, -80)
Low-Power/Self-Refresh
Code
TMS416100 DJ
Package Code
W
B
P
XXX LLL
Lot Traceability Code
Date Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
Printed in U. S. A.
SMKS611
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1998, Texas Instruments Incorporated
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