TMS416400A [TI]
4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES; 4194304 4位动态随机存取存储器
| 型号： | TMS416400A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 文件： | 总27页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
DJ PACKAGE
(TOP VIEW)
This data sheet is applicable to all
TMS41x400As symbolized by Revision “B”,
Revision “E” and subsequent revisions as
described in the device symbolization section.
V
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
CC
DQ1
DQ2
W
DQ4
DQ3
CAS
OE
Organization . . . 4194304 × 4
Single 5-V Power Supply (±10% Tolerance)
RAS
2048-Cycle Refresh in 32 ms for
TMS417400A
†
A11
A9
4096-Cycle Refresh in 64 ms for
TMS416400A
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
9
Performance Ranges:
10
11
12
13
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
CYCLE
MIN
90 ns
110 ns
130 ns
t
t
t
RAC
CAC
AA
MAX
50 ns
60 ns
70 ns
MAX
13 ns
15 ns
18 ns
MAX
25 ns
30 ns
35 ns
V
V
SS
CC
’41x400A-50
’41x400A-60
’41x400A-70
PIN NOMENCLATURE
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
†
A[0:11]
CAS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
No Internal Connection
Row-Address Strobe
5-V Supply
DQ[1:4]
OE
3-State Unlatched Output
Low Power Dissipation
NC
RAS
High-Reliability Plastic 24/26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix)
V
V
W
CC
SS
Ground
Write Enable
Ambient Temperature Range:
†
A11 is NC for TMS417400A
0°C to 70°C
description
The TMS41x400A is a set of 16 777 216-bit dynamic random-access memory (DRAMs) devices organized as
4194304 words of 4 bits each. The TMS41x400A employs state-of-the-art technology for high performance,
reliability, and low power.
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS416400A and TMS417400A are offered in a 24/26-lead plastic surface-mount SOJ package
(DJ suffix). This package is designed for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
†
logic symbol (TMS416400A)
RAM 4096 K × 4
20D10/21D0
9
A0
A1
10
11
12
15
16
17
18
19
21
8
A2
A3
A4
0
A5
A
4194303
A6
A7
A8
A9
20D19/21D9
20D20
A10
A11
6
20D21
C20 [ROW]
G23/[REFRESH ROW]
5
RAS
CAS
24 [PWR DWN]
C21[COLUMN]
G24
&
23
23C22
24,25 EN
4
W
23,21D
G25
22
OE
2
DQ1
A,22D
26
A,Z26
3
DQ2
DQ3
24
25
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
†
logic symbol (TMS417400A)
RAM 4096 K × 4
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
20D11/21D0
10
11
12
15
16
17
18
19
21
8
0
A
4194303
20D21/21D10
C20 [ROW]
G23/[REFRESH ROW]
5
RAS
CAS
24 [PWR DWN]
C21[COLUMN]
G24
&
23
23C22
24,25 EN
4
W
23,21D
G25
22
OE
2
DQ1
A,22D
26
A,Z26
3
DQ2
DQ3
24
25
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
functional block diagram
TMS416400A
RAS CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
256K Array
4
Column-
Address
Buffers
R
o
w
Data-
In
†
4
256K Array
A11
4
Reg.
I/O
Buffers
4
D
e
c
o
d
e
64
Data-
Out
Reg.
Row-
Address
Buffers
12
256K Array
DQ1–DQ4
12
Column addresses A10 and A11 are not used.
†
TMS417400A
RAS CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
4
Column-
Address
Buffers
256K Array R 256K Array
o
Data-
In
4
256K Array
256K Array
A10
w
4
Reg.
I/O
Buffers
4
D
e
c
o
d
e
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
256K Array
11
256K Array
DQ1–DQ4
4
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
operation
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by t
, the maximum RAS low time.
RASP
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode devices because data retrieval begins as soon as the
column address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced-page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after t
max
CAC
(access time from CAS low) if t max (access time from column address) and t
have been satisfied. In the
AA
RAC
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of t or t
.
CAC
CPA
address: A0–A11 (TMS416400A) and A0–A10 (TMS417400A)
Twenty-two address bits are required to decode each of the 4194304 storage cell locations. For the
TMS416400A, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS417400A, 11 row-address bits
are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address bits are set up
on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS. RAS is similar
to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used as a chip
select, activating the output buffers and latching the address bits into the column-address buffers.
write enable (W)
The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1–DQ4)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup-and-hold times referenced to this signal. In a delayed-write- or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with the setup-and-hold time
referenced to this signal. Also, OE must be high to bring the output buffers to the high-impedance state prior
to impressing data on the I/O lines.
data out (DQ1–DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access-time interval t
(which begins with
CAC
the negative transition of CAS) as long as t
and t are satisfied.
RAC
AA
5
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
RAS-only refresh
TMS416400A
Arefreshoperationmustbeperformedatleastonceevery64mstoretaindata. Thiscanbeachievedbystrobing
each of the 4 096 rows (A0–A11). A normal read- or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
TMS417400A
Arefreshoperationmustbeperformedatleastonceevery32mstoretaindata. Thiscanbeachievedbystrobing
each of the 2 048 rows (A0–A10). A normal read- or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
IL
refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
) and holding it low after RAS
CSR
falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
CHR
external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs, followed by a minimum of eight initialization
cycles, is required after power up to the full V
refresh (RAS-only or CBR) cycle.
level. These eight initialization cycles must include at least one
CC
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the Winput low. The entry cycle
performs an internal-refresh cycle while internally setting the device to perform a parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR-refresh cycle (with W held high) or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1 024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel-read-andwritedatabusthatignorescolumnaddressesA0andA1. Duringareadcycle, thefourinternal
bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. Test
time is reduced by a factor of four for this series of events.
6
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
test mode (continued)
Exit Cycle
Normal
Mode
Entry Cycle
RAS
Test Mode Cycle
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
7
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS41x400A
MIN NOM MAX
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Ambient temperature
2.4
– 1
0
6.5
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
8
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TMS416400A
’416400A-50 ’416400A-60 ’416400A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
100
0.4
± 10
± 10
80
0.4
± 10
± 10
70
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
CC
Output current
(leakage)
V
= 5.5 V,
CC
CAS high
V
= 0 V to V ,
CC
O
O
Average read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
After one memory cycle,
RAS and CAS high
IH
2
1
2
1
2
1
mA
mA
Average standby
current
I
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS-only
refresh or CBR)
‡§
‡¶
I
I
100
80
80
70
70
60
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
Average page current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each page-mode cycle, t
.
PC
9
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TMS417400A
’417400A-50 ’417400A-60 ’417400A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
130
0.4
± 10
± 10
110
0.4
± 10
± 10
100
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
CC
Output current
(leakage)
V
= 5.5 V,
CC
CAS high
V
= 0 V to V ,
CC
O
O
Average read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
After one memory cycle,
RAS and CAS high
IH
2
1
2
1
2
1
mA
mA
Average standby
current
I
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After one memory cycle,
RAS and CAS high
Average refresh
current (RAS-only
refresh or CBR)
V
= 5.5 V,
Minimum cycle,
CAS high (RAS only),
RAS low after CAS low (CBR)
CC
RAS cycling,
‡§
‡¶
I
I
130
90
110
70
100
60
mA
mA
CC3
Average page
current
V
= 5.5 V, = MIN,
t
CC
RAS low,
PC
CAS cycling
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each page-mode cycle, t
.
PC
10
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
†
C
C
C
C
C
Input capacitance, A0–A11
5
7
7
7
7
i(A)
Input capacitance, OE
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
‡
Output capacitance
pF
†
‡
A11 is NC (no internal connection) for TMS417400A.
CAS = V to disable outputs.
IH
NOTE 3:
V
CC
= 5 V ±10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 4)
’41x400A-50
’41x400A-60
’41x400A-70
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Access time from column address
Access time from CAS
25
13
30
50
13
30
15
35
60
15
35
18
40
70
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
CAC
CPA
RAC
OEA
CLZ
OH
Access time from CAS precharge
Access time from RAS
Access time from OE
Delay time, CAS to output in low-impedance state
Output data hold time from CAS
Output data hold time from OE
0
3
3
0
0
0
3
3
0
0
0
3
3
0
0
OHO
OFF
OEZ
Output buffer turn-off delay from CAS (see Note 5)
Output buffer turn-off delay from OE (see Note 5)
13
13
15
15
18
18
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
5.
t
and t
are specified when the output is no longer driven. Data-in should not be enabled until one of the maximum values
OEZ
OFF
is satisfied.
11
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
ac timing requirements (see Note 4)
’41x400A-50
’41x400A-60
’41x400A-70
UNIT
MIN
90
MAX
MIN
110
110
155
40
MAX
MIN
130
130
181
45
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write
90
WC
Cycle time, read-write
131
35
RWC
PC
Cycle time, page-mode read or write (see Note 6)
Cycle time, page-mode read-write
Pulse duration, RAS active, page mode (see Note 7)
Pulse duration, RAS active, nonpage mode (see Note 7)
Pulse duration, CAS active (see Note 8)
Pulse duration, CAS precharge
76
85
96
PRWC
RASP
RAS
CAS
CP
50 100 000
60 100 000
70 100 000
50
13
8
10 000
10 000
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
Pulse duration, RAS precharge
30
10
0
RP
Pulse duration, write command
WP
Setup time, column address
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data-in (see Note 9)
Setup time, read command
0
0
0
0
0
0
RCS
CWL
RWL
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
13
13
15
15
18
18
Setup time, write command before CAS active
(early-write only)
t
t
t
0
10
10
0
10
10
0
10
10
ns
ns
ns
WCS
WRP
WTS
Setup time, write before RAS active (CBR refresh only)
Setup time, write command before RAS active
(test mode only)
t
t
t
t
t
Hold time, column address
10
10
8
10
10
10
0
15
15
10
0
ns
ns
ns
ns
ns
CAH
Hold time, data-in (see Note 9)
DH
Hold time, row address
RAH
RCH
RRH
Hold time, read command referenced to CAS (see Note 10)
Hold time, read command referenced to RAS (see Note 10)
0
0
0
0
Hold time, write command during CAS active
(early-write only)
t
10
10
15
ns
WCH
t
t
t
t
t
Hold time, RAS active from CAS precharge
Hold time, OE command
30
13
10
10
10
35
15
10
10
10
40
18
10
10
10
ns
ns
ns
ns
ns
RHCP
OEH
ROH
WRH
WTH
Hold time, RAS referenced to OE
Hold time, write after RAS active (CBR refresh only)
Hold time, write command after RAS active (test mode only)
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
CP
6. To assure t
7. In a read-write cycle, t
8. In a read-write cycle, t
min, t
should be ≥ t
.
PC
ASC
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
9. Referenced to the later of CAS or W in write operations
10. Either t or t must be satisfied for a read cycle.
RRH
RCH
12
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
ac timing requirements (see Note 4) (continued)
’41x400A-50 ’41x400A-60 ’41x400A-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, column address to write command
(read-write operation only)
t
48
55
63
ns
AWD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CAS referenced to RAS (CBR refresh only)
Delay time, CAS precharge to RAS
10
5
10
5
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CHR
CRP
CSH
CSR
CWD
OED
RAD
RAL
Delay time, RAS active to CAS precharge
Delay time, CAS referenced to RAS (CBR refresh only)
Delay time, CAS to write command (read-write operation only)
Delay time, OE to data in
50
5
60
5
70
5
36
13
13
25
25
18
5
40
15
15
30
30
20
5
46
18
15
35
35
20
5
Delay time, RAS to column address (see Note 11)
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 11)
25
37
30
45
35
52
CAL
RCD
RPC
RSH
RWD
CPW
TAA
Delay time, RAS precharge to CAS active
Delay time, CAS active to RAS precharge
Delay time, RAS to write command (read-write operation only)
Delay time, CAS precharge to write command (read-write only)
Access time from address (test mode)
13
73
53
30
35
55
15
85
60
35
40
65
18
98
68
40
45
75
Access time from column precharge (test mode)
Access time from RAS (test mode)
TCPA
TRAC
’416400A
’417400A
64
32
30
64
32
30
64
32
30
t
Refresh time interval
ms
ns
REF
t
T
Transition time
2
2
2
NOTES: 4. With ac parameters, it is assumed that t = 5 ns.
T
11. The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
V
TH
V
CC
R
R
L
1
2
Output Under Test
Output Under Test
R
C
= 100 pF
L
C
= 100 pF
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
L
DEVICE
V
(V)
R
(Ω)
R
(Ω)
V
(V)
TH
1.31
R (Ω)
L
CC
1
2
’41x400A
5
828
295
218
Figure 2. Load Circuits for Timing Parameters
13
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SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
CP
t
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Row
Column
Don’t Care
Address
t
t
RRH
RCS
t
CAH
t
RCH
Don’t Care
Don’t Care
W
t
CAC
t
OFF
OH
t
AA
t
Valid Data Out
DQ1–DQ4
Hi-Z
See Note A
t
CLZ
t
OHO
t
RAC
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
14
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
t
CAL
RAS
t
RP
t
T
t
RSH
t
RCD
t
CAS
t
CRP
t
CSH
t
CAS
Address
W
ASR
t
CP
t
ASC
t
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
t
CWL
t
t
RAD
RWL
t
WCH
Don’t Care
Don’t Care
t
WCS
t
DH
t
DS
Valid Data
Don’t Care
DQ1–DQ4
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
15
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CAS
t
CSH
t
CAS
ASR
t
t
CP
ASC
t
RAL
t
CAL
t
RAH
t
CAH
Don’t Care
Row
Column
Address
t
CWL
t
RAD
t
DS
t
RWL
Don’t Care
Don’t Care
Don’t Care
W
t
WP
t
CLZ
t
DH
Valid Data In
DQ1–DQ4
Invalid Data Out
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 5. Write-Cycle Timing
16
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
t
CRP
RCD
t
CAS
t
ASR
t
CP
t
RAH
t
CAH
t
RAD
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWL
t
RWD
t
WP
Don’t Care
Don’t Care
Don’t Care
t
W
AWD
t
CWD
t
CAC
t
DS
t
AA
t
DH
t
CLZ
Data
Out
Data
In
DQ1–DQ4
See Note A
t
RAC
t
t
OEH
OEZ
t
OHO
t
t
OED
OEA
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
17
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RHCP
t
PC
RAS
t
RCD
t
CRP
t
t
t
CSH
RSH
CP
t
CAS
CAS
Address
W
t
RAH
t
CAL
t
t
t
CAH
ASR
t
ASC
RAL
Row
Column
Column
Don’t Care
†
t
t
AA
RRH
t
RCH
t
RCS
†
t
CAC
t
RAD
†
t
CPA
t
CAC
t
AA
t
OFF
t
RAC
t
OH
t
CLZ
Valid
Out
Valid
Out
DQ1–DQ4
See Note A
t
t
OHO
OHO
t
t
OEZ
OEZ
t
OEA
t
OEA
Don’t Care
OE
Access time is t
†
-, t
CPA CAC
-, or t -dependent.
AA
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
18
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
t
CSH
PC
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
CAH
ASR
Address
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
t
CWL
t
RWL
WP
t
DS
W
Don’t Care
Don’t Care
Don’t Care
t
OEH
t
DH
t
CLZ
Valid
In
Don’t Care
Valid Data In
Don’t Care
DQ1–DQ4
Invalid Data out
t
OEH
t
OED
Don’t Care
Don’t Care
OE
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
19
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
RHCP
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
CAS
t
ASR
t
ASC
t
RAD
t
CAH
Column
Don’t Care
Row
Column
Address
t
RAH
t
CWL
t
CWD
t
t
AWD
RWD
CPW
t
RWL
t
t
WP
W
t
CPA
t
OEH
t
RCS
t
t
DH
AA
t
t
DS
†
RAC
Valid Out
t
CAC
Valid
In
Valid
In
DQ1–DQ4
t
CLZ
Valid Out
t
OED
t
OEZ
t
OEH
t
OEA
OE
t
OHO
†
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
20
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
t
ASR
t
RAH
Row
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Row
Address
W
DQ1–DQ4
OE
Figure 10. RAS-Only Refresh Timing
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WRP
t
WRH
Don’t Care
Don’t Care
W
Address
OE
Don’t Care
Don’t Care
DQ1–DQ4
Hi-Z
Figure 11. Automatic-CBR-Refresh-Cycle Timing
21
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
RP
Memory Cycle
t
RP
t
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
Address
t
t
WRH
RRH
t
t
WRH
WRH
t
WRP
t
WRP
t
t
RCS
WRP
W
t
CAC
AA
t
t
OFF
t
RAC
Valid Data Out
DQ1–DQ4
OE
t
CLZ
t
OEZ
t
OEA
Figure 12. Hidden-Refresh-Cycle (Read) Timing
22
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Row
Col
Address
t
WRH
t
WCS
t
WRP
t
WP
W
t
WCH
t
DH
t
DS
Don’t Care
Valid Data
DQ1–DQ4
OE
Don’t Care
Figure 13. Hidden-Refresh-Cycle (Write) Timing
23
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
CHR
t
RPC
t
T
t
WTH
t
WTS
Don’t Care
W
Don’t Care
Address
OE
Don’t Care
Hi-Z
DQ1–DQ4
Figure 14. Test-Mode-Entry-Cycle Timing
t
RC
t
RP
t
RAS
RAS
t
CSR
t
RPC
t
CHR
t
T
CAS
t
WRP
W
Don’t Care
Don’t Care
t
WRH
Address
Don’t Care
t
OFF
Hi-Z
Don’t Care
DQ1–DQ4
Figure 15. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
24
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TMS416400A, TMS417400A
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.008 (0,20) NOM
0.148 (3,76)
0.128 (3,25)
Seating Plane
0.004 (0,10)
0.275 (6,99)
0.260 (6,60)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18)
M
0.050 (1,27)
40400A92-3/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416400A illustrated)
TI
-SS
Speed ( -50, - 60, -70)
Package Code
TMS416400A DJ
W
E
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
25
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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