TMS417400-80DZ [TI]
IC 4M X 4 FAST PAGE DRAM, 80 ns, PDSO24, Dynamic RAM;
| 型号： | TMS417400-80DZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC 4M X 4 FAST PAGE DRAM, 80 ns, PDSO24, Dynamic RAM 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总30页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
DJ PACKAGE
(TOP VIEW)
DGA PACKAGE
(TOP VIEW)
Electrical characteristics for TMS416400/P and
TMS417400/P is Production Data. Electrical
characteristics
TMS427400/P is Product Preview only.
for
TMS426400/P
and
V
1
2
3
4
5
6
26
25
24
23
22
21
V
V
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
CC
SS
CC
DQ1
DQ2
W
DQ4 DQ1
DQ3 DQ2
CAS
OE
A9
DQ4
DQ3
CAS
OE
Organization . . . 4194304 × 4
Single 5 V Power Supply for TMS41x400/P
(±10% Tolerance)
W
RAS
RAS
†
†
A11
A11
A9
Single 3.3 V Power Supply for
TMS42x400/P (±0.3 V Tolerance)
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
Performance Ranges:
9
9
ACCESS ACCESS ACCESS READ OR
10
11
12
13
10
11
12
13
TIME
TIME
TIME
WRITE
CYCLE
MIN
t
t
t
RAC
CAC
AA
MAX
MAX
MAX
’4xx400/P-60
’4xx400/P-70
’4xx400/P-80
60 ns
70 ns
80 ns
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
V
V
V
V
SS
CC
SS
CC
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
Long Refresh Period and Self-Refresh
Option (TMS4xx400P)
PIN NOMENCLATURE
†
A0–A11
CAS
Address Inputs
3-State Unlatched Output
Low Power Dissipation
Column-Address Strobe
Data In/Data Out
DQ1–DQ4
OE
Output Enable
High-Reliability Plastic 24/26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package and 24/26-Lead
Surface-Mount Thin Small-Outline Package
(TSOP)
NC
No Internal Connection
RAS
Row-Address Strobe
‡
V
V
5-V or 3.3-V Supply
Ground
CC
SS
W
Write Enable
Operating Free-Air Temperature Range:
†
‡
A11 is NC for TMS4x7400/P.
See Available Options Table
0°C to 70°C
EPIC (Enhanced Performance Implanted
CMOS) Technology
description
AVAILABLE OPTIONS
SELF
The TMS4xx400 is
a set of high-speed,
POWER
SUPPLY
REFRESH
CYCLES
REFRESH
BATTERY
BACKUP
DEVICE
16777216-bit dynamic random-access memories
organized as 4194304 words of 4 bits each. The
TMS4xx400P series are high-speed, low-power,
self-refresh, 16777216-bit dynamic random-
access memories organized as 4194304 words of
4 bits each. The TMS4xx400 and TMS4xx400P
employ state-of-the-art EPIC
Performance Implanted CMOS) technology for
high performance, reliability, and low power.
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426400
TMS426400P
TMS427400
TMS427400P
5 V
5 V
5 V
—
Yes
—
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
5 V
Yes
—
Yes
—
3.3 V
3.3 V
3.3 V
3.3 V
(Enhanced
Yes
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
description (continued)
The TMS4xx400 and TMS4xx400P are each offered in a 24/26-lead plastic surface-mount TSOP (DGA suffix)
package and a 24/26-lead plastic surface-mount SOJ (DJ suffix) package. These packages are characterized
for operation from 0°C to 70°C.
operation
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by t
, the maximum RAS low time.
RASP
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge
of CAS latches the column addresses and enables the output. This feature allows the devices to operate at a
higher data bandwidth than conventional page-mode parts because data retrieval begins as soon as the column
address is valid rather than when CAS transitions low. This performance improvement is referred to as
enhanced page mode. A valid column address can be presented immediately after row-address hold time has
been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained after t
max
CAC
(access time from CAS low) if t max (access time from column address) and t
have been satisfied. In the
AA
RAC
event that column address for the next cycle is valid at the time CAS goes high, access time for the next cycle
is determined by the later occurrence of t or t
.
CAC
CPA
address: A0–A11 (TMS4x6400/P) and A0–A10 (TMS4x7400/P)
Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. For the TMS4x6400 and
TMS4x6400P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address
strobe (RAS). Ten column-address bits are set up on A0 through A9. For TMS4x7400 and TMS4x7400P, 11
row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Eleven column-address
bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of RAS and CAS.
RAS is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip select, activating the output buffers and latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ1–DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ1–DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t
(which begins with
CAC
the negative transition of CAS) as long as t
and t are satisfied.
AA
RAC
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
RAS-only refresh
TMS4x6400, TMS4x6400P
A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This
can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
TMS4x7400, TMS4x7400P
A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This
can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
IL
refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
) and holding it low after RAS
CSR
falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
CHR
external address is ignored, and the refresh address is generated internally.
battery-backup refresh
TMS4x6400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current
is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25 µs while
holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
( V < 0.2 V, V > V
– 0.2 V).
IL
IH
CC
TMS4x7400P
A low-power battery-backup refresh mode that requires less than 500 µA (5 V) or 350 µA (3.3 V) refresh current
is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5 µs while
holding RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
(V < 0.2 V, V > V – 0.2 V).
CC
IL
IH
self refresh (TMS4xx400P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy t
. Upon exiting self-refresh mode, a burst refresh (refresh a
CHS
full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures
the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or CBR) cycle.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
test mode
The test mode is initiated with a CBR-refresh cycle while simultaneously holding the Winput low. The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test mode
if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin separately. If the four bits agree, DQ goes high; if not, DQ goes low. During
a write cycle, the data states of all four DQs must be the same to ensure proper function of the test mode. Test
time is reduced by a factor of four for this series.
Exit Cycle
Entry Cycle
Normal
Mode
Test Mode Cycle
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
Figure 1. Test-Mode Cycle
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
†
logic symbol
RAM 4096 K × 4
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
20D10/21D0
10
11
12
15
16
17
18
19
21
8
0
A
4194303
20D19/21D9
20D20
6
‡
A11
20D21
C20 [ROW]
G23/[REFRESH ROW]
5
RAS
CAS
24 [PWR DWN]
C21[COLUMN]
G24
&
25
23C22
24,25 EN
4
W
23,21D
G25
22
OE
2
DQ1
A,22D
26
A,Z26
3
DQ2
DQ3
24
25
DQ4
†
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
A11 is NC for TMS4x7400 and TMS4x7400P.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
functional block diagram
TMS4x6400/P
RAS CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
256K Array
4
Column-
Address
Buffers
Data-
In
†
R
o
4
256K Array
A11
Reg.
4
w
I/O
4
Buffers
D
e
c
o
d
e
64
Data-
Out
Reg.
Row-
Address
Buffers
12
256K Array
DQ1–DQ4
12
Column addresses A10 and A11 are not used.
†
TMS4x7400/P
RAS CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
4
Column-
Address
Buffers
256K Array
256K Array
256K Array
256K Array
Data-
In
R
o
4
A10
Reg.
4
w
I/O
4
Buffers
D
e
c
o
d
e
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
256K Array
11
256K Array
DQ1–DQ4
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
:
TMS41x400, TMS41x400P . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x400, TMS42x400P . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
TMS41x400, TMS41x400P . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x400, TMS42x400P . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
Voltage range on any pin (see Note 1):
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS41x400
MIN NOM
TMS42x400
UNIT
MAX
MIN
NOM
3.3
0
MAX
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
3
3.6
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
2
– 0.3
0
V
CC
+ 0.3
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416400/P
’416400-60
’416400-70
’416400-80
’416400P-60
’416400P-70
’416400P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
80
0.4
± 10
± 10
70
0.4
± 10
± 10
60
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V
O CC
,
CC
CAS high
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
2
2
2
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
’416400
1
1
1
mA
IH
After 1 memory cycle,
RAS and CAS high
’416400P
500
500
500
µA
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS-only
refresh or CBR)
‡§
I
80
70
60
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
PC
‡¶
#
I
I
Average page current
Self-refresh current
70
60
50
mA
CC4
RAS low,
CAS cycling
CAS < 0.2 V,
Measured after t
RAS < 0.2 V,
500
500
500
µA
CC6
min
RASS
Battery back-up
operating current
(equivalent refresh
time is 128 ms); CBR
only
t
V
= 31.25 µs,
t
≤ 1 µs,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
CC
IH
#
I
500
500
500
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
For TMS416400P only
IL
IH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417400/P
’417400-60
’417400-70
’417400-80
’417400P-60
’417400P-70
’417400P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
110
0.4
± 10
± 10
100
0.4
± 10
± 10
90
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
Output current
(leakage)
V
= 5.5 V,
V
= 0 V to V
O CC
,
CC
CAS high
O
Read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
2
2
2
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
’417400
1
1
1
mA
IH
After 1 memory cycle,
RAS and CAS high
’417400P
500
500
500
µA
Average refresh
current (RAS-only
refresh or CBR)
V
= 5.5 V,
Minimum cycle,
CAS high (RAS only),
RAS low after CAS low (CBR)
CC
RAS cycling,
‡§
I
110
100
90
mA
CC3
Average page
current
V
= 5.5 V, = MIN,
t
CC
PC
‡¶
#
I
I
70
60
50
mA
CC4
RAS low,
CAS cycling
CAS < 0.2 V,
Measured after t
RAS < 0.2 V,
Self-refresh current
500
500
500
µA
CC6
min
RASS
Battery back-up
operating current
(equivalent refresh
time is 128 ms);
CBR only
t
V
= 62.5 µs,
t
≤ 1 µs,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
CC
IH
#
I
500
500
500
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
For TMS417400P only
IL
IH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
TMS426400/P
’426400-60
’426400-70
’426400-80
’426400P-60
’426400P-70
’426400P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
High-level
output voltage
OH
OH
OL
OL
V
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
CC
CC
CC
0.4
0.2
0.4
0.2
0.4
0.2
Low-level
output voltage
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
I
± 10
± 10
70
± 10
± 10
60
± 10
± 10
50
µA
µA
I
CC
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V
O CC
,
CC
CAS high
O
Read- or write-
cycle current
‡§
V
V
= 3.6 V,
Minimum cycle
mA
CC1
CC
= 2 V (LVTTL),
IH
After 1 memory cycle,
RAS and CAS high
1
1
1
mA
Standby
current
I
CC2
V
= V
– 0.2 V
CC
IH
(LVCMOS),
’426400
500
200
500
200
500
200
µA
µA
After 1 memory cycle,
RAS and CAS high
’426400P
Average
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
refresh current
(RAS-only
refresh
‡§
I
70
60
50
mA
CC3
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
or CBR)
Average page
current
V
= 3.6 V,
t
= MIN,
CC
PC
‡¶
#
I
I
60
50
40
mA
CC4
RAS low,
CAS cycling
Self-refresh
current
CAS < 0.2 V,
Measured after t
RAS < 0.2 V,
250
250
250
µA
CC6
min
RASS
Battery
back-up
operating
current
(equivalent
refresh time is
128 ms),
CBR only
t
V
= 31.25 µs,
t
≤ 1 µs,
RC
RAS
– 0.2 V ≤ V ≤ 3.9 V,
CC
IH
#
I
350
350
350
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
For TMS426400P only
IL
IH
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
TMS427400/P
’427400-60
’427400-70
’427400-80
’427400P-60
’427400P-70
’427400P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
High-level
output voltage
OH
OH
OL
OL
V
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
CC
CC
CC
0.4
0.2
0.4
0.2
0.4
0.2
Low-level
output voltage
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
I
± 10
± 10
100
± 10
± 10
90
± 10
± 10
80
µA
µA
I
CC
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V
O CC
,
CC
CAS high
O
Read- or write-
cycle current
‡§
V
V
= 3.6 V,
Minimum cycle
mA
CC1
CC
= 2 V (LVTTL),
IH
After 1 memory cycle,
RAS and CAS high
1
1
1
mA
Standby
current
I
CC2
V
= V
– 0.2 V
CC
IH
(LVCMOS),
’427400
500
200
500
200
500
200
µA
µA
After 1 memory cycle,
RAS and CAS high
’427400P
Average
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
refresh current
(RAS-only
refresh
‡§
I
100
90
80
mA
CC3
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
or CBR)
Average page
current
V
= 3.6 V,
t
= MIN,
CC
PC
‡¶
#
I
I
60
50
40
mA
CC4
RAS low,
CAS cycling
Self-refresh
current
CAS < 0.2 V,
Measured after t
RAS < 0.2 V,
250
250
250
µA
CC6
min
RASS
Battery
back-up
operating
current
(equivalent
refresh time is
128 ms),
CBR only
t
V
= 62.5 µs,
t
≤ 1 µs,
RC
RAS
– 0.2 V ≤ V ≤ 3.9 V,
CC
IH
#
I
350
350
350
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while CAS = V
For TMS427400P only
IL
IH
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
C
Input capacitance, A0–A11
Input capacitance, OE
5
7
7
7
7
i(A)
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
NOTE 3:
V
CC
= NOM supply voltage ±10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’4xx400-60
’4xx400-70
’4xx400-80
’4xx400P-60
’4xx400P-70
’4xx400P-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CAS low (see Note 4)
Access time from column precharge (see Note 4)
Access time from RAS low (see Note 4)
Access time from OE low (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
CPA
RAC
OEA
CLZ
OH
35
40
45
60
70
80
15
18
20
Delay time, CAS low to output in low-impedance state
Output data hold time (from CAS)
0
3
3
0
0
0
3
3
0
0
0
3
3
0
0
Output data hold time (from OE)
OHO
OFF
OEZ
Output disable time after CAS high (see Note 5)
Output disable time after OE high (see Note 5)
15
15
18
18
20
20
NOTES: 4. Access times for TMS42x400 measured with output reference levels of V
OH
= 2 V and V
OL
= 0.8 V.
5.
t
and t are specified when the output is no longer driven.
OEZ
OFF
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4xx400-60
’4xx400-70
’4xx400-80
’4xx400P-60
’4xx400P-70
’4xx400P-80
UNIT
MIN
110
110
155
40
MAX
MIN
130
130
181
45
MAX
MIN
150
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (see Note 6)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write (see Note 6)
WC
Cycle time, read-write (see Note 6)
RWC
PC
Cycle time, page-mode read or write (see Notes 6 and 7)
Cycle time, page-mode read-write (see Note 6)
Pulse duration, RAS low, page mode (see Note 8)
Pulse duration, RAS low, nonpage mode (see Note 8)
Pulse duration, CAS low (see Note 9)
85
96
105
PRWC
RASP
RAS
CAS
CP
60 100 000
70 100 000
80 100 000
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
RP
Pulse duration, W low
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 10)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
0
0
0
RCS
CWL
RWL
WCS
WRP
WTS
CAH
DH
Setup time, W low before CAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high before RAS low (CBR refresh only)
Setup time, W low before RAS low (test mode only)
Hold time, column address after CAS low
Hold time, data (see Note 10)
10
10
10
10
10
0
10
10
15
15
10
0
10
10
15
15
10
0
Hold time, row address after RAS low
RAH
RCH
RRH
WCH
RHCP
OEH
ROH
CHS
WRH
WTH
Hold time, W high after CAS high (see Note 11)
Hold time, W high after RAS high (see Note 11)
Hold time, W low after CAS low (early-write operation only)
Hold time, RAS high from CAS precharge
Hold time, OE command
0
0
0
10
35
15
10
– 50
10
10
15
40
18
10
– 50
10
10
15
45
20
10
– 50
10
10
Hold time, RAS referenced to OE
Hold time, CAS low after RAS high (self refresh)
Hold time, W high after RAS low (CBR refresh only)
Hold time, W low after RAS low (test mode only)
NOTES: 6. All cycle times assume t = 5 ns.
T
ASC
7. To assure t
min, t
should be ≥ to t
.
CP
PC
8. In a read-write cycle, t
9. In a read-write cycle, t
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
10. Referenced to the later of CAS or W in write operations
11. Either t or t must be satisfied for a read cycle.
RRH
RCH
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4xx400-60
’4xx400-70
’4xx400-80
’4xx400P-60
’4xx400P-70
’4xx400P-80
UNIT
MIN
55
10
5
MAX
MIN
63
10
5
MAX
MIN
70
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, column address to W low (read-write operation only)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
AWD
CHR
CRP
CSH
CSR
CWD
OED
RAD
RAL
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, CAS low to W low (read-write operation only)
Delay time, OE to data
40
15
15
30
30
20
0
46
18
15
35
35
20
0
50
20
15
40
40
20
0
Delay time, RAS low to column address (see Note 12)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 12)
Delay time, RAS high to CAS low
30
45
35
52
40
60
CAL
RCD
RPC
RSH
RWD
CPW
RASS
RPS
TAA
Delay time, CAS low to RAS high
15
85
60
100
110
35
40
65
18
98
68
100
130
40
45
75
20
110
75
100
150
45
50
85
Delay time, RAS low to W low (read-write operation only)
Delay time, W low after CAS precharge (read-write operation only)
Pulse duration, self-refresh entry from RAS low
Pulse duration, RAS precharge after self refresh
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RAS (test mode)
TCPA
TRAC
’4x6400
64
128
32
64
128
32
64
128
32
’4x6400P
t
Refresh time interval
’4x7400
ms
ns
REF
’4x7400P
128
30
128
30
128
30
t
T
Transition time
3
3
3
NOTE 12: The maximum value is specified only to assure access time.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
V
TH
V
CC
R
R
L
1
2
Output Under Test
Output Under Test
R
C
= 100 pF
L
C
= 100 pF
L
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
(V) (Ω)
DEVICE
’41x400/P
’42x400/P
V
CC
(V)
R
(Ω)
R
(Ω)
V
TH
R
L
1
2
5
828
1178
295
868
1.31
1.4
218
500
3.3
Figure 2. Load Circuits for Timing Parameters
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
CP
t
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Row
Column
Don’t Care
Address
t
t
RRH
RCS
t
CAH
t
RCH
Don’t Care
Don’t Care
W
t
CAC
t
OFF
OH
t
AA
t
Valid Data Out
DQ1–DQ4
Hi-Z
See Note A
t
CLZ
t
OHO
t
RAC
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
t
CAL
RAS
t
RP
t
T
t
RSH
t
RCD
t
CAS
t
CRP
t
CSH
t
CAS
Address
W
ASR
t
CP
t
ASC
t
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
t
CWL
t
t
RAD
RWL
t
WCH
Don’t Care
Don’t Care
t
WCS
t
WP
t
DH
t
DS
Valid Data
Don’t Care
DQ1–DQ4
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CSH
t
t
CAS
ASR
t
CP
t
ASC
t
RAL
CAL
t
t
RAH
t
CAH
Row
Column
Don’t Care
Address
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WP
t
DS
t
DH
Don’t Care
Valid Data
Don’t Care
DQ1–DQ4
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 5. Write-Cycle Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
t
CRP
RCD
t
CAS
t
ASR
t
CP
t
RAH
t
CAH
t
RAD
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWL
t
RWD
t
WP
Don’t Care
Don’t Care
Don’t Care
t
W
AWD
t
CWD
t
CAC
t
DS
t
AA
t
DH
t
CLZ
Data
Out
Data
In
DQ1–DQ4
See Note A
t
RAC
t
t
OEH
OEZ
t
OHO
t
t
OED
OEA
Don’t Care
OE
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RHCP
t
PC
RAS
t
RCD
t
CRP
t
t
t
CSH
RSH
CP
t
CAS
CAS
Address
W
t
RAH
t
CAL
t
t
t
CAH
ASR
t
ASC
RAL
Row
Column
Column
Don’t Care
†
t
t
AA
RRH
t
RCH
t
RCS
†
t
CAC
t
RAD
†
t
CPA
t
CAC
t
AA
t
OFF
t
RAC
t
OH
t
CLZ
Valid
Out
Valid
Out
DQ1–DQ4
See Note A
t
t
OHO
OHO
t
t
OEZ
OEZ
t
OEA
t
OEA
Don’t Care
OE
Access time is t
†
, t
CPA CAC
, or t
dependent.
AA
NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
PC
t
CSH
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
ASR
CAH
Address
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
CWL
t
t
RWL
WP
W
Don’t Care
Don’t Care
Don’t Care
t
DH
DH
t
DS
(see Note A)
t
t
OEH
t
DS
(see Note A)
Valid
In
Valid Data In
OEH
Don’t Care
DQ1–DQ4
OE
t
t
OED
Don’t Care
Don’t Care
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
RHCP
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
CAS
t
ASR
t
ASC
t
RAD
t
CAH
Column
Don’t Care
Row
Column
Address
t
RAH
t
CWL
t
CWD
t
t
AWD
RWD
CPW
t
RWL
t
t
WP
W
t
CPA
t
OEH
t
RCS
t
t
DH
AA
†
t
t
DS
Valid Out
RAC
t
CAC
Valid
In
Valid
In
DQ1–DQ4
t
CLZ
Valid Out
t
OED
t
OEZ
t
OEH
t
OEA
OE
t
OHO
†
Output can go from high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
t
ASR
t
RAH
Row
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Row
Address
W
DQ1–DQ4
OE
Figure 10. RAS-Only Refresh Timing
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WRP
t
WRH
W
Address
OE
Don’t Care
Don’t Care
DQ1–DQ4
Hi-Z
Figure 11. Automatic-CBR-Refresh-Cycle Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
RP
Memory Cycle
t
RP
t
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
Address
t
t
WRH
RRH
t
t
WRH
WRH
t
WRP
t
WRP
t
t
RCS
WRP
W
t
CAC
AA
t
t
OFF
t
RAC
Valid Data Out
DQ1–DQ4
OE
t
CLZ
t
OEZ
t
OEA
Figure 12. Hidden-Refresh-Cycle (Read) Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Row
Col
Address
t
RRH
t
WRH
t
WCS
t
WRP
t
WP
W
t
WCH
t
DH
t
DS
Don’t Care
Valid Data
DQ1–DQ4
OE
Don’t Care
Figure 13. Hidden-Refresh-Cycle (Write) Timing
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RASS
RAS
t
t
RPC
RPS
t
CSR
t
CHS
CAS
t
CP
Address
Don’t Care
t
WRP
t
WRH
W
Don’t Care
OE
Don’t Care
t
OFF
DQ1–DQ4
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
CHR
t
RPC
t
T
t
WTH
t
WTS
Don’t Care
W
Don’t Care
Address
OE
Don’t Care
Hi-Z
DQ1–DQ4
Figure 15. Test-Mode-Entry-Cycle Timing
t
RC
t
RP
t
RAS
RAS
t
CSR
t
RPC
t
CHR
t
T
CAS
t
WRP
W
Don’t Care
Don’t Care
t
WRH
Address
Don’t Care
t
OFF
Hi-Z
Don’t Care
DQ1–DQ4
Figure 16. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
MECHANICAL DATA
DJ (R-PDSO-J24/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
21
19
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
6
8
13
0.032 (0,81)
0.026 (0,66)
0.106 (2,69) TYP
0.008 (0,20) NOM
0.148 (3,76)
0.128 (3,25)
Seating Plane
0.004 (0,10)
0.275 (6,99)
0.260 (6,60)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18)
M
0.050 (1,27)
4040092-3/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
MECHANICAL DATA
DGA (R-PDSO-G24/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.008 (0,21)
M
0.050 (1,27)
26
0.012 (0,30)
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
1
13
0.679 (17,24)
0.671 (17,04)
Gage Plane
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.002 (0,05) MIN
4040265-3/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
device symbolization (TMS416400 illustrated)
TI
-SS
Speed ( -60, - 70, -80)
Low-Power/Self-Refresh Designator (Blank or P)
Package Code
TMS416400 DJ
W
B
Y
M LLLL P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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