TMS418169P-60DGE [TI]
1MX16 EDO DRAM, 60ns, PDSO44, 0.400 INCH, PLASTIC, TSOP-50/44;
| 型号： | TMS418169P-60DGE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1MX16 EDO DRAM, 60ns, PDSO44, 0.400 INCH, PLASTIC, TSOP-50/44 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
DZ PACKAGE
(TOP VIEW)
Organization . . . 1048576 Words by 16 Bits
Single 5-V Power Supply
Performance Ranges:
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
V
SS
CC
ACCESS ACCESS ACCESS READ OR
2
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
TIME
TIME
TIME
EDO
CYCLE
MIN
25 ns
30 ns
35 ns
3
t
t
t
RAC
CAC
AA
4
MAX
’41x169/P-60 60 ns
’41x169/P-70 70 ns
’41x169/P-80 80 ns
MAX
15 ns
18 ns
20 ns
MAX
30 ns
35 ns
40 ns
5
6
V
V
CC
SS
7
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
Extended-Data-Out (EDO) Operation
xCAS-Before-RAS (xCBR) Refresh
RAS-Only Refresh
8
9
10
11
12
13
14
15
16
17
18
19
20
21
– 1024-Cycle Refresh in 16 ms
(TMS418169)
– 4096-Cycle Refresh in 64 ms
(TMS416169)
NC
W
RAS
3-State Unlatched Output
†
A11
A10
A9
A8
A7
A6
A5
A4
High-Reliability Plastic 42-Lead (DZ
Suffix) 400-Mil-Wide Surface-Mount (SOJ)
Package
Operating Free-Air Temperature Range
0°C to 70°C
Texas Instruments Enhanced Performance
†
A0
A1
A2
A3
V
V
SS
CC
Implanted CMOS (EPIC ) Process
†
A10 and A11 are NC for TMS418169.
description
The TMS418169 and the TMS416169 are
high-speed, 16777216-bit dynamic random-ac-
cess memories (DRAMs) organized as 1048576
words of 16 bits each. Both devices employ
state-of-the-art EPIC technology for high perform-
ance, reliability, and low power at low cost.
PIN NOMENCLATURE
A0–A11
DQ0–DQ15
LCAS
UCAS
NC
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
5-V Supply
Ground
OE
RAS
These devices feature maximum RAS access
timesof60ns, 70ns, and80ns. Alladdressesand
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
V
V
W
CC
SS
Write Enable
The TMS416169 and TMS418169 are offered in a 42-lead plastic surface-mount SOJ (DZ suffix) package. The
package is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
†
logic symbol
RAM 1M × 16
17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
20D8/21D0
18
19
20
23
24
25
26
27
28
16
15
0
A
1 048 575
20D15/21D7
20D16
20D17
20D18
20D19
‡
‡
A10
A11
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21
G24
14
31
RAS
LCAS
&
23C22
31
C21
G34
30
&
UCAS
23C32
31
Z31
24,25EN27
13
29
23,21D
W
34,25EN37
25
OE
2
DQ0
A,22D
26,27
A, Z26
3
4
5
7
8
9
10
33
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A,32D
36,37
A, Z36
34
35
36
38
39
40
41
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
†
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the DZ package.
A10 and A11 are NC for TMS418169.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
functional block diagram (TMS416169)
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
8
Column Decode
Sense Amplifiers
32
Column-
Address
Buffers
256K Array
256K Array
256K Array
Data-
In
Reg.
R
o
16
256K Array
A7
32
I/O
Buffers
w
D
e
c
o
d
e
16
16 of 32
Selection
32
32
Data-
Out
Reg.
Row-
Address
Buffers
12
DQ0–DQ15
4
256K Array
12
256K Array
A8–
A11
functional block diagram (TMS418169)
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
32
Column-
Address
Buffers
256K Array
256K Array
256K Array
Data-
In
R
o
16
16
256K Array
A9
32
I/O
Reg.
w
Buffers
D
e
c
o
d
e
16 of 32
Selection
32
32
Data-
Out
Reg.
Row-
Address
Buffers
10
DQ0–DQ15
256K Array
10
256K Array
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
operation
dual CAS
Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins
(DQ0–DQ15), with LCAS corresponding to DQ0–DQ7 and UCAS corresponding to DQ8–DQ15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter t
) is measured from each individual xCAS to its corresponding DQx pin.
CAC
In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time
(see parameter t ) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
CP
Keeping a column address valid while toggling xCAS requires a minimum setup time, t
least one xCAS must be brought low before the other xCAS is taken high.
. During t
, at
CLCH
CLCH
For early-write cycles, the data is latched on the first xCAS falling edge. Data is written only into the DQs
that have the corresponding xCAS low. Each xCAS must meet t minimum in order to ensure writing into
CAS
the storage cell. To latch a new address and new data, all xCAS pins must be high and meet t
.
CP
extended data out
Extended data out (EDO) allows for data-output rates of up to 40 MHz for 60-ns devices. When keeping the
same row address while selecting random column addresses, the time for row-address setup and hold and
address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the
maximum RAS low time (t
).
RASP
EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains
valid for the system to latch the data. After xCAS goes high, the DRAM is decoding the next address. OE and
W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation
benefit.
address: A0–A11 (TMS416169) and A0–A9 (TMS418169)
Twenty address bits are required to decode one of the 1048576 storage cell locations. For the TMS416169,
12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits
are set up on A0 through A7 and latched on the chip by the first xCAS. For the TMS418169, 10 row-address
bits are set up on A0–A9 and latched on the chip by RAS. Ten column-address bits are set up on A0–A9 and
latched on the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and
xCAS. RAS is similar to a chip-enable in that it activates the sense amplifiers as well as the row decoder. xCAS
is used as a chip-select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation
independent of the state of OE. This permits early-write operation to be completed with OE grounded. If W goes
low in an extended-data-out read cycle, the DQs go into the high-impedance state as long as xCAS is high.
data in (DQ0–DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
data in (DQ0–DQ15) (continued)
delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0–DQ15)
Data out is the same polarity as data-in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t
(which begins with
CAC
the negative transition of xCAS) as long as t
and t are satisfied.
RAC
AA
output enable (OE)
OEcontrolstheimpedanceoftheoutputbuffers. WhilexCASandRASarelowandWishigh, OEcanbebrought
low or high and the DQs switch from valid data to high impedance. There are two methods for placing the DQs
into the high-impedance state and keeping them in that state during xCAS high time using OE. The first method
is to switch OE high before xCAS goes high and keep OE high for t
past the CAS transition. This disables
CHO
the DQs and they remain in the high-impedance state, regardless of OE, until xCAS falls again. The second
method is to have OE low as xCAS transitions high. Then OE can pulse high for a minimum of t anytime
OEP
during CAS high time disabling the DQs regardless of further transitions on OE until CAS falls again.
RAS-only refresh
TMS416169
A refresh operation must be performed at least once every 64 ms to retain data. This is achieved by strobing
each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.
A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
TMS418169
A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing
each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the
output buffers remain in the high-impedance state. Externally generated addresses must be used for a
RAS-only refresh.
hidden refresh
Hiddenrefreshcanbeperformedwhilemaintainingvaliddataattheoutputpins. Thisisaccomplishedbyholding
xCAS at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
IL
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is achieved by bringing at least one xCAS low earlier than RAS (see parameter t
) and holding
CSR
it low after RAS falls (see parameter t
). For successive xCBR refresh cycles, xCAS can remain low while
CHR
cycling RAS. The external address is ignored and the refresh address is generated internally.
power-up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power-up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or xCBR) cycle.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
’41x169
UNIT
MIN NOM
MAX
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
TMS416169
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’416169-60
’416169-70
’416169-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output voltage
Input current (leakage)
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All other inputs = 0 V to V
I
I
± 10
± 10
± 10
µA
CC
V
= 5.5 V,
V
= 0 V to V
,
CC
CC
xCAS high
O
I
I
Output current (leakage)
± 10
± 10
± 10
µA
O
‡§
Read- or write-cycle current
V
V
= 5.5 V,
Minimum cycle
90
80
70
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and xCAS high
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and xCAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh current
(RAS-only refresh or CBR)
§
I
I
90
80
90
70
80
mA
mA
CC3
xCAS high (RAS only),
RAS low after xCAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
HPC
xCAS cycling
‡¶
Average EDO current
100
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change while xCAS = V
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
TMS418169
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
’418169-60
’418169-70
’418169-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
190
0.4
± 10
± 10
180
0.4
± 10
± 10
170
OL
OL
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All other inputs = 0 V to V
I
I
I
Input current (leakage)
µA
µA
mA
I
CC
V
= 5.5 V,
CC
xCAS high
V
= 0 V to V
,
CC
Output current
(leakage)
O
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
After 1 memory cycle,
RAS and xCAS high
IH
2
1
2
1
2
1
mA
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After 1 memory cycle,
RAS and xCAS high
V
= 5.5 V,
Minimum cycle,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
= 5.5 V, = MIN,
Average refresh
current (RAS-only
refresh or CBR)
CC
RAS cycling,
§
I
I
190
100
180
90
170
80
mA
mA
CC3
V
t
CC
RAS low,
HPC
xCAS cycling
‡¶
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change while xCAS = V
IH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
†
C
C
C
C
C
Input capacitance, A0–A11
5
7
7
7
7
i(A)
Input capacitance, OE
pF
i(OE)
i(RC)
i(W)
O
Input capacitance, xCAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
†
A10 and A11 are NC for TMS418169.
NOTE 3:
V
CC
= 5 V ± 0.5 V or 3.3 V ± 0.3 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x169-60
’41x169-70
’41x169-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
Access time from column address
30
15
35
60
15
35
18
40
70
18
40
20
45
80
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Access time from CAS
CAC
CPA
RAC
OEA
CLZ
OEZ
REZ
CEZ
WEZ
Access time from CAS precharge
Access time from RAS
Access time from OE
Delay time, CAS to output in the low-impedance state
Output buffer turn off delay from OE (see Note 5)
Output buffer turn off delay from RAS (see Note 5)
Output buffer turn off delay from CAS (see Note 5)
Output buffer turn off delay from W (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
15
15
15
15
18
18
18
18
20
20
20
20
NOTES: 4. With ac parameters, it is assumed t = 5 ns.
T
5. Maximum t
, t
, t
, and t
are specified when the output is no longer driven.
OEZ
REZ CEZ WEZ
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x169-60
’41x169-70
’41x169-80
UNIT
MIN
25
80
50
10
3
MAX
MIN
30
90
55
10
3
MAX
MIN
35
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page-mode read or write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
OCH
CP
100
60
Delay time, RAS active to CAS precharge
Hold time, OE from CAS
10
Hold time, output from CAS active
Pulse duration, CAS active
3
10 10000
12 10000
15 10000
Pulse duration, W (output disable only)
Setup time, OE before CAS
5
10
5
5
10
5
5
10
5
Pulse duration, CAS precharge
Precharge time, OE (output disable only)
5
5
5
OEP
NOTE 4: With ac parameters, it is assumed t = 5 ns.
T
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x169-60
’41x169-70
’41x169-80
UNIT
MIN
110
110
150
MAX
MIN
130
130
175
MAX
MIN
150
150
200
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write
WC
Cycle time, read-write
RWC
RASP
RAS
RP
Pulse duration, RAS active, page mode (see Note 6)
Pulse duration, RAS active, nonpage mode (see Note 6)
Pulse duration, RAS precharge
Pulse duration, write command
Setup time, column address
60 100 000
70 100 000
80 100 000
60
40
10
0
10 000
70
50
10
0
10 000
80
60
10
0
10 000
WP
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data in (see Note 7)
Setup time, read command
0
0
0
0
0
0
RCS
CWL
RWL
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
10
10
12
12
15
15
Setup time, write command before CAS active (early-write
only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, CAS referenced to RAS (CBR refresh only)
Hold time, column address
5
10
10
10
0
5
12
12
10
0
5
15
15
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSR
CAH
DH
Hold time, data in (see Note 7)
Hold time, row address
RAH
RCH
RRH
WCH
CLCH
RHCP
OEH
ROH
CHR
Hold time, read command referenced to CAS (see Note 8)
Hold time, read command referenced to RAS (see Note 8)
Hold time, write command during CAS active (early-write only)
Hold time, CAS low to CAS high
0
0
0
10
5
12
5
15
5
Hold time, RAS active from CAS precharge
Hold time, OE command
35
15
10
10
40
18
10
10
45
20
10
10
Hold time, RAS referenced to OE
Hold time, CAS referenced to RAS (CBR refresh only)
Delay time, column address to write command
(read-write only)
t
55
63
70
ns
AWD
t
t
t
t
t
t
t
Delay time, CAS precharge to RAS
5
40
15
15
30
20
20
5
46
18
15
35
25
20
5
50
20
15
40
30
20
ns
ns
ns
ns
ns
ns
ns
CRP
CWD
OED
RAD
RAL
CAL
RCD
Delay time, CAS to write command (read-write only)
Delay time, OE to data in
Delay time, RAS to column address (see Note 9)
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 9)
30
45
35
52
40
60
NOTES: 4. With ac parameters, it is assumed t = 5 ns.
T
RWL
6. In a read-write cycle, t
and t must be observed.
RWD
7. Referenced to the later of xCAS or W in write operations
8. Either t or t must be satisfied for a read cycle.
RRH
RCH
9. The maximum value is specified only to ensure access time.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’41x169-60
’41x169-70
’41x169-80
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
t
t
t
t
Delay time, RAS precharge to CAS
ns
ns
ns
ns
ms
ms
ns
RPC
RSH
RWD
CPW
Delay time, CAS active to RAS precharge
10
85
60
12
98
68
15
Delay time, RAS to write command (read-write only)
Delay time, CAS precharge to write command (read-write only)
110
75
’416169
’418169
64
16
30
64
16
30
64
16
30
t
Refresh time interval
Transition time
REF
T
t
2
2
2
PARAMETER MEASUREMENT INFORMATION
1.31 V
5 V
218 Ω
828 Ω
Output Under Test
Output Under Test
295 Ω
C
= 100 pF
L
C
= 100 pF
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
L
Figure 1. Load Circuits for Timing Parameters
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
T
t
t
RP
t
RCD
t
CAS
UCAS
t
CLCH
(see Note A)
CP
t
CRP
LCAS
t
CSH
t
RSH
t
RAD
t
RAH
t
ASC
t
CAL
t
ASR
t
RAL
Row
Column
Don’t Care
Address
t
RRH
t
CAH
t
RCH
t
RCS
t
CAC
Don’t Care
Don’t Care
W
(see Note B)
t
AA
t
REZ
t
CLZ
Valid Data Out
DQ0–DQ15
See Note C
t
RAC
t
OEZ
t
ROH
Don’t Care
Don’t Care
t
OE
OEA
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B.
t
is measured from xCAS to its corresponding DQx.
CAC
C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
D. xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
CAS
t
T
t
RP
t
RCD
t
UCAS
t
CLCH
(see Note A)
t
CP
LCAS
t
ASR
t
CRP
t
CSH
t
RSH
t
RAH
t
ASC
t
CAL
t
RAL
Address
Row
Column
Don’t Care
t
CAH
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WP
t
DH
(see Note B)
Valid Data In
(see Note B)
Don’t Care
Don’t Care
DQ0–DQ15
t
DS
t
OED
t
OEH
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
B. Referenced to the first xCAS or W, whichever occurs last
C. xCAS order is arbitrary.
must be met.
CLCH
Figure 3. Write-Cycle Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
t
T
t
RP
t
RCD
t
CSH
t
CRP
t
CAS
UCAS
t
RSH
t
CLCH
(see Note A)
LCAS
t
RAD
t
CP
t
ASR
t
RAH
t
ASC
t
CAL
t
RAL
Column
Address
Row
Don’t Care
t
CAH
t
WCS
t
WCH
W
t
CWL
t
RWL
t
WP
Don’t Care
DQ0–DQ15
Don’t Care
Valid Data In
t
DH
t
DS
OE
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
B. xCAS order is arbitrary.
must be met.
CLCH
Figure 4. Early-Write-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
t
RP
t
T
t
RCD
t
CAS
UCAS
t
CSH
t
CRP
t
CLCH
(see Note A)
t
CP
t
RSH
t
LCAS
RAD
t
RAH
t
ASC
t
ASR
Column
Address
Row
Don’t Care
t
t
CWL
CAH
t
AWD
t
RWL
t
CWD
t
RCS
t
WP
W
Don’t Care
Don’t Care
t
RWD
t
CLZ
See Note B
DQ8–DQ15
Valid Out
Don’t Care
DH
t
AA
t
t
CAC
(see Note C)
t
DS
t
t
OEZ
RAC
t
OEA
OE
Don’t Care
t
OED
t
CAC
See Note B
Don’t Care
DQ0–DQ7
Valid Out
Valid In
must be met.
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. is measured from xCAS to its corresponding DQx.
D. xCAS order is arbitrary.
t
CAC
Figure 5. Read-Modify-Write-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
t
RCD
t
CRP
UCAS
t
RHCP
t
RSH
t
CLCH
(see Note A)
t
HPC
t
CSH
t
CAS
t
CP
t
LCAS
ASR
t
RAH
t
CAL
t
ASC
t
RAL
t
CAH
Column
#1
Address
W
Row
RAD
Don’t Care
Column #2
Don’t Care
t
RRH
t
t
RCH
Don’t
Care
Don’t Care
t
CAC
(see Note B)
t
AA
t
CPA
(see Note C)
t
RCS
t
REZ
t
RAC
t
DOH
t
CLZ
DQ8–DQ15
(See Note D)
Data #1
t
AA
DQ0–DQ7
Data #1
Data #2
(See Note D)
t
OEZ
t
OEA
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B.
t
is measured from xCAS to its corresponding DQx.
CAC
C. Access time is t
or t
dependent.
AA
CPA
D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 6. Extended-Data-Out Read-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
xCAS
Addr
t
CSH
t
HPC
t
CP
t
CAS
t
RSH
t
ASR
t
RAH
t
t
CAL
ASC
t
CAH
t
RAL
Row
Column #1
Column #2
Column #3
t
t
RAD
OCH
t
t
CHO
OEP
t
OEP
OE
t
OEA
t
RRH
t
RCS
t
RCH
t
OEA
t
CAC
W
t
t
DOH
AA
t
CLZ
t
OEZ
t
CAC
t
t
CEZ
CPA
t
AA
t
REZ
t
OEZ
t
t
RAC
CAC
t
AA
DATA #1
DATA #1
DATA #2
DATA #3
DQ
Figure 7. Extended-Data-Out Read-Cycle Timing With OE Control
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
t
RP
t
CSH
t
CRP
t
HPC
t
RSH
t
CP
t
CAS
xCAS
t
ASR
t
RAH
t
CAH
t
t
CAL
ASC
t
RAL
Column #3
Row
Column #1
Column #2
Addr
OE
t
RAD
t
OEA
t
CAC
t
RCS
t
CAC
t
WPE
t
RCH
t
RRH
W
t
DOH
t
CAC
t
WEZ
t
CPA
t
CEZ
t
AA
t
CPA
t
t
AA
t
CLZ
AA
t
RAC
DATA #1
DATA #2
DATA #3
DQ
Figure 8. Extended-Data-Out Read-Cycle Timing With W Control
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RAS
RASP
t
RSH
UCAS
t
RHCP
t
CLCH
t
HPC
t
(see Note A)
RCD
t
t
CP
CRP
t
CSH
t
LCAS
CAS
t
ASR
t
CAH
t
ASC
t
CAL
t
RAH
t
RAL
Address
Row
RAD
Column
Don’t Care
Column
Don’t Care
t
CWL
t
t
CWL
t
WP
t
RWL
t
DS
t
DS
W
Don’t Care
Don’t Care
Don’t Care
t
DH
DQ8–
DQ15
Valid In
Don’t Care
t
DH
DQ0–
DQ7
Valid In
Valid In
Don’t Care
t
OED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing
specifications are not violated.
C. xCAS order is arbitrary.
Figure 9. Extended-Data-Out Write-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RAS
RASP
t
RSH
UCAS
t
RHCP
t
CLCH
t
HPC
t
(see Note A)
RCD
t
t
CP
CRP
t
CSH
t
LCAS
CAS
t
ASR
t
CAH
t
ASC
t
CAL
t
RAH
t
RAL
Address
Row
RAD
Column
Don’t Care
Column
Don’t Care
t
t
CWL
t
CWL
t
t
WCS
RWL
t
DS
t
WCH
W
Don’t Care
Don’t Care
Don’t Care
DQ8–
DQ15
Valid In
Don’t Care
t
DH
DQ0–
DQ7
Valid In
Valid In
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing
specifications are not violated.
C. xCAS order is arbitrary.
Figure 10. Extended-Data-Out Early Write-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
UCAS
LCAS
t
CSH
t
RSH
t
RCD
t
CRP
t
PRWC
t
CAS
t
CP
t
CLCH
(see Note A)
t
ASR
ASC
t
t
t
CAH
RAD
Address
Row
Column
Column
t
t
CWD
t
RAH
CWL
t
WP
t
AWD
t
t
RWL
CPW
t
RWD
W
t
CAC
t
AA
t
RCS
t
OEH
t
t
DS
CPA
t
AA
(see Note B)
t
RAC
CLZ
t
DH
Valid Out
(see Note C)
t
Valid In
Valid In
DQ0–DQ15
Valid Out
t
OEH
t
OEA
t
OEZ
t
OED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B. Access time is t
- or t -dependent.
CPA AA
C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
D. xCAS order is arbitrary.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F.
t
is measured from xCAS to its corresponding DQx.
CAC
Figure 11. Extended-Data-Out Read-Modify-Write-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
xCAS
t
RP
t
CRP
t
RPC
t
T
See Note A
Don’t Care
t
ASR
t
RAH
Don’t Care
Row
Don’t Care
Row
Address
Don’t Care
W
Hi-Z
DQ0–DQ15
Don’t Care
OE
NOTE G: All xCAS must be high.
Figure 12. RAS-Only Refresh-Cycle Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
t
t
RP
RAS
t
RAS
RAS
t
t
RP
CHR
t
CAS
xCAS
t
ASR
RAH
t
t
ASC
t
CAH
Address
W
Row Col
Don’t Care
t
RRH
t
RCS
Don’t Care
t
t
CAC
AA
t
REZ
t
t
CEZ
RAC
DQ0–DQ15
OE
Valid Data
t
OEZ
t
OEA
Figure 13. Hidden-Refresh-Cycle Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
t
CSR
t
t
CHR
RPC
t
T
xCAS
Don’t Care
Don’t Care
Don’t Care
W
Address
OE
DQ0–DQ15
Hi-Z
NOTE A: Any xCAS can be used.
Figure 14. Automatic (xCBR) Refresh-Cycle Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416169, TMS418169
1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C – MAY1995–REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J42)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
1.080 (27,43)
1.070 (27,18)
42
22
0.445 (11,30)
0.435 (11,05)
0,405 (10,29)
0.395 (10,03)
1
21
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.020 (0,51)
0.016 (0,41)
0.380 (9,65)
0.360 (9,14)
0.007 (0,18)
M
0.008 (0,20) NOM
0.050 (1,27)
4040094-6/C 4/95
NOTES: B. All linear dimensions are in inches (millimeters).
C. This drawing is subject to change without notice.
D. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416169 illustrated)
TI
-SS
Speed ( -60, - 70, -80)
Package Code
TMS416169 DZ
W
B
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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