TMS427809A-60DGCR [TI]
IC,DRAM,EDO,2MX8,CMOS,TSOP,28PIN,PLASTIC;
| 型号： | TMS427809A-60DGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,DRAM,EDO,2MX8,CMOS,TSOP,28PIN,PLASTIC 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总29页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
DZ/DGC PACKAGE
(TOP VIEW)
This data sheet is applicable to all
TMS417809As and TMS427809A/Ps
symbolized by Revision “E” and subsequent
revisions as described in the device
symbolization section.
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
V
SS
CC
2
DQ0
DQ1
DQ2
DQ3
W
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
3
Organization . . . 2097152 by 8 Bits
Single Power Supply (5 V or 3.3 V)
Performance Ranges:
4
5
6
ACCESS ACCESS ACCESS
EDO
7
RAS
NC
TIME
TIME
TIME
CYCLE
t
t
t
t
8
RAC
CAC
AA
HPC
MAX
50 ns
60 ns
70 ns
50 ns
60 ns
70 ns
MAX
13 ns
15 ns
18 ns
13 ns
15 ns
18 ns
MAX
25 ns
30 ns
35 ns
25 ns
30 ns
35 ns
MIN
9
A10
A0
A8
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
20 ns
25 ns
30 ns
20 ns
25 ns
30 ns
10
11
12
13
14
A7
A1
A6
A2
A5
A3
A4
V
V
SS
CC
Extended-Data-Out (EDO) Operation
CAS-Before-RAS (CBR) Refresh
PIN NOMENCLATURE
Long Refresh Period and Self-Refresh
Option (TMS427809AP)
A[0:10]
DQ[0:7]
CAS
Address Inputs
Data In/Data Out
Column-Address Strobe
No Internal Connection
Output Enable
High-Impedance State Unlatched Output
High-Reliability Plastic 28-Lead
NC
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DZ Suffix) and
28-Lead 400-Mil-Wide Surface-Mount Thin
Small-Outline Package (TSOP) (DGC Suffix)
OE
RAS
Row-Address Strobe
3.3-V or 5-V Supply
Ground
V
V
CC
SS
W
Write Enable
Ambient Temperature Range
0°C to 70°C
description
AVAILABLE OPTIONS
POWER
SUPPLY
REFRESH
CYCLES
The TMS417809A and TMS427809A series are
16777216-bit dynamic random access memory
(DRAM) devices organized as 2097152 words of
8 bits each. The TMS427809AP series is a
low-power, self-refresh, 16777216-bit DRAM
organized as 4194304 words of four bits.They
employ TI state-of-the-art technology for high
performance, reliability, and low power.
DEVICE
TMS417809A
TMS427809A
TMS427809AP
5 V
2048 in 32 ms
2048 in 32 ms
2048 in 128 ms
3.3 V
3.3 V
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS417809A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). The TMS427809A/P
is offered in a 28-lead plastic surface-mount TSOP package (DGC suffix). These packages are designed for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
†
logic symbol (TMS417809A and TMS427809A/P)
RAM 2M x 8
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
20D10/21D0
11
12
13
16
17
18
19
20
21
9
0
A
2 097 151
20D19/21D9
20D20
C20[ROW]
G23/[REFRESH ROW]
7
RAS
24[PWR DWN]
C21[COL]
G24
23
6
CAS
W
&
23C22
24,25EN
23,21D
G25
22
2
OE
DQ0
A,22D
26
A,Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
4
5
24
25
26
27
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
functional block diagram (TMS417809A and TMS427809A/P)
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
8
Column-
Address
Buffers
256K Array
256K Array
256K Array
256K Array
Data-
In
Reg.
R
o
8
A9
8
w
I/O
Buffers
D
e
c
o
d
e
8
32
32
Data-
Out
Reg.
Row-
Address
Buffers
11
DQ0–DQ7
A10
256K Array
11
256K Array
operation
extended data out
Extended data out (EDO) allows data output rates up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup-and-hold and for
address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by
t
, the maximum RAS low time.
RASP
The EDO does not place the data-in/data-out pins (DQ pins) in the high-impedance state with the rising edge
of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the
next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO
operation benefits.
address: A0–A10
Twenty-one address bits are required to decode each of the 2097152 storage-cell locations. Eleven
row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Ten column-address
bits are set up on A0 through A9. All addresses must be stable on or before the falling edge of RAS and CAS.
RASis similar to a chip-enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip-select, activating the output buffers and latching the address bits into the column-address buffers.
output-enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods of placing the DQs into the high-impedance state and maintaining that state during CAShigh time. The
first method is to transition OE high before CAS transitions high and keep OE high for t
(hold time, OE from
CHO
CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls
again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum
of t
(precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions
OEP
on OE until CAS falls again (see Figure 8).
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
write-enable (W)
The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled as long as CAS is high
(see Figure 8).
data in/data out (DQ0–DQ7)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the latter of the
falling edges of CAS or W strobes data into the on-chip data latch with setup-and-hold times referenced to the
latter edge. The DQs drive valid data after all access times are met and the data remains valid except in cases
described in the W and OE descriptions.
RAS-only refresh
A refresh operation must be performed once every 32 ms (128 ms for TMS427809AP) to retain data. This can
be achieved by strobing each of the 2048 rows (A0–A10). A normal read- or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a
IL
RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter t
) and holding it low after
CSR
RAS falls (see parameter t
). For successive CBR-refresh cycles, CAS can remain low while cycling RAS.
CHR
The external address is ignored and the refresh address is generated internally.
battery-backup refresh
TMS427809AP
A low-power battery-backup refresh mode that requires less than 350 A of refresh current is available on the
TMS427809AP. Data integrity is maintained using CBR refresh with a period of 62.5 s while holding RAS low
for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(V < 0.2 V, V > V – 0.2 V).
IL
IH
CC
self-refresh (TMS427809AP)
The self-refresh mode is entered by dropping CAS low prior to RAS going low, then CAS and RAS are both held
low for a minimum of 100 s. The chip is refreshed internally by an on-board oscillator. No external address is
required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy t
. Upon exiting self-refresh mode, a burst refresh (refreshes a full set
CHS
of row addresses) must be executed before continuing with normal operation to ensure that the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or CBR) cycle.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(TMS417809A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
(TMS427809A, TMS427809AP) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
CC
Voltage range on any pin (TMS417809A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (TMS427809A, TMS427809AP) (see Note 1) . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS417809A
MIN NOM MAX
TMS427809A/P
MIN NOM MAX
3.6
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
3
3.3
0
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
2.4
– 1
0
6.5
0.8
70
2
– 0.3
0
V
+ 0.3
CC
‡
Low-level input voltage
Ambient temperature
0.8
70
IL
°C
A
‡
The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TMS417809A
’417809A-50 ’417809A-60 ’417809A-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
Input current (leakage)
Output current (leakage)
± 10
± 10
± 10
µA
CC
V
= 5.5 V,
CC
CAS high
V
O
= 0 V to V ,
CC
I
O
± 10
± 10
± 10
µA
Average read- or
write-cycle current
‡§
I
V
V
= 5.5 V,
Minimum cycle
130
110
100
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
2
1
2
1
2
1
I
Average standby current
mA
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh current
(RAS-only refresh or CBR)
‡§
‡¶
I
I
130
110
110
90
100
80
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
HPC
CAS cycling
Average EDO current
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient conditions
(unless otherwise noted) (continued)
TMS427809A/P
’427809A/P-50
’427809A/P-60
’427809A/P-70
†
PARAMETER
UNIT
TEST CONDITIONS
= – 2 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
CC
–0.2
V
CC
–0.2
V
CC
–0.2
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
CC
Output
current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
CC
CC
CAS high
O
O
Average
read- or
write-cycle
current
‡§
I
V
= 3.6 V,
CC
Minimum cycle
120
100
90
mA
mA
CC1
V
IH
= 2 V (LVTTL)
’427809A
2
1
2
1
2
1
After one memory cycle,
RAS and CAS high
’427809AP
Average
standby
current
I
CC2
V
= V
– 0.2 V
CC
IH
(LVCMOS),
’427809A
1
1
1
mA
After one memory cycle,
RAS and CAS high
’427809AP
150
150
150
µA
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
‡§
I
120
100
90
mA
CC3
(RAS-only
refresh
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
or CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
CC
HPC
I
I
110
200
90
80
mA
CC4
EDO current
RAS low,
CAS cycling
Average
self-refresh
current
CAS < 0.2 V,
Measured after t
RAS < 0.2 V,
#
200
200
µA
CC6
min
RASS
Battery
back-up
operating
current
(equivalent
refresh time
is 128 ms),
CBR only
t
V
= 62.5 µs,
t
≤ 300 ns
RC
RAS
– 0.2 V ≤ V ≤ 3.9 V,
CC
IH
#
I
350
350
350
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
For TMS427809AP only
HPC
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
C
Input capacitance, A0–A10
Input capacitance, OE
5
7
7
7
7
i(A)
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, CAS and RAS
Input capacitance, W
pF
pF
†
Output capacitance
pF
†
CAS and OE = V to disable outputs
IH
= NOM supply voltage ±10%, and the bias on pins under test is 0 V.
NOTE 2:
V
CC
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
PARAMETER
UNIT
MIN
MAX
25
MIN
MAX
30
MIN
MAX
35
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CAS (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
13
15
18
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CAS precharge (see Note 4)
Access time from RAS (see Note 4)
28
35
40
50
60
70
Access time from OE (see Note 4)
13
15
18
Delay time, CAS to output in low impedance
Output buffer turn-off delay from RAS (see Note 5)
Output buffer turn-off delay from CAS (see Note 5)
Output buffer turn-off delay from OE (see Note 5)
Output buffer turn-off delay from W (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
13
13
13
13
15
15
15
15
18
18
18
18
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
4. For TMS427809A/P, access times are measured with output reference levels of V
= 2 V and V
OL
= 0.8 V.
OH
5. Themaximumvaluesoft
,t
,t
,andt
REZ CEZ OEZ
arespecifiedwhentheoutputisnolongerdriven.Data-inshouldnotbeenabled
WEZ
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
UNIT
MIN
20
57
40
7
MAX
MIN
25
68
48
10
5
MAX
MIN
30
78
58
10
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
CP
Delay time, RAS active to CAS precharge
Hold time, OE from CAS
Hold time, output from CAS
5
Pulse duration, CAS active (see Note 6)
Pulse duration, W active (output disable only)
Pulse duration, CAS precharge
Setup time, OE before CAS
8
10000
10
7
10000
12
7
10000
7
8
10
10
5
10
10
5
8
OCH
OEP
Precharge time, OE
5
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
6. In a read-write cycle, t
CWD
and t must be observed.
CWL
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
ac timing requirements (see Note 3)
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
UNIT
MIN
84
MAX
MIN
104
135
MAX
MIN
124
160
70
70
50
10
100
130
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
ns
ns
ns
ns
ns
ns
s
RC
Cycle time, read-write
111
RWC
RASP
RAS
RP
Pulse duration, RAS active, fast page mode (see Note 7)
Pulse duration, RAS active, non-page mode (see Note 7)
Pulse duration, RAS precharge
50 100 000
60 100 000
100 000
10 000
50
30
8
10 000
60
40
10
100
110
0
10 000
Pulse duration, write command
WP
Pulse duration, RAS active, self refresh (see Note 8)
Pulse duration, RAS precharge after self refresh
Setup time, column address
100
90
0
RASS
RPS
ASC
ASR
DS
ns
ns
ns
ns
ns
ns
ns
Setup time, row address
0
0
0
Setup time, data in (see Note 9)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CAS precharge
Setup time, write command before RAS precharge
8
10
10
12
12
8
Setup time, write command before CAS active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
Setup time, W high before RAS low (CBR refresh only)
Setup time, CAS referenced to RAS (CBR refresh only)
Hold time, column address
10
5
10
5
10
5
ns
ns
ns
ns
ns
ns
ns
WRP
CSR
CAH
DH
8
10
10
10
0
12
12
10
0
Hold time, data in (see Note 9)
8
Hold time, row address
8
RAH
RCH
RRH
Hold time, read command referenced to CAS (see Note 10)
Hold time, read command referenced to RAS (see Note 10)
0
0
0
0
Hold time, write command during CAS active
(early-write only)
t
8
10
12
ns
WCH
t
t
t
t
t
t
Hold time, RAS referenced to OE
8
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ROH
WRH
CHR
OEH
RHCP
CHS
Hold time, W high after RAS low (CBR refresh only)
Hold time, CAS referenced to RAS (CBR refresh only)
Hold time, OE command
10
10
10
13
15
18
Hold time, RAS active from CAS precharge
Hold time, CAS referenced to RAS (self refresh only)
28
35
40
– 50
– 50
– 50
Delay time, column address to write command
(read-write only)
t
42
5
49
5
57
5
ns
ns
AWD
t
Delay time, CAS precharge to RAS
CRP
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
7. In a read-write cycle, t
RWD
and t
must be observed.
≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
RWL
8. During the period of 10 µs ≤ t
RASS
9. Referenced to the later of CAS or W in write operations
10. Either t or t must be satisfied for a read cycle.
RRH
RCH
9
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ac timing requirements (see Note 3) (continued)
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
UNIT
MIN
30
13
10
25
18
12
5
MAX
MIN
34
15
12
30
20
14
5
MAX
MIN
40
18
12
35
25
14
5
MAX
t
t
t
t
t
t
t
t
t
Delay time, CAS to write command (read-write only)
Delay time, OE to data in
ns
ns
ns
ns
ns
ns
ns
ns
ns
CWD
OED
RAD
RAL
Delay time, RAS to column address (see Note 11)
Delay time, column address to RAS precharge
Delay time, column address to CAS precharge
Delay time, RAS to CAS (see Note 11)
25
30
35
CAL
37
45
52
RCD
RPC
RSH
RWD
Delay time, RAS precharge to CAS
Delay time, CAS active to RAS precharge
Delay time, RAS to write command (read-write only)
8
10
79
12
92
67
Delay time, CAS precharge to write command
(read-write only)
t
45
54
62
ns
CPW
’417809A
32
32
32
32
32
32
t
t
Refresh time interval
Transition time
’427809A
ms
ns
REF
’427809AP
128
30
128
30
128
30
2
2
2
T
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
11. The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
V
TH
V
CC
R
R
R
L
1
2
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
L
DEVICE
’417809A
’427809A/P
V
(V)
R
( )
R
( )
V
(V)
R ( )
L
CC
1
2
TH
5
828
295
868
1.31
1.4
218
500
3.3
1178
Figure 1. Load Circuits for Timing Parameters
10
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
CAS
ASR
t
t
CP
RAD
t
ASC
t
RAH
t
CAL
t
RAL
Don’t Care
Row
Column
Address
t
RCS
t
t
RRH
RCH
t
CAH
Don’t Care
Don’t Care
W
t
CAC
t
CEZ
REZ
t
t
AA
Valid Data Out
Hi-Z
DQ0–DQ7
See Note A
CLZ
t
t
WEZ
t
RAC
t
WPE
t
OEA
t
OEZ
t
ROH
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
11
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CSH
t
t
CAS
ASR
t
CP
t
ASC
t
t
CAL
RAL
t
RAH
t
CAH
Row
Column
Don’t Care
Address
t
CWL
t
RAD
t
RWL
t
WCH
t
WCS
Don’t Care
Don’t Care
W
t
DH
t
DS
Don’t Care
Valid Data
DQ0–DQ7
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
12
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
T
t
RSH
t
RCD
t
CRP
t
CAS
t
CSH
t
CAS
ASR
t
t
CP
ASC
t
RAL
t
t
RAH
CAL
t
CAH
Don’t Care
Row
Column
Address
t
CWL
t
RAD
t
DS
t
RWL
Don’t Care
Don’t Care
Don’t Care
W
t
WP
t
CLZ
t
DH
Valid Data In
DQ0–DQ7
Invalid Data Out
t
OED
t
OEH
Don’t Care
Don’t Care
OE
Figure 4. Write-Cycle Timing
13
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PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
RP
t
T
t
t
CRP
RCD
t
CAS
t
ASR
t
t
CP
RAH
t
CAH
t
RAD
t
T
t
ASC
Row
Column
Don’t Care
Address
t
t
CWL
RCS
t
RWL
t
RWD
t
WP
Don’t Care
W
t
AWD
t
CWD
t
CAC
t
DS
t
AA
t
t
DH
CLZ
Data
Out
Data
In
Don’t Care
Hi-Z
DQ0–DQ7
See Note A
t
RAC
t
OEZ
t
OEA
t
OEH
t
OED
Don’t Care
Don’t Care
OE
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
14
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PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
t
RP
t
RHCP
t
T
t
t
RSH
RCD
t
CSH
t
t
CRP
HPC
t
CAS
t
CAS
t
CP
CAS
t
RAH
t
ASC
t
CAL
t
CAL
t
ASR
t
RAL
t
CAH
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
RCH
t
OEA
OE
t
RCS
t
CAC
t
RRH
t
DOH
W
t
CAC
t
AA
t
t
CEZ
AA
(see Note C)
t
CPA
t
RAC
t
REZ
t
CLZ
Data #1
Data #2
Data #3
DQ0–DQ7
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is t -, t -, or t -dependent.
CPA AA
C. Output is turned off by t
CAC
if RAS goes high during CAS low.
CEZ
Figure 6. EDO Read Cycle
15
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PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
CSH
RHCP
t
HPC
t
CP
t
t
CAS
t
CAS
RSH
t
ASR
t
CAL
t
RAH
t
CAL
t
ASC
t
RAL
t
CAH
Row
Column #1
Column #2
Column #3
Address
t
RAD
t
OCH
t
CHO
t
OEP
OE
t
OEA
t
RRH
t
RCS
t
RCH
t
OEA
t
CAC
W
t
DOH
t
CLZ
t
OEZ
t
CAC
t
t
CEZ
CPA
t
AA
t
REZ
t
OEZ
(see Note A)
t
RAC
t
AA
Data #1
if RAS goes high during CAS low.
Data #1
Data #2
Data #3
DQ0–DQ7
NOTE A: Output is turned off by t
CEZ
Figure 7. EDO Read-Cycle With OE Control
16
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PARAMETER MEASUREMENT INFORMATION
t
RASP
RAS
CAS
t
RP
t
t
CSH
RHCP
t
CRP
t
t
HPC
RSH
t
CP
t
CAS
t
ASR
t
RAH
t
CAH
t
CAL
t
ASC
t
RAL
Column #3
Row
Column #1
Column #2
Address
OE
t
RAD
t
OEA
t
CAC
t
RCS
t
CAC
t
WPE
t
RCH
t
RRH
W
t
DOH
t
CAC
t
WEZ
t
CPA
t
CEZ
t
AA
t
CPA
t
AA
t
AA
t
CLZ
t
REZ
t
RAC
Data #1
Data #2
Data #3
DQ0–DQ7
Figure 8. EDO Read-Cycle With W Control
17
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PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
RHCP
t
HPC
t
t
CSH
CRP
t
RCD
t
RSH
t
CAS
t
ASC
t
CP
t
RAH
t
CAL
t
t
RAL
CAH
t
t
ASR
CAL
Row
Column
Column
Don’t Care
Address
t
CWL
t
CWL
t
RAD
t
WCH
t
RWL
t
WCS
Don’t Care
Don’t Care
Don’t Care
W
t
DH
t
DS
Data In
Data In
DQ0–DQ7
OE
Don’t Care
Don’t Care
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 9. EDO-Early-Write-Cycle Timing
18
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
t
RAS
RHCP
t
t
CSH
HPC
t
CRP
t
RSH
t
RCD
t
CAL
t
CAS
t
ASC
CAS
t
RAH
t
CP
t
RAL
t
t
ASR
CAH
Address
Row
Column
Column
Don’t Care
t
RAD
t
CAL
t
CWL
t
t
CWL
t
RWL
WP
t
DS
W
Don’t Care
Don’t Care
Don’t Care
t
OEH
t
DH
t
CLZ
Valid
In
Don’t Care
Valid Data In
Don’t Care
DQ0–DQ7
Invalid Data out
t
OEH
t
OED
Don’t Care
Don’t Care
OE
NOTE A: Areadcycleoraread-writecyclecanbeintermixedwithwritecyclesaslongasreadandread-writetimingspecificationsarenotviolated.
Figure 10. EDO Write-Cycle Timing
19
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
CAS
t
t
CSH
t
RSH
t
PRWC
t
CRP
t
RCD
CP
t
t
CAS
ASR
ASC
t
t
CAL
t
CAH
t
RAL
t
RAD
Row
Column 1
Column 2
Don’t Care
Address
t
RAH
t
CWL
t
CWD
t
CPW
t
AWD
t
RWL
t
WP
t
RWD
W
t
RCS
t
CPA
t
OEH
t
AA
t
DH
t
t
Valid Out 2
RAC
t
DS
See Note A
t
CAC
Valid
In 1
Valid
In 2
DQ0–DQ7
Valid
Out 1
t
CLZ
t
OED
OEA
t
t
OEH
OEZ
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 11. EDO Read-Write-Cycle Timing
20
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
t
CRP
RP
t
T
t
RPC
Don’t Care
Don’t Care
CAS
t
RAH
t
ASR
Address
Row
Don’t Care
Row
Don’t Care
W
DQ0–DQ7
OE
Hi-Z
Don’t Care
Figure 12. RAS-Only Refresh-Cycle Timing
21
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PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
CHR
RPC
t
T
t
WRP
t
WRH
Don’t Care
Don’t Care
W
Address
OE
Don’t Care
Don’t Care
DQ0–DQ7
Hi-Z
Figure 13. Automatic-CBR-Refresh-Cycle Timing
22
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PARAMETER MEASUREMENT INFORMATION
t
RASS
RAS
t
t
RPC
RPS
t
CSR
t
CHS
CAS
t
CP
Address
Don’t Care
t
WRP
t
WRH
W
Don’t Care
OE
Don’t Care
DQ0–DQ7
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
23
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
RP
Memory Cycle
t
RP
t
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Row
Col
Don’t Care
Address
t
WRH
t
WRH
t
RRH
t
WRP
t
WRP
t
RCS
t
W
RAC
t
CAC
t
REZ
t
WEZ
t
CEZ
t
AA
Valid Data Out
OEA
Don’t Care
DQ0–DQ7
OE
t
CLZ
t
OEZ
t
Figure 15. Hidden-Refresh-Cycle (Read) Timing
24
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
ASR
Don’t Care
Row
Col
Address
t
WRH
t
WCS
t
WRP
t
WP
W
t
WCH
t
DH
t
DS
Don’t Care
Valid Data
DQ0–DQ7
OE
Don’t Care
Figure 16. Hidden-Refresh-Cycle (Write) Timing
25
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MECHANICAL DATA
DGC (R-PDSO-G28)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
28
0.008 (0,20)
M
15
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
0.006 (0,15) NOM
1
14
Gage Plane
0.729 (18,51)
0.721 (18,31)
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.000 (0,00) MIN
4040260-2/B 02/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
26
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
MECHANICAL DATA
DZ (R-PDSO-J**)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
32 PIN SHOWN
A
32
17
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
16
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
0.008 (0,20) NOM
Seating Plane
0.004 (0,10)
0.380 (9,65)
0.360 (9,14)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18)
M
0.050 (1,27)
PINS **
24
28
32
40
42
DIM
0.730
(18,54)
0.730
(18,54)
0.830
(21,08)
1.030
(26,16)
1.080
(27,43)
A MAX
0.720
(18,29)
0.720
(18,29)
0.820
(20,83)
1.020
(25,91)
1.070
(27,18)
A MIN
4040094/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,13).
D. The 24 pin package has the center two pins removed on both sides.
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
device symbolization (TMS417809A illustrated)
TI
-SS
Speed ( -50, - 60, -70)
Low-Power/Self Refresh Designator (Blank or P)
TMS417809A DZ
Package Code
W
E
Y
M
LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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