TMS44100-80SD [TI]
4MX1 FAST PAGE DRAM, 80ns, PZIP20, PLASTIC, ZIP-20;
| 型号： | TMS44100-80SD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4MX1 FAST PAGE DRAM, 80ns, PZIP20, PLASTIC, ZIP-20 动态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
DGA PACKAGE
(TOP VIEW)
DJ PACKAGE
(TOP VIEW)
Organization . . . 4194304 × 1
Single 5 V Power Supply, for TMS44100/P
(±10% Tolerance)
D
W
RAS
NC
1
2
3
4
5
26
25
24
23
22
V
Q
CAS
NC
A9
D
W
RAS
NC
1
2
3
4
5
26
25
24
23
22
V
SS
Q
CAS
NC
A9
SS
Single 3.3 V Power Supply, for TMS46100/P
(±10% Tolerance)
Low Power Dissipation (TMS46100P only)
– 200-µA CMOS Standby
– 200-µA Self Refresh
A10
A10
– 300-µA Extended-Refresh Battery
Backup
A0
A1
A2
A3
9
18
17
16
15
14
A8
A7
A6
A5
A4
A0
A1
A2
A3
9
18
17
16
15
14
A8
A7
A6
A5
A4
10
11
12
13
10
11
12
13
Performance Ranges:
ACCESS ACCESS ACCESS
TIME TIME TIME OR WRITE
(t (t
READ
V
V
CC
CC
)
)
(t
AA
)
CYCLE
(MIN)
RAC CAC
(MAX)
60 ns
70 ns
80 ns
(MAX)
15 ns
18 ns
20 ns
(MAX)
30 ns
35 ns
40 ns
’4x100/P-60
’4x100/P-70
’4x100/P-80
110 ns
130 ns
150 ns
PIN NOMENCLATURE
A0–A10
CAS
D
Address Inputs
Column-Address Strobe
Enhanced Page-Mode Operation for Faster
Memory Access
Data In
NC
No Connection
Data Out
CAS-Before-RAS (CBR) Refresh
Q
RAS
W
Row-Address Strobe
Write Enable
5-V or 3.3-V Supply
Ground
Long Refresh Period
– 1024-Cycle Refresh in 16 ms
– 128 ms (Max) for Low-Power,
Self-Refresh Version (TMS4x100P)
V
CC
V
SS
3-State Unlatched Output
Texas Instruments EPIC CMOS Process
Operating Free-Air Temperature Range
0°C to 70°C
description
The TMS4x100 series are high-speed,
4194304-bit dynamic random-access memories,
organized as 4194304 words of one bit each. The
TMS4x100P series are high-speed, low-power,
self-refresh with extended-refresh, 4194304-bit
dynamic random-access memories, organized as
4194304 words of one bit each. Both series
SELF-REFRESH
POWER
SUPPLY
REFRESH
CYCLES
DEVICE
BATTERY
BACKUP
TMS44100
TMS44100P
TMS46100
TMS46100P
5 V
5 V
—
YES
—
1024 in 16 ms
1024 in 128 ms
1024 in 16 ms
1024 in 128 ms
3.3 V
3.3 V
employ state-of-the-art EPIC
(Enhanced
YES
Performance Implanted CMOS) technology for
high performance, reliability, and low voltage.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x100 and TMS4x100P are offered in a 20-/26-lead plastic surface-mount small-outline (TSOP)
package(DGAsuffix)anda300-mil20-/26-leadplasticsurface-mountSOJpackage(DJsuffix). Bothpackages
are characterized for operation from 0°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
†
logic symbol
RAM 4096K × 1
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
30D11/21D0
10
11
12
14
15
16
17
18
22
5
0
A
4 194 303
31D21/21D10
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR DWN]
C31 [COL]
3
RAS
CAS
G34
24
&
33C32
2
1
W
D
33,31D
A, 32D
34 EN
25
A
Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
functional block diagram
RAS
CAS
W
Timing and Control
A0
A1
8
Column Decode
Sense Amplifiers
16
Column-
Address
Buffers
3
128K Array
128K Array
128K Array
Data-
In
Reg.
R
o
128K Array
D
Q
A10
16
I/O
Buffers
1 of 16
w
D
e
c
o
d
e
Data-
Out
Selection
16
16
Row-
Address
Buffers
Reg.
10
3
128K Array
10
128K Array
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
operation
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x100 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after t
max (access time from CAS low),
CAC
if t max (access time from column address) has been satisfied. If column addresses for the next cycle are
AA
valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of t
CAC
or t
(access time from rising edge of CAS).
CPA
address (A0–A10)
Twenty-two address bits are required to decode 1 of 4194304 storage cell locations. Eleven row-address bits
are set up on inputs A0 through A10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on A0 through A10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enableinthatitactivatesthesenseamplifiersaswellastherowdecoder. CASisusedasachipselect, activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on W selects the read mode
and a logic low selects the write mode. W can be driven from standard TTL circuits (TMS44100/P) or
low-voltage TTL circuits (TMS46100/P) without a pullup resistor. The data input is disabled when the read mode
is selected. When W goes low prior to CAS (early write), data out remains in the high-impedance state for the
entire cycle, permitting common I/O operation.
data in (D)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS is already low and the data is strobed in by W with setup and hold times referenced to this signal.
data out (Q)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS is brought
low. In a read cycle, the output becomes valid after the access time interval t (which begins with the negative
CAC
transition of CAS) as long as t
and t are satisfied. The output becomes valid after the access time has
RAC
AA
elapsed and remains valid while CAS is low; CAS going high returns it to the high-impedance state. In a
delayed-write or read-write cycle, the output follows the sequence for the read cycle.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x100P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS at V after a read operation and cycling RAS after a specified
IL
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
) and holding it low after RAS
CSR
falls (see parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
CHR
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-µA (TMS46100P) or 500-µA
(TMS44100P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 µs while holding RAS low for less than 1 µs. To minimize current consumption, all
input levels need to be at CMOS levels (V ≤ 0.2 V, V ≥ V – 0.2 V).
IL
IH
CC
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RASand CAS
are brought high to satisfy t
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
CHS
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full V level is achieved. These eight initialization cycles must include at least one refresh
CC
(RAS-only or CBR) cycle.
test mode
An industry-standard design-for-test (DFT) mode is incorporated in the TMS4x100 and TMS4x100P. A CBR
cycle with W low (WCBR) cycle is used to enter the test mode. In the test mode, data is written into and read
from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data-out
terminal goes high. If any one bit is different, the data-out terminal goes low. Any combination of read, write,
read-write, or page-mode cycles can be used in the test mode. The test-mode function reduces test times by
enabling the 4-Mbit DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10,
and column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
test mode (continued)
Exit Cycle
Entry Cycle
Normal
Mode
Test-Mode Cycle
RAS
CAS
W
†
The states of W, data in, and address are defined by the type of cycle used during test mode.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
:
TMS44100, TMS44100P . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS46100, TMS46100P . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
Voltage range on any pin (see Note 1): TMS44100, TMS44100P . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS46100, TMS46100P . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS44100/P
MIN NOM MAX
TMS46100/P
NOM
UNIT
MIN
MAX
V
V
V
T
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
3
2
3.3
3.6
V
V
V
CC
IH
IL
High-level input voltage
V
CC
+ 0.3
Low-level input voltage (see Note 2)
Operating free-air temperature
– 0.3
0
0.8
70
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’44100-60
’44100P-60
’44100-70
’44100P-70
’44100-80
’44100P-80
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
0.4
0.4
0.4
OL
OL
V
= 5.5 V,
CC
I
Input current (leakage)
Output current (leakage)
V = 0 V to 6.5 V,
I
All others = 0 V to V
± 10
± 10
± 10
µA
I
CC
V
= 5.5 V,
V
= 0 V to V
,
CC
CAS high
O
CC
I
I
± 10
± 10
± 10
µA
O
Read- or write-cycle current
(see Note 3)
V
CC
= 5.5 V,
Minimum cycle
105
90
80
mA
CC1
After 1 memory cycle,
RAS and CAS high,
2
2
2
mA
V
IH
= 2.4 V (TTL)
I
Standby current
CC2
CC3
After 1 memory cycle,
RAS and CAS high,
’44100
’44100P
1
1
1
mA
V
= V
– 0.2 V
CC
IH
(CMOS)
500
500
500
µA
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR)
Average refresh current
(RAS only or CBR)
(see Note 4)
I
105
90
80
mA
V
= 5.5 V, = minimum,
t
Average page current
(see Notes 3 and 5)
CC
PC
I
I
I
90
500
5
80
500
5
70
500
5
mA
µA
CC4
CC6
CC7
RAS low,
CAS cycling
Self-refresh current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
> 1000 ms
†
t
and t
RAS
CAS
Standby current, outputs
enabled (see Note 3)
RAS = V
Data out = enabled
,
CAS = V ,
IL
IH
mA
t
= 125 µs,
t
≤ 1 ms,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
V
CC
IH
Battery-backup current
(with CBR)
†
I
0 V ≤ V ≤ 0.2 V,
500
500
500
µA
CC10
IL
W and OE = V
,
IH
Address and data stable
†
For TMS44100P only
NOTES: 3. I max is specified with no load connected.
CC
4. Measured with a maximum of one address change while RAS = V
5. Measured with a maximum of one address change while CAS = V
IL
IH
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’46100-60
’46100P-60
’46100-70
’46100P-70
’46100-80
’46100P-80
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA (LVTTL)
= – 100 µA (LVCMOS)
= 2 mA (LVTTL)
2.4
2.4
2.4
High-level
output voltage
OH
OH
OL
OL
V
V
V
OH
V
–0.2
V
–0.2
V
–0.2
CC
CC
CC
0.4
0.2
0.4
0.2
0.4
0.2
Low-level
output voltage
V
OL
= 100 µA (LVCMOS)
Input current
(leakage)
V = 0 V to 3.9 V,
All others = 0 V to V
V
= 3.6 V,
I
CC
CC
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
V
O
= 0 V to V , V
= 3.6 V,
Output current
(leakage)
CC CC
O
CAS high
Read- or
write-cycle
current
(see Note 3)
I
Minimum cycle,
V
= 3.6 V
70
2
60
2
50
2
mA
mA
CC1
CC
After 1 memory cycle,
RAS and CAS high,
V
= 2.0 V (LVTTL)
IH
Standby
current
I
CC2
CC3
After 1 memory cycle,
RAS and CAS high,
’46100
’46100P
= 3.6 V,
300
200
300
200
300
200
µA
µA
V
= V
– 0.2 V
CC
IH
(LVCMOS)
Average
Minimum cycle,
RAS cycling,
V
CC
refresh current
(RAS only or
CBR)
I
70
60
50
mA
CAS high (RAS only);
RAS low after CAS low (CBR)
(see Note 4)
Average page
current
(see Notes 3
and 5)
t
= minimum,
V
= 3.6 V,
PC
CC
I
I
60
50
40
mA
CC4
RAS low,
CAS cycling
Self-refresh
current
(see Note 3)
CAS ≤ 0.2 V,
RAS < 0.2 V,
> 1000 ms
†
200
200
200
µA
CC6
t
and t
RAS
CAS
Standby
current,
outputs
enabled
(see Note 3)
RAS = V
Data out = enabled
,
CAS = V ,
IL
IH
I
5
5
5
mA
CC7
t
= 125 µs,
t
≤ 1 ms,
RC
RAS
– 0.2 V ≤ V ≤ 3.9 V,
V
Battery-backup
current
(with CBR)
CC
IH
†
I
0 V ≤ V ≤ 0.2 V,
300
300
300
µA
CC10
IL
W and OE = V
,
IH
Address and data stable
†
For TMS46100P only
NOTES: 3.
I
max is specified with no load connected.
CC
4. Measured with a maximum of one address change while RAS = V
5. Measured with a maximum of one address change while CAS = V
IL
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
Input capacitance, A0–A10
Input capacitance, CAS and RAS
Input capacitance, W
5
7
7
7
i(A)
i(RC)
i(W)
o
pF
pF
Output capacitance
pF
NOTE 6:
V
CC
= 5 V ± .5 V for the TMS44100 devices, V = 3.3 V ± 0.3 V for the TMS46100 devices, and the bias on pins under test is 0 V.
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’4x100-60
’4x100-70
’4x100-80
’4x100P-60
’4x100P-70
’4x100P-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
Access time from column address
ns
ns
ns
ns
ns
ns
AA
Access time from CAS low
15
18
20
CAC
CPA
RAC
CLZ
OFF
Access time from column precharge
Access time from RAS low
35
40
45
60
70
80
CAS to output in low impedance
Output disable time after CAS high (see Note 7)
0
0
0
0
0
0
15
18
20
NOTE 7:
t
is specified when the output is no longer driven.
OFF
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x100-60
’4x100-70
’4x100-80
’4x100P-60
’4x100P-70
’4x100P-80
UNIT
MIN
110
130
40
MAX
MIN
130
153
45
MAX
MIN
150
175
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 8)
Cycle time, read-write (see Note 8)
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
RWC
PC
Cycle time, page-mode read or write (see Notes 8 and 9)
Cycle time, page-mode read-write (see Note 8)
Pulse duration, RAS low, page mode (see Note 10)
Pulse duration, RAS low, nonpage mode (see Note 10)
Pulse duration, RAS low, self refresh
60
68
75
PRWC
RASP
RAS
RASS
CAS
CP
60 100 000
70 100 000
80 100 000
60
100
15
10
40
140
10
0
10 000
70
100
18
10
50
130
10
0
10 000
80
100
20
10
60
150
10
0
10 000
Pulse duration, CAS low, (see Note 11)
Pulse duration, CAS high
10 000
10 000
10 000
Pulse duration, RAS high (precharge)
RP
Precharge time after self refresh using RAS
Pulse duration, write
RPS
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 12)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
0
0
0
RCS
CWL
RWL
WCS
WSR
WTS
CAH
DHR
DH
Setup time, W low before CAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high (CBR refresh only)
Setup time, W low (test mode only)
10
10
10
50
10
50
10
0
10
10
15
55
15
55
10
0
10
10
15
60
15
60
10
0
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 13)
Hold time, data (see Note 12)
Hold time, column address after RAS low (see Note 13)
Hold time, row address after RAS low
AR
RAH
RCH
RRH
WCH
WCR
WHR
WTH
Hold time, W high after CAS high (see Note 14)
Hold time, W high after RAS high (see Note 14)
Hold time, W low after CAS low (early-write operation only)
Hold time, W low after RAS low (see Note 13)
Hold time, W high (CBR refresh only)
0
0
0
10
50
10
10
15
55
10
10
15
60
10
10
Hold time, W low (test mode only)
Delay time, column address to W low
(read-write operation only)
t
30
35
40
ns
AWD
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
10
0
10
0
10
0
ns
ns
ns
CHR
CRP
CSH
Delay time, RAS low to CAS high
60
70
80
NOTES: 8. All cycle times assume t = 5 ns.
T
ASC
9. To assure t
min, t
should be ≥ 5 ns.
PC
10. In a read-write cycle, t
11. In a read-write cycle, t
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
12. Referenced to the later of CAS or W in write operations
13. The minimum value is measured when t is set to t
min as a reference.
RCD
RCD
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
9
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x100-60
’4x100-70
’4x100-80
’4x100P-60
’4x100P-70
’4x100P-80
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CAS low to RAS low (CBR refresh only)
Hold time, CAS low after RAS high, self refresh
Delay time, CAS low to W low (read-write operation only)
Delay time, RAS low to column address (see Note 15)
Delay time, column address to RAS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
CSR
CHS
CWD
RAD
RAL
–50
15
15
30
30
20
0
–50
18
15
35
35
20
0
–50
20
15
40
40
20
0
30
45
35
52
40
60
Delay time, column address to CAS high
CAL
Delay time, RAS low to CAS low (see Note 15)
Delay time, RAS high to CAS low
RCD
RPC
RSH
RWD
TAA
Delay time, CAS low to RAS high
15
60
35
40
65
18
70
40
45
75
20
80
45
50
85
Delay time, RAS low to W low (read-write operation only)
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RAS (test mode)
TCPA
TRAC
’4x100
16
128
50
16
128
50
16
128
50
t
Refresh time interval
REF
’4x100P
t
T
Transition time
2
2
2
NOTE 15: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
V
CC
= 5 V
R
= 218 Ω
R1 = 828 Ω
R2 = 295 Ω
L
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
L
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
Figure 1. Load Circuits for Timing Parameters
10
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TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.4 V
V
= 3.3 V
CC
R
= 500 Ω
R1 = 1178 Ω
L
Output Under Test
= 100 pF
Output Under Test
= 100 pF
C
C
L
L
R2 = 868 Ω
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
Figure 2. Low-Voltage Load Circuits for Timing Parameters
t
RC
t
RAS
RAS
t
t
RP
CSH
t
t
CRP
RCD
t
RSH
t
T
t
CAS
CAS
t
RAD
t
CP
t
ASC
t
ASR
t
RAL
CAL
t
RAH
t
Row
Column
Don’t Care
A0–A10
t
RCS
t
RRH
t
AR
t
RCH
t
CAH
Don’t Care
Don’t Care
W
Q
t
CAC
t
OFF
t
AA
Hi-Z
Valid Data Out
See Note A
CLZ
t
t
RAC
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
11
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TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
T
t
RSH
t
RP
t
RCD
t
CAS
t
CRP
t
CSH
CAS
t
ASC
t
CAH
t
RAH
t
CP
t
CAL
t
ASR
t
RAL
t
AR
A0–A10
Row
Column
WCR
Don’t Care
t
CWL
t
RWL
t
RAD
t
WCH
t
t
WCS
Don’t Care
Don’t Care
W
t
DH
t
WP
t
DS
Valid Data
Don’t Care
D
Q
t
DHR
Hi-Z
Figure 4. Early-Write-Cycle Timing
12
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
CAS
t
RP
t
T
t
RSH
t
RCD
t
t
CRP
CAS
t
CSH
t
ASC
t
t
CAL
RAH
t
t
CP
CAH
t
AR
t
RAL
t
ASR
Row
Column
Don’t Care
A0–A10
t
CWL
t
RAD
t
RWL
t
DS
Don’t Care
Don’t Care
W
t
WP
t
WCR
t
DH
t
DHR
Valid Data
Don’t Care
Don’t Care
D
Q
t
t
OFF
CLZ
Invalid
Figure 5. Write-Cycle Timing
13
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
CAS
t
t
T
t
CAS
RP
t
t
RCD
CRP
t
ASR
t
RAH
t
CP
t
ASC
t
t
RAD
CAH
t
AR
A0–A10
Row
Column
Don’t Care
t
CWL
t
CAH
t
RWL
t
RCS
t
WP
t
AWD
W
Don’t Care
Don’t Care
t
CWD
t
RWD
t
DS
D
Q
Don’t Care
Valid In
Don’t Care
t
DH
t
OFF
t
CLZ
(see Note A)
Valid Out
Hi-Z
t
CAC
t
AA
t
RAC
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
14
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
t
t
PC
RCD
t
t
CRP
CSH
t
CP
t
t
T
t
RSH
CAS
CAS
t
RAH
t
CAH
t
RAL
t
ASR
t
ASC
t
CAL
A0–A10
Row
Column
Column
Don’t Care
t
t
t
AA
AR
RRH
(see Note A)
t
RCH
t
RCS
W
t
RAD
t
CPA
(see Note A)
t
CAC
t
AA
t
OFF
t
RAC
t
CLZ
Valid
Out
Q
Valid Out
See Note B
NOTES: A. Access time is t
or t
dependent.
CPA
AA
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Enhanced-Page-Mode Read-Cycle Timing
15
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
t
t
CRP
CSH
t
PC
t
RCD
t
RSH
t
CAS
CAS
t
ASR
t
ASC
t
CP
t
AR
t
RAL
t
t
CAH
RAH
t
CAL
A0–A10
Row
Column
Column
Don’t Care
t
RAD
t
CWL
t
CWL
t
WCR
t
t
RWL
WP
t
DHR
W
Don’t Care
See Note A
Don’t Care
See Note A
Don’t Care
t
DH
t
t
DS
t
DH
(see Note A)
DS
See Note A
Valid Data In
Valid
Data In
D
Q
Don’t Care
Hi-Z
NOTES: A. Referenced to CAS or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
16
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
t
PRWC
t
CRP
t
t
CP
CSH
t
t
RSH
RCD
t
CAS
CAS
t
t
RAD
t
ASR
ASC
t
t
CAH
RAH
t
AR
A0–A10
Row
Column
Column
Don’t Care
t
CWD
t
t
CWL
RCS
t
AWD
t
RWL
t
WP
t
RWD
W
t
DS
t
DH
Valid
CAC
D
Don’t Care
Don’t Care
Valid
Don’t Care
t
t
t
OFF
CLZ
t
AA
t
t
RAC
CPA
t
CLZ
See Note A
See Note A
Valid
Out
Q
Valid Out
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
17
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
RP
t
CRP
t
CRP
t
T
t
RPC
CAS
Don’t Care
Don’t Care
t
RAH
t
ASR
A0–A10
Row
Don’t Care
Don’t Care
Don’t Care
Row
See Note A
W
D
Q
NOTE A: A10 is a don’t care.
Figure 10. RAS-Only Refresh-Cycle Timing
18
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
RPC
CHR
t
T
t
WSR
t
WHR
W
A0–A10
Don’t Care
Don’t Care
D
Q
Hi-Z
Figure 11. Automatic CBR-Refresh-Cycle Timing
19
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RPS
t
RP
t
RASS
RAS
CAS
t
CSR
t
t
CHS
RPC
t
T
t
WSR
t
WHR
W
A0–A10
Don’t Care
Don’t Care
D
Q
Hi-Z
Figure 12. Self-Refresh-Cycle Timing
20
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
RP
Refresh Cycle
Memory Cycle
t
t
RP
t
RAS
t
RAS
RAS
CAS
t
CHR
t
CAS
t
AR
t
CAH
ASC
t
t
RAH
t
ASR
Don’t Care
t
A0–A10
Row
Col
t
t
WHR
t
t
WHR
RRH
WHR
t
t
WSR
RCS
WSR
t
WSR
W
D
Don’t Care
t
RAC
t
AA
t
OFF
t
CAC
t
CLZ
Q
Valid Data
Figure 13. Hidden-Refresh-Cycle (Read) Timing
21
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TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
RAS
Refresh Cycle
t
t
RP
RP
t
t
RAS
RAS
CAS
t
CHR
t
CAS
t
CAH
t
t
ASC
t
RAH
AR
t
ASR
Row
Col
A0–A10
Don’t Care
t
RRH
t
t
WCS
WHR
t
WSR
t
WCR
t
WP
W
t
WCH
t
DH
t
DHR
t
DS
D
Q
Don’t Care
Hi-Z
Figure 14. Hidden-Refresh-Cycle (Write) Timing
22
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TMS44100, TMS44100P, TMS46100, TMS46100P
4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
CAS
t
CSR
t
t
RPC
CHR
t
T
t
WTH
t
WTS
Don’t Care
W
A0–A10
D
Don’t Care
Don’t Care
Hi-Z
Q
Figure 15. Test-Mode Entry Cycle
device symbolization (TMS44100 illustrated)
-SS
Speed ( -60, - 70, -80)
Low-Power/Self-Refresh Designator (blank or P)
Package Code
TMS44100
DJ
M
W
B
Y
LLL
P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
23
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4194304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS561A – MARCH 1995 – REVISED JUNE 1995
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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