TMS45160-10DZ [TI]
256KX16 FAST PAGE DRAM, 100ns, PDSO40;
| 型号： | TMS45160-10DZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 256KX16 FAST PAGE DRAM, 100ns, PDSO40 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总23页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMHS160D − AUGUST 1992 − REVISED JUNE 1995
DZ PACKAGE
(TOP VIEW)
DGE PACKAGE
(TOP VIEW)
This data sheet is applicable to all TMS45160/Ps
symbolized with Revision “D” and subsequent
revisions as described on page 21.
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
V
V
V
V
SS
CC
SS
CC
2
3
4
5
6
7
8
9
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
D Organization . . . 262144 × 16
D 5-V Supply ( 10% Tolerance)
D Performance Ranges:
V
V
V
V
ACCESS ACCESS ACCESS READ OR
CC
SS
CC
SS
TIME
TIME
TIME
WRITE
CYCLE
MIN
DQ4
DQ5
DQ6
DQ7
NC
NC
W
RAS
NC
A0
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
DQ4
DQ5
DQ6
DQ7
DQ11
DQ10
DQ9
t
t
t
RAC
CAC
AA
MAX
MAX
MAX
’45160/P-60
’45160/P-70
’45160/P-80
60 ns
70 ns
80 ns
15 ns
20 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
10
11
12
13
14
15
16
17
18
19
20
DQ8
D Enhanced-Page-Mode Operation With
13
32
NC
NC
NC 14
31 LCAS
xCAS-Before-RAS (xCBR) Refresh
15
16
17
18
19
20
21
22
30
29
28
27
26
25
24
23
W
RAS
NC
A0
UCAS
OE
A8
A7
A6
D Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
64 ms Max for Low Power With
Self-Refresh Version (TMS45160P)
A1
A2
A3
A1
A2
A3
A4
V
A5
A4
V
D 3-State Unlatched Output
CC
SS
D Low Power Dissipation
V
V
CC
SS
D Texas Instruments EPIC CMOS Process
D All Inputs, Outputs, and Clocks Are TTL
Compatible
PIN NOMENCLATURE
D High-Reliability, 40-Lead, 400-Mil-Wide
Plastic Surface-Mount (SOJ) Package and
40/44-Lead Thin Small-Outline Package
(TSOP)
A0−A8
Address Inputs
Data In/Data Out
DQ0−DQ15
LCAS
NC
OE
RAS
Lower Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Upper Column-Address Strobe
5-V Supply
D Operating Free-Air Temperature Range
0°C to 70°C
UCAS
D Low Power With Self-Refresh Version
V
CC
V
SS
D Upper and Lower Byte Control During Read
Ground
Write Enable
W
and Write Operations
description
The TMS45160 series are high-speed, 4194304-bit dynamic random-access memories organized as 262144
words of 16 bits each. The TMS45160P series are high-speed, low-power, self-refresh 4194304-bit dynamic
random-access memories organized as 262144 words of 16 bits each. They employ state-of-the-art EPIC
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power at low
cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation
is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs, including clocks,
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS45160 and TMS45160P are each offered in a 40-lead plastic surface-mount SOJ package (DZ suffix)
and a 40/44-lead plastic surface-mount small-outline (TSOP) package (DGE suffix). These packages are
characterized for operation from 0°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
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Copyright 1995, Texas Instruments Incorporated
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1
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ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
operation
dual CAS
Two CAS pins (LCAS−UCAS) are provided to give independent control of the 16 data I/O pins (DQ0−DQ15)
with LCAS corresponding to DQ0−DQ7 and UCAS corresponding to DQ8−DQ15. For read or write cycles, the
column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx
pins with data associated with the column address latched on the first falling xCAS edge. All address setup and
hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out
(see parameter t
) is measured from each individual xCAS to its corresponding DQx pins.
CAC
In order to latch in a new column address, both xCAS pins must be brought high. The column precharge time
(see parameter t ) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
CP
Keeping a column address valid while toggling xCAS requires a minimum setup time, t
least one xCAS must be brought low before the other xCAS is taken high.
. During t
, at
CLCH
CLCH
For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet t minimum in order to ensure writing into
CAS
the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet t
.
CP
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 512 columns specified by column
addresses A0 through A8 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The first falling edge
of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after t
well in advance of the falling edge of xCAS. In this case, data is obtained after t
(row-address hold time) has been satisfied, usually
RAH
max (access time from xCAS
CAC
low) if t max (access time from column address) has been satisfied. In the event that column addresses for
AA
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by t
(access time from rising edge of the last xCAS).
CPA
address (A0−A8)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Nine row-address bits are set
up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through
A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of
RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. W can be driven from the standard TTL circuits without a pullup resistor. The data input lines
are disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains
in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.
2
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SMHS160D − AUGUST 1992 − REVISED JUNE 1995
data in (DQ0−DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to data in. In a
delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to data in. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0−DQ15)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating)
state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time interval
t
(which begins with the negative transition of xCAS) as long as t
and t are satisfied.
CAC
RAC AA
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state. They remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
A refresh operation must be performed at least once every 8 ms (64 ms for TMS45160P) to retain data. This
can be achieved by strobing each of the 512 rows (A0−A8). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding all xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
IL
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter t
) and holding
CSR
it low after RAS falls (see parameter t
). For successive xCBR refresh cycles, xCAS can remain low while
CHR
cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 500-µA refresh current is available on the
TMS45160P. Data integrity is maintained using xCBR refresh with a period of 125 µs holding
RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
(V ≤ 0.2 V, V ≥ V − 0.2 V).
IL
IH
CC
self refresh (TMS45160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 µs. The chip is refreshed internally by an on-board oscillator. No external address
is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and xCAS are brought high to satisfy t
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set
CHS
of row addresses) must be executed before continuing with normal operation. This ensures that the DRAM is
fully refreshed.
3
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight RAS cycles is
required after power up to the full V
(RAS-only or xCBR) cycle.
level.These eight initialization cycles must include at least one refresh
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMHS160D − AUGUST 1992 − REVISED JUNE 1995
†
logic symbol
RAM 256K × 16
20D9/21D0
16
17
18
19
22
23
24
25
26
A0
A1
A2
A3
A4
A5
A6
A7
A8
0
A
262 143
20D17/21D8
C20[ROW]
G23/[REFRESH ROW]
14
29
RAS
24[PWR DWN]
C21
G24
LCAS
&
23C22
31
C21
G34
28
UCAS
&
23C32
31
Z31
24,25EN27
34,25EN37
13
27
W
23,21D
G25
OE
2
A,22D
DQ0
A, Z26
∇ 26,27
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
4
5
7
8
9
10
31
A,32D
A, Z36
∇ 36,37
32
33
34
36
37
38
39
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the DZ package.
5
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
functional block diagram
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
16
Column-
Address
Buffers
128K Array
128K Array
128K Array
R
o
Data-
In
Reg.
16
128K Array
A8
16
w
16 I/O
D
e
c
o
d
e
16
Buffers
Data-
In
Reg.
16
16
Row-
Address
Buffers
9
DQ0−DQ15
128K Array
9
128K Array
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
− 1
0
6.5
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’45160-60
’45160-70
’45160-80
’45160P-60
’45160P-70
’45160P-80
PARAMETER
TEST CONDITIONS
UNIT
MIN MAX
MIN
MAX
MIN MAX
High-level output
voltage
V
V
I
I
= − 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
10
0.4
10
0.4
10
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
CC
= 0 V to V
CC
V
= 5.5 V,
V
O
,
Output current
(leakage)
CC
CAS high
10
10
10
O
Read- or write-cycle
current
†§
V
V
= 5.5 V,
Minimum cycle
180
160
140
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and xCAS high
2
2
2
mA
I
Standby current
CC2
V
= V − 0.2 V (CMOS),
CC
’45160
1
1
1
mA
IH
After 1 memory cycle,
RAS and xCAS high
’45160P
350
350
350
µA
V
= 5.5 V,
Minimum cycle,
RAS cycling,
CC
(RAS only),
Average refresh
current (RAS-only
refresh or CBR)
‡
I
I
180
160
160
140
140
120
mA
mA
CC3
xCAS high (CBR only),
RAS low after xCAS low
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
xCAS cycling
†§
Average page current
CC4
Battery-backup
operating current
(equivalent refresh
time is 64 ms);
CBR only
t
V
= 125 µs,
CC
t
≤ 1 µs,
RC
RAS
− 0.2 V ≤ V ≤ 6.5 V,
IH
¶
I
I
500
400
500
400
500
400
µA
µA
CC5
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IL
IH
xCAS < 0.2 V,
RAS < 0.2 V,
> 1000 ms
CAS
†¶
Self-refresh current
CC6
t
and t
RAS
†
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while xCAS = V
For TMS45160P only
IL
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
#
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
C
Input capacitance, A0−A8
Input capacitance, OE
5
7
7
7
7
i(A)
pF
i(OE)
i(RC)
i(W)
o
Input capacitance, xCAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
#
Capacitance measurements are made on a sample basis only.
NOTE 3: = 5 V 0.5 V, and the bias on pins under test is 0 V.
V
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’45160-60
’45160-70
’45160-80
’45160P-60
’45160P-70
’45160P-80
PARAMETER
UNIT
MIN
MAX
15
MIN
MAX
20
MIN
MAX
20
t
t
t
t
t
t
t
t
Access time from xCAS low
ns
ns
ns
ns
ns
ns
ns
ns
CAC
Access time from column address
30
35
40
AA
Access time from RAS low
60
70
80
RAC
OEA
CPA
CLZ
OFF
OEZ
Access time from OE low
15
20
20
Access time from column precharge
Delay time, xCAS low to output in low impedance
Output disable time after xCAS high (see Note 4)
Output disable time after OE high (see Note 4)
35
40
45
0
0
0
0
0
0
0
0
0
15
15
20
20
20
20
NOTE 4:
t
and t are specified when the output is no longer driven.
OEZ
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
’45160-60
’45160-70
’45160-80
’45160P-60
’45160P-70
’45160P-80
UNIT
MIN
110
110
155
40
MAX
MIN
130
130
185
45
MAX
MIN
150
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (see Note 6)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write
WC
Cycle time, read-write/read-modify-write
Cycle time, page-mode read or write (see Note 7)
Cycle time, page-mode read-modify-write
Pulse duration, RAS low, page mode (see Note 8)
Pulse duration, RAS low, nonpage mode (see Note 8)
Pulse duration, xCAS low (see Note 9)
Pulse duration, xCAS high
RWC
PC
85
90
105
PRWC
RASP
RAS
CAS
CP
60 100 000
70 100 000
80 100 000
60
15
10
40
15
0
10 000
10 000
70
20
10
50
15
0
10 000
10 000
80
20
10
60
15
0
10 000
10 000
Pulse duration, RAS high (precharge)
Pulse duration, write
RP
WP
Setup time, column address before xCAS low
Setup time, row address before RAS low
Setup time, data before W low (see Note 10)
Setup time, read before xCAS low
ASC
ASR
DS
0
0
0
0
0
0
0
0
0
RCS
CWL
Setup time, W low before xCAS high
Setup time, W low before RAS high
Setup time, W low before xCAS low (see Note 11)
15
15
0
20
20
0
20
20
0
t
RWL
WCS
t
NOTES: 5. Timing measurements are referenced to V max and V min.
IL
IH
6. All cycle times assume t = 5 ns.
T
7. To assure t
min, t
should be ≥ t
CP
.
PC
ASC
8. In a read-modify-write cycle, t
9. In a read-modify-write cycle, t
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
10. Referenced to the later of xCAS or W in write operations
11. Early-write operation only
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
’45160-60
’45160-70
’45160-80
’45160P-60
’45160P-70
’45160P-80
UNIT
MIN
10
30
10
30
10
0
MAX
MIN
15
35
15
35
10
0
MAX
MIN
15
35
15
35
10
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, column address after xCAS low (see Note 10)
Hold time, data after RAS low (see Note 12)
Hold time, data after xCAS low (see Note 10)
Hold time, column address after RAS low (see Note 12)
Hold time, row address after RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
CAH
DHR
DH
AR
RAH
RCH
RRH
WCH
WCR
CLCH
AWD
CHR
CRP
CSH
CSR
CWD
OEH
OED
ROH
RAD
RAL
CAL
RCD
RPC
Hold time, read after xCAS high (see Note 13)
Hold time, read after RAS high (see Note 13)
Hold time, write after xCAS low (see Note 13)
Hold time, write after RAS low (see Note 14)
Hold time, xCAS low to xCAS high
0
0
0
10
30
5
15
35
5
15
35
5
Delay time, column address to W low (see Note 15)
Delay time, RAS low to xCAS high (see Note 11)
Delay time, xCAS high to RAS low
55
15
0
65
15
0
70
20
0
Delay time, RAS low to xCAS high
60
10
40
15
15
10
15
30
30
20
0
70
10
50
20
20
10
15
35
35
20
0
80
10
50
20
20
10
15
40
40
20
0
Delay time, xCAS low to RAS low (see Note 11)
Delay time, xCAS low to W low (see Note 15)
Hold time, OE command
Delay time, OE high before data at DQ
Delay time, OE low to RAS high
Delay time, RAS low to column address (see Note 16)
Delay time, column address to RAS high
Delay time, column address to xCAS high
Delay time, RAS low to xCAS low (see Note 16)
Delay time, RAS high to xCAS low (see Note 11)
Delay time, xCAS low to RAS high
30
45
35
50
40
60
t
t
t
t
t
t
15
85
0
20
100
0
20
110
0
RSH
RWD
CPR
RPS
RASS
CHS
Delay time, RAS low to W low (see Note 15)
Pulse duration, xCAS precharge before self refresh
Pulse duration, RAS precharge after self refresh
Pulse duration, self refresh entry from RAS low
Hold time, xCAS low after RAS high (for self refresh)
110
100
− 50
130
100
− 50
150
100
− 50
’45160
8
64
50
8
64
50
8
64
50
t
Refresh time interval
Transition time
ms
ns
REF
T
’45160P
t
2
2
2
NOTES: 5. Timing measurements are referenced to V max and V min.
IL
IH
10. Referenced in the later of xCAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when t
is set to t min as a reference.
RCD
RCD
13. Either t
RRH
or t must be satisfied for a read cycle.
RCH
14. xCBR refresh only
15. Read-modify-write operation only
16. Maximum value specified only to assure access time
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.31 V
V
CC
= 5 V
R
= 218 Ω
R1 = 828 Ω
L
Output Under Test
Output Under Test
R2 = 295 Ω
C
= 100 pF
L
C
= 100 pF
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
L
Figure 1. Load Circuits for Timing Parameters
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
T
t
t
RP
CP
t
RCD
t
CAS
UCAS
t
CLCH
(see Note A)
t
CRP
LCAS
t
CSH
t
RSH
t
RAD
t
RAH
t
ASC
t
CAL
t
ASR
t
RAL
Row
Column
Don’t Care
A0−A8
t
AR
t
RRH
t
CAH
t
RCS
t
RCH
Don’t Care
Don’t Care
W
t
CAC
t
t
AA
OFF
See Note B
t
CLZ
Valid Data Out
DQ0−DQ15
t
RAC
t
OEZ
t
OEA
t
ROH
OE
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
must be met.
CLCH
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C.
t
is measured from xCAS to its corresponding DQx.
CAC
D. xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
t
T
t
RP
t
RCD
t
UCAS
CAS
t
CLCH
(see Note A)
t
CP
LCAS
t
ASR
t
CRP
t
CSH
t
RSH
t
RAH
t
ASC
t
CAL
t
RAL
A0−A8
Row
Column
Don’t Care
t
AR
t
CAH
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WCR
t
WP
t
(see Note B)
DH
t
DHR
DQ0−DQ15
Valid Data In
t
DS
t
OED
t
OEH
OE
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
B. Later of xCAS or W in write operations
must be met.
CLCH
C. xCAS order is arbitrary.
Figure 3. Write-Cycle Timing
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
t
T
t
RP
t
RCD
t
CSH
t
CRP
t
CAS
UCAS
t
RSH
t
CLCH
(see Note A)
LCAS
t
RAD
t
CP
t
ASR
t
RAH
t
ASC
t
CAL
t
RAL
Column
Address
A0−A8
Row Address
Don’t Care
Don’t Care
Don’t Care
t
CAH
t
AR
t
WCS
t
WCH
W
Don’t Care
t
CWL
t
RWL
t
WCR
t
WP
Don’t Care
DQ0−DQ15
Valid Data In
t
DH
t
DHR
t
DS
OE
Don’t Care
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
B. xCAS order is arbitrary.
must be met.
CLCH
Figure 4. Early-Write-Cycle Timing
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
t
RP
t
T
t
RCD
t
CAS
UCAS
t
CSH
t
CRP
t
t
CLCH
(see Note A)
AR
t
CP
t
RSH
t
LCAS
RAD
t
RAH
t
ASC
t
ASR
Column
A0−A8
Row
Don’t Care
t
t
CAH
CWL
t
AWD
t
RWL
t
CWD
t
t
WP
RCS
W
Don’t Care
Don’t Care
t
RWD
See Note B
DQ8−DQ15
Don’t Care
Valid Out
Don’t Care
t
AA
t
DH
t
CAC
t
DS
t
RAC
t
OEZ
t
t
OEA
OE
OED
See Note B
DQ0−DQ7
Don’t Care
Valid Out
Valid In
Don’t Care
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RAS
RASP
t
RCD
t
CRP
UCAS
t
RSH
t
PC
t
t
CSH
CP
t
t
LCAS
CAS
ASR
t
AR
t
RAH
t
CAL
t
ASC
t
t
CAH
Don’t Care
RAL
A0−A8
W
Row
RAD
Column
Column
Don’t Care
t
RRH
t
t
RCH
Don’t
Care
Don’t
Care
t
CAC
(see Note A)
t
AA
t
RCS
t
RAC
t
CLZ
t
OFF
Valid
Out
DQ8−DQ15
DQ0−DQ7
See Note B
CPA
t
OEZ
t
t
AA
Valid
Out
Valid
Out
t
OEA
OE
NOTES: A.
t
is measured from xCAS to its corresponding DQx.
CAC
B. Access time is t
or t dependent.
AA
CPA
C. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
D. xCAS order is arbitrary.
E. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
15
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RAS
RASP
t
RSH
UCAS
t
CRP
t
CLCH
(see Note A)
t
PC
t
RCD
t
CP
t
CSH
t
LCAS
CAS
t
ASR
t
CAH
t
AR
t
CAL
t
t
ASC
RAL
t
RAH
A0−A8
Row
RAD
Column
Don’t Care
Column
Don’t Care
t
t
CWL
t
t
CWL
t
t
WP
RWL
WCR
t
DS
(see Note B)
t
WCH
Don’t Care
W
Don’t Care
Don’t Care
t
DHR
DQ8−DQ15
Valid In
Valid In
Valid In
t
DH
Valid In
OED
See Note B
DQ0−DQ7
OE
t
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
B. Referenced to xCAS or W, whichever occurs last
C. xCAS order is arbitrary.
must be met.
CLCH
D. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
16
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
UCAS
LCAS
t
CSH
t
RSH
t
RCD
t
CRP
t
PRWC
t
CAS
t
CP
t
CLCH
(see Note A)
t
ASR
ASC
t
t
t
CAH
RAD
A0−A8
Row
Column
Column
t
t
CWD
t
RAH
CWL
t
WP
t
AWD
t
RWL
t
RWD
W
t
CAC
(see Note B)
t
RCS
t
t
OEH
CPA
t
DS
t
AA
t
RAC
CLZ
Valid Out
Valid In
See Note C
t
Valid In
DQ0−DQ15
Valid Out
OEA
t
OEH
t
t
OEZ
t
OED
OE
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter t
CLCH
must be met.
B.
t
is measured from xCAS to its corresponding DQx.
CAC
C. Output can go from the high-impedance state to an invalid data state prior to the specified access time.
D. xCAS order is arbitrary.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
xCAS
t
CRP
t
RP
t
t
T
RPC
See Note A
Don’t Care
Don’t Care
t
ASR
t
RAH
Row
Don’t Care
Row
A0−A8
Don’t Care
W
Hi-Z
DQ0−DQ15
Don’t Care
OE
NOTE A: All xCAS must be high.
Figure 9. RAS-Only Refresh Timing
18
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
t
t
RP
RAS
t
RAS
RAS
t
t
RP
CHR
t
CAS
xCAS
t
ASR
RAH
t
t
ASC
t
CAH
A0−A8
W
Row Col
Don’t Care
t
RRH
t
RCS
Don’t Care
t
CAC
t
t
AA
OFF
t
RAC
DQ0−DQ15
OE
Valid Data
t
t
OEZ
OEA
Figure 10. Hidden-Refresh-Cycle Timing
19
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
t
CSR
t
t
CHR
RPC
t
T
xCAS
Don’t Care
Don’t Care
Don’t Care
W
A0−A8
OE
DQ0−DQ15
Hi-Z
NOTE A: Any xCAS can be used.
Figure 11. Automatic-CBR- Refresh-Cycle Timing
20
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢖ
ꢖ
ꢉ
ꢐ
ꢂ
ꢊ ꢆ ꢊ ꢋ ꢅꢃ ꢃ ꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕꢔ ꢌꢂ ꢉ ꢖ
ꢐ
ꢒ
ꢗ
ꢘ
ꢁ
ꢓ
ꢙ
ꢏ
ꢘ
ꢗ
ꢐ
ꢎ
ꢁ
ꢌ
ꢘ
ꢙ
ꢙ
ꢖ
ꢂ
ꢂ
ꢁ
ꢖ
ꢁ
ꢎ
ꢏ
ꢓ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
RASS
RAS
t
t
RPS
CSR
t
RPC
t
CHS
xCAS
t
CPR
Don’t Care
Don’t Care
Don’t Care
A0−A8
W
OE
Hi-Z
DQ0−DQ15
NOTE A: Any xCAS can be used.
Figure 12. Self-Refresh-Cycle Timing
device symbolization (TMS45160 illustrated)
TI
-SS
Speed ( -60, - 70, -80)
Low-Power/Self-Refresh Designator (Blank or P)
Package Code
TMS45160 DZ
W
B
Y
M LLL
P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢉ
ꢊꢆ ꢊꢋꢅꢃ ꢃ ꢌꢍꢎꢏ ꢐ ꢑꢒ ꢅ ꢆ ꢌꢑꢓ ꢀ ꢔꢓ ꢕ ꢔꢌꢂ ꢉꢖ ꢖ ꢐ
ꢐ ꢒꢗ ꢘ ꢁꢓ ꢙ ꢏ ꢘꢗ ꢐ ꢎ ꢁꢌꢘꢙ ꢙꢖ ꢂꢂ ꢁꢖ ꢁꢎ ꢏꢓ ꢖꢂ
SMHS160D − AUGUST 1992 − REVISED JUNE 1995
22
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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相关型号：
TMS45160DZ-80
IC 256K X 16 FAST PAGE DRAM, 80 ns, PDSO40, 0.400 INCH, PLASTIC, SOJ-40, Dynamic RAM
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