TMS470R1B768PGE_技术文档

TMS470R1B768

www.ti.com ......................................................................................................................................................... SPNS108B–AUGUST 2005–REVISED MAY 2008

16/32-Bit RISC Flash Microcontroller

1

FEATURES

•

Ten Communication Interfaces:

23

•

High-Performance Static CMOS Technology

–

Five Serial Peripheral Interfaces (SPIs)

255 Programmable Baud Rates

•

TMS470R1x 16/32-Bit RISC Core (ARM7TDM™)

–

60-MHz (Pipeline Mode)

–

Two Serial Communications Interfaces

(SCIs)

Independent 16/32-Bit Instruction Set

Open Architecture With Third-Party Support

Built-In Debug Module

–

2²⁴Selectable Baud Rates

Asynchronous/Isosynchronous Modes

–

Three High-End CAN Controllers (HECCs)

Utilizes Big-Endian Format

–

32-Mailbox Capacity Each

•

Integrated Memory

Fully Compliant With CAN Protocol,

Version 2.0B

–

768K-Byte Program Flash

–

3 Banks With 18 Contiguous Sectors

•

High-End Timer (HET)

Internal State Machine for Programming

and Erase

–

32 Programmable I/O Channels:

–

24 High-Resolution Pins

–

48K-Byte Static RAM (SRAM)

8 Standard-Resolution Pins

•

15 Dedicated GIO Pins, 1 Input-Only GIO Pin,

and 71 Additional Peripheral I/Os

–

High-Resolution Share Feature (XOR)

High-End Timer RAM

Operating Features

–

Core Supply Voltage (V_CC): 1.81–2.05 V

I/O Supply Voltage (V_CCIO): 3.0–3.6 V

Low-Power Modes: STANDBY and HALT

Extended Industrial Temperature Range

– 128-Instruction Capacity

•

16-Channel 10-Bit Multi-Buffered ADC

(MibADC)

–

256-Word FIFO Buffer

Single- or Continuous-Conversion Modes

•

470+ System Module

1.55-µs Minimum Sample and Conversion

Time

–

32-Bit Address Space Decoding

Bus Supervision for Memory and

Peripherals

–

Calibration Mode and Self-Test Features

•

Eight External Interrupts

–

Analog Watchdog (AWD) Timer

Real-Time Interrupt (RTI)

Flexible Interrupt Handling

External Clock Prescale (ECP) Module

System Integrity and Failure Detection

Interrupt Expansion Module (IEM)

–

Programmable Low-Frequency External

Clock (CLK)

•

Direct Memory Access (DMA) Controller

32 Control Packets and 16 Channels

•

On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1⁽¹⁾(JTAG) Test-Access Port

–

Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

•

144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)

–

Multiply-by-4 or -8 Internal ZPLL Option

ZPLL Bypass Mode

(1)

The test-access port is compatible with the IEEE Standard

1149.1-1990, IEEE Standard Test-Access Port and Boundary

Scan Architecture specification. Boundary scan is not

supported on this device.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM).

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMS470R1B768

SPNS108B–AUGUST 2005–REVISED MAY 2008 ......................................................................................................................................................... www.ti.com

TMS470R1B768 144-Pin PGE Package (Top View)

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

ADIN[11]

ADIN[14]

ADIN[10]

ADIN[13]

ADIN[9]

AWD

HET[18]

HET[19]

HET[20]

HET[21]

HET[22]

SPI2SCS

SPI2ENA

SPI2SOMI

SPI2SIMO

SPI2CLK

SPI5ENA

SPI5CLK

SPI5SOMI

SPI5SIMO

CAN2HRX

CAN2HTX

ADIN[12]

ADIN[8]

AD

REFHI

AD

REFLO

V

CCAD

V

SSAD

TMS

TMS2

GIOC[0]

HET[23]

HET[25]

HET[26]

HET[27]

V

CC

V

SS

CC

CCIO

HET[0]

HET[1]

SSIO

HET[24]

HET[31]

HET[30]

HET[29]

HET[28]

SPI5SCS

SCI2CLK

SCI2TX

SCI2RX

GIOA[3]/INT3

GIOA[2]/INT2

GIOA[1]/INT1/ECLK

GIOA[0]/INT0

TEST

V

SS

CC

FLTP2

FLTP1

V

CCP

V

SS

HET[2]

HET[3]

HET[4]

HET[5]

HET[6]

HET[7]

GIOC[1]

GIOC[2]

(A)

TRST

A. GIOA[0]/INT0 (pin 39) is an input-only GIO pin.

2

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TMS470R1B768

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DESCRIPTION

The TMS470R1B768⁽¹⁾device is a member of the Texas Instruments (TI) TMS470R1x family of general-purpose

16/32-bit reduced instruction set computer (RISC) microcontrollers. The B768 microcontroller offers high

performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a

high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views

memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B768 utilizes the big-endian

format where the most significant byte of a word is stored at the lowest numbered byte and the least significant

byte at the highest numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low

costs. The B768 RISC core architecture offers solutions to these performance and cost demands while

maintaining low power consumption.

The B768 device contains the following:

•

ARM7TDMI 16/32-Bit RISC CPU

TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM)

and a 16-channel direct-memory access (DMA) controller]

•

768K-byte flash

48K-byte SRAM

Zero-pin phase-locked loop (ZPLL) clock module

Analog watchdog (AWD) timer

Real-time interrupt (RTI) module

Five serial peripheral interface (SPI) modules

Two serial communications interface (SCI) modules

Three high-end CAN controller (HECC) modules

10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels

High-end timer (HET) controlling 32 I/Os

External clock prescale (ECP) module

Up to 86 I/O pins and 1 input-only pin

The functions performed by the 470+ system module (SYS) include:

•

Address decoding

Memory protection

Memory and peripherals bus supervision

Reset and abort exception management

Expanded interrupt capability with prioritization for all internal interrupt sources

Device clock control

Direct-memory access (DMA) and control

Parallel signature analysis (PSA)

This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt

priority, and a device memory map. For a more detailed functional description of the SYS module, see the

TMS470R1x System Module Reference Guide (literature number SPNU189). For a more detailed functional

description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide

(literature number SPNU211). And for a more detailed functional description of the DMA module, see the

TMS470R1x Direct-Memory Access (DMA) Controller Reference Guide (literature number SPNU210).

The B768 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,

half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented

with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When

in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed

information on the F05 devices flash, see the F05 flash section of this data sheet.

(1) Throughout the remainder of this document, TMS470R1B768 shall be referred to as either the full device name or B768.

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The B768 device has ten communication interfaces: five SPIs, two SCIs, and three HECCs. The SPI provides a

convenient method of serial interaction for high-speed communications between similar shift-register type

devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the

CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses a serial,

multimaster communication protocol that efficiently supports distributed real-time control with robust

communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in

noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed

wiring. For more detailed functional information on the SPI, SCI, and HECC, see the specific reference guides for

these modules (literature numbers SPNU195, SPNU196, and SPNU197, respectively).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.

The timer is software controlled, using a reduced instruction set, with a specialized timer micromachine and an

attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited

for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.

For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference

Guide (literature number SPNU199).

The B768 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-resolution

channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more

detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference

Guide (literature number SPNU199).

The B768 device has a 10-bit-resolution, 16-channel sample-and-hold MibADC. The MibADC channels can be

converted individually or can be grouped by software for sequential conversion sequences. There are three

separate groupings, two of which are triggerable by an external event. Each sequence can be converted once

when triggered or configured for continuous conversion mode. For more detailed functional information on the

MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature

number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a

clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the

external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system

(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock

(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other B768 device modules. For more

detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock

Module Reference Guide (literature number SPNU212).

NOTE:

ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the

continuous system clock from an external resonator/crystal reference.

The B768 device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous

external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the

peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the

TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

4

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Device Characteristics

Table 1 identifies all the characteristics of the TMS470R1B768 device except the SYSTEM and CPU, which are

generic.

Table 1. Device Characteristics

DEVICE DESCRIPTION

CHARACTERISTICS

COMMENTS For B768

TMS470R1B768

MEMORY

For the number of memory selects on this device, see Table 3, Memory Selection Assignment.

INTERNAL MEMORY

Pipeline/non-pipeline

Flash is pipeline-capable.

The B768 RAM is implemented in one 48K array selected by two

memory-select signals (see Table 3, Memory Selection Assignment).

768K-byte flash

48K-byte SRAM

PERIPHERALS

For the device-specific interrupt priority configurations, see Table 7, Interrupt Priority (IEM and CIM). And for the 1K peripheral address

ranges and their peripheral selects, see Table 5, B768 Peripherals, System Module, and Flash Base Addresses.

CLOCK

ZPLL

Zero-pin PLL has no external loop filter pins.

GENERAL-PURPOSE I/Os

15 I/O

1 input only

Port A has eight (8) external pins, port B has one (1), port C has

three (3), and port D has four (4).

ECP

YES

SCI

2 (3 pin)

3 HECCs

5 (5 pin)

SCI1 and SCI2

CAN (HECC and/or SCC)

SPI (5-pin, 4-pin or 3-pin)

Three HECCs (HECC1, HECC2, and HECC3)

SPI1, SPI2, SPI3, SPI4, and SPI5

The B768 device has both the logic and registers for a full 32-I/O

HET implemented and all 32 pins are available externally.

The high-resolution (HR) SHARE feature allows even HR pins to

share the next higher odd HR pin structures. This HR sharing is

independent of whether or not the odd pin is available externally. If

an odd pin is available externally and shared, then the odd pin can

only be used as a general-purpose I/O. For more information on HR

SHARE, see the TMS470R1x High-End Timer (HET) Reference

Guide (literature number SPNU199).

HET with XOR Share

32 I/O

HET RAM

MibADC

128-instruction capacity

The B768 device has both the logic and registers for a full

16-channel MibADC implemented and all 16 pins are available

externally.

10-bit, 16-channel, 256-word

FIFO

CORE VOLTAGE

I/O VOLTAGE

PINS

1.81V to 2.05 V

3.0 V to 3.6 V

144

PACKAGE

PGE

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Functional Block Diagram

External

Pins

External Pins

OSCIN

ZPLL

OSCOUT

PLLDIS

V

CCP

FLASH

(768K Bytes)

18 Sectors

RAM

(48K Bytes)

FLTP1

FLTP2

ADIN[15:0]

ADEVT

MibADC

with

256−Word

AD

REFHI

CPU Address/Data Bus

REFLO

FIFO

V

CCAD

V

SSAD

HET with

XOR Share

(128−Word)

HET [0:23]

HET[24:31]

TRST

TCK

TMS470R1x

CPU

TDI

TDO

TMS

TMS2

RST

CAN1HTX

CAN1HRX

HECC1

HECC2

HECC3

CAN2HTX

CAN2HRX

TMS470R1x System Module

AWD

CAN3HTX

CAN3HRX

TEST

PORRST

CLKOUT

Interrupt

DMA Controller

16 Channels

Expansion

SCI1CLK

SCI1TX

Module (IEM)

SCI1

SCI2

SCI2CLK

SCI2TX

GIOD[0:3]

GIOC[0:2]

GIOB[7]

GIOA[2:7]/INT[2:7]

GIOA[0]/INT[0]

GIO

(A)

SPI5

SPI4

SPI3

SPI2

SPI1

GIOA[1]/INT[1]/

ECLK

ECP

A. GIOA[0]/INT[0] is an input-only GIO pin.

6

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Table 2. Terminal Functions

TERMINAL

NAME

INTERNAL

PULLUP/

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

HIGH-END TIMER (HET)

HET[0]

129

HET[1]

130

137

138

139

140

141

142

79

HET[2]

HET[3]

HET[4]

HET[5]

HET[6]

HET[7]

HET[8]

HET[9]

80

HET[10]

HET[11]

HET[12]

HET[13]

HET[14]

HET[15]

HET[16]

HET[17]

HET[18]

HET[19]

HET[20]

HET[21]

HET[22]

HET[23]

HET[24]

HET[25]

HET[26]

HET[27]

HET[28]

HET[29]

HET[30]

HET[31]

29

28

The B768 device has both the logic and registers for a full 32-I/O HET

implemented and all 32 pins are available externally.

27

26

Timer input capture or output compare. The HET[31:0] applicable pins can be

programmed as general-purpose input/output (GIO) pins. HET[23:0] are

high-resolution pins and HET[31:24] are standard-resolution pins.

25

24

The high-resolution (HR) SHARE feature allows even HR pins to share the

next higher odd-numbered HR pin structures. This HR sharing is independent

of whether or not the odd pin is available externally. If an odd pin is available

externally and shared, then the odd pin can only be used as a

general-purpose I/O. For more information on HR SHARE, see the

TMS470R1x High-End Timer (HET) Reference Guide (literature number

SPNU199).

3.3-V I/O

IPD (20 µA)

23

22

71

70

69

68

67

123

51

124

125

126

47

48

49

50

HIGH-END CAN CONTROLLER 1 (HECC1)

CAN1HTX

CAN1HRX

88

87

3.3-V I/O

IPU (20 µA)

HECC1 transmit pin or GIO pin

HECC1 receive pin or GIO pin

HIGH-END CAN CONTROLLER 2 (HECC2)

CAN2HTX

CAN2HRX

56

57

3.3-V I/O

IPU (20 µA)

HECC2 transmit pin or GIO pin

HECC2 receive pin or GIO pin

HIGH-END CAN CONTROLLER 3 (HECC3)

CAN3HTX

CAN3HRX

78

77

3.3 V I/O

IPU (20 µA)

HECC3 transmit pin or GIO pin

HECC3 receive pin or GIO pin

(1) I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect

(2) All I/O pins, except RST , are configured as inputs while PORRST is low and immediately after PORRST goes high.

(3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST

state.)

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

GENERAL-PURPOSE I/O (GIO)

GIOA[0]/INT0

39

3.3-V I

GIOA[1]/INT1

/ECLK

40

GIOA[2]/INT2

GIOA[3]/INT3

GIOA[4]/INT4

GIOA[5]/INT5

GIOA[6]/INT6

GIOA[7]/INT7

GIOB[7]

41

42

36

35

General-purpose input/output pins.

34

GIOA[0]/INT0 is an input-only pin. GIOA[7:0]/INT[7:0] are interrupt-capable

pins.

33

IPD (20 µA)

3.3-V I/O

84

The GIOA[1]/INT1/ECLK pin is multiplexed with the external clock-out function

of the external clock prescale (ECP) module.

GIOC[0]

122

143

144

21

GIOC[1]

GIOC[2]

GIOD[0]

GIOD[1]

20

GIOD[2]

19

GIOD[3]

18

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)

3.3-V I/O IPD (20 µA) MibADC event input. ADEVT can be programmed as a GIO pin.

ADEVT

ADIN[0]

ADIN[1]

ADIN[2]

ADIN[3]

ADIN[4]

ADIN[5]

ADIN[6]

ADIN[7]

ADIN[8]

ADIN[9]

ADIN[10]

99

108

107

106

105

104

102

101

100

115

113

111

3.3-V I

MibADC analog input pins

8

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) (CONTINUED)

ADIN[11]

109

ADIN[12]

ADIN[13]

ADIN[14]

ADIN[15]

114

112

110

103

3.3-V I

MibADC analog input pins

3.3-V

REF I

AD_REFHI

AD_REFLO

116

117

MibADC module high-voltage reference input

MibADC module low-voltage reference input

GND

REF I

3.3-V

PWR

V_CCAD

V_SSAD

118

119

MibADC analog supply voltage

MibADC analog ground reference

GND

SERIAL PERIPHERAL INTERFACE 1 (SPI1)

SPI1CLK

SPI1ENA

SPI1SCS

SPI1SIMO

SPI1SOMI

5

1

2

3

4

SPI1 clock. SPI1CLK can be programmed as a GIO pin.

SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.

SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.

SPI1 data stream. Slave in/master out. Can be programmed as a GIO pin.

SPI1 data stream. Slave out/master in. Can be programmed as a GIO pin.

3.3-V I/O

IPD (20 µA)

SERIAL PERIPHERAL INTERFACE 2 (SPI2)

SPI2 clock. SPI2CLK can be programmed as a GIO pin.

SPI2CLK

SPI2ENA

SPI2SCS

SPI2SIMO

SPI2SOMI

62

65

66

63

64

SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.

3.3-V I/O

IPD (20 µA)

SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.

SPI2 data stream. Slave in/master out. Can be programmed as a GIO pin.

SPI2 data stream. Slave out/master in. Can be programmed as a GIO pin.

SERIAL PERIPHERAL INTERFACE 3 (SPI3)

SPI3 clock. SPI3CLK can be programmed as a GIO pin.

SPI3CLK

SPI3ENA

SPI3SCS

SPI3SIMO

SPI3SOMI

94

98

97

96

95

SPI3 chip enable. SPI3ENA can be programmed as a GIO pin.

IPD (20 µA)

SPI3 slave chip select. SPI3SCS can be programmed as a GIO pin.

SPI3 data stream. Slave in/master out. Can be programmed as a GIO pin.

SP3 data stream. Slave out/master in. Can be programmed as a GIO pin.

SERIAL PERIPHERAL INTERFACE 4 (SPI4)

SPI4 clock. SPI4CLK can be programmed as a GIO pin.

SPI4CLK

SPI4ENA

SPI4SCS

SPI4SIMO

SPI4SOMI

10

6

SPI4 chip enable. SPI4ENA can be programmed as a GIO pin.

7

IPD (20 µA)

SPI4 slave chip select. SPI4SCS can be programmed as a GIO pin.

SPI4 data stream. Slave in/master out. Can be programmed as a GIO pin.

SPI4 data stream. Slave out/master in. Can be programmed as a GIO pin.

8

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

SERIAL PERIPHERAL INTERFACE 5 (SPI5)

SPI5CLK

60

SPI5 clock. SPI5CLK can be programmed as a GIO pin.

SPI5ENA

SPI5SCS

SPI5SIMO

SPI5SOMI

61

46

58

59

SPI5 chip enable. SPI5ENA can be programmed as a GIO pin.

SPI5 slave chip select. SPI5SCS can be programmed as a GIO pin.

SPI5 data stream. Slave in/master out. Can be programmed as a GIO pin.

SPI5 data stream. Slave out/master in. Can be programmed as a GIO pin.

3.3-V I/O

IPD (20 µA)

ZERO-PIN PHASE-LOCKED LOOP (ZPLL)

Crystal connection pin or external clock input

OSCIN

13

12

1.8-V I

OSCOUT

1.8-V O

External crystal connection pin

Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator

becomes the system clock. If not in bypass mode, TI recommends that this

pin be connected to ground or pulled down to ground by an external resistor.

PLLDIS

73

3.3-V I

IPD (20 µA)

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)

SCI1CLK

SCI1RX

SCI1TX

89

91

90

3.3-V I/O

IPD (20 µA)

IPU (20 µA)

SCI1 clock. SCI1CLK can be programmed as a GIO pin.

SCI1 data receive. SCI1RX can be programmed as a GIO pin.

SCI1 data transmit. SCI1TX can be programmed as a GIO pin.

SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)

SCI2CLK

SCI2RX

SCI2TX

45

43

44

3.3-V I/O

IPD (20 µA)

IPU (20 µA)

SCI2 clock. SCI2CLK can be programmed as a GIO pin.

SCI2 data receive. SCI2RX can be programmed as a GIO pin.

SCI2 data transmit. SCI2TX can be programmed as a GIO pin.

SYSTEM MODULE (SYS)

Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of

SYSCLK, ICLK, or MCLK.

CLKOUT

PORRST

83

32

3.3-V I/O

3.3-V I

IPD (20 µA)

Input master chip power-up reset. External V_CCmonitor circuitry must assert a

power-on reset.

IPD (20 µA)

Bidirectional reset. The internal circuitry can assert a reset, and an external

system reset can assert a device reset.

RST

15

3.3-V I/O

IPU (20 µA)

On this pin, the output buffer is implemented as an open drain (drives low

only). To ensure an external reset is not arbitrarily generated, TI recommends

that an external pullup resistor be connected to this pin.

WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)

Analog watchdog reset. The AWD pin provides a system reset if the WD KEY

is not written in time by the system, providing an external RC network circuit

is connected. If the user is not using AWD, TI recommends that this pin be

connected to ground or pulled down to ground by an external resistor.

AWD

72

3.3-V I/O

IPD (20 µA)

For more details on the external RC network circuit, see the TMS470R1x

System Module Reference Guide (literature number SPNU189) and the

application note Analog Watchdog Resistor, Capacitor and Discharge Interval

Selection Constraints (literature number SPNA005).

TEST/DEBUG (T/D)

TCK

TDI

76

74

3.3-V I

IPD (20 µA)

IPU (20 µA)

Test clock. TCK controls the test hardware (JTAG).

Test data in. TDI inputs serial data to the test instruction register, test data

register, and programmable test address (JTAG).

Test data out. TDO outputs serial data from the test instruction register, test

data register, identification register, and programmable test address (JTAG).

TDO

75

3.3-V O

IPD (20 µA)

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Table 2. Terminal Functions (continued)

TERMINAL

NAME

INTERNAL

PULLUP/

TYPE⁽¹⁾⁽²⁾

DESCRIPTION

PULLDOWN⁽³⁾

NO.

TEST/DEBUG (T/D) (CONTINUED)

Test enable. Reserved for internal use only. TI recommends that this pin be

connected to ground or pulled down to ground by an external resistor.

TEST

TMS

38

3.3-V I

IPD (20 µA)

IPU (20 µA)

Serial input for controlling the state of the CPU test access port (TAP)

controller (JTAG)

120

121

Serial input for controlling the second TAP. TI recommends that this pin be

connected to V_CCIOor pulled up to V_CCIOby an external resistor.

TMS2

TRST

Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)

Boundary-Scan Logic. TI recommends that this pin be pulled down to ground

by an external resistor.

37

3.3-V I

IPD (20 µA)

FLASH

Flash test pad 1. For proper operation, this pin must not be connected

[no connect (NC)].

FLTP1

FLTP2

V_CCP

134

133

135

NC

Flash test pad 2. For proper operation, this pin must not be connected

[no connect (NC)].

Flash external pump voltage (3.3 V). This pin is required for both flash read

and flash program and erase operations.

3.3-V PWR

SUPPLY VOLTAGE CORE (1.8 V)

14

31

55

V_CC

86

1.8-V PWR

Core logic supply voltage

93

128

132

SUPPLY VOLTAGE DIGITAL I/O (3.3 V)

Digital I/O supply voltage

17

53

82

V_CCIO

3.3-V PWR

SUPPLY GROUND CORE

11

30

54

85

V_SS

GND

Core supply ground reference

92

127

131

136

SUPPLY GROUND DIGITAL I/O

16

52

81

V_SSIO

GND

Digital I/O supply ground reference

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B768 DEVICE-SPECIFIC INFORMATION

Memory

Figure 1 shows the memory map of the B768 device.

Memory (4G Bytes)

0xFFFF_FFFF

SYSTEM with PSA, CIM,

System Module

Control Registers

(512K Bytes)

RTI, DEC

0xFFFF_FD00

IEM

0xFFF8_0000

0xFFF7_FFFF

0xFFFF_FC00

0xFFF8_0000

Reserved

Peripheral Control Registers

(512K Bytes)

0xFFF0_0000

0xFFEF_FFFF

HET

SPI1

SCI2

0xFFF7_FC00

Reserved

Flash Control Registers

Reserved

0xFFE8_C000

0xFFE8_BFFF

0xFFE8_8000

0xFFE8_7FFF

0xFFF7_F800

0xFFF7_F500

0xFFE8_4024

0xFFE8_4023

SCI1

0xFFF7_F400

0xFFF7_F000

0xFFF7_EC00

MPU Control Registers

0xFFE8_4000

0xFFE8_3FFF

MibADC

GIO/ECP

Reserved

0xFFE0_0000

HECC1/HECC2

HECC1/2 RAM

0xFFF7_E800

0xFFF7_E400

0xFFF7_D800

Reserved

SPI4/SPI5

SPI2/SPI3

0xFFF7_D600

0xFFF7_D400

RAM

(48K Bytes)

HECC3 and HECC3 RAM

Reserved

Program

and

Data Area

FLASH

(768K Bytes)

18 Sectors

0xFFF7_D000

0xFFF7_C000

Reserved

HET RAM

(1.5K Bytes)

0xFFF0_0000

0x0000_001F

FIQ

IRQ

0x0000_001C

0x0000_0018

Reserved

0x0000_0014

Data Abort

0x0000_0010

0x0000_000C

0x0000_0008

0x0000_0004

Prefetch Abort

Software Interrupt

Undefined Instruction

Reset

0x0000_0020

0x0000_001F

Exception, Interrupt, and

Reset Vectors

0x0000_0000

A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.

B. The CPU registers are not part of the memory map.

Figure 1. TMS470R1B768 Memory Map

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Memory Selects

Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined

addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx

and MFBALRx) that, together, define the array's starting (base) address, block size, and protection.

The base address of each memory select is configurable to any memory address boundary that is a multiple of

the decoded block size. For more information on how to control and configure these memory select registers, see

the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature number

SPNU189).

For the memory selection assignments and the memory selected, see Table 3.

Table 3. Memory Selection Assignment

MEMORY

SELECT

MEMORY SELECTED

(ALL INTERNAL)

MEMORY

SIZE

MEMORY BASE ADDRESS

REGISTER

STATIC MEM

CTL REGISTER

MPU

0 (fine)

1 (fine)

2 (fine)

3 (fine)

4 (fine)

FLASH

RAM

NO

MFBAHR0 and MFBALR0

MFBAHR1 and MFBALR1

MFBAHR2 and MFBALR2

MFBAHR3 and MFBALR3

MFBAHR4 and MFBALR4

768K

YES

48K⁽¹⁾

1.5K

RAM

HET RAM

SMCR1

(1) The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block

size in the memory-base address register.

RAM

The B768 device contains 48K bytes of internal static RAM configurable by the SYS module to be addressed

within the range of 0x0000_0000 to 0xFFE0_0000. This B768 RAM is implemented in one 48K-byte array

selected by two memory-select signals. This B768 configuration imposes an additional constraint on the memory

map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the

multiples of the size of the physical RAM (i.e., 48K bytes for the B768 device). The B768 RAM is addressed

through memory selects 2 and 3.

The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user

finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an

operating system while allowing access to the current task. For more detailed information on the MPU portion of

the SYS module and memory protection, see the memory section of the TMS470R1x System Module Reference

Guide (literature number SPNU189).

F05 Flash

The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a

32-bit-wide data bus interface. The F05 flash has an external state machine for program and erase functions.

See the flash read and flash program and erase sections below.

Flash Protection Keys

The B768 device provides flash protection keys. These four 32-bit protection keys prevent

program/erase/compaction operations from occurring until after the four protection keys have been matched by

the CPU loading the correct user keys into the FMPKEY control register. The protection keys on the B768 are

located in the last 4 words of the first 16K sector. For more detailed information on flash program and erase

operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

Flash Read

The B768 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000 to

0xFFE0_0000. The flash is addressed through memory selects 0 and 1.

NOTE:

The flash external pump voltage (V_CCP) is required for all operations (program, erase,

and read).

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Flash Pipeline Mode

When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system

clock in normal mode of up to 30 MHz). Flash in pipeline mode is capable of accessing 64-bit words and

provides two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash can be read with no wait states

when memory addresses are contiguous (after the initial 1-or 2-wait-state reads).

NOTE:

After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In

other words, the B768 device powers up and comes out of reset in non-pipeline

mode. Furthermore, setting the flash configuration mode bit (GBLCTRL.4) will override

pipeline mode.

Flash Program and Erase

The B768 device flash contains three 256K-byte memory arrays (or banks) for a total of 768K bytes of flash and

consists of 18 sectors. These 18 sectors are sized as follows:

Table 4. B768 Flash Memory Banks and Sectors

MEMORY ARRAYS

SECTOR NO.

SEGMENT

LOW ADDRESS

HIGH ADDRESS

(OR BANKS)

0

1

2

3

4

5

6

7

8

9

16K Bytes

32K Bytes

16K Bytes

0x0000_0000

0x0000_4000

0x0000_8000

0x0001_0000

0x0001_8000

0x0002_0000

0x0002_8000

0x0003_0000

0x0003_8000

0x0003_C000

0x0000_3FFF

0x0000_7FFF

0x0000_FFFF

0x0001_7FFF

0x0001_FFFF

0x0002_7FFF

0x0002_FFFF

0x0003_7FFF

0x0003_BFFF

0x0003_FFFF

BANK0

(256K Bytes)

0

1

2

3

64K Bytes

0x0004_0000

0x0005_0000

0x0006_0000

0x0007_0000

0x0004_FFFF

0x0005_FFFF

0x0006_FFFF

0x0007_FFFF

BANK1

(256K Bytes)

0

1

2

3

64K Bytes

0x0008_0000

0x0009_0000

0x000A_0000

0x000B_0000

0x0008_FFFF

0x0009_FFFF

0x000A_FFFF

0x000B_FFFF

BANK2

(256K Bytes)

The minimum size for an erase operation is one sector. The maximum size for a program operation is one 16-bit

word. For more detailed information on flash program and erase operations, see the TMS470R1x Flash

Reference Guide (literature number SPNU194).

NOTE:

The flash external pump voltage (V_CCP) is required for all operations (program, erase,

and read).

HET RAM

The B768 device contains HET RAM. The HET RAM has a 128-instruction capability. The HET RAM is

configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET

RAM is addressed through memory select 4.

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Peripheral Selects and Base Addresses

The B768 device uses 8 of the 16 peripheral selects to decode the base addresses of the peripherals. These

peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the

SYS module.

Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 5.

Table 5. B768 Peripherals, System Module, and Flash Base Addresses

ADDRESS RANGE

CONNECTING MODULE

PERIPHERAL SELECTS

BASE ADDRESS

0 x FFFF_FFD0

0 x FFFF_FF60

0 x FFFF_FF40

0 x FFFF_FF20

0 x FFFF_FF00

0 x FFFF_FE80

0 x FFFF_FE00

0 x FFFF_FD00

0 x FFFF_FC00

0 x FFF8_0000

0 x FFF7_FD00

0 x FFF7_FC00

0 x FFF7_F900

0 x FFF7_F800

0 x FFF7_F600

0 x FFF7_F500

0 x FFF7_F400

0 x FFF7_F100

0 x FFF7_F000

0 x FFF7_EF00

0 x FFF7_ED00

0 x FFF7_EC00

0 x FFF7_EA00

0 x FFF7_E800

0 x FFF7_E600

0 x FFF7_E400

0 x FFF7_E000

0 x FFF7_DC00

0 x FFF7_D800

0 x FFF7_D700

0 x FFF7_D600

0 x FFF7_D500

0 x FFF7_D400

0 x FFF7_D200

0 x FFF7_D000

0 x FFF7_C000

0 x FFF7_0000

0 x FFE8_8000

0 x FFE8_4000

ENDING ADDRESS

0 x FFFF_FFFF

0 x FFFF_FFCB

0 x FFFF_FF5F

0 x FFFF_FF3F

0 x FFFF_FF1F

0 x FFFF_FEFF

0 x FFFF_FE7F

0 x FFFF_FD7F

0 x FFFF_FCFF

0 x FFFF_FBFF

0 x FFF7_FFFF

0 x FFF7_FCFF

0 x FFF7_FBFF

0 x FFF7_F8FF

0 x FFF7_F7FF

0 X FFF7_F5FF

0 x FFF7_F4FF

0 x FFF7_F3FF

0 x FFF7_F0FF

0 x FFF7_EFFF

0 x FFF7_EEFF

0 x FFF7_ECFF

0 x FFF7_EBFF

0 x FFF7_E9FF

0 x FFF7_E7FF

0 x FFF7_E5FF

0 x FFF7_E3FF

0 x FFF7_DFFF

0 x FFF7_DBFF

0 x FFF7_D7FF

0 x FFF7_D6FF

0 x FFF7_D5FF

0 x FFF7_D4FF

0 x FFF7_D3FF

0 x FFF7_D1FF

0 x FFF7_CFFF

0 x FFF7_BFFF

0 x FFE8_BFFF

0 x FFE8_4023

SYSTEM

N/A

RESERVED

PSA

CIM

RTI

DMA

DEC

MMC

IEM

RESERVED

HET

PS[0]

PS[1]

RESERVED

SPI1

RESERVED

SCI2

PS[2]

PS[3]

PS[4]

SCI1

RESERVED

MibADC

ECP

RESERVED

GIO

HECC2

PS[5]

PS[6]

HECC1

HECC2 RAM

HECC1 RAM

RESERVED

SPI5

PS[7]

PS[8]

PS[9]

SPI4

PS[10]

PS[11]

SPI3

SPI2

HECC3 RAM

HECC3

RESERVED

FLASH CONTROL REGISTERS

MPU CONTROL REGISTERS

PS[12]–PS[15]

N/A

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Direct-Memory Access (DMA)

The direct-memory access (DMA) controller transfers data to and from any specified location in the B768

memory map (except for restricted memory locations like the system control registers area). The DMA manages

up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The DMA

controller is connected to both the CPU and Peripheral busses, enabling these data transfers to occur in parallel

with CPU activity and thus maximizing overall system performance.

Although the DMA controller has two possible configurations, for the B768 device, the DMA controller

configuration is 32 control packets and 16 channels.

For the B768 DMA request hardwired configuration, see Table 6.

Table 6. DMA Request Lines Connections

MODULES

RESERVED

SPI1

DMA REQUEST INTERRUPT SOURCES

DMA CHANNEL

DMAREQ[0]

DMAREQ[1]

DMAREQ[2]

DMAREQ[3]

DMAREQ[4]

DMAREQ[5]

DMAREQ[6]

DMAREQ[7]

DMAREQ[8]

DMAREQ[9]

DMAREQ[10]

DMAREQ[11]

DMAREQ[12]

DMAREQ[13]

DMAREQ[14]

DMAREQ[15]

SPI1 end-receive

SPI1 end-transmit

MibADC event

SPI1DMA0

SPI1

SPI1DMA1

MibADC⁽¹⁾

MibADC⁽¹⁾/SCI1

SPI4

MibADCDMA0

MibADC G1/SCI1 end-receive

MibADC G2/SCI1 end-transmit

SPI4 end-receive

MibADCDMA1/SCI1DMA0

MibADCDMA2/SCI1DMA1

SPI4DMA0

SPI2

SPI2 end-receive

SPI2DMA0

SPI2

SPI2 end-transmit

SPI2DMA1

RESERVED

SPI4

SPI4 end-transmit

SPI4DMA1

SPI5

SPI5 end-receive

SPI5DMA0

SPI5

SPI5 end-transmit

SPI5DMA1

SCI2/SPI3

SCI2 end-receive/SPI3 end-receive

SCI2 end-transmit/SPI3 end-transmit

SCI2DMA0/SPI3DMA0

SCI2DMA1/SPI3DMA1

(1) The MibADC can be serviced by the DMA when the device is in buffered mode. For more information on buffered mode, see the

MibADC section of this data sheet and the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature

number SPNU206).

Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate

periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,

and the channels determine the priority level of the interrupt.

DMA transfers occur in one of two modes:

•

Non-request mode (used when transferring from memory to memory)

Request mode (used when transferring from memory to peripheral)

For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access

(DMA) Controller Reference Guide (literature number SPNU210).

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Interrupt Priority (IEM to CIM)

Interrupt requests originating from the B768 peripheral modules (i.e., SPI1, SPI2, or SPI3; SCI1 or SCI2; HECC1

or HECC2; RTI; etc.) are assigned to channels within the 48-channel interrupt expansion module (IEM) where,

via programmable register mapping, these channels are then mapped to the 32-channel central interrupt

manager (CIM) portion of the SYS module.

Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel

between sources.

The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt

requests can be programmed in the CIM to be of either type:

•

Fast interrupt request (FIQ)

Normal interrupt request (IRQ)

The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel order in the

CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their

associated modules, see Table 7.

Table 7. Interrupt Priority (IEM and CIM)

DEFAULT CIM INTERRUPT

MODULES

INTERRUPT SOURCES

IEM CHANNEL

LEVEL/CHANNEL

SPI1

RTI

SPI1 end-transfer/overrun

0

COMP2 interrupt

COMP1 interrupt

TAP interrupt

1

RTI

2

RTI

3

SPI2

SPI2 end-transfer/overrun

GIO interrupt A

4

GIO

5

RESERVED

HET

6

HET interrupt 1

7

SPI4

SPI4 end-transfer/overrun

SCI1 or SCI2 error interrupt

SCI1 receive interrupt

8

SCI1/SCI2

SCI1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

RESERVED

SPI5

SPI5 end-transfer/overrun

HECC1 interrupt A

HECC1

RESERVED

SPI3

SPI3 end-transfer/overrun

MibADC end event conversion

SCI2 receive interrupt

DMA interrupt 0

MibADC

SCI2

DMA

HECC3

SCI1

HECC3 interrupt A

SCI1 transmit interrupt

SW interrupt (SSI)

System

RESERVED

HET

HET interrupt 2

HECC1

RESERVED

SCI2

HECC1 interrupt B

SCI2 transmit interrupt

MibADC end Group 1 conversion

DMA interrupt 1

MibADC

DMA

GIO

GIO interrupt B

MibADC

HECC3

MibADC end Group 2 conversion

HECC3 interrupt B

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Table 7. Interrupt Priority (IEM and CIM) (continued)

DEFAULT CIM INTERRUPT

MODULES

INTERRUPT SOURCES

IEM CHANNEL

LEVEL/CHANNEL

RESERVED

HECC2

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

HECC2 interrupt A

HECC2 interrupt B

HECC2

RESERVED

For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)

Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the

TMS470R1x System Module Reference Guide (literature number SPNU189).

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MibADC

The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a

10-bit digital value.

The B768 MibADC module can function in two modes: compatibility mode, where its programmer's model is

compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in

buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion

group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by

interrupts or by the DMA.

MibADC Event Trigger Enhancements

The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.

•

Both group1 and the event group can be configured for event-triggered operation, providing up to two

event-triggered groups.

•

The trigger source and polarity can be selected individually for both group 1 and the event group from the

three options identified in Table 8.

Table 8. MibADC Event Hookup Configuration

SOURCE SELECT BITS FOR G1 OR

EVENT(G1SRC[1:0] OR EVSRC[1:0])

EVENT #

SIGNAL PIN NAME

EVENT1

EVENT2

EVENT3

EVENT4

00

01

10

11

ADEVT

HET18

HET19

N/C

For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0]) in

the AD event source register (ADEVTSRC[5:4]). For the event group, these event-triggered selections are

configured via the event group source select bits (EVSRC[1:0]) in the AD event source register

(ADEVTSRC[1:0]).

For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital

Converter (MibADC) Reference Guide (literature number SPNU206).

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Documentation Support

Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types of

documentation available include data sheets with design specifications; complete user guides for all devices and

development support tools; and hardware and software applications. Useful reference documentation includes:

•

Bulletin

–

TMS470 Microcontroller Family Product Bulletin (literature number SPNB086)

•

User's Guides

–

TMS470R1x System Module Reference Guide (literature number SPNU189)

TMS470R1x General Purpose Input/Output (GIO) Reference Guide (literature number SPNU192)

TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)

TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)

TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)

TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)

TMS470R1x High End Timer (HET) Reference Guide (literature number SPNU199)

TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)

TMS470R1x MultiBuffered Analog to Digital (MibADC) Reference Guide (literature number SPNU206)

TMS470R1x Zero-Pin Phase Locked Loop (ZPLL) Clock Module Reference Guide (literature number

SPNU212)

–

TMS470R1x F05 Flash Reference Guide (literature number SPNU213)

TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214)

TMS470R1x Class II Serial Interface A (C2SIa) Reference Guide (literature number SPNU218)

TMS470R1x JTAG Security Module (JSM) Reference Guide (literature number SPNU245)

TMS470R1x Memory Security Module (MSM) Reference Guide (literature number SPNU246)

TMS470 Peripherals Overview Reference Guide (literature number SPNU248)

•

Errata Sheet

TMS470R1B768 TMS470 Microcontrollers Silicon Errata (literature number SPNZ140)

–

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Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP

devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS

(e.g., TMS470R1B768). Texas Instruments recommends two of three possible prefix designators for its support

tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX Experimental device that is not necessarily representative of the final device's electrical specifications

TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and

reliability verification

TMS Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.

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TMS 470 R1

B

PGE

T

768

OPTIONS

PREFIX

TMS = Fully Qualified Device

FAMILY

470 = TMS470 RISC − Embedded

Microcontroller Family

TEMPERATURE RANGE

T = −40°C to 105°C

Q = −40°C to 125°C

PACKAGE TYPE

ARCHITECTURE

PGE = 144-pin Low-Profile Quad Flatpack (LQFP)

R1 = ARM7TDM1 CPU

REVISION CHANGE

= Original

DEVICE TYPE B

With 768K-Bytes Flash Memory:

60-MHz Frequency

Blank

FLASH MEMORY

768 = 768K-Bytes Flash Memory

1.8-V Core, 3.3-V I/O

Flash Program Memory

48K-Byte SRAM

ECP Module

Up to 68 I/O Pins and 1 Input-Only Pin

ZPLL Clock

1.5K-Byte HET RAM (128 Instructions)

AWD

RTI

10-Bit, 12-Input MibADC

Five SPI Modules

Two SCI Modules

Three High-End CAN [HECC] Modules

HET, 32 Channels

ECP

DMA

Figure 2. TMS470R1x Family Nomenclature

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Device Identification Code Register

The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash

device, and an assigned device-specific part number (see Figure 3). The B768 device identification code register

value is 0xn87F.

Figure 3. TMS470 Device ID Bit Allocation Register [offset = 0xFFFF_FFF0h]

31

15

16

0

Reserved

12

11

10

9

3

2

1

VERSION

R-K

TF

R/F

R-K

PART NUMBER

R-K

1

R-K

R-1

LEGEND:

For bits 3-15: R = Read only, -K = Value constant after RST

For bits 0-2: R = Read only, -1 = Value after RST

Table 9. TMS470 Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value Description

31–16 Reserved

15–12 VERSION

Reads are undefined and writes have no effect.

Silicon version (revision) bits. These bits identify the silicon version of the device. Initial device

version numbers start at 0000. The current revision for the B768 device is 0000.

11

TF

Technology family bit. This bit distinguishes the technology family core power supply:

0

1

3.3 V for F10/C10 devices

1.8 V for F05/C05 devices

10

R/F

ROM/flash bit. This bit distinguishes between ROM and flash devices:

0

1

Flash device

ROM device

9–3

2–0

PART NUMBER

1

Device-specific part number bits. These bits identify the assigned device-specific part number. The

assigned device-specific part number for the B768 device is 0001111.

Mandatory high

Bits 2, 1, and 0 are tied high by default.

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DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS

Absolute Maximum Ratings

over operating free-air temperature range, T version unless otherwise noted⁽¹⁾

(2)

Supply voltage range:

Input voltage range:

Input clamp current:

V_CC

–0.3 V to 2.5 V

–0.3 V to 4.1 V

V_CCIO, V_CCAD, V_CCP(flash pump)⁽²⁾

All input pins

I_IK(V_I< 0 or V_I> V_CCIO

)

All pins except ADIN[0:15], PORRST, TRST,

TEST, and TCK

±20 mA

I_IK(V_I< 0 or V_I> V_CCAD

ADIN[0:15]

)

±10 mA

–40°C to 105°C

–40°C to 125°C

–40°C to 150°C

–65°C to 150°C

Operating free-air temperature range, T_A:

T version

Q version

Operating junction temperature range, T_J:

Storage temperature range, T_stg:

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to their associated grounds.

Device Recommended Operating Conditions⁽¹⁾

MIN

1.81

3

NOM

MAX UNIT

V_CC

Digital logic supply voltage (core)

Digital logic supply voltage (I/O)

MibADC supply voltage

2.05

3.6

V

V_CCIO

V_CCAD

V_CCP

V_SS

3.3

0

3

Flash pump supply voltage

Digital logic supply ground

MibADC supply ground

3

V_SSAD

T_A

–0.1

–40

0.1

Operating free-air temperature

T version

Q version

105 °C

125 °C

150 °C

T_J

Operating junction temperature

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

.

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ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, T version (unless otherwise noted)⁽¹⁾

PARAMETER

Input hysteresis

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_hys

V_IL

0.15

V

All inputs⁽²⁾except

OSCIN

–0.3

2

0.8

Low-level input voltage

V

OSCIN only

0.35 V_CC

V_CCIO+ 0.3

All inputs except

OSCIN

V_IH

High-level input voltage

Input threshold voltage

OSCIN only

AWD only

0.65 V_CC

1.35

V_CC+ 0.3

1.8

V_th

V

Drain-to-source on

resistance

RDS_ON

AWD only⁽³⁾

V_OL= 0.35 V at I_OL= 2 mA

175

Ω

I_OL= I_OLMAX

I_OL= 50 µA

0.2 V_CCIO

0.2

V_OL

Low-level output voltage⁽⁴⁾

High-level output voltage⁽⁴⁾

V

I_OH= I_OHMIN

I_OH= 50 µA

0.8 V_CCIO

V_OH

I_IC

V

V_CCIO– 0.2

V_I< V_SSIO– 0.3 or

V_I> V_CCIO+ 0.3

Input clamp current (I/O pins)⁽⁵⁾

I_ILPulldown

–2

2

mA

V_I= V_SS

–1

5

1

40

–5

1

I_IHPulldown

I_ILPullup

V_I= V_CCIO

I_I

Input current (I/O pins)

Low-level output current

High-level output current

V_I= V_SS

–40

–1

µA

mA

I_IHPullup

V_I= V_CCIO

All other pins

CLKOUT, TDO

No pullup or pulldown

1

8

RST, SPInCLK,

SPInSOMI,

4

2

I_OL

V_OL= V_OLMAX

SPInSIMO⁽⁶⁾

All other output

pins⁽⁷⁾

CLKOUT, TDO

–8

–4

RST, SPInCLK,

SPInSOMI,

I_OH

V_OH= V_OHMIN

SPInSIMO⁽⁶⁾

All other output

–2

pins except RST⁽⁷⁾

SYSCLK = 60 MHz,

ICLK = 20 MHz, V_CC= 2.05 V

135

105

mA

V_CCDigital supply current (operating mode)

SYSCLK = 24 MHz,

ICLK = 12 MHz, V_CC= 2.05 V

I_CC

V_CCDigital supply current (standby mode)⁽⁸⁾

V_CCDigital supply current (halt mode)⁽⁸⁾

V_CCIODigital supply current (operating mode) No DC load, V_CCIO= 3.6 V⁽⁸⁾

OSCIN = 6 MHz, V_CC= 2.05 V

All frequencies, V_CC= 2.05 V

4

mA

µA

2

10

300

I_CCIO

V_CCIODigital supply current (standby mode)

V_CCIODigital supply current (halt mode)

No DC load, V_CCIO= 3.6 V⁽⁸⁾

µA

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

(2) This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section.

(3) These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide

(literature number SPNU189).

(4) V_OLand V_OHare linear with respect to the amount of load current (I_OL/I_OH) applied.

(5) Parameter does not apply to input-only or output-only pins.

(6) n = 1–5.

(7) The 2-mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a

low level and the other is outputting a high level, the resulting value is always low.

(8) I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ V_CCIO– 0.2 V.

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ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range, T version (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

15

UNIT

mA

µA

V_CCADsupply current (operating mode)

V_CCADsupply current (standby mode)

V_CCADsupply current (halt mode)

All frequencies, V_CCAD= 3.6 V

V_CCP= 3.6 V read operation

V_CCP= 3.6 V program and erase

I_CCAD

20

µA

55

mA

70

V_CCP= 3.6 V standby mode

operation⁽⁹⁾

I_CCP

V_CCPpump supply current

20

µA

V_CCP= 3.6 V halt mode

operation⁽⁹⁾

C_I

Input capacitance

Output capacitance

2

3

pF

C_O

(9) For flash banks/pumps in sleep mode.

Parameter Measurement Information

I_OL

Tester Pin

Electronics

Output

Under

Test

Ω

50

V_LOAD

C_L

I_OH

(A)

Where:

I

= I MAX for the respective pin

OL

(A)

= I MIN for the respective pin

OH

V

C

= 1.5 V

LOAD

(B)

= 150-pF typical load-circuit capacitance

L

A. For these values, see the "Electrical Characteristics over Recommended Operating Free-Air Temperature Range"

table.

B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.

Figure 4. Test Load Circuit

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Timing Parameter Symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,

some of the pin names and other related terminology have been abbreviated as follows:

CM

CO

ER

ICLK

M

Compaction, CMPCT

CLKOUT

RD

Read

RST

RX

Reset, RST

SCInRX

Erase

Interface clock

Master mode

S

Slave mode

SCInCLK

SPInSIMO

SPInSOMI

SPInCLK

System clock

SCInTX

SCC

SIMO

SOMI

SPC

SYS

TX

OSC, OSCI OSCIN

OSCO

P

OSCOUT

Program, PROG

R

Ready

R0

R1

Read margin 0, RDMRGN0

Read margin 1, RDMRGN1

Lowercase subscripts and their meanings are:

a

c

d

f

access time

cycle time (period)

delay time

r

rise time

su

t

setup time

transition time

valid time

fall time

v

h

hold time

w

pulse duration (width)

The following additional letters are used with these meanings:

H

L

High

Low

X

Z

Unknown, changing, or don't care level

High impedance

V

Valid

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External Reference Resonator/Crystal Oscillator Clock Option

The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load

capacitors across the external OSCIN and OSCOUT pins as shown in Figure 5a. The oscillator is a single-stage

inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and

HALT mode. TI strongly encourages each customer to submit samples of the device to the

resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will

best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over

temperature/voltage extremes.

An external oscillator source can be used by connecting a 1.8-V clock signal to the OSCIN pin and leaving the

OSCOUT pin unconnected (open) as shown in Figure 5b.

OSCIN

OSCOUT

OSCIN

OSCOUT

External

Clock Signal

(toggling 0-1.8 V)

(A)

C1

C2

Crystal

(a)

(b)

A. The values of C1 and C2 should be provided by the resonator/crystal vendor.

Figure 5. Crystal/Clock Connection

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ZPLL AND CLOCK SPECIFICATIONS

Timing Requirements for ZPLL Circuits Enabled or Disabled

MIN

4

MAX UNIT

f_(OSC)

Input clock frequency

20 MHz

t_c(OSC)

Cycle time, OSCIN

50

15

ns

t_w(OSCIL)

t_w(OSCIH)

f_(OSCRST)

Pulse duration, OSCIN low

Pulse duration, OSCIN high

OSC FAIL frequency⁽¹⁾

ns

53 kHz

(1) Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)

bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide

(literature number SPNU189).

Switching Characteristics over Recommended Operating Conditions for Clocks⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS⁽³⁾

Pipeline mode enabled

Pipeline mode disabled

Flash config mode

MIN

MAX UNIT

60 MHz

24 MHz

25 MHz

24 MHz

25 MHz

24 MHz

ns

f_(SYS)

System clock frequency⁽⁴⁾

f_(CONFIG)

f_(ICLK)

System clock frequency

Interface clock frequency

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

Flash config mode

f_(ECLK)

External clock output frequency for ECP module

16.7

41.6

40

t_c(SYS)

Cycle time, system clock

Cycle time, interface clock

ns

t_c(CONFIG)

t_c(ICLK)

ns

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

ns

41.6

40

ns

t_c(ECLK)

Cycle time, ECP module external clock output

41.6

ns

(1) When PLLDIS = 0, f_(SYS)= M

נ

f_(OSC)/R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8}. R is the system-clock divider determined by the

CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit

(GLBCTRL.3).

When PLLDIS = 1, f_(SYS)= f_(OSC)/R, where R = {1,2,3,4,5,6,7,8}.

f_(ICLK)= f_(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]

bits in the SYS module.

(2) f_(ECLK)= f_(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(3) Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).

(4) Flash Vread must be set to 5 V to achieve maximum system clock frequency.

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Switching Characteristics over Recommended Operating Conditions for External Clocks^(1)(2)(3)

(see Figure 6 and Figure 7)

PARAMETER

TEST CONDITIONS

SYSCLK or MCLK⁽⁴⁾

MIN

MAX

UNIT

0.5t_c(SYS)– t_f

t_w(COL)

t_w(COH)

t_w(EOL)

t_w(EOH)

Pulse duration, CLKOUT low

ICLK: X is even or 1⁽⁵⁾

ICLK: X is odd and not 1⁽⁵⁾

SYSCLK or MCLK⁽⁴⁾

0.5t_c(ICLK)– t_f

ns

0.5t_c(ICLK)+ 0.5t_c(SYS)– t_f

0.5t_c(SYS)– t_r

Pulse duration, CLKOUT high

Pulse duration, ECLK low

Pulse duration, ECLK high

ICLK: X is even or 1⁽⁵⁾

0.5t_c(ICLK)– t_r

ns

ICLK: X is odd and not 1⁽⁵⁾

N is even and X is even or odd

N is odd and X is even

0.5t_c(ICLK)– 0.5t_c(SYS)– t_r

0.5t_c(ECLK)– t_f

N is odd and X is odd and not 1

N is even and X is even or odd

N is odd and X is even

0.5t_c(ECLK)+ 0.5t_c(SYS)– t_f

0.5t_c(ECLK)– t_r

N is odd and X is odd and not 1

0.5t_c(ECLK)– 0.5t_c(SYS)– t_r

(1) X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.

(2) N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.

(3) CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.

(4) Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).

(5) Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).

t

w(COH)

CLKOUT

t

w(COL)

Figure 6. CLKOUT Timing Diagram

t

w(EOH)

ECLK

t

w(EOL)

Figure 7. ECLK Timing Diagram

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RST AND PORRST TIMINGS

Timing Requirements for PORRST

(see Figure 8)

MIN

MAX UNIT

V_CCPORL

V_CClow supply level when PORRST must be active during power up

0.6

V

V_CChigh supply level when PORRST must remain active during power up and become

active during power down

V_CCPORH

V_CCIOPORL

V_CCIOPORH

1.5

V_CCIOlow supply level when PORRST must be active during power up

1.1

V_CCIOhigh supply level when PORRST must remain active during power up and become

active during power down

2.75

V_IL

Low-level input voltage after V_CCIO> V_CCIOPORH

0.2 V_CCIO

0.5

V

V_IL(PORRST)

t_su(PORRST)r

t_su(VCCIO)r

t_h(PORRST)r

t_su(PORRST)f

t_h(PORRST)rio

t_h(PORRST)d

Low-level input voltage of PORRST before V_CCIO> V_CCIOPORL

Setup time, PORRST active before V_CCIO> V_CCIOPORLduring power up

Setup time, V_CCIO> V_CCIOPORLbefore V_CC> V_CCPORL

Hold time, PORRST active after V_CC> V_CCPORH

V

0

1

8

1

0

ms

µs

ms

ns

Setup time, PORRST active before V_CC≤ V_CCPORHduring power down

Hold time, PORRST active after V_CCV_CCIOPORH

Hold time, PORRST active after V_CC< V_CCPORL

t_{su(PORRST)fio}Setup time, PORRST active before V_CC≤ V_CCIOPORHduring power down

t_su(VCCIO)f

Setup time, V_CC< V_CCPORLbefore V_CCIO< V_CCIOPORL

V_CCP/V_CCIO

V_CCIOPORH

V_CCIO

t

h(PORRST)rio

t

su(VCCIO)f

V_CC

V_CCPORH

t

su(PORRST)f

t

h(PORRST)r

t

su(PORRST)fio

t

V_CCIOPORL

su(PORRST)f

V_CCPORL

t

h(PORRST)r

V_CC

t

su(VCCIO)r

V /V

CCP CCIO

t

h(PORRST)d

t

su(PORRST)r

V_IL(PORRST)

V_IL

V_IL(PORRST)

PORRST

NOTE: V_CCIO> 1.1 V before V_CC> 0.6 V

Figure 8. PORRST Timing Diagram

Switching Characteristics over Recommended Operating Conditions for RST⁽¹⁾

PARAMETER

MIN

MAX UNIT

Valid time, RST active after PORRST inactive

Valid time, RST active (all others)

4112t_c(OSC)

8t_c(SYS)

t_v(RST)

ns

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see the "Switching Characteristics for Output Timings versus

Load Capacitance" table.

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JTAG Scan Interface Timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)

MIN

50

MAX UNIT

t_c(JTAG)

Cycle time, JTAG low and high period

Setup time, TDI, TMS before TCK rise (TCKr)

Hold time, TDI, TMS after TCKr

ns

t_{su(TDI/TMS - TCKr)}

t_{h(TCKr -TDI/TMS)}

t_{h(TCKf -TDO)}

t_{d(TCKf -TDO)}

15

Hold time, TDO after TCKf

10

Delay time, TDO valid after TCK fall (TCKf)

45

ns

T CK

t

c(J TAG )

t

c

(

J

T

A

G

)

T MS

T D I

t

s

u

(

T

D

I

/

T

M

S

Ć

T

C

K

r

)

t

h

(

T

C

K

r

Ć

T

D

I

/

T

M

S

)

T

D

O

t

h

(

T

C

K

f

Ć

T

D

O

)

t

d

(

T

C

K

f

Ć

T

D

O

)

Figure 9. JTAG Scan Timings

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OUTPUT TIMINGS

Switching Characteristics for Output Timings versus Load Capacitance _L)

(see Figure 10)

PARAMETER

MIN

0.5

1.5

3

MAX UNIT

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

2.50

5

t_r

t_f

t_r

t_f

t_r

t_f

Rise time, CLKOUT, AWD, TDO

ns

9

4.5

0.5

1.5

3

12.5

2.5

5

Fall time, CLKOUT, AWD, TDO

ns

9

4.5

2.5

5

12.5

8

14

ns

23

Rise time, SPInCLK, SPInSOMI, SPInSIMO⁽¹⁾

Fall time, RST, SPInCLK, SPInSOMI, SPInSIMO⁽¹⁾

Rise time, all other output pins

9

13

2.5

5

32

8

14

ns

23

9

13

2.5

6.0

12

18

3

32

12

28

ns

50

73

12

8.5

16

23

28

ns

50

Fall time, all other output pins

73

(1) Where n = 1-5.

t_r

t_f

V_CC

80%

Output

20%

0

Figure 10. CMOS-Level Outputs

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INPUT TIMINGS

Timing Requirements for Input Timings⁽¹⁾

(see Figure 11)

MIN

MAX UNIT

t_pw

Input minimum pulse width

t_c(ICLK)+ 10

ns

(1) t_c(ICLK)= interface clock cycle time = 1 / f_(ICLK)

t_pw

V_CC

Input

80%

20%

0

Figure 11. CMOS-Level Inputs

FLASH TIMINGS

Timing Requirements for Program Flash⁽¹⁾

MIN

TYP

16

MAX

UNIT

t_prog(16-bit)

t_prog(Total)

t_{erase(sector)}

t_wec

Half word (16-bit) programming time

768K-byte programming time⁽²⁾

Sector erase time

4

200

20

µs

6

s

1.7

Write/erase cycles at T_A= –40°C to 125°C

50000

cycles

(1) For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.

(2) The 768K-byte programming time includes overhead of state machine.

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SPIn MASTER MODE TIMING PARAMETERS

SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)(see Figure 12)

NO.

MIN

MAX

UNIT

1

t_c(SPC)M

Cycle time, SPInCLK⁽⁴⁾

100

256t_c(ICLK)

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)M– t_r0.5t_c(SPC)M+ 5

2⁽⁵⁾

3⁽⁵⁾

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

0.5t_c(SPC)M– t_f0.5t_c(SPC)M+ 5

0.5t_c(SPC)M– t_r0.5t_c(SPC)M+ 5

t_{d(SPCH-SIMO)M}Delay time, SPInCLK high to SPInSIMO valid (clock polarity = 0)

10

t_{d(SPCL-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

Delay time, SPInCLK low to SPInSIMO valid (clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)

10

t_c(SPC)M– 5 – t_f

t_c(SPC)M– 5 – t_r

t_{su(SOMI-SPCL)M}Setup time, SPInSOMI before SPInCLK low (clock polarity = 0)

t_{su(SOMI-SPCH)M}Setup time, SPInSOMI before SPInCLK high (clock polarity = 1)

6

4

t_{v(SPCL-SOMI)M}

t_{v(SPCH-SOMI)M}

Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)

Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) When the SPI is in master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥(PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(ICLK)≥ 100 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSIMO

SPInSOMI

Master Out Data Is Valid

6

7

Master In Data

Must Be Valid

Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 0)

SPIn Master Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)(see Figure 13)

(1) The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

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SPIn Master Mode External Timing Parameters (continued)

(CLOCK PHASE = 1, SPInCLK = output, SPInSIMO = output, and SPInSOMI = input) (see Figure 13)

NO.

MIN

MAX

UNIT

1

t_c(SPC)M

Cycle time, SPInCLK⁽⁴⁾

100

256t_c(ICLK)

ns

t_w(SPCH)M

t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)M– t_r

0.5t_c(SPC)M– t_f

0.5t_c(SPC)M– t_r

0.5t_c(SPC)M+ 5

2⁽⁵⁾

3⁽⁵⁾

ns

Valid time, SPInCLK high after SPInSIMO data valid

(clock polarity = 0)

t_{v(SIMO-SPCH)M}

t_{v(SIMO-SPCL)M}

t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

t_{v(SPCH-SOMI)M}

t_{v(SPCL-SOMI)M}

0.5t_c(SPC)M–15

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

Valid time, SPInCLK low after SPInSIMO data valid

(clock polarity = 1)

0.5t_c(SPC)M– 15

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 0)

0.5t_c(SPC)M– 5 – t_r

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 1)

0.5t_c(SPC)M– 5 – t_f

Setup time, SPInSOMI before SPInCLK high

(clock polarity = 0)

6

4

Setup time, SPInSOMI before SPInCLK low

(clock polarity = 1)

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

(4) When the SPI is in master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(ICLK)≥ 100 ns.

(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSIMO

Master Out Data Is Valid

6

Data Valid

7

Master In Data

Must Be Valid

SPInSOMI

Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 1)

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SPIn SLAVE MODE TIMING PARAMETERS

SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 0, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)(see Figure 14)

NO.

MIN

MAX

UNIT

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

100

256t_c(ICLK)

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)S– 0.25t_c(ICLK)0.5t_c(SPC)S+ 0.25t_c(ICLK)

2⁽⁶⁾

3⁽⁶⁾

ns

Delay time, SPInCLK high to SPInSOMI valid

(clock polarity = 0)

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{v(SPCH-SOMI)S}

t_{v(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{v(SPCL-SIMO)S}

t_{v(SPCH-SIMO)S}

6 + t_r

4⁽⁶⁾

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

ns

Delay time, SPInCLK low to SPInSOMI valid

(clock polarity = 1)

6 + t_f

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

t_c(SPC)S– 6 – t_r

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

t_c(SPC)S– 6 – t_f

Setup time, SPInSIMO before SPInCLK low

(clock polarity = 0)

6

Setup time, SPInSIMO before SPInCLK high

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(5) When the SPIn is in slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(ICLK)≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPISOMI Data Is Valid

SPInSOMI

SPInSIMO

6

7

SPISIMO Data

Must Be Valid

Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 0)

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SPIn Slave Mode External Timing Parameters

(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)^(1)(2)(3)(4)(see Figure 15)

NO.

MIN

MAX

UNIT

1

t_c(SPC)S

Cycle time, SPInCLK⁽⁵⁾

100

256t_c(ICLK)

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

Pulse duration, SPInCLK low (clock polarity = 1)

Pulse duration, SPInCLK low (clock polarity = 0)

Pulse duration, SPInCLK high (clock polarity = 1)

0.5t_c(SPC)S– 0.25t_c(ICLK)0.5t_c(SPC)S+ 0.25t_c(ICLK)

2⁽⁶⁾

3⁽⁶⁾

ns

Valid time, SPInCLK high after SPInSOMI data valid

(clock polarity = 0)

t_{v(SOMI-SPCH)S}

t_{v(SOMI-SPCL)S}

t_{v(SPCH-SOMI)S}

t_{v(SPCL-SOMI)S}

t_{su(SIMO-SPCH)S}

t_{su(SIMO-SPCL)S}

t_{v(SPCH-SIMO)S}

t_{v(SPCL-SIMO)S}

0.5t_c(SPC)S– 6 – t_r

4⁽⁶⁾

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

ns

Valid time, SPInCLK low after SPInSOMI data valid

(clock polarity = 1)

0.5t_c(SPC)S– 6 – t_f

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

0.5t_c(SPC)S– 6 – t_r

Valid time, SPInSOMI data valid after SPInCLK low

(clock polarity = 1)

0.5t_c(SPC)S– 6 – t_f

Setup time, SPInSIMO before SPInCLK high

(clock polarity = 0)

6

Setup time, SPInSIMO before SPInCLK low

(clock polarity = 1)

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 0)

Valid time, SPInSIMO data valid after SPInCLK low

(clock polarity = 1)

(1) The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(ICLK), where PS = prescale value set in SPInCTL1[12:5].

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(4) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(5) When the SPIn is in slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(ICLK)≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(ICLK)≥ 100 ns.

(6) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).

1

SPInCLK

(clock polarity = 0)

2

3

SPInCLK

(clock polarity = 1)

4

5

SPInSOMI

SPISOMI Data Is Valid

6

Data Valid

7

SPISIMO Data Must

Be Valid

SPInSIMO

Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 1)

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SCIn ISOSYNCHRONOUS MODE TIMINGS INTERNAL CLOCK

Timing Requirements for Internal Clock SCIn Isosynchronous Mode^(1)(2)(3)

(see Figure 16)

(BAUD + 1)

IS EVEN OR BAUD = 0

IS ODD AND BAUD ≠ 0

UNIT

MIN

MAX

MIN

MAX

Cycle time,

SCInCLK

t_c(SCC)

2t_c(ICLK)

2²⁴t_c(ICLK)

3t_c(ICLK)

(2²⁴-1) t_c(ICLK)

ns

Pulse duration,

SCInCLK low

t_w(SCCL)

t_w(SCCH)

0.5t_c(SCC)– t_f

0.5t_c(SCC)– t_r

0.5t_c(SCC)+ 5

0.5t_c(SCC)+ 0.5t_c(ICLK)– t_f

0.5t_c(SCC)– 0.5t_c(ICLK)– t_r

0.5t_c(SCC)+ 0.5t_c(ICLK)

0.5t_c(SCC)– 0.5t_c(ICLK)

Pulse duration,

SCInCLK high

Delay time,

t_d(SCCH-TXV)

SCInCLK high to

SCInTX valid

10

ns

Valid time,

SCInTX data

after SCInCLK

low

t_v(TX)

t_c(SCC)– 10

t_c(ICLK)+ t_f+ 20

–t_c(ICLK)+ t_f+ 20

t_c(SCC)– 10

t_c(ICLK)+ t_f+ 20

–t_c(ICLK)+ t_f+ 20

Setup time,

SCInRX before

SCInCLK low

t_su(RX-SCCL)

Valid time,

SCInRX data

after SCInCLK

low

t_v(SCCL-RX)

(1) BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.

(2) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(3) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

t

c(SCC)

t

w(SCCH)

t

w(SCCL)

SCICLK

SCITX

SCIRX

t

v(TX)

t

d(SCCHĆTXV)

Data Valid

t

su(RXĆSCCL)

t

v(SCCLĆRX)

Data Valid

A. Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the

asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK

falling edge.

Figure 16. SCIn Isosynchronous Mode Timing Diagram for Internal Clock

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SCIn ISOSYNCHRONOUS MODE TIMINGS EXTERNAL CLOCK

Timing Requirements for External Clock SCIn Isosynchronous Mode⁽¹⁾⁽²⁾

(see Figure 17)

MIN

MAX

UNIT

ns

t_c(SCC)

Cycle time, SCInCLK⁽³⁾

8t_c(ICLK)

t_w(SCCH)

t_w(SCCL)

t_d(SCCH-TXV)

t_v(TX)

t_su(RX-SCCL)

t_v(SCCL-RX)

Pulse duration, SCInCLK high

0.5t_c(SCC)– 0.25t_c(ICLK)

0.5t_c(SCC)+ 0.25t_c(ICLK)

2t_c(ICLK)+ 12 + t_r

ns

Pulse duration, SCInCLK low

ns

Delay time, SCInCLK high to SCInTX valid

Valid time, SCInTX data after SCInCLK low

Setup time, SCInRX before SCInCLK low

Valid time, SCInRX data after SCInCLK low

ns

2t_c(SCC)– 10

0

ns

2t_c(ICLK)+ 10

ns

(1) t_c(ICLK)= interface clock cycle time = 1/f_(ICLK)

(2) For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.

(3) When driving an external SCInCLK, the following must be true: t_c(SCC)≥ 8t_c(ICLK)

.

t

c(SCC)

t

w(SCCH)

t

w(SCCL)

SCICLK

SCITX

SCIRX

t

v(TX)

t

d(SCCHĆTXV)

Data Valid

t

su(RXĆSCCL)

t

v(SCCLĆRX)

Data Valid

A. Data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the

asynchronous mode. Data transmission occurs on the SCICLK rising edge, and data reception occurs on the SCICLK

falling edge.

Figure 17. SCIn Isosynchronous Mode Timing Diagram for External Clock

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HIGH-END TIMER (HET) TIMINGS

Minimum PWM Output Pulse Width:

This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale

factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.

Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK

For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns

Minimum Input Pulses that Can Be Captured:

The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the

HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which

is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.

Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK

For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns

NOTE:

Once the input pulse width is greater than LRP, the resolution of the measurement is

still HRP. (That is, the captured value gives the number of HRP clocks inside the

pulse.)

Abbreviations:

hr = HET high resolution divide rate = 1, 2, 3,...63, 64

lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32

High resolution clock period = HRP = hr/SYSCLK

Loop resolution clock period = LRP = hr*lr/SYSCLK

HIGH-END CAN CONTROLLER (HECCn) MODE TIMINGS

Dynamic Characteristics for the CANnHTX and CANnHRX Pins

PARAMETER

MIN

MAX UNIT

t_d(CANnHTX)

t_d(CANnHRX)

Delay time, transmit shift register to CANnHTX pin⁽¹⁾

15

5

ns

Delay time, CANnHRX pin to receive shift register

(1) These values do not include rise/fall times of the output buffer.

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MULTI-BUFFERED A-TO-D CONVERTER (MibADC)

The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances

the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on V_SS

and V_CC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to AD_REFLO

unless otherwise noted.

Resolution

10 bits (1024 values)

Assured

Monotonic

Output conversion code

00h to 3FFh [00 for V_AI≤ AD_REFLO; 3FFh for V_AI≥ AD_REFHI

]

Table 10. MibADC Recommended Operating Conditions⁽¹⁾

MIN

V_SSAD

MAX

V_CCAD

UNIT

AD_REFHI

AD_REFLO

V_AI

A-to-D high-voltage reference source

V

A-to-D low-voltage reference source

Analog input voltage

V_CCAD

V_SSAD– 0.3

V_CCAD+ 0.3

Analog input clamp current⁽²⁾

(V_AI< V_SSAD– 0.3 or V_AI> V_CCAD+ 0.3)

I_AIC

–2

2

mA

(1) For V_CCADand V_SSADrecommended operating conditions, see the "Device Recommended Operating Conditions" table.

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 11. Operating Characteristics Over Full Ranges of Recommended Operating Conditions⁽¹⁾⁽²⁾

PARAMETER

DESCRIPTION/CONDITIONS

See Figure 18.

MIN

TYP

MAX UNIT

500

R_I

C_I

Analog input resistance

250

Ω

Conversion

Sampling

10 pF

30 pF

Analog input capacitance

See Figure 18.

I_AIL

Analog input leakage current

AD_REFHIinput current

See Figure 18.

–1

3

1

5

µA

I_ADREFHI

AD_REFHI= 3.6 V, AD_REFLO= V_SSAD

AD_REFHI- AD_REFLO

mA

Conversion range over which specified

accuracy is maintained

CR

3.6

V

Difference between the actual step width

and the ideal value. See Figure 19.

E_DNL

Differential nonlinearity error

±1.5 LSB

±2.0 LSB

Maximum deviation from the best straight

line through the MibADC. MibADC

transfer characteristics, excluding the

quantization error. See Figure 20.

E_INL

Integral nonlinearity error

Maximum value of the difference

between an analog value and the ideal

midstep value. See Figure 21.

E _TOT

Total error/absolute accuracy

±2 LSB

(1) V_CCAD= AD_REFHI

(2) 1 LSB = (AD_REFHI– AD_REFLO)/2¹⁰for the MibADC

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External

MibADC

R_s

R_i

Sample Switch

Input Pin

Sample

Capacitor

Parasitic

Capacitance

R_leak

V_src

C_i

Figure 18. MibADC Input Equivalent Circuit

Multi-Buffer ADC Timing Requirements

MIN

0.05

1

NOM

MAX UNIT

t_c(ADCLK)

t_d(SH)

t_d)

Cycle time, MibADC clock

µs

Delay time, sample and hold time

Delay time, conversion time

0.55

1.55

(1)

t_d(SHC)

Delay time, total sample/hold and conversion time

(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for

more details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

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The differential nonlinearity error shown in Figure 19 (sometimes referred to as differential linearity) is the

difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

DifferentialLinearity

Error(1/2 LSB)

1 LSB

0 ... 010

DifferentialLinearity

Error(- 1/2 LSB)

0 ... 001

1 LSB

0 ... 000

0

1

2

3

4

5

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 19. Differential Nonlinearity (DNL)

The integral nonlinearity error shown in Figure 20 (sometimes referred to as linearity error) is the deviation of the

values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

0 ... 101

Ideal

Transition

Actual

Transition

0 ... 100

0 ... 011

At Transition

011/100

(ć 1/2 LSB)

0 ... 010

0 ... 001

End-Point Lin. Error

At Transition

001/010 (ć 1/4 LSB)

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 20. Integral Nonlinearity (INL) Error

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The absolute accuracy or total error of an MibADC as shown in Figure 21 is the maximum value of the difference

between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(-1 1/4 LSB)

0 ... 011

0 ... 010

Total Error

At Step 0 ... 001

(1/2 LSB)

0 ... 001

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI- AD_REFLO)/2¹⁰

Figure 21. Absolute Accuracy (Total) Error

Thermal Resistance Characteristics

PARAMETER

R_θJA

°C/W

43

R_θJC

6.5

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Revision History

This revision history highlights the changes made to the device-specific data sheet SPNS108.

Table 12. Revision History

SPNS108A to SPNS108B

Corrected the device identification code register value from 0xn83F to 0xn87F in Device Identification Code Register.

SPNS108 to SPNS108A

Revised the Family Nomenclature drawing to add Q version of the temperature range.

Revised "Absolute Maximum Ratings" table to add Q version of the temperature range.

Revised "Device Recommended Operating Conditions" table to add Q version of the temperature range.

Added note to PORRST Timing Diagram.

Changed T_Arange to –40°C to 125°C on t_wecin "Timing Requirements for Program Flash" table.

Added t_wecMIN value of 50000 and deleted MAX value in "Timing Requirements for Program Flash" table.

Changed t_{erase(sector)}TYP value to 1.7 and removed MAX value in "Timing Requirements for Program Flash" table.

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PACKAGE OPTION ADDENDUM

www.ti.com

19-Mar-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TMS470R1B768PGET

NRND

LQFP

PGE

144

60 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

M

0,08

0,17

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/C 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	TMS470R1B768PGE
厂家：	TEXAS INSTRUMENTS
描述：	32-BIT, FLASH, 60MHz, RISC MICROCONTROLLER, PQFP144, PLASTIC, LQFP-144 时钟微控制器外围集成电路
文件：	总49页 (文件大小：524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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