TMS470R1VF338EPZA [TI]
16/32-BIT RISC FLASH MICROCONTROLLERS; 16位/ 32位RISC闪存微控制器
| 型号： | TMS470R1VF338EPZA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16/32-BIT RISC FLASH MICROCONTROLLERS |
| 文件： | 总56页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
z
z
High-Performance Static CMOS Technology
– Class II Serial Interface (C2SIb)
– Two Selectable Data Rates
– Normal Mode 10.4 Kbps and 4X Mode
41.6 Kbps
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (48-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
z
High-End Timer (HET)
– 27 Programmable I/O Channels (VF338x):
– 23 High-Resolution Pins
– Utilizes Big-Endian Format
– 4 Standard-Resolution Pins
– 16 Programmable I/O Channels (VF348x):
– 14 High-Resolution Pins
– 2 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
z
Integrated Memory
– 256K-Byte Program Flash
– One Bank With 14 Contiguous Sectors
– Internal State Machine for Programming
and Erase
– 64-Instruction Capacity
– 10K-Byte Static RAM (SRAM) (VF3x8)
– 12K-Byte Static RAM (SRAM) (VF3x82)
z
10-Bit Multi-Buffered ADC (MibADC)
12-Channel (VF338x)
16-Channel (VF348x)
z
Operating Features
– Core Supply Voltage (V ): 1.81 V - 2.06 V
CC
– 64-Word FIFO Buffer
– Core Supply Voltage (V ): 1.70 V - 2.06 V for
CC
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
VF3x8xE when used from - 40C to 85C
– I/O Supply Voltage (V
): 3.0 V - 3.6 V
CCIO
– Low-Power Modes: STANDBY and HALT
– Industrial and Automotive Temperature
Ranges
– Calibration Mode and Self-Test Features
z
z
z
Eight External Interrupts
Flexible Interrupt Handling
z
470+ System Module
5 Dedicated General-Purpose I/O (GIO) Pins,
1 Input-Only GIO Pin, and 48 Additional
Peripheral I/Os (VF338x)
– 32-Bit Address Space Decoding
– Bus Supervision for Mem and Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
z
z
11 Dedicated GIO Pins,1 Input-Only GIO Pin,
and 38 Additional Peripheral I/Os (VF348x)
– System Integrity and Failure Detection
z
z
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
z
z
Compatible ROM Device
Six Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communications Interfaces
(SCIs)
On-Chip Scan-Base Emulation Logic,
†
IEEE Standard 1149.1 (JTAG)Test-Access Port
z
z
100-Pin Plastic Low-Profile Quad Flatpack
(PZ Suffix)
24
Development System Support Tools Available
– Code Composer Studio™ Integrated Devel-
opment Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
– 2 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Standard CAN Controller (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are property of their respective owners.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
† The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
TMS470R1VF338x 100-PIN PZ PACKAGE (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
AWD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
ADIN[11]
ADIN[10]
ADIN[9]
ADIN[8]
HET[18]
HET[19]
HET[20]
HET[21]
HET[22]
AD
REFHI
AD
REFLO
V
SPI2ENA
SPI2SOMI
SPI2SIMO
CCAD
V
SSAD
TMS
TMS2
SPI2CLK
V
V
SS
CC
V
V
CC
SS
HET[0]
HET[1]
C2SIbRX
C2SIbTX
V
C2SIbLPN
HET[24]
SS
V
CC
FLTP2
FLTP1
HET[31]
HET[30]
V
HET[29]
CCP
HET[2]
HET[3]
HET[4]
HET[5]
HET[6]
HET[7]
SCI2TX
SCI2RX
GIOA[1]/INT[1]/ECLK
†
GIOA[0]/INT0
TEST
TRST
99
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
† GIOA[0]/INT0 (pin 28) is an input-only GIO pin.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
TMS470R1VF348x 100-PIN PZ PACKAGE (TOP VIEW)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
AWD
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
ADIN[11]
ADIN[14]
ADIN[10]
ADIN[13]
HET[18]
HET[19]
HET[20]
HET[21]
SPI2SCS
ADIN[9]
ADIN[12]
ADIN[8]
SPI2ENA
SPI2SOMI
SPI2SIMO
AD
REFHI
AD
REFLO
V
SPI2CLK
CCAD
V
V
SSAD
CC
TMS
V
SS
TMS2
C2SIbRX
C2SIbTX
V
SS
V
C2SIbLPN
HET[24]
CC
HET[0]
V
HET[31]
SS
V
SCI2TX
CC
FLTP2
FLTP1
SCI2RX
GIOA[3]/INT3
GIOA[2]/INT2
GIOA[1]/INT1/ECLK
V
CCP
HET[2]
HET[4]
HET[6]
HET[7]
†
GIOA[0]/INT0
TEST
TRST
99
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
† GIOA[0]/INT0 (pin 28) is an input-only GIO pin.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
description
†
The TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, and TMS470R1VF3482 devices are mem-
bers of the Texas Instruments TMS470R1x family of general-purpose16/32-bit reduced instruction set computer
(RISC) microcontrollers. The VF3x8x microcontroller offers high performance utilizing the high-speed
ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while
maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection
of bytes numbered upwards from zero. The TMS470R1VF3x8x utilizes the big-endian format where the most
significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest
numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF3x8x RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF338/VF348/VF3382/VF3482 device contains the following:
z
z
z
z
z
z
z
z
z
z
z
z
z
ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
256K-byte flash
10K-byte SRAM (VF3x8)
12K-byte SRAM (VF3x82)
Zero-pin phase-locked loop (ZPLL) clock module
Analog watchdog (AWD) timer
Real-time interrupt (RTI) module
Two serial peripheral interface (SPI) modules
Two serial communications interface (SCI) modules
Standard CAN controller (SCC)
Class II serial interface (C2SIb)
10-bit multi-buffered analog-to-digital converter (MibADC), 12-input channels (VF338x), 16-input channels
(VF348x)
z
z
z
High-end timer (HET) controlling 27 I/Os (VF338x), controlling 16 I/Os (VF348x)
External Clock Prescale (ECP)
Up to 53 I/O pins and 1 input-only pin (VF338x), up to 49 I/O pins and 1 input-only pin (VF348x)
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection;
memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal
interrupt sources; device clock control; and parallel signature analysis (PSA). This data sheet includes device-
specific information such as memory and peripheral select assignment, interrupt priority, and a device memory
map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
The VF3x8x memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. In
pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information
on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).
† Throughout the remainder of this document, the TMS470R1VF338, TMSVF348, TMS470R1VF3382 and TMS470R1VF3482 device names,
where generic, shall be referred to as TMS470R1VF3x8x or VF3x8x; where applicable to only the 10K SRAM devices, VF3x8; where applicable
to only the 12K SRAM devices, VF3x82; where applicable to only VF338 and VF3382 as VF338x; where applicable to only VF348 and VF3482
as VF348x;and, where unique, shall be referred to as either their full device name or VF338 or VF348 or VF3382 or VF3482.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
description (continued)
The VF3x8x device has six communication interfaces: two SPIs, two SCIs, an SCC, and a C2SIb. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between
the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The SCC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy
and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The C2SIb allows the VF3x8x to transmit and receive messages on a class II network
†
following an SAE J1850 standard. For more detailed functional information on the SPI, SCI, and SCC periph-
erals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively).
For more detailed functional information on the C2SIb peripheral, see the TMS470R1x Class II Serial Interface
B (C2SIb) Reference Guide (literature number SPNU214).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
The VF3x8x device has a 10-bit-resolution sample-and-hold MibADC. The MibADC channels can be converted
individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the Mi-
bADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
‡
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF3x8x device modules. For
more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase Locked Loop (ZPLL)
Clock Module Reference Guide (literature number SPNU212).
The VF3x8x device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the pe-
ripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
device characteristics
The TMS470R1VF3x8x device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1VF3x8x device except the SYSTEM and CPU, which are
generic. The COMMENTS column aids the user in software-programming and references device-specific in-
formation.
† SAE Standard J1850 Class B Data Communication Network Interface
‡ ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal
reference.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
device characteristics (continued)
Table 1. Device Characteristics
DEVICE DESCRIPTION
TMS470R1VF338X
DEVICE DESCRIPTION
TMS470R1VF348X
CHARACTERISTICS
COMMENTS FOR VF3X8X
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Flash is pipeline-capable
256K-Byte Flash
256K-Byte Flash
The VF3x8 RAM is implemented in one 10K array
selected by two memory-select signals. The VF3x82
RAM is implemented in one 12K array selected by two
memory-select signals. (See the Memory Selection
Assignment table, Table 2).
INTERNAL
MEMORY
10K-Byte SRAM (VF338)
12K-Byte SRAM (VF3382) 12K-Byte SRAM (VF3482)
10K-Byte SRAM (VF348)
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 4). And for the 1K peripheral address ranges and
their peripheral selects, see the VF338/VF348x Peripherals, System Module, and Flash Base Addresses table (Table 3).
CLOCK
ZPLL
ZPLL
Zero-pin PLL has no external loop filter pins.
Port A has six (6) external pins
(VF338x – GIOA[2]/INT2 and GIOA[3]/INT3 are not
available.)
Port A has eight (8) external pins and Port B has four (4)
external pins (VF348x)
GENERAL-PURPOSE
I/Os
5 I/O
1 Input only
11 I/O
1 Input only
ECP
YES
1
YES
1
C2SIb
1 (3-pin)
1 (2-pin)
1 (3-pin)
1 (2-pin)
SCI2hasnoexternalclockpin, onlytransmit/receivepins
(SCI2TX and SCI2RX)
SCI
CAN
1 SCC
1 SCC
Standard CAN controller
(HECC and/or SCC)
SPI
1 (5-pin)
1 (4-pin)
VF338x SPI1 (5-pin), SPI2 (4-pin)
SPI2 has no chip select pin
2 (5-pin)
(5-pin, 4-pin or 3-pin)
TheVF338xand VF348x deviceshave both the logic and
registers for a full 32-I/O HET implemented, even though
not all 32 pins are available externally.
Thehigh-resolution(HR)SHAREfeatureallowsevenHR
pins to share the next higher odd HR pin structures. This
HR sharing is independent of whether or not the odd pin
is available externally. If an odd pin is available externally
and shared, then the odd pin can only be used as a
general-purpose I/O. For more information on HR
SHARE, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
HET with
XOR Share
27 I/O
16 I/O
HET RAM
MibADC
64-Instruction Capacity
64-Instruction Capacity
12-channel MibADC (VF338x), 16-channel MibADC
(VF348x). Both the logic and registers for a full
16-channel MibADC are present. Capable of being event
triggered from a user-selectable event source.
10-bit, 12-channel
64-word FIFO
10-bit, 16-channel
64-word FIFO
When used from -40C to 85C, the core voltage range for
VF3x8xE devices is 1.70 - 2.06 V
CORE VOLTAGE
1.81 - 2.06 V (see note)
1.81 - 2.06 V (see note)
I/O VOLTAGE
PINS
3.0 - 3.6 V
100
3.0 - 3.6 V
100
PACKAGE
PZ
PZ
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
functional block diagram
External Pins
External Pins
VCCP
OSCIN
RAM
FLASH
(256K Bytes)
14 Sectors
OSCOUT
PLLDIS
(10K Bytes) (VF3x8)
(12K Bytes) (VF3x82)
ZPLL
FLTP1
FLTP2
ADIN[11:0]†
ADEVT
CPU Address/Data Bus
MibADC
with
64-Word
FIFO
ADREFHI
ADREFLO
VCCAD
TRST
TCK
TDI
TMS470R1x
CPU
VSSAD
TDO
TMS
HET with
XOR Share
(64-Word)
HET [31:29, 24]‡
HET[22:0]‡
TMS470R1x 470+ SYSTEM MODULE
TMS2
RST
CANSTX
CANSRX
SCC
SCI1
AWD
SCI1CLK
SCI1TX
SCI1RX
TEST
PORRST
CLKOUT
SCI2TX
SCI2RX
SCI2
C2SIbTX
C2SIbRX
C2SIbLPN
C2SIb
GIOA[1]/INT[1]/
ECLK
SPI2
GIO
SPI1
ECP
† ADIN[11:0] for VF338x and ADIN[15:0] for VF348.
‡ HET[31:29, 24] and HET[22:0] for VF338, HET[31, 24] and HET[21:18, 13:10, 8, 7, 6, 4, 2, 0] for VF348.
§ The SPI2 chip select pin (SPI2SCS) is only applicable to the VF348x device.
¶ GIOA[0]/INT[0] is an input-only GIO pin.
# GIOA[2]/INT[2], GIOA[3]/INT[3], and GIOB[3:0] pins are not applicable to the VF338x device.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
Terminal Functions
TERMINAL
VF338
INTERNAL
PULLUP/
PULLDOWN§
TYPE†‡
DESCRIPTION
NAME
VF348
HIGH-END TIMER (HET)
HET[0]
88
89
95
96
97
98
99
100
55
56
20
19
18
17
16
15
14
13
49
48
47
46
45
35
91
–
HET[1]
HET[2]
97
–
HET[3]
The VF338x and VF348x devices have both the logic and registers for a
full 32-I/O HET implemented, even though not all 32 pins are available
externally
HET[4]
98
–
HET[5]
HET[6]
99
100
55
–
HET[7]
Timer input capture or output compare. The HET[31:0] applicable pins
can be programmed as general-purpose input/output (GIO) pins.
HET[22:0] are high-resolution pins and HET[31:29, 24] are standard-
resolution pins for VF338x.
HET[21:18, 13:10, 8, 7, 6, 4, 2, 0] are high-resolution pins and HET[31,
24] are standard-resolution pins for VF348x.
HET[8]
HET[9]
HET[10]
HET[11]
HET[12]
HET[13]
HET[14]
HET[15]
HET[16]
HET[17]
HET[18]
HET[19]
HET[20]
HET[21]
HET[22]
HET[24]
HET[28]
HET[29]
HET[30]
HET[31]
20
19
18
17
–
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent of
whether or not the odd pin is available externally. If an odd pin is available
externally and shared, then the odd pin can only be used as a general-
purpose I/O. For more information on HR SHARE, see the TMS470R1x
High-End Timer (HET) Reference Guide (literature number SPNU199).
3.3-V I/O
IPD
–
–
–
49
48
47
46
–
The HET[19] or HET[18] pins can also be used as a user-selectable event
source to event trigger the MibADC event group or group1 providing the
associated register source bits are properly configured and defined. For
the internal device connections, see the MibADC section of this data
sheet. And for more detailed functional information on the MibADC, see
the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC)
Reference Guide (literature number SPNU206).
35
¶
¶
–
–
32
33
34
–
–
34
STANDARD CAN CONTROLLER (SCC)
CANSRX
CANSTX
60
61
59
60
3.3-V I/O
3.3-V I/O
SCC receive pin or GIO pin
SCC transmit pin or GIO pin
IPU
CLASS II SERIAL INTERFACE (C2SIb)
C2SIbLPN
C2SIbRX
C2SIbTX
36
38
37
36
38
37
3.3-V I/O
IPD
IPD
C2SIb module loopback enable pin or GIO pin
3.3-V I/O
3.3-V I/O
C2SIb module receive data input pin or GIO pin
C2SIb module transmit data output pin or GIO pin
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
¶ N/A on the VF348x device. For the VF338x device only, the HET[28] signal is only connected to the pad not to a package pin.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
VF338
INTERNAL
TYPE†‡
PULLUP/
DESCRIPTION
NAME
VF348
PULLDOWN§
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT0
28
29
28
29
3.3-V I
GIOA[1]/INT1/
ECLK
General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.
GIOA[7:0]/INT[7:0] are interrupt-capable pins.
GIOA[2]/INT2
GIOA[3]/INT3
GIOA[4]/INT4
GIOA[5]/INT5
GIOA[6]/INT6
GIOA[7]/INT7
GIOB[0]
–
–
30
31
25
24
23
22
16
15
14
13
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out
function of the external clock prescale (ECP) module.
IPD
IPD
3.3-V I/O
3.3-V I/O
25
24
23
22
–
GIOA[2]/INT[2] and GIOA[3]/INT[3] pins are not applicable on the VF338x
device.
GIOB[1]
–
General-purpose input/output pins (VF348x only).
GIOB[2]
–
GIOB[3]
–
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
MibADC event input. ADEVT can be programmed as a GIO pin.The
ADEVT pin can also be used as a user-selectable event source to event
trigger the MibADC event group or group1 providing the associated
register source bits are properly configured and defined. For the internal
device connections, see the MibADC section of this data sheet.
ADEVT
67
66
3.3-V I/O
IPD
ADIN[0]
ADIN[1]
ADIN[2]
ADIN[3]
ADIN[4]
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADIN[12]
ADIN[13]
ADIN[14]
ADIN[15]
75
74
73
72
71
70
69
68
79
78
77
76
–
75
74
73
72
71
69
68
67
82
80
78
76
81
79
77
70
MibADC analog input pins
The VF338x device has only 12 input channels but all S/W registers are
capable. ADIN[15:12] pins are not applicable to the VF338x device.
3.3-V I
The VF348x device has all 16 input channels.
–
–
–
3.3-V
REF I
ADREFHI
ADREFLO
VCCAD
VSSAD
80
81
83
84
MibADC module high-voltage reference input
MibADC module low-voltage reference input
GND
REF I
3.3-V
PWR
82
83
85
86
MibADC analog supply voltage
MibADC analog ground reference
GND
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
VF338
INTERNAL
PULLUP/
PULLDOWN§
TYPE†‡
DESCRIPTION
NAME
VF348
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
5
1
2
5
1
2
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
SPI1SCS
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as
a GIO pin.
SPI1SIMO
SPI1SOMI
3
4
3
4
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as
a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2CLK
SPI2ENA
41
44
41
44
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.
(This pin is not applicable to the VF338x device.)
SPI2SCS
SPI2SIMO
SPI2SOMI
–
45
42
43
3.3-V I/O
IPD
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as
a GIO pin.
42
43
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as
a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
Crystal connection pin or external clock input
OSCIN
8
7
8
7
1.8-V I
OSCOUT
1.8-V O
External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
becomes the system clock. If not in bypass mode, TI recommends that this
pinbe connected togroundor pulled downto ground by anexternalresistor.
PLLDIS
51
51
3.3-V I
IPD
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
SCI1CLK
SCI1RX
SCI1TX
62
64
63
61
63
62
3.3-V I/O
IPD
IPU
IPU
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
3.3-V I/O
3.3-V I/O
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2RX
SCI2TX
30
31
32
33
3.3-V I/O
IPU
IPU
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
3.3-V I/O
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output
of SYSCLK, ICLK, or MCLK.
CLKOUT
PORRST
59
21
58
21
3.3-V I/O
3.3-V I
IPD
IPD
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset. On this pin, the output buffer is
implemented as an open drain (drives low only).
RST
10
10
3.3-V I/O
IPU
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
Terminal Functions (Continued)
TERMINAL
VF338
INTERNAL
PULLUP/
PULLDOWN§
TYPE†‡
DESCRIPTION
NAME
VF348
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC network
circuit is connected. If the user is not using AWD, TI recommends that this
pin be connected to ground or pulled down to ground by an external
resistor.
AWD
50
50
3.3-V I/O
IPD
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189) and the
application note Analog Watchdog Resistor, Capacitor and Discharge
Interval Selection Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
TCK
TDI
54
52
54
52
3.3-V I
3.3-V I
IPD
Test clock. TCK controls the test hardware (JTAG)
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
IPU
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
TDO
53
53
3.3-V O
IPD
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
TEST
TMS
27
84
85
27
87
88
3.3-V I
3.3-V I
3.3-V I
IPD
IPU
IPU
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG)
Serial input for controlling the second TAP. TI recommends that this pin
be connected to VCCIO or pulled up to VCCIO by an external resistor.
TMS2
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
TRST
26
26
3.3-V I
IPD
FLASH
FLTP1
FLTP2
93
92
95
94
Flash test pads 1 and 2. For proper operation, these pins must not be
connected [no connect (NC)].
NC
3.3-V
PWR
VCCP
94
96
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
9
9
40
66
87
91
40
65
90
93
1.8-V
PWR
VCC
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
Digital I/O supply voltage
12
58
12
57
3.3-V
PWR
VCCIO
SUPPLY GROUND CORE
6
6
39
65
86
90
39
64
89
92
VSS
GND
Core supply ground reference
SUPPLY GROUND DIGITAL I/O
11
57
11
56
VSSIO
GND
Digital I/O supply ground reference
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
VF338X/VF348X DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF3x8x device.
0xFFFF_FFFF
Memory (4G Bytes)
SYSTEM
Reserved
0xFFFF_FFFF
0xFFFF_FD00
0xFFF8_0000
System Module Control Registers
(512K Bytes)
0xFFF8_0000
0xFFF7_FFFF
HET
SPI1
SCI2
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
Reserved
Flash Control Registers
Reserved
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
SCI1
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E400
MibADC
GIO/ECP
Reserved
0xFFE8_4024
0xFFE8_4023
MPU Control Registers
Reserved
0xFFE8_4000
0xFFE8_3FFF
SCC
0xFFF7_E000
0xFFF7_DC00
0xFFF7_D800
SCC RAM
Reserved
0xFFE0_0000
RAM
(10K Bytes)
(VF3x8)
SPI2
Reserved
C2SIb
0xFFF7_D400
0xFFF7_CC00
0xFFF7_C800
Reserved
RAM
(12K Bytes)
(VF3x82)
Program
and
0xFFF0_0000
Data Area
0x0000_001F
0x0000_001C
FIQ
IRQ
FLASH
(256K Bytes)
14 Sectors
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
Reserved
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
0x0000_0020
0x0000_001F
Exception, Interrupt, and
Reset Vectors
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. Memory Map
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
MEMORY
SIZE
STATIC MEM
CTL REGISTER
MPU
MEMORY BASE ADDRESS REGISTER
0 (fine)
1 (fine)
2 (fine)
3 (fine)
4 (fine)
FLASH
FLASH
RAM
NO
NO
MFBAHR0 and MFBALR0
MFBAHR1 and MFBALR1
MFBAHR2 and MFBALR2
MFBAHR3 and MFBALR3
MFBAHR4 and MFBALR4
256K
10K (VF3x8)†
12K (VF3x82)†
1K
YES
YES
RAM
HET RAM
SMCR1
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the
memory-base address register.
RAM
The VF3x8 device contains 10K of internal static RAM configurable by the SYS module to be addressed within
the range of 0x0000_0000 to 0xFFE0_0000. This VF3x8 RAM is implemented in one 10K array selected by
two memory-select signals. The VF3x82 device contains 12K of internal static RAM configurable by the SYS
module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. This VF3x82 RAM is implemented
in one 12K array selected by two memory-select signals. This VF3x8x configuration imposes an additional
constraint on the memory map for RAM; the starting addresses for both RAM memory selects cannot be offset
from each other by the multiples of the size of the physical RAM (i.e., 12K for the VF3x82 device). The VF3x8x
RAM is addressed through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections of this document.
flash protection keys
The VF3x8x device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the fourprotection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on both VF338x and VF348x are
located in the last 4 words of the first 8K sector. For more detailed information on the flash protection keys and
the FMPKEY control register, see the Optional Quadruple Protection Keys and Programming the Protection
Keys portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
FLASH read
The VF3x8x flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
Note: The flash external pump voltage (V
) is required for all operations (program, erase, and read).
CCP
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz (versus a system
clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides
two 32-bit pipelined words to the CPU. Also in pipeline mode, the flash can be read with no wait states when
memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
Note: After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the
VF3x8x device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash config-
uration mode bit (GLBCTRL.4) will override pipeline mode.
flash program and erase
The VF3x8x device flash has one 256K-byte bank that consists of fourteen sectors. These fourteen sectors
are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
8K Bytes
8K Bytes
8K Bytes
8K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
32K Bytes
8K Bytes
8K Bytes
8K Bytes
8K Bytes
0x00000000
0x00002000
0x00004000
0x00006000
0x00008000
0x00010000
0x00018000
0x00020000
0x00028000
0x00030000
0x00038000
0x0003A000
0x0003C000
0x0003E000
0x00001FFF
0x00003FFF
0x00005FFF
0x00007FFF
0x0000FFFF
0x00017FFF
0x0001FFFF
0x00027FFF
0x0002FFFF
0x00037FFF
0x00039FFF
0x0003BFFF
0x0003DFFF
0x0003FFFF
1
2
3
4
5
6
7
8
9
10
11
12
13
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
Note: The flash external pump voltage (V
) is required for all operations (program, erase, and read).
CCP
Formoredetailedinformationonflashprogramanderaseoperations, seetheTMS470R1xF05FlashReference
Guide (literature number SPNU213).
HET RAM
The VF3x8x device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
XOR share
The VF3x8x HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high-
resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET.
For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
peripheral selects and base addresses
The VF3x8x device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 3.
Table 3. Peripherals, System Module, and Flash Base Addresses
ADDRESS RANGE
CONNECTING MODULE
PERIPHERAL SELECTS
BASE ADDRESS
0XFFFF_FD00
0XFFF8_0000
0XFFF7_FC00
0XFFF7_F800
0XFFF7_F500
0XFFF7_F400
0XFFF7_F000
0XFFF7_EC00
0XFFF7_E400
0XFFF7_E000
0XFFF7_DC00
0XFFF7_D800
0XFFF7_D400
0XFFF7_CC00
0XFFF7_C800
0XFFF7_C000
0XFFF0_0000
0XFFE8_8000
0XFFE8_4000
ENDING ADDRESS
0XFFFF_FFFF
0XFFFF_FCFF
0XFFF7_FFFF
0XFFF7_FBFF
0XFFF7_F7FF
0XFFF7_F4FF
0XFFF7_F3FF
0XFFF7_EFFF
0XFFF7_EBFF
0XFFF7_E3FF
0XFFF7_DFFF
0XFFF7_DBFF
0XFFF7_D7FF
0XFFF7_D3FF
0XFFF7_CBFF
0XFFF7_C7FF
0XFFF7_BFFF
0XFFE8_BFFF
0XFFE8_4023
SYSTEM
N/A
N/A
RESERVED
HET
PS[0]
PS[1]
SPI1
SCI2
PS[2]
SCI1
ADC
PS[3]
PS[4]
GIO/ECP
RESERVED
SCC
PS[5] - PS[6]
PS[7]
SCC RAM
PS[8]
RESERVED
SPI2
PS[9]
PS[10]
RESERVED
C2SIb
PS[11] - PS[12]
PS[13]
RESERVED
RESERVED
FLASH CONTROL REGISTERS
MPU CONTROL REGISTERS
PS[14] - PS[15]
N/A
N/A
N/A
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
interrupt priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the VF3x8x device only uses 21 of those
interrupt request signals. The request channels are maskable so that individual channels can be selectively
disabled. All interrupt requests can be programmed in the CIM to be of either type:
z
z
Fast interrupt request (FIQ)
Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and
31 [lowest] priority). For these channel priorities and the associated modules, see Table 4.
Table 4. Interrupt Priority
MODULES
SPI1
INTERRUPT SOURCES
SPI1 end-transfer/overrun
INTERRUPT LEVEL/CHANNEL
0
RTI
COMP2 interrupt
COMP1 interrupt
TAP interrupt
1
RTI
2
RTI
3
SPI2
SPI2 end-transfer/overrun
Interrupt A
4
GIO
5
RESERVED
HET
6
Interrupt 1
7
RESERVED
SCI1/SCI2
SCI1
8
SCI1/SCI2 error interrupt
SCI1 receive interrupt
C2SIb interrupt
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
C2SIb
RESERVED
RESERVED
SCC
Interrupt A
RESERVED
MibADC
SCI2
End event conversion
SCI2 receive interrupt
RESERVED
RESERVED
SCI1
SCI1 transmit interrupt
SW interrupt (SSI)
System
RESERVED
HET
Interrupt 2
RESERVED
SCC
Interrupt B
SCI2
SCI2 transmit interrupt
End Group 1 conversion
MibADC
RESERVED
GIO
Interrupt B
MibADC
RESERVED
End Group 2 conversion
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF3x8x MibADC module can function in two modes: compatibility mode, where it’s programmer’s model
is compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or
in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by
interrupts.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
z
z
Both group1 and the event group can be configured for event-triggered operation, providing up to two event-
triggered groups.
The trigger source and polarity can be selected individually for both group 1 and the event group from the
three options identified in Table 5.
Table 5. MibADC Event Hookup Configuration
SOURCE SELECT BITS FOR G1 OR EVENT
EVENT #
SIGNAL PIN NAME
(G1SRC[1:0] or EVSRC[1:0])
EVENT1
EVENT2
EVENT3
EVENT4
00
01
10
11
ADEVT
HET18
HET19
RESERVED
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
z
z
Code Composer Studio™ IDE
–
–
–
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Optimizing C compiler
–
–
–
–
–
–
–
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
z
Assembly language tools (assembler and linker)
–
–
–
–
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
z
z
TMS470R1x CPU Simulator
–
–
–
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
Allow high-speed JTAG communication to the TMS470R1x emulator or target board
–
For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documen-
tation includes:
z
User’s Guides
–
–
–
–
–
–
–
–
–
–
–
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
TMS470R1x System Module Reference Guide (literature number SPNU189)
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide
(literature number SPNU212)
–
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide
(literature number SPNU214)
z
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 33 8 2 PZ
Q
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family: 470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
C = Masked ROM
F = Flash
L = ROM-less
B = System Emulator for Development Tools
R = RAM
CPU Type:
R1 = ARM7TDMI CPU
Device Type:
33 = ’33 Devices Containing the Following Modules:
– ZPLL Clock
– 1K-Byte HET RAM (64 Instructions)
– Analog Watchdog (AWD)
– Real-Time Interrupt (RTI)
– 10-Bit, 12-Input Multi-buffered Analog-to-Digital
Converter (MibADC)†
– Two Serial Peripheral Interface (SPI) Modules
– Two Serial Communications Interface (SCI) Modules
– Class II Serial Interface (C2SIb)
– Standard Controller Area Network (CAN) [SCC]
– High-End Timer (HET)
– External Clock Prescaler (ECP)
Program Memory Size
Device Sub-type
8 =
0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
2 = Blank – 10 KB SRAM
– 12 KB SRAM
=
2
Operating Free-Air
A = –40°C to 85°C
T = –40°C to105°C
Q = –40°C to 125°C
Temperature Ranges:
Package:
PZ = 100-Pin Plastic Low-Profile Quad Flatpack (LQFP)
† The VF348x device contains a 10-bit, 16-input MibADC.
Figure 2. TMS470R1x Family Nomenclature
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 6). The VF3x8x device identification code
register value is 0x0857.
Table 6. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17 BIT 16
Reserved
FFFF_FFF0
BIT 15
14
13
12
11
TF
10
9
8
7
6
5
4
3
2
1
1
1
BIT 0
1
VERSION
R-K
R/F
R-K
PART NUMBER
R-K
R-K
R-1
R-1
R-1
LEGEND:
For bits 3–15: R = Read only, -K = Value constant after RESET
For bits 0–2: R = Read only, -1 = Value after RESET
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
VERSION. Silicon version (revision) bits
Bits 15:12
These bits identify what version of silicon the device is. Initial device version numbers
start at "0000".
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/flash bit
This bit distinguishes between ROM and flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
Bits 2:0
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF3x8x device is: 0001010.
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
device part numbers
Table 7 lists all the available TMS470R1VF3x8x devices.
†
Table 7. Device Part Number
PROGRAM MEMORY
PACKAGE
TEMPERATURE RANGES
DEVICE PART
NUMBER
FLASH
ROM
100-PIN
LQFP
−40°C TO 85°C
−40°C TO 105°C
−40°C TO 125°C
EEPROM
TMS470R1VF338PZQ
TMS470R1VF338PZ-T
TMS470R1VF338PZA
TMS470R1VF348PZQ
TMS470R1VF348PZ-T
TMS470R1VF348PZA
TMS470R1VF338APZQ
TMS470R1VF338APZ-T
TMS470R1VF338APZA
TMS470R1VF348APZQ
TMS470R1VF348APZ-T
TMS470R1VF348APZA
TMS470R1VF338EPZQ
TMS470R1VF338EPZ-T
TMS470R1VF338EPZA
TMS470R1VF348EPZQ
TMS470R1VF348EPZ-T
TMS470R1VF348EPZA
TMS470R1VF3382APZQ
TMS470R1VF3382APZ-T
TMS470R1VF3382APZA
TMS470R1VF3482APZQ
TMS470R1VF3482APZ-T
TMS470R1VF3482APZA
TMS470R1VF3382EPZQ
TMS470R1VF3382EPZ-T
TMS470R1VF3382EPZA
TMS470R1VF3482EPZQ
TMS470R1VF3482EPZ-T
TMS470R1VF3482EPZA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
† The various part numbers listed in this table differ due to differences in either electrical specifications or functional errata. Electrical differences
will be noted in this datasheet. For functional errata, see the errata document for the specific part number you are using.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, Q version
(unless otherwise noted)†
Supply voltage ranges: V , V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
CCF
CC
Supply voltage ranges: V
, V
, V
(flash pump) (see Note 1) . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1V
CCP
CCIO
CCAD
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input clamp current: I (V < 0 or V > V
)
CCIO
IK
I
I
‡
All pins except ADIN[0:11] , PORRST, TRST, TEST and TCK . . . . . . . . . . . . . . ±20 mA
(V < 0 or V > V
I
)
CCAD
IK
I
I
‡
ADIN[0:11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating free-air temperature ranges, T : A version (VF348x). . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 85°C
A
T version (VF348x) . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 105°C
Q version (VF338x). . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 125°C
Operating junction temperature range, T A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 115°C
J
T version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 130°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65°C to 150°C
stg
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ ADIN[0:11] for VF338x only and ADIN[0:15] for VF348x only.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions§
MIN
1.81
1.70
3
NOM
MAX
2.06
2.06
3.6
UNIT
− 40C to 125C
V
V
V
VCC
Digital logic supply voltage (Core)
− 40C to 85C (VF3x8xE only)
VCCIO
VCCAD
VCCP
VSS
3.3
3.3
3.3
0
Digital logic supply voltage (I/O)
ADC supply voltage
3
3.6
V
V
3
3.6
Flash pump supply voltage
Digital logic supply ground
ADC supply ground
V
VSSAD
− 0.1
− 40
− 40
− 40
− 40
− 40
− 40
0.1
85
V
A version (VF348x)
T version (VF348x)
Q version (VF338x)
A version
°C
°C
°C
°C
°C
°C
TA
105
125
115
130
150
Operating free-air temperature
Operating junction temperature
TJ
T version
Q version
§ All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
.
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Vhys
VIL
Input hysteresis
0.15
V
All inputs‡ except OSCIN
OSCIN only
− 0.3
− 0.3
0.8
V
V
Low-level input voltage
High-level input voltage
0.35 VCC
VCCIO + 0.3
VCC + 0.3
All inputs except OSCIN
OSCIN only
2
VIH
0.65 VCC
Vth
AWD only
AWD only§
Input threshold voltage
1.35
1.8
45
V
RDSON
VOL = 0.35V @ IOL = 8mA
IOL = IOL MAX
IOL = 50 μA
Drain to source on resistance
Ω
0.2 VCCIO
Low-level output voltage¶
VOL
V
0.2
IOH = IOH MIN
0.8 VCCIO
High-level output voltage¶
VOH
V
IOH = 50 μA
VCCIO − 0.2
VI < VSSIO − 0.3 or
VI > VCCIO + 0.3
Input clamp current (I/O pins)#
IIC
−2
2
mA
I
I
IL Pulldown
IH Pulldown
VI = VSS
−1
5
1
40
−5
1
VI = VCCIO
VI = VSS
II
Input current (I/O pins)
IIL Pullup
IH Pullup
μA
−40
−1
−1
I
VI = VCCIO
All other pins
No pullup or pulldown
VOL = VOL MAX
1
CLKOUT, AWD, TDO
8
RST, SPI1CLK,
SPI1SIMO, SPI1SOMI,
SPI2CLK, SPI2SIMO,
SPI2SOMI
Low-level output
current
V
OL = VOL MAX
IOL
4
2
mA
mA
All other output pins||
CLKOUT, TDO
VOL = VOL MAX
VOH = VOH MIN
−8
−4
−2
SPI1CLK, SPI1SIMO,
SPI1SOMI, SPI2CLK,
SPI2SIMO, SPI2SOMI
High-level output
current
V
OH = VOH MIN
IOH
All other output pins||
VOH = VOH MIN
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 31.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
,For flash pumps/banks in sleep mode.
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted) (continued)†
PARAMETER
TEST CONDITIONS
SYSCLK = 48 MHz,
ICLK = 24 MHz, VCC = 2.06 V
MIN
TYP
MAX
UNIT
70
mA
VCC digital supply current (operating mode)
SYSCLK = 24 MHz,
ICLK = 12 MHz, VCC = 2.06 V
50
mA
ICC
VCC digital supply current (standby mode)K
VCC digital supply current (halt mode)K
VCCIO digital supply current (operating mode)
OSCIN = 6 MHz, VCC = 2.06 V
All frequencies, VCC = 2.06 V
No DC load, VCCIO = 3.6 Vo
No DC load, VCCIO = 3.6 Vo
3.0
1.0
10
mA
mA
mA
μA
ICCIO
VCCIO digital supply current (standby mode)
300
No DC load, VCCIO = 3.6 Vo
All frequencies, VCCAD = 3.6 V
All frequencies, VCCAD = 3.6 V
All frequencies, VCCAD = 3.6 V
VCCIO digital supply current (halt mode)
VCCAD supply current (operating mode)
300
15
20
20
45
70
μA
mA
μA
ICCAD
V
V
CCAD supply current (standby mode)
CCAD supply current (halt mode)
μA
V
CCP = 3.6 V read operation
mA
mA
VCCP = 3.6 V program and erase
VCCP = 3.6 V standby mode
operationK
ICCP
VCCP pump supply current
20
20
μA
μA
VCCP = 3.6 V halt mode
operationK
CI
Input capacitance
Output capacitance
2
3
pF
pF
CO
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 31.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
¶ Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
,For flash pumps/banks in sleep mode.
I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
Output
Under
Test
50 Ω
VLOAD
CL
IOH
Where: IOL
IOH
=
=
=
=
IOL MAX for the respective pin (see Note A)
IOH MIN for the respective pin (see Note A)
1.5 V
VLOAD
CL
150-pF typical load-circuit capacitance (see Note B)
NOTES: A. For these values, see the electrical characteristics over recommended operating free-air temperature range table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
Compaction, CMPCT
CLKOUT
RD
Read
RST
RX
Reset, RST
SCInRX
Erase
Interface clock
Master mode
S
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
SCC
SIMO
SOMI
SPC
SYS
TX
OSC, OSCI OSCIN
OSCO
P
OSCOUT
Program, PROG
R
Ready
R0
R1
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
Lowercase subscripts and their meanings are:
a
c
d
f
access time
cycle time (period)
delay time
r
rise time
su
t
setup time
transition time
valid time
fall time
v
h
hold time
w
pulse duration (width)
The following additional letters are used with these meanings:
H
High
X
Z
Unknown, changing, or don’t care
level
L
Low
High impedance
V
Valid
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a single-
stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measure-
ment and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temper-
ature/voltage extremes.
An external oscillator source can be used by connecting a 1.8V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 4b.
OSCIN
OSCOUT
OSCIN
OSCOUT
External
Clock Signal
(toggling 0–1.8 V)
C1
(see Note A)
Crystal
(a)
C2
(see Note A)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Crystal/Clock Connection
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
ZPLL and clock specifications
timing requirements for ZPLL circuits enabled or disabled
MIN
4
MAX
UNIT
MHz
ns
f(OSC)
20
Input clock frequency
tc(OSC)
50
15
15
Cycle time, OSCIN
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
Pulse duration, OSCIN low
Pulse duration, OSCIN high
ns
ns
OSC FAIL frequency†
53
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks‡§
TEST CONDITIONS¶
Pipeline mode enabled
Pipeline mode disabled
MIN
MAX
48
PARAMETER
System clock frequency#
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
f(SYS)
24
f(CONFIG)
f(ICLK)
24
System clock frequency - flash config mode
Interface clock frequency
25
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
24
25
f(ECLK)
External clock output frequency for ECP Module
24
20.8
41.6
41.6
40
tc(SYS)
Cycle time, system clock
ns
tc(CONFIG)
tc(ICLK)
Cycle time, system clock - flash config mode
Cycle time, interface clock
ns
Pipeline mode enabled
Pipeline mode disabled
Pipeline mode enabled
Pipeline mode disabled
ns
41.6
40
ns
ns
tc(ECLK)
Cycle time, ECP module external clock output
41.6
ns
‡ f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f
(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module
¶ Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
ZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡
§
NO.
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK¶
MIN
MAX
UNIT
0.5tc(SYS) – tf
ICLK, X is even or 1#
ICLK, X is odd and not 1#
SYSCLK or MCLK¶
tw(COL)
0.5tc(ICLK) – tf
0.5tc(ICLK)+ 0.5tc(SYS) – tf
0.5tc(SYS) – tr
1
Pulse duration, CLKOUT low
ns
ICLK, X is even or 1#
tw(COH)
tw(EOL)
tw(EOH)
0.5tc(ICLK) – tr
2
3
4
Pulse duration, CLKOUT high
Pulse duration, ECLK low
Pulse duration, ECLK high
ns
ns
ns
ICLK, X is odd and not 1#
N is even and X is even or odd
N is odd and X is even
0.5tc(ICLK)– 0.5tc(SYS) – tr
0.5tc(ECLK) – tf
0.5tc(ECLK) – tf
0.5tc(ECLK)+ 0.5tc(SYS) – tf
0.5tc(ECLK) – tr
N is odd and X is odd and not 1
N is even and X is even or odd
N is odd and X is even
0.5tc(ECLK) – tr
0.5tc(ECLK)– 0.5tc(SYS) – tr
N is odd and X is odd and not 1
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
RST and PORRST timings
timing requirements for PORRST (see Figure 7)
MIN
MAX
NO.
UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
0.6
V
VCC highsupplylevelwhenPORRSTmustremainactiveduringpowerupandbecome
active during power down
VCCPORH
VCCIOPORL
VCCIOPORH
1.5
V
V
V
VCCIO low supply level when PORRST must be active during power up
1.1
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
2.75
0.2 VCCIO
0.5
VIL
Low-level input voltage after VCCIO > VCCIOPORH
V
VIL(PORRST)
tsu(PORRST)r
tsu(VCCIO)r
th(PORRST)r
tsu(PORRST)f
th(PORRST)rio
th(PORRST)d
tsu(PORRST)fio
tsu(VCCIO)f
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
Hold time, PORRST active after VCC > VCCPORH
V
0
0
1
8
1
0
0
0
3
5
ms
ms
ms
μs
ms
ms
ns
ns
6
Setup time, PORRST active before VCC ≤ VCCPORH during power down
Hold time, PORRST active after VCC > VCCIOPORH
7
8
Hold time, PORRST active after VCC < VCCPORL
9
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
10
11
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
11
VCC
VCC
VCCPORH
VCCPORH
7
6
6
10
7
VCCIOPORL
VCC
VCCIOPORL
VCCPORL
VCCPORL
5
3
VCCP/VCCIO
9
VIL(PORRST)
VIL
VIL
VIL
VIL VIL(PORRST)
PORRST
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST†
PARAMETER
MIN
MAX
UNIT
4112tc(OSC)
8tc(SYS)
Valid time, RST active after PORRST inactive
tv(RST)
ns
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from flash
(flash pump stabilization time)
tfsu
456tc(OSC)
ns
† Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
50
MAX
NO.
1
UNIT
ns
tc(JTAG)
Cycle time, JTAG low and high period
Setup time, TDI, TMS before TCK rise (TCKr)
Hold time, TDI, TMS after TCKr
tsu(TDI/TMS - TCKr)
th(TCKr -TDI/TMS)
th(TCKf -TDO)
td(TCKf -TDO)
15
2
ns
15
3
ns
10
4
Hold time, TDO after TCKf
ns
45
5
Delay time, TDO valid after TCK fall (TCKf)
ns
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 8. JTAG Scan Timing
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 9)
MIN
0.5
1.5
3
MAX
2.50
5
PARAMETER
UNIT
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL= 50 pF
tr
tf
tr
tf
tr
Rise time, CLKOUT, AWD, TDO
Fall time, CLKOUT, AWD, TDO
ns
9
4.5
0.5
1.5
3
12.5
2.5
5
ns
ns
ns
ns
ns
9
4.5
2.5
5
12.5
8
14
23
32
8
Rise time, SPInCLK, SPInSOMI, SPInSIMO†
9
13
2.5
5
14
23
32
10
25
45
65
10
25
45
65
Fall time, RST, SPInCLK, SPInSOMI, SPInSIMO†
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
9
13
2.5
6.0
12
18
3
Rise time, all other output pins
Fall time, all other output pins
8.5
16
23
tf
† n = 1 and 2
tr
tf
VCC
80%
80%
Output
20%
20%
0
Figure 9. CMOS-Level Outputs
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
input timings
timing requirements for input timings† (see Figure 10)
MIN
MAX
UNIT
tpw
tc(ICLK) + 10
Input minimum pulse width
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
VCC
Input
80%
80%
20%
20%
0
Figure 10. CMOS-Level Inputs
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
flash timings
timing requirements for program flash†
MIN
TYP
16
2
MAX
200
8
UNIT
tprog(16-bit)
4
Half word (16-bit) programming time
μs
256K-byte programming time‡
tprog(Total)
s
s
terase(sector)
2
15
Sector erase time
twec
Write/erase cycles at TA = 125°C
100
cycles
ns
91tc(SYS)
91tc(SYS)
46tc(SYS)
tfp(RST)
tfp(SLEEP)
tfp(STDBY)
Flash pump settling time from RST to SLEEP
Initial flash pump settling time from SLEEP to STANDBY
Initial flash pump settling time from STANDBY to ACTIVE
ns
ns
† For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
‡ The 256K-byte programming times include overhead of state machine.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
MAX
NO.
MIN
UNIT
Cycle time, SPInCLK ¶
tc(SPC)M
256tc(ICLK)
1
100
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
0.5tc(SPC)M – tr
0.5tc(SPC)M – tf
0.5tc(SPC)M – tf
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
2#
3#
ns
ns
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
td(SPCH-SIMO)M
10
10
4#
5#
6#
ns
ns
ns
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCL)M
tc(SPC)M – 5 – tr/f
6
Valid time, SPInSIMO data valid
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
6
4
4
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
7#
ns
Validtime, SPInSOMIdatavalidafterSPInCLKhigh
(clock polarity = 1)
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the “switching characteristics for output timings versus load capacitance” table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
For PS values of 0:
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPInSOMI
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 12)
MIN
NO.
MAX
UNIT
Cycle time, SPInCLK ¶
tc(SPC)M
256tc(ICLK)
100
1
ns
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
0.5tc(SPC)M – tr
0.5tc(SPC)M – tf
0.5tc(SPC)M – tf
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
0.5tc(SPC)M + 5
Pulse duration, SPInCLK high (clock polarity = 0)
Pulse duration, SPInCLK low (clock polarity = 1)
Pulse duration, SPInCLK low (clock polarity = 0)
Pulse duration, SPInCLK high (clock polarity = 1)
2#
3#
ns
ns
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
tv(SIMO-SPCH)M
tv(SIMO-SPCL)M
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
0.5tc(SPC)M – 10
4#
5#
6#
7#
ns
ns
ns
ns
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 10
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
6
4
4
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
For PS values of 0:
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
Data Valid
7
Master In Data
Must Be Valid
SPInSOMI
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO.
MIN
MAX
UNIT
Cycle time, SPInCLK#
tc(SPC)S
256tc(ICLK)
1
100
ns
Pulse duration, SPInCLK high
(clock polarity = 0)
tw(SPCH)S
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
6 + tr
2||
3||
4||
5||
6||
7||
ns
ns
ns
ns
ns
ns
Pulse duration, SPInCLK low
(clock polarity = 1)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
tw(SPCL)S
Pulse duration, SPInCLK high
(clock polarity = 1)
tw(SPCH)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
td(SPCH-SOMI)S
td(SPCL-SOMI)S
tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity = 0)
t
c(SPC)S – 6 – tr
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity = 1)
t
c(SPC)S – 6 – tf
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
6
6
6
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 0)
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 1)
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
c(SPC)S = 2tc(ICLK) ≥ 100 ns.
For PS values of 0:
t
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPISOMI Data Is Valid
SPInSOMI
6
7
SPISIMO Data
Must Be Valid
SPInSIMO
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 14)
NO.
MIN
MAX
UNIT
Cycle time, SPInCLK#
tc(SPC)S
256tc(ICLK)
1
100
ns
Pulse duration, SPInCLK high
(clock polarity = 0)
tw(SPCH)S
0.5tc(SPC)S–0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
2||
3||
4||
5||
6||
7||
ns
ns
ns
ns
ns
ns
Pulse duration, SPInCLK low
(clock polarity = 1)
tw(SPCL)S
0.5tc(SPC)S–0.25tc(ICLK)
Pulse duration, SPInCLK low
(clock polarity = 0)
tw(SPCL)S
0.5tc(SPC)S–0.25tc(ICLK)
Pulse duration, SPInCLK high
(clock polarity = 1)
tw(SPCH)S
0.5tc(SPC)S–0.25tc(ICLK)
Valid time, SPInCLK high after SPInSOMI
data valid (clock polarity = 0)
tv(SOMI-SPCH)S
tv(SOMI-SPCL)S
tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
tv(SPCH-SIMO)S
tv(SPCL-SIMO)S
0.5tc(SPC)S – 6 – tr
Valid time, SPInCLK low after SPInSOMI
data valid (clock polarity = 1)
0.5tc(SPC)S – 6 – tf
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 6 – tr
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 6 – tf
Setup time, SPInSIMO before SPInCLK
high (clock polarity = 0)
6
6
6
6
Setup time, SPInSIMO before SPInCLK
low (clock polarity = 1)
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 0)
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 1)
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
For PS values of 0:
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
Data Valid
7
SPISIMO Data Must
Be Valid
SPInSIMO
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode†‡§ (see Figure 15)
(BAUD + 1)
(BAUD + 1)
IS EVEN OR BAUD = 0
IS ODD AND BAUD ≠ 0
NO.
UNIT
MIN
MAX
MIN
3tc(ICLK)
MAX
224tc(ICLK)
(224 –1) tc(ICLK)
tc(SCC)
2tc(ICLK)
1
2
Cycle time, SCInCLK
ns
ns
Pulse duration,
SCInCLK low
tw(SCCL)
0.5tc(SCC) – tf
0.5tc(SCC) – tr
0.5tc(SCC) + 5 0.5tc(SCC)+0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
0.5tc(SCC) + 5 0.5tc(SCC)–0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
Pulse duration,
SCInCLK high
tw(SCCH)
3
4
5
6
7
ns
ns
ns
ns
ns
Delay time, SCInCLK
high to SCInTX valid
td(SCCH-TXV)
tv(TX)
tsu(RX-SCCL)
tv(SCCL-RX)
10
10
Validtime, SCInTXdata
after SCInCLK low
tc(SCC) – 10
tc(SCC) – 10
tc(ICLK) + tf + 20
- tc(ICLK) + tf + 20
Setup time, SCInRX
before SCInCLK low
t
c(ICLK) + tf + 20
Validtime,SCInRXdata
after SCInCLK low
- tc(ICLK) + tf + 20
† BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
1
3
2
SCICLK
5
4
Data Valid
SCITX
6
7
Data Valid
SCIRX
NOTE A: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode.
Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 15. SCIn Isosynchronous Mode Timing Diagram For Internal Clock
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode†‡ (see Figure 16)
NO.
MIN
MAX
UNIT
Cycle time, SCInCLK§
tc(SCC)
8tc(ICLK)
1
ns
tw(SCCH)
tw(SCCL)
td(SCCH-TXV)
tv(TX)
tsu(RX-SCCL)
tv(SCCL-RX)
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
2tc(ICLK) + 12 + tr
2
3
4
5
6
7
Pulse duration, SCInCLK high
ns
ns
ns
ns
ns
ns
Pulse duration, SCInCLK low
Delay time, SCInCLK high to SCInTX valid
Valid time, SCInTX data after SCInCLK low
Setup time, SCInRX before SCInCLK low
Valid time, SCInRX data after SCInCLK low
2tc(SCC)–10
0
2tc(ICLK) + 10
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
‡ For rise and fall timings, see the switching characteristics for output timings versus load capacitance table.
§ When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
1
2
3
SCICLK
5
4
Data Valid
SCITX
6
7
Data Valid
SCIRX
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one High Resolution Clock Period (HRP). The HRP is defined by the 6-bit High Resolution
Prescale Factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the Low Resolution Clock Period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit Loop-Resolution Prescale Factor
(lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
Note: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
MIN
MAX
15
PARAMETER
TEST CONDITIONS
UNIT
ns
Delay time, transmit shift register to CANSTX pin†
Delay time, CANSRX pin to receive shift register
td(CANSTX)
td(CANSRX)
5
ns
† These values do not include rise/fall times of the output buffer.
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
V
and V
from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
SS
CC
AD
unless otherwise noted.
REFLO
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion code. . . . . . . . . . . . . . . . . . . . . . . .00h to 3FFh [00 for V ≤ADREFLO; 3FF for V ≥ ADREFHI
]
AI
AI
MibADC recommended operating conditions†
MIN
MAX
UNIT
V
ADREFHI
ADREFLO
VAI
VSSAD
VCCAD
A-to-D high -voltage reference source
A-to-D low-voltage reference source
Analog input voltage
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
Analog input clamp current‡
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
IAIC
− 2
2
mA
† For VCCAD and VSSAD recommended operating conditions, see the device recommended operating conditions table.
‡ Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions§¶
MIN
TYP
MAX
500
10
30
1
PARAMETER
DESCRIPTION/CONDITIONS
See Figure 17
UNIT
Ω
Ri
250
Analog input resistance
Conversion
Sampling
pF
Ci
Analog input capacitance
See Figure 17
pF
IAIL
–1
3
Analog input leakage current
See Figure 17
μA
mA
IADREFHI ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
5
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
3.6
CR
V
Difference between the actual step width and the
ideal value after offset correction. (See Figure 18)
EDNL
±2
Differential nonlinearity error
LSB
Maximumdeviationfromthebeststraightlinethrough
the MibADC. MibADC transfer characteristics,
excluding the quantization error after offset
correction.
EINL
±2
±2
Integral nonlinearity error
LSB
LSB
(See Figure 19)
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 20)
ETOT
Total error/Absolute accuracy
§ VCCIO = VCCAD = ADREFHI
¶ 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC) (continued)
External
MibADC
Rs
Ri
Sample Switch
Input Pin
Sample
Capacitor
Parasitic
Capacitance
Rleak
Vsrc
Ci
Figure 17. MibADC Input Equivalent Circuit
Multi-Buffer ADC timing requirements
MIN
0.05
1
NOM
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
μs
td(C)
0.55
Delay time, conversion time
μs
†
1.55
Delay time, total sample/hold and conversion time
μs
td(SHC)
† This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for more detail,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 18 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ... 101
0.... 100
0.... 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0.... 010
Differential Linearity
Error (–1/2 LSB)
0.... 001
0.... 000
1 LSB
2
0
1
3
4
5
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 18. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 19 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Ideal
0 ... 110
0 ... 101
Transition
Actual
Transition
0 ... 100
0 ... 011
At Transition
011/100
(– 1/2 LSB)
0 ... 010
0 ... 001
End-Point Lin. Error
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 19. Integral Nonlinearity (INL) Error
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 20 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
0 ... 011
(–1 1/4 LSB)
0 ... 010
Total Error
At Step
0 ... 001
0 ... 001 (1/2 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 20. Absolute Accuracy (Total) Error
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
0,05 MIN
SQ
0°-7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
RΘJC
51
5
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
List of Figures
TMS470R1VF338x 100-Pin PZ Package (TOP VIEW)
TMS470R1VF348x 100-Pin PZ Package (TOP VIEW)
Functional Block Diagram
Figure 1. Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. JTAG Scan Timing
Figure 9. CMOS-Level Outputs
Figure 10. CMOS-Level Inputs
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 15. SCIn Isosynchronous Mode Timing Diagram For Internal Clock
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 17. MibADC Input Equivalent Circuit
Figure 18. Differential Nonlinearity (DNL)
Figure 19. Integral Nonlinearity (INL) Error
Figure 20. Absolute Accuracy (Total) Error
Mechanical Data
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device Characteristics
Memory Selection Assignment
Peripherals, System Module, and Flash Base Addresses
Interrupt Priority
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERS
REVISION HISTORY
REVISION HISTORY
REV
J
DATE
8/06
NOTES
Updates:
Page 23, operating junction temperature range broken out into A, T, and Q versions
Page 36, timing #5 updated
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without
notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is
current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order
acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
application s using TI components. To minimize the risks associated with customer products and applications, customers should
provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services
are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such
products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under
the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is
an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.
Resale of TI products or services with statements different form or beyond the parameters stated by TI for that product or service
voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business
practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
Data Converters
DSP
Interface
Logic
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
interface.ti.com
logic.ti.com
Audio
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Power Mgmt
Microcontrollers
Low Power Wireless
power.ti.com
microcontroller.ti.com
www..ti.com/lpw
Optical Networking
Security
Telephony
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
Video & Imaging
Imaging Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright ꢀ 2006, Texas Instruments Incorporated
相关型号：
TMS470R1VF338EPZQ
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF338PZ-T
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF338PZA
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF338PZQ
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF346A
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF346APZ-T
IC 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PQFP100, PLASTIC, LQFP-100, MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF346APZA
暂无描述Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF346APZQ
IC 32-BIT, FLASH, 48 MHz, RISC MICROCONTROLLER, PQFP100, PLASTIC, LQFP-100, MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF346BPZA
32-BIT, FLASH, 48MHz, RISC MICROCONTROLLER, PQFP100, PLASTIC, LQFP-100Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF348
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF3482
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS470R1VF3482APZ-T
16/32-BIT RISC FLASH MICROCONTROLLERSWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明