首页 |元器件品牌

TMS55160 [TI]

262144 BY 16-BIT MULTIPORT VIDEO RAMS; 262144 ×16位MULTIPORT视频RAMS
TMS55160
型号： TMS55160
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

262144 BY 16-BIT MULTIPORT VIDEO RAMS
262144 ×16位MULTIPORT视频RAMS
文件： 总67页 (文件大小：1462K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
Organization:  
DRAM: 262144 Words × 16 Bits  
SAM: 256 Words × 16 Bits  
Split-Register-Transfer Function Transfers  
Data from the DRAM to One-Half of the  
Serial Register While the Other Half is  
Outputing Data to the SAM Port  
Single 5.0-V Power Supply (±10%)  
256 Selectable Serial Register Starting  
Points  
Dual-Port Accessibility – Simultaneous and  
Asynchronous Access From the DRAM and  
Serial-Address-Memory (SAM) Ports  
Programmable Split-Register Stop Point  
Write-per-Bit Function for Selective Write to  
Each I/O of the DRAM Port  
Up to 55-MHz Uninterrupted Serial-Data  
Streams  
Byte-Write Function for Selective Write to  
Lower Byte (DQ0–DQ7) or Upper Byte  
(DQ8–DQ15) of the DRAM Port  
3-State Serial Outputs for Easy Multiplexing  
of Video Data Streams  
All Inputs/Outputs and Clocks TTL  
Compatible  
4-Column or 8-Column Block-Write  
Function for Fast Area-Fill Operations  
Compatible With JEDEC Standards  
Enhanced Page Mode for Faster Access  
With Extended-Data-Output (EDO) Option  
for Faster System Cycle Time  
Designed to Work With the Texas  
Instruments (TI ) Graphics Family  
Fabricated Using TI’s Enhanced  
Performance Implanted CMOS (EPIC )  
Process  
CAS-Before-RAS (CBR) and Hidden  
Refresh Functions  
Long Refresh Period – Every 8 ms  
(Maximum)  
Full-Register-Transfer Function Transfers  
Data from the DRAM to the Serial Register  
performance ranges  
ACCESS TIME  
ROW ENABLE  
ACCESS TIME  
SERIAL DATA  
DRAM PAGE  
CYCLE TIME  
DRAM EDO  
CYCLE TIME  
SERIAL  
CYCLE TIME  
OPERATING CURRENT  
SERIAL PORT STANDBY  
t
t
t
t
t
l
RAC  
SCA  
PC  
PC  
SCC  
CC1  
(MAX)  
60 ns  
70 ns  
(MIN)  
15 ns  
20 ns  
(MIN)  
35 ns  
40 ns  
(MIN)  
30 ns  
30 ns  
(MIN)  
18 ns  
22 ns  
(MAX)  
180 mA  
165 mA  
–60 Speed  
–70 Speed  
Table 1. Device Option Table  
DEVICE  
POWER SUPPLY VOLTAGE  
5.0 V ± 0.5 V  
BLOCK-WRITE CAPABILITY  
4-column  
PAGE/EDO OPERATION  
55160  
55161  
55170  
55171  
Page  
EDO  
Page  
EDO  
5.0 V ± 0.5 V  
4-column  
5.0 V ± 0.5 V  
8-column  
5.0 V ± 0.5 V  
8-column  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
DGH PACKAGE  
(TOP VIEW)  
V
1
2
3
4
5
6
7
8
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
SC  
SE  
V
CC  
TRG  
V
SS  
SS  
SQ0  
DQ0  
SQ1  
DQ1  
SQ15  
DQ15  
SQ14  
DQ14  
V
V
CC  
CC  
SQ2  
SQ13  
DQ13  
SQ12  
DQ12  
9
10  
11  
DQ2  
SQ3  
DQ3  
54  
53  
12  
13  
14  
15  
16  
V
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
V
SS  
SS  
SQ4  
DQ4  
SQ5  
SQ11  
DQ11  
SQ10  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
DQ5  
V
DQ10  
V
CC  
CC  
SQ6  
DQ6  
SQ7  
DQ7  
SQ9  
DQ9  
SQ8  
DQ8  
V
V
SS  
SS  
CASL  
DSF  
NC / GND  
CASU  
QSF  
A0  
WE  
RAS  
A8  
A7  
A6  
A1  
29  
30  
31  
32  
A5  
A4  
A2  
A3  
V
V
CC  
SS  
PIN NOMENCLATURE  
A0–A8  
Address Inputs  
RAS  
Row-Address Strobe  
CASL, CASU  
DSF  
Column-Address Strobe, Byte Select  
Special-Function Select  
Output Enable, Transfer Select  
Write Enable, Write Mask Select  
DRAM Data I/O  
TRG  
WE  
DQ0 –DQ15  
SC  
Serial Clock  
SE  
Serial Enable  
SQ0–SQ15  
QSF  
Serial Data Output  
Special-Function Output  
Power Supply  
V
V
CC  
Ground  
SS  
NC/GND  
No Connect/Ground  
(Important: not connected internally to V  
)
SS  
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
description  
The TMS551xx multiport video RAMs (VRAMs) are high-speed dual-ported memory devices. Each consists of  
a dynamic random-access memory (DRAM) organized as 262 144 words of 16 bits each interfaced to a  
serial-data register [serial-access memory (SAM)] organized as 256 words of 16 bits each. These devices  
support three basic types of operation: random access to and from the DRAM, serial access from the serial  
register, and transfer of data from the DRAM to the SAM. Except during transfer operations, these devices can  
be accessed simultaneously and asynchronously from the DRAM and SAM ports.  
The TMS551xx multiport VRAMs provide several functions designed to provide higher system-level bandwidth  
and to simplify design integration on both the DRAM and SAM ports (see Table 2). On the DRAM port, greater  
pixel draw rates areachievedbytheblock-writefunction. TheTMS5516xdevices’4-columnblock-writefunction  
allows 16 bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent  
column-address locations, up to a total of 64 bits of data per CASx cycle time. Similarly, the TMS5517x devices’  
8-column block-write function allows 16 bits of data to be written to any combination of eight adjacent  
column-address locations, up to a total of 128 bits of data per CASx cycle time. Also on the DRAM port, the  
write-per-bit (or write-mask) function allows masking of any combination of the 16 DQs on any write cycle. The  
persistent write-per-bit function uses a mask register that, once loaded, can be used on subsequent write cycles  
without reloading. All TMS551xx devices offer byte control. Byte control can be applied in write cycles, read  
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. The TMS551xx  
devices offer enhanced-page-mode operation that results in faster access time. The TMS551x1 devices also  
offer extended-data-output (EDO) mode. The EDO mode is effective in both the page-mode and the standard  
DRAM cycles.  
The TMS551xx devices offer a split-register-transfer (DRAM to SAM) function. This feature enables real-time  
register load implementation for continuous serial-data streams without critical timing requirements. The serial  
register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half  
can be loaded from the DRAM. For applications not requiring real-time register load (for example, loads done  
during CRT-retrace periods), the full-register-transfer operation is retained to simplify system design.  
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up  
to 55 MHz. A separate output, QSF, is included to indicate which half of the serial register is active. Refreshing  
the SAM is not required because the data register that comprises the SAM is static.  
All inputs, outputs, and clock signals on the TMS551xx devices are compatible with Series 74 TTL. All address  
lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow  
greater system flexibility.  
All TMS551xx employ TI’s state-of-the-art EPIC technology combining very high performance with improved  
reliability.  
All TMS551xx are offered in a 64-pin small-outline gull-wing-leaded package (DGH suffix) for direct surface  
mounting.  
The TMS551xx VRAMs and other TI multiport VRAMs are supported by a broad line of graphics processors  
and control devices from Texas Instruments.  
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column functional block diagram (TMS5516x)  
Input  
DSF  
Buffer  
1 of 4 Sub-Blocks  
(see next page)  
Refresh  
Counter  
Special-  
Function  
Logic  
Input  
Buffer  
Row  
Buffer  
9
1 of 4 Sub-Blocks  
(see next page)  
16  
DQ0–  
DQ15  
A0–A8  
Column  
Buffer  
Output  
Buffer  
1 of 4 Sub-Blocks  
(see next page)  
Serial-  
Address  
Counter  
SC  
Split-  
Register  
Status  
Serial-  
Output  
Buffer  
16  
SQ0–SQ15  
QSF  
SE  
1 of 4 Sub-Blocks  
(see next page)  
SE  
RAS  
CASx  
Timing  
Generator  
TRG  
WE  
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column functional block diagram (TMS5516x) (continued)  
Special-  
Function  
Logic  
DSF  
Input  
Buffer  
Color  
Register  
W/B  
Unlatch  
W/B  
Latch  
DRAM  
Input  
Address  
Mask  
MUX  
Buffer  
DQx  
Write-  
Per-Bit  
Control  
DQx+1  
DQx+2  
DQx+3  
Refresh  
Counter  
DRAM  
Output  
Buffer  
Row  
Buffer  
Column Dec.  
Sense AMP  
RAS  
CASx  
TRG  
WE  
A0–A8  
Timing  
Generator  
512 × 512  
Memory  
Array  
Column  
Buffer  
Row  
Decoder  
Serial-Data  
Register  
Serial-Data  
Pointer  
SQx  
SQx+1  
SQx+2  
SQx+3  
Serial-  
Address  
Counter  
Serial-  
Output  
Buffer  
SC  
Split-  
Register  
Status  
1 of 4 Sub-Blocks  
SE  
QSF  
SE  
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
8-column functional block diagram (TMS5517x)  
Input  
DSF  
Buffer  
Special-  
Function  
Logic  
Refresh  
Counter  
1 of 2 Sub-Blocks  
(see next page)  
Input  
Buffer  
Row  
9
Buffer  
16  
DQ0–  
DQ15  
A0–A8  
Output  
Buffer  
Column  
Buffer  
Serial-  
Address  
Counter  
SC  
Split-  
Register  
Status  
1 of 2 Sub-Blocks  
(see next page)  
16  
SQ0–SQ15  
QSF  
Serial-  
Output  
Buffer  
SE  
SE  
RAS  
CASx  
TRG  
WE  
Timing  
Generator  
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
8-column functional block diagram (TMS5517x) (continued)  
DSF  
Special-  
Function  
Logic  
Input  
Buffer  
Color  
Register  
W/B  
Unlatch  
W/B  
Latch  
Address  
Mask  
MUX  
DRAM  
Input  
Buffer  
Write-  
Per-Bit  
Control  
Refresh  
Counter  
DQx  
DQx + 1  
DQx + 2  
DQx + 3  
DQx + 4  
DQx + 5  
DQx + 6  
DQx + 7  
Row  
Buffer  
DRAM  
Output  
Buffer  
Column DEC  
Sense AMP  
A0–A8  
Column  
Buffer  
512 × 512  
Memory  
Array  
Row  
Decoder  
RAS  
CASx  
TRG  
WE  
Timing  
Generator  
Serial-Data  
Register  
Serial-Data  
Pointer  
Serial-  
Address  
Counter  
SC  
SQx  
SQx + 1  
SQx + 2  
SQx + 3  
SQx + 4  
SQx + 5  
Split-  
Register  
Status  
Serial  
Output  
Buffer  
SQx + 6  
SQx + 7  
QSF  
1 of 2 Sub-Blocks  
SE  
SE  
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
Table 2. Function Table  
CASx  
FALL  
†
RAS FALL  
ADDRESS  
DQ0–DQ15  
MNEMONIC  
CODE  
FUNCTION  
CASL  
CASU  
WE  
‡
§
CASx  
TRG  
WE  
DSF  
DSF  
RAS  
CASx  
RAS  
Reserved (do not use)  
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
—
Stop  
Point  
CBR refresh (no reset) and stop-point set  
X
H
CBRS  
#
||  
CBR refresh (option reset)  
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
X
CBR  
CBR refresh (no reset)  
Full-register transfer  
H
X
CBRN  
Row  
Addr  
Tap  
Point  
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
L
H
L
X
X
L
X
X
X
X
X
RT  
Row  
Addr  
Tap  
Point  
Split-register transfer  
SRT  
RW  
Row  
Addr  
Col  
Addr  
Valid  
Data  
DRAM write (nonmasked)  
H
H
H
H
H
H
H
H
Row  
Addr  
Col  
Addr  
Write  
Mask  
Valid  
Data  
DRAM write (nonpersistent write-per-bit)  
DRAM write (persistent write-per-bit)  
DRAM block write (nonmasked)  
L
L
RWM  
RWM  
BW  
Row  
Addr  
Col  
Addr  
Valid  
Data  
L
L
L
X
X
Row  
Addr  
Block  
Addr  
Col  
Mask  
H
L
L
H
H
H
L
Row  
Addr  
Block  
Addr  
Write  
Mask  
Col  
Mask  
DRAM block write (nonpersistent write-per-bit)  
DRAM block write (persistent write-per-bit)  
L
BWM  
BWM  
LMR  
LCR  
Row  
Addr  
Block  
Addr  
Col  
Mask  
L
L
X
X
X
Refresh  
Addr  
Write  
Mask  
◊
Load write-mask register  
H
H
H
H
X
X
Refresh  
Addr  
Color  
Data  
Load color register  
Legend:  
H
X
=
=
=
Don’t care  
H: Write to address/column enabled  
H: Write to I/O enabled  
Col Mask  
Write Mask  
†
‡
§
#
||  
DQ0–DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later.  
Logic L is selected when either or both CASL and CASU are low.  
The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed.  
CBRS cycle should be performed immediately after the power-up initialization for stop-point mode.  
A0–A3, A8: don’t care; A4–A7 : stop-point code  
CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.  
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.  
For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.  
◊ Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)  
cycle.  
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
Table 3. Pin Description Versus Operational Mode  
PIN  
A0–A8  
RAS  
DRAM  
TRANSFER  
Row address, tap point  
Row-address strobe  
SAM  
Row, column address  
Row-address strobe  
CASL  
CASU  
Column-address strobe, DQ output enable  
Tap-address strobe  
DSF  
Block-write enable  
Split-register-transferenable  
Load-write-mask-register enable  
Load-color-register enable  
CBR (option reset)  
TRG  
WE  
DQ output enable  
Transfer enable  
Write enable, write-per-bit enable  
DRAM data I/O, write mask  
DQx  
SC  
Serial clock  
SQ output enable,  
QSF output enable  
SE  
SQx  
QSF  
Serial-data output  
Serial-register status  
†
V
V
Power supply  
Ground  
CC  
†
SS  
NC/GND  
Make no external connection or tie to system GND  
†
For proper device operation, all V  
CC  
pins must be connected to a 5.0-V supply and all V pins must be tied to ground.  
SS  
pin definitions  
address (A0–A8)  
Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row-address bits are  
set up on pins A0–A8 and latched onto the chip on the falling edge of RAS. Nine column-address bits are set  
up on pins A0–A8 and latched onto the chip on the first falling edge of CASx. All addresses must be stable on  
or before the falling edge of RAS and the first falling edge of CASx.  
In4-columnblock-writeoperations(TMS5516x), column-addressbitsA0–A1areignored. Column-addressbits  
A2–A8 become the block address that selects one of the 128 blocks in the active row. In 8-column block write  
operations (TMS5517x), column-address bits A0–A2 are ignored. Column address bits A3–A8 become the  
block address that selects one of the 64 blocks in the active row.  
In full-register operations, column-address bit A8 selects which half of the active row in the DRAM is transferred  
to the SAM. Column address bits A0–A7 select one of 256 tap points (starting positions) for the serial-data  
output.  
In split-register-transfer operations, column address bit A8 selects the DRAM half row. Column-address bit A7  
is ignored. The internal serial-address counter identifies which half of the SAM is in use. If the high half of the  
SAM is in use, the low half of the SAM is loaded with the low half of the DRAM half row, and vice versa.  
Column-address bits A0–A6 select one of 127 tap points (starting locations) for the serial output. Locations 127  
and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations are  
not valid tap points in split-register-transfer operations.  
row-address strobe (RAS)  
The falling edge of RAS latches the states of the row address, CASL, CASU, DSF, TRG, WE, and the DQs onto  
the chip to initiate DRAM and transfer functions. RAS also functions as a DRAM output enable.  
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
column-address strobe (CASL, CASU)  
The first falling edge of CASx latches the states of the column address and DSF onto the chip to control DRAM  
and transfer functions. CASL and CASU provide byte control in DRAM operations. CASL controls the lower byte  
(DQ0–DQ7), and CASU controls the upper byte (DQ8–DQ15). Byte control can be applied in read cycles, write  
cycles, block-write cycles, load-write-mask-register cycles, and load-color-register cycles. CASx also functions  
as a DRAM output enable.  
special-function select (DSF)  
DSF is latched on the falling edge of RAS and the falling edge of CASx to determine which functions are invoked  
on a particular cycle (see Table 2).  
output enable, transfer select (TRG)  
TRG selects either DRAM or transfer operation as RAS falls. Holding TRG high on the falling edge of RAS  
selects the DRAM operation. Dropping TRG low on the falling edge of RAS selects the transfer operation. TRG  
also functions as DRAM output enable.  
write enable, write-per-bit select (WE)  
WE selects either the write mode or the read mode in a CASx cycle. Dropping WE low selects the write mode.  
Holding WE high selects the read mode. Holding WE low on the falling edge of RAS selects the write-per-bit  
operation.  
DRAM data I/O, write mask, column mask (DQ0–DQ15)  
DQ0–DQ15 function as the DRAM input/output port in DRAM operations. In normal DRAM write cycles, all  
16 bits of write data are latched on either the falling edge of WE or the first falling edge of CASx, whichever  
occurs later. Similarly, the DQs are latched as write mask in load-mask-register cycles, as color data in  
load-color-register cycles, and as column mask in block-write cycles. In non-persistent write-per-bit cycles, the  
DQs are latched as the write mask on the falling edge of RAS.  
Data out is in the same polarity as data in. The 3-state output buffer provides direct TTL compatibility (no pullup  
resistorrequired)withafan-outofoneSeries74TTLload. Theoutputsareinthehigh-impedance(floating)state  
until RAS, CASx, and TRG have all been brought low in read cycles. For the TMS551x0 devices, the outputs  
remain valid until CASx is brought high, TRG is brought high, or WE is brought low. For the TMS551x1 devices,  
the outputs remain valid until both RAS and CASx are brought high, TRG is brought high, or WE is brought low.  
serial clock (SC)  
The rising edge of SC increments the internal serial-address counter and accesses serial data at the next SAM  
location.  
serial enable (SE)  
SE functions as the output enable for SQ0–SQ15 and QSF. SE low enables the serial-data output. SE high  
disables the serial-data output. Holding SE high does not disable the serial clock SC. The rising edge of SC  
automatically increments the internal serial-address counter regardless of the state of SE.  
serial data outputs (SQ0–SQ15)  
SQ0–SQ15 function as the SAM output port. The 3-state output buffer provides direct TTL compatibility (no  
pullup resistors) with a fan-out of one Series 74 TTL load. Serial data is accessed from the SAM on the rising  
edge of SC. SE low enables the outputs. The outputs are in the high-impedance (floating) state when disabled.  
special-function output (QSF)  
QSF is an output pin that indicates which half of the SAM is being accessed. QSF is low when the internal  
serial-address counter points to the lower (least significant) 128 bits of the SAM. QSF is high when the internal  
serial-address counter points to the higher (most significant) 128 bits of SAM. QSF is in the high-impedance  
state when SE is high.  
10  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
functional operation description  
random-access operation  
Table 4. DRAM Function Table  
CASx  
FALL  
†
RAS FALL  
ADDRESS  
DQ0–DQ15  
MNEMONIC  
CODE  
FUNCTION  
CASL  
CASU  
WE  
‡
§
CASx  
TRG  
WE  
DSF  
DSF  
RAS  
CASx  
RAS  
Reserved (do not use)  
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
—
Stop  
Point  
CBR refresh (no reset) and stop-point set  
X
H
CBRS  
#
||  
CBR refresh (option reset)  
L
L
X
X
H
H
L
X
X
X
X
X
X
X
X
X
CBR  
CBR refresh (no reset)  
H
X
CBRN  
Row  
Addr  
Col  
Addr  
Valid  
Data  
DRAM write (nonmasked)  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
L
L
X
RW  
RWM  
RWM  
BW  
Row  
Addr  
Col  
Addr  
Write  
Mask  
Valid  
Data  
DRAM write (nonpersistent write-per-bit)  
DRAM write (persistent write-per-bit)  
DRAM block write (nonmasked)  
Row  
Addr  
Col  
Addr  
Valid  
Data  
L
L
X
X
Row  
Addr  
Block  
Addr  
Col  
Mask  
H
L
H
H
H
L
Row  
Addr  
Block  
Addr  
Write  
Mask  
Col  
Mask  
DRAM block write (nonpersistent write-per-bit)  
DRAM block write (persistent write-per-bit)  
BWM  
BWM  
LMR  
LCR  
Row  
Addr  
Block  
Addr  
Col  
Mask  
L
X
X
X
Refresh  
Addr  
Write  
Mask  
◊
Load write-mask register  
H
H
X
X
Refresh  
Addr  
Color  
Data  
Load color register  
Legend:  
H
X
=
=
=
Don’t care  
H: Write to address/column enabled  
H: Write to I/O enabled  
Col Mask  
Write Mask  
†
‡
§
#
||  
DQ0–DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later.  
Logic L is selected when either or both CASL and CASU are low.  
The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed.  
CBRS cycle should be performed immediately after the power-up initialization for stop-point mode.  
A0–A3, A8: don’t care; A4–A7 : stop-point code  
CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.  
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.  
For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.  
◊ Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)  
cycle.  
11  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
refresh  
CAS-before-RAS (CBR) refresh  
CBR refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS. The external  
row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles  
are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode.  
The CBRN (no reset) and CBRS (no reset and stop point set) refreshes do not end the persistent write-per-bit  
mode or the stop-point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively  
as long as the entire refresh is completed within the required time period, t  
the high-impedance state during the CBR type refresh cycles regardless of the state of TRG.  
. The output buffers remain in  
rf(MA)  
hidden refresh  
A hidden refresh is accomplished by holding either or both CASL and CASU low in the DRAM read cycle and  
cycling RAS. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the  
CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.  
RAS-only refresh  
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the  
output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be  
supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row  
to be refreshed.  
enhanced page mode (TMS551x0)  
Enhanced page mode allows faster memory access by keeping the same row address while selecting random  
column addresses. The maximum RAS low time and minimum CASx page cycle time are used to determine  
the number of columns that can be accessed.  
Unlike conventional page mode, the enhanced page mode allows the TMS551x0 to operate at a higher data  
bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx goes low. A  
valid column address can be presented immediately after the row-address hold time has been satisfied, usually  
well in advance of the falling edge of CASx. In this case, data is obtained after t  
max (access time from CASx  
a(C)  
low) if t  
max (access time from column address) has been satisfied.  
a(CA)  
extended data output (TMS551x1)  
The TMS551x1 features extended data output during DRAM accesses. While RAS and TRG are low, theDRAM  
output remains valid even when CASx returns high. The output remains valid until WE is low, TRG is high, or  
both CASx and RAS are high (see Figure 1, Figure 2, and Figure 3). The extended data-output mode functions  
in all read cycles including DRAM read, page-mode read, and read-modify-write cycles.  
RAS  
CASx  
†
t
dis(RH)  
Valid Output  
DQ0 –DQ15  
TRG  
†
See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 1. DRAM Read Cycle With RAS-Controlled Output (TMS551x1)  
12  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
extended data output (TMS551x1) (continued)  
RAS  
CASx  
DQ0 –DQ15  
TRG  
†
dis(CH)  
t
Valid Output  
†
See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 2. DRAM Read Cycle With CAS-Controlled Output (TMS551x1)  
RAS  
CASx  
Row  
Column  
Column  
A0–A8  
†
t
t
t
t
a(CP)  
†
†
t
a(C)  
†
a(C)  
†
a(CA)  
t
a(CA)  
‡
†
t
h(CLQ)  
dis(RH)  
Valid Output  
Valid Output  
DQ0–DQ15  
†
t
dis(G)  
TRG  
†
‡
See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.  
See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 3. DRAM Page-Read Cycle With Extended Data Output (TMS551x1)  
13  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
byte operation  
Byte operation can be applied in DRAM read cycles, write cycles, block-write cycles, load-write-mask-register  
cyclesand load-color-register cycles. In byte operation, the column address (A0–A8) is latched at the first falling  
edge of CASx. In read cycles, CASL enables the lower byte (DQ0–DQ7) and CASU enables the upper byte  
(DQ8–DQ15) (see Figure 4).  
RAS  
CASL  
†
CASU  
t
su(CA)  
†
t
h(CLCA)  
A0–A8  
Row  
Column  
‡
t
a(C)  
DQ0–DQ7  
Lower Byte Output  
‡
t
a(C)  
Upper Byte  
Output  
DQ8–DQ15  
‡
t
a(G)  
TRG  
†
‡
See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.  
See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 4. Example of a Byte-Read Cycle  
14  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
byte operation (continued)  
In byte-write operation, CASL enables data to be written to the lower byte (DQ0–DQ7) and CASU enables data  
to be written to the upper byte (DQ8–DQ15). In an early-write cycle, WE is brought low prior to both CASx  
signals. Data setup and hold times for DQ0 –DQ15 are referenced to the first falling edge of CASx  
(see Figure 5).  
RAS  
WE  
CASL  
†
t
su(CA)  
CASU  
†
t
h(CLCA)  
Row  
Column  
A0–A8  
†
t
su(DCL)  
†
t
h(CLD)  
Valid Input  
DQ0–DQ15  
†
See “switching characteristics over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 5. Example of an Early-Write Cycle  
15  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
byte operation (continued)  
For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data  
is strobed in with data setup and hold times for DQ0 –DQ15 referenced to WE (see Figure 6).  
RAS  
CASL  
CASU  
WE  
†
t
su(DWL)  
†
t
h(WLD)  
DQ0–DQ15  
Valid Input  
†
See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 6. Example of a Late-Write Cycle  
16  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
write-per-bit  
The write-per-bit function allows the masking of any combination of the 16 DQs on any write cycle. The  
write-per-bit operation is invoked when WE is held low on the falling edge of RAS. If WE is held high on the falling  
edge of RAS, the write operation is performed without any masking. There are two write-per-bit modes: the  
nonpersistent write-per-bit and the persistent write-per-bit.  
nonpersistent write-per-bit  
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit  
mask) is input to the device through the DQ pins and latched on the falling edge of RAS. The write-per-bit mask  
selects which of the 16 DQs are to be written and which are not. After RAS has latched the on-chip write-per-bit  
mask, input data is driven onto the DQ pins and is latched on either the falling edge of WE or the first falling edge  
of CASx, whichever occurs later. CASL enables the lower byte (DQ0–DQ7) to be written through the mask and  
CASU enables the upper byte (DQ8–DQ15) to be written through the mask. If a write-mask-low (write  
mask = 0) is strobed into a particular DQ pin on the falling edge of RAS, data is not written to that DQ. If a  
write-mask-high (write mask = 1) is strobed into a particular DQ pin on the falling edge of RAS, data is written  
to that DQ (see Figure 7).  
RAS  
CASL  
CASU  
WE  
†
t
su(DQR)  
†
t
h(WLD)  
†
t
h(RDQ)  
†
t
su(DWL)  
DQ0–DQ15  
Write Mask  
Valid Input  
†
See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 7. Example of a Nonpersistent Write-Per-Bit (Late-Write) Operation  
17  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
persistent write-per-bit  
The persistent write-per-bit mode is initiated only by performing a load-write-mask-register (LMR) cycle first.  
In the persistent write-per-bit mode, the write-per-bit mask is not overwritten but remains valid over an arbitrary  
number of write cycles until another LMR cycle is performed or until power is removed.  
The LMR cycle is performed using DRAM write-cycle timing except DSF is held high on the falling edge of RAS  
and held low on the first falling edge of CASx. A binary code is input to the write-mask register through the  
random I/O pins and latched on either the first falling edge of CASx or the falling edge of WE, whichever occurs  
later. Byte-writecontrolcanbeappliedtothewritemaskduringtheLMRcycle. Thepersistentwrite-per-bitmode  
can then be used in exactly the same way as the nonpersistent write-per-bit mode except that the input data  
on the falling edge of RAS is ignored. When the device is set to the persistent write-per-bit mode, it remains in  
this mode and is reset only by a CBR refresh with option reset cycle (see Figure 8).  
Load Write-Mask Register  
Persistent Write-Per-Bit  
CBR Refresh (option reset)  
RAS  
CASx  
A0–A8  
Refresh  
Address  
Row  
Column  
DSF  
WE  
DQ0–  
DQ15  
Write-Mask  
Data  
Valid  
Input  
Mask Data  
=
=
1: Write to DQ enabled  
0: Write to DQ disabled  
Figure 8. Example of a Persistent Write-Per-Bit Operation  
18  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column block write (TMS5516x)  
The 4-column block-write function allows up to 64 bits of data to be written simultaneously to one row of the  
memory array. This function is implemented as 4 columns × 4 DQs and repeated in four quadrants. In this  
manner, each of the four one-megabit quadrants can have up to four consecutive columns written at a time with  
up to four DQs per column (see Figure 9).  
DQ15  
DQ14  
4th Quadrant  
DQ13  
DQ12  
DQ11  
DQ10  
3rd Quadrant  
DQ9  
DQ8  
One Row of 0–511  
DQ7  
DQ6  
2nd Quadrant  
DQ5  
DQ4  
DQ3  
DQ2  
1st Quadrant  
DQ1  
DQ0  
Four Consecutive Columns of 0–511  
Figure 9. 4-Column Block-Write Operation  
Eachone-megabit quadrant has a 4-bit column mask to mask off any or all of the four columns from being written  
with data. Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write  
operation to provide write-masking options. Write data (color data) is provided by four bits from the on-chip color  
register. Bits 0 –3 from the 16-bit write-mask register, bits 0 –3 from the 16-bit column-mask register, and  
bits 0 –3 from the 16-bit color-data register configure the block write for the first quadrant, while bits 4 –7, 8 –11,  
and 12 –15 of the corresponding registers control the other quadrants in a similar fashion (see Figure 10).  
19  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column block write (continued)  
DQ15  
DQ14  
DQ13  
DQ12  
DQ11  
DQ10  
12  
13  
14  
15  
DQ9  
DQ8  
One Row of 0–511  
DQ7  
DQ6  
DQ5  
8
9
10  
11  
DQ4  
DQ3  
DQ2  
4
5
6
7
DQ1  
DQ0  
0
1
2
3
3
7
11  
15  
2
6
10  
14  
1
5
9
13  
0
4
8
12  
0
1
2
3
4
5
6
7
8
9
10 11  
12 13 14 15  
Color Register  
Figure 10. 4-Column Block Write With Masks  
20  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column block write (continued)  
Every four adjacent columns makes a block, which results in 128 blocks along one row. Block 0 comprises  
columns 0 –3, block 1 comprises columns 4 –7, block 2 comprises columns 8 –11, etc., as shown in Figure 11.  
Block 0  
Block 1 . . . . . . . . . . . . . . . . . . . . . . Block 127  
One Row of 0–511  
0
1
2
3
4
5
6
7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 511  
Columns  
Figure 11. 4-Column-Block Column-Organization  
During 4-column block-write cycles, only the seven most significant column addresses (A2 –A8) are latched on  
the falling edge of CASx to decode one of the 128 blocks. Address bits A0 –A1 are ignored. All one-megabit  
quadrants have the same block selected.  
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the falling  
edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper  
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on  
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data  
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section  
for details on the use of the write-mask capability, allowing additional performance options.  
Example of block write:  
block-write column address = 110000000 (A0 –A8 from left to right)  
bit 0  
bit 15  
0111  
1011  
1010  
color-data register = 1011  
write-mask register = 1110  
column-mask register = 1111  
1011  
1111  
0000  
1100  
1111  
0111  
1st  
2nd  
3rd  
4th  
Quad  
Quad  
Quad  
Quad  
Column-address bits A0 and A1 are ignored. Block 0 (columns 0 –3) is selected for all one-megabit quadrants.  
The first quadrant has DQ0 –DQ2 written with bits 0 –2 from the color-data register to all four columns of  
block 0. DQ3 is not written and retains its previous data due to the write-mask bit 3 being a 0.  
The second quadrant (DQ4–DQ7) has all four columns masked off due to the column-mask bits 4 –7 being 0,  
so that no data is written.  
The third quadrant (DQ8–DQ11) has its four DQs written with bits 8 –11 from the color-data register to columns  
1–3 of its block 0. Column 0 is not written and retains its previous data on all four DQs due to the  
column-mask bit 8 being 0.  
The fourth quadrant (DQ12–DQ15) has DQ12, DQ14, and DQ15 written with bits 12, 14, and 15 from the  
color-data register to column 0 and column 2 of its block 0. DQ13 retains its previous data on all columns due  
to the write mask. Columns 1 and 3 retain their previous data on all DQs due to the column mask. If the previous  
data for the quadrant was all 0s, the fourth quadrant would contain the data pattern shown in Figure 12 after  
the 4-column block-write operation shown in the example.  
21  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
4-column block write (continued)  
DQ15  
1
1
0
0
1
0
DQ14  
1
0
0
0
4th Quadrant  
DQ13  
0
0
0
0
DQ12  
0
0
Columns  
0
1
2
3
Figure 12. Example of Fourth Quadrant After 4-Column Block-Write Operation  
22  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
8-column block write (TMS5517x)  
The 8-column block-write function allows up to 128 bits of data to be written simultaneously to one row of the  
memory array. This function is implemented as 8 columns × 8 DQs and repeated in two bytes. In this manner,  
each of the two bytes can have up to eight consecutive columns written at a time with up to eight DQs per column  
(see Figure 13).  
DQ15  
DQ14  
DQ13  
DQ12  
Upper Byte  
DQ11  
DQ10  
DQ9  
DQ8  
One Row of 0–511  
DQ7  
DQ6  
DQ5  
DQ4  
Lower Byte  
DQ3  
DQ2  
DQ1  
DQ0  
Eight Consecutive Columns of 0–511  
Figure 13. 8-Column Block-Write Operation  
Each byte has an 8-bit column mask to mask off any or all of the eight columns from being written with data.  
Nonpersistent write-per-bit or persistent write-per-bit functions can be applied to the block-write operation to  
provide write-masking options. Write data (color data) is provided by eight bits from the on-chip color register.  
Bits 0 –7 from the 16-bit write-mask register, bits 0 –7 from the 16-bit column-mask register, and bits 0 –7 from  
the 16-bit color-data register configure the block write for the lower byte, while bits 8–15 control the upper byte  
in a similar fashion (see Figure 14).  
23  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
8-column block write (TMS5517x) (continued)  
Lower Byte  
Upper Byte  
DQ0  
DQ1  
DQ2  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
One Row of 0–511  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Color Register  
Figure 14. 8-Column Block Write With Masks  
Every eight adjacent columns makes a block resulting in 64 blocks along one row. Block 0 comprises  
columns 0 –7, block 1 comprises columns 8 –15, block 2 comprises columns 16 –23, etc., as shown in  
Figure 15.  
Block 0  
Block 63  
One Row of 0–511  
0
1
2
3
4
5
6
7 . . . . . . . . . . . . . 504 505 506 507 508 509 510 511  
Columns  
Figure 15. 8-Column-Block Column-Organization  
During 8-column block-write cycles, only the six most significant column addresses (A3 –A8) are latched on the  
fallingedgeofCASxtodecodeoneofthe64blocks. AddressbitsA0 –A2areignored. Bothbyteshavethesame  
block selected.  
24  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
8-column block write (continued)  
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first  
fallingedgeofCASx. AsinaDRAMwriteoperation, CASLandCASUenablethecorrespondinglowerandupper  
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on  
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data  
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section  
for details on use of the write-mask capability allowing additional performance options.  
Example of block write:  
block-write column address  
=
110000000 (A0 –A8 from left to right)  
bit 0  
bit 15  
11000111  
11111011  
01111010  
color-data register = 10111011  
write-mask register = 11101111  
column-mask register = 11110000  
Lower  
Byte  
Upper  
Byte  
Column-address bits A0–A2 are ignored. Block 0 (columns 0 –7) is selected for both bytes. The lower byte has  
DQ0 –DQ2 and DQ4–DQ7 written with bits 0 –2 and 4–7 from the color-data register to columns 0–3.  
Columns 4 –7 are not written and retain their previous data due to the column-mask bits 4–7 being 0. DQ3 is  
not written and retains its previous data due to the write-mask bit 3 being 0.  
The upper byte has DQ8–DQ12 and DQ14–DQ15 written with bits 8 –12 and 14–15 from the color-data  
register to columns 1–4 and 6. Columns 0, 5, and 7 are not written and retain their previous data due to the  
column-mask bits 8, 13, and 15 being 0. DQ13 is not written and retains its previous data due to the  
write-mask-register bit 13 being 0. If the previous data was all 0s, the upper byte would contain the data pattern  
in Figure 16 after the 8-column block-write operation shown in the example.  
0 1 1 1 1 0 1 0  
DQ15  
0 1 1 1 1 0 1 0  
DQ14  
0 0 0 0 0 0 0 0  
DQ13  
0 0 0 0 0 0 0 0  
DQ12  
0 0 0 0 0 0 0 0  
Upper Byte  
DQ11  
0 0 0 0 0 0 0 0  
DQ10  
0 1 1 1 1 0 1 0  
DQ9  
0 1 1 1 1 0 1 0  
DQ8  
Columns 0 1 2 3 4 5 6 7  
Figure 16. Example of Upper Byte After 8-Column Block-Write Operation  
25  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
load color register  
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high  
on the falling edges of RAS and on the first falling edge of CASx. The color register is loaded from pins  
DQ0 –DQ15, which are latched on either the falling edge of WE or the first falling edge of CASx, whichever  
occurs later. If only one CASx is low, only the corresponding byte of the color register is loaded. When the color  
register is loaded, it retains data until power is lost or until another load-color-register cycle is performed (see  
Figure 17 and Figure 18).  
Load-Color-Register Cycle  
Block-Write Cycle  
(no write mask)  
Block-Write Cycle  
(nonpersistent write-per-bit)  
RAS  
CASx  
A0–A8  
WE  
1
2
3
2
3
TRG  
DSF  
DQ0–DQ15  
4
6
5
6
Legend:  
1. Refresh address: A0–A8 are latched on the falling edge of RAS.  
2. Row address: A0–A8 are latched on the falling edge of RAS.  
3. Block address A2–A8 (TMS5516x) or A3–A8 (TMS5517x) are latched on the first falling edge of CASx.  
4. Color data: DQ0–DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.  
5. Write-mask data: DQ0–DQ15 are latched on the falling edge RAS.  
6. Column-mask data: DQ0–DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.  
= don’t care  
Figure 17. Example of Block Writes  
26  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
load color register (continued)  
Load-Mask-Register Cycle  
Load-Color-Register Cycle  
Persistent Write-Per-Bit  
Block-Write Cycle  
RAS  
CASx  
A0–A8  
WE  
1
1
2
3
TRG  
DSF  
DQ0–DQ15  
5
4
6
Legend:  
1. Refresh address: A0–A8 are latched on the falling edge of RAS.  
2. Row address: A0–A8 are latched on the falling edge of RAS.  
3. Block address A2–A8 (TMS5516x) or A3–A8 (TMS5517x) are latched on the first falling edge of CASx.  
4. Color data: DQ0–DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.  
5. Write-mask data: DQ0–DQ15 are latched on the falling edge RAS.  
6. Column-mask data: DQ0–DQ15 are latched on the falling edge WE or on the first falling edge of CASx, whichever occurs first.  
= don’t care  
Figure 18. Example of a Persistent Block Write  
DRAM-to-SAM transfer operation  
During the DRAM-to-SAM transfer operation, one-half of a row (256 columns) in the DRAM array is selected  
to be transferred to the 256-bit serial-data register. The transfer operation is invoked by bringing TRG low and  
holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,  
determines whether the full-register-transfer operation or the split-register-transfer operation is performed.  
Table 5. SAM Function Table  
CASx  
FALL  
RAS FALL  
ADDRESS  
DQ0 –DQ15  
MNEMONIC  
CODE  
FUNCTION  
CASx  
WE  
†
CASx  
TRG  
WE  
DSF  
L
DSF  
RAS  
CASx  
RAS  
Row  
Addr  
Tap  
Point  
Full-register-transfer read  
Split-register-transfer read  
H
H
L
L
H
H
X
X
X
X
X
RT  
Row  
Addr  
Tap  
Point  
H
X
SRT  
†
Logic L is selected when either or both CASL and CASU are low.  
don’t care  
X
=
27  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
full-register-transfer read  
A full-register-transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is  
brought low and latched at the falling edge of RAS. Nine row-address bits (A0 –A8) are also latched at the falling  
edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0 –A8)  
are latched at the first falling edge of CASx, where address bit A8 selects which half of the row is transferred.  
Address bits A0 –A7 select one of the SAM’s 256 available tap points from which the serial data is read out (see  
Figure 19).  
A8 = 0  
A8 = 1  
0
255 256  
511  
512 × 512  
Memory Array  
256-Bit  
Data Register  
0
255  
Figure 19. Full-Register-Transfer Read  
A full-register transfer can be performed in three ways: early load, real-time load (or midline load), or late load.  
Each of these offers the flexibility of controlling the TRG trailing edge in the full-register-transfer cycle  
(see Figure 20).  
Early Load  
Real-Time Load  
Late Load  
RAS  
CASx  
A0–A8  
Row  
Tap  
Point  
Row  
Tap  
Point  
Row  
Tap  
Point  
TRG  
WE  
SC  
Old  
Data  
Tap  
Bit  
Old  
Data  
Old  
Data  
Tap  
Bit  
Old  
Data  
Old  
Data  
Tap  
Bit  
Figure 20. Example of Full-Register-Transfer Read Operations  
28  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
split-register-transfer read  
In split-register-transfer operations, the serial-data register is split into halves (see Figure 21). The low half  
contains bits 0 –127, and the high half contains bits 128 – 255. While one half is being read out of the SAM port,  
the other half can be loaded from the memory array.  
A8 = 0  
A8 = 1  
0
255 256  
511  
512 × 512  
Memory Array  
256-Bit  
Data Register  
0
255  
Figure 21. Split-Register-Transfer Read  
To invoke a split-register-transfer cycle, DSF is brought high, TRG is brought low, and both are latched at the  
falling edge of RAS (see Figure 22). Nine row-address bits (A0 –A8) are also latched at the falling edge of RAS  
to select one of the 512 rows available for the transfer. Eight of the nine column-address bits (A0 –A6 and A8)  
are latched at the first falling edge of CASx. Column-address bit A8 selects which half of the row is to be  
transferred. Column-address bit A7 is ignored, and the split-register transfer is internally controlled to select the  
inactive half. Column-address bits A0–A6 select one of 127 tap points in the specified half of SAM. Locations  
127 and 255 are not valid tap points in split-register-transfer operations. In stop-point mode, stop-point locations  
are not valid tap points in split-register-transfer operations.  
Full XFER  
Split XFER  
A8 = 1  
Split XFER  
A8 = 1  
Split XFER  
RAS  
A8 = 0  
A8 = 0  
†
†
†
0
511  
0
A7 = 0 511  
0
A7 = 1 511  
0
A7 = 0  
A
511  
A
B
A
B
C
A
B
C
D
B
C
D
D
E
DRAM  
SAM  
0
255  
0
255  
B
0
255  
0
255  
A
B
C
C
D
E
SQ  
A7 shown is internally controlled.  
SQ  
SQ  
SQ  
†
Figure 22. Example of a Split-Register-Transfer Read Operation  
A full-register transfer must precede the first split-register transfer to ensure proper operation. After the  
full-register transfer cycle, the first split-register transfer can follow immediately without any minimum SC clock  
requirement.  
29  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
split-register-transfer read (continued)  
QSF indicates which half of the register is being accessed during serial-access operation. When QSF is low,  
the serial-address pointer is accessing the lower (least significant) 128 bits of SAM. When QSF is high, the  
pointer is accessing the higher (most significant) 128 bits of SAM. QSF changes state upon completing a  
full-register-transfer read cycle. The tap point loaded during the current transfer cycle determines the state of  
QSF. QSF also changes state when a boundary between two register halves is reached.  
Full-Register-Transfer Read  
With Tap Point N  
Split-Register-  
Transfer Read  
RAS  
CASx  
TRG  
DSF  
SC  
Tap  
Point N  
t
d(CLQSF)  
t
d(GHQSF)  
QSF  
NOTE A: See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 23. Example of a Split-Register-Transfer Read After a Full-Register-Transfer Read  
Split-Register-  
Transfer Read  
With Tap Point N  
Split-Register-  
Transfer Read  
RAS  
CASx  
TRG  
DSF  
t
d(MSRL)  
t
d(RHMS)  
SC  
127  
Tap  
or 255  
Point N  
t
d(SCQSF)  
QSF  
NOTE A: See “timing requirements over recommended ranges of supply voltage and operating free-air temperature” table.  
Figure 24. Example of Successive Split-Register-Transfer Read Operations  
30  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
serial-read operation  
The serial-read operation can be performed through the SAM port simultaneously and asynchronously with  
DRAM operations except during transfer operations. Serial data is accessed from the SAM at the rising edge  
of serial clock SC. SE low enables the outputs. SE high disables the outputs. Holding SE high does not disable  
SC. The rising edge of SC automatically increments the internal serial-address counter regardless of the state  
of SE. In full-register-transfer operations, the counter proceeds sequentially to the most significant bit (bit 255),  
and then wraps around to the least significant bit (bit 0), as shown in Figure 25.  
0
1
2
Tap  
254  
255  
Figure 25. Serial-Pointer Direction for Serial Read  
In split-register-transfer operations, serial data can be read out from the active half of SAM by clocking SC  
starting at the tap point loaded by the preceding split-register-transfer cycle. The serial pointer then proceeds  
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register-transfer read to  
the inactive half during this period, the serial pointer points next to the tap point location loaded by that  
split-register-transfer (see Figure 26).  
0
Tap  
126  
127  
128  
Tap  
254  
255  
Figure 26. Serial Pointer for Split-Register Read – Case I  
If there is no split-register transfer to the inactive half during this period, the serial pointer points to the next bit,  
bit 128 or bit 0, respectively (see Figure 27).  
0
Tap  
126  
127  
128  
Tap  
254  
255  
Figure 27. Serial Pointer for Split-Register Read – Case II  
split-register programmable stop point  
The TMS551xx offers programmable stop-point mode for split-register-transfer read operation. This mode can  
be used to improve 2-D drawing performance in a nonscanline data format.  
In split-register-transfer read operations, the stop point is defined as a register location at which the serial output  
stops coming from one half of the SAM and switches to the opposite half of the SAM. While in stop-point mode,  
the SAM is divided into partitions whose length is programmed on row addresses A4–A7 in a CBR set (CBRS)  
cycle. The last serial-address location of each partition is the stop point (see Figure 28).  
127  
128  
255  
0
Partition  
Length  
Stop  
Points  
Figure 28. Example of SAM With Partitions  
31  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
split-register programmable stop point (continued)  
Stop-point mode is not active until the CBRS cycle is initiated. The CBRS operation is performed by holding  
CASxlow, WElow, andDSFhighonthefallingedgeofRAS. ThefallingedgeofRASalsolatchesrowaddresses  
A4–A7, which are used to define the SAM’s partition length. The other row-address inputs are don’t cares.  
Stop-point mode should be initiated immediately after the power-up initialization (see Table 6).  
Table 6. Programming Code for Stop-Point Mode  
MAXIMUM  
PARTITION  
LENGTH  
ADDRESS AT RAS IN CBRS CYCLE  
NUMBER OF  
PARTITIONS  
STOP-POINT LOCATIONS  
A8  
A7  
A6  
A5  
A4  
A0–A3  
15, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175,  
191, 207, 223, 239, 255  
16  
X
L
L
L
L
X
16  
32  
64  
X
X
L
L
L
L
L
H
H
X
X
8
4
31, 63, 95, 127, 159, 191, 223, 255  
63, 127, 191, 255  
H
128  
(default)  
X
L
H
H
H
X
2
127, 255  
In stop-point mode, the tap point loaded during the split-register-transfer read cycle determines in which SAM  
partition the serial output begins and at which stop point the serial output stops coming from one half of SAM  
and switches to the opposite half of SAM (see Figure 29).  
Full  
Split  
Split  
Split  
RAS  
SC  
Read XFER  
Read XFER  
Read XFER  
Read XFER  
Tap = H1  
Tap = L1  
Tap = H2  
Tap = L2  
H1  
191 L1  
63 H2  
255 L2  
SAM Low Half  
63  
SAM High Half  
191  
0
L1  
L2  
127  
128  
H1  
H2  
255  
Figure 29. Example of Split-Register Operation With Programmable Stop Points  
32  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
256-/512-bit compatibility of split-register programmable stop point  
The stop-point mode is designed to be compatible with both 256-bit SAM and 512-bit SAM devices. After the  
CBRS cycle is initiated, the stop-point mode becomes active. In the stop-point mode, and only in the stop-point  
mode, the column-address bits AY7 and AY8 are swapped internally to assure compatibility (see Figure 29).  
This address-bit swap applies to the column address, and it is effective for all DRAM and transfer cycles. For  
example, during the split-register-transfer cycle with stop point, column-address bit AY8 is a don’t care and AY7  
decodes the DRAM row half for the split-register-transfer. During stop-point mode, a CBR (option reset) cycle  
is not recommended because this ends the stop-point mode and restores address bits AY7 and AY8 to their  
normal functions. Consistent use of CBR cycles ensures that the TMS551xx remains in nomal mode.  
NON STOP-POINT MODE  
AY8 = 0 AY8 = 1  
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1  
STOP-POINT MODE  
AY8 = 0  
AY8 = 1  
AY7 = 0 AY7 = 1 AY7 = 0 AY7 = 1  
512 × 512  
Memory Array  
512 × 512  
Memory Array  
256-Bit  
Data Register  
256-Bit  
Data Register  
0
255  
0
255  
Figure 30. DRAM-to-SAM Mapping, Nonstop-Point Versus Stop Point  
IMPORTANT: For proper device operation, a stop-point-mode (CBRS) cycle should be initiated immediately  
after the power-up initialization cycles are performed.  
power up  
To achieve proper device operation, an initial pause of 200 µs is required after power up followed by a minimum  
of eight RAS cycles or eight CBR cycles to initialize the DRAM port. A full-register-transfer read cycle and two  
SC cycles are required to initialize the SAM port.  
After initialization, the internal state of the TMS551xx is as follows:  
STATE AFTER INITIALIZATION  
QSF  
Defined by the transfer cycle during initialization  
Write mode  
Nonpersistent mode  
Write-mask register  
Color register  
Serial-register tap point  
SAM port  
Undefined  
Undefined  
Defined by the transfer cycle during initialization  
Output mode  
33  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
TMS551xx  
Supply voltage range, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V  
CC  
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1 V to 7 V  
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W  
Operating free-air temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C  
stg  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values are with respect to V  
.
SS  
recommended operating conditions  
TMS551xx  
UNIT  
MIN NOM  
MAX  
V
V
V
V
Supply voltage  
4.5  
5.0  
0
5.5  
V
V
CC  
SS  
IH  
Supply voltage  
High-level input voltage  
Low-level input voltage (see Note 2)  
Operating free-air temperature  
2.4  
–1.0  
0
6.5  
0.8  
70  
V
V
IL  
T
A
°C  
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.  
34  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
electrical characteristics over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
’551xx-60  
’551xx-70  
SAM  
PORT  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
†
MIN  
MAX  
MIN  
MAX  
V
V
High-level output voltage  
Low-level output voltage  
I
I
= –1 mA  
2.4  
2.4  
V
V
OH  
OH  
= 2 mA  
= 5.5 V,  
0.4  
0.4  
OL  
OL  
V
CC  
V = 0 V to 5.8 V,  
I
I
Input current (leakage)  
±10  
±10  
µA  
I
All other pins at 0 V to V  
CC  
V
V
= 5.5 V,  
CC  
= 0 V to V , See Note 3  
I
O
Output current (leakage)  
±10  
±10  
µA  
O
CC  
‡
‡
I
I
I
I
I
I
Operating current  
Operating current  
Standby current  
See Note 4  
= MIN  
Standby  
Active  
180  
225  
5
165  
205  
5
mA  
mA  
mA  
mA  
mA  
mA  
CC1  
t
CC1A  
CC2  
c(SC)  
All clocks = V  
Standby  
Active  
CC  
‡
Standby current  
t
= MIN  
70  
65  
CC2A  
CC3  
c(SC)  
See Note 4  
RAS only refresh current  
RAS only refresh current  
Standby  
Active  
180  
225  
135  
140  
175  
185  
180  
225  
200  
250  
165  
205  
115  
140  
155  
185  
165  
205  
180  
225  
‡
t = MIN,  
c(SC)  
See Note 4  
See Note 5  
CC3A  
’551x0  
‡
I
t
= MIN,  
= MIN,  
Standby  
Active  
mA  
mA  
Page-mode current  
CC4  
c(P)  
’551x1  
’551x0  
’551x1  
‡
I
t
See Note 5  
See Note 4  
Page-mode current  
CC4A  
c(SC)  
I
I
I
I
CBR current  
See Note 4  
t = MIN,  
Standby  
Active  
mA  
mA  
mA  
mA  
CC5  
‡
CBR current  
CC5A  
CC6  
c(SC)  
See Note 4  
= MIN  
Data-transfer current  
Data-transfer current  
Standby  
Active  
‡
t
CC6A  
c(SC)  
†
‡
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.  
Measured with outputs open  
NOTES: 3. SE is disabled for SQ output leakage tests.  
4. Measured with one address change while RAS = V ; t  
5. Measured with one address change while CASx = V  
, t  
, t  
= MIN  
IL c(rd) c(W) c(TRD)  
IH  
capacitance over recommended ranges of supply voltage and operating free-air temperature,  
f = 1 MHz (see Note 6)  
PARAMETER  
MIN  
MAX  
UNIT  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
C
C
C
C
C
C
C
C
C
Input capacitance, address inputs  
6
7
7
7
7
7
7
7
9
i(A)  
Input capacitance, address strobe inputs  
Input capacitance, write enable input  
Input capacitance, serial clock  
i(RC)  
i(W)  
i(SC)  
i(SE)  
i(DSF)  
i(TRG)  
o(O)  
Input capacitance, serial enable  
Input capacitance, special function  
Input capacitance, transfer register input  
Output capacitance, SQ and DQ  
Output capacitance, QSF  
o(QSF)  
NOTE 6:  
V
CC  
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.  
35  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature (see Note 7)  
’551xx-60  
’551xx-70  
TEST  
CONDITIONS  
ALT.  
SYMBOL  
PARAMETER  
UNIT  
†
MIN MAX  
MIN MAX  
t
t
t
t
t
t
t
Access time, DQx from CASx low  
Access time, DQx from column address  
Access time, DQx from CASx high  
Access time, DQx from TRG low  
Access time, DQx from RAS low  
Access time, SQx from SE low  
Access time, SQx from SC high  
t
t
t
= MAX  
= MAX  
= MAX  
t
17  
30  
35  
15  
60  
12  
15  
20  
35  
40  
20  
70  
15  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
a(C)  
d(RLCL)  
d(RLCL)  
d(RLCL)  
CAC  
t
a(CA)  
a(CP)  
a(G)  
AA  
t
CPA  
OEA  
RAC  
t
t
t
= MAX  
a(R)  
d(RLCL)  
C
C
= 30 pF  
t
a(SE)  
a(SQ)  
L
L
SEA  
SCA  
= 30 pF  
t
Disable time, random output from CASx high  
(see Note 8)  
t
t
C
C
= 50 pF  
t
3
3
15  
15  
3
3
20  
20  
ns  
ns  
dis(CH)  
dis(G)  
L
L
OFF  
OEZ  
Disable time, random output from TRG high  
(see Note 8)  
= 50 pF  
t
Disable time, random output from RAS high  
(see Note 8)  
t
t
t
C
C
C
= 50 pF  
= 30 pF  
= 30 pF  
3
3
0
15  
10  
15  
3
3
0
20  
20  
20  
ns  
ns  
ns  
dis(RH)  
dis(SE)  
dis(WL)  
L
L
L
Disable time, serial output from SE high (see Note 8)  
t
SEZ  
Disable time, random output from WE low  
(see Note 8)  
t
WEZ  
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.  
NOTES: 7. Switching times for RAM-port output are measured with a load equivalent to 1 TTL load and 50 pF. Data out reference level:  
/ V = 2 V/0.8 V. SwitchingtimesforSAM-portoutputaremeasuredwithaloadequivalentto1TTLloadand30pF.Serial-data  
V
OH OL  
out reference level: V  
/ V  
= 2 V/0.8 V.  
and t  
OH OL  
, t  
8.  
t
t
, t  
are specified when the output is no longer driven.  
dis(SE)  
dis(CH), dis(RH) dis(G) dis(WL),  
36  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
timing requirements over recommended ranges of supply voltage and operating free-air  
†
temperature  
’551xx-60  
’551xx-70  
ALT.  
SYMBOL  
UNIT  
MIN  
35  
MAX  
MIN  
40  
MAX  
’551x0  
’551x1  
t
t
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PC  
PC  
RC  
t
Cycle time, page-mode read, write  
c(P)  
30  
30  
t
t
t
t
t
t
t
Cycle time, read  
t
110  
150  
80  
130  
175  
90  
c(rd)  
Cycle time, read-modify-write  
Cycle time, page-mode read-modify-write  
Cycle time, serial clock (see Note 9)  
Cycle time, transfer read  
t
RMW  
c(rdW)  
c(RDWP)  
c(SC)  
t
PRMW  
t
18  
22  
SCC  
t
110  
110  
10  
130  
130  
10  
c(TRD)  
c(W)  
RC  
Cycle time, write  
t
WC  
Pulse duration, CASx high  
t
CPN  
w(CH)  
’551x0  
’551x1  
t
10  
10 000  
10 000  
10  
10 000  
10 000  
CAS  
CAS  
t
Pulse duration, CASx low (see Note 10)  
w(CL)  
t
17  
20  
t
t
t
t
t
t
t
t
t
t
Pulse duration, TRG high  
t
20  
20  
w(GH)  
TP  
RP  
Pulse duration, RAS high  
t
40  
50  
w(RH)  
Pulse duration, RAS low (see Note 11)  
Pulse duration, RAS low (page mode)  
Pulse duration, SC high  
t
60  
10 000  
70  
10 000  
w(RL)  
RAS  
t
60 100 000  
70 100 000  
w(RL)P  
w(SCH)  
w(SCL)  
w(TRG)  
w(WL)  
RASP  
t
5
5
8
8
SC  
Pulse duration, SC low  
t
SCP  
Pulse duration, TRG low  
15  
10  
0
20  
10  
0
Pulse duration, WE low  
t
WP  
Setup time, column address before CASx low  
Setup time, data valid before CASx low, early write  
t
su(CA)  
su(DCL)  
ASC  
DSC  
t
0
0
Setup time, write mask valid before RAS low,  
non-persistent write-per-bit  
t
t
0
0
ns  
su(DQR)  
MS  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, data valid before WE low, late write  
Setup time, row address before RAS low  
Setup time, WE high before first CASx low, read  
Setup time, DSF before first CASx low  
t
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
su(DWL)  
DSW  
t
su(RA)  
ASR  
RCS  
t
0
0
su(rd)  
t
t
t
0
0
su(SFC)  
su(SFR)  
su(TRG)  
su(WCH)  
su(WCL)  
su(WMR)  
su(WRH)  
h(CHrd)  
h(CLCA)  
h(CLD)  
FSC  
FSR  
THS  
Setup time, DSF before RAS low  
0
0
Setup time, TRG before RAS low  
0
0
Setup time, WE low before both CASx high, write  
Setup time, WE low before first CASx low, early write  
Setup time, WE low before RAS low, write-per-bit  
Setup time, WE low before RAS high, write  
t
15  
0
15  
0
CWL  
WCS  
WSR  
t
t
0
0
t
15  
0
15  
0
RWL  
Hold time, WE high after both CASx high, read (see Note 12)  
Hold time, column address after first CASx low  
t
RCH  
t
10  
15  
4
10  
15  
5
CAH  
Hold time, data valid after first CASx low, early write  
Hold time, DQ output after CASx low (TMS551x1)  
t
DH  
t
h(CLQ)  
DHC  
†
Timing measurements are referenced to V max and V min.  
IL  
IH  
NOTES: 9. Cycle time assumes t = 3 ns.  
t
10. In a read-modify-write cycle, t  
and t  
must be observed. Depending on the user’s transition times, this can require  
must be observed. Depending on the user’s transition times, this can require  
d(CLWL)  
su(WCH)  
su(WRH)  
additional CASx low time [t  
11. In a read-modify-write cycle, t  
].  
w(CL)  
and t  
d(RLWL)  
].  
additional RAS low time [t  
w(RL)  
12. Either t  
or t  
must be satisfied for a read cycle.  
h(CHrd)  
h(RHrd)  
37  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
timing requirements over recommended ranges of supply voltage and operating free-air  
†
temperature (continued)  
’551xx-60  
’551xx-70  
ALT.  
SYMBOL  
UNIT  
MIN MAX  
MIN MAX  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, WE low after first CASx low, early write  
Hold time, row address after RAS low  
t
10  
10  
10  
0
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
h(CLW)  
WCH  
t
h(RA)  
RAH  
Hold time, write mask valid after RAS low, non-persistent write-per-bit  
Hold time, WE high after RAS high, read (see Note 12)  
Hold time, column address valid after RAS low (see Note 13)  
Hold time, data valid after RAS low (see Note 13)  
Hold time, WE low after RAS low, write  
t
MH  
h(RDQ)  
h(RHrd)  
h(RLCA)  
h(RLD)  
h(RLW)  
h(RSF)  
h(RWM)  
h(SFC)  
h(SFR)  
h(SHSQ)  
h(TRG)  
h(WLD)  
h(WLG)  
d(CACH)  
t
RRH  
t
30  
35  
30  
30  
10  
10  
10  
4
30  
35  
35  
35  
10  
10  
10  
5
AR  
t
DHR  
t
WCR  
Hold time, DSF after RAS low  
t
FHR  
Hold time, WE low after RAS low, write-per-bit  
Hold time, DSF after first CASx low  
t
RWH  
t
CFH  
RFH  
SOH  
Hold time, DSF after RAS low  
t
Hold time, SQ after SC high  
t
Hold time, TRG after RAS low  
t
10  
15  
10  
30  
10  
15  
10  
45  
THH  
Hold time, data valid after WE low, late write  
Hold time, TRG high after WE low (see Note 14)  
Delay time, column address valid to CASx high  
t
DH  
t
OEH  
t
CAL  
ATH  
RAL  
ASD  
Delay time, column address to TRG high in real-time-load and late-load  
full-register transfer  
t
t
t
t
t
20  
30  
25  
50  
20  
35  
25  
60  
ns  
ns  
ns  
ns  
d(CAGH)  
d(CARH)  
d(CASH)  
d(CAWL)  
Delay time, column address valid to RAS high  
t
Delay time, column address to first SC high after TRG high, early-load  
full-register transfer  
t
Delay time, column address valid to WE low, read-modify-write  
t
AWD  
t
Delay time, both CASx high to RAS low  
Delay time, CASx low to TRG high, read  
t
0
0
ns  
ns  
d(CHRL)  
d(CLGH)  
CRP  
t
17  
20  
Delay time, first CASx low to QSF switching, full-register transfer  
(see Note 15)  
t
t
30  
30  
ns  
d(CLQSF)  
CQD  
t
t
Delay time, CASx low to RAS high  
t
t
17  
0
20  
0
ns  
ns  
d(CLRH)  
RSH  
Delay time, first CASx low to RAS low, CBR refresh  
d(CLRL)  
CSR  
Delay time, first CASx low to first SC high after TRG high, early-load  
full-register transfer  
t
t
t
20  
15  
20  
15  
ns  
ns  
d(CLSH)  
CSD  
Delay time, first CASx low to TRG high, real-time-load and late-load  
full-register transfer  
t
d(CLTH)  
CTH  
t
t
t
t
Delay time, CASx low to WE low, read-modify-write (see Note 16)  
Delay time, first CASx low to DQ in the low-impedance state  
Delay time, data to CASx low  
t
37  
3
45  
2
ns  
ns  
ns  
ns  
d(CLWL)  
d(CLZ)  
d(DCL)  
d(DGL)  
CWD  
t
CLZ  
t
0
0
DZC  
Delay time, data to TRG low  
t
0
0
DZO  
t
Delay time, TRG high before data applied at DQ  
t
10  
15  
ns  
d(GHD)  
OED  
†
Timing measurements are referenced to V max and V min.  
IL IH  
NOTES: 12. Either t  
or t  
must be satisfied for a read cycle.  
h(RHrd)  
13. The minimum value is measured when t  
h(CHrd)  
is set to t  
min as a reference.  
d(RLCL)  
d(RLCL)  
14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.  
15. TRG must disable the output buffers prior to applying data to the DQ pins.  
16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is  
/ V = 2 V/0.8 V.  
V
OH OL  
38  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
timing requirements over recommended ranges of supply voltage and operating free-air  
†
temperature (continued)  
’551xx-60  
’551xx-70  
ALT.  
SYMBOL  
UNIT  
MIN  
MAX  
MIN  
MAX  
Delay time, TRG high to QSF switching, full-register transfer  
(see Note 16)  
t
t
25  
30  
ns  
d(GHQSF)  
TQD  
t
t
Delay time, TRG low to RAS high  
t
10  
3
15  
3
ns  
ns  
d(GLRH)  
ROH  
Delay time, TRG low to DQ in the low-impedance state  
t
OELZ  
d(GLZ)  
Delay time, last SC high at boundary (127 or 255) to RAS low,  
split-register transfer  
t
t
t
t
15  
0
20  
0
ns  
ns  
ns  
d(MSRL)  
d(RHCL)  
d(RHMS)  
d(RLCA)  
Delay time, RAS high to first CASx low, CBR refresh  
t
RPC  
Delay time, RAS high to last SC high at boundary (127 or 255),  
split-register-transfer  
15  
20  
Delay time, RAS low to column address valid  
t
t
t
15  
60  
53  
10  
20  
30  
15  
70  
60  
10  
20  
35  
ns  
ns  
ns  
ns  
ns  
RAD  
CSH  
CSH  
CHR  
RCD  
’551x0  
t
’551x1  
Delay time, RAS low to CASx high  
d(RLCH)  
CBR  
t
t
t
t
Delay time, RAS low to first CASx low (see Note 17)  
43  
65  
50  
70  
d(RLCL)  
Delay time, RAS low to QSF switching, full-register transfer  
(see Note 16)  
t
ns  
ns  
d(RLQSF)  
RQD  
Delay time, RAS low to first SC high after TRG high,  
early-load full-register transfer  
t
t
65  
70  
d(RLSH)  
RSD  
t
t
Delay time, RAS low to TRG high (see Note 18)  
Delay time, RAS low to WE low, read-modify-write  
t
50  
80  
55  
95  
ns  
ns  
d(RLTH)  
RTH  
t
d(RLWL)  
RWD  
Delay time, last SC high at boundary (127 or 255) to QSF switching,  
split-register transfer (see Note 16)  
t
t
20  
25  
ns  
d(SCQSF)  
SQD  
t
t
t
t
t
t
Delay time, SC high to TRG high, full-register transfer  
Delay time, TRG high to RAS high (see Note 18)  
Delay time, TRG high to RAS low (see Note 18)  
Delay time, TRG high to SC high (see Note 18)  
Refresh time interval, memory  
t
5
–10  
40  
5
–10  
50  
ns  
ns  
ns  
ns  
ms  
ns  
d(SCTR)  
d(THRH)  
d(THRL)  
d(THSC)  
rf(MA)  
TSL  
t
TRD  
t
t
t
TRP  
TSD  
REF  
20  
25  
8
8
Transition time  
t
T
3
50  
3
50  
t
†
Timing measurements are referenced to V max and V min.  
IL IH  
NOTES: 16. Switching times for QSF output are measured with a load equivalent to 1 TTL load and 30 pF, and output reference level is  
/ V = 2 V/0.8 V.  
V
OH OL  
17. The maximum value is specified only to assure RAS access time.  
18. Real-time-load and late-load full-register transfer  
39  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(rd)  
t
w(RL)  
t
d(RLCH)  
RAS  
t
w(RH)  
t
t
t
d(CLRH)  
t
t
d(RLCL)  
d(CHRL)  
t
w(CL)  
CASx  
t
w(CH)  
t
d(CACH)  
t
d(RLCA)  
t
d(CARH)  
t
h(RA)  
t
h(RLCA)  
t
su(RA)  
t
h(CLCA)  
t
su(CA)  
A0–A8  
Row  
Column  
t
h(SFR)  
t
su(SFR)  
DSF  
t
d(CLGH)  
t
su(TRG)  
t
d(GLRH)  
t
t
w(TRG)  
h(TRG)  
TRG  
t
t
h(RHrd)  
su(rd)  
t
h(CHrd)  
WE  
t
†
t
t
dis(CH)  
a(G)  
d(DGL)  
Data In  
t
dis(G)  
Data Out  
DQ0–DQ15  
t
d(GLZ)  
t
d(CLZ)  
t
a(C)  
t
a(CA)  
t
a(R)  
†
For TMS551x0, CASx high disables the output regardless of the state of RAS. For TMS551x1, both RAS and CASx must be high to disable the  
output.  
Figure 31. Read-Cycle Timing With CASx-Controlled Output  
40  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(rd)  
t
w(RL)  
d(RLCH)  
t
RAS  
t
w(RH)  
t
t
t
d(CLRH)  
t
d(RLCL)  
t
t
w(CL)  
d(CHRL)  
CASx  
t
w(CH)  
t
d(RLCA)  
t
d(CARH)  
t
h(RA)  
t
h(RLCA)  
t
d(CACH)  
t
su(RA)  
t
h(CLCA)  
t
su(CA)  
A0–A8  
Row  
Column  
t
h(SFR)  
t
su(SFR)  
DSF  
t
d(CLGH)  
t
t
t
d(GLRH)  
su(TRG)  
t
h(TRG)  
w(TRG)  
TRG  
t
h(RHrd)  
t
su(rd)  
t
h(CHrd)  
WE  
t
t
dis(G)  
†
d(DGL)  
Data In  
t
dis(RH)  
t
a(G)  
t
Data Out  
DQ0–DQ15  
d(GLZ)  
t
d(CLZ)  
t
a(C)  
t
a(CA)  
t
a(R)  
†
For TMS551x0, RAS high does not disable the output. For TMS551x1, both RAS and CASx must be high to disable the output.  
Figure 32. Read-Cycle Timing With RAS-Controlled Output  
41  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
d(RLCH)  
t
w(RH)  
t
t
t
d(CLRH)  
t
t
t
d(RLCL)  
t
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
w(CH)  
t
h(RLCA)  
t
t
h(RA)  
d(CACH)  
t
su(CA)  
t
d(RLCA)  
su(RA)  
t
h(CLCA)  
t
d(CARH)  
t
Row  
Column  
A0–A8  
t
su(SFC)  
t
su(SFR)  
t
h(RSF)  
t
t
h(SFC)  
h(SFR)  
DSF  
t
h(TRG)  
t
su(TRG)  
TRG  
t
t
su(WCH)  
t
su(WMR)  
su(WRH)  
t
h(RLW)  
t
t
h(CLW)  
h(RWM)  
t
su(WCL)  
t
w(WL)  
1
2
WE  
t
su(DQR)  
†
t
h(CLD)  
†
t
su(DCL)  
h(RLD)  
t
h(RDQ)  
t
3
DQ0–DQ15  
†
In early-write operations, DQ0–DQ15 are all latched on the first falling edge of CASx. Thus, t  
falling edge of CASx.  
and t  
are referenced only to the first  
h(CLD)  
su(DCL)  
Figure 33. Early-Write-Cycle Timing  
Table 7. Early-Write-Cycle State Table  
STATE  
CYCLE  
1
H
L
2
3
Write operation (nonmasked)  
Don’t care  
Write mask  
Don’t care  
Valid data  
Valid data  
Valid data  
Write operation with nonpersistent write-per-bit  
Write operation with persistent write-per-bit  
L
42  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
t
t
d(CLRH)  
t
t
d(CHRL)  
d(CHRL)  
t
d(RLCL)  
t
t
t
w(CL)  
CASx  
t
d(RLCA)  
t
h(RLCA)  
t
w(CH)  
t
su(CA)  
t
h(CLCA)  
t
h(RA)  
t
d(CACH)  
t
su(RA)  
t
d(CARH)  
Row  
Column  
t
A0–A8  
t
h(RSF)  
t
su(SFC)  
su(SFR)  
t
t
h(SFC)  
h(SFR)  
DSF  
TRG  
t
su(rd)  
t
su(WRH)  
su(WCH)  
h(CLW)  
t
su(TRG)  
t
t
t
d(GHD)  
t
h(RLW)  
t
su(WMR)  
t
h(WLG)  
w(WL)  
t
h(RWM)  
t
WE  
1
t
su(DWL)  
t
su(DQR)  
t
h(WLD)  
t
h(RDQ)  
t
h(RLD)  
2
3
DQ0–DQ15  
Figure 34. Late-Write-Cycle Timing (Output-Enable-Controlled Write)  
Table 8. Late-Write-Cycle State Table  
STATE  
CYCLE  
1
H
L
2
3
Write operation (nonmasked)  
Don’t care  
Write mask  
Don’t care  
Valid data  
Valid data  
Valid data  
Write operation with nonpersistent write-per-bit  
Write operation with persistent write-per-bit  
L
43  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(rdW)  
t
w(RL)  
t
d(RLCH)  
RAS  
t
t
t
w(RH)  
d(CHRL)  
t
t
d(CLRH)  
t
d(RLCL)  
d(CHRL)  
t
w(CL)  
t
h(RA)  
CASx  
t
su(CA)  
w(CH)  
t
su(RA)  
t
h(CLCA)  
t
h(RLCA)  
t
d(CACH)  
t
d(RLCA)  
t
d(CARH)  
A0–A8  
Row  
t
Column  
t
h(RSF)  
t
h(SFC)  
su(SFR)  
t
t
su(SFC)  
h(SFR)  
DSF  
t
t
su(WCH)  
su(rd)  
t
h(TRG)  
t
su(WRH)  
t
d(CAWL)  
t
w(TRG)  
TRG  
t
h(WLG)  
t
h(RLW)  
t
t
h(CLW)  
su(TRG)  
t
d(CLWL)  
t
t
su(WMR)  
t
d(DCL)  
t
h(RWM)  
t
d(CLGH)  
t
w(WL)  
1
2
t
a(CA)  
WE  
t
d(RLWL)  
t
h(WLD)  
t
a(R)  
t
t
d(GHD)  
d(DGL)  
su(DQR)  
t
t
t
a(C)  
h(RDQ)  
su(DWL)  
Valid  
Out  
3
DQ0–DQ15  
t
t
a(G)  
dis(G)  
Figure 35. Read-Modify-Write-Cycle Timing  
Table 9. Read-Modify-Write-Cycle State Table  
STATE  
2
CYCLE  
1
H
L
3
Write operation (nonmasked)  
Don’t care  
Valid data  
Valid data  
Valid data  
Write operation with nonpersistent write-per-bit  
Write operation with persistent write-per-bit  
Write mask  
L
Don’t care  
44  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
t
d(RLCH)  
t
t
t
t
d(CLRH)  
t
d(RLCL)  
t
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
t
w(CH)  
h(CLCA)  
t
h(RLCA)  
t
d(RLCA)  
su(RA)  
t
t
d(CARH)  
d(CACH)  
t
t
h(RA)  
t
su(CA)  
Row  
A0–A8  
t
†
h(RSF)  
Block Address  
t
su(SFR)  
t
su(SFC)  
t
h(SFR)  
t
h(SFC)  
DSF  
TRG  
t
h(TRG)  
t
su(TRG)  
t
su(WCH)  
t
h(RWM)  
t
su(WRH)  
t
su(WMR)  
t
su(WCL)  
t
h(CLW)  
t
h(RLW)  
t
w(WL)  
1
2
WE  
t
h(RLD)  
‡
t
su(DCL)  
t
su(DQR)  
‡
t
h(CLD)  
t
h(RDQ)  
3
DQ0–DQ15  
†
‡
For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.  
In early-write operations, DQ0–DQ15 are all latched on the first falling edge of CASx. Thus, t  
and t  
are referenced only to the first  
h(CLD)  
su(DCL)  
falling edge of CASx.  
Figure 36. Block-Write-Cycle Timing (Early Write)  
Table 10. Block-Write-Cycle State Table  
STATE  
CYCLE  
1
2
3
Block-write operation (nonmasked)  
H
Don’t care  
Write mask  
Don’t care  
Column mask  
Column mask  
Column mask  
Block-write operation with nonpersistent write-per-bit  
Block-write operation with persistent write-per-bit  
L
L
45  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
t
t
t
t
d(CLRH)  
t
d(RLCL)  
t
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
w(CH)  
t
d(RLCA)  
t
t
d(CACH)  
d(CARH)  
t
h(RLCA)  
t
h(RA)  
t
su(CA)  
t
t
su(RA)  
h(CLCA)  
Row  
A0–A8  
t
h(RSF)  
†
Block Address  
t
t
su(SFR)  
t
su(SFC)  
t
h(SFR)  
h(SFC)  
DSF  
TRG  
t
su(TRG)  
t
h(CLW)  
t
su(WCH)  
t
d(GHD)  
t
h(RLW)  
t
su(WRH)  
t
su(WMR)  
t
h(WLG)  
t
h(RWM)  
t
w(WL)  
1
WE  
t
su(DQR)  
t
‡
t
su(DWL)  
‡
h(RDQ)  
t
h(WLD)  
t
h(RLD)  
3
2
DQ0–DQ15  
†
‡
For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.  
Inlate-writeoperations,DQ0–DQ15arealllatchedonthefirstfallingedgeofWE.Thust  
andt  
arereferencedonlytothefirstfalling  
su(DWL)  
h(WLD)  
edge of WE.  
Figure 37. Block-Write-Cycle Timing (Late Write)  
Table 11. Block-Write-Cycle State Table  
STATE  
CYCLE  
1
2
3
Block-write operation (nonmasked)  
H
Don’t care  
Write mask  
Don’t care  
Column mask  
Column mask  
Column mask  
Block-write operation with nonpersistent write-per-bit  
Block-write operation with persistent write-per-bit  
L
L
46  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
t
w(RH)  
t
d(RLCH)  
t
t
t
d(CLRH)  
t
t
d(RLCL)  
t
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
w(CH)  
t
h(RA)  
Refresh Row  
t
su(RA)  
A0–A8  
t
su(SFC)  
t
su(SFR)  
t
h(RSF)  
t
t
h(SFC)  
h(SFR)  
DSF  
t
h(TRG)  
t
su(TRG)  
TRG  
t
t
su(WCH)  
su(WMR)  
t
su(WRH)  
t
h(RLW)  
t
h(CLW)  
t
h(RWM)  
t
su(WCL)  
t
w(WL)  
WE  
†
t
su(DCL)  
†
t
h(CLD)  
t
h(RLD)  
Write Mask  
DQ0–DQ15  
†
In early-write operations, DQ0–DQ15 are all latched on the first falling edge of CASx. Thus, t  
falling edge of CASx.  
and t  
are referenced only to the first  
h(CLD)  
su(DCL)  
Figure 38. Load-Write-Mask-Register-Cycle Timing (Early-Write Load)  
47  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
t
t
d(CLRH)  
t
t
d(CHRL)  
d(CHRL)  
t
d(RLCL)  
t
t
t
w(CL)  
CASx  
t
w(CH)  
t
h(RA)  
Refresh Row  
t
su(RA)  
A0–A8  
t
h(RSF)  
t
su(SFR)  
t
t
su(SFC)  
t
h(SFR)  
h(SFC)  
DSF  
TRG  
t
su(WRH)  
t
t
su(WCH)  
su(TRG)  
t
h(CLW)  
t
d(GHD)  
t
h(RLW)  
t
su(WMR)  
t
h(WLG)  
t
h(RWM)  
t
w(WL)  
WE  
t
su(DWL)  
t
h(WLD)  
t
h(RLD)  
Write Mask  
DQ0–DQ15  
Figure 39. Load-Write-Mask-Register-Cycle Timing (Late-Write Load)  
48  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
t
t
t
t
d(CLRH)  
t
d(RLCL)  
t
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
h(RA)  
t
w(CH)  
t
su(RA)  
Refresh Row  
A0–A8  
t
h(SFC)  
t
h(RSF)  
t
t
su(SFR)  
su(TRG)  
t
su(SFC)  
t
h(SFR)  
DSF  
TRG  
t
h(TRG)  
t
su(WCH)  
t
su(WMR)  
t
su(WRH)  
t
h(RLW)  
t
t
h(RWM)  
h(CLW)  
t
su(WCL)  
WE  
t
t
w(WL)  
†
t
su(DCL)  
†
h(CLD)  
t
h(RLD)  
DQ0–  
DQ15  
Valid Color Input  
†
In early-write operations, DQ0–DQ15 are all latched on the first falling edge of CASx. Thus, t  
falling edge of CASx.  
and t  
are referenced only to the first  
h(CLD)  
su(DCL)  
Figure 40. Load-Color-Register-Cycle Timing (Early-Write Load)  
49  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(W)  
t
w(RL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
t
t
t
t
d(CLRH)  
t
t
d(RLCL)  
d(CHRL)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
t
h(RSF)  
w(CH)  
t
h(RA)  
su(RA)  
Refresh Row  
t
A0–A8  
t
t
h(SFC)  
su(SFR)  
t
su(SFC)  
t
h(SFR)  
DSF  
TRG  
t
su(TRG)  
t
h(CLW)  
t
su(WRH)  
t
su(WCH)  
t
d(GHD)  
t
h(RLW)  
t
su(WMR)  
t
h(WLG)  
t
w(WL)  
WE  
t
su(DWL)  
t
h(WLD)  
t
h(RLD)  
DQ0–  
DQ15  
Valid Color Input  
Figure 41. Load-Color-Register-Cycle Timing (Late-Write Load)  
50  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RH)  
t
w(RL)P  
RAS  
t
t
d(CLRH)  
d(RLCL)  
t
t
t
d(CHRL)  
w(CH)  
t
t
t
w(CL)  
CASx  
t
d(RLCA)  
t
d(RLCH)  
t
c(P)  
t
su(RA)  
t
t
su(CA)  
d(CACH)  
t
h(CLCA)  
h(RA)  
t
d(CARH)  
t
h(RLCA)  
h(SFR)  
Row  
Column  
Column  
A0–A8  
t
t
d(CLGH)  
t
su(SFR)  
DSF  
t
h(TRG)  
t
su(TRG)  
TRG  
WE  
t
su(WMR)  
t
t
h(RHrd)  
su(rd)  
t
a(C)  
t
a(CA)  
t
d(DGL)  
Data In  
t
t
a(CA)  
a(G)  
t
t
t
dis(G)  
a(R)  
a(CP)  
t
DQ0–  
DQ15  
Data Out  
Data Out  
dis(CH)  
t
d(DCL)  
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing  
specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write  
mode (normal, block write, etc.).  
Figure 42. Enhanced-Page-Mode Read-Cycle Timing (TMS551x0)  
51  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RH)  
t
w(RL)P  
RAS  
t
t
d(CLRH)  
d(RLCL)  
t
t
t
w(CH)  
t
d(CHRL)  
t
t
w(CL)  
CASx  
t
d(RLCA)  
t
d(RLCH)  
t
c(P)  
t
su(RA)  
t
t
su(CA)  
d(CACH)  
t
h(CLCA)  
h(RA)  
t
d(CARH)  
t
h(RLCA)  
h(SFR)  
Row  
Column  
Column  
A0–A8  
t
t
d(CLGH)  
t
su(SFR)  
DSF  
t
h(TRG)  
t
su(TRG)  
TRG  
WE  
t
su(WMR)  
t
t
h(RHrd)  
t
su(rd)  
t
a(C)  
t
t
dis(WL)  
h(CLQ)  
t
a(CA)  
t
d(DGL)  
Data In  
t
t
a(CA)  
a(G)  
dis(RH)  
t
t
t
a(R)  
dis(G)  
a(CP)  
DQ0–  
DQ15  
Data Out  
Data Out  
t
d(DCL)  
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing  
specifications are not violated and the proper state of DSF is latched on the falling edge of RAS and CASx to select the desired write  
mode (normal, block write, etc.).  
Figure 43. Extended-Data-Output Read-Cycle Timing (TMS551x1)  
52  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RL)P  
RAS  
t
t
t
d(RLCH)  
c(P)  
w(RH)  
t
d(RLCL)  
t
t
d(CLRH)  
w(CH)  
t
t
t
d(CHRL)  
t
w(CL)  
d(CHRL)  
CASx  
d(RLCA)  
t
su(CA)  
t
su(RA)  
t
d(CACH)  
t
t
h(RA)  
h(CLCA)  
h(RLCA)  
t
t
d(CARH)  
Row  
Column  
Column  
A0–  
A8  
t
su(SFR)  
t
t
h(RSF)  
t
h(SFC)  
t
h(SFC)  
h(SFR)  
t
t
su(SFC)  
su(SFC)  
1
2
2
DSF  
TRG  
t
su(TRG)  
t
h(TRG)  
See Note A  
t
t
su(WMR)  
su(WCH)  
t
su(WCH)  
t
h(RWM)  
t
su(WRH)  
t
w(WL)  
WE  
3
†
t
su(DWL)  
t
t
su(DQR)  
t
†
†
t
t
h(CLD)  
su(DCL)  
†
h(WLD)  
h(RDQ)  
t
h(RLD)  
DQ0–  
DQ15  
4
5
5
†
DQ0–DQ15arelatchedoneitherthefallingedgeofWEorthefirstfallingedgeofCASx,whicheveroccurslater.Inearly-writeoperations,t  
su(DWL)  
andt  
arenotapplicable; t  
andt  
arereferencedonlytothefirstfallingedgeofCASx. Inlate-writeoperations, t and  
h(WLD)  
su(DCL)  
h(CLD)  
su(DCL)  
t
are not applicable.  
h(CLD)  
NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications  
are not violated.  
Figure 44. Enhanced-Page-Mode Write-Cycle Timing  
Table 12. Enhanced-Page-Mode Write-Cycle State Table  
STATE  
CYCLE  
1
L
L
L
2
L
L
L
3
H
L
4
5
Write operation (nonmasked)  
Don’t care  
Write mask  
Don’t care  
Valid data  
Valid data  
Valid data  
Write operation with nonpersistent write-per-bit  
Write operation with persistent write-per-bit  
L
Load-write-mask register on either the first falling edge of  
WE or the falling edge of CASx, whichever occurs later.  
H
L
H
Don’t care  
Write mask  
53  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RL)P  
RAS  
t
w(RH)  
t
d(RLCH)  
t
d(CLRH)  
t
t
t
t
d(CHRL)  
c(RDWP)  
t
t
d(RLCL)  
w(CH)  
d(CHRL)  
t
t
w(CL)  
CASx  
h(RA)  
t
d(RLCA)  
t
t
d(CARH)  
su(CA)  
t
h(CLCA)  
su(RA)  
t
t
d(CACH)  
h(RLCA)  
Row  
Column  
t
Column  
A0–A8  
t
h(SFR)  
su(SFR)  
t
su(SFC)  
t
t
t
h(SFC)  
h(SFC)  
su(SFC)  
1
2
t
2
DSF  
t
su(rd)  
su(WCH)  
d(CLWL)  
d(CAWL)  
t
su(WCH)  
t
t
d(DCL)  
t
t
d(CLGH)  
t
d(RLWL)  
t
t
t
t
h(TRG)  
d(CLGH)  
su(WRH)  
t
su(TRG)  
w(TRG)  
TRG  
WE  
t
w(TRG)  
t
su(WMR)  
t
t
w(WL)  
h(RWM)  
3
t
a(C)  
t
t
a(CA)  
su(DWL)  
t
t
h(WLD)  
su(DQR)  
t
t
h(WLD)  
t
d(DCL)  
t
t
d(GHD)  
5
su(DWL)  
h(RDQ)  
t
a(CP)  
DQ0–DQ15  
4
Valid Out  
5
t
t
t
Valid Out  
a(G)  
d(DGL)  
t
d(DGL)  
t
dis(G)  
d(GHD)  
t
a(R)  
t
a(C)  
NOTE A: A read cycle or a write cycle can be mixed with read-modify-write cycles as long as the read and write timing specifications are not  
violated.  
Figure 45. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing  
Table 13. Enhanced Page-Mode Read-Modify-Write-Cycle State Table  
STATE  
CYCLE  
1
L
L
L
2
L
L
L
3
H
L
4
5
Write operation (nonmasked)  
Don’t care  
Write mask  
Don’t care  
Valid data  
Valid data  
Valid data  
Write operation with nonpersistent write-per-bit  
Write operation with persistent write-per-bit  
L
Load-write-mask register on either the first falling edge of  
WE or the falling edge of CASx, whichever occurs later.  
H
L
H
Don’t care  
Write mask  
54  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RH)  
t
w(RL)P  
RAS  
t
t
d(CLRH)  
d(RLCL)  
t
t
t
w(CH)  
t
d(CHRL)  
t
t
w(CL)  
CASx  
t
d(RLCA)  
t
d(RLCH)  
t
c(P)  
t
su(RA)  
t
t
su(CA)  
d(CACH)  
t
h(CLCA)  
h(RA)  
t
d(CARH)  
t
h(RLCA)  
h(SFR)  
Row  
Column  
Column  
A0–A8  
t
t
d(CLGH)  
t
su(SFR)  
su(TRG)  
DSF  
t
su(WCL)  
t
h(TRG)  
t
t
h(CLW)  
TRG  
WE  
t
su(WMR)  
t
su(rd)  
t
w(WL)  
t
a(C)  
t
a(CA)  
t
h(CLD)  
t
d(DGL)  
Data In  
t
a(G)  
t
su(DCL)  
t
dis(WL)  
t
a(R)  
DQ0–  
DQ15  
Data In  
Data Out  
t
d(DCL)  
Figure 46. Extended-Data-Output Read-Followed-by-Write-Cycle Timing (TMS551x1)  
55  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
w(RL)P  
RAS  
t
t
t
w(RH)  
d(RLCH)  
d(RLCL)  
c(P)  
t
t
d(CLRH)  
t
w(CH)  
w(CL)  
t
d(CHRL)  
t
t
d(CHRL)  
CASx  
t
d(RLCA)  
t
h(CLCA)  
t
su(CA)  
t
t
d(CACH)  
h(RA)  
t
h(RLCA)  
Block Address  
t
d(CARH)  
t
su(RA)  
†
†
Row  
Block Address  
A0–A8  
t
h(SFR)  
t
t
h(SFC)  
su(SFC)  
h(SFC)  
t
t
t
su(SFC)  
su(SFR)  
DSF  
TRG  
t
h(TRG)  
su(TRG)  
t
See Note A  
su(WCH)  
t
su(WMR)  
t
su(WCH)  
t
t
w(WL)  
t
t
su(WRH)  
h(RWM)  
WE  
1
‡
t
‡
su(DWL)  
t
h(CLD)  
t
su(DQR)  
‡
t
h(WLD)  
‡
t
t
h(RDQ)  
su(DCL)  
3
t
h(RLD)  
DQ0–  
DQ15  
2
3
†
‡
For 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8.  
DQ0–DQ15arelatchedoneitherthefallingedgeofWEorthefirstfallingedgeofCASx,whicheveroccurslater.Inearly-writeoperations,t  
su(DWL)  
and  
andt  
t
arenotapplicable; t  
are not applicable.  
andt  
arereferencedonlytothefirstfallingedgeofCASx. Inlate-writeoperations, t  
h(CLD) su(DCL)  
h(WLD)  
su(DCL)  
h(CLD)  
NOTE A: A read cycle or a read-modify-write cycle can be mixed with write cycles as long as read- and read-modify-write timing specifications  
are not violated.  
Figure 47. Enhanced-Page-Mode Block-Write-Cycle Timing  
Table 14. Enhanced-Page-Mode Block-Write-Cycle State Table  
STATE  
CYCLE  
1
H
L
2
3
Block-write operation (nonmasked)  
Don’t care  
Write mask  
Don’t care  
Column mask  
Column mask  
Column mask  
Block-write operation with nonpersistent write-per-bit  
Block-write operation with persistent write-per-bit  
L
56  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(rd)  
t
w(RL)  
RAS  
t
t
w(RH)  
t
t
t
d(RHCL)  
t
d(CHRL)  
d(CHRL)  
CASx  
t
h(RA)  
t
su(RA)  
Row  
A0–A8  
DSF  
TRG  
t
h(TRG)  
t
su(TRG)  
WE  
DQ0–  
DQ15  
Hi-Z  
Figure 48. RAS-Only Refresh-Cycle Timing  
57  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(rd)  
t
w(RH)  
t
w(RL)  
RAS  
t
d(RHCL)  
t
t
t
d(CLRL)  
t
d(RLCH)  
CASx  
t
d(CHRL)  
t
t
t
t
su(RA)  
h(RA)  
1
2
A0–A8  
su(SFR)  
h(SFR)  
DSF  
TRG  
t
t
h(RWM)  
su(WMR)  
3
WE  
Hi-Z  
DQ0–DQ15  
Figure 49. CBR-Refresh-Cycle TIming  
Table 15. CBR-Cycle State Table  
STATE  
CYCLE  
1
2
L
3
H
H
L
CBR refresh with option reset  
CBR refresh with no reset (CBRN)  
CBR refresh with stop point set and no reset (CBRS)  
Don’t care  
Don’t care  
H
H
Stop address  
58  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
Memory Read Cycle  
Refresh Cycle  
Refresh Cycle  
t
c(rd)  
t
c(rd)  
t
c(rd)  
t
w(RH)  
t
w(RH)  
t
t
w(RL)  
w(RL)  
RAS  
t
d(CARH)  
t
d(RLCH)  
t
t
d(CHRL)  
t
t
w(CL)  
CASx  
t
d(RLCA)  
t
su(RA)  
t
su(RA)  
t
h(CLCA)  
t
su(CA)  
t
h(RA)  
t
h(RA)  
t
h(RA)  
t
t
su(RA)  
t
t
su(RA)  
Col  
h(RA)  
Row  
1
1
2
1
2
A0–A8  
t
t
su(SFR)  
su(SFR)  
t
su(SFR)  
t
h(SFR)  
t
h(SFR)  
h(SFR)  
DSF  
2
t
h(RHrd)  
t
dis(CH)  
t
su(TRG)  
t
t
h(TRG)  
dis(G)  
t
d(GLRH)  
TRG  
WE  
t
su(WMR)  
t
t
su(WMR)  
t
su(rd)  
t
h(RWM)  
t
h(RWM)  
t
a(G)  
3
3
3
t
a(C)  
t
a(R)  
DQ0–  
DQ15  
Data Out  
Figure 50. Hidden-Refresh-Cycle Timing  
Table 16. Hidden-Refresh-Cycle State Table  
STATE  
CYCLE  
1
2
L
3
H
H
L
CBR refresh with option reset  
Don’t care  
Don’t care  
Stop address  
CBR refresh with no reset (CBRN)  
H
H
CBR refresh with stop point set and no option reset (CBRS)  
59  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(TRD)  
t
w(RL)  
t
d(RLCL)  
RAS  
t
w(RH)  
t
d(RLCH)  
t
d(CHRL)  
t
d(CARH)  
t
t
w(CL)  
CASx  
d(RLCA)  
t
h(RA)  
t
su(CA)  
t
h(CLCA)  
t
su(RA)  
t
h(RLCA)  
See Note C  
Tap Point  
A0–A8  
Row  
A0–A8  
DSF  
t
su(SFR)  
t
h(SFR)  
t
su(TRG)  
t
h(TRG)  
TRG  
WE  
t
w(GH)  
t
h(RWM)  
t
t
su(WMR)  
d(CASH)  
See Note A  
DQ0–  
DQ15  
Hi-Z  
t
d(SCTR)  
t
d(CLSH)  
t
t
w(SCH)  
w(SCL)  
t
d(RLSH)  
SC  
SQ  
t
w(SCH)  
t
t
c(SC)  
a(SQ)  
t
a(SQ)  
t
t
h(SHSQ)  
Old Data  
h(SHSQ)  
Old Data  
New Data  
t
d(GHQSF)  
Tap Point Bit A7  
QSF  
SE  
t
d(CLQSF)  
H
L
t
d(RLQSF)  
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The  
memory-to-data-register-transfercycle is used to load the data registers in parallel from the memory array. The 256 locations in each  
data register are written into from the 256 corresponding columns of the selected row.  
B. Once data is transferred into the data registers, SAM is in the serial-read mode (that is, SQx is enabled), allowing data to be shifted  
out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition  
of SC.  
C. A0–A7: register tap point; A8: identifies the DRAM half of the row  
D. Early-load operation is defined as t  
) min < t  
) < t  
min.  
d(RLTH)  
h(TRG  
h(TRG  
Figure 51. Full-Register-Transfer Read Timing, Early-Load Operations  
60  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(TRD)  
t
w(RL)  
RAS  
t
d(RLCL)  
t
w(RH)  
t
d(RLCH)  
t
d(CHRL)  
t
w(CL)  
CASx  
t
d(RLCA)  
t
h(RA)  
t
t
su(CA)  
t
su(RA)  
h(RLCA)  
t
See Note C  
h(CLCA)  
Tap Point  
A0–A8  
Row  
A0–A8  
DSF  
t
t
su(SFR)  
h(SFR)  
t
d(CLTH)  
t
d(THRL)  
d(THRH)  
t
su(TRG)  
t
See Note D  
t
d(CAGH)  
t
d(RLTH)  
TRG  
WE  
t
w(GH)  
t
h(RWM)  
t
su(WMR)  
t
d(SCTR)  
t
d(THSC)  
See Note A  
See Note B  
DQ0–  
Hi-Z  
DQ15  
t
w(SCH)  
SC  
SQ  
t
a(SQ)  
t
a(SQ)  
t
c(SC)  
t
h(SHSQ)  
t
w(SCL)  
t
h(SHSQ)  
Old Data  
Old Data  
Old Data  
New Data  
t
d(GHQSF)  
QSF  
SE  
Tap Point Bit A7  
t
H
L
d(CLQSF)  
t
d(RLQSF)  
NOTES: A. DQ outputs remain in the high-impedance state for the entire memory-to-data-register-transfer cycle. The memory to data  
register-transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data register  
are written into from the 256 corresponding columns of the selected row.  
B. Once data is transferred into the data registers, SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out  
of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive transition  
of SC.  
C. A0–A7: register tap point; A8: identifies the DRAM half of the row  
D. Late-load operation is defined as t  
) < 0 ns.  
d(THRH  
Figure 52. Full-Register-Transfer Read Timing, Real-Time Load Operation/Late-Load Operation  
61  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
t
c(TRD)  
t
w(RH)  
t
w(RL)  
t
RAS  
CASx  
d(RLCL)  
t
d(CHRL)  
t
t
w(CH)  
d(RLCH)  
t
t
d(RLCA)  
w(CL)  
t
su(CA)  
t
h(RA)  
t
t
h(CLCA)  
su(RA)  
A0–A8  
Tap Point A0–A8  
Row  
t
See Note A  
su(TRG)  
t
h(TRG)  
TRG  
DSF  
t
h(SFR)  
t
su(SFR)  
t
h(RWM)  
t
su(WMR)  
WE  
DQ0–  
DQ15  
Hi-Z  
t
d(MSRL)  
t
d(RHMS)  
t
c(SC)  
t
t
c(SC)  
w(SCH)  
t
w(SCL)  
Bit 127  
or 255  
Tap  
Point M  
Bit 255  
or 127  
Tap  
Point N  
SC  
SQ  
t
t
a(SQ)  
t
t
a(SQ)  
t
a(SQ)  
w(SCL)  
h(SHSQ)  
Bit 126 or  
Bit 254  
Bit 127 or  
Bit 255  
Bit 127 or  
Bit 255  
Tap  
Point N  
Tap Point M  
t
t
a(SQ)  
d(SCQSF)  
t
d(SCQSF)  
QSF  
SE  
MSB Old  
New MSB  
V
IL  
NOTE A: A0–A6: tap point of the given half; A7: don’t care; A8: identifies the DRAM half of the row  
Figure 53. Split-Register-Transfer Read Timing  
62  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
RAS  
TRG  
t
su(TRG)  
t
h(TRG)  
t
c(SC)  
t
t
w(SCH)  
c(SC)  
t
w(SCH)  
t
w(SCH)  
t
w(SCL)  
t
w(SCL)  
SC  
t
a(SQ)  
t
a(SQ)  
t
a(SQ)  
t
t
h(SHSQ)  
h(SHSQ)  
t
h(SHSQ)  
SQ  
SE  
Valid Out  
Valid Out  
Valid Out  
t
a(SE)  
NOTE A: While reading data through the serial-data register, TRG is a don’t care, except TRG must be held high when RAS goes low. This is  
to avoid the initiation of a register-data transfer operation.  
Figure 54. Serial-Read Timing (SE = V )  
IL  
63  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
RAS  
TRG  
t
su(TRG)  
t
h(TRG)  
t
c(SC)  
t
c(SC)  
t
w(SCH)  
t
w(SCH)  
t
w(SCH)  
t
w(SCL)  
t
w(SCL)  
SC  
t
a(SQ)  
t
a(SQ)  
t
a(SQ)  
t
h(SHSQ)  
t
a(SE)  
t
h(SHSQ)  
Valid Out  
SQ  
SE  
Valid Out  
Valid Out  
Valid Out  
t
dis(SE)  
NOTE A: While reading data through the serial-data register, TRG is a don’t care except TRG must be held high when RAS goes low. This is  
to avoid the initiation of a register-data transfer operation.  
Figure 55. Serial-Read Timing (SE-Controlled Read)  
64  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
PARAMETER MEASUREMENT INFORMATION  
RAS  
CASx  
ADDR  
RowTap1  
(low)  
RowTap1  
(high)  
RowTap2  
(low)  
RowTap2  
(high)  
TRG  
DSF  
CASE I  
SC  
Tap1  
(low)  
Bit Tap1  
127 (high)  
Bit  
255  
Tap2  
(low)  
Bit  
127  
QSF  
CASE II  
SC  
Tap1  
(high)  
Tap1  
(low)  
Bit  
127  
Bit  
255  
Tap2  
(low)  
Bit  
127  
QSF  
CASE III  
SC  
Tap1  
(low)  
Bit Tap1  
127 (high)  
Bit  
255  
Tap2  
(low)  
Bit  
127  
QSF  
Split Register to the  
High Half of the  
Data Register  
Split Register to the  
Split Register to the  
High Half of the  
Data Register  
Full-Register-Transfer Read  
Low Half of the  
Data Register  
NOTES: A. In order to achieve proper split-register operation, a full-register-transfer read should be performed before the first  
split-register-transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then  
begin either after the full-register-transfer read cycle (CASE I), during the first split-register-transfer cycle (CASE II), or even after  
the first split-register-transfer cycle (CASE III). There is no minimum requirement of SC clock between the full-register-transfer read  
cycle and the first split-register cycle.  
B. Asplit-register-transferintotheinactivehalfisnotalloweduntilt  
ismet.t  
istheminimumdelaytimebetweentherising  
d(MSRL)  
d(MSRL)  
edge of the serial clock of the last bit (bit 127 or 255) and the falling edge of RAS of the split-register-transfer cycle into the inactive  
half. After the t is met, the split-register-transfer into the inactive half must also satisfy the minimum t requirement.  
d(MSRL)  
d(RHMS)  
t
is the minimum delay time between the rising edge of RAS of the split-register-transfer cycle into the inactive half and the  
d(RHMS)  
rising edge of the serial clock of the last bit (bit 127 or 255).  
Figure 56. Split-Register Operating Sequence  
65  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
TMS55160, TMS55161, TMS55170, TMS55171  
262144 BY 16-BIT MULTIPORT VIDEO RAMS  
SMVS464 – MARCH 1996  
MECHANICAL DATA  
DGH (R-PDSO-G64)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,45  
0,25  
M
0,80  
64  
0,12  
33  
0,15 NOM  
12,12 14,50  
11,96 14,00  
Gage Plane  
0,25  
1
32  
0°–5°  
0,70  
0,40  
26,42  
26,17  
Seating Plane  
0,10  
2,38 MAX  
0,00 MIN  
4040068/B 10/94  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Plastic body dimensions do not include mold flash or protrusion. Maximum mold protrusion is 0,125.  
device symbolization  
TI  
-SS  
P
Speed Code (-60, -70)  
Package Code  
TMS551xx  
DGH  
LLLL  
W
B
Y
M
Assembly Site Code  
Lot Traceability Code  
Month Code  
Year Code  
Die Revision Code  
Wafer Fab Code  
66  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with  
TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary  
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except  
those mandated by government requirements.  
Customers are responsible for their applications using TI components.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
products or services might be or are used. TI’s publication of information regarding any third party’s products  
or services does not constitute TI’s approval, license, warranty or endorsement thereof.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation  
or reproduction of this information with alteration voids all warranties provided for an associated TI product or  
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.  
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for  
that product or service voids all express and any implied warranties for the associated TI product or service,  
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.  
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2001, Texas Instruments Incorporated  

相关型号：

TMS55160-60DGH

 256KX16 VIDEO DRAM, 60ns, PDSO64, PLASTIC, SOP-64
TI

TMS55160-60DGH

 256KX16 VIDEO DRAM, 60ns, PDSO64, PLASTIC, SOP-64
ROCHESTER

TMS55160-70DGHR

 256KX16 VIDEO DRAM, 70ns, PDSO64, PLASTIC, SOP-64
TI

TMS55160-80DGH

 256KX16 VIDEO DRAM, 80ns, PDSO64, PLASTIC, SOP-64
TI

TMS55161

 262144 BY 16-BIT MULTIPORT VIDEO RAMS
TI

TMS55161-60DGH

 256KX16 VIDEO DRAM, 60ns, PDSO64, PLASTIC, SOP-64
ROCHESTER

TMS55161-70DGH

 256KX16 VIDEO DRAM, 70ns, PDSO64, PLASTIC, SOP-64
TI

TMS55161-80DGH

 256KX16 VIDEO DRAM, 80ns, PDSO64, PLASTIC, SOP-64
TI

TMS55165

 262144 BY 16-BIT MULTIPORT VIDEO RAM
TI

TMS55165-60DGH

 262144 BY 16-BIT MULTIPORT VIDEO RAM
TI

TMS55165-70DGH

 262144 BY 16-BIT MULTIPORT VIDEO RAM
TI

TMS55165-80DGH

 Fast Page Mode VRAM
ETC
©2020 ICPDF网 联系我们和版权申明