TMS5701115CZWTQQ1 [TI]
16/32 位 RISC 闪存 MCU，Cortex R4F，通过 Q100 车规认证，Flexray | ZWT | 337 | -40 to 125;
| 型号： | TMS5701115CZWTQQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16/32 位 RISC 闪存 MCU，Cortex R4F，通过 Q100 车规认证，Flexray | ZWT | 337 | -40 to 125 闪存 |
| 文件： | 总177页 (文件大小：9819K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMS570LS1115
SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
TMS570LS1115 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1 Features
1
• High-Performance Automotive-Grade
• Enhanced Timing Peripherals for Motor Control
Microcontroller for Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– 7 Enhanced Pulse Width Modulator (ePWM)
Modules
– 6 Enhanced Capture (eCAP) Modules
– Built-In Self-Test (BIST) for CPU and On-chip
RAMs
– 2 Enhanced Quadrature Encoder Pulse (eQEP)
Modules
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
• Two Next Generation High-End Timer (N2HET)
Modules
• ARM® Cortex®-R4F 32-Bit RISC CPU
– 1.66 DMIPS/MHz With 8-Stage Pipeline
– FPU With Single- and Double-Precision
– 12-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM Each With Parity
Protection
– Each N2HET Includes Hardware Angle
Generator
– Dedicated High-End Timer Transfer Unit (HTU)
for Each N2HET
– Up to 180-MHz System Clock
– Core Supply Voltage (VCC): 1.14 to 1.32 V
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
• Integrated Memory
• Two 12-Bit Multibuffered Analog-to-Digital
Converter (MibADC) Modules
– ADC1: 24 Channels
– 1MB of Program Flash With ECC
– 128KB of RAM With ECC
– 64KB of Flash for Emulated EEPROM With
ECC
– ADC2: 16 Channels Shared With ADC1
– 64 Result Buffers Each With Parity Protection
• Multiple Communication Interfaces
– FlexRay Controller With 2 Channels
• 16-Bit External Memory Interface (EMIF)
• Common Platform Architecture
•
•
8KB of Message RAM With Parity Protection
Dedicated FlexRay Transfer Unit (FTU)
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer (OS Timer)
– 128-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity Protection for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• Separate Nonmodulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• Advanced JTAG Security Module (AJSM)
• Calibration Capabilities
– Three CAN Controllers (DCANs)
•
•
64 Mailboxes Each With Parity Protection
Compliant to CAN Protocol Version 2.0A and
2.0B
– Inter-Integrated Circuit (I2C)
– Three Multibuffered Serial Peripheral Interface
(MibSPI) Modules
•
•
128 Words Each With Parity Protection
8 Transfer Groups
– Up to Two Standard Serial Peripheral Interface
(SPI) Modules
– Two UART (SCI) Interfaces, One With Local
Interconnect Network (LIN 2.1) Interface
Support
• Packages
– Parameter Overlay Module (POM)
• 16 General-Purpose Input/Output (GPIO) Pins
Capable of Generating Interrupts
– 144-Pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS570LS1115
SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
www.ti.com
1.2 Applications
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•
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Braking Systems (ABS and ESC)
Electric Power Steering (EPS)
HEV and EV Inverter Systems
Battery Management Systems
•
•
•
•
Active Driver Assistance Systems
Aerospace and Avionics
Railway Communications
Off-road Vehicles
1.3 Description
The TMS570LS1115 device is a high-performance automotive-grade microcontroller family for safety
systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on
both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral
I/Os.
The TMS570LS1115 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient
1.66 DMIPS/MHz, and has configurations which can run up to 180 MHz providing up to 298 DMIPS. The
device supports the word-invariant big-endian [BE32] format.
The TMS570LS1115 device has 1MB of integrated flash and 128KB of data RAM with single-bit error
correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically
erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash
operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations.
When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM
supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout
the supported frequency range.
The TMS570LS1115 device features peripherals for real-time control-based applications, including two
Next Generation High-End Timer (N2HET) timing coprocessors with up to 44 I/O terminals, seven
Enhanced Pulse Width Modulator (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP)
modules, two Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital
Converters (ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for
applications requiring multiple sensor information and drive actuators with complex and accurate time
pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data
to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.
The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or
intervention. The ePWM is easy to use and it supports both high-side and low-side PWM and deadband
generation. With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM
module is ideal for digital motor control applications.
The eCAP module is essential in systems where the accurately timed capture of external events is
important. The eCAP can also be used to monitor the ePWM outputs or for simple PWM generation when
the eCAP is not needed for capture applications.
The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position,
direction, and speed information from a rotating machine as used in high-performance motion and
position-control systems.
2
Device Overview
Copyright © 2012–2015, Texas Instruments Incorporated
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SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. Each MibADC
supports three separate groupings of channels. Each group can be converted once when triggered or
configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility
with older devices or faster conversion time is desired. MibADC1 also supports the use of external analog
multiplexers.
The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three
DCANs, one I2C, and one FlexRay controller with two channels. The SPI provides a convenient method of
serial high-speed communications between similar shift-register type devices. The LIN supports the Local
Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-
Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a
serial, multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh
environments (for example, automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The FlexRay controller uses a dual-channel serial, fixed time base multimaster
communication protocol with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU)
enables autonomous transfers of FlexRay data to and from main CPU memory. Transfers are protected
by a dedicated, built-in MPU.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100
and 400 Kbps.
A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the
mapping between the available clock sources and the device clock domains.
The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of
the device operating frequency.
The Direct Memory Access (DMA) controller has 16 channels, 32 control packets, and parity protection on
its memory. An MPU is built into the DMA to protect memory against erroneous transfers.
The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt or
external error pin (ball) is triggered when a fault is detected. The nERROR terminal can be monitored
externally as an indicator of a fault condition in the microcontroller.
The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous
memories or other slave devices.
A Parameter Overlay Module (POM) enhances the calibration capabilities of application code. The POM
can reroute flash accesses to internal memory or to the EMIF, thus avoiding the reprogramming steps
necessary for parameter updates in flash.
With integrated safety features and a wide choice of communication and control peripherals, the
TMS570LS1115 device is an ideal solution for high-performance real-time control applications with safety-
critical requirements.
Table 1-1. Device Information(1)
PART NUMBER
TMS570LS1115ZWT
TMS570LS1115PGE
PACKAGE
NFBGA (337)
LQFP (144)
BODY SIZE
16.0 mm × 16.0 mm
20.0 mm × 20.0 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.
Copyright © 2012–2015, Texas Instruments Incorporated
Device Overview
3
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TMS570LS1115
SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
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1.4 Functional Block Diagram
NOTE
The block diagram reflects the 337BGA package. Some pins are multiplexed or not available
in the 144QFP. For details, see the respective terminal functions tables in Section 4.3.
128kB RAM
with ECC
1MB
Flash
with
32K
32K
32K
32K
ECC
DMA
POM
HTU1
FTU
HTU2
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
Peripheral Central Resource Bridge
CRC
Switched Central Resource
Switched Central Resource
nPORRST
EMIF_nWAIT
EMIF_CLK
SYS
nRST
ECLK
eQEPxA
IOMM
PMM
64 KB Flash
EMIF_CKE
eQEP
1,2
eQEPxB
eQEPxS
eQEPxI
nERROR
ESM
for EEPROM
Emulation
with ECC
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[12:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
DCAN1
eCAP
1..6
EMIF
eCAP[6:1]
DCAN2
DCAN3
VIM
CAN3_RX
nTZ[3:1]
SYNCO
SYNCI
CAN3_TX
EMIF_nWE
ePWM
1..7
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
EMIF_nRAS
ePWMxA
ePWMxB
EMIF_nCAS
MibSPI1
SPI2
RTI
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
Color Legend for Power Domains
RAM
DCC1
Core/RAM
Core
SPI2_nCS[1:0]
SPI2_nENA
always on
# 1
# 2
# 3
# 4
# 5
# 1
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
MibSPI3
SPI4
DCC2
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
FlexRay
N2HET1 N2HET2 GIO
I2C
MibADC1
MibADC2
MIBSPI5_CLK
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MibSPI5
MIBSPI5_nENA
LIN_RX
LIN_TX
LIN
SCI
SCI_RX
SCI_TX
Figure 1-1. Functional Block Diagram
4
Device Overview
Copyright © 2012–2015, Texas Instruments Incorporated
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TMS570LS1115
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SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
Table of Contents
Device Overview ......................................... 1
1
6.10 Flash Memory ....................................... 77
6.11 Tightly Coupled RAM Interface Module ............. 80
6.12 Parity Protection for Accesses to Peripheral RAMs 80
6.13 On-Chip SRAM Initialization and Testing ........... 82
6.14 External Memory Interface (EMIF) .................. 84
6.15 Vectored Interrupt Manager ......................... 92
6.16 DMA Controller ...................................... 96
6.17 Real Time Interrupt Module ......................... 98
6.18 Error Signaling Module............................. 100
6.19 Reset / Abort / Error Sources...................... 104
6.20 Digital Windowed Watchdog....................... 107
6.21 Debug Subsystem ................................. 108
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 Description............................................ 2
1.4 Functional Block Diagram ............................ 4
Revision History ......................................... 6
Device Comparison ..................................... 8
Terminal Configuration and Functions ............. 9
4.1 PGE QFP Package Pinout (144-Pin)................. 9
2
3
4
4.2
ZWT BGA Package Ball-Map (337 Ball Grid Array) 10
4.3 Terminal Functions ................................. 11
5
Specifications .......................................... 42
5.1
Absolute Maximum Ratings Over Operating Free-
7
Peripheral Information and Electrical
Air Temperature Range ............................ 42
5.2 ESD Ratings ........................................ 42
5.3 Power-On Hours (POH)............................. 42
Specifications ......................................... 113
7.1
Enhanced Translator PWM Modules (ePWM)..... 113
7.2 Enhanced Capture Modules (eCAP)............... 118
7.3
5.4
Device Recommended Operating Conditions....... 43
Switching Characteristics Over Recommended
Enhanced Quadrature Encoder (eQEP) ........... 120
Multibuffered 12bit Analog-to-Digital Converter.... 121
5.5
7.4
Operating Conditions for Clock Domains ........... 44
7.5 General-Purpose Input/Output..................... 133
7.6 Enhanced High-End Timer (N2HET) .............. 134
7.7 FlexRay Interface .................................. 138
7.8 Controller Area Network (DCAN) .................. 140
5.6 Wait States Required ............................... 44
5.7
Power Consumption Over Recommended
Operating Conditions................................ 45
Input/Output Electrical Characteristics Over
5.8
7.9
Local Interconnect Network Interface (LIN)........ 141
Recommended Operating Conditions............... 46
7.10 Serial Communication Interface (SCI) ............. 142
5.9 Thermal Resistance Characteristics ................ 46
5.10 Output Buffer Drive Strengths ...................... 47
5.11 Input Timings........................................ 48
5.12 Output Timings...................................... 49
5.13 Low-EMI Output Buffers ............................ 51
7.11 Inter-Integrated Circuit (I2C) ....................... 143
7.12 Multibuffered / Standard Serial Peripheral
Interface............................................ 146
8
Device and Documentation Support.............. 158
8.1
Device and Development-Support Tool
6
System Information and Electrical
Specifications ........................................... 52
Nomenclature ...................................... 158
8.2 Documentation Support............................ 160
8.3 Trademarks ........................................ 160
8.4 Electrostatic Discharge Caution ................... 160
8.5 Glossary............................................ 160
8.6 Device Identification................................ 161
8.7 Module Certifications............................... 163
6.1 Device Power Domains ............................. 52
6.2 Voltage Monitor Characteristics ..................... 52
6.3
Power Sequencing and Power On Reset ........... 54
6.4 Warm Reset (nRST)................................. 56
6.5 ARM Cortex-R4F CPU Information ................. 57
6.6 Clocks ............................................... 60
6.7 Clock Monitoring .................................... 68
6.8 Glitch Filters......................................... 70
6.9 Device Memory Map ................................ 71
9
Mechanical Packaging and Orderable
Information............................................. 170
9.1 Packaging Information ............................. 170
Copyright © 2012–2015, Texas Instruments Incorporated
Table of Contents
5
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SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
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2 Revision History
This data manual revision history highlights the technical changes made to the SPNS189A device-specific
data manual addendum to make it an SPNS189B revision.
Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the
TMS570LS1115 devices, which are now in the production data (PD) stage of development have been
incorporated.
Changes from September 1, 2013 to February 28, 2015 (from A Revision (September 2013) to B Revision)
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Updated/Changed section title to "Device Overview" ........................................................................... 1
Updated/changed the N2HET feature ............................................................................................. 1
Added Table 1-1, Device Information .............................................................................................. 3
Added Section 3, Device Comparison ............................................................................................. 8
Updated/Changed section title to "Terminal Configuration and Functions" ................................................... 9
Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)) Updated/Changed N2HET1 time input capture or
output compare pin description.................................................................................................... 13
Table 4-2 Updated/Changed N2HET2 time input capture or output compare pin description ............................ 14
Table 4-5Updated/Changed the EPWM1SYNCI Signal Type from "Output" to "Input" .................................... 15
Table 4-5Updated/Changed the EPWM1SYNCI pin description from "Output" to "Input"................................. 15
Table 4-16 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin description........................ 21
Table 4-22 (ZWT Enhanced High-End Timer Modules (N2HET)) Updated/Changed N2HET1 time input capture
or output compare pin description ................................................................................................ 25
Table 4-22 Updated/Changed N2HET2 time input capture or output compare pin description .......................... 26
Updated/Changed the EPWM1SYNCI pin description from "Output" to "Input" ............................................ 28
Table 4-34 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function............................... 33
Table 4-37 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin description ....................... 36
Updated/Changed section title to "Specifications" ............................................................................. 42
Moved Storage temperature range, Tstg back to Section 5.1, Absolute Maximum Ratings Over Operating Free-
Air Temperature Range ............................................................................................................ 42
Added Section 5.2, Handling Ratings (Automotive) ............................................................................ 42
Added Section 5.3, Power-On-Hours (POH) .................................................................................... 42
Moved Thermal Data section here. ............................................................................................... 46
Section 5.9 (Thermal Resistance Characteristics): Updated/Changed title from "Thermal Data" to "Thermal
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Resistance Characteristics"........................................................................................................ 46
Added ΘJA test conditions and added ΨJT for PGE package.................................................................. 46
Added ΘJA test conditions and added ΨJT for ZWT package.................................................................. 47
Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin .................................................. 48
Changed the number of cycles of tv(RST) from 2252 to 2256................................................................... 56
Figure 6-7 (Device Clock Domains): Added VCLK4 (to ePWM, eQEP, eCAP)............................................. 66
Section 6.9.1 (Memory Map Diagram): Updated/Changed memory map (Figure 6-10 .................................... 71
Table 6-22 (Flash Memory Banks and Sectors): Updated/Changed the BANK 0 Sector No. to support 1MB Flash.. 77
Table 6-22: Added associated footnotes ........................................................................................ 77
Figure 6-11 (TCRAM Block Diagram): Updated/Changed figure ............................................................. 80
Added table notes identifying address ranges of ESRAM PBIST groups ................................................... 82
Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to "0xFF45FFFF" in Table 6-26, Memory
Initialization .......................................................................................................................... 83
Updated EMIF Timings ............................................................................................................ 84
Changed maximum addressable size of asynchronous memories from 16MB to 32KB .................................. 84
Updated/Changed the EMIF address bus signals from "EMIF_ADDR[21:0]" to "EMIF_ADDR[12:0]" for all figures
in Section 6.14.2, Electrical and Timing Specifications ........................................................................ 84
Updated/Changed EMIF address from "EMIF_ADDR[21:0]" to "EMIF_ADDR[12:0]"...................................... 84
Changed EMIF tsu(EMDV-EMOEH) from 30nS to 9nS................................................................................ 86
Changed EMIF th(EMOEH-EMDIV) from 0.5nS to 0nS ............................................................................... 86
Changed EMIF tsu(EMOEL-EMWAIT) from 4E+30nS to 4E+9nS .................................................................... 86
Changed EMIF tsu(EMWEL-EMWAIT) from 4E+30nS to 4E+14nS................................................................... 86
Changed EMIF tsu(EMCEL-EMOEL) from (RS)*E-5 to (RS)*E-6..................................................................... 87
Changed EMIF tsu(EMCEL-EMOEL) from -5 to -6 ..................................................................................... 87
Changed EMIF th(EMOEH-EMCEH) from (RH)*E -4 to (RH)*E -3 ................................................................... 87
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Revision History
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS570LS1115
TMS570LS1115
www.ti.com
SPNS189B –OCTOBER 2012–REVISED FEBRUARY 2015
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Changed EMIF th(EMOEH-EMCEH) from (RH)*E +4 to (RH)*E +5.................................................................. 87
Changed EMIF th(EMOEH-EMCEH) from -4 to -3...................................................................................... 87
Changed EMIF th(EMOEH-EMCEH) from +4 to +5 .................................................................................... 87
Changed EMIF tsu(EMBAV-EMOEL) from (RS)*E-5 to (RS)*E-6..................................................................... 87
Changed EMIF th(EMOEH-EMBAIV) from (RS)*E-4 to (RS)*E-3..................................................................... 87
Changed EMIF tsu(EMAV-EMOEL) from (RS)*E-5 to (RS)*E-6...................................................................... 87
Changed EMIF th(EMOEH-EMAIV) from (RS)*E-4 to (RS)*E-3...................................................................... 87
Changed EMIF td(EMWAITH-EMOEH) from 3E-3 to 3E+9 ............................................................................ 87
Changed EMIF td(EMWAITH-EMOEH) from 4E+30 to 4E+20......................................................................... 87
Changed EMIF tsu(EMDQMV-EMOEL) from (RS)*E-5 to (RS)*E-6................................................................... 87
Changed EMIF th(EMOEH-EMDQMIV) from (RS)*E-4 to (RS)*E-3................................................................... 87
Changed EMIF tsu(EMCEL-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................. 88
Changed EMIF tsu(EMCEL-EMWEL) from -4 to -3 ..................................................................................... 88
Changed EMIF th(EMWEH-EMCEH) from (WS)*E -4 to (WS)*E -3.................................................................. 88
Changed EMIF th(EMWEH-EMCEH) from -4 to -3 ..................................................................................... 88
Changed EMIF tsu(EMDQMV-EMWEL) from (WS)*E -4 to (WS)*E -3................................................................ 88
Changed EMIF th(EMWEH-EMDQMIV) from (WS)*E -4 to (WS)*E -3................................................................ 88
Changed EMIF tsu(EMBAV-EMWEL) from (WS)*E -4 to (WS)*E -3 ................................................................. 88
Changed EMIF th(EMWEH-EMBAIV) from (WS)*E -4 to (WS)*E -3 ................................................................. 88
Changed EMIF tsu(EMAV-EMWEL) from (WS)*E -4 to (WS)*E -3................................................................... 88
Changed EMIF th(EMWEH-EMAIV) from (WS)*E -4 to (WS)*E -3................................................................... 88
Changed EMIF td(EMWAITH-EMWEH) from 3E-4 to 3E+11........................................................................... 88
Changed EMIF td(EMWAITH-EMWEH) from 4E+30 to 4E+24 ........................................................................ 88
Changed EMIF tsu(EMDV-EMWEL) from (WS)*E -4 to (WS)*E -3 .................................................................. 88
Changed EMIF th(EMWEH-EMDIV) from (WS)*E -4 to (WS)*E -3................................................................... 88
Changed EMIF tsu(EMDQMV-EMWEL) from (WS)*E -4 to (WS)*E -3................................................................ 88
Changed EMIF th(EMWEH-EMDQMIV) from (WS)*E -4 to (WS)*E -3................................................................ 88
Added JTAG ID for revision C silicon .......................................................................................... 108
Revised description of ePWM Trip Zone Timing Requirement tw(TZ) ........................................................ 117
Corrected SPI table note describing Master mode, phase = 0 condition .................................................. 150
Added Device Identification code for revision C silicon ...................................................................... 161
Changed address of die identification registers ............................................................................... 161
Updated/Changed the section title to "Mechanical Packaging and Orderable Information" ............................. 170
Section 9.1 (Packaging Information): Updated/Changed paragraph........................................................ 170
Copyright © 2012–2015, Texas Instruments Incorporated
Revision History
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3 Device Comparison
Table 3-1 lists the features of the TMS570LS1115 devices.
Table 3-1. TMS570LS1115 Device Comparison(1)(2)
FEATURES
DEVICES
TMS570LS3137ZWT(3) TMS570LS1227ZWT(3) TMS570LS1115ZWT TMS570LS1115PGE TMS570LS0714PGE
Generic Part
Number
TMS570LS0714PZ
TMS570LS0432PZ
Package
337 BGA
337 BGA
337 BGA
144 QFP
144 QFP
100 QFP
100 QFP
CPU
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4
Frequency (MHz)
Flash (KB)
RAM (KB)
180
3072
256
180
1280
192
180
1024
128
160
1024
128
160
768
128
100
768
128
80
384
32
Data Flash
[EEPROM] (KB)
64
64
64
64
64
64
16
EMAC
FlexRay
CAN
10/100
2-ch
3
10/100
2-ch
3
–
2-ch
3
–
2-ch
3
–
–
3
–
–
2
–
–
2
MibADC
12-bit (Ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (24ch)
2 (16ch)
1 (16ch)
N2HET (Ch)
ePWM Channels
eCAP Channels
eQEP Channels
MibSPI (CS)
SPI (CS)
2 (44)
2 (44)
2 (44)
2 (40)
2 (40)
2 (21)
1 (19)
–
14
14
14
14
8
–
–
6
6
6
6
4
0
–
2
2
2
3 (5 + 6 + 1)
1 (1)
2
3 (5 + 6 + 4)
1 (1)
1
2 (5 + 1)
1 (1)
1
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
3 (6 + 6 + 4)
2 (2 + 1)
2 (1 with LIN)
1
1 (4)
2
SCI (LIN)
2 (1 with LIN)
1
2 (1 with LIN)
1
1 (with LIN)
–
1 (with LIN)
–
I2C
144 (with 16 interrupt 101 (with 16 interrupt 101 (with 16 interrupt
58 (with 4 interrupt
capable)
64 (with 10 interrupt
capable)
45 (with 9 interrupt
capable)
45 (with 8 interrupt
capable)
GPIO (INT)(4)
capable)
16-bit data
32-bit
capable)
capable)
EMIF
16-bit data
16-bit data
–
–
–
–
–
–
–
–
–
–
–
–
ETM (Trace)
RTP/DMM
–
–
–
–
YES
Operating
Temperature
-40ºC to 125ºC
-40ºC to 125ºC
-40ºC to 125ºC
-40ºC to 125ºC
-40ºC to 125ºC
-40ºC to 125ºC
-40ºC to 125ºC
Core Supply (V)
I/O Supply (V)
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
1.14 V – 1.32 V
3.0 V – 3.6 V
(1) For additional device variants, see www.ti.com/tms570
(2) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the
same time.
(3) Superset device.
(4) Total number of pins that can be used as general purpose input or output when not used as part of a peripheral.
8
Device Comparison
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4 Terminal Configuration and Functions
4.1 PGE QFP Package Pinout (144-Pin)
AD1IN[10] / AD2IN[10]
AD1IN[1]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
nTRST
TDI
TDO
TCK
RTCK
VCC
VSS
nRST
AD1IN[9] / AD2IN[9]
VCCAD
VSSAD
ADREFLO
ADREFHI
AD1IN[21] / AD2IN[5]
AD1IN[20] / AD2IN[4]
AD1IN[19] / AD2IN[3]
AD1IN[18] / AD2IN[2]
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
AD1IN[7]
AD1IN[0]
AD1IN[17] / AD2IN[1]
AD1IN[16] / AD2IN[0]
VCC
VCC
N2HET1[12]
N2HET1[14]
FRAYRX1
N2HET1[30]
CAN2TX
VSS
MIBSPI3NCS[0]
MIBSPI3NENA
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
VSS
VCC
VCC
VSS
nPORRST
VCC
VSS
VSS
VCCIO
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
FRAYTX1
VCCP
VSS
VCCIO
VCC
VSS
N2HET1[16]
N2HET1[18]
N2HET1[20]
FRAYTXEN1
VCC
N2HET1[15]
MIBSPI1NCS[2]
N2HET1[13]
N2HET1[6]
MIBSPI3NCS[1]
VSS
Figure 4-1. PGE QFP Package Pinout (144-Pin)
Note: Pins can have multiplexed functions. Only the default function is depicted in above diagram.
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Terminal Configuration and Functions
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4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
AD1IN[15] AD1IN[22]
AD1IN[11]
/
AD2IN[11]
N2HET1 MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
CLK
AD1IN
[6]
19
18
17
16
15
14
13
12
11
VSS
VSS
TMS
NC
CAN3RX AD1EVT
/
AD2IN[15] AD2IN[6]
/
VSSAD
VSSAD 19
[10]
NCS[0]
SIMO
NENA
SIMO[0]
[28]
AD1IN[8] AD1IN[14] AD1IN[13]
N2HET1 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1
NENA
AD1IN
[4]
AD1IN
[2]
VSS
TDI
TCK
TDO
NC
NC
NC
NC
NC
NC
NC
nTRST
NC
CAN3TX
NC
/
AD2IN[8] AD2IN[14] AD2IN[13]
/
/
VSSAD 18
AD1IN[9]
[8]
CLK
SOMI
SOMI[0]
[0]
AD1IN[10]
/
AD2IN[10]
EMIF_
nWE
MIBSPI5
SOMI[1]
MIBSPI5 MIBSPI5 N2HET1
[31]
EMIF_
nCS[3]
EMIF_
nCS[2]
EMIF_
nCS[4]
EMIF_
nCS[0]
AD1IN
[5]
AD1IN
[3]
AD1IN
[1]
nRST
NC
NC
NC
/
AD2IN[9]
17
SIMO[3] SIMO[2]
AD1IN[23] AD1IN[12] AD1IN[19]
/
AD2IN[7] AD2IN[12] AD2IN[3]
FRAY
TXEN1
EMIF_
BA[1]
MIBSPI5
SIMO[1]
MIBSPI5 MIBSPI5
SOMI[3] SOMI[2]
RTCK
NC
NC
NC
NC
NC
NC
/
/
ADREFLO VSSAD 16
ADREFHI VCCAD 15
AD1IN[21] AD1IN[20]
FRAY
RX1
FRAY
TX1
EMIF_
DATA[0]
EMIF_
DATA[1]
EMIF_
DATA[2]
EMIF_
DATA[3]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
/
/
AD2IN[5] AD2IN[4]
AD1IN[18]
/
AD2IN[2]
N2HET1
[26]
AD1IN
[7]
AD1IN
[0]
nERROR
NC
VCCIO
VCCIO
VCCIO
VCCIO
VCC
VCCIO
VCCIO
VCC
VCC
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCPLL
VCC
NC
NC
14
13
12
11
AD1IN[17] AD1IN[16]
/
AD2IN[1] AD2IN[0]
N2HET1 N2HET1
[19]
EMIF_BA[0]
EMIF_nOE
/
NC
NC
NC
[17]
N2HET1
[4]
MIBSPI5
NCS[3]
ECLK
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
NC
NC
NC
NC
N2HET1 N2HET1
[14] [30]
EMIF_
nDQM[1]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
EMIF_
ADDR[12]
MIBSPI3
NCS[0]
EMIF_
nDQM[0]
10 CAN1TX CAN1RX
NC
GIOB[3] 10
N2HET1
[27]
FRAY EMIF_
TXEN2 ADDR[11]
EXTCLKI
N2
MIBSPI3 MIBSPI3
NENA
EMIF_
ADDR[5]
9
8
7
6
5
4
3
2
1
VCC
VCCIO
VCCIO
VCCIO
VCCIO
NC
9
8
7
6
5
4
3
2
1
CLK
FRAY
RX2
FRAY
TX2
EMIF_
ADDR[10]
MIBSPI3 MIBSPI3
SIMO
EMIF_
ADDR[4]
EMIF_
DATA[15]
VCCP
VCCIO
VCCIO
NC
SOMI
EMIF_
ADDR[9]
N2HET1
[9]
EMIF_
ADDR[3]
EMIF_
DATA[14]
nPORRST
LINRX
LINTX
NC
MIBSPI5
NCS[1]
EMIF_
ADDR[8]
N2HET1 MIBSPI5
[5] NCS[2]
EMIF_
ADDR[2]
EMIF_
DATA[13]
GIOA[4]
NC
VCCIO
VCCIO
FLTP2
VCCIO
FLTP1
VCC
VCC
VCCIO
VCCIO
NC
EMIF_ EMIF_
ADDR[7] ADDR[1]
MIBSPI3 N2HET1
[2]
EMIF_
DATA[4]
EMIF_
DATA[5]
EMIF_
DATA[6]
EMIF_
DATA[7]
EMIF_
DATA[8]
EMIF_
DATA[9]
EMIF_
DATA[10]
EMIF_
DATA[11]
EMIF_
DATA[12]
GIOA[0] GIOA[5]
N2HET1 N2HET1
NC
NCS[1]
EMIF_ EMIF_
ADDR[6] ADDR[0]
N2HET1 N2HET1
[21]
EMIF_
nCAS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
[16]
[12]
[23]
N2HET1 N2HET1 MIBSPI3
NCS[3]
SPI2
NENA
N2HET1 MIBSPI1 MIBSPI1
[11] NCS[1] NCS[2]
MIBSPI1
NCS[3]
EMIF_
CLK
EMIF_
CKE
N2HET1
[25]
SPI2
NCS[0]
EMIF_
nWAIT
EMIF_
nRAS
N2HET1
[6]
GIOA[6]
NC
NC
[29]
[22]
MIBSPI3
NCS[2]
SPI2
SOMI
KELVIN_
GND
N2HET1 N2HET1 MIBSPI1
[20]
N2HET1
[1]
VSS
GIOA[1]
SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1]
GIOB[0]
TEST
VSS
[13]
NCS[0]
SPI2
SIMO
N2HET1
[18]
N2HET1 N2HET1
[24]
N2HET1 N2HET1
[7]
VSS
A
VSS
B
GIOA[2]
C
GIOA[3] GIOB[7] GIOB[4] CAN2RX
OSCIN
K
OSCOUT GIOA[7]
NC
R
VSS
V
VSS
W
[15]
[3]
D
E
F
G
H
J
L
M
N
P
T
U
Figure 4-2. ZWT Package Pinout. Top View
Note: Balls can have multiplexed functions. Only the default function is depicted in above diagram.
10
Terminal Configuration and Functions
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4.3 Terminal Functions
Section 4.3.1 and Section 4.3.2 identify the external signal names, the associated pin/ball numbers along
with the mechanical package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether
the pin/ball has any internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a
functional pin/ball description. The first signal name listed is the primary function for that terminal. The
signal name in Bold is the function being described. Refer to the I/O Multiplexing Module (IOMM) chapter
of the TMS570LS12x/11x Technical Reference Manual (SPNU515).
NOTE
In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to
the terminal while nPORRST is low and immediately after nPORRST goes High. The default
pull direction may change when software configures the pin for an alternate function. The
"Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given
terminal by the IOMM control registers.
All I/O signals except nRST are configured as inputs while nPORRST is low and
immediately after nPORRST goes High. While nPORRST is low, the input buffers
are disabled, and the output buffers are disabled with the default pulls enabled.
All output-only signals have the output buffer disabled and the default pull enabled
while nPORRST is low, and are configured as outputs with the pulls disabled
immediately after nPORRST goes High.
4.3.1 PGE Package
4.3.1.1 Multibuffered Analog-to-Digital Converters (MibADC)
Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
ADREFHI(1)
66
Power
N/A
None
ADC high reference
supply
ADREFLO(1)
VCCAD(1)
VSSAD(1)
AD1EVT
67
69
68
86
Power
Power
Ground
I/O
ADC low reference supply
Operating supply for ADC
Pull Down Programmable, ADC1 event trigger input,
20 µA or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
55
I/O
Pull Up
Programmable, ADC2 event trigger input,
EQEP1I/N2HET2_PIN_nDIS
20 µA
or GPIO
AD1IN[0]
AD1IN[1]
AD1IN[2]
AD1IN[3]
AD1IN[4]
AD1IN[5]
AD1IN[6]
AD1IN[7]
60
71
73
74
76
78
80
61
Input
N/A
None
ADC1 analog input
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
Terminal Configuration and Functions
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Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2) (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
AD1IN[8] / AD2IN[8]
AD1IN[9] / AD2IN[9]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[1]
AD1IN[18] / AD2IN[2]
AD1IN[19] / AD2IN[3]
AD1IN[20] / AD2IN[4]
AD1IN[21] / AD2IN[5]
AD1IN[22] / AD2IN[6]
AD1IN[23] / AD2IN[7]
83
70
72
75
77
79
82
85
58
59
62
63
64
65
81
84
51
Input
N/A
None
ADC1/ADC2 shared
analog inputs
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
Output
Output
Output
Pull Up
Pull Up
Pull Up
None
None
None
AWM1 external analog
mux enable
52
53
AWM1 external analog
mux select line0
AWM1 external analog
mux select line0
12
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4.3.1.2 Enhanced High-End Timer Modules (N2HET)
Table 4-2. PGE Enhanced High-End Timer Modules (N2HET)
Terminal
Signal
Type
Reset Pull
State
Pull Type
Description
Signal Name
144
PGE
N2HET1[0]/SPI4CLK/EPWM2B
25
23
I/O
Pull Down
Programmable,
20 µA
N2HET1
capture
compare, or GIO.
time
or
input
output
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[2]/SPI4SIMO[0]/EPWM3A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
N2HET1[4]/EPWM4B
30
Each terminal has
suppression filter with a
programmable duration.
a
24
36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
N2HET1[6]/SCIRX/EPWM5A
N2HET1[7]/N2HET2[14]/EPWM7B
N2HET1[8]/MIBSPI1SIMO[1]
31
38
33
106
35
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[10]/nTZ3
118
6
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO
N2HET1[12]
124
39
N2HET1[13]/SCITX/EPWM5B
N2HET1[14]
125
41
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S
N2HET1[18]/EPWM6A
139
130
140
40
Pull Up
Pull Down
Pull Up
MIBSPI1NCS[2]/N2HET1[19]
N2HET1[20]/EPWM6B
141
15
Pull Down
N2HET1[22]
MIBSPI1NENA/N2HET1[23]/ECAP4
N2HET1[24]/MIBSPI1NCS[5]
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
N2HET1[26]
96
Pull Up
Pull Down
Pull Up
91
37
92
Pull Down
Pull Up
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
N2HET1[28]
4
107
3
Pull Down
Pull Up
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
N2HET1[30]/EQEP2S
127
54
Pull Down
Pull Up
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
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Table 4-2. PGE Enhanced High-End Timer Modules (N2HET) (continued)
Terminal
Signal
Type
Reset Pull
State
Pull Type
Description
Signal Name
144
PGE
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
14
I/O
I/O
Pull Down
Pull Down
Programmable, Disable selected PWM
20 µA(1)
outputs
GIOA[2]/N2HET2[0]/ EQEP2I
9
Programmable,
20 µA
N2HET2
capture
time
or
input
output
GIOA[6]/N2HET2[4]/EPWM1B
16
22
23
24
31
33
35
6
compare, or GPIO
GIOA[7]/N2HET2[6]/EPWM2A
Each terminal has
suppression filter with a
programmable duration.
a
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
N2HET1[7]/N2HET2[14]/EPWM7B
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ EPWM1SYNCO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
55
I/O
Pull Up
Programmable, Disable selected PWM
20 µA(1)
outputs
(1) The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is
controlled by the function which is selected by the output mux control for this terminal.
4.3.1.3 Enhanced Capture Modules (eCAP)
Table 4-3. PGE Enhanced Capture Modules (eCAP)(1)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
41
51
I/O
Pull Down
Pull Up
Fixed 20 µA
Pull Up
Enhanced Capture
Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
MIBSPI1NENA/N2HET1[23]/ECAP4
Enhanced Capture
Module 2 I/O
52
Enhanced Capture
Module 3 I/O
96
Enhanced Capture
Module 4 I/O
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
97
Enhanced Capture
Module 5 I/O
105
Enhanced Capture
Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
14
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4.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
Table 4-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
53
54
55
Input
Input
I/O
Pull Up
Fixed 20 µA
Pull Up
Enhanced QEP1 Input A
Enhanced QEP1 Input B
Enhanced QEP1 Index
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
GIOA[2]/N2HET2[0]/ EQEP2I
130
23
24
9
I/O
Input
Input
I/O
Enhanced QEP1 Strobe
Enhanced QEP2 Input A
Enhanced QEP2 Input B
Enhanced QEP2 Index
Enhanced QEP2 Strobe
Pull Down
N2HET1[30]/EQEP2S
127
I/O
(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
4.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)
Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM)
Terminal
Signal Reset Pull
Type State
Pull Type
Description
Signal Name
144
PGE
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
GIOA[6]/N2HET2[4]/EPWM1B
14
16
6
Output Pull Down
None
Enhanced PWM1 Output
A
Enhanced PWM1 Output
B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
GIOA[7]/N2HET2[6]/EPWM2A
External ePWM Sync
Pulse Output
139
22
25
30
31
32
36
38
39
140
141
35
33
Input
Fixed 20 µA
Pull Up
External ePWM Sync
Pulse Input
Output
None
Enhanced PWM2 Output
A
N2HET1[0]/SPI4CLK/EPWM2B
N2HET1[2]/SPI4SIMO[0]/EPWM3A
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
MIBSPI5NCS[0]/EPWM4A
Enhanced PWM2 Output
B
Enhanced PWM3 Output
A
Enhanced PWM3 Output
B
Pull Up
Enhanced PWM4 Output
A
N2HET1[4]/EPWM4B
Pull Down
Enhanced PWM4 Output
B
N2HET1[6]/SCIRX/EPWM5A
Enhanced PWM5 Output
A
N2HET1[13]/SCITX/EPWM5B
Enhanced PWM5 Output
B
N2HET1[18]/EPWM6A
Enhanced PWM6 Output
A
N2HET1[20]/EPWM6B
Enhanced PWM6 Output
B
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[7]/N2HET2[14]/EPWM7B
Enhanced PWM7 Output
A
Enhanced PWM7 Output
B
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15
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Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM) (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
N2HET1[10]/nTZ3
3
4
Input
Pull Up
Fixed 20 µA
Pull Up
Trip Zone Inputs 1, 2 and
3. These signals are
either connected
118
Pull Down
asynchronously to the
ePWMx trip zone inputs,
or double-synchronized
with VCLK4, or double-
synchronized and then
filtered with a 6-cycle
VCLK4-based counter
before connecting to the
ePWMx trip zone inputs.
4.3.1.6 General-Purpose Input / Output (GPIO)
Table 4-6. PGE General-Purpose Input / Output (GPIO)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
GIOA[2]/N2HET2[0]/EQEP2I
9
14
I/O
Pull Down Programmable, General-purpose I/O.
20 µA
All GPIO terminals are
capable of generating
interrupts to the CPU on
rising / falling / both
edges.
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
GIOA[6]/N2HET2[4]/EPWM1B
16
GIOA[7]/N2HET2[6]/EPWM2A
22
55(1)
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
Pull Up
EQEP1I/N2HET2_PIN_nDIS
(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt
whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable using the
GIO module control registers.
4.3.1.7 FlexRay Interface Controller (FlexRay)
Table 4-7. FlexRay Interface Controller (FlexRay)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
FRAYRX1
FRAYTX1
126
133
142
2
Input
Output
Output
Input
Pull Up
N/A
Fixed 100 µA
Pull Up
FlexRay data receive
(channel 1)
None
FlexRay data transmit
(channel 1)
FRAYTXEN1
FRAYRX2
FRAYTX2
FlexRay transmit enable
(channel 1)
Pull Up
N/A
Fixed 100 µA
Pull Up
FlexRay data receive
(channel 2)
1
Output
Output
None
FlexRay data transmit
(channel 2)
FRAYTXEN2
5
FlexRay transmit enable
(channel 2)
16
Terminal Configuration and Functions
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4.3.1.8 Controller Area Network Controllers (DCAN)
Table 4-8. PGE Controller Area Network Controllers (DCAN)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
90
89
I/O
Pull Up
Programmable, CAN1 receive, or GPIO
20 µA
CAN1 transmit, or GPIO
129
128
12
CAN2 receive, or GPIO
CAN2 transmit, or GPIO
CAN3 receive, or GPIO
CAN3 transmit, or GPIO
13
4.3.1.9 Local Interconnect Network Interface Module (LIN)
Table 4-9. PGE Local Interconnect Network Interface Module (LIN)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
LINRX
LINTX
131
132
I/O
Pull Up
Programmable, LIN receive, or GPIO
20 µA
LIN transmit, or GPIO
4.3.1.10 Standard Serial Communication Interface (SCI)
Table 4-10. PGE Standard Serial Communication Interface (SCI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
N2HET1[6]/SCIRX/EPWM5A
N2HET1[13]/SCITX/EPWM5B
38
39
I/O
Pull Down Programmable, SCI receive, or GPIO
20 µA
SCI transmit, or GPIO
4.3.1.11 Inter-Integrated Circuit Interface Module (I2C)
Table 4-11. PGE Inter-Integrated Circuit Interface Module (I2C)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
4
3
I/O
Pull Up
Programmable, I2C serial data, or GPIO
20 µA
I2C serial clock, or GPIO
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4.3.1.12 Standard Serial Peripheral Interface (SPI)
Table 4-12. PGE Standard Serial Peripheral Interface (SPI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
N2HET1[0]/SPI4CLK/EPWM2B
25
24
23
30
I/O
Pull Down Programmable, SPI4 clock, or GPIO
20 µA
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[2]/SPI4SIMO[0]/EPWM3A
SPI4 chip select, or GPIO
SPI4 enable, or GPIO
SPI4 slave-input master-
output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
31
SPI4 slave-output master-
input, or GPIO
4.3.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-13. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
MIBSPI1CLK
95
105
130
40
I/O
Pull Up
Programmable, MibSPI1 clock, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S
MIBSPI1NCS[2]/N2HET1[19]
MibSPI1 chip select, or
GPIO
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
N2HET1[24]/MIBSPI1NCS[5]
41
Pull Down Programmable, MibSPI1 chip select, or
20 µA GPIO
91
MIBSPI1NENA/N2HET1[23]/ECAP4
MIBSPI1SIMO[0]
96
Pull Up
Programmable, MibSPI1 enable, or GPIO
20 µA
93
MibSPI1 slave-in master-
out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]
106
Pull Down Programmable, MibSPI1 slave-in master-
20 µA out, or GPIO
MIBSPI1SOMI[0]
94
Pull Up
Programmable, MibSPI1 slave-out master-
20 µA in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
105
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
53
55
I/O
Pull Up
Programmable, MibSPI3 clock, or GPIO
20 µA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
MibSPI3 chip select, or
EQEP1I/N2HET2_PIN_nDIS
GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
37
4
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
3
6
Pull Down Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
54
Pull Up
Programmable, MibSPI3 chip select, or
20 µA
GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
54
52
MibSPI3 enable, or GPIO
MibSPI3 slave-in master-
out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
51
MibSPI3 slave-out master-
in, or GPIO
18
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Table 4-13. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI) (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
MIBSPI5CLK
100
32
I/O
Pull Up
Programmable, MibSPI5 clock, or GPIO
20 µA
MIBSPI5NCS[0]/EPWM4A
MibSPI5 chip select, or
GPIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
97
99
MibSPI5 enable, or GPIO
MibSPI5 slave-in master-
out, or GPIO
MIBSPI5SOMI[0]
98
97
99
MibSPI5 slave-out master-
in, or GPIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
MibSPI5 slave-out master-
in, or GPIO
MibSPI5 slave-out master-
in, or GPIO
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4.3.1.14 System Module Interface
Table 4-14. PGE System Module Interface
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
nPORRST
46
Input
Pull Down
Fixed 100 µA
Pull Down
Power-on reset, cold reset
External power supply
monitor circuitry must
drive nPORRST low when
any of the supplies to the
microcontroller fall out of
the specified range. This
terminal has a glitch filter.
See Section 6.8.
nRST
116
I/O
Pull Up
Fixed 100 µA
Pull Up
System reset, warm reset,
bidirectional.
The internal circuitry
indicates any reset
condition by driving nRST
low.
The external circuitry can
assert a system reset by
driving nRST low. To
ensure that an external
reset is not arbitrarily
generated, TI
recommends that an
external pull-up resistor is
connected to this terminal.
This terminal has a glitch
filter. See Section 6.8.
nERROR
117
I/O
Pull Down
Fixed 20 µA
Pull Down
ESM Error Signal
Indicates error of high
severity. See
Section 6.18.
4.3.1.15 Clock Inputs and Outputs
Table 4-15. PGE Clock Inputs and Outputs
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
OSCIN
18
Input
N/A
None
From external
crystal/resonator, or
external clock input
KELVIN_GND
OSCOUT
19
20
Input
Kelvin ground for oscillator
Output
To external
crystal/resonator
ECLK
119
14
I/O
Pull Down Programmable, External prescaled clock
20 µA
output, or GPIO.
GIOA[5]/EXTCLKIN/EPWM1A /N2HET1_PIN_nDIS
Input
Pull Down
Fixed 20 µA
Pull Down
External clock input #1
20
Terminal Configuration and Functions
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4.3.1.16 Test and Debug Modules Interface
Table 4-16. PGE Test and Debug Modules Interface
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
TEST
34
Input
Pull Down
Fixed 100 µA
Pull Down
Test enable. This terminal
must be connected to
ground directly or via a
pull-down resistor.
nTRST
RTCK
TCK
109
113
112
Input
Output
Input
JTAG test hardware reset
JTAG return test clock
JTAG test clock
N/A
None
Pull Down
Fixed 100 µA
Pull Down
TDI
110
111
108
Input
Output
Input
Pull Up
Fixed 100 µA
Pull Up
JTAG test data in
JTAG test data out
JTAG test select
TDO
TMS
100 µA
Pull Down
None
Pull Up
Fixed 100 µA
Pull Up
4.3.1.17 Flash Supply and Test Pads
Table 4-17. PGE Flash Supply and Test Pads
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
VCCP
134
3.3V
Power
N/A
None
None
Flash pump supply
FLTP1
FLTP2
7
8
-
N/A-
Flash test pads. These
terminals are reserved for
TI use only. For proper
operation these terminals
must connect only to a
test pad or not be
connected at all [no
connect (NC)].
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4.3.1.18 Supply for Core Logic: 1.2V nominal
Table 4-18. PGE Supply for Core Logic: 1.2V nominal
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17
29
1.2V
Power
N/A
None
Core supply
45
48
49
57
87
101
114
123
137
143
4.3.1.19 Supply for I/O Cells: 3.3V nominal
Table 4-19. PGE Supply for I/O Cells: 3.3V nominal
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
10
26
3.3V
Power
N/A
None
Operating supply for I/Os
42
104
120
136
22
Terminal Configuration and Functions
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4.3.1.20 Ground Reference for All Supplies Except VCCAD
Table 4-20. PGE Ground Reference for All Supplies Except VCCAD
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
144
PGE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
11
21
Ground
N/A
None
Ground reference
27
28
43
44
47
50
56
88
102
103
115
121
122
135
138
144
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4.3.2 ZWT Package
4.3.2.1 Multibuffered Analog-to-Digital Converters (MibADC)
Table 4-21. ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
ADREFHI(1)
V15
Power
N/A
None
ADC high reference
supply
ADREFLO(1)
VCCAD(1)
VSSAD
V16
W15
V19
Power
Power
Ground
ADC low reference supply
Operating supply for ADC
ADC supply power
N/A
None
VSSAD
W16
W18
W19
N19
VSSAD
VSSAD
AD1EVT
I/O
I/O
Pull Down Programmable, ADC1 event trigger input,
20 µA or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
V10
Pull Up
Programmable, ADC2 event trigger input,
EQEP1I/N2HET2_PIN_nDIS
20 µA
or GPIO
AD1IN[0]
W14
V17
V18
T17
U18
R17
T19
V14
P18
W17
U17
U19
T16
T18
R18
P19
V13
U13
U14
U16
U15
T15
R19
R16
V8
Input
N/A
None
ADC1 analog input
AD1IN[1]
AD1IN[2]
AD1IN[3]
AD1IN[4]
AD1IN[5]
AD1IN[6]
AD1IN[7]
AD1IN[8] / AD2IN[8]
AD1IN[9] / AD2IN[9]
AD1IN[10] / AD2IN[10]
AD1IN[11] / AD2IN[11]
AD1IN[12] / AD2IN[12]
AD1IN[13] / AD2IN[13]
AD1IN[14] / AD2IN[14]
AD1IN[15] / AD2IN[15]
AD1IN[16] / AD2IN[0]
AD1IN[17] / AD2IN[1]
AD1IN[18] / AD2IN[2]
AD1IN[19] / AD2IN[3]
AD1IN[20] / AD2IN[4]
AD1IN[21] / AD2IN[5]
AD1IN[22] / AD2IN[6]
AD1IN[23] / AD2IN[7]
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
Input
N/A
None
ADC1/ADC2 shared
analog inputs
Output
Pull Up
None
AWM1 external analog
mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
W8
V9
AWM1 external analog
mux select line0
AWM1 external analog
mux select line0
(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
24
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4.3.2.2 Enhanced High-End Timer Modules (N2HET)
Table 4-22. ZWT Enhanced High-End Timer Modules (N2HET)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
N2HET1[0]/SPI4CLK/EPWM2B
K18
V2
I/O
Pull Down Programmable,
20 µA
N2HET1
capture
compare, or GIO.
time
or
input
output
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[2]/SPI4SIMO[0]/EPWM3A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
N2HET1[4]/EPWM4B
W5
U1
B12
V6
Each terminal has
suppression filter with
programmable duration.
a
a
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
N2HET1[6]/SCIRX/EPWM5A
N2HET1[7]/N2HET2[14]/EPWM7B
N2HET1[8]/MIBSPI1SIMO[1]
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[10]/nTZ3
W3
T1
E18
V7
D19
E3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
N2HET1[12]
B4
N2HET1[13]/SCITX/EPWM5B
N2HET1[14]
N2
A11
N1
A4
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
N2HET1[17]
A13
F3
MIBSPI1NCS[1]/N2HET1[17]/ EQEP1S
N2HET1[18]/EPWM6A
J1
N2HET1[19]
B13
G3
P2
MIBSPI1NCS[2]/N2HET1[19]
N2HET1[20]/EPWM6B
N2HET1[21]
H4
J3
MIBSPI1NCS[3]/N2HET1[21]
N2HET1[22]
B3
N2HET1[23]
J4
MIBSPI1NENA/N2HET1[23]/ECAP4
N2HET1[24]/MIBSPI1NCS[5]
N2HET1[25]
G19
P1
Pull Up
Pull Down
M3
V5
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
N2HET1[26]
A14
A9
N2HET1[27]
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
N2HET1[28]
B2
Pull Up
K19
A3
Pull Down
N2HET1[29]
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
C3
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Table 4-22. ZWT Enhanced High-End Timer Modules (N2HET) (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
N2HET1[30]/EQEP2S
B11
J17
W9
B5
I/O
Pull Down Programmable,
20 µA
N2HET1[31]
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
Pull Up
input
I/O
Pull Down Programmable, Disable selected PWM
20 µA(1)
outputs
GIOA[2]/N2HET2[0] /EQEP2I
C1
D4
E1
Pull Down Programmable,
20 µA
N2HET2
capture
compare, or GIO.
time
or
input
output
EMIF_ADDR[0]/N2HET2[1]
GIOA[3]/N2HET2[2]
Each terminal has
suppression filter with
programmable duration.
a
a
EMIF_ADDR[1]/N2HET2[3]
D5
H3
D16
M1
N17
V2
GIOA[6]/N2HET2[4]/EPWM1B
EMIF_BA[1]/N2HET2[5]
GIOA[7]/N2HET2[6]/EPWM2A
EMIF_nCS[0]/N2HET2[7]
N2HET1[1]/SPI4NENA/ N2HET2[8]/EQEP2A
EMIF_nCS[3]/N2HET2[9]
K17
U1
C4
V6
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
EMIF_ADDR[6]/N2HET2[11]
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
EMIF_ADDR[7]/N2HET2[13]
C5
T1
N2HET1[7]/N2HET2[14]/EPWM7B
EMIF_ADDR[8]/N2HET2[15]
C6
V7
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
E3
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
V10
I/O
Pull Up
Programmable, Disable selected PWM
20 µA(1)
outputs
(1) The N2HETx_PIN_nDIS function is always available on this terminal. There is no mux control to select this function. The pull direction is
controlled by the function which is selected by the output mux control for this terminal.
26
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4.3.2.3 Enhanced Capture Modules (eCAP)
Table 4-23. ZWT Enhanced Capture Modules (eCAP)(1)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
N1
I/O
I/O
I/O
I/O
I/O
I/O
Pull Down
Pull Up
Fixed 20 µA
Pull Up
Enhanced Capture
Module 1 I/O
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
MIBSPI1NENA/N2HET1[23]/ECAP4
V8
Enhanced Capture
Module 2 I/O
W8
G19
H18
R2
Enhanced Capture
Module 3 I/O
Enhanced Capture
Module 4 I/O
MIBSPI5NENA/MIBSPI5SOMI[1]/ ECAP5
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ ECAP6
Enhanced Capture
Module 5 I/O
Enhanced Capture
Module 6 I/O
(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
4.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)
Table 4-24. ZWT Enhanced Quadrature Encoder Pulse Modules (eQEP)(1)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
V9
W9
V10
Input
Input
I/O
Pull Up
Fixed 20 µA
Pull Up
Enhanced QEP1 Input A
Enhanced QEP1 Input B
Enhanced QEP1 Index
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
MIBSPI1NCS[1]/N2HET1[17]/ EQEP1S
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
GIOA[2]/N2HET2[0]/ EQEP2I
F3
V2
I/O
Input
Input
I/O
Enhanced QEP1 Strobe
Enhanced QEP2 Input A
Enhanced QEP2 Input B
Enhanced QEP2 Index
Enhanced QEP2 Strobe
Pull Down
Pull Down
Pull Down
Pull Down
U1
C1
B11
N2HET1[30]/EQEP2S
I/O
(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
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4.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)
Table 4-25. ZWT Enhanced Pulse-Width Modulator Modules (ePWM)
TERMINAL
SIGNA Reset Pull
L TYPE State
PULL TYPE
DESCRIPTION
337
ZWT
SIGNAL NAME
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
GIOA[6]/N2HET2[4]/EPWM1B
B5
H3
E3
Output Pull Down
None
Enhanced PWM1 Output A
Enhanced PWM1 Output B
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
External ePWM Sync Pulse
Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
A4
Input
Fixed 20 µA External ePWM Sync Pulse
Pull Up
Input
GIOA[7]/N2HET2[6]/EPWM2A
N2HET1[0]/SPI4CLK/EPWM2B
N2HET1[2]/SPI4SIMO[0]/EPWM3A
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
MIBSPI5NCS[0]/EPWM4A
M1
K18
W5
V6
Output
None
Enhanced PWM2 Output A
Enhanced PWM2 Output B
Enhanced PWM3 Output A
Enhanced PWM3 Output B
Enhanced PWM4 Output A
Enhanced PWM4 Output B
Enhanced PWM5 Output A
Enhanced PWM5 Output B
Enhanced PWM6 Output A
Enhanced PWM6 Output B
Enhanced PWM7 Output A
Enhanced PWM7 Output B
E19
B12
W3
N2
Pull Up
N2HET1[4]/EPWM4B
Pull Down
N2HET1[6]/SCIRX/EPWM5A
N2HET1[13]/SCITX/EPWM5B
N2HET1[18]/EPWM6A
J1
N2HET1[20]/EPWM6B
P2
N2HET1[9]/N2HET2[16]/EPWM7A
N2HET1[7]/N2HET2[14]/EPWM7B
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
N2HET1[10]/nTZ3
V7
T1
C3
Input
Pull Up
Fixed 20 µA Trip Zone Inputs 1, 2 and 3.
Pull Up
These signals are either
connected asynchronously to
the ePWMx trip zone inputs,
or double-synchronized with
VCLK4, or double-
B2
D19
Pull Down
synchronized and then
filtered with a 6-cycle
VCLK4-based counter before
connecting to the ePWMx
trip zone inputs.
28
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4.3.2.6 General-Purpose Input / Output (GPIO)
Table 4-26. ZWT General-Purpose Input / Output (GPIO)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
GIOA[0]
GIOA[1]
A5
C2
I/O
Pull Down Programmable, General-purpose I/O.
20 µA
All GPIO terminals are
capable of generating
interrupts to the CPU on
rising / falling / both
edges.
GIOA[2]/N2HET2[0] /EQEP2I
GIOA[3]/N2HET2[2]
GIOA[4]
C1
E1
A6
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
GIOA[6]/N2HET2[4]/EPWM1B
GIOA[7]/N2HET2[6]/EPWM2A
GIOB[0]
B5
H3
M1
M2
K2
GIOB[1]
GIOB[2]
F2
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
V10(1)
EQEP1I/N2HET2_PIN_nDIS
GIOB[3]
GIOB[4]
GIOB[5]
GIOB[6]
GIOB[7]
W10
G1
G2
J2
F1
(1) GIOB[2] cannot output a level on to terminal V10. Only the input functionality is supported so that the application can generate an
interrupt whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pull up is enabled on the input. This is not programmable
using the GIO module control registers.
4.3.2.7 FlexRay Interface Controller (FlexRay)
Table 4-27. FlexRay Interface Controller (FlexRay)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
FRAYRX1
FRAYTX1
A15
B15
B16
A8
Input
Output
Output
Input
Pull Up
N/A
Fixed 100 µA
Pull Up
FlexRay data receive
(channel 1)
None
FlexRay data transmit
(channel 1)
FRAYTXEN1
FRAYRX2
FRAYTX2
FlexRay transmit enable
(channel 1)
Pull Up
N/A
Fixed 100 µA
Pull Up
FlexRay data receive
(channel 2)
B8
Output
Output
None
FlexRay data transmit
(channel 2)
FRAYTXEN2
B9
FlexRay transmit enable
(channel 2)
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4.3.2.8 Controller Area Network Controllers (DCAN)
Table 4-28. ZWT Controller Area Network Controllers (DCAN)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
CAN1RX
CAN1TX
CAN2RX
CAN2TX
CAN3RX
CAN3TX
B10
A10
H1
I/O
Pull Up
Programmable, CAN1 receive, or GPIO
20 µA
CAN1 transmit, or GPIO
CAN2 receive, or GPIO
CAN2 transmit, or GPIO
CAN3 receive, or GPIO
CAN3 transmit, or GPIO
H2
M19
M18
4.3.2.9 Local Interconnect Network Interface Module (LIN)
Table 4-29. ZWT Local Interconnect Network Interface Module (LIN)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
LINRX
LINTX
A7
B7
I/O
Pull Up
Programmable, LIN receive, or GPIO
20 µA
LIN transmit, or GPIO
4.3.2.10 Standard Serial Communication Interface (SCI)
Table 4-30. ZWT Standard Serial Communication Interface (SCI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
N2HET1[6]/SCIRX/EPWM5A
N2HET1[13]/SCITX/EPWM5B
W3
N2
I/O
Pull Down Programmable, SCI receive, or GPIO
20 µA
SCI transmit, or GPIO
30
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4.3.2.11 Inter-Integrated Circuit Interface Module (I2C)
Table 4-31. ZWT Inter-Integrated Circuit Interface Module (I2C)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
B2
C3
I/O
Pull Up
Programmable, I2C serial data, or GPIO
20 µA
I2C serial clock, or GPIO
4.3.2.12 Standard Serial Peripheral Interface (SPI)
Table 4-32. ZWT Standard Serial Peripheral Interface (SPI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
SPI2CLK
E2
N3
D3
D3
D1
I/O
Pull Up
Programmable, SPI2 clock, or GPIO
20 µA
SPI2NCS[0]
SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1]
SPI2NENA/SPI2NCS[1]
SPI2SIMO[0]
SPI2 chip select, or GPIO
SPI2 enable, or GPIO
SPI2 slave-input master-
output, or GPIO
SPI2SOMI[0]
D2
SPI2 slave-output master-
input, or GPIO
N2HET1[0]/SPI4CLK/EPWM2B
K18
U1
I/O
Pull Down Programmable, SPI4 clock, or GPIO
20 µA
N2HET1[3]/SPI4NCS[0]/N2HET2[10]/EQEP2B
N2HET1[1]/SPI4NENA/N2HET2[8]/EQEP2A
N2HET1[2]/SPI4SIMO[0]/EPWM3A
SPI4 chip select, or GPIO
V2
SPI4 enable, or GPIO
W5
SPI4 slave-input master-
output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
V6
SPI4 slave-output master-
input, or GPIO
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4.3.2.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-33. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
MIBSPI1CLK
F18
R2
I/O
Pull Up
Programmable, MibSPI1 clock, or GPIO
20 µA
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S
MIBSPI1NCS[2]/N2HET1[19]
MibSPI1 chip select, or
GPIO
F3
G3
J3
MIBSPI1NCS[3]/N2HET1[21]
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
N2HET1[24]/MIBSPI1NCS[5]
N1
Pull Down Programmable, MibSPI1 chip select, or
20 µA GPIO
P1
MIBSPI1NENA/N2HET1[23]/ECAP4
MIBSPI1SIMO[0]
G19
F19
Pull Up
Programmable, MibSPI1 enable, or GPIO
20 µA
MibSPI1 slave-in master-
out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]
E18
Pull Down Programmable, MibSPI1 slave-in master-
20 µA out, or GPIO
MIBSPI1SOMI[0]
G18
R2
Pull Up
Programmable, MibSPI1 slave-out master-
20 µA in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
V9
I/O
Pull Up
Programmable, MibSPI3 clock, or GPIO
20 µA
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
V10
MibSPI3 chip select, or
EQEP1I/N2HET2_PIN_nDIS
GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK
V5
B2
C3
E3
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]/nTZ2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]/nTZ1
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
Pull Down Programmable, MibSPI3 chip select, or
20 µA GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
W9
Pull Up
Programmable, MibSPI3 chip select, or
20 µA
GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
W9
W8
MibSPI3 enable, or GPIO
MibSPI3 slave-in master-
out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
V8
MibSPI3 slave-out master-
in, or GPIO
MIBSPI5CLK
H19
E19
B6
I/O
Pull Up
Programmable, MibSPI5 clock, or GPIO
20 µA
MIBSPI5NCS[0]/EPWM4A
MIBSPI5NCS[1]
MibSPI5 chip select, or
GPIO
MIBSPI5NCS[2]
W6
MIBSPI5NCS[3]
T12
H18
J19
E16
H17
G17
J18
E17
H18
H16
J19
G16
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
MIBSPI5SIMO[1]
MibSPI5 enable, or GPIO
MibSPI5 slave-in master-
out, or GPIO
MIBSPI5SIMO[2]
MIBSPI5SIMO[3]
MIBSPI5SOMI[0]
MibSPI5 slave-out master-
in, or GPIO
MIBSPI5SOMI[1]
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5
MIBSPI5SOMI[2]
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
MIBSPI5SOMI[3]
32
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4.3.2.14 External Memory Interface (EMIF)
Table 4-34. External Memory Interface (EMIF)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
EMIF_CKE
EMIF_CLK
L3
K3
Output
I/O
Pull Up
None
None
EMIF Clock Enable
EMIF clock. This is an
output signal in functional
mode. It is gated off by
default, so that the signal
is pulled up. PINMUX29[8]
must be cleared to enable
this output.
EMIF_nOE
E12
P3
Output
I/O
Pull Up
Pull Up
None
EMIF Read Enable
EMIF_nWAIT
Fixed 20 µA
Pull Up
EMIF Extended Wait
Signal
EMIF_nWE
EMIF_nCAS
D17
R4
Output
Output
Pull Up
None
EMIF Write Enable
EMIF column address
strobe
EMIF_nRAS
EMIF_nCS[0]/N2HET2[7](1)
R3
Output
Output
EMIF row address strobe
N17
EMIF chip select,
synchronous
EMIF_nCS[2]
EMIF_nCS[3]/N2HET2[9](1)
L17
K17
M17
E10
E11
Output
Output
Output
Output
Output
EMIF chip selects,
asynchronous
This applies to chip
selects 2, 3 and 4
EMIF_nCS[4]
EMIF_nDQM[0]
EMIF_nDQM[1]
EMIF Data Mask or Write
Strobe.
Data mask for SDRAM
devices, write strobe for
connected asynchronous
devices.
EMIF_BA[0]
E13
D16
Output
Output
EMIF bank address or
address line
EMIF_BA[1]/N2HET2[5](1)
EMIF bank address or
address line
EMIF_ADDR[0]/N2HET2[1](1)
EMIF_ADDR[1]/N2HET2[3](1)
EMIF_ADDR[2]
D4
D5
E6
E7
E8
E9
C4
C5
C6
C7
C8
C9
C10
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
EMIF address
EMIF_ADDR[3]
EMIF_ADDR[4]
EMIF_ADDR[5]
EMIF_ADDR[6]/N2HET2[11](1)
EMIF_ADDR[7]/N2HET2[13](1)
EMIF_ADDR[8]/N2HET2[15](1)
EMIF_ADDR[9]
EMIF_ADDR[10]
EMIF_ADDR[11]
EMIF_ADDR[12]
(1) These signals are tri-stated and pulled up by default after power-up. Any application that requires the EMIF must set the bit 31 of the
system module general-purpose register GPREG1.
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Table 4-34. External Memory Interface (EMIF) (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
EMIF_DATA[0]
EMIF_DATA[1]
EMIF_DATA[2]
EMIF_DATA[3]
EMIF_DATA[4]
EMIF_DATA[5]
EMIF_DATA[6]
EMIF_DATA[7]
EMIF_DATA[8]
EMIF_DATA[9]
EMIF_DATA[10]
EMIF_DATA[11]
EMIF_DATA[12]
EMIF_DATA[13]
EMIF_DATA[14]
EMIF_DATA[15]
K15
L15
M15
N15
E5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pull Up
Fixed 20 µA
Pull Up
EMIF Data
F5
G5
K5
L5
M5
N5
P5
R5
R6
R7
R8
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4.3.2.15 System Module Interface
Table 4-35. ZWT System Module Interface
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
nPORRST
W7
Input
Pull Down
Fixed 100 µA
Pull Down
Power-on reset, cold reset
External power supply
monitor circuitry must
drive nPORRST low when
any of the supplies to the
microcontroller fall out of
the specified range. This
terminal has a glitch filter.
See Section 6.8.
nRST
B17
I/O
Pull Up
Fixed 100 µA
Pull Up
System reset, warm reset,
bidirectional.
The internal circuitry
indicates any reset
condition by driving nRST
low.
The external circuitry can
assert a system reset by
driving nRST low. To
ensure that an external
reset is not arbitrarily
generated, TI
recommends that an
external pull-up resistor is
connected to this terminal.
This terminal has a glitch
filter. See Section 6.8.
nERROR
B14
I/O
Pull Down
Fixed 20 µA
Pull Down
ESM Error Signal
Indicates error of high
severity. See
Section 6.18.
4.3.2.16 Clock Inputs and Outputs
Table 4-36. ZWT Clock Inputs and Outputs
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
OSCIN
K1
Input
N/A
None
From external
crystal/resonator, or
external clock input
KELVIN_GND
OSCOUT
L2
L1
Input
Kelvin ground for oscillator
Output
To external
crystal/resonator
ECLK
A12
I/O
Pull Down Programmable, External prescaled clock
20 µA
output, or GIO.
GIOA[5]/EXTCLKIN/EPWM1A/N2HET1_PIN_nDIS
B5
R9
Input
Input
Pull Down
N/A
20 µA
External clock input #1
External clock input #2
EXTCLKIN2
VCCPLL
P11
1.2V
Power
None
Dedicated core supply for
PLL's
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4.3.2.17 Test and Debug Modules Interface
Table 4-37. ZWT Test and Debug Modules Interface
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
TEST
U2
Input
Pull Down
Fixed 100 µA
Pull Down
Test enable. This terminal
must be connected to
ground directly or via a
pull-down resistor.
nTRST
RTCK
TCK
D18
A16
B18
Input
Output
Input
JTAG test hardware reset
JTAG return test clock
JTAG test clock
N/A
None
Pull Down
Fixed 100 µA
Pull Down
TDI
A17
C18
C19
Input
Output
Input
Pull Up
Fixed 100 µA
Pull Up
JTAG test data in
JTAG test data out
JTAG test select
TDO
TMS
100 µA
Pull Down
None
Pull Up
Fixed 100 µA
Pull Up
4.3.2.18 Flash Supply and Test Pads
Table 4-38. ZWT Flash Supply and Test Pads
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
VCCP
F8
3.3V
Power
N/A
N/A
None
None
Flash pump supply
FLTP1
FLTP2
J5
-
Flash test pads. These
terminals are reserved for
TI use only. For proper
operation these terminals
must connect only to a
test pad or not be
H5
connected at all [no
connect (NC)].
36
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4.3.2.19 No Connects
Table 4-39. No Connects
Terminal
Signal Name
Signal Reset Pull
Pull Type
Description
Type
State
337
ZWT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C11
C12
C13
C14
C15
C16
C17
D6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
No Connects. These balls
are not connected to any
internal logic and can be
connected to the PCB
ground without affecting
the functionality of the
device.
D7
D8
D9
D10
D11
D12
D13
D14
D15
E4
E14
E15
F4
F15
F16
F17
G4
G15
H15
J15
J16
K4
K16
L4
L16
L18
L19
M4
M16
N4
N16
N18
P4
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Table 4-39. No Connects (continued)
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P15
P16
P17
R1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
No Connects. These balls
are not connected to any
internal logic and can be
connected to the PCB
ground without affecting
the functionality of the
device.
R10
R11
R12
R13
R14
R15
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T13
T14
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
V3
V4
V11
V12
W4
W11
W12
W13
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4.3.2.20 Supply for Core Logic: 1.2V nominal
Table 4-40. ZWT Supply for Core Logic: 1.2V nominal
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F9
F10
H10
J14
K6
1.2V
Power
N/A
None
Core supply
K8
K12
K14
L6
M10
P10
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4.3.2.21 Supply for I/O Cells: 3.3V nominal
Table 4-41. ZWT Supply for I/O Cells: 3.3V nominal
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
F6
F7
3.3V
Power
N/A
None
Operating supply for I/Os
F11
F12
F13
F14
G6
G14
H6
H14
J6
L14
M6
M14
N6
N14
P6
P7
P8
P9
P12
P13
P14
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4.3.2.22 Ground Reference for All Supplies Except VCCAD
Table 4-42. ZWT Ground Reference for All Supplies Except VCCAD
Terminal
Signal Reset Pull
Pull Type
Description
Type
State
Signal Name
337
ZWT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
Ground
N/A
None
Ground reference
A18
A19
B1
B19
H8
H9
H11
H12
J8
J9
J10
J11
J12
K9
K10
K11
L8
L9
L10
L11
L12
M8
M9
M11
M12
V1
W1
W2
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5 Specifications
(1)
5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
MIN
MAX
1.43
4.6
UNIT
(2)
VCC
-0.3
-0.3
-0.3
-0.3
-0.3
V
V
V
V
V
(2)
Supply voltage range:
Input voltage range:
VCCIO, VCCP
VCCAD
6.25
4.6
All input pins, with exception of ADC pins
ADC input pins
6.25
IIK (VI < 0 or VI > VCCIO
All pins, except AD1IN[23:0] or AD2IN[15:0]
)
-20
-10
+20
+10
mA
mA
Input clamp current:
IIK (VI < 0 or VI > VCCAD)
AD1IN[23:0] or AD2IN[15:0]
Total
-40
-40
-40
-65
+40
125
150
150
mA
°C
°C
°C
Operating free-air temperature range, TA:
Operating junction temperature range, TJ:
Storage temperature range, Tstg
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.
5.2 ESD Ratings
VALUE
±2
UNIT
kV
Human body model (HBM), per AEC Q100-002(1)
Electrostatic discharge
(ESD) performance:
All pins
±500
V
VESD
Charged device model (CDM),
per AEC Q100-011
Corner pins on 144-pin PGE
(1, 36, 37, 72, 73, 108, 109, 144)
±750
±750
V
V
Corner balls on 337-ball ZWT
(A1, A19, W1, W19)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.
5.3 Power-On Hours (POH)(1)(2)
JUNCTION
TEMPERATURE (Tj)
NOMINAL CORE VOLTAGE (VCC
)
LIFETIME POH
1.2
105ºC
100K
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to
equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application
Report (SPNA207).
42
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5.4 Device Recommended Operating Conditions(1)
MIN
1.14
1.14
3
NOM
1.2
MAX UNIT
VCC
Digital logic supply voltage (Core)
PLL Supply Voltage
1.32
1.32
3.6
V
V
VCCPLL
VCCIO
VCCAD
VCCP
1.2
Digital logic supply voltage (I/O)
MibADC supply voltage
3.3
V
3
5.25
3.6
V
Flash pump supply voltage
3
3.3
0
V
VSS
Digital logic supply ground
V
VSSAD
VADREFHI
VADREFLO
VSLEW
TA
MibADC supply ground
-0.1
VSSAD
VSSAD
0.1
VCCAD
VCCAD
1
V
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Maximum positive slew rate for VCCIO, VCCAD and VCCP supplies
Operating free-air temperature
Operating junction temperature(2)
V
V
V/µs
°C
°C
-40
-40
125
TJ
150
(1) All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.
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5.5 Switching Characteristics Over Recommended Operating Conditions for Clock Domains
Table 5-1. Clock Domain Timing Specifications
PARAMETER
DESCRIPTION
CONDITIONS
Pipeline mode
MAX
UNIT
160
MHz
enabled
PGE
ZWT
Pipeline mode
disabled
50
180
50
MHz
MHz
MHz
fHCLK
HCLK - System clock frequency
Pipeline mode
enabled
Pipeline mode
disabled
fGCLK
fVCLK
GCLK - CPU clock frequency
fHCLK
100
MHz
MHz
VCLK - Primary peripheral clock frequency
VCLK2 - Secondary peripheral clock
frequency
fVCLK2
fVCLK3
fVCLK4
fVCLKA1
fVCLKA2
fVCLKA3
100
100
150
100
100
100
MHz
MHz
MHz
MHz
MHz
MHz
VCLK3 - Secondary peripheral clock
frequency
VCLK4 - Secondary peripheral clock
frequency
VCLKA1 - Primary asynchronous
peripheral clock frequency
VCLKA2 - Secondary asynchronous
peripheral clock frequency
VCLKA3 - Primary asynchronous
peripheral clock frequency
VCLKA4 - Secondary asynchronous
peripheral clock frequency
fVCLKA4
fRTICLK
100
MHz
MHz
RTICLK - clock frequency
fVCLK
5.6 Wait States Required
RAM
0
0
Address Wait States
0MHz
fHCLK(max)
Data Wait States
0MHz
fHCLK(max)
Flash (Main Memory)
1
Address Wait States
0
150MHz
150MHz
0MHz
fHCLK(max)
fHCLK(max)
Data Wait States
0
0
1
2
2
3
3
0MHz
50MHz
50MHz
100MHz
Flash (Data Memory)
1
Data Wait States
0MHz
100MHz
150MHz
fHCLK(max)
Figure 5-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined
mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and
180 MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
44
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5.7 Power Consumption Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
fHCLK = 160MHz
fHCLK = 180MHz
MIN
TYP
MAX UNIT
(1)
(2)
175
350
VCC digital supply current (operating mode)
fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax
mA
195(1)
370(2)
215(1)
465(3)(4) mA
ICC
LBIST/PBIST clock
frequency = 80MHz
VCC Digital supply current (LBIST/PBIST mode)
LBIST/PBIST clock
frequency = 90MHz
(3)(4)
240(1)
465
mA
ICCPLL
ICCIO
VCCPLL digital supply current (operating mode)
VCCIO Digital supply current (operating mode.
VCCPLL = VCCPLLmax
No DC load, VCCmax
10 mA
10 mA
Single ADC
operational,
VCCADmax
15
ICCAD
VCCAD supply current (operating mode)
mA
30
Both ADCs
operational,
VCCADmax
Single ADC
operational,
ADREFHImax
3
IADREFHI
ADREFHI supply current (operating mode)
mA
6
Both ADCs
operational,
ADREFHImax
read from 1 bank
and program
another bank,
VCCPmax
ICCP
VCCP supply current
55 mA
(1) The typical value is the average current for the nominal process corner and junction temperature of 25C.
(2) The maximum ICC, value can be derated
•
•
•
linearly with voltage
by 1 ma/MHz for lower operating frequency when fHCLK= 2 * fVCLK
for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
164 - 0.07 0.01813T
JK
(3) The maximum ICC, value can be derated
•
•
•
linearly with voltage
by 1.5 ma/MHz for lower operating frequency
for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
164 - 0.07 0.01813T
JK
(4) LBIST and PBIST currents are for a short duration, typically less than 10ms. They are usually ignored for thermal calculations for the
device and the voltage regulator
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5.8 Input/Output Electrical Characteristics Over Recommended Operating Conditions(1)
PARAMETER
TEST CONDITIONS
MIN
180
100
-0.3
TYP
MAX UNIT
All inputs (except
FRAYRX1,
FRAYRX2)
mV
mV
Vhys
Input hysteresis
FRAYRX1, FRAYRX2
All inputs(2) (except
FRAYRX1,
0.8
0.4 VCCIO
V
V
V
V
VIL
Low-level input voltage
High-level input voltage
FRAYRX2)
FRAYRX1, FRAYRX2
All inputs(2) (except
FRAYRX1,
2
VCCIO + 0.3
VIH
FRAYRX2)
FRAYRX1, FRAYRX2
0.6 VCCIO
IOL = IOLmax
0.2 VCCIO
0.2
IOL = 50 µA, standard
output mode
VOL
Low-level output voltage
V
IOL = 50 µA, low-EMI
output mode (see
Section 5.13)
0.2 VCCIO
IOH = IOHmax
0.8 VCCIO
VCCIO -0.3
IOH = 50 µA, standard
output mode
VOH
High-level output voltage
Input clamp current (I/O pins)(3)
Input current (I/O pins)
V
IOH = 50 µA, low-EMI
output mode (see
Section 5.13)
0.8 VCCIO
-3.5
VI < VSSIO - 0.3 or VI
> VCCIO + 0.3
IIK
3.5
mA
µA
IIH Pulldown 20µA
IIH Pulldown 100µA
IIL Pullup 20µA
IIL Pullup 100µA
All other pins
VI = VCCIO
5
40
40
195
-5
VI = VCCIO
II
VI = VSS
-40
-195
-1
VI = VSS
-40
1
No pullup or pulldown
CI
Input capacitance
Output capacitance
2
3
pF
pF
CO
(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.
(2) This does not apply to the nPORRST pin.
(3) If the input voltage extends outside of the range VIL to VIH then the input current must be limited to IIK to maintain proper operation. See
the application note SPNA201 for more information on limiting input clamp currents.
5.9 Thermal Resistance Characteristics
Table 5-2 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-3 shows the thermal resistance characteristics for the BGA - ZWT mechanical package.
Table 5-2. Thermal Resistance Characteristics (PGE Package)
°C/W
Junction-to-free air thermal resistance, Still
RΘJA
40
air using JEDEC 2S2P test board
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Junction-to-package top, Still air
RΘJB
RΘJC
ΨJT
27.2
7.3
0.10
46
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Table 5-3. Thermal Resistance Characteristics (ZWT Package)
°C/W
Junction-to-free air thermal resistance, Still
air (includes 5x5 thermal via cluster in 2s2p
PCB connected to 1st ground plane)
RΘJA
18.8
RΘJB
RΘJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
14.1
7.1
Junction-to-package top, Still air (includes
5x5 thermal via cluster in 2s2p PCB
connected to 1st ground plane)
ΨJT
0.33
5.10 Output Buffer Drive Strengths
Table 5-4. Output Buffer Drive Strengths
LOW-LEVEL OUTPUT CURRENT,
IOL for VI=VOLmax
or
SIGNALS
HIGH-LEVEL OUTPUT CURRENT,
IOH for VI=VOHmin
FRAYTX2, FRAYTX1, FRAYTXEN1, FRAYTXEN2,
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
TMS, TDI, TDO, RTCK,
SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,
N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11], N2HET2[13],
N2HET2[15]
8 mA
ECAP1, ECAP4, ECAP5, ECAP6
EQEP1I, EQEP1S, EQEP2I, EQEP2S
EPWM1A, EPWM1B, EPWM1SYNCO, ETPW2A, EPWM2B, EPWM3A, EPWM3B,
EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B
EMIF_ADDR[0:12], EMIF_BA[0:1], EMIF_CKE, EMIF_CLK, EMIF_DATA[0:15], EMIF_nCAS,
EMIF_nCS[0:4], EMIF_nDQM[0:1], EMIF_nOE, EMIF_nRAS, EMIF_nWAIT, EMIF_nWE,
EMIF_RNW
TEST,
MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,
4 mA
ECAP2, ECAP3
nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
GIOA[0-7], GIOB[0-7],
LINRX, LINTX,
2 mA zero-dominant
MIBSPI1nCS[0], MIBSPI1nCS[1-3], MIBSPI1nENA, MIBSPI3nCS[0-3], MIBSPI3nENA,
MIBSPI5nCS[0-3], MIBSPI5nENA,
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],
N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],
N2HET2[15], N2HET2[16], N2HET2[18],
SPI2nCS[0], SPI2nENA, SPI4nCS[0], SPI4nENA
ECLK,
selectable 8 mA / 2 mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8 mA for these signals.
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Table 5-5. Selectable 8 mA/2 mA Control
Signal
ECLK
Control Bit
SYSPC10[0]
SPI2PC9[9]
Address
8 mA
2 mA
0xFFFF FF78
0xFFF7 F668
0xFFF7 F668
0xFFF7 F668
0
0
0
0
1
1
1
1
SPI2CLK
SPI2SIMO
SPI2SOMI
SPI2PC9[10]
SPI2PC9[11](1)
(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits
differ, SPI2PC9[11] determines the drive strength.
5.11 Input Timings
tpw
VCCIO
Input
VIH
VIH
VIL
VIL
0
Figure 5-2. TTL-Level Inputs
Table 5-6. Timing Requirements for Inputs(1)
Parameter
MIN
tc(VCLK) + 10(2)
MAX
Unit
ns
tpw
Input minimum pulse width
tin_slew
Time for input signal to go from VIL to VIH or from VIH to VIL
1
ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.
tpw
VCCIO
Input
0.6*VCCIO
0.6*VCCIO
0.4*VCCIO
0.4*VCCIO
0
Figure 5-3. Flexray Inputs
Table 5-7. Timing Requirements for FlexRay Inputs(1)
Parameter
MIN
MAX
Unit
tpw
Input minimum pulse width to meet the Flexray sampling
requirement
tc(VCLKA2) + 2.5
ns
(1) tc(VCLKA2) = sample clock cycle time for FlexRay = 1 / f(VCLKA2)
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5.12 Output Timings
Table 5-8. Switching Characteristics for Output Timings versus Load Capacitance ©L)
Parameter
MIN
MAX
2.5
4
Unit
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
Rise time, tr
Fall time, tf
8 mA low EMI pins
(see Table 5-4)
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL= 50 pF
ns
7.2
12.5
2.5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.2
12.5
5.6
10.4
16.8
23.2
5.6
10.4
16.8
23.2
8
4 mA low EMI pins
(see Table 5-4)
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
CL = 15 pF
CL = 50 pF
CL = 100 pF
CL = 150 pF
2 mA-z low EMI pins
(see Table 5-4)
15
23
33
8
15
23
33
Selectable 8 mA / 2 mA-z 8 mA mode
2.5
4
pins
(see Table 5-4)
7.2
12.5
2.5
4
7.2
12.5
8
2 mA-z mode
15
23
33
8
15
23
33
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tr
t
f
VCCIO
Output
VOH
VOH
VOL
VOL
0
Figure 5-4. CMOS-Level Outputs
Table 5-9. Timing Requirements for Outputs(1)
Parameter
MIN
MAX
UNIT
td(parallel_out)
Delay between low to high, or high to low transition of general-purpose output signals
that can be configured by an application in parallel, e.g. all signals in a GIOA port, or
all N2HET1 signals, etc.
6
ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 5-4 for output buffer drive strength information on each signal.
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5.13 Low-EMI Output Buffers
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of
emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of
the output buffer, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the
system module GPCR1 register for the desired module or signal, as shown in . The adaptive impedance
control circuit monitors the DC bias point of the output signal. The buffer internally generates two
reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO
,
respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then
the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal
ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,
e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull
the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain
the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above
VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling
between internal power bus ad output pin will occur with capacitive loads or any loads in which no current
is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which
attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so
as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance
control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this
manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will
allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a
negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an
issue since the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the
device enters a low-power mode.
Table 5-10. Low-EMI Output Buffer Hookup
Module or Signal Name
Control Register to Enable Low-EMI Mode
GPREG1.0
Module: MibSPI1
Module: SPI2
Module: MibSPI3
Reserved
GPREG1.1
GPREG1.2
GPREG1.3
Module: MibSPI5
Module: FlexRay
Module: EMIF
Reserved
GPREG1.4
GPREG1.5
GPREG1.6
GPREG1.7
Signal: TMS
GPREG1.8
Signal: TDI
GPREG1.9
Signal: TDO
GPREG1.10
GPREG1.11
GPREG1.12
GPREG1.13
GPREG1.14
Signal: RTCK
Signal: TEST
Signal: nERROR
Signal: AD1EVT
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6 System Information and Electrical Specifications
6.1 Device Power Domains
The device core logic is split up into multiple power domains to optimize the Self-Test Clock Configuration
power for a given application use case. There are 7 power domains in total: PD1, PD2, PD3, PD4, PD5,
and RAM_PD1. Refer to Section 1.4 for more information.
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other power domains can
be turned OFF one time during device initialization as per the application requirement. Refer to the Power
Management Module (PMM) chapter of TMS570LS12x/11x Technical Reference Manual (SPNU515) for
more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that
contains the module.
NOTE
The logic in the modules that are powered down loses its power completely. Any access to
modules that are powered down results in an abort being generated. When power is
restored, the modules power-up to their default states (after normal power-up). No register or
memory contents are preserved in the core domains that are turned off.
6.2 Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.
6.2.1 Important Considerations
•
The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in
reset when the voltage supplies are out of range.
•
The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not
monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for
VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.
6.2.2 Voltage Monitor Operation
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO
signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when
the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and
PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down
of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing
information on this glitch filter.
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Table 6-1. Voltage Monitoring Specifications
PARAMETER
VCC low - VCC level below this
MIN
0.75
TYP
MAX
UNIT
0.9
1.13
V
threshold is detected as too low.
Voltage monitoring
thresholds
VCC high - VCC level above this
threshold is detected as too high.
1.40
1.85
1.7
2.4
2.1
2.9
VMON
VCCIO low - VCCIO level below this
threshold is detected as too low.
6.2.3 Supply Filtering
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the
maximum specification cannot be filtered.
Table 6-2. VMON Supply Glitch Filtering Capability
Parameter
MIN
MAX
1 µs
1 µs
Width of glitch on VCC that can be filtered
Width of glitch on VCCIO that can be filtered
250 ns
250 ns
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6.3 Power Sequencing and Power On Reset
6.3.1 Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-
up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator start-up and validity check
eFuse autoload
1032 oscillator cycles
1160 oscillator cycles
688 oscillator cycles
617 oscillator cycles
3497 oscillator cycles
Flash pump power-up
Flash bank power-up
Total
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
6.3.2 Power-Down Sequence
The different supplies to the device can be powered down in any order.
6.3.3 Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core
supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1 nPORRST Electrical and Timing Requirements
Table 6-4. Electrical Requirements for nPORRST
NO Parameter
MIN
MAX
Unit
VCCPORL
VCC low supply level when nPORRST must be active during power-
up
0.5
V
VCCPORH
VCC high supply level when nPORRST must remain active during
power-up and become active during power down
1.14
V
V
V
VCCIOPORL
VCCIOPORH
VIL(PORRST)
VCCIO / VCCP low supply level when nPORRST must be active during
power-up
1.1
VCCIO / VCCP high supply level when nPORRST must remain active
during power-up and become active during power down
3.0
Low-level input voltage of nPORRST VCCIO > 2.5V
Low-level input voltage of nPORRST VCCIO < 2.5V
0.2 * VCCIO
0.5
V
V
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL
during power-up
0
ms
6
7
th(PORRST)
tsu(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
2
ms
µs
Setup time, nPORRST active before VCC < VCCPORH during power
down
8
9
th(PORRST)
th(PORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
Hold time, nPORRST active after VCC < VCCPORL
1
0
ms
ms
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Table 6-4. Electrical Requirements for nPORRST (continued)
NO Parameter
MIN
475
MAX
Unit
tf(nPORRST)
2000
ns
Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than MAX
will generate a reset.
3.3 V
1.2 V
VCCIOPORH
VCCIOPORH
VCCIO / VCCP
8
6
VCCPORH
VCC
VCCPORH
7
6
VCCIOPORL
7
VCCIOPORL
VCCPORL
VCCPORL
VCC (1.2 V)
VCCIO / VCCP(3.3 V)
3
9
VIL
VIL
VIL
VIL(PORRST)
VIL(PORRST)
nPORRST
NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.
Figure 6-1. nPORRST Timing Diagram
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6.4 Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup.
6.4.1 Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Exception Status Register, bit 15
Global Status Register, bit 0
Power-Up Reset
Oscillator fail
PLL slip
Global Status Register, bits 8 and 9
Exception Status Register, bit 13
Exception Status Register, bit 4
Exception Status Register, bit 3
Watchdog exception / Debugger reset
Software Reset
External Reset
6.4.2 nRST Timing Requirements
Table 6-6. nRST Timing Requirements
PARAMETER
MIN
MAX
UNIT
(1)
tv(RST)
Valid time, nRST active after
nPORRST inactive
2256 tc(OSC)
ns
Valid time, nRST active (all other
System reset conditions)
32 tc(VCLK)
475
tf(nRST)
2000
ns
Filter time nRST pin;
pulses less than MIN will be
filtered out, pulses greater than
MAX will generate a reset
(1) Assumes the oscillator has started up and stabilized before nPORRST is released ..
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6.5 ARM Cortex-R4F CPU Information
6.5.1 Summary of ARM Cortex-R4F CPU Features
The features of the ARM Cortex-R4F CPU include:
•
•
An integer unit with integral Embedded ICE-RT logic.
High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
•
•
•
•
•
Floating Point Coprocessor
Dynamic branch prediction with a global history buffer, and a 4-entry return stack
Low interrupt latency.
Non-maskable interrupt.
A Harvard Level one (L1) memory system with:
–
Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
–
ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
•
•
Dual core logic for fault detection in safety-critical applications.
An L2 memory interface:
–
–
Single 64-bit master AXI interface
64-bit slave AXI interface to TCM RAM blocks
•
•
•
A debug interface to a CoreSight Debug Access Port (DAP).
A Performance Monitoring Unit (PMU).
A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F CPU, see www.arm.com.
6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
•
•
•
•
ECC On Tightly-Coupled Memory (TCM) Accesses
Hardware Vectored Interrupt (VIC) Port
Floating Point Coprocessor
Memory Protection Unit (MPU)
6.5.3 Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-
R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock
cycles as shown in Figure 6-3.
The CPUs have a diverse CPU placement given by following requirements:
•
different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
•
dedicated guard ring for each CPU
Flip West
North
Figure 6-2. Dual - CPU Orientation
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6.5.4 Duplicate clock tree after GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.
6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in
the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in
a different way as shown in the figure below.
Output + Control
CCM-R4
2 cycle delay
CCM-R4
compare
compare
error
CPU1CLK
CPU 1
CPU 2
2 cycle delay
CPU2CLK
Input + Control
Figure 6-3. Dual Core Implementation
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
6.5.6 CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
•
•
•
Ability to divide the complete test run into independent test intervals
Capable of running the complete test as well as running few intervals at a time
Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
•
•
•
Complete isolation of the self-tested CPU core from rest of the system during the self-test run
Ability to capture the Failure interval number
Timeout counter for the CPU self-test run as a fail-safe feature
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6.5.6.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515).
6.5.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515).
6.5.6.3 CPU Self-Test Coverage
Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 6-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
0
TEST CYCLES
0
0
1
62.13
70.09
74.49
77.28
79.28
80.90
82.02
83.10
84.08
84.87
85.59
86.11
86.67
87.16
87.61
87.98
88.38
88.69
88.98
89.28
89.50
89.76
90.01
90.21
1365
2
2730
3
4095
4
5460
5
6825
6
8190
7
9555
8
10920
12285
13650
15015
16380
17745
19110
20475
21840
23205
24570
25935
27300
28665
30030
31395
32760
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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6.6 Clocks
6.6.1 Clock Sources
The table below lists the available clock sources on the device. Each of the clock sources can be enabled
or disabled using the CSDISx registers in the system module. The clock source number in the table
corresponds to the control bit in the CSDISx register for that clock source.
The table also shows the default state of each clock source.
Table 6-8. Available Clock Sources
Clock
Source #
Name
Description
Default State
0
1
2
3
4
OSCIN
PLL1
Main Oscillator
Output From PLL1
Enabled
Disabled
Disabled
Disabled
Enabled
Reserved
EXTCLKIN1
LFLPO
Reserved
External Clock Input #1
Low Frequency Output of Internal Reference Oscillator
High Frequency Output of Internal Reference
Oscillator
5
HFLPO
Enabled
6
7
PLL2
Output From PLL2
Disabled
Disabled
EXTCLKIN2
External Clock Input #2
6.6.1.1 Main Oscillator
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
TI strongly encourages each customer to submit samples of the device to the resonator/crystal
vendors for validation. The vendors are equipped to determine what load capacitors will best tune
their resonator/crystal to the microcontroller device for optimum start-up and operation over
temperature/voltage extremes.
An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in the figure below.
(see Note B)
OSCIN
Kelvin_GND
OSCOUT
OSCIN
OSCOUT
C1
C2
External
Clock Signal
(toggling 0 V to 3.3 V)
(see Note A)
Crystal
(a)
(b)
Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Note B: Kelvin_GND should not be connected to any other GND.
Figure 6-4. Recommended Crystal/Clock Connection
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6.6.1.1.1 Timing Requirements for Main Oscillator
Table 6-9. Timing Requirements for Main Oscillator
Parameter
MIN
50
Type
MAX
200
Unit
ns
tc(OSC)
Cycle time, OSCIN (when using a sine-wave input)
tc(OSC_SQR)
Cycle time, OSCIN, (when input to the OSCIN is a
square wave )
50
200
ns
tw(OSCIL)
tw(OSCIH)
Pulse duration, OSCIN low (when input to the OSCIN
is a square wave)
15
15
ns
ns
Pulse duration, OSCIN high (when input to the OSCIN
is a square wave)
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6.6.1.2 Low Power Oscillator
The Low Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single
macro.
6.6.1.2.1 Features
The main features of the LPO are:
•
•
•
Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #
4 of the Global Clock Module.
Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5
of the Global Clock Module.
Provides a comparison clock for the crystal oscillator failure detection circuit.
BIAS_EN
LFEN
LFLPO
LF_TRIM
Low
Power
Oscillator
HFEN
HFLPO
HF_TRIM
HFLPO_VALID
nPORRST
Figure 6-5. LPO Block Diagram
Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO)
and provides two clock sources: one nominally 80KHz and one nominally 10MHz.
Table 6-10. LPO Specifications
Parameter
MIN
Typical
MAX
Unit
Clock Detection
oscillator fail frequency - lower threshold, using
untrimmed LPO output
1.375
2.4
4.875
MHz
oscillator fail frequency - higher threshold, using
untrimmed LPO output
22
38.4
78
MHz
LPO - HF oscillator
untrimmed frequency
trimmed frequency
5.5
8
9
19.5
11
MHz
MHz
µs
(fHFLPO
)
9.6
startup time from STANDBY (LPO BIAS_EN High for
at least 900µs)
10
cold startup time
900
180
100
µs
kHz
µs
LPO - LF oscillator
untrimmed frequency
36
85
startup time from STANDBY (LPO BIAS_EN High for
at least 900µs)
cold startup time
2000
µs
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6.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
•
Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
•
•
•
Configurable frequency multipliers and dividers.
Built-in PLL Slip monitoring circuit.
Option to reset the device on a PLL slip detection.
6.6.1.3.1 Block Diagram
Figure 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
/NR
/OD
/R
PLLCLK
OSCIN
INTCLK
VCOCLK
post_ODCLK
PLL
/1 to /64
/1 to /8
/1 to /32
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
/NF
/1 to /256
/NR2
/OD2
/R2
PLL2CLK
OSCIN
VCOCLK2
INTCLK2
post_ODCLK2
/1 to /64
PLL#2
/1 to /8
/1 to /32
fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2)
/NF2
/1 to /256
Figure 6-6. PLLx Block Diagram
6.6.1.3.2 PLL Timing Specifications
Table 6-11. PLL Timing Specifications
PARAMETER
MIN
MAX
f(OSC_SQR)
400
UNIT
fINTCLK
PLL1 Reference Clock frequency
1
MHz
MHz
fpost_ODCLK
Post-ODCLK – PLL1 Post-divider input
clock frequency
fVCOCLK
VCOCLK – PLL1 Output Divider (OD) input
clock frequency
150
1
550
MHz
fINTCLK2
PLL2 Reference Clock frequency
f(OSC_SQR)
400
MHz
MHz
fpost_ODCLK2
Post-ODCLK – PLL2 Post-divider input
clock frequency
fVCOCLK2
VCOCLK – PLL2 Output Divider (OD) input
clock frequency
150
550
MHz
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6.6.1.4 External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified below. The external clock sources
are not checked for validity. They are assumed valid when enabled.
Table 6-12. External Clock Timing and Electrical Specifications
Parameter
fEXTCLKx
Description
External clock input frequency
EXTCLK high-pulse duration
EXTCLK low-pulse duration
Low-level input voltage
Min
Max
Unit
MHz
ns
80
tw(EXTCLKIN)H
tw(EXTCLKIN)L
viL(EXTCLKIN)
viH(EXTCLKIN)
6
6
ns
-0.3
2
0.8
V
High-level input voltage
VCCIO + 0.3
V
6.6.2 Clock Domains
6.6.2.1 Clock Domain Descriptions
The table below lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 6-13. Clock Domain Descriptions
Clock Domain Name
Default Clock
Source
Clock Source
Selection Register
Description
HCLK
OSCIN
GHVSRC
•
•
Is disabled through the CDDISx registers bit 1
Used for all system modules including DMA, ESM
GCLK
OSCIN
GHVSRC
•
•
•
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK through the CDDISx registers
bit 0
•
Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GCLK2
OSCIN
GHVSRC
•
•
•
•
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
VCLK
OSCIN
OSCIN
GHVSRC
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the CDDISx registers
bit 2
VCLK2
•
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK through the CDDISx registers
bit 3
VCLK3
VCLK4
OSCIN
OSCIN
GHVSRC
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the CDDISx registers
bit 8
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the CDDISx registers
bit 9
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Table 6-13. Clock Domain Descriptions (continued)
Clock Domain Name
Default Clock
Source
Clock Source
Selection Register
Description
VCLKA1
VCLK
VCLK
VCLK
VCLKASRC
VCLKASRC
VCLKACON1
•
•
Defaults to VCLK as the source
Is disabled through the CDDISx registers bit 4
VCLKA2
•
•
Defaults to VCLK as the source
Is disabled through the CDDISx registers bit 5
VCLKA4_S
•
•
•
Defaults to VCLK as the source
Frequency can be as fast as HCLK frequency
Is disabled through the CDDISx registers bit 11
VCLKA4_DIVR
VCLK
VCLKACON1
•
•
Divided down from the VCLKA4_S using the VCLKA4R field of
the VCLKACON1 register at address 0xFFFFE140
Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or
VCLKA4_S/8
•
•
Default frequency is VCLKA4_S/2
Is disabled separately through the VCLKACON1 register
VCLKA4_DIV_CDDIS bit only if the VCLKA4_S clock is not
disabled
RTICLK
VCLK
RCLKSRC
•
•
Defaults to VCLK as the source
If a clock source other than VCLK is selected for RTICLK, then
the RTICLK frequency must be less than or equal to VCLK/3
–
Application can ensure this by programming the RTI1DIV
field of the RCLKSRC register, if necessary
•
Is disabled through the CDDISx registers bit 6
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6.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figures below.
GCM
0
GCLK, GCLK2 (to CPU)
HCLK (to SYSTEM)
OSCIN
PLL #1 (FMzPLL)
1
X1..256
/1..32
/1..64
/1..8
*
VCLK_peri (VCLK toperipherals on PCR1)
VCLK_sys (VCLK to system modules)
VCLK2 (to N2HETx and HTUx)
/1..16
4
5
80kHz
10MHz
/1..16
/1..16
/1..16
Low Power
Oscillator
VCLK3 (to EMIF)
PLL #2 (FMzPLL)
VCLK4 (to ePWM, eQEP, eCAP)
6
/1..32
*
/1..64 X1..256
/1..8
0
1
3
4
3
7
* the frequency at this node must not
exceed the maximum HCLK specifiation.
EXTCLKIN1
EXTCLKIN2
VCLKA1 (to DCANx)
5
6
7
VCLK
VCLK3
0
1
3
4
5
6
7
VCLKA2 (to FlexRay)
VCLKA4_S (left open)
VCLK
0
1
3
4
5
6
7
VCLK
0
1
3
4
5
6
7
/1, 2, 4, or 8
EMIF
RTICLK (to RTI, DWWD)
VCLK
VCLKA1
VCLK
VCLK2
VCLKA2
VCLKA2
VCLK2
HRP
/1..64
/2,3..224
/1,2..32
/1,2..65536
/1,2..256
/1,2,..4
/1,2,..256
/1,2,..1024
N2HETx
TU
FlexRay
TU
GTUC1,2
FlexRay
Baud
Rate
LRP
/20..25
Prop_seg
Phase_seg2
I2C baud
rate
ECLK
SPI
Baud Rate
ADCLK
LIN / SCI
Baud Rate
Phase_seg1
I2C
Loop
High
Resolution Clock
SPIx,MibSPIx
LIN, SCI
External Clock
MibADCx
FlexRay
EXTCLKIN1
NTU[3]
CAN Baud Rate
DCANx
PLL#2 output
Startof cycle
Macro Tick
NTU[2]
NTU[1]
NTU[0]
N2HETx
RTI
Figure 6-7. Device Clock Domains
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6.6.3 Clock Test Mode
The RM4x platform architecture defines a special mode that allows various clock signals to be brought out
on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured through the CLKTEST register in the system
module.
Table 6-14. Clock Test Mode Options
SEL_ECP_PIN
SEL_GIO_PIN
=
=
SIGNAL ON ECLK
SIGNAL ON N2HET1[12]
CLKTEST[3-0]
CLKTEST[11-8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator Valid Status
Main PLL Valid status
Reserved
Main PLL free-running clock output
Reserved
EXTCLKIN1
Reserved
LFLPO
Reserved
HFLPO
HFLPO Valid status
Secondary PLL Valid Status
Reserved
Secondary PLL free-running clock output
EXTCLKIN2
GCLK
LFLPO
RTI Base
Reserved
VCLKA1
Oscillator Valid status
Oscillator Valid status
Oscillator Valid status
Oscillator Valid status
Reserved
VCLKA2
Reserved
VCLKA4_DIVR
Reserved
VCLKA4_S
Oscillator Valid status
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6.7 Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low
power oscillator (LPO).
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.
6.7.1 Clock Monitor Timings
For more information on LPO and Clock detection, refer to Table 6-10.
upper
threshold
lower
threshold
fail
pass
fail
f[MHz]
1.375
4.875
22
78
Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO
6.7.2 External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
6.7.3 Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
6.7.3.1 Features
•
•
•
•
Takes two different clock sources as input to two independent counter blocks.
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the expected
frequency for the clock under test generates an error signal which is used to interrupt the CPU.
6.7.3.2 Mapping of DCC Clock Source Inputs
Table 6-15. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
oscillator (OSCIN)
high frequency LPO
others
0x5
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Table 6-15. DCC1 Counter 0 Clock Sources (continued)
CLOCK SOURCE [3:0]
CLOCK NAME
0xA
test clock (TCK)
Table 6-16. DCC1 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET1[31]
others
-
0x0
Main PLL free-running clock output
PLL #2 free-running clock output
low frequency LPO
high frequency LPO
reserved
0x1
0x2
0xA
0x3
0x4
0x5
EXTCLKIN1
0x6
EXTCLKIN2
0x7
reserved
0x8 - 0xF
VCLK
Table 6-17. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
others
0xA
oscillator (OSCIN)
test clock (TCK)
Table 6-18. DCC2 Counter 1 Clock Sources
KEY [3:0]
others
0xA
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET2[0]
Reserved
VCLK
-
00x0 - 0x7
0x8 - 0xF
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6.8 Glitch Filters
A glitch filter is present on the following signals.
Table 6-19. Glitch Filter Timing Specifications
Pin
Parameter
MIN
MAX
Unit
nPORRST
tf(nPORRST)
475
2000
ns
Filter time nPORRST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset(1)
nRST
TEST
tf(nRST)
475
475
2000
2000
ns
ns
Filter time nRST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will generate a reset
tf(TEST)
Filter time TEST pin;
pulses less than MIN will be filtered out, pulses greater than
MAX will pass through
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, etc.) without also generating a valid reset signal to the CPU.
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6.9 Device Memory Map
6.9.1 Memory Map Diagram
The figure below shows the device memory map.
Figure 6-9. Memory Map
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and
EEPROM Emulation accesses)
0xF0000000
RESERVED
0x87FFFFFF
0x80000000
EMIF (128MB)
SDRAM
CS0
RESERVED
reserved
CS4
0x6FFFFFFF
0x60000000
0x6C000000
EMIF (32KB * 3)
0x68000000
CS3
CS2
Async RAM
0x64000000
RESERVED
0x200FFFFF
0x20000000
Flash (1MB) (Mirrored Image)
RESERVED
0x0841FFFF
0x08400000
RAM - ECC
RESERVED
0x0801FFFF
0x08000000
RAM (128KB)
RESERVED
Flash (1MB)
0x000FFFFF
0x00000000
Figure 6-10. Memory Map
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash
image is 0x2000 0000.
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6.9.2 Memory Map Table
Table 6-20. Device Memory Map
FRAME ADDRESS RANGE
START END
Memories tightly coupled to the ARM Cortex-R4F CPU
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUAL
SIZE SIZE
MODULE NAME
TCM Flash
CS0
0x0000_0000
0x00FF_FFFF
16MB
1MB
TCM RAM + RAM
ECC
CSRAM0
0x0800_0000
0x0BFF_FFFF
64MB
128KB
Abort
Flash mirror
frame
Mirrored Flash
0x2000_0000
0x20FF_FFFF
16MB
1MB
External Memory Accesses
EMIF Chip Select
2 (asynchronous)
EMIF select 2
EMIF select 3
EMIF select 4
EMIF select 0
0x6000_0000
0x6400_0000
0x6800_0000
0x8000_0000
0x63FF_FFFF
0x67FF_FFFF
0x6BFF_FFFF
0x87FF_FFFF
64MB
32KB
32KB
EMIF Chip Select
3 (asynchronous)
64MB
64MB
Access to "Reserved" space will
generate Abort
EMIF Chip Select
4 (asynchronous)
32KB
EMIF Chip Select
0 (synchronous)
128MB
128MB
Flash Module Bus2 Interface
Customer OTP,
TCM Flash Banks
0xF000_0000
0xF000_1FFF
0xF000_FFFF
8KB
4KB
2KB
Customer OTP,
Bank 7
0xF000_E000
0xF004_0000
8KB
1KB
Customer
OTP–ECC, TCM
Flash Banks
0xF004_03FF
0xF004_1FFF
512B
256B
Customer
OTP–ECC,
Bank 7
0xF004_1C00
1KB
TI OTP, TCM
Flash Banks
0xF008_0000
0xF008_E000
0xF00C_0000
0xF00C_1C00
0xF008_1FFF
0xF008_FFFF
0xF00C_03FF
0xF00C_1FFF
8KB
8KB
1KB
1KB
4KB
2KB
Abort
TI OTP,
Bank 7
TI OTP–ECC,
TCM Flash Banks
512B
256B
TI OTP–ECC,
Bank 7
Bank 7 – ECC
Bank 7
0xF010_0000
0xF020_0000
0xF013_FFFF
0xF03F_FFFF
256KB
2MB
8KB
64KB
Flash Data Space
ECC
0xF040_0000
0xF04F_FFFF
1MB
128KB
EMIF slave interfaces
EMIF Registers
0xFCFF_E800
0xFCFF_E8FF
256B
256B
Abort
SCR5: Enhanced Timer Peripherals
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
eCAP1
0xFCF7_8C00
0xFCF7_8D00
0xFCF7_8E00
0xFCF7_8F00
0xFCF7_9000
0xFCF7_9100
0xFCF7_9200
0xFCF7_9300
0xFCF7_8CFF
0xFCF7_8DFF
0xFCF7_8EFF
0xFCF7_8FFF
0xFCF7_90FF
0xFCF7_91FF
0xFCF7_92FF
0xFCF7_93FF
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
Abort
Abort
Abort
Abort
Abort
Abort
Abort
Abort
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUAL
MODULE NAME
SIZE
SIZE
START
END
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
eQEP1
eQEP2
0xFCF7_9400
0xFCF7_9500
0xFCF7_9600
0xFCF7_9700
0xFCF7_9800
0xFCF7_9900
0xFCF7_9A00
0xFCF7_94FF
0xFCF7_95FF
0xFCF7_96FF
0xFCF7_97FF
0xFCF7_98FF
0xFCF7_99FF
0xFCF7_9AFF
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
Abort
Abort
Abort
Abort
Abort
Abort
Abort
Cyclic Redundancy Checker (CRC) Module Registers
Accesses above 0x200 generate
abort.
CRC
CRC frame
0xFE00_0000
0xFEFF_FFFF
16MB
512B
Peripheral Memories
0xFF0B_FFFF
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
PCS[5]
PCS[6]
PCS[7]
0xFF0A_0000
0xFF0C_0000
0xFF0E_0000
128KB
128KB
128KB
2KB
2KB
2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
0xFF0D_FFFF
0xFF0F_FFFF
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
PCS[13]
PCS[14]
PCS[15]
0xFF1A_0000
0xFF1C_0000
0xFF1E_0000
0xFF1B_FFFF
0xFF1D_FFFF
0xFF1F_FFFF
128KB
128KB
128KB
2KB
2KB
2KB
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Look-Up Table for ADC2 wrapper.
Starts at address offset 0x2000 and
ends at address offset 0x217F. Wrap
around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
PCS[29]
0xFF3A_0000
0xFF3B_FFFF
128KB
MIBADC2 Look-
Up Table
384B
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
MIBADC1 RAM
Look-Up Table for ADC1 wrapper.
Starts at address offset 0x2000 and
ends at address offset 0x217F. Wrap
around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
PCS[31]
0xFF3E_0000
0xFF3F_FFFF
128KB
MibADC1 Look-
Up Table
384B
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET2 RAM
N2HET1 RAM
PCS[34]
PCS[35]
0xFF44_0000
0xFF46_0000
0xFF45_FFFF
0xFF47_FFFF
128KB
128KB
16KB
16KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
HTU2 RAM
HTU1 RAM
PCS[38]
PCS[39]
0xFF4C_0000
0xFF4E_0000
0xFF4D_FFFF
0xFF4F_FFFF
128KB
128KB
1KB
1KB
Abort
Abort
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUAL
MODULE NAME
SIZE
SIZE
START
END
FlexRay TU RAM
PCS[40]
0xFF50_0000
0xFF51_FFFF
128KB
1KB
Abort
Debug Components
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
4KB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
CSCS1
CSCS4
0xFFA0_1000
0xFFA0_4000
0xFFA0_1FFF
0xFFA0_4FFF
4KB
4KB
4KB
4KB
POM
Abort
Peripheral Control Registers
Reads return zeros, writes have no
effect
FTU
HTU1
PS[23]
PS[22]
PS[22]
PS[17]
PS[17]
PS[16]
PS[15]
PS[15]
PS[12]+PS[13]
PS[10]
PS[8]
0xFFF7_A000 512B
0xFFF7_A1FF
0xFFF7_A4FF
0xFFF7_A5FF
0xFFF7_B8FF
0xFFF7_B9FF
0xFFF7_BDFF
0xFFF7_C1FF
0xFFF7_C3FF
0xFFF7_CFFF
0xFFF7_D4FF
0xFFF7_DDFF
0xFFF7_DFFF
0xFFF7_E1FF
0xFFF7_E4FF
0xFFF7_E5FF
0xFFF7_F5FF
0xFFF7_F7FF
0xFFF7_F9FF
0xFFF7_FBFF
0xFFF7_FDFF
512B
256B
256B
256B
256B
256B
512B
512B
2KB
Reads return zeros, writes have no
effect
0xFFF7_A400
0xFFF7_A500
0xFFF7_B800
0xFFF7_B900
0xFFF7_BC00
0xFFF7_C000
0xFFF7_C200
0xFFF7_C800
0xFFF7_D400
0xFFF7_DC00
0xFFF7_DE00
0xFFF7_E000
0xFFF7_E400
0xFFF7_E500
0xFFF7_F400
0xFFF7_F600
0xFFF7_F800
0xFFF7_FA00
0xFFF7_FC00
256B
256B
256B
256B
512B
512B
512B
2KB
Reads return zeros, writes have no
effect
HTU2
Reads return zeros, writes have no
effect
N2HET1
N2HET2
GIO
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
MIBADC1
MIBADC2
FlexRay
I2C
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
256B
512B
512B
512B
256B
256B
512B
512B
512B
512B
512B
256B
512B
512B
512B
256B
256B
512B
512B
512B
512B
512B
Reads return zeros, writes have no
effect
DCAN1
DCAN2
DCAN3
LIN
Reads return zeros, writes have no
effect
PS[8]
Reads return zeros, writes have no
effect
PS[7]
Reads return zeros, writes have no
effect
PS[6]
Reads return zeros, writes have no
effect
SCI
PS[6]
Reads return zeros, writes have no
effect
MibSPI1
SPI2
PS[2]
Reads return zeros, writes have no
effect
PS[2]
Reads return zeros, writes have no
effect
MibSPI3
SPI4
PS[1]
Reads return zeros, writes have no
effect
PS[1]
Reads return zeros, writes have no
effect
MibSPI5
PS[0]
System Modules Control Registers and Memories
DMA RAM
VIM RAM
PPCS0
PPCS2
0xFFF8_0000
0xFFF8_0FFF
4KB
4KB
Abort
Wrap around for accesses to
unimplemented address offsets
between 1KB and 4KB.
0xFFF8_2000
0xFFF8_2FFF
4KB
1KB
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUAL
MODULE NAME
SIZE
SIZE
START
END
Flash Module
PPCS7
0xFFF8_7000
0xFFF8_C000
0xFFF8_7FFF
0xFFF8_CFFF
4KB
4KB
4KB
4KB
Abort
Abort
eFuse Controller
PPCS12
Power
Management
Module (PMM)
PPSE0
PPS0
PPS0
0xFFFF_0000
0xFFFF_E000
0xFFFF_E100
0xFFFF_01FF
0xFFFF_E0FF
0xFFFF_E1FF
512B
256B
256B
512B
256B
256B
Abort
Reads return zeros, writes have no
effect
PCR registers
System Module -
Frame 2 (see
SPNU515)
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
PBIST
STC
PPS1
PPS1
0xFFFF_E400
0xFFFF_E600
0xFFFF_E5FF
0xFFFF_E6FF
512B
256B
512B
256B
Generates address error interrupt, if
enabled
IOMM
Multiplexing
Control Module
Reads return zeros, writes have no
effect
PPS2
0xFFFF_EA00
0xFFFF_EBFF
512B
512B
Reads return zeros, writes have no
effect
DCC1
DMA
PPS3
PPS4
PPS5
PPS5
PPS5
PPS6
PPS6
PPS7
PPS7
PPS7
0xFFFF_EC00
0xFFFF_F000
0xFFFF_F400
0xFFFF_F500
0xFFFF_F600
0xFFFF_F800
0xFFFF_F900
0xFFFF_FC00
0xFFFF_FD00
0xFFFF_FE00
0xFFFF_ECFF
0xFFFF_F3FF
0xFFFF_F4FF
0xFFFF_F5FF
0xFFFF_F6FF
0xFFFF_F8FF
0xFFFF_F9FF
0xFFFF_FCFF
0xFFFF_FDFF
0xFFFF_FEFF
256B
1KB
256B
1KB
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
DCC2
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
256B
Reads return zeros, writes have no
effect
ESM
Reads return zeros, writes have no
effect
CCMR4
Reads return zeros, writes have no
effect
RAM ECC even
RAM ECC odd
RTI + DWWD
VIM Parity
VIM
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
Reads return zeros, writes have no
effect
System Module -
Frame 1 (see
SPNU515)
Reads return zeros, writes have no
effect
PPS7
0xFFFF_FF00
0xFFFF_FFFF
256B
256B
6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an
imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to
handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU’s
program status register (CPSR).
6.9.4 Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
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Table 6-21. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
CRC
Flash Module
Bus2 Interface:
OTP, ECC, Bank
7
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
EMIF Slave
Interface
Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
CPU READ
CPU WRITE
DMA
User/Privilege
User/Privilege
User
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
POM
User
DAP
Privilege
Privilege
Privilege
User
HTU1
HTU2
No
FTU
No
6.9.5 Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
6.9.6 Parameter Overlay Module (POM) Considerations
•
The POM can map onto up to 8MB of the internal or external memory space. The starting address and the size of
the memory overlay are configurable through the POM control registers. Care must be taken to ensure that the
overlay is mapped on to available memory.
•
•
•
ECC must be disabled by software through CP15 in case POM overlay is enabled; otherwise ECC errors will be
generated.
POM overlay must not be enabled when the flash and internal RAM memories are swapped through the MEM
SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
When POM is used to overlay the flash on to internal or external RAM, there is a bus contention possibility when
another master accesses the TCM flash. This results in a system hang.
–
–
–
The POM implements a timeout feature to detect this exact scenario. The timeout needs to be enabled
whenever POM overlay is enabled.
The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global Control
register (POMGLBCTRL, address = 0xFFA04000).
In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO) flag is set in
the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is generated to the CPU. This can
be a prefetch abort for an instruction fetch or a data abort for a data fetch.
–
The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM is set. If so, then
the application can assume that the timeout is caused by a bus contention between the POM transaction and
another master accessing the same memory region. The abort handlers need to clear the TO flag, so that any
further aborts are not misinterpreted as having been caused due to a timeout from the POM.
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6.10 Flash Memory
6.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 6-22. Flash Memory Banks and Sectors
Memory Arrays (or Banks)
Sector
No.
Segment
Low Address
High Address
BANK0 (1MByte)(1)
0
1
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
32K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
128K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
0x0000_0000
0x0000_4000
0x0000_8000
0x0000_C000
0x0001_0000
0x0001_4000
0x0001_8000
0x0002_0000
0x0004_0000
0x0006_0000
0x0008_0000
0x000A_0000
0x000C_0000
0x000E_0000
0xF020_0000
0xF020_4000
0xF020_8000
0xF020_C000
0x0000_3FFF
0x0000_7FFF
0x0000_BFFF
0x0000_FFFF
0x0001_3FFF
0x0001_7FFF
0x0001_FFFF
0x0003_FFFF
0x0005_FFFF
0x0007_FFFF
0x0009_FFFF
0x000B_FFFF
0x000D_FFFF
0x000F_FFFF
0xF020_3FFF
0xF020_7FFF
0xF020_BFFF
0xF020_FFFF
2
3
4
5
6
7
8
9
10
11
12
13
0
BANK7 (64KBytes) for EEPROM emulation(2)(3)
1
2
3
(1) The Flash banks are 144-bit wide bank with ECC support.
(2) The flash bank7 can be programmed while executing code from flash bank0.
(3) Code execution is not allowed from flash bank7.
6.10.2 Main Features of Flash Module
•
•
•
•
•
Support for multiple flash banks for program and/or data storage
Simultaneous read access on a bank while performing program or erase operation on any other bank
Integrated state machines to automate flash erase and program operations
Pipelined mode operation to improve instruction access interface bandwidth
Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
–
Error address is captured for host system debugging
•
Support for a rich set of diagnostic features
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6.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by Single Error Correction Double Error Detection
(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of
instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on
the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is
corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error
through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting
the "X" bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0
MRC p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
;Set 4th bit (‘X’) of PMNC register
The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM
and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN
bits of the System Control coprocessor's Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000
DMB
;Enable ECC checking for ATCM and BTCMs
MCR p15, #0, r1, c1, c0, #1
6.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, refer to Section 5.6.
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6.10.5 Program Flash
Table 6-23. Timing Requirements for Program Flash
Parameter
MIN
NOM
MAX
300
11
Unit
µs
s
tprog(144bit)
tprog(Total)
Wide Word (144bit) programming time
1MByte programming time(1)
40
-40°C to 125°C
0°C to 60°C, for first
25 cycles
2.8
5.5
s
terase(bank0)
Sector/Bank erase time(2)
-40°C to 125°C
0.03
16
4
s
0°C to 60°C, for first
25 cycles
100
ms
twec
Write/erase cycles with 15 year Data Retention -40°C to 125°C
requirement
1000
cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
6.10.6 Data Flash
Table 6-24. Timing Requirements for Data Flash
Parameter
MIN
NOM
MAX
300
660
330
Unit
µs
tprog(144bit)
tprog(Total)
Wide Word (144bit) programming time
40
EEPROM Emulation (bank 7) 64KByte
programming time(1)
-40°C to 125°C
ms
ms
0°C to 60°C, for first
25 cycles
165
terase(bank7)
EEPROM Emulation (bank 7) Sector/Bank
erase time
-40°C to 125°C
0.2
14
8
s
(2)
0°C to 60°C, for first
25 cycles
100
ms
twec
Write/erase cycles with 15 year Data Retention -40°C to 125°C
requirement
100000
cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
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6.11 Tightly Coupled RAM Interface Module
Figure 6-11 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
36 Bit
Upper 32 bitsdata &
4 ECC bits
wide
RAM
Cortex-R4F
TCM BUS
TCRAM
B0
TCM
36 Bit
Interface 1
wide
RAM
72 Bit data + ECC
Lower32 bits data &
4 ECC bits
36 Bit
wide
RAM
Upper 32 bitsdata &
4 ECC bits
B1
TCM
TCM BUS
TCRAM
Interface 2
72 Bit data + ECC
36 Bit
wide
RAM
Lower32 bits data &
4 ECC bits
Figure 6-11. TCRAM Block Diagram
6.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
•
•
•
•
•
•
•
•
Acts as slave to the BTCM interface of the Cortex-R4F CPU
Supports the internal ECC scheme of the CPU by providing 64-bit data and 8-bit ECC code
Monitors CPU Event Bus and generates single or multibit error interrupts
Stores addresses for single and multibit errors
Supports RAM trace module
Provides CPU address bus integrity checking by supporting parity checking on the address bus
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
•
Supports auto-initialization of the RAM banks along with the ECC bits
6.11.2 TCRAM ECC Support
The TCRAM interface passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM.
It also stores the contents of the CPU ECC port in the ECC RAM when the CPU does a write to the RAM.
The TCRAM interface monitors the CPU event bus and provides registers for indicating single/multibit
errors and also for identifying the address that caused the single or multibit error. The event signaling and
the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information see TMS570LS12x/11x Technical Reference Manual (SPNU515).
6.12 Parity Protection for Accesses to Peripheral RAMs
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
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NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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6.13 On-Chip SRAM Initialization and Testing
6.13.1 On-Chip SRAM Self-Test Using PBIST
6.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
6.13.1.2 PBIST RAM Groups
Table 6-25. PBIST RAM Grouping
Test Pattern (Algorithm)
March 13N(1)
two port
(cycles)
March 13N(1)
single port
(cycles)
triple read
slow read
triple read
fast read
Memory
RAM Group
Test Clock
MEM Type
ALGO MASK
0x1
ALGO MASK
0x2
ALGO MASK
0x4
ALGO MASK
0x8
PBIST_ROM
STC_ROM
DCAN1
1
2
ROM CLK
ROM CLK
VCLK
ROM
24578
19586
8194
6530
ROM
3
Dual Port
Dual Port
Dual Port
Single Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
25200
25200
25200
DCAN2
4
VCLK
DCAN3
5
VCLK
ESRAM1(2)
MIBSPI1
MIBSPI3
MIBSPI5
VIM
6
HCLK
VCLK
266280
7
33440
33440
33440
12560
4200
8
VCLK
9
VCLK
10
11
12
13
14
VCLK
MIBADC1
DMA
VCLK
HCLK
VCLK
18960
31680
6480
N2HET1
HTU1
VCLK
FLEXRAY I/O
buffer,
Transient
16(3)
VCLK
Dual Port
75400
Buffer, FTU
Control Packet
FLEXRAY
Message RAM
17(4)
VCLK
Single Port
133160
266280
MIBADC2
N2HET2
HTU2
18
19
20
21
VCLK
VCLK
VCLK
HCLK
Dual Port
Dual Port
Dual Port
Single Port
4200
31680
6480
ESRAM5(5)
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
(2) ESRAM1: Address 0x08000000 - 0x0800FFFF
(3) This RAM group includes the FTU control packet RAM, the FlexRay controller's I/O buffer, and the transient buffer.
(4) This RAM group inclludes the FlexRay controller's message RAM
(5) ESRAM5: Address 0x08010000 - 0x0801FFFF
The PBIST ROM clock frequency is limited to 100MHz, if 100MHz < HCLK <= HCLKmax, or HCLK, if
HCLK <= 100MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
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6.13.2 On-Chip SRAM Auto Initialization
This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware
Initialization mechanism in the System module. This hardware mechanism allows an application to
program the memory arrays with error detection capability to a known state based on their error detection
scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects
the memories that are to be initialized.
For more information on these registers see TMS570LS12x/11x Technical Reference Manual (SPNU515).
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in
Table 6-26.
Table 6-26. Memory Initialization
ADDRESS RANGE
CONNECTING MODULE
MSINENA REGISTER BIT #
BASE ADDRESS
0x08000000
0x08010000
0xFF0A0000
0xFF0C0000
0xFF0E0000
0xFF1A0000
0xFF1C0000
0xFF1E0000
ENDING ADDRESS
0x0800FFFF
0x0801FFFF
0xFF0BFFFF
0xFF0DFFFF
0xFF0FFFFF
0xFF1BFFFF
0xFF1DFFFF
0xFF1FFFFF
RAM (PD#1)
RAM (RAM_PD#1)
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
FlexRay RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
HTU2 RAM
0(1)
0(1)
12(2)
11(2)
7(2)
10
6
5
RAM is not CPU-Addressable
n/a(3)
14
8
0xFF3A0000
0xFF3E0000
0xFF440000
0xFF460000
0xFF4C0000
0xFF4E0000
0xFFF80000
0xFFF82000
0xFF500000
0xFF3BFFFF
0xFF3FFFFF
0xFF45FFFF
0xFF47FFFF
0xFF4DFFFF
0xFF4FFFFF
0xFFF80FFF
0xFFF82FFF
0xFF51FFFF
15
3
16
4
HTU1 RAM
DMA RAM
1
VIM RAM
2
FlexRay TU (FTU) RAM
13
(1) The TCM RAM interface module has separate control bits to select the RAM power domain that is to be auto-initialized.
(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset..
This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization
method. The MibSPIx module must be first brought out of its local reset in order to use the system module auto-initialization method.
(3) Reserved only. The FlexRay RAM has its own initialization mechanism.
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6.14 External Memory Interface (EMIF)
6.14.1 Features
The EMIF includes many features to enhance the ease and flexibility of connecting to external
asynchronous memories or SDRAM devices. The EMIF features includes support for:
•
•
•
•
•
•
•
3 addressable chip select for asynchronous memories of up to 32KB each
1 addressable chip select space for SDRAMs up to 128MB
8 or 16-bit data bus width
Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time
Select strobe mode
Extended Wait mode
Data bus parking
6.14.2 Electrical and Timing Specifications
6.14.2.1 Asynchronous RAM
3
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_nDQM[1:0]
4
8
5
9
6
7
29
30
10
EMIF_nOE
13
12
EMIF_DATA[15:0]
EMIF_nWE
Figure 6-12. Asynchronous Memory Read Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
14
11
EMIF_nOE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 6-13. EMIFnWAIT Read Timing Requirements
15
1
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_nDQM[1:0]
16
18
17
19
21
23
20
24
22
EMIF_nWE
27
26
EMIF_DATA[15:0]
EMIF_nOE
Figure 6-14. Asynchronous Memory Write Timing
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Extended Due to EMIF_WAIT
SETUP
STROBE
STROBE HOLD
EMIF_nCS[3:2]
EMIF_BA[1:0]
EMIF_ADDR[12:0]
EMIF_DATA[15:0]
28
25
EMIF_nWE
EMIF_WAIT
2
2
Asserted
Deasserted
Figure 6-15. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements(1)
NO.
Value
Unit
MIN
Reads and Writes
11
NOM
MAX
E
EMIF clock period
ns
ns
2
tw(EM_WAIT)
Pulse duration, EMIF_nWAIT
assertion and deassertion
2E
Reads
12
13
14
tsu(EMDV-EMOEH)
th(EMOEH-EMDIV)
tsu(EMOEL-EMWAIT)
Setup time, EMIF_DATA[15:0]
valid before EMIFnOE high
9
0
ns
ns
ns
Hold time, EMIF_DATA[15:0]
valid after EMIF_nOE high
Setup Time, EMIF_nWAIT
asserted before end of Strobe
Phase(2)
4E+9
Writes
28
tsu(EMWEL-EMWAIT)
Setup Time, EMIF_nWAIT
asserted before end of Strobe
Phase(2)
4E+14
ns
(1) E = EMIF_CLK period in ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-13 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)
NO
PARAMETER
Value
NOM
UNIT
MIN
MAX
Reads and Writes
1
3
td(TURNAROUND)
Turnaround time
(TA)*E - 4
Reads
(RS+RST+RH)* (RS+RST+RH)* (RS+RST+RH)*
E -3 E + 3
(RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+(
(TA)*E
(TA)*E + 3
ns
tc(EMRCYCLE)
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
ns
ns
E
EWC*16))*E -3
EWC*16))*E
EWC*16))*E +
3
4
5
6
tsu(EMCEL-EMOEL)
Output setup time,
EMIF_nCS[4:2] low to
EMIF_nOE low (SS = 0)
(RS)*E-6
(RS)*E
(RS)*E+3
ns
ns
ns
ns
ns
Output setup time,
EMIF_nCS[4:2] low to
EMIF_nOE low (SS = 1)
-6
0
+3
th(EMOEH-EMCEH)
Output hold time, EMIF_nOE
high to EMIF_nCS[4:2] high (SS
= 0)
(RH)*E -3
-3
(RH)*E
0
(RH)*E + 5
+5
Output hold time, EMIF_nOE
high to EMIF_nCS[4:2] high (SS
= 1)
tsu(EMBAV-EMOEL)
Output setup time,
EMIF_BA[1:0] valid to
EMIF_nOE low
(RS)*E-6
(RS)*E
(RS)*E+3
7
8
th(EMOEH-EMBAIV)
tsu(EMAV-EMOEL)
Output hold time, EMIF_nOE
high to EMIF_BA[1:0] invalid
(RH)*E-3
(RS)*E-6
(RH)*E
(RS)*E
(RH)*E+5
(RS)*E+3
ns
ns
Output setup time,
EMIF_ADDR[12:0] valid to
EMIFnOE low
9
th(EMOEH-EMAIV)
Output hold time, EMIF_nOE
high to EMIF_ADDR[12:0]
invalid
(RH)*E-3
(RH)*E
(RH)*E+5
ns
10
tw(EMOEL)
EMIF_nOE active low width (EW
= 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
ns
ns
ns
EMIF_nOE active low width (EW (RST+(EWC*16 (RST+(EWC*16 (RST+(EWC*16
= 1)
)) *E-3
))*E
)) *E+3
11
29
td(EMWAITH-EMOEH)
tsu(EMDQMV-EMOEL)
Delay time from EMIF_nWAIT
deasserted to EMIF_nOE high
3E+9
4E
4E+20
Output setup time,
EMIF_nDQM[1:0] valid to
EMIF_nOE low
(RS)*E-6
(RH)*E-3
(RS)*E
(RH)*E
(RS)*E+3
(RH)*E+5
30
15
th(EMOEH-EMDQMIV)
Output hold time, EMIF_nOE
high to EMIF_nDQM[1:0] invalid
ns
Writes
(WS+WST+WH (WS+WST+WH (WS+WST+WH
)* E-3 )*E )* E+3
tc(EMWCYCLE)
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
ns
ns
(WS+WST+WH (WS+WST+WH (WS+WST+WH
+( EWC*16))*E +(E WC*16))*E +( EWC*16))*E
-3
+ 3
(1) TA = Turnaround, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information.
(2) E = EMIF_CLK period in ns.
(3) EWC = external wait cycles determined by EMIF_nWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note
that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See
the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information.
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Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO
PARAMETER
Value
NOM
UNIT
MIN
MAX
16
tsu(EMCEL-EMWEL)
th(EMWEH-EMCEH)
tsu(EMDQMV-EMWEL)
Output setup time,
EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 0)
(WS)*E -3
(WS)*E
(WS)*E + 3
ns
Output setup time,
EMIF_nCS[4:2] low to
EMIF_nWE low (SS = 1)
-3
0
+3
ns
ns
ns
ns
17
Output hold time, EMIF_nWE
high to EMIF_nCS[4:2] high (SS
= 0)
(WH)*E-3
-3
(WH)*E
0
(WH)*E+3
+3
Output hold time, EMIF_nWE
high to EMIF_CS[4:2] high (SS =
1)
18
Output setup time,
EMIF_BA[1:0] valid to
EMIF_nWE low
(WS)*E-3
(WS)*E
(WS)*E+3
19
20
th(EMWEH-EMDQMIV)
tsu(EMBAV-EMWEL)
Output hold time, EMIF_nWE
high to EMIF_BA[1:0] invalid
(WH)*E-3
(WS)*E-3
(WH)*E
(WS)*E
(WH)*E+3
(WS)*E+3
ns
ns
Output setup time,
EMIF_BA[1:0] valid to
EMIF_nWE low
21
22
th(EMWEH-EMBAIV)
tsu(EMAV-EMWEL)
Output hold time, EMIF_nWE
high to EMIF_BA[1:0] invalid
(WH)*E-3
(WS)*E-3
(WH)*E
(WS)*E
(WH)*E+3
(WS)*E+3
ns
ns
Output setup time,
EMIF_ADDR[12:0] valid to
EMIF_nWE low
23
24
th(EMWEH-EMAIV)
Output hold time, EMIF_nWE
high to EMIF_ADDR[12:0]
invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
tw(EMWEL)
EMIF_nWE active low width
(EW = 0)
(WST)*E-3
(WST)*E
(WST)*E+3
ns
ns
ns
ns
EMIF_nWE active low width
(EW = 1)
(WST+(EWC*1 (WST+(EWC*1 (WST+(EWC*1
6)) *E-3
6))*E
6)) *E+3
25
26
td(EMWAITH-EMWEH)
tsu(EMDV-EMWEL)
Delay time from EMIF_nWAIT
deasserted to EMIF_nWE high
3E+11
4E
4E+24
Output setup time,
EMIF_DATA[15:0] valid to
EMIF_nWE low
(WS)*E-3
(WS)*E
(WS)*E+3
27
31
th(EMWEH-EMDIV)
Output hold time, EMIF_nWE
high to EMIF_DATA[15:0] invalid
(WH)*E-3
(WH)*E-3
(WH)*E
(WH)*E
(WH)*E+3
(WH)*E+3
ns
ns
tsu(EMDQMV-EMWEL)
Output setup time,
EMIF_nDQM[1:0] valid to
EMIF_nWE low
32
th(EMWEH-EMDQMIV)
Output hold time, EMIF_nWE
high to EMIF_nDQM[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
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6.14.2.2 Synchronous Timing
BASIC SDRAM
1
READ OPERATION
2
2
EMIF_CLK
4
3
5
7
7
EMIF_nCS[0]
6
EMIF_nDQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[12:0]
19
20
2 EM_CLK Delay
18
17
EMIF_DATA[15:0]
EMIF_nRAS
11
12
13
14
EMIF_nCAS
EMIF_nWE
Figure 6-16. Basic SDRAM Read Operation
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMIF_CLK
EMIF_CS[0]
3
5
7
7
9
4
6
EMIF_DQM[1:0]
EMIF_BA[1:0]
8
8
EMIF_ADDR[12:0]
10
EMIF_DATA[15:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
11
12
13
15
16
Figure 6-17. Basic SDRAM Write Operation
Table 6-29. EMIF Synchronous Memory Timing Requirements
NO.
Parameter
tsu(EMIFDV-EM_CLKH)
MIN
MAX
Unit
19
Input setup time, read data valid on
EMIF_DATA[15:0] before EMIF_CLK
rising
2
ns
20
th(CLKH-DIV)
Input hold time, read data valid on
EMIF_DATA[15:0] after EMIF_CLK
rising
2
ns
Table 6-30. EMIF Synchronous Memory Switching Characteristics
NO.
1
Parameter
tc(CLK)
MIN
22
5
MAX
Unit
ns
Cycle time, EMIF clock EMIF_CLK
2
tw(CLK)
Pulse width, EMIF clock EMIF_CLK
high or low
ns
3
4
5
6
7
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMIF_CLK rising to
EMIF_nCS[0] valid
13
13
13
ns
ns
ns
ns
ns
Output hold time, EMIF_CLK rising to
EMIF_nCS[0] invalid
1
1
Delay time, EMIF_CLK rising to
EMIF_nDQM[1:0] valid
Output hold time, EMIF_CLK rising to
EMIF_nDQM[1:0] invalid
Delay time, EMIF_CLK rising to
EMIF_ADDR[12:0] and EMIFBA[1:0]
valid
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Table 6-30. EMIF Synchronous Memory Switching Characteristics (continued)
NO.
Parameter
MIN
MAX
13
13
13
13
7
Unit
8
toh(CLKH-AIV)
Output hold time, EMIF_CLK rising to
EMIF_ADDR[12:0] and EMIF_BA[1:0]
invalid
1
ns
9
td(CLKH-DV)
Delay time, EMIF_CLK rising to
EMIF_DATA[15:0] valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
Output hold time, EMIF_CLK rising to
EMIF_DATA[15:0] invalid
1
1
1
1
1
Delay time, EMIF_CLK rising to
EMIF_nRAS valid
Output hold time, EMIF_CLK rising to
EMIF_nRAS invalid
Delay time, EMIF_CLK rising to
EMIF_nCAS valid
Output hold time, EMIF_CLK rising to
EMIF_nCAS invalid
Delay time, EMIF_CLK rising to
EMIF_nWE valid
Output hold time, EMIF_CLK rising to
EMIF_nWE invalid
Delay time, EMIF_CLK rising to
EMIF_DATA[15:0] tri-stated
Output hold time, EMIF_CLK rising to
EMIF_DATA[15:0] driving
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6.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
6.15.1 VIM Features
The VIM module has the following features:
•
Supports 128 interrupt channels.
Provides programmable priority and enable for interrupt request lines.
–
•
•
Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
Provides two software dispatch mechanisms when the CPU VIC port is not used.
–
–
Index interrupt
Register vectored interrupt
•
Parity protected vector interrupt table against soft errors.
6.15.2 Interrupt Request Assignments
Table 6-31. Interrupt Request Assignments
Modules
Interrupt Sources
Default VIM Interrupt
Channel
ESM
Reserved
RTI
ESM High level interrupt (NMI)
Reserved
0
1
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI timebase interrupt
GIO interrupt A
2
RTI
3
RTI
4
RTI
5
RTI
6
RTI
7
RTI
8
GIO
9
N2HET1
HTU1
MIBSPI1
LIN
N2HET1 level 0 interrupt
HTU1 level 0 interrupt
MIBSPI1 level 0 interrupt
LIN level 0 interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MIBADC1
MIBADC1
DCAN1
SPI2
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
SPI2 level 0 interrupt
FlexRay level 0 interrupt
CRC Interrupt
FlexRay
CRC
ESM
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
SYSTEM
CPU
GIO
GIO interrupt B
N2HET1
HTU1
MIBSPI1
N2HET1 level 1 interrupt
HTU1 level 1 interrupt
MIBSPI1 level 1 interrupt
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Table 6-31. Interrupt Request Assignments (continued)
Modules
Interrupt Sources
Default VIM Interrupt
Channel
LIN
MIBADC1
DCAN1
SPI2
LIN level 1 interrupt
MIBADC1 sw group 2 interrupt
DCAN1 level 1 interrupt
SPI2 level 1 interrupt
MIBADC1 magnitude compare interrupt
FlexRay level 1 interrupt
FTCA interrupt
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
73
74
75
76-79
80
81
82
MIBADC1
FlexRay
DMA
DMA
LFSA interrupt
DCAN2
Reserved
MIBSPI3
MIBSPI3
DMA
DCAN2 level 0 interrupt
Reserved
MIBSPI3 level 0 interrupt
MIBSPI3 level 1 interrupt
HBCA interrupt
DMA
BTCA interrupt
EMIF
AEMIFINT3
DCAN2
Reserved
DCAN1
DCAN3
DCAN2
FPU
DCAN2 level 1 interrupt
Reserved
DCAN1 IF3 interrupt
DCAN3 level 0 interrupt
DCAN2 IF3 interrupt
FPU interrupt
FlexRay TU (FTU)
SPI4
FTU Transfer Status interrupt
SPI4 level 0 interrupt
MibADC2 event group interrupt
MibADC2 sw group1 interrupt
FlexRay T0C interrupt
MIBSPI5 level 0 interrupt
SPI4 level 1 interrupt
DCAN3 level 1 interrupt
MIBSPI5 level 1 interrupt
MibADC2 sw group2 interrupt
FTU Error interrupt
MIBADC2
MIBADC2
FlexRay
MIBSPI5
SPI4
DCAN3
MIBSPI5
MIBADC2
FlexRay TU (FTU)
MIBADC2
DCAN3
FMC
MibADC2 magnitude compare interrupt
DCAN3 IF3 interrupt
FSM_DONE interrupt
FlexRay T1C interrupt
N2HET2 level 0 interrupt
SCI level 0 interrupt
FlexRay
N2HET2
SCI
HTU2
HTU2 level 0 interrupt
I2C level 0 interrupt
I2C
N2HET2
SCI
N2HET2 level 1 interrupt
SCI level 1 interrupt
HTU2
HTU2 level 1 interrupt
Reserved
Reserved
HWAG1
HWAG2
DCC1
HWA_INT_REQ_H
HWA_INT_REQ_H
DCC done interrupt
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Table 6-31. Interrupt Request Assignments (continued)
Modules
Interrupt Sources
Default VIM Interrupt
Channel
DCC2
DCC2 done interrupt
Reserved
83
Reserved
84
PBIST Controller
Reserved
PBIST Done Interrupt
Reserved
85
86-87
88
HWAG1
HWA_INT_REQ_L
HWA_INT_REQ_L
ePWM1 Interrupt
HWAG2
89
ePWM1INTn
ePWM1TZINTn
ePWM2INTn
ePWM2TZINTn
ePWM3INTn
ePWM3TZINTn
ePWM4INTn
ePWM4TZINTn
ePWM5INTn
ePWM5TZINTn
ePWM6INTn
ePWM6TZINTn
ePWM7INTn
ePWM7TZINTn
eCAP1INTn
eCAP2INTn
eCAP3INTn
eCAP4INTn
eCAP5INTn
eCAP6INTn
eQEP1INTn
eQEP2INTn
Reserved
90
ePWM1 Trip Zone Interrupt
ePWM2 Interrupt
91
92
ePWM2 Trip Zone Interrupt
ePWM3 Interrupt
93
94
ePWM3 Trip Zone Interrupt
ePWM4 Interrupt
95
96
ePWM4 Trip Zone Interrupt
ePWM5 Interrupt
97
98
ePWM5 Trip Zone Interrupt
ePWM6 Interrupt
99
100
101
102
103
104
105
106
107
108
109
110
111
112-127
ePWM6 Trip Zone Interrupt
ePWM7 Interrupt
ePWM7 Trip Zone Interrupt
eCAP1 Interrupt
eCAP2 Interrupt
eCAP3 Interrupt
eCAP4 Interrupt
eCAP5 Interrupt
eCAP6 Interrupt
eQEP1 Interrupt
eQEP2 Interrupt
Reserved
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..126 can be used and are offset by 1 address in the
VIM RAM.
NOTE
The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"
interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt
condition is indicated as soon as the device is powered up. This can be ignored if the
EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used
in the application, then the external slave memory must always drive the EMIF_nWAIT signal
such that an interrupt is not caused due to the default pull-up on this signal.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.
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NOTE
The application can change the mapping of interrupt sources to the interrupt channels
through the interrupt channel control registers (CHANCTRLx) inside the VIM module.
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6.16 DMA Controller
The DMA controller is used to transfer data between two locations in the memory map in the background
of CPU operations. Typically, the DMA is used to:
•
•
•
Transfer blocks of data between external and internal data memories
Restructure portions of internal data memory
Continually service a peripheral
6.16.1 DMA Features
•
•
•
•
•
•
•
•
•
•
•
•
•
CPU independent data transfer
One 64-bit master port that interfaces to the RM4x Memory System.
FIFO buffer(4 entries deep and each 64bit wide)
Channel control information is stored in RAM protected by parity
16 channels with individual enable
Channel chaining capability
32 peripheral DMA requests
Hardware and Software DMA requests
8, 16, 32 or 64-bit transactions supported
Multiple addressing modes for source/destination (fixed, increment, offset)
Auto-initiation
Power-management mode
Memory Protection with four configurable memory regions
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6.16.2 Default DMA Request Map
The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The
module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By
default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 6-32. The application must ensure that
only one of these DMA request sources is enabled at any time.
Table 6-32. DMA Request Line Connection
Modules
MIBSPI1
DMA Request Sources
MIBSPI1[1](1)
DMA Request
DMAREQ[0]
DMAREQ[1]
DMAREQ[2]
DMAREQ[3]
DMAREQ[4]
DMAREQ[5]
DMAREQ[6]
DMAREQ[7]
DMAREQ[8]
DMAREQ[9]
DMAREQ[10]
DMAREQ[11]
DMAREQ[12]
DMAREQ[13]
DMAREQ[16]
DMAREQ[17]
DMAREQ[20]
MIBSPI1
MIBSPI1[0](2)
SPI2
SPI2 receive
SPI2
SPI2 transmit
MIBSPI1 / MIBSPI3 / DCAN2
MIBSPI1 / MIBSPI3 / DCAN2
DCAN1 / MIBSPI5
MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3
MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2
DCAN1 IF2 / MIBSPI5[2]
MIBADC1 / MIBSPI5
MIBADC1 event / MIBSPI5[3]
MIBSPI1 / MIBSPI3 / DCAN1
MIBSPI1 / MIBSPI3 / DCAN2
MIBADC1 / I2C / MIBSPI5
MIBADC1 / I2C / MIBSPI5
RTI / MIBSPI1 / MIBSPI3
RTI / MIBSPI1 / MIBSPI3
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2
N2HET1 / N2HET2 / DCAN3
MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1
MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1
MIBADC1 G1 / I2C receive / MIBSPI5[4]
MIBADC1 G2 / I2C transmit / MIBSPI5[5]
RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]
RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]
MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1
MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2
N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3
IF2
N2HET1 / N2HET2 / DCAN3
N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3
IF3
DMAREQ[21]
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1 / MIBSPI3 / MIBSPI5
MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]
MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]
DMAREQ[22]
DMAREQ[23]
DMAREQ[24]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4
receive / MIBSPI5[12]
N2HET1 / N2HET2 / SPI4 / MIBSPI5
N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4
transmit / MIBSPI5[13]
DMAREQ[25]
CRC / MIBSPI1 / MIBSPI3
CRC / MIBSPI1 / MIBSPI3
CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]
CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]
DMAREQ[26]
DMAREQ[27]
DMAREQ[30]
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[14] / MIBSPI3[14] / SCI receive /
MIBSPI5[1](1)
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5
MIBSPI1[15] / MIBSPI3[15] / SCI transmit /
MIBSPI5[0](2)
DMAREQ[31]
(1) Receive DMA when configured in standard SPI mode
(2) Transmit DMA when configured in standard SPI mode
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6.17 Real Time Interrupt Module
The real-time interrupt (RTI) module provides timer functionality for operating systems and for
benchmarking code. The RTI module can incorporate several counters that define the timebases needed
for scheduling an operating system.
The timers also allow you to benchmark certain areas of code by reading the values of the counters at the
beginning and the end of the desired code range and calculating the difference between the values.
In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay
communication cycle. Clock supervision can detect issues on the FlexRay bus with an automatic switch to
an internally generated timebase.
6.17.1 Features
The RTI module has the following features:
•
•
Two independent 64 bit counter blocks
Four configurable compares for generating operating system ticks or DMA requests. Each event can
be driven by either counter block 0 or counter block 1.
•
One counter block usable for application synchronization to FlexRay network including clock
supervision
•
•
Fast enabling/disabling of events
Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block
6.17.2 Block Diagrams
Figure 6-18 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI
module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only
available as time base inputs for the counter block 0.
31
0
Compare
up counter
RTICPUCx
OVLINTx
31
0
=
Up counter
RTIUCx
31
0
RTICLK
To Compare
Unit
Free running counter
RTIFRCx
NTU0
NTU1
NTU2
NTU3
31
0
31
0
Capture
up counter
RTICAUCx
Capture
free running counter
RTICAFRCx
CAP event source 0
CAP event source 1
External
control
Figure 6-18. Counter Block Diagram
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31
Update
compare
0
RTIUDCPy
+
31
0
DMAREQy
INTy
Compare
RTICOMPy
From counter
block 0
=
From counter
block 1
Compare
control
Figure 6-19. Compare Block Diagram
6.17.3 Clock Source Options
The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the
System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.
For more information on clock sources refer to Table 6-8 and Table 6-13.
6.17.4 Network Time Synchronization Inputs
The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which
can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are
connected as shown below.
Table 6-33. Network Time Synchronization Inputs
NTU Input
Source
0
1
2
3
FlexRay Macrotick
FlexRay Start of Cycle
PLL2 Clock output
EXTCLKIN1 clock input
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6.18 Error Signaling Module
The Error Signaling Module (ESM) manages the various error conditions on the RM4x microcontroller. The
error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be
configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an
indicator to an external monitor circuit to put the system into a safe state.
6.18.1 Features
The features of the Error Signaling Module are:
•
128 interrupt/error channels are supported, divided into 3 different groups
–
–
–
64 channels with maskable interrupt and configurable error pin behavior
32 error channels with non-maskable interrupt and predefined error pin behavior
32 channels with predefined error pin behavior only
•
•
•
Error pin to signal severe device failure
Configurable timebase for error signal
Error forcing capability
6.18.2 ESM Channel Assignments
The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order
of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest
severity. The device response to each error is determined by the severity group it is connected to.
Table 6-35 shows the channel assignment for each group.
Table 6-34. ESM Groups
ERROR GROUP
Group1
INTERRUPT CHARACTERISTICS
maskable, low or high priority
non-maskable, high priority
no interrupt generated
INFLUENCE ON ERROR PIN
configurable
fixed
Group2
Group3
fixed
Table 6-35. ESM Channel Assignments
ERROR Condition
Group
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Channels
Reserved
0
1
2
3
4
5
6
MibADC2 - RAM parity error
DMA - MPU configuration violation
DMA - control packet RAM parity error
Reserved
DMA - error on DMA read access, imprecise error
FMC - correctable ECC error: bus1 and bus2 interfaces
(does not include accesses to Bank 7)
N2HET1 - RAM parity error
HTU1/HTU2 - dual-control packet RAM parity error
HTU1/HTU2 - MPU configuration violation
PLL1 - Slip
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
7
8
9
10
11
12
13
14
15
16
17
18
Clock Monitor - oscillator fail
Flexray - message RAM parity error
DMA - error on DMA write access, imprecise error
Flexray TU (FTU) - control packet RAM parity error
VIM RAM - parity error
FTU - MPU configuration violation
MibSPI1 - RAM parity error
MibSPI3 - RAM parity error
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Table 6-35. ESM Channel Assignments (continued)
ERROR Condition
MibADC1 - RAM parity error
Reserved
Group
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Channels
19
20
DCAN1 - RAM parity error
DCAN3 - RAM parity error
DCAN2 - RAM parity error
MibSPI5 - RAM parity error
Reserved
21
22
23
24
25
RAM even bank (B0TCM) - correctable ECC error
CPU - self-test failed
26
27
RAM odd bank (B1TCM) - correctable ECC error
Reserved
28
29
DCC1 - error
30
CCM-R4 - self-test failed
Reserved
31
32
Reserved
33
N2HET2 - RAM parity error
FMC - correctable ECC error (Bank 7 access)
FMC - uncorrectable ECC error (Bank 7 access)
34
35
36
IOMM - Access to unimplemented location in IOMM frame, or write access
detected in unprivileged mode
37
Power domain controller compare error
Power domain controller self-test error
Group1
Group1
Group1
38
39
40
eFuse Controller Error – this error signal is generated when any bit in the eFuse
controller error status register is set. The application can choose to generate an
interrupt whenever this bit is set to service any eFuse controller error conditions.
eFuse Controller - Self Test Error. This error signal is generated only when a self
test on the eFuse controller generates an error condition. When an ECC self test
error is detected, group 1 channel 40 error signal will also be set.
Group1
41
PLL#2 - Slip
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DCC2 - error
Reserved
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
Group1
42
43
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
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Table 6-35. ESM Channel Assignments (continued)
ERROR Condition
Group
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group2
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Channels
Reserved
0
1
Reserved
CCMR4 - dual-CPU lock-step error
2
Reserved
3
FMC - uncorrectable address parity error on accesses to main flash
4
Reserved
5
RAM even bank (B0TCM) - uncorrectable redundant address decode error
6
Reserved
7
RAM odd bank (B1TCM) - uncorrectable redundant address decode error
8
Reserved
9
RAM even bank (B0TCM) - address bus parity error
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
Reserved
RAM odd bank (B1TCM) - address bus parity error
Reserved
Reserved
Reserved
TCM - ECC live lock detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Windowed Watchdog (WWD) violation
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
eFuse Farm - autoload error
Reserved
1
2
RAM even bank (B0TCM) - ECC uncorrectable error
Reserved
3
4
RAM odd bank (B1TCM) - ECC uncorrectable error
Reserved
5
6
FMC - uncorrectable ECC error: ATCM and Flash OTP interfaces
(does not include address parity error and errors on accesses to Bank 7 data
memory)
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Group3
Group3
Group3
Group3
Group3
Group3
8
9
10
11
12
13
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Table 6-35. ESM Channel Assignments (continued)
ERROR Condition
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Group
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Group3
Channels
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
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6.19 Reset / Abort / Error Sources
Table 6-36. Reset/Abort/Error Sources
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
CPU TRANSACTIONS
User/Privilege
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
n/a
n/a
n/a
User/Privilege
User/Privilege
Undefined Instruction Trap
(CPU)(1)
Illegal instruction
User/Privilege
n/a
n/a
MPU access violation
User/Privilege
SRAM
Abort (CPU)
B0 TCM (even) ECC single error (correctable)
User/Privilege
ESM
1.26
3.3
Abort (CPU), ESM =>
nERROR
B0 TCM (even) ECC double error (non-correctable)
User/Privilege
B0 TCM (even) uncorrectable error (for example, redundant
address decode)
User/Privilege
ESM => NMI => nERROR
2.6
B0 TCM (even) address bus parity error
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM
2.10
1.28
B1 TCM (odd) ECC single error (correctable)
Abort (CPU), ESM =>
nERROR
B1 TCM (odd) ECC double error (non-correctable)
User/Privilege
3.5
B1 TCM (odd) uncorrectable error (for example, redundant
address decode)
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM => NMI => nERROR
2.8
B1 TCM (odd) address bus parity error
2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to Bank 7)
User/Privilege
User/Privilege
User/Privilege
ESM
1.6
3.7
2.4
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
Abort (CPU), ESM =>
nERROR
FMC uncorrectable error - address parity error on Bus1
accesses
ESM => NMI => nERROR
FMC correctable error - Accesses to Bank 7
FMC uncorrectable error - Accesses to Bank 7
User/Privilege
User/Privilege
ESM
ESM
1.35
1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
1.13
Memory access permission violation
Memory parity error
User/Privilege
User/Privilege
ESM
ESM
1.2
1.3
High-End Timer Transfer Unit 1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
Memory parity error
ESM
High-End Timer Transfer Unit 2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
Memory parity error
ESM
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
N2HET1
User/Privilege
Memory parity error
Memory parity error
Memory parity error
ESM
ESM
ESM
1.7
N2HET2
User/Privilege
1.34
1.12
FLEXRAY
User/Privilege
FLEXRAY Transfer Unit (FTU)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.16
1.14
Memory parity error
ESM
MIBSPI
MibSPI1 memory parity error
MibSPI3 memory parity error
MibSPI5 memory parity error
User/Privilege
User/Privilege
User/Privilege
ESM
ESM
ESM
1.17
1.18
1.24
MIBADC
MibADC1 Memory parity error
MibADC2 Memory parity error
User/Privilege
User/Privilege
ESM
ESM
1.19
1.1
DCAN
DCAN1 memory parity error
DCAN2 memory parity error
DCAN3 memory parity error
User/Privilege
User/Privilege
User/Privilege
PLL
ESM
ESM
ESM
1.21
1.23
1.22
PLL slip error
User/Privilege
User/Privilege
ESM
ESM
1.10
1.42
PLL #2 slip error
CLOCK MONITOR
User/Privilege
Clock monitor interrupt
ESM
1.11
DCC
DCC1 error
DCC2 error
User/Privilege
ESM
ESM
1.30
1.62
User/Privilege
CCM-R4
Self test failure
Compare failure
User/Privilege
ESM
1.31
2.2
User/Privilege
ESM => NMI => nERROR
VIM
Memory parity error
User/Privilege
ESM
Reset
ESM
ESM
1.15
n/a
VOLTAGE MONITOR
n/a
VMON out of voltage range
CPU Selftest (LBIST) error
Mux configuration error
CPU SELFTEST (LBIST)
User/Privilege
1.27
1.37
PIN MULTIPLEXING CONTROL
User/Privilege
POWER DOMAIN CONTROL
User/Privilege
PSCON compare error
PSCON self-test error
ESM
ESM
1.38
1.39
User/Privilege
eFuse CONTROLLER
User/Privilege
eFuse Controller Autoload error
ESM => nERROR
ESM
3.1
eFuse Controller - Any bit set in the error status register
User/Privilege
1.40
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Table 6-36. Reset/Abort/Error Sources (continued)
ESM HOOKUP
group.channel
ERROR SOURCE
eFuse Controller self-test error
SYSTEM MODE
ERROR RESPONSE
User/Privilege
WINDOWED WATCHDOG
n/a
ESM
1.41
WWD Non-Maskable Interrupt exception
ESM => NMI => nERROR
2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset
n/a
n/a
n/a
n/a
n/a
n/a
Reset
Reset
Reset
Reset
Reset
Reset
n/a
n/a
n/a
n/a
n/a
n/a
Oscillator fail / PLL slip(2)
Watchdog exception
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
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6.20 Digital Windowed Watchdog
This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or an ESM group2 error signal in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
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6.21 Debug Subsystem
6.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Boundary Scan
Boundary Scan I/F
BSR/BSDL
Debug
ROM1
TRST
TMS
TCK
RTCK
Debug APB
TDI
TDO
DAP
Secondary Tap 0
APB Mux
AHB-AP
APB slave
Cortex
R4F
POM
from
to SCR1 via A2A
PCR1/Bridge
Secondary Tap 2
Test Tap 0
AJSM
eFuse Farm
PSCON
Test Tap 1
Figure 6-20. Debug Subsystem Block Diagram
6.21.2 Debug Components Memory Map
Table 6-37. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
4KB
4KB
L SIZE
START
END
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
CSCS1
0xFFA0_0000
0xFFA0_0FFF
4KB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
0xFFA0_1000
0xFFA0_1FFF
4KB
6.21.3 JTAG Identification Code
The JTAG ID code for this device is the same as the device ICEPick Identification Code.
Table 6-38. JTAG ID Code
Silicon Revision
Rev A
ID
0x0B95502F
0x2B95502F
0x3B95502F
Rev B
Rev C
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6.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
Table 6-39. Debug ROM table
ADDRESS
0x000
DESCRIPTION
pointer to Cortex-R4F
Reserved
VALUE
0x0000 1003
0x0000 2002
0x0000 3002
0x0000 4003
0x0000 0000
0x001
0x002
Reserved
0x003
POM
0x004
end of table
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6.21.5 JTAG Scan Interface Timings
Table 6-40. JTAG Scan Interface Timing(1)
No.
Parameter
Min
MAX
Unit
MHz
MHz
ns
fTCK
TCK frequency (at HCLKmax)
12
fRTCK
RTCK frequency (at TCKmax and HCLKmax)
Delay time, TCK to RTCK
10
1
2
3
4
5
td(TCK -RTCK)
tsu(TDI/TMS - RTCKr)
th(RTCKr -TDI/TMS)
th(RTCKr -TDO)
td(TCKf -TDO)
24
12
Setup time, TDI, TMS before RTCK rise (RTCKr)
Hold time, TDI, TMS after RTCKr
26
0
ns
ns
Hold time, TDO after RTCKf
0
ns
Delay time, TDO valid after RTCK fall (RTCKf)
ns
(1) Timings for TDO are specified for a maximum of 50pF load on TDO
TCK
RTCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 6-21. JTAG Timing
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6.21.6 Advanced JTAG Security Module
This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to
the device’s memory content by allowing users to secure the device after programming.
Flash Module Output
OTP Contents
(example)
. . .
. . .
H
L
H
L
H
L
L
H
Unlock By Scan
Register
H
H
L
L
Internal Tie-Offs
(example only)
L
L
H
H
UNLOCK
128-bit comparator
Internal Tie-Offs
(example only)
H
L
L
H
H
L
L
H
Figure 6-22. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The
outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this
combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash
region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the
device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on
the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-
Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of
the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not
accessible in this state.
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6.21.7 Boundary Scan Chain
The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary
scan chain is connected to the Boundary Scan Interface of the ICEPICK module.
Device Pins (conceptual)
TRST
TMS
TCK
TDI
Boundary
Scan
Boundary Scan Interface
TDO
RTCK
TDI
TDO
BSDL
Figure 6-23. Boundary Scan Implementation (Conceptual Diagram)
Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.
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7 Peripheral Information and Electrical Specifications
7.1 Enhanced Translator PWM Modules (ePWM)
Figure 7-1 illustrates the connections between the seven ePWM modules (ePWM1,2,3,4,5,6,7) on the
device.
PINMMR36[25]
NHET1_LOOP_SYNC
EPWMSYNCI
EPWM1A
EPWM1TZINTn
EPWM1INTn
VIM
VIM
EPWM1B
TZ1/2/3n
Mux
Selector
SOCA1, SOCB1
ADC Wrapper
EPWM1
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL Slip
EQEP1 + EQEP2
System Module
CPU
TZ4n
VCLK4, SYS_nRST
EPWM1ENCLK
TBCLKSYNC
TZ5n
TZ6n
Debug Mode Entry
EPWM2/3/4/5/6A
EPWM2/3/4/5/6B
EPWM2/3/4/5/6TZINTn
EPWM2/3/4/5/6INTn
VIM
VIM
TZ1/2/3n
ADC Wrapper
Mux
Selector
SOCA2/3/4/5/6
SOCB2/3/4/5/6
EPWM
2/3/4/5/6
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL Slip
EQEP1 + EQEP2
System Module
CPU
TZ4n
VCLK4, SYS_nRST
EPWM2/3/4/5/6ENCLK
TBCLKSYNC
TZ5n
TZ6n
Debug Mode Entry
EPWM7A
EPWM7TZINTn
EPWM7INTn
VIM
VIM
EPWM7B
TZ1/2/3n
Mux
Selector
SOCA7, SOCB7
ADC Wrapper
EPWM
7
VBus32
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL SLip
EQEP1 + EQEP2
System Module
CPU
TZ4n
TZ5n
TZ6n
VCLK4, SYS_nRST
EPWM7ENCLK
TBCLKSYNC
Debug Mode Entry
Pulse
Stretch,
8 VCLK4
cycles
EPWMSYNCO
ECAP1
VBus32 / VBus32DP
ECAP
1
ECAP1INTn
VIM
Figure 7-1. ePWMx Module Interconnections
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7.1.1 ePWM Clocking and Reset
Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active low, the clock
enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When
SYS_nRST goes in-active high, the state of clock enable is respected.
Table 7-1. ePWMx Clock Enable Control
ePWM Module Instance
ePWM1
Control Register to Enable Clock
PINMMR37[8]
Default Value
1
1
1
1
1
1
1
ePWM2
PINMMR37[16]
ePWM3
PINMMR37[24]
ePWM4
PINMMR38[0]
ePWM5
PINMMR38[8]
ePWM6
PINMMR38[16]
ePWM7
PINMMR38[24]
The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means
that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can
choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control
register bit.
7.1.2 Synchronization of ePWMx Time Base Counters
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-1 shows the
synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or
ignore the synchronization input. Refer to the ePWM chapter in the TMS570LS12x/11x Technical
Reference Manual (SPNU515) for more information.
7.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented
as shown in Figure 7-2.
N2HET1_LOOP_SYNC
EXT_LOOP_SYNC
N2HET1
N2HET2
ePWM1
2 VCLK4 cycles
Pulse Strength
SYNCI
ePWM1_SYNCI
ePWM1_SYNCI_SYNCED
ePWM1_SYNCI_FILTERED
PINMMR36[25]
PINMMR47[8,9,10]
Figure 7-2. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules
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7.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is implemented as PINMMR37 register bit 1.
When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default
condition.
When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.
For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must
be set identically. The proper procedure for enabling the ePWM clocks is as follows:
1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-1.
2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Configure TBCLKSYNC = 1.
7.1.5 ePWM Synchronization with External Devices
The output sync from EPWM1 Module is also exported to a device output terminal so that multiple devices
can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being exported
on the terminal as the EPWM1SYNCO signal.
7.1.6 ePWM Trip Zones
The ePWMx modules have six trip zone inputs each. These are active-low signals. The application can
control the ePWMx module response to each of the trip zone input separately. The timing requirements
from the assertion of the trip zone inputs to the actual response are specified in Section 7.1.8.
7.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n
These three trip zone inputs are driven by external circuits and are connected to device-level inputs.
These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-
synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter
before connecting to the ePWMx. By default, the trip zone inputs are asynchronously connected to the
ePWMx modules.
Table 7-2. Connection to ePWMx Modules for Device-Level Trip Zone Inputs
Trip Zone Input
Control for
Asynchronous
Control for Double-Synchronized
Connection to ePWMx
Control for Double-Synchronized and Filtered
Connection to ePWMx
Connection to ePWMx
TZ1n
TZ2n
TZ3n
PINMMR46[16] = 1
PINMMR46[24] = 1
PINMMR47[0] = 1
PINMMR46[16] = 0 AND
PINMMR46[17] = 1
PINMMR46[16] = 0 AND PINMMR46[17] = 0
AND PINMMR46[18] = 1
PINMMR46[24] = 0 AND
PINMMR46[25] = 1
PINMMR46[24] = 0 AND PINMMR46[25] = 0
AND PINMMR46[26] = 1
PINMMR47[0] = 0 AND PINMMR47[1] PINMMR47[0] = 0 AND PINMMR47[1] = 0 AND
= 1 PINMMR47[2] = 1
7.1.6.2 Trip Zone TZ4n
This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device.
Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control
registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on
the application’s requirements.
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Table 7-3. TZ4n Connections for ePWMx Modules
ePWMx
Control for TZ4n =
not(EQEP1ERR OR
EQEP2ERR)
Control for TZ4n = not(EQEP1ERR)
Control for TZ4n = not(EQEP2ERR)
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
PINMMR41[0] = 1
PINMMR41[8]
PINMMR41[16]
PINMMR41[24]
PINMMR42[0]
PINMMR42[8]
PINMMR42[16]
PINMMR41[0] = 0 AND PINMMR41[1] PINMMR41[0] = 1 AND PINMMR41[1] = 0 AND
= 1 PINMMR41[2] = 1
PINMMR41[8] = 0 AND PINMMR41[9] PINMMR41[8] = 1 AND PINMMR41[9] = 0 AND
= 1
PINMMR41[10] = 1
PINMMR41[16] = 0 AND
PINMMR41[17] = 1
PINMMR41[16] = 1 AND PINMMR41[17] = 0
AND PINMMR41[18] = 1
PINMMR41[24] = 0 AND
PINMMR41[25] = 1
PINMMR41[24] = 1 AND PINMMR41[25] = 0
AND PINMMR41[26] = 1
PINMMR42[0] = 0 AND PINMMR42[1] PINMMR42[0] = 1 AND PINMMR42[1] = 0 AND
= 1 PINMMR42[2] = 1
PINMMR42[8] = 0 AND PINMMR42[9] PINMMR42[8] = 1 AND PINMMR42[9] = 0 AND
= 1
PINMMR42[10] = 1
PINMMR42[16] = 0 AND
PINMMR42[17] = 1
PINMMR42[16] = 1 AND PINMMR42[17] = 0
AND PINMMR42[18] = 1
7.1.6.3 Trip Zone TZ5n
This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted
whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip
zone input for each ePWMx module in order to prevent the external system from going out of control when
the device clocks are not within expected range (system running at limp clock).
The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the
system module. These are level signals are set until cleared by the application.
7.1.6.4 Trip Zone TZ6n
This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,
the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the
external system from going out of control when the CPU is stopped.
7.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
A special scheme is implemented in order to select the actual signal used for triggering the start of
conversion on the two ADCs on this device. This scheme is defined in Section 7.4.2.3.
7.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
Table 7-4. ePWMx Timing Requirements
PARAMETER
TEST CONDITIONS
Asynchronous
MIN
MAX
UNIT
cycles
cycles
cycles
tw(SYNCIN)
Synchronization input pulse width
2 tc(VCLK4)
2 tc(VCLK4)
Synchronous
Synchronous, with input 2 tc(VCLK4) + filter width
filter
Table 7-5. ePWMx Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
33.33
MAX
UNIT
ns
tw(PWM)
Pulse duration, ePWMx output high or low
tw(SYNCOUT Synchronization Output Pulse Width
8 tc(VCLK4)
cycles
)
td(PWM)tza
Delay time, trip input active to PWM forced high,
no pin load
25
ns
OR Delay time, trip input active to PWM forced
low
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Table 7-5. ePWMx Switching Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(TZ-
Delay time, trip input active to PWM Hi-Z
20
ns
PWM)HZ
Table 7-6. ePWMx Trip-Zone Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(TZ)
Pulse duration, TZn input low
Asynchronous
2 * HSPCLKDIV *
CLKDIV * tc(VCLK4)
ns
(1)
Synchronous
2 tc(VCLK4)
ns
ns
Synchronous, with input
filter
8 tc(VCLK4)
(1) Refer to the ePWM chapter of the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information on the clock divider
fields HSPCLKDIV and CLKDIV.
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7.2 Enhanced Capture Modules (eCAP)
Figure 7-3 shows how the eCAP modules are interconnected on this microcontroller.
EPWM1SYNCO
ECAP1SYNCI
ECAP1
ECAP1INTn
ECAP1
VIM
VBus32
VCLK4, SYS_nRST
ECAP1ENCLK
ECAP1SYNCO
ECAP2SYNCI
ECAP2
ECAP
ECAP2INTn
VIM
2/3/4/5
VBus32
VCLK4, SYS_nRST
ECAP2ENCLK
ECAP2SYNCO
ECAP6
ECAP
6
VBus32
VIM
ECAP6INTn
VCLK4, SYS_nRST
ECAP6ENCLK
Figure 7-3. eCAP Module Connections
7.2.1 Clock Enable Control for eCAPx Modules
Each of the ECAPx modules have a clock enable (ECAPxENCLK). These signals need to be generated
from a device-level control register. When SYS_nRST is active low, the clock enables are ignored and the
ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the
state of clock enable is respected.
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Table 7-7. eCAPx Clock Enable Control
ePWM Module Instance
Control Register to Enable Clock
PINMMR39[0]
Default Value
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
1
1
1
1
1
1
PINMMR39[8]
PINMMR39[16]
PINMMR39[24]
PINMMR40[0]
PINMMR40[8]
The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that
the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose
to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register
bit.
7.2.2 PWM Output Capability of eCAPx
When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM
output. This is called the auxiliary PWM (APWM) mode of operation of the eCAP modules. Refer to the
eCAP chapter of the TMS570LS12x/11x Technical Reference Manual (SPNU515) for more information.
7.2.3 Input Connection to eCAPx Modules
The input connection to each of the eCAP modules can be selected between a double-VCLK4-
synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-8.
Table 7-8. Device-Level Input Connection to eCAPx Modules
Input Signal
Control for Double-Synchronized Connection to
eCAPx
Control for Double-Synchronized and Filtered
Connection to eCAPx
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
PINMMR43[0] = 1
PINMMR43[8] = 1
PINMMR43[16] = 1
PINMMR43[24] = 1
PINMMR44[0] = 1
PINMMR44[8] = 1
PINMMR43[0] = 0 AND PINMMR43[1] = 1
PINMMR43[8] = 0 AND PINMMR43[9] = 1
PINMMR43[16] = 0 AND PINMMR43[17] = 1
PINMMR43[24] = 0 AND PINMMR43[25] = 1
PINMMR44[0] = 0 AND PINMMR44[1] = 1
PINMMR44[8] = 0 AND PINMMR44[9] = 1
7.2.4 Enhanced Capture Module (eCAP) Timings
Table 7-9. eCAPx Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
MAX
UNIT
cycles
cycles
tw(CAP)
Capture input pulse width
Synchronous
2 tc(VCLK4)
Synchronous, with input 2 tc(VCLK4) + filter width
filter
Table 7-10. eCAPx Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
UNIT
tw(APWM)
Pulse duration, APWMx output high or low
20
ns
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7.3 Enhanced Quadrature Encoder (eQEP)
Figure 7-4 shows the eQEP module interconnections on the device.
VBus32
EQEP1A
EQEP1B
EQEP1ENCLK
VCLK4
SYS_nRST
EQEP1I
EQEP1IO
EQEP1IOE
EQEP1
Module
EPWM1/../7
EQEP1INTn
EQEP1ERR
VIM
EQEP1S
EQEP1SO
EQEP1SOE
IO
Mux
VBus32
EQEP2A
EQEP2B
EQEP2ENCLK
VCLK4
SYS_nRST
EQEP2I
EQEP2IO
EQEP2IOE
EQEP2
Module
EQEP2INTn
EQEP2ERR
VIM
Connection
Selection
Mux
EQEP2S
EQEP2SO
EQEP2SOE
Figure 7-4. eQEP Module Interconnections
7.3.1 Clock Enable Control for eQEPx Modules
Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST
is active low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper
state. When SYS_nRST goes in-active high, the state of clock enable is respected.
Table 7-11. eQEPx Clock Enable Control
ePWM Module Instance
eQEP1
Control Register to Enable Clock
PINMMR40[16]
Default Value
1
1
eQEP2
PINMMR40[24]
The default value of the control registers to enable the clocks to the eQEPx modules is 1. This means that
the VCLK4 clock connections to the eQEPx modules are enabled by default. The application can choose
to gate off the VCLK4 clock to any eQEPx module individually by clearing the respective control register
bit.
7.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexor. This multiplexor is defined in Table 7-3. As shown in Figure 7-1, the output of this selection
multiplexor is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection
allows the application to define the response of each ePWMx module on a phase error indicated by the
eQEP modules.
7.3.3 Input Connections to eQEPx Modules
The input connections to each of the eQEP modules can be selected between a double-VCLK4-
synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.
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Table 7-12. Device-Level Input Connection to eCAPx Modules
Input Signal
Control for Double-Synchronized Connection to
eQEPx
Control for Double-Synchronized and Filtered
Connection to eQEPx
eQEP1A
eQEP1B
eQEP1I
eQEP1S
eQEP2A
eQEP2B
eQEP2I
eQEP2S
PINMMR44[16] = 1
PINMMR44[24] = 1
PINMMR45[0] = 1
PINMMR45[8] = 1
PINMMR45[16] = 1
PINMMR45[24] = 1
PINMMR46[0] = 1
PINMMR46[8] = 1
PINMMR44[16] = 0 and PINMMR44[17] = 1
PINMMR44[24] = 0 and PINMMR44[25] = 1
PINMMR45[0] = 0 and PINMMR45[1] = 1
PINMMR45[8] = 0 and PINMMR45[9] = 1
PINMMR45[16] = 0 and PINMMR45[17] = 1
PINMMR45[24] = 0 and PINMMR45[25] = 1
PINMMR46[0] = 0 and PINMMR46[1] = 1
PINMMR46[8] = 0 and PINMMR46[9] = 1
7.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
Table 7-13. eQEPx Timing Requirements
PARAMETER
QEP input period
TEST CONDITIONS
MIN
MAX
UNIT
cycles
cycles
tw(QEPP)
Synchronous
2 tc(VCLK4)
Synchronous, with input 2 tc(VCLK4) + filter width
filter
tw(INDEXH)
QEP Index Input High Time
QEP Index Input Low Time
Synchronous
2 tc(VCLK4)
cycles
cycles
Synchronous, with input 2 tc(VCLK4) + filter width
filter
tw(INDEXL)
Synchronous
2 tc(VCLK4)
cycles
cycles
Synchronous, with input 2 tc(VCLK4) + filter width
filter
tw(STROBH) QEP Strobe Input High Time
tw(STROBL) QEP Strobe Input Low Time
Synchronous
2 tc(VCLK4)
cycles
cycles
Synchronous, with input 2 tc(VCLK4) + filter width
filter
Synchronous
2 tc(VCLK4)
cycles
cycles
Synchronous, with input 2 tc(VCLK4) + filter width
filter
Table 7-14. eQEPx Switching Characteristics
PARAMETER
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4 tc(VCLK4)
6 tc(VCLK4)
cycles
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
7.4 Multibuffered 12bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.
Table 7-15. MibADC Overview
Description
Resolution
Value
12 bits
Assured
Monotonic
Output conversion code
00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]
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7.4.1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
12-bit resolution
ADREFHI and ADREFLO pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600ns Minimum at 30MHz ADCLK
One memory region per conversion group is available (event, group 1, group 2)
Allocation of channels to conversion groups is completely programmable
Supports flexible channel conversion order
Memory regions are serviced either by interrupt or by DMA
Programmable interrupt threshold counter is available for each group
Programmable magnitude threshold interrupt for each group for any one channel
Option to read either 8-bit, 10-bit or 12-bit values from memory regions
Single or continuous conversion modes
Embedded self-test
Embedded calibration logic
Enhanced power-down mode
–
Optional feature to automatically power down ADC core when no conversion is in progress
•
External event pin (ADxEVT) programmable as general-purpose I/O
7.4.2 Event Trigger Options
The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3
groups can be configured to be hardware event-triggered. In that case, the application can select from
among 8 event sources to be the trigger for a group's conversions.
7.4.2.1 MIBADC1 Event Trigger Hookup
Table 7-16. MIBADC1 Event Trigger Hookup
Trigger Event Signal
Group Source
Select, G1SRC,
G2SRC or
EVSRC
PINMMR30[0] = 0 and PINMMR30[1] = 1
Event #
PINMMR30[0] = 1
(default)
Control for
Option B
Option A
Control for
Option B
Option A
000
001
010
1
2
3
AD1EVT
N2HET1[8]
N2HET1[10]
AD1EVT
—
PINMMR30[8] = 1
—
AD1EVT
—
PINMMR30[8] = 0
and
PINMMR30[9] = 1
N2HET2[5]
ePWM_B
N2HET1[27]
N2HET1[27]
—
PINMMR30[16] =
RTI Compare 0
Interrupt
RTI Compare 0
Interrupt
PINMMR30[16] =
1
0 and
PINMMR30[17] =
1
011
100
101
4
5
6
ePWM_A1
N2HET1[17]
N2HET2[1]
N2HET1[12]
N2HET1[14]
N2HET1[17]
N2HET1[19]
—
—
PINMMR30[24] =
PINMMR30[24] =
1
0 and
PINMMR30[25] =
1
PINMMR31[0] = 0
and
PINMMR31[1] = 1
110
111
7
8
GIOB[0]
GIOB[1]
N2HET1[11]
N2HET2[13]
PINMMR31[0] = 1
ePWM_A2
ePWM_AB
PINMMR31[8] = 0
and
PINMMR31[9] = 1
PINMMR32[16] =
1
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NOTE
If ADEVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC1
module trigger input is made from the output side of the input buffer. This way, a trigger
condition can be generated either by configuring the function as output onto the pad (through
the mux control), or by driving the function from an external trigger source as input. If the
mux control module is used to select different functionality instead of the ADEVT, N2HET1[x]
or GIOB[x] signals, then care must be taken to disable these signals from triggering
conversions; there is no multiplexing on the input connections.
If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13],
N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection
to the ADC is made directly from the N2HET or ePWM module outputs. As a result,
the ADC can be triggered without having to enable the signal from being output on
a device terminal.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.4.2.2 MIBADC2 Event Trigger Hookup
Table 7-17. MIBADC2 Event Trigger Hookup
Trigger Event Signal
Group Source
Select, G1SRC,
G2SRC or
PINMMR30[0] = 0 and PINMMR30[1] = 1
Event #
PINMMR30[0] = 1
(default)
Control for
Option B
Option A
Control for
Option B
Option A
EVSRC
000
001
010
011
1
2
3
4
AD2EVT
N2HET1[8]
N2HET1[10]
AD2EVT
—
AD2EVT
—
PINMMR31[16] =
PINMMR31[16] =
1
0 and
PINMMR31[17] =
1
N2HET2[5]
ePWM_B
N2HET1[27]
—
N2HET1[27]
ePWM_A1
—
PINMMR31[24] =
RTI Compare 0
Interrupt
RTI Compare 0
Interrupt
PINMMR31[24] =
1
0 and
PINMMR31[25] =
1
100
101
5
6
N2HET1[12]
N2HET1[14]
N2HET1[17]
N2HET1[19]
—
N2HET1[17]
N2HET2[1]
—
PINMMR32[0] = 0
and
PINMMR32[0] = 1
PINMMR32[1] = 1
PINMMR32[8] = 0
and
PINMMR32[9] = 1
110
111
7
8
GIOB[0]
GIOB[1]
N2HET1[11]
N2HET2[13]
PINMMR32[8] = 1
ePWM_A2
ePWM_AB
PINMMR32[16] =
PINMMR32[16] =
1
0 and
PINMMR32[17] =
1
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NOTE
If AD2EVT, N2HET1 or GIOB is used as a trigger source, the connection to the MibADC2
module trigger input is made from the output side of the input buffer. This way, a trigger
condition can be generated either by configuring the function as output onto the pad (through
the mux control), or by driving the function from an external trigger source as input. If the
mux control module is used to select different functionality instead of the AD2EVT,
N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from
triggering conversions; there is no multiplexing on the input connections.
If ePWM_B, ePWM_S2, ePWM_AB, N2HET2[5], N2HET2[1], N2HET2[13],
N2HET1[11], N2HET1[17] or N2HET1[19] is used to trigger the ADC the connection
to the ADC is made directly from the N2HET or ePWM module outputs. As a result,
the ADC can be triggered without having to enable the signal from being output on
a device terminal.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
As shown in Figure 7-5, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are used
to generate 4 signals – ePWM_B, ePWM_A1, ePWM_A2 and ePWM_AB, that are available to trigger the
ADC based on the application requirement.
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SOCAEN, SOCBEN bits
inside ePWMx modules
Controlled by PINMMR
EPWM1SOCA
EPWM1
module
EPWM1SOCB
EPWM2SOCA
EPWM2SOCB
EPWM2
module
EPWM3SOCA
EPWM3SOCB
EPWM3
module
EPWM4SOCA
EPWM4SOCB
EPWM4
module
EPWM5SOCA
EPWM5SOCB
EPWM5
module
EPWM6SOCA
EPWM6SOCB
EPWM6
module
EPWM7SOCA
EPWM7SOCB
EPWM7
module
ePWM_B ePWM_A1 ePWM_A2 ePWM_AB
Figure 7-5. ADC Trigger Source Generation from ePWMx
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Table 7-18. Control Bit to SOC Output
Control Bit
PINMMR35[0]
PINMMR35[8]
PINMMR35[16]
PINMMR35[24]
PINMMR36[0]
PINMMR36[8]
PINMMR36[16]
SOC Output
SOC1A_SEL
SOC2A_SEL
SOC3A_SEL
SOC4A_SEL
SOC5A_SEL
SOC6A_SEL
SOC7A_SEL
The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-5.
The logic equations for the 4 outputs from the combinational logic shown in Figure 7-5 are:
ePWM_
SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B
B =
ePWM_
[ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or
A1 =
[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or
[ SOC7A and not(SOC7A_SEL) ]
ePWM_
[ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or
A2 =
[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or
[ SOC7A and SOC7A_SEL ]
ePWM_
ePWM_B or ePWM_A2
AB =
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7.4.3 ADC Electrical and Timing Specifications
Table 7-19. MibADC Recommended Operating Conditions
Parameter
MIN
MAX
Unit
V
(1)
ADREFHI
ADREFLO
VAI
A-to-D high-voltage reference source
A-to-D low-voltage reference source
Analog input voltage
ADREFLO
VCCAD
ADREFHI
ADREFHI
2
(1)
VSSAD
V
ADREFLO
- 2
V
IAIK
Analog input clamp current(2)
mA
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 7-20. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
Parameter
Description/Conditions
MIN
Nom
MAX
Unit
Rmux
Analog input mux on-
resistance
See Figure 7-6
250
Ω
Rsamp
ADC sample switch on-
resistance
See Figure 7-6
250
Ω
Cmux
Csamp
IAIL
Input mux capacitance
See Figure 7-6
See Figure 7-6
16
13
200
200
500
250
250
1000
2
pF
pF
nA
nA
nA
nA
nA
nA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
ADC sample capacitance
Analog off-state input
leakage current
VCCAD = 3.6V
maximum
V
SSAD ≤ VIN < VSSAD + 100mV
-300
-200
-200
-1000
-250
-250
-8
VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV
VCCAD - 200mV < VIN ≤ VCCAD
IAIL
Analog off-state input
leakage current
VCCAD = 5.5V
maximum
VSSAD ≤ VIN < VSSAD + 300mV
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV
VCCAD - 300mV < VIN ≤ VCCAD
(1)
IAOSB1
ADC1 Analog on-state input VCCAD = 3.6V
bias current maximum
VSSAD ≤ VIN < VSSAD + 100mV
VSSAD + 100mV < VIN < VCCAD - 200mV
VCCAD - 200mV < VIN < VCCAD
-4
2
-4
12
2
(1)
IAOSB2
ADC2 Analog on-state input VCCAD = 3.6V
bias current maximum
VSSAD ≤ VIN < VSSAD + 100mV
-7
VSSAD + 100mV ≤ VIN ≤ VCCAD - 200mV
VCCAD - 200mV < VIN ≤ VCCAD
-4
2
-4
10
3
(1)
IAOSB1
ADC1 Analog on-state input VCCAD = 5.5V
bias current maximum
VSSAD ≤ VIN < VSSAD + 300mV
-10
-5
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV
VCCAD - 300mV < VIN ≤ VCCAD
3
-5
14
3
(1)
IAOSB2
ADC2 Analog on-state input VCCAD = 5.5V
bias current
VSSAD ≤ VIN < VSSAD + 300mV
-8
maximum
VSSAD + 300mV ≤ VIN ≤ VCCAD - 300mV
VCCAD - 300mV < VIN ≤ VCCAD
-5
3
-5
12
3
IADREFHI
ICCAD
ADREFHI input current
Static supply current
ADREFHI = VCCAD, ADREFLO = VSSAD
Normal operating mode
15
5
ADC core in power down mode
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSB1 + IAOSB2
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Rext
Pin
Rmux
Smux
VS1
IAOSB
Cext
On-State
Bias Current
Smux
Rext
Pin
Rmux
VS2
IAIL
Cext
IAIL
IAIL
Off-State
Leakages
Smux
Rext
Pin
Rmux
Ssamp
Rsamp
VS24
IAIL
Csamp
Cmux
Cext
IAIL
IAIL
Figure 7-6. MibADC Input Equivalent Circuit
Table 7-21. MibADC Timing Specifications
Parameter
Cycle time, MibADC clock
MIN
0.033
0.2
NOM
MAX
Unit
µs
(1)
tc(ADCLK)
(2)
td(SH)
Delay time, sample and hold
time
µs
td(PU-ADV)
Delay time from ADC power on
until first input can be sampled
1
µs
12-bit mode
td©)
Delay time, conversion time
0.4
0.6
µs
µs
(3)
td(SHC)
Delay time, total sample/hold
and conversion time
10-bit mode
td©)
Delay time, conversion time
0.33
0.53
µs
µs
(3)
td(SHC)
Delay time, total sample/hold
and conversion time
(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits
4:0.
(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each
conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as
well as the ADC’s internal impedance.
(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, for
example, the prescale settings.
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Table 7-22. MibADC Operating Characteristics Over Full Ranges of Recommended Operating
Conditions(1)(2)
Parameter
Description/Conditions
MIN
Type
MAX
Unit
CR
Conversion range over ADREFHI - ADREFLO
3
5.5
V
which specified
accuracy is
maintained
ZSET
Zero Scale Offset
Difference between the first ideal transition
(from code 000h to 001h) and the actual
transition
10-bit
mode
1
2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
12-bit
mode
FSET
EDNL
EINL
Full Scale Offset
Difference between the range of the
measured code transitions (from first to last)
and the range of the ideal code transitions
10-bit
mode
2
12-bit
mode
3
Differential
nonlinearity error
Difference between the actual step width and 10-bit
the ideal value. (See Figure 7-7)
± 1.5
± 2
± 2
± 2
± 2
± 4
mode
12-bit
mode
Integral nonlinearity
error
Maximum deviation from the best straight line 10-bit
through the MibADC. MibADC transfer
characteristics, excluding the quantization
error.
mode
12-bit
mode
ETOT
Total unadjusted error Maximum value of the difference between an 10-bit
analog value and the ideal midstep value.
mode
12-bit
mode
(1) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode
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7.4.4 Performance (Accuracy) Specifications
7.4.4.1 MibADC Nonlinearity Errors
The differential nonlinearity error shown in Figure 7-7 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
0 ... 101
0 ... 100
0 ... 011
Differential Linearity
Error (–½ LSB)
1 LSB
0 ... 010
Differential Linearity
Error (–½ LSB)
0 ... 001
0 ... 000
1 LSB
0
1
2
3
4
5
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-7. Differential Nonlinearity (DNL) Error
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The integral nonlinearity error shown in Figure 7-8 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
0 ... 101
0 ... 100
0 ... 011
0 ... 010
0 ... 001
0 ... 000
Actual
Transition
At Transition
011/100
(–½ LSB)
End-Point Lin. Error
At Transition
001/010 (–1/4 LSB)
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-8. Integral Nonlinearity (INL) Error
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7.4.4.2 MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in Figure 7-9 is the maximum value of the
difference between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-9. Absolute Accuracy (Total) Error
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7.5 General-Purpose Input/Output
The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and
bit-programmable. Both GIOA and GIOB support external interrupt capability.
7.5.1 Features
The GPIO module has the following features:
•
Each IO pin can be configured as:
–
–
–
Input
Output
Open Drain
•
The interrupts have the following characteristics:
–
–
–
–
Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
Individual interrupt flags (set in GIOFLG register)
Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers
respectively
–
Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
•
Internal pullup/pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 5.11 and Section 5.12
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7.6 Enhanced High-End Timer (N2HET)
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses.
7.6.1 Features
The N2HET module has the following features:
•
•
•
•
•
Programmable timer for input and output timing functions
Reduced instruction set (30 instructions) for dedicated time and angle functions
160 words of instruction RAM protected by parity
User defined number of 25-bit virtual counters for timer, event counters and angle counters
7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
•
•
•
•
Up to 32 pins usable for input signal measurements or output signal generation
Programmable suppression filter for each input pin with adjustable limiting frequency
Low CPU overhead and interrupt load
Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
•
Diagnostic capabilities with different loopback mechanisms and pin status read back functionality
7.6.2 N2HET RAM Organization
The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one
RAM address may be written while another address is read. The RAM words are 96-bits wide, which are
split into three 32-bit fields (program, control, and data).
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7.6.3 Input Timing Specifications
All of the N2HET channels have an enhanced pulse capture circuit. The N2HET instructions PCNT and
WCAP use this circuit to achieve the input timing requirements shown in Figure 7-10 and Table 7-23
below.
1
N2HETx
3
4
2
Figure 7-10. N2HET Input Capture Timings
Table 7-23. Input Timing Requirements for N2HET Channels with Enhanced Pulse Capture
PARAMETER
MIN
MAX
UNIT
ns
1, 2 Input signal period, PCNT or WCAP
(HRP) (LRP) tc(VCLK2) + 2
2 (HRP) tc(VCLK2) + 2
2 (HRP) tc(VCLK2) + 2
225 (HRP) (LRP) tc(VCLK2) - 2
225 (HRP) (LRP) tc(VCLK2) - 2
225 (HRP) (LRP) tc(VCLK2) - 2
3
4
Input signal high phase, PCNT or WCAP
Input signal low phase, PCNT or WCAP
ns
ns
7.6.4 N2HET1-N2HET2 Synchronization
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the re-synchronization signal from the
master, the slave must synchronize itself again..
N2HET1
N2HET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 7-11. N2HET1 – N2HET2 Synchronization Hookup
7.6.5 N2HET Checking
7.6.5.1 Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in Figure 7-12. The direction of the monitoring is controlled
by the I/O multiplexing control module.
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IOMM mux control signal x
N2HET1[1,3,5,7,9,11]
N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]
N2HET1
N2HET2[8,10,12,14,16,18]
N2HET2
Figure 7-12. N2HET Monitoring
7.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].
Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to
measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].
Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection
to the DCC module is made directly from the output of the N2HETx module (from the input of the output
buffer).
For more information on DCC see Section 6.7.3.
7.6.6 Disabling N2HET Outputs
Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET
module provides this capability through the "Pin Disable" input signal. This signal, when driven low,
causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. For more
details on the "N2HET Pin Disable" feature, see the device-specific Terminal Reference Manual.
GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin
Disable" input for N2HET2.
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7.6.7 High-End Timer Transfer Unit (HTU)
A High End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or
from main memory. A Memory Protection Unit (MPU) is built into the HTU.
7.6.7.1 Features
•
CPU and DMA independent
•
•
•
•
•
•
•
•
Master Port to access system memory
8 control packets supporting dual buffer configuration
Control packet information is stored in RAM protected by parity
Event synchronization (HET transfer requests)
Supports 32 or 64 bit transactions
Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64bit)
One shot, circular and auto switch buffer transfer modes
Request lost detection
7.6.7.2 Trigger Connections
Table 7-24. HTU1 Request Line Connection
Modules
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
N2HET1
Request Source
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HTU1 Request
HTU1 DCP[0]
HTU1 DCP[1]
HTU1 DCP[2]
HTU1 DCP[3]
HTU1 DCP[4]
HTU1 DCP[5]
HTU1 DCP[6]
HTU1 DCP[7]
Table 7-25. HET TU2 Request Line Connection
Modules
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
N2HET2
Request Source
HTUREQ[0]
HTUREQ[1]
HTUREQ[2]
HTUREQ[3]
HTUREQ[4]
HTUREQ[5]
HTUREQ[6]
HTUREQ[7]
HET TU2 Request
HTU2 DCP[0]
HTU2 DCP[1]
HTU2 DCP[2]
HTU2 DCP[3]
HTU2 DCP[4]
HTU2 DCP[5]
HTU2 DCP[6]
HTU2 DCP[7]
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7.7 FlexRay Interface
The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The
sample clock bitrate can be programmed to values up to 10 MBit per second. Additional bus driver (BD)
hardware is required for connection to the physical layer.
For communication on a FlexRay network, individual message buffers with up to 254 data bytes are
configurable. The message storage consists of a single-ported message RAM that holds up to 128
message buffers. All functions concerning the handling of messages are implemented in the message
handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay
Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as
providing message status information.
The register set of the FlexRay module can be accessed directly by the CPU via the VBUS interface.
These registers are used to control, configure and monitor the FlexRay channel protocol controllers,
message handler, global time unit, system universal control, frame/symbol processing, network
management, interrupt control, and to access the message RAM via the input / output buffer.
7.7.1 Features
The FlexRay module has the following features:
•
•
•
•
Conformance with FlexRay protocol specification v2.1
Data rates of up to 10 Mbit/s on each channel
Up to 128 message buffers
8 Kbyte of message RAM for storage of, for example, 128 message buffers with a maximum 48 byte
data section or up to 30 message buffers with 254 byte data section
•
•
•
Configuration of message buffers with different payload lengths
One configurable receive FIFO
Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive
FIFO
•
•
CPU access to message buffers via input and output buffer
FlexRay Transfer Unit (FTU) for automatic data transfer between data memory and message buffers
without CPU interaction
•
•
•
Filtering for slot counter, cycle counter, and channel ID
Maskable module interrupts
Supports Network Management
7.7.2 Electrical and Timing Specifications
Table 7-26. Timing Requirements for FlexRay Inputs
Parameter
MIN
MAX
UNIT
tpw
Input minimum pulse width to meet the FlexRay sampling
requirement
tc(VCLKA2) + 2.5(1)
ns
(1) tRxAsymDelay parameter
tpw
0.6*VCCIO
VCCIO
Input
0.4*VCCIO
0.6*VCCIO
0.4*VCCIO
0
Figure 7-13. FlexRay Inputs
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Table 7-27. FlexRay Jitter Timing(1)
Parameter
MIN
98
MAX
102
Unit
ns
tTx1bit
Clock jitter and signal symmetry
FlexRay BSS (byte start sequence) to BSS
Average over 10000 samples
tTx10bit
999
999.5
–
1001
1000.5
2.5
ns
tTx10bitAvg
tRxAsymDelay
ns
(2)
Delay difference between rise and fall from Rx pin to sample
point in FlexRay core
ns
tjit(SCLK)
Jitter for the 80MHz Sample Clock generated by the PLL
–
0.5
ns
(1) This parameter will be characterized, but not production-tested.
(2) This value is based on design simulation.
7.7.3 FlexRay Transfer Unit
The FlexRay Transfer Unit is able to transfer data between the input buffer (IBF) and output buffer (OBF)
of the communication controller and the system memory without CPU interaction.
Because the FlexRay module is accessed through the FTU, the FTU must be powered up by the setting
bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay
module register.
For more information on the FTU refer to the TMS570LS12x/11x Technical Reference Manual
(SPNU515).
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7.8 Controller Area Network (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh
environments (for example, automotive and industrial fields) that require reliable serial communication or
multiplexed wiring.
7.8.1 Features
Features of the DCAN module include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
The CAN kernel can be clocked by the oscillator for baud-rate generation.
64 mailboxes on each DCAN
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Message RAM protected by parity
Direct access to Message RAM during test mode
CAN Rx / Tx pins configurable as general purpose IO pins
Message RAM Auto Initialization
DMA support
For more information on the DCAN see the TMS570LS12x/11x Technical Reference Manual (SPNU515).
7.8.2 Electrical and Timing Specifications
Table 7-28. Dynamic Characteristics for the DCANx TX and RX pins
Parameter
MIN
MAX
15
Unit
ns
td(CANnTX)
td(CANnRX)
Delay time, transmit shift register to CANnTX pin(1)
Delay time, CANnRX pin to receive shift register
5
ns
(1) These values do not include rise/fall times of the output buffer.
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7.9 Local Interconnect Network Interface (LIN)
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-
line.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is
single-master/multiple-slave with a message identification for multi-cast transmission between any network
nodes.
7.9.1 LIN Features
The following are features of the LIN module:
•
•
•
•
Compatible to LIN 1.3, 2.0 and 2.1 protocols
Multibuffered receive and transmit units DMA capability for minimal CPU intervention
Identification masks for message filtering
Automatic Master Header Generation
–
–
–
Programmable Synch Break Field
Synch Field
Identifier Field
•
Slave Automatic Synchronization
–
–
–
Synch break detection
Optional baudrate update
Synchronization Validation
231 programmable transmission rates with 7 fractional bits
•
•
•
Error detection
2 Interrupt lines with priority encoding
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7.10 Serial Communication Interface (SCI)
7.10.1 Features
•
•
•
•
•
Standard universal asynchronous receiver-transmitter (UART) communication
Supports full- or half-duplex operation
Standard nonreturn to zero (NRZ) format
Double-buffered receive and transmit functions
Configurable frame format of 3 to 13 bits per character based on the following:
–
–
–
–
Data word length programmable from one to eight bits
Additional address bit in address-bit mode
Parity programmable for zero or one parity bit, odd or even parity
Stop programmable for one or two stop bits
•
•
•
•
•
•
Asynchronous or isosynchronous communication modes
Two multiprocessor communication formats allow communication between more than two devices.
Sleep mode is available to free CPU resources during multiprocessor communication.
The 24-bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection.
Four error flags and Five status flags provide detailed information regarding SCI events.
Capability to use DMA for transmit and receive data.
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7.11 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface
between the RM4x microcontroller and devices compliant with Philips Semiconductor I2C-bus specification
version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible
device.
7.11.1 Features
The I2C has the following features:
•
Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
–
–
–
–
–
–
–
–
Bit/Byte format transfer
7-bit and 10-bit device addressing modes
General call
START byte
Multi-master transmitter/ slave receiver mode
Multi-master receiver/ slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
•
•
•
•
•
•
•
•
•
•
Free data format
Two DMA events (transmit and receive)
DMA event enable/disable capability
Seven interrupts that can be used by the CPU
Module enable/disable capability
The SDA and SCL are optionally configurable as general purpose I/O
Slew rate control of the outputs
Open drain control of the outputs
Programmable pullup/pulldown capability on the inputs
Supports Ignore NACK mode
NOTE
This I2C module does not support:
•
•
•
High-speed (HS) mode
C-bus compatibility mode
The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
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7.11.2 I2C I/O Timing Specifications
Table 7-29. I2C Signals (SDA and SCL) Switching Characteristics(1)
Parameter
Standard Mode
Fast Mode
Unit
MIN
MAX
MIN
MAX
tc(I2CCLK)
Cycle time, Internal Module clock for I2C,
prescaled from VCLK
75.2
149
75.2
149
ns
f(SCL)
SCL Clock frequency
Cycle time, SCL
0
100
0
400
kHz
µs
tc(SCL)
10
4.7
2.5
0.6
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
µs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
START condition)
4
0.6
µs
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
tsu(SDA-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
250
0
Hold time, SDA valid after SCL low (for I2C bus
devices)
3.45(2)
0.9
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
4.0
1.3
0.6
0
µs
µs
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP
condition)
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(3)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
(3) Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SP)
tw(SCLL)
tr(SCL)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
tf(SCL)
th(SCLL-SDAL)
tsu(SCLH-SDAL)
th(SDA-SCLL)
Stop
Start
Repeated Start
Stop
Figure 7-14. I2C Timings
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NOTE
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
•
•
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + tsu(SDA-SCLH)
.
•
Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-
times are allowed.
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7.12 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.
Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display
drivers, and analog-to-digital converters.
7.12.1 Features
Both Standard and MibSPI modules have the following features:
•
•
•
•
16-bit shift register
Receive buffer register
8-bit baud clock generator
SPICLK can be internally-generated (master mode) or received from an external clock source (slave
mode)
•
•
Each word transferred can have a unique format
SPI I/Os not used in the communication can be used as digital input/output signals
Table 7-30. MibSPI/SPI Configurations PGE Package
MibSPIx/SPIx
MibSPI1
I/Os
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA
MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA
SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA
MibSPI3
MibSPI5
SPI4
Table 7-31. MibSPI/SPI Configurations ZWT Package
MibSPIx/SPIx
I/Os
MibSPI1
MibSPI3
MibSPI5
SPI2
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA
MIBSPI3SIMO[0], MIBSPI3SOMI[0], MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2SIMO[0], SPI2SOMI[0], SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4
SPI4SIMO[0], SPI4SOMI[0], SPI4CLK, SPI4nCS[0], SPI4nENA
7.12.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx
module supports 8 transfer groups.
7.12.3 MibSPI Transmit Trigger Events
Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event
and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low
level at a selectable trigger source. For example, up to 15 trigger sources are available for use by each
transfer group. These trigger options are listed in Table 7-32 and Section 7.12.3.2 for MibSPI1 and
MibSPi3 respectively.
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7.12.3.1 MIBSPI1 Event Trigger Hookup
Table 7-32. MIBSPI1 Event Trigger Hookup
Event #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
TGxCTRL TRIGSRC[3:0]
Trigger
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI1 transfers; there is no multiplexing on the input connections.
7.12.3.2 MIBSPI3 Event Trigger Hookup
Table 7-33. MIBSPI3 Event Trigger Hookup
Event #
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
TGxCTRL TRIGSRC[3:0]
Trigger
No trigger source
GIOA[0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
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Table 7-33. MIBSPI3 Event Trigger Hookup (continued)
Event #
EVENT9
TGxCTRL TRIGSRC[3:0]
Trigger
N2HET1[10]
1010
1011
1100
1101
1110
1111
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI3 transfers; there is no multiplexing on the input connections.
7.12.3.3 MIBSPI5 Event Trigger Hookup
Table 7-34. MIBSPI5 Event Trigger Hookup
Event #
TGxCTRL TRIGSRC[3:0]
Trigger
Disabled
EVENT0
EVENT1
EVENT2
EVENT3
EVENT4
EVENT5
EVENT6
EVENT7
EVENT8
EVENT9
EVENT10
EVENT11
EVENT12
EVENT13
EVENT14
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No trigger source
GIOA[0]
GIOA[1]
GIOA[2]
GIOA[3]
GIOA[4]
GIOA[5]
GIOA[6]
GIOA[7]
N2HET1[8]
N2HET1[10]
N2HET1[12]
N2HET1[14]
N2HET1[16]
N2HET1[18]
Internal Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
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NOTE
For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI5 transfers; there is no multiplexing on the input connections.
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7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-35. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO. Parameter
tc(SPC)M
2(5) tw(SPCH)M
MIN
MAX
Unit
ns
1
Cycle time, SPICLK(4)
40
256tc(VCLK)
0.5tc(SPC)M + 3
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
ns
tw(SPCL)M
3(5) tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 6
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
4(5) td(SPCH-SIMO)M Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
td(SPCL-SIMO)M Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
5(5) tv(SPCL-SIMO)M
0.5tc(SPC)M – 6
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf(SPC) – 4
0.5tc(SPC)M – tr(SPC) – 4
tf(SPC) + 2.2
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
6(5) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
7(5) th(SPCL-SOMI)M Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
tr(SPC) + 2.2
10
th(SPCH-SOMI)M Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
8(6) tC2TDELAY
10
Setup time CS active
until SPICLK high
(clock polarity = 0)
CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) + 5.5
-
-
-
-
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) + 5.5
Setup time CS active
until SPICLK low
CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) + 5.5
(clock polarity = 1)
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY
Hold time SPICLK low until CS inactive
(clock polarity = 0)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tf(SPC) + tr(SPICS) - 7
+
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tf(SPC) + tr(SPICS) + 11
+
ns
ns
-
-
-
-
Hold time SPICLK high until CS
inactive (clock polarity = 1)
0.5*tc(SPC)M
T2CDELAY*tc(VCLK) + tc(VCLK)
tr(SPC) + tr(SPICS) - 7
+
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK)
tr(SPC) + tr(SPICS) + 11
10
11
tSPIENA
SPIENAn Sample point
(C2TDELAY+1) * tc(VCLK)
tf(SPICS) – 29
-
(C2TDELAY+1)*tc(VCLK)
ns
ns
tSPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 5-8.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 7-15. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 7-16. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
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Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
ns
(4)
1
tc(SPC)M
Cycle time, SPICLK
40
256tc(VCLK)
0.5tc(SPC)M + 3
2(5) tw(SPCH)M
tw(SPCL)M
3(5) tw(SPCL)M
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
ns
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M – 6
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
0.5tc(SPC)M + 3
Pulse duration, SPICLK low (clock
polarity = 0)
ns
ns
Pulse duration, SPICLK high (clock
polarity = 1)
4(5) tv(SIMO-SPCH)M
Valid time, SPICLK high after
SPISIMO data valid (clock polarity =
0)
tv(SIMO-SPCL)M
Valid time, SPICLK low after
0.5tc(SPC)M – 6
SPISIMO data valid (clock polarity =
1)
5(5) tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
6(5) tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
7(5) tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr(SPC) – 4
ns
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf(SPC) – 4
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tr(SPC) + 2.2
tf(SPC) + 2.2
10
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
10
8(6) tC2TDELAY
Setup time CS
active until SPICLK
high (clock polarity =
0)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) + 5.5
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tr(SPC) – 7
-
-
-
-
-
-
-
-
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) + 5.5
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tr(SPC) – 7
Setup time CS
active until SPICLK
low (clock polarity =
1)
0.5*tc(SPC)M
+
0.5*tc(SPC)M
+
ns
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) – 7
(C2TDELAY+2) * tc(VCLK)
tf(SPICS) + tf(SPC) + 5.5
-
0.5*tc(SPC)M
+
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) + 5.5
(C2TDELAY+3) * tc(VCLK)
tf(SPICS) + tf(SPC) – 7
-
9(6) tT2CDELAY
Hold time SPICLK low until CS
inactive (clock polarity = 0)
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
7
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tf(SPC) + tr(SPICS)
11
+
ns
ns
+
+
Hold time SPICLK high until CS
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
7
+
T2CDELAY*tc(VCLK)
tc(VCLK) - tr(SPC) + tr(SPICS)
11
+
10 tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)* tc(VCLK)
tf(SPICS) – 29
-
(C2TDELAY+1)*tc(VCLK)
ns
ns
11 tSPIENAW
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*tc(VCLK)
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see the Table 5-8.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
Master Out Data Is Valid
Data Valid
SPISIMO
SPISOMI
6
7
Master In Data
Must Be Valid
Figure 7-17. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
SPICSn
Master Out Data Is Valid
8
9
10
11
SPIENAn
Figure 7-18. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
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7.12.5 SPI Slave Mode I/O Timings
Table 7-37. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
1
Parameter
tc(SPC)S
MIN
40
MAX
Unit
ns
Cycle time, SPICLK(5)
2(6)
tw(SPCH)S
tw(SPCL)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
14
3(6)
4(6)
tw(SPCL)S
14
ns
ns
tw(SPCH)S
td(SPCH-SOMI)S
14
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
trf(SOMI) + 20
trf(SOMI) + 20
td(SPCL-SOMI)S
th(SPCH-SOMI)S
th(SPCL-SOMI)S
tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
th(SPCL-SIMO)S
th(SPCH-SIMO)S
td(SPCL-SENAH)S
td(SPCH-SENAH)S
td(SCSL-SENAL)S
Delay time, SPISOMI valid after SPICLK low (clock polarity
= 1)
5(6)
6(6)
7(6)
8
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
2
ns
ns
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
Setup time, SPISIMO before SPICLK low (clock polarity =
0)
4
Setup time, SPISIMO before SPICLK high (clock polarity =
1)
4
2
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
Hold time, SPISIMO data valid after S PICLK high (clock
polarity = 1)
2
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
2.5tc(VCLK)+tr(ENAn)
+
22
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
2.5tc(VCLK)+ tr(ENAn)
22
+
9
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tc(VCLK)+tf(ENAn)+27
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-8.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
SPISIMO
6
7
SPISIMO Data
Must Be Valid
Figure 7-19. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
Figure 7-20. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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Table 7-38. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO. Parameter
tc(SPC)S
2(6) tw(SPCH)S
tw(SPCL)S
3(6) tw(SPCL)S
tw(SPCH)S
MIN
40
MAX
Unit
ns
1
Cycle time, SPICLK(5)
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
14
ns
14
14
ns
ns
14
4(6) td(SOMI-SPCL)S
Delay time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
trf(SOMI) + 20
trf(SOMI) + 20
td(SOMI-SPCH)S
5(6) th(SPCL-SOMI)S
th(SPCH-SOMI)S
Delay time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
2
ns
ns
ns
ns
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock
polarity = 0)
4
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity
= 1)
7(6) tv(SPCH-SIMO)S
4
2
High time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
tv(SPCL-SIMO)S
High time, SPISIMO data valid after SPICLK low (clock
polarity = 1)
2
8
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high
(clock polarity = 0)
1.5tc(VCLK)
1.5tc(VCLK)
tf(ENAn)
tc(VCLK)
2.5tc(VCLK)+tr(ENAn) + 22
2.5tc(VCLK)+tr(ENAn) + 22
tc(VCLK)+tf(ENAn)+ 27
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock
polarity = 1)
9
td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
ns
ns
10
td(SCSL-SOMI)S
Delay time, SOMI valid after SPICSn low (if new data
has been written to the SPI buffer)
2tc(VCLK)+trf(SOMI)+ 28
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 5-8.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-21. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
SPICSn
9
10
SPISOMI
Slave Out Data Is Valid
Figure 7-22. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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8 Device and Documentation Support
8.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of
all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP,
or TMS (for example,TMS570LS1115). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP
TMS
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
TMX and TMP devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices
are to be used.
The figure below illustrates the numbering and symbol nomenclature for the TMS570LS1115 .
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Full Part #
TMS
TMX
570
570
LS 11
11
1
1
5
5
B
B
ZWT
ZWT
Q
Q
Q1
Q1
R
R
Orderable Part #
Prefix: TM
TMS = Fully Qualified
TMP = Prototype
TMX = Samples
Core Technology:
570 = Cortex R4F
Architecture:
LS = Dual CPUs in Lockstep
(not included in orderable part #)
Flash Memory Size:
11 = 1MB
RAM MemorySize:
1 = 128kB
Peripheral Set:
5 = FlexRay
Die Revision:
A
= Die Revision A
= Die Revision B
B
Package Type:
ZWT = 337-Pin Plastic BGA with pb-free solder ball
PGE = 144 Pin Plastic Quad Flatpack
Temperature Range:
Q = -40...+125oC
Quality Designator:
Q1 = Automotive
Shipping Options:
R = Tape and Reel
Figure 8-1. TMS570LS1115 Device Numbering Conventions
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8.2 Documentation Support
8.2.1 Related Documentation from Texas Instruments
The following documents describe the TMS570LS11x/12x microcontroller..
SPNU515
TMS570LS12x/11x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual details the
integration, the environment, the functional description, and the programming models for each
peripheral and subsystem in the device.
SPNZ199
SPNZ218
TMS570LS12x/11x Microcontroller, Silicon Revision B, Silicon Errata describes the usage notes
and known exceptions to the functional specifications for the device silicon revision B.
TMS570LS12x/11x Microcontroller, Silicon Revision C, Silicon Errata describes the usage notes
and known exceptions to the functional specifications for the device silicon revision C.
8.2.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve
problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers
get started with Embedded Processors from Texas Instruments and to foster innovation and growth of
general knowledge about the hardware and software surrounding these devices.
8.3 Trademarks
E2E is a trademark of Texas Instruments.
CoreSight is a trademark of ARM Limited.
ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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8.6 Device Identification
8.6.1 Device Identification Code Register
The device identification code register identifies several aspects of the device including the silicon version.
The details of the device identification code register are shown in Table 8-1. The device identification code
register value for this device is:
•
•
•
Rev A = 0x8046AD05
Rev B = 0x8046AD15
Rev C = 0x8046AD1D
Figure 8-2. Device ID Bit Allocation Register
31
CP-15
R-1
30
29
13
28
27
26
25
24
23
22
21
20
19
3
18
17
16
TECH
R-0
UNIQUE ID
R-00000000100011
15
14
12
11
10
9
8
7
6
5
4
2
1
1
0
0
1
TECH
I/O
PERIPH FLASH ECC
RAM
ECC
VERSION
VOLT PARITY
AGE
R-101
R-0
R-1
R-10
R-1
R-00011
R-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-1. Device ID Bit Allocation Register Field Descriptions
Bit
Field
Value
Description
31
CP15
Indicates the presence of coprocessor 15
CP15 present
1
30-17
16-13
UNIQUE ID
TECH
100011 Unique device identification number
This bitfield holds a unique number for a dedicated device configuration (die).
Process technology on which the device is manufactured.
0101
F021
12
I/O VOLTAGE
I/O voltage of the device.
I/O are 3.3v
0
1
11
PERIPHERAL
PARITY
Peripheral Parity
Parity on peripheral memories
10-9
FLASH ECC
Flash ECC
10
1
Program memory with ECC
Indicates if RAM memory ECC is present.
ECC implemented
8
RAM ECC
7-3
2-0
REVISION
101
Revision of the Device.
The platform family ID is always 0b101
8.6.2 Die Identification Registers
The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the
information as shown in Table 8-2.
Table 8-2. Die-ID Registers
Item
X Coordinate on Wafer
Y Coordinate on Wafer
Wafer #
# of Bits
Bit Location
12
12
8
0xFFFFFF7C[11:0]
0xFFFFFF7C[23:12]
0xFFFFFF7C[31:24]
0xFFFFFF80[23:0]
Lot #
24
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Table 8-2. Die-ID Registers (continued)
Item
# of Bits
Bit Location
Reserved
8
0xFFFFFF80[31:24]
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8.7 Module Certifications
The following communications modules have received certification of adherence to a standard.
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8.7.1 FlexRay™ Certifications
Figure 8-3. Flexray Certification for ZWT Package
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Figure 8-4. Flexray Certification for PGE Package
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8.7.2 DCAN Certification
Figure 8-5. DCAN Certification
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8.7.3 LIN Certification
8.7.3.1 LIN Master Mode
Figure 8-6. LIN Certification - Master Mode
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8.7.3.2 LIN Slave Mode - Fixed Baud Rate
Figure 8-7. LIN Certification - Slave Mode - Fixed Baud Rate
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8.7.3.3 LIN Slave Mode - Adaptive Baud Rate
Figure 8-8. LIN Certification - Slave Mode - Adaptive Baud Rate
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9 Mechanical Packaging and Orderable Information
9.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
without revision of this document. For browser-based versions of this data sheet, refer to the left-hand
navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS5701115CPGEQQ1
TMS5701115CZWTQQ1
ACTIVE
LQFP
PGE
144
337
60
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
TMS570LS
1115CPGEQQ1
ACTIVE
NFBGA
ZWT
90
SNAGCU
TMS570LS
1115CZWTQQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
ZWT0337A
NFBGA - 1.4 mm max height
SCALE 0.950
PLASTIC BALL GRID ARRAY
16.1
15.9
A
B
BALL A1 CORNER
16.1
15.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
TYP
14.4 TYP
SYMM
(0.8) TYP
(0.8) TYP
W
V
U
T
R
P
N
M
L
14.4
TYP
SYMM
K
J
H
G
F
0.55
337X
0.45
E
D
C
0.15
0.05
C A B
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
0.8 TYP
0.8 TYP
BALL A1 CORNER
4223381/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
337X ( 0.4)
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:7X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.4)
METAL
EXPOSED METAL
(
0.4)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223381/A 02/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZWT0337A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
11
12
13 14 15 16 17 18 19
1
3
4
6
7
8
9
10
2
5
A
B
C
(0.8) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
U
V
W
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:7X
4223381/A 02/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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