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TMS570LS0714

SPNS226E –JUNE 2013–REVISED NOVEMBER 2016

TMS570LS0714 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

1

• High-Performance Automotive-Grade

Microcontroller (MCU) for Safety-Critical

Applications

• Enhanced Timing Peripherals

– 7 Enhanced Pulse Width Modulator (ePWM)

Modules

– Dual CPUs Running in Lockstep

– ECC on Flash and RAM Interfaces

– Built-In Self-Test (BIST) for CPU and On-chip

RAMs

– Error Signaling Module With Error Pin

– Voltage and Clock Monitoring

– 6 Enhanced Capture (eCAP) Modules

– 2 Enhanced Quadrature Encoder Pulse (eQEP)

Modules

• Two Next Generation High-End Timer (N2HET)

Modules

– N2HET1: 32 Programmable Channels

– N2HET2: 18 Programmable Channels

– 160-Word Instruction RAM With Parity

Protection Each

– Each N2HET Includes Hardware Angle

Generator

– Dedicated High-End Timer Transfer Unit (HTU)

for Each N2HET

• ARM^®Cortex^®-R4F 32-Bit RISC CPU

– 1.66 DMIPS/MHz With 8-Stage Pipeline

– FPU With Single and Double Precision

– 12-Region Memory Protection Unit (MPU)

– Open Architecture With Third-Party Support

• Operating Conditions

– Up to 160-MHz System Clock

• Two 12-Bit Multibuffered ADC Modules

– ADC1: 24 Channels

– Core Supply Voltage (VCC): 1.14 to 1.32 V

– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

• Integrated Memory

– ADC2: 16 Channels

– 16 Shared Channels

– 64 Result Buffers With Parity Protection Each

• Multiple Communication Interfaces

– Up to Three CAN Controllers (DCANs)

– 64 Mailboxes With Parity Protection Each

– 768KB of Flash With ECC

– 128KB of RAM With ECC

– 64KB of Flash for Emulated EEPROM With

ECC

• Common Platform Architecture

– Compliant to CAN Protocol Version 2.0A and

2.0B

– Inter-Integrated Circuit (I²C)

– 3 Multibuffered Serial Peripheral Interfaces

(MibSPIs)

– 128 Words With Parity Protection Each

– 8 Transfer Groups

– One Standard Serial Peripheral Interface (SPI)

Module

– Two UART (SCI) Interfaces, One With Local

Interconnect Network (LIN 2.1) Interface

Support

– Consistent Memory Map Across Family

– Real-Time Interrupt Timer (RTI) OS Timer

– 128-Channel Vectored Interrupt Module (VIM)

– 2-Channel Cyclic Redundancy Checker (CRC)

• Direct Memory Access (DMA) Controller

– 16 Channels and 32 Peripheral Requests

– Parity for Control Packet RAM

– DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked Loop

(FMPLL) With Built-In Slip Detector

• IEEE 1149.1 JTAG, Boundary Scan and ARM

CoreSight™ Components

• Advanced JTAG Security Module (AJSM)

• Up to 64 General-Purpose I/O (GIO) Pins

• Packages

– 144-Pin Quad Flatpack (PGE) [Green]

– 100-Pin Quad Flatpack (PZ) [Green]

– Up to 16 GIO Pins With Interrupt Generation

Capability

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS570LS0714

SPNS226E –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com

1.2 Applications

•

Electric Power Steering (EPS)

Braking Systems (ABS and ESC)

HEV and EV Inverter Systems

Battery-Management Systems

•

Active Driver Assistance Systems

Aerospace and Avionics

Railway Communications

Off-road Vehicles

2

Device Overview

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1.3 Description

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade

ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to

assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating

today with the Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip

diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic;

ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most

peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient

1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The

TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-

bit error correction and double-bit error detection. The flash memory on this device is nonvolatile,

electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The

flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase

operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and

doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two

Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven

Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two

Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters

(ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,

capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for

applications requiring multiple sensor information and drive actuators with complex and accurate time

pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A

Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or

intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation.

With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for

digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is

important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when

not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position,

direction, and speed information from a rotating machine as used in high-performance motion and

position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer

RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three

separate groups. Each group can be converted once when triggered or configured for continuous

conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster

conversion time is desired.

Device Overview

3

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The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can

be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial

interaction for high-speed communications between similar shift-register type devices. The LIN supports

the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard

Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial,

multimaster communication protocol that efficiently supports distributed real-time control with robust

communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh

environments (for example, automotive and industrial fields) that require reliable serial communication or

multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the

microcontroller and an I²C-compatible device through the I²C serial bus. The I2C module supports speeds

of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible

clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the

available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous

external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral

interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of

the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests,

and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous

transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external

error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored

externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the

TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-

critical requirements.

Device Information⁽¹⁾

PART NUMBER

TMS570LS0714PGE

TMS570LS0714PZ

PACKAGE

LQFP (144)

LQFP (100)

BODY SIZE

20.0 mm × 20.0 mm

14.0 mm × 14.0 mm

(1) For more information, see Section 10, Mechanical Packaging and Orderable Information.

4

Device Overview

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SPNS226E –JUNE 2013–REVISED NOVEMBER 2016

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

NOTE: The block diagram reflects the 144PGE package. Some functions are multiplexed or not available

in other packages. For details, see the respective terminal functions table in Section 4.2, Terminal

Functions.

128KBRAM

with ECC

768KB

Flash

with

32K

ECC

DMA

HTU1

HTU2

Dual Cortex-R4F

CPUs in Lockstep

Switched Central Resource Switched Central Resource

Main Cross Bar: Arbitration and Prioritization Control

Switched Central Resource

Peripheral Central Resource Bridge

CRC

nPORRST

SYS

nRST

ECLK

eQEPxA

IOMM

eQEP

64KB Flash

eQEPxB

nERROR

1,2

eQEPxS

eQEPxI

ESM

for EEPROM

Emulation

with ECC

PMM

VIM

CAN1_RX

CAN1_TX

CAN2_RX

CAN2_TX

DCAN1

eCAP

1..6

eCAP[6:1]

DCAN2

DCAN3

CAN3_RX

CAN3_TX

nTZ[3:1]

SYNCO

SYNCI

ePWM

1..7

MIBSPI1_CLK

MIBSPI1_SIMO[1:0]

MIBSPI1_SOMI[1:0]

ePWMxA

ePWMxB

MibSPI1

SPI2

RTI

MIBSPI1_nCS[5:0]

MIBSPI1_nENA

SPI2_CLK

SPI2_SIMO

SPI2_SOMI

Color Legend for Power Domains

Core/RAM

DCC1

Core

RAM

SPI2_nCS[1:0]

SPI2_nENA

always on

# 1

# 2

# 3

# 5

# 1

MIBSPI3_CLK

MIBSPI3_SIMO

MIBSPI3_SOMI

MIBSPI3_nCS[5:0]

MIBSPI3_nENA

MibSPI3

SPI4

DCC2

I2C

SPI4_CLK

SPI4_SIMO

SPI4_SOMI

SPI4_nCS0

SPI4_nENA

MibADC1

MibADC2 N2HET1 N2HET2

GIO

MIBSPI5_SIMO[3:0]

MIBSPI5_SOMI[3:0]

MIBSPI5_nCS[3:0]

MIBSPI5_nENA

MibSPI5

LIN_RX

LIN_TX

LIN

SCI

SCI_RX

SCI_TX

Figure 1-1. Functional Block Diagram

Device Overview

5

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Table of Contents

1

Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 3

1.4 Functional Block Diagram ............................ 5

Revision History ......................................... 7

Device Comparison ..................................... 8

3.1 Related Products ..................................... 8

Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Signal Descriptions ................................. 11

4.3 Pin Multiplexing...................................... 29

4.4 Buffer Type.......................................... 35

Specifications .......................................... 36

5.1 Absolute Maximum Ratings......................... 36

5.2 ESD Ratings ........................................ 36

5.3 Power-On Hours (POH)............................. 36

5.4 Recommended Operating Conditions............... 37

6.14 Vectored Interrupt Manager ......................... 73

6.15 DMA Controller ...................................... 76

6.16 Real-Time Interrupt Module ......................... 78

6.17 Error Signaling Module.............................. 80

6.18 Reset/Abort/Error Sources .......................... 84

6.19 Digital Windowed Watchdog ........................ 87

6.20 Debug Subsystem................................... 88

2

3

7

Peripheral Information and Electrical

Specifications ........................................... 93

4

7.1 I/O Timings ......................................... 93

7.2 Enhanced PWM Modules (ePWM).................. 96

7.3 Enhanced Capture Modules (eCAP)............... 102

7.4

Enhanced Quadrature Encoder (eQEP) ........... 105

12-Bit Multibuffered Analog-to-Digital Converter

7.5

5

(MibADC)........................................... 108

7.6 General-Purpose Input/Output..................... 121

7.7 Enhanced High-End Timer (N2HET) .............. 122

7.8 Controller Area Network (DCAN) .................. 126

7.9

Local Interconnect Network Interface (LIN)........ 127

5.5

Input/Output Electrical Characteristics Over

7.10 Serial Communication Interface (SCI) ............. 128

Recommended Operating Conditions............... 38

Power Consumption Over Recommended

7.11 Inter-Integrated Circuit (I2C) Module .............. 129

5.6

Operating Conditions................................ 39

5.7 Thermal Resistance Characteristics ................ 40

5.8 Timing and Switching Characteristics............... 41

System Information and Electrical

Specifications ........................................... 43

7.12 Multibuffered / Standard Serial Peripheral

Interface............................................ 132

8

9

Applications, Implementation, and Layout ...... 144

8.1 TI Designs or Reference Designs ................. 144

Device and Documentation Support.............. 145

9.1 Getting Started and Next Steps ................... 145

6

6.1 Device Power Domains ............................. 43

6.2 Voltage Monitor Characteristics ..................... 43

9.2

Device and Development-Support Tool

Nomenclature ...................................... 145

6.3

Power Sequencing and Power-On Reset ........... 44

9.3 Tools and Software ................................ 147

9.4 Documentation Support............................ 149

9.5 Community Resources............................. 149

9.6 Trademarks ........................................ 149

9.7 Electrostatic Discharge Caution ................... 150

9.8 Glossary............................................ 150

9.9 Device Identification................................ 151

9.10 Module Certifications............................... 152

6.4 Warm Reset (nRST)................................. 46

6.5 ARM Cortex-R4F CPU Information ................. 47

6.6 Clocks ............................................... 51

6.7 Clock Monitoring .................................... 58

6.8 Glitch Filters......................................... 60

6.9 Device Memory Map ................................ 61

6.10 Flash Memory ....................................... 66

6.11 Tightly Coupled RAM Interface Module ............. 69

6.12 Parity Protection for Accesses to Peripheral RAMs 69

6.13 On-Chip SRAM Initialization and Testing ........... 71

10 Mechanical Packaging and Orderable

Information............................................. 157

10.1 Packaging Information ............................. 157

6

Table of Contents

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPNS226D device-specific

data manual to make it an SPNS226E revision.

Scope: Applicable updates to the TMS570LS0714 device family, specifically relating to the

TMS570LS0714 devices (Silicon Revision A), which are now in the production data (PD) stage of

development have been incorporated.

Changes from September 15, 2015 to November 1, 2016 (from D Revision (September 2015) to E Revision)

Page

•

GLOBAL: PZ package is now fully qualified ...................................................................................... 1

Section 1.1 (Features): Updated/Changed the GIO pin count in GIO bullet .................................................. 1

Section 1.1: Updated/Changed the SPI features bullet.......................................................................... 1

Section 3.1 (Related Products): Added new section. ............................................................................ 8

Section 4.2 (Signal Descriptions): Updated/Changed reference to Technical Reference Manual ....................... 11

Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Added a description for pins 14 and 55

(N2HET1_PIN_nDIS and N2HET2_PIN_nDIS, respectively).................................................................. 13

Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Added Pin 10, GIOA[5] / INT[5] / EXTCLKIN

/EPWM1A/N2HET1_PIN_nDIS.................................................................................................... 22

Table 6-20 (Device Memory Map): Updated/Changed the FRAME SIZE column value for "Flash Data Space

ECC" under Flash Module Bus2 Interface from "768KB" to "1MB". .......................................................... 62

Section 6.19 (Digital Windowed Watchdog): Added Figure 6-13, Digital Windowed Watchdog Example............... 87

Table 7-11 (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in MODULE INSTANCE

column............................................................................................................................... 103

Table 7-15 (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in MODULE INSTANCE

column............................................................................................................................... 106

Table 7-20 (MibADC1 Trigger Event Hookup): Added lead-in paragraph referencing the table ........................ 108

Table 7-21 (MibADC2 Event Trigger Hookup): Added lead-in paragraph referencing the table ........................ 110

Figure 7-11 (ePWM1SOC1A Switch Implementation): Added missing ePWM1 SOC1A detailed switch

•

connection example and lead-in reference sentence ......................................................................... 114

Section 9.1 (Getting Started and Next Steps): Added new section ......................................................... 145

Section 9.2 (Device and Development-Support Tool Nomenclature): Moved subsection after "Getting Started

and Next Steps" subsection (new) .............................................................................................. 145

Section 9.9.1 Added the address of the Device ID register. ................................................................. 151

•

Revision History

7

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3 Device Comparison

Table 3-1 lists the features of the TMS570LS0714 devices.

Table 3-1. TMS570LS0714 Device Comparison

FEATURES

Generic Part Number

Package

TMS570LS DEVICES

3137ZWT⁽¹⁾

337 BGA

ARM Cortex-R4F

180

1227ZWT⁽¹⁾

337 BGA

ARM Cortex-R4F

180

0914PGE⁽¹⁾

0714PGE

144 QFP

ARM Cortex-R4F

160

0714PZ

100 QFP

ARM Cortex-R4F

100

0432PZ

144 QFP

100 QFP

CPU

ARM Cortex-R4F

ARM Cortex-R4

Frequency (MHz)

Flash (KB)

160

1024

128

80

384

32

3072

1280

768

RAM (KB)

256

192

128

Data Flash [EEPROM]

(KB)

64

16

EMAC

FlexRay

CAN

10/100

2-ch

3

10/100

2-ch

3

–

3

–

3

–

2

–

2

MibADC

12-bit (Ch)

2 x (24ch)

2 x (16ch)

1 x (16ch)

N2HET (Ch)

ePWM Channels

eCAP Channels

eQEP Channels

MibSPI (CS)

SPI (CS)

2 (44)

2 (40)

2 (21)

1 (19)

–

14

8

–

6

4

0

–

2

3 (5 + 6 + 1)

1 (1)

2

3 (5 + 6 + 4)

1 (1)

1

2 (5 + 1)

1 (1)

2

3 (6 + 6 + 4)

2 (2 + 1)

2 (1 with LIN)

1

3 (6 + 6 + 4)

2 (2 + 1)

2 (1 with LIN)

1

1 (4)

2

SCI (LIN)

2 (1 with LIN)

1

2 (1 with LIN)

1

1 (with LIN)

–

1 (with LIN)

–

I2C

120 (with 16 interrupt

capable)

101 (with 16 interrupt

capable)

64 (with 10 interrupt

capable)

64 (with 10 interrupt

capable)

45 (with 9 interrupt

capable)

45 (with 8 interrupt

capable)

GPIO (INT)

EMIF

16-bit data

32-bit

16-bit data

–

ETM (Trace)

RTP/DMM

–

YES

Operating

Temperature

-40ºC to 125ºC

Core Supply (V)

I/O Supply (V)

1.14 V – 1.32 V

3.0 V – 3.6 V

1.14 V – 1.32 V

3.0 V – 3.6 V

1.14 V – 1.32 V

3.0 V – 3.6 V

1.14 V – 1.32 V

3.0 V – 3.6 V

1.14 V – 1.32 V

3.0 V – 3.6 V

1.14 V – 1.32 V

3.0 V – 3.6 V

(1) Bolding denotes a superset device. For additional device variants, see www.ti.com/tms570

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TMS570 16-Bit and 32-Bit MCUs

An expansive portfolio of software and pin-compatible high-performance ARM^®Cortex^®-R-based MCU

products from 80 MHz up to 300 MHz with on-chip features that prove a high level of diagnostic coverage,

as well as provide scalability to address a wide range of applications.

Companion Products for TMS570LS0714

Review products that are frequently purchased or used with this product.

8

Device Comparison

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.1.1 PGE QFP Package Pinout (144-Pin)

AD1IN[10] / AD2IN[10]

AD1IN[01]

AD1IN[09] / AD2IN[09]

VCCAD

VSSAD

ADREFLO

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

nTRST

TDI

TDO

TCK

RTCK

VCC

ADREFHI

VSS

nRST

nERROR

N2HET1[10]

ECLK

AD1IN[21] / AD2IN[05]

AD1IN[20] / AD2IN[04]

AD1IN[19] / AD2IN[03]

AD1IN[18] / AD2IN[02]

AD1IN[07]

AD1IN[0]

AD1IN[17] / AD2IN[01]

AD1IN[16] / AD2IN[0]

VCC

VCCIO

VSS

VCC

N2HET1[12]

N2HET1[14]

GIOB[0]

N2HET1[30]

CAN2TX

VSS

MIBSPI3NCS[0]

MIBSPI3NENA

MIBSPI3CLK

MIBSPI3SIMO

MIBSPI3SOMI

VSS

VCC

VSS

nPORRST

VCC

VSS

VCCIO

N2HET1[15]

MIBSPI1NCS[2]

N2HET1[13]

N2HET1[06]

MIBSPI3NCS[1]

CAN2RX

MIBSPI1NCS[1]

LINRX

LINTX

GIOB[1]

VCCP

VSS

VCCIO

VCC

VSS

N2HET1[16]

N2HET1[18]

N2HET1[20]

GIOB[2]

VCC

VSS

A. Pins can have multiplexed functions. Only the default function is shown in Figure 4-1.

Figure 4-1. PGE QFP Package Pinout (144-Pin)

Terminal Configuration and Functions

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4.1.2 PZ QFP Package Pinout (100-Pin)

50

49

AD1IN[10]

AD1IN[1]

AD1IN[9]

76

nTRST

77

TDI

48

47

78

TDO

VSSAD/ADREFLO

VCCAD/ADREFHI

AD1IN[21]

79

TCK

RTCK

46

45

80

81

nRST

44

AD1IN[20]

82

nERROR

N2HET1[10]

43

42

AD1IN[7]

83

AD1IN[0]

84

ECLK

VCCIO

VSS

41

40

39

AD1IN[17]

85

86

87

AD1IN[16]

MIBSPI1nCS[3]

MIBSPI3nCS[0]

VSS

38

37

36

35

34

33

32

31

30

29

28

27

26

VCC

88

89

90

91

92

93

94

95

96

97

98

99

100

MIBSPI3nENA

MIBSPI3CLK

N2HET1[12]

N2HET1[14]

CAN2TX

MIBSPI3SIMO

MIBSPI3SOMI

CAN2RX

MIBSPI1nCS[1]

VSS

VCC

LINRX

LINTX

nPORRST

VCC

VCCP

VSS

N2HET1[16]

N2HET1[18]

VCC

VCCIO

MIBSPI1nCS[2]

N2HET1[6]

VSS

Figure 4-2. PZ QFP Package Pinout (100-Pin)

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4.2 Signal Descriptions

The signal descriptions section shows pin information in module function order per package.

Section 4.2.1 and Section 4.2.2 identify the external signal names, the associated pin or ball numbers

along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground),

whether the pin or ball has any internal pullup/pulldown, whether the pin or ball can be configured as a

GIO, and a functional pin or ball description. The first signal name listed is the primary function for that

terminal (pin or ball). The signal name in Bold is the function being described. For information on how to

select between different multiplexed functions, see Section 4.3, Pin Multiplexing or see the I/O Multiplexing

and Control Module (IOMM) chapter of the TMS570LS09x/07x 16/32-Bit RISC Flash Microcontroller

Technical Reference Manual (SPNU607).

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately

after nPORRST goes high.

All output-only signals are configured as high impedance while nPORRST is low, and are

configured as outputs immediately after nPORRST goes high.

While nPORRST is low, the input buffers are disabled, and the output buffers are high

impedance.

In the Terminal Functions tables of Section 4.2.1 and Section 4.2.2, the RESET PULL

STATE is the state of the pullup or pulldown while nPORRST is low and immediately after

nPORRST goes high. The default pull direction may change when software configures the

pin for an alternate function. The PULL TYPE is the type of pull asserted when the signal

name in bold is enabled for the given terminal.

Terminal Configuration and Functions

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4.2.1 PGE Package Terminal Functions

4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)

Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

ADREFHI⁽¹⁾

66

Power

–

None

ADC high reference

supply

ADREFLO⁽¹⁾

VCCAD⁽¹⁾

VSSAD⁽¹⁾

AD1EVT

67

69

68

86

Power

Ground

I/O

ADC low reference supply

Operating supply for ADC

Pulldown Programmable, ADC1 event trigger input,

20 µA or GIO

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/

55

I/O

Pullup

Programmable, ADC2 event trigger input,

EQEP1I/N2HET2_PIN_nDIS

20 µA

or GIO

AD1IN[0]

60

71

73

74

76

78

80

61

83

70

72

75

77

79

82

85

58

59

62

63

64

65

81

84

51

Input

–

None

ADC1 analog input

AD1IN[01]

AD1IN[02]

AD1IN[03]

AD1IN[04]

AD1IN[05]

AD1IN[06]

AD1IN[07]

AD1IN[08] / AD2IN[08]

AD1IN[09] / AD2IN[09]

AD1IN[10] / AD2IN[10]

AD1IN[11] / AD2IN[11]

AD1IN[12] / AD2IN[12]

AD1IN[13] / AD2IN[13]

AD1IN[14] / AD2IN[14]

AD1IN[15] / AD2IN[15]

AD1IN[16] / AD2IN[0]

AD1IN[17] / AD2IN[01]

AD1IN[18] / AD2IN[02]

AD1IN[19] / AD2IN[03]

AD1IN[20] / AD2IN[04]

AD1IN[21] / AD2IN[05]

AD1IN[22] / AD2IN[06]

AD1IN[23] / AD2IN[07]

MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2

Input

–

None

ADC1/ADC2 shared

analog inputs

Output

Pullup

–

AWM1 external analog

mux enable

MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A

52

53

AWM1 external analog

mux select line0

AWM1 external analog

mux select line0

(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

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4.2.1.2 Enhanced High-End Timer (N2HET) Modules

Table 4-2. PGE Enhanced High-End Timer (N2HET) Modules

TERMINAL

DESCRIPTION

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

144

SIGNAL NAME

PGE

N2HET1[0]/SPI4CLK/EPWM2B

N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A

N2HET1[02]/SPI4SIMO[0]/EPWM3A

N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B

N2HET1[04]/EPWM4B

25

23

30

24

36

N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B

N2HET1[06]/SCIRX/EPWM5A

N2HET1[07]/N2HET2[14]/EPWM7B

N2HET1[08]/MIBSPI1SIMO[1]/

N2HET1[09]/N2HET2[16]/EPWM7A

N2HET1[10]/nTZ3

31

38

33

106

35

Pulldown

118

6

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO

N2HET1[12]

124

39

N2HET1[13]/SCITX/EPWM5B

N2HET1[14]

N2HET1 timer input

capture

or

output

125

41

compare, or GIO.

N2HET1[15]/MIBSPI1NCS[4]/ECAP1

N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO

MIBSPI1NCS[1]/N2HET1[17]/EQEP1S

N2HET1[18]/EPWM6A

Programmable,

20 µA

I/O

Each terminal has

suppression filter with a

programmable duration.

a

139

130

140

40

Pullup

Pulldown

Pullup

MIBSPI1NCS[2]/N2HET1[19]

N2HET1[20]/EPWM6B

141

15

Pulldown

N2HET1[22]

MIBSPI1NENA/N2HET1[23]/ECAP4

N2HET1[24]/MIBSPI1NCS[5]

MIBSPI3NCS[1]/N2HET1[25]

N2HET1[26]

96

Pullup

Pulldown

Pullup

91

37

92

Pulldown

Pullup

MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2

N2HET1[28]

4

107

3

Pulldown

Pullup

MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1

N2HET1[30]/EQEP2S

127

54

Pulldown

Pullup

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B

Disable selected PWM

outputs

GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS

14

Pulldown

Pullup

GIOA[2]/N2HET2[0]/EQEP2I

9

GIOA[6]/N2HET2[4]/EPWM1B

16

22

23

24

31

33

35

6

GIOA[7]/N2HET2[6]EPWM2A

N2HET2 timer input

capture

or

output

N2HET1[01]/SPI4NENA//N2HET2[8]

N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B

N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EQEP3B

N2HET1[07]/N2HET2[14]/EPWM7B

N2HET1[09]/N2HET2[16]

compare, or GIO

Programmable,

20 µA

I/O

Each terminal has

suppression filter with a

programmable duration.

a

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO

Disable selected PWM

outputs

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1l/N2HET2_PIN_nDIS

55

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4.2.1.3 Enhanced Capture Modules (eCAP)

Table 4-3. PGE Enhanced Capture Modules (eCAP)⁽¹⁾

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

144

PGE

SIGNAL NAME

Enhanced Capture Module 1

I/O

N2HET1[15]/MIBSPI1NCS[4]/ECAP1

41

51

Pulldown

Enhanced Capture Module 2

I/O

MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2

MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3

MIBSPI1NENA/N2HET1[23]/ECAP4

Enhanced Capture Module 3

I/O

52

I/O

Fixed, 20 µA

Enhanced Capture Module 4

I/O

96

Pullup

Enhanced Capture Module 5

I/O

MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6

97

Enhanced Capture Module 6

I/O

105

(1) These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

4.2.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP)⁽¹⁾

TERMINAL

RESET

SIGNAL

TYPE

PULL

STATE

PULL TYPE

DESCRIPTION

144

PGE

SIGNAL NAME

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS

MIBSPI1NCS[1]/N2HET1[17]//EQEP1S

N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A

N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B

GIOA[2]/N2HET2[0]/EQEP2I

53

54

55

130

23

24

9

Input

I/O

Enhanced QEP1 Input A

Enhanced QEP1 Input B

Enhanced QEP1 Index

Enhanced QEP1 Strobe

Enhanced QEP2 Input A

Enhanced QEP2 Input B

Enhanced QEP2 Index

Enhanced QEP2 Strobe

Pullup

I/O

Fixed, 20 µA

Input

I/O

Pulldown

N2HET1[30]/EQEP2S

127

I/O

(1) These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.

14

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4.2.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

144

PGE

SIGNAL NAME

GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS

GIOA[6]/N2HET2[4]/EPWM1B

14

16

Enhanced PWM1 Output A

Enhanced PWM1 Output B

Output

Input

Pulldown

Pullup

–

External ePWM Sync Pulse

Output

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO

N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO

6

External ePWM Sync Pulse

Output

139

Fixed, 20 µA

GIOA[7]/N2HET2[6]/EPWM2A

N2HET1[0]/SPI4CLK/EPWM2B

N2HET1[02]/SPI4SIMO[0]/EPWM3A

N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B

MIBSPI5NCS[0]/EPWM4A

22

25

30

31

32

36

38

39

140

141

35

33

3

Enhanced PWM2 Output A

Enhanced PWM2 Output B

Enhanced PWM3 Output A

Enhanced PWM3 Output B

Enhanced PWM4 Output A

Enhanced PWM4 Output B

Enhanced PWM5 Output A

Enhanced PWM5 Output B

Enhanced PWM6 Output A

Enhanced PWM6 Output B

Enhanced PWM7 Output A

Enhanced PWM7 Output B

Output

Pulldown

Pullup

–

N2HET1[04]/EPWM4B

N2HET1[06]/SCIRX/EPWM5A

N2HET1[13]/SCITX/EPWM5B

N2HET1[18]/EPWM6A

Output

Pulldown

–

N2HET1[20]/EPWM6B

N2HET1[09]/N2HET2[16]/EPWM7A

N2HET1[07]/N2HET2[14]/EPWM7B

MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1

MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2

Trip Zone Inputs 1, 2 and 3.

These signals are either

connected asynchronously to

the ePWMx trip zone inputs,

or double-synchronized with

VCLK4, or double-

Pullup

4

Input

Fixed, 20 µA

synchronized and then filtered

with a 6-cycle VCLK4-based

counter before connecting to

the ePWMx trip zone inputs.

N2HET1[10]/nTZ3

118

Pulldown

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4.2.1.6 General-Purpose Input/Output (GIO)

Table 4-6. PGE General-Purpose Input/Output (GIO)

Terminal

Signal Name

Signal Reset Pull

Pull Type

Description

Type

State

144 PGE

GIOA[0]

GIOA[1]

2

5

GIOA[2]/N2HET2[0]/EQEPII

9

GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS

14

General-purpose I/O.

All GIO terminals are

GIOA[6]/N2HET2[4]/EPWM1B

16

Pulldown

Programmable, capable of generating

GIOA[7]/N2HET2[6]/EPWM2A

22

I/O

20 µA

interrupts to the CPU

on rising / falling /

both edges.

GIOB[0]

126

133

142

55⁽¹⁾

1

GIOB[1]

GIOB[2]

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS

Pullup

GIOB[3]

Pulldown

(1) GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt

whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the

GIO module control registers.

4.2.1.7 Controller Area Network Controllers (DCAN)

Table 4-7. PGE Controller Area Network Controllers (DCAN)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

CAN1RX

CAN1TX

CAN2RX

CAN2TX

CAN3RX

CAN3TX

90

89

I/O

Pullup

Programmable, CAN1 receive, or GIO

20 µA

CAN1 transmit, or GIO

129

128

12

CAN2 receive, or GIO

CAN2 transmit, or GIO

CAN3 receive, or GIO

CAN3 transmit, or GIO

13

4.2.1.8 Local Interconnect Network Interface Module (LIN)

Table 4-8. PGE Local Interconnect Network Interface Module (LIN)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

LINRX

LINTX

131

132

I/O

Pullup

Programmable, LIN receive, or GIO

20 µA

LIN transmit, or GIO

16

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4.2.1.9 Standard Serial Communication Interface (SCI)

Table 4-9. PGE Standard Serial Communication Interface (SCI)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

N2HET1[06]/SCIRX/EPWM5A

N2HET1[13]/SCITX/EPWM5B

38

39

I/O

Pulldown Programmable, SCI receive, or GIO

20 µA

SCI transmit, or GIO

4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)

Table 4-10. PGE Inter-Integrated Circuit Interface Module (I2C)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2

MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1

4

3

I/O

Pullup

Programmable, I2C serial data, or GIO

20 µA

I2C serial clock, or GIO

4.2.1.11 Standard Serial Peripheral Interface (SPI)

Table 4-11. PGE Standard Serial Peripheral Interface (SPI)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

N2HET1[0]/SPI4CLK/EPWM2B

25

24

23

30

I/O

Pulldown Programmable, SPI4 clock, or GIO

20 µA

N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B

N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A

N2HET1[02]/SPI4SIMO[0]/EPWM3A

SPI4 chip select, or GIO

SPI4 enable, or GIO

SPI4 slave-input master-

output, or GIO

N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B

31

SPI4 slave-output master-

input, or GIO

Terminal Configuration and Functions

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4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-12. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

MIBSPI1CLK

95

105

130

40

I/O

Pullup

Programmable, MibSPI1 clock, or GIO

20 µA

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6

MIBSPI1NCS[1]/N2HET1[17]//EQEP1S

MIBSPI1NCS[2]/N2HET1[19]/

MibSPI1 chip select, or

GIO

N2HET1[15]/MIBSPI1NCS[4]/ECAP1

N2HET1[24]/MIBSPI1NCS[5]

41

Pulldown Programmable, MibSPI1 chip select, or

20 µA GIO

91

MIBSPI1NENA/N2HET1[23]/ECAP4

MIBSPI1SIMO[0]

96

Pullup

Programmable, MibSPI1 enable, or GIO

20 µA

93

MibSPI1 slave-in master-

out, or GIO

N2HET1[08]/MIBSPI1SIMO[1]

106

Pulldown Programmable, MibSPI1 slave-in master-

20 µA out, or GIO

MIBSPI1SOMI[0]

94

105

53

Pullup

Programmable, MibSPI1 slave-out master-

20 µA in, or GIO

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6

MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A

I/O

Pullup

Programmable, MibSPI3 clock, or GIO

20 µA

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD

55

MibSPI3 chip select, or

IS

GIO

MIBSPI3NCS[1]/N2HET1[25]

37

4

MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2

MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO

3

6

Pulldown Programmable, MibSPI3 chip select, or

20 µA GIO

MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B

54

Pullup

Programmable, MibSPI3 chip select, or

20 µA

GIO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B

MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3

54

52

MibSPI3 enable, or GIO

MibSPI3 slave-in master-

out, or GIO

MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2

51

MibSPI3 slave-out master-

in, or GIO

MIBSPI5CLK

100

32

I/O

Pullup

Programmable, MibSPI5 clock, or GIO

20 µA

MIBSPI5NCS[0]/EPWM4A

MibSPI5 chip select, or

GIO

MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5

MIBSPI5SIMO[0]/MIBSPI5SOMI[2]

97

99

MibSPI5 enable, or GIO

MibSPI5 slave-in master-

out, or GIO

MIBSPI5SOMI[0]

98

MibSPI5 slave-out master-

in, or GIO

MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5

MIBSPI5SIMO[0]/MIBSPI5SOMI[2]

97

99

MibSPI5 SOMI[0], or GIO

18

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4.2.1.13 System Module Interface

Table 4-13. PGE System Module Interface

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

144

PGE

SIGNAL NAME

Power-on reset, cold reset

External power supply monitor

circuitry must drive nPORRST

low when any of the supplies

to the microcontroller fall out

of the specified range. This

terminal has a glitch filter.

See Section 6.8.

nPORRST

46

Input

Pulldown

100 µA

System reset, warm reset,

bidirectional.

The internal circuitry indicates

any reset condition by driving

nRST low.

The external circuitry can

assert a system reset by

driving nRST low. To ensure

that an external reset is not

arbitrarily generated, TI

recommends that an external

pullup resistor is connected to

this terminal.

nRST

116

I/O

Pullup

100 µA

This terminal has a glitch

filter. See Section 6.8.

ESM Error Signal

nERROR

117

I/O

Pulldown

20 µA

Indicates error of high

severity. See Section 6.8.

4.2.1.14 Clock Inputs and Outputs

Table 4-14. PGE Clock Inputs and Outputs

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

OSCIN

18

Input

–

None

From external

crystal/resonator, or

external clock input

KELVIN_GND

OSCOUT

19

20

Input

Kelvin ground for oscillator

Output

To external

crystal/resonator

ECLK

119

14

I/O

Pulldown Programmable, External prescaled clock

20 µA

output, or GIO.

GIOA[5]/EXTCLKIN1/EPWM1A /N2HET1_PIN_nDIS

Input

Pulldown

20 µA

External clock input #1

Terminal Configuration and Functions

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4.2.1.15 Test and Debug Modules Interface

Table 4-15. PGE Test and Debug Modules Interface

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

TEST

34

Input

Pulldown

Fixed, 100 µA Test enable. This terminal

must be connected to

ground directly or via a

pulldown resistor.

nTRST

RTCK

TCK

109

113

112

110

111

108

Input

Output

Input

JTAG test hardware reset

-

None

JTAG return test clock

Pulldown

Pullup

Fixed, 100 µA JTAG test clock

JTAG test data in

TDI

Input

TDO

TMS

Output

Input

Pulldown

Pullup

JTAG test data out

JTAG test select

4.2.1.16 Flash Supply and Test Pads

Table 4-16. PGE Flash Supply and Test Pads

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

VCCP

134

3.3-V

Power

–

None

Flash pump supply

FLTP1

FLTP2

7

8

–

Flash test pads. These

terminals are reserved for

TI use only. For proper

operation these terminals

must connect only to a

test pad or not be

connected at all [no

connect (NC)].

4.2.1.17 Supply for Core Logic: 1.2V nominal

Table 4-17. PGE Supply for Core Logic: 1.2V nominal

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

VCC

17

29

1.2-V

Power

–

None

Core supply

45

48

49

57

87

101

114

123

137

143

20

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4.2.1.18 Supply for I/O Cells: 3.3V nominal

Table 4-18. PGE Supply for I/O Cells: 3.3V nominal

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

VCCIO

10

26

3.3-V

Power

–

None

Operating supply for I/Os

42

104

120

136

4.2.1.19 Ground Reference for All Supplies Except VCCAD

Table 4-19. PGE Ground Reference for All Supplies Except VCCAD

Terminal

Signal Reset Pull

Pull Type

Description

Type

State

Signal Name

144

PGE

VSS

11

21

Ground

–

None

Ground reference

27

28

43

44

47

50

56

88

102

103

115

121

122

135

138

144

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4.2.2 PZ Package Terminal Functions

4.2.2.1 High-End Timer (N2HET) Modules

Table 4-20. PZ Enhanced High-End Timer (N2HET) Modules

TERMINAL

SIGNAL

TYPE

RESET

PULL

STATE

PULL TYPE

DESCRIPTION

SIGNAL NAME

100 PZ

N2HET1[0]/ SPI4CLK / EPWM2B

N2HET1[2] / SPI4SIMO / EPWM3A

N2HET1[4] / EPWM4B

N2HET1[6] / SCIRX / EPWM5A

N2HET1[8] / MIBSPI1SIMO[1]

N2HET1[10] / nTZ3

19

22

25

26

74

83

89

90

97

I/O

Pulldown

Programmable,

20 µA

N2HET2 timer input capture or output

compare, or GIO.

Each terminal has a suppression filter with a

programmable duration.

Timer input capture or output compare. The N2HET

applicable terminals can be programmed as

general-purpose input/output (GIO).

N2HET1[12]

N2HET1[14]

N2HET1[16] / EPWM1SYNCI /

EPWM1SYNCO

MIBSPI1nCS[1] / N2HET1[17] / EQEP1S

N2HET1[18] / EPWM6A

93

98

27

39

11

68

64

37

Pullup

Pulldown

Pullup

MIBSPI1nCS[2] / N2HET1[19]

MIBSPI1nCS[3] / N2HET1[21]

N2HET1[22]

Pulldown

Pullup

MIBSPI1nENA / N2HET1[23] / ECAP4

N2HET1[24] / MIBSPI1nCS[5]

Pulldown

Pullup

MIBSPI3nENA / MIBSPI3nCS[5] /

N2HET1[31] / EQEP1B

GIOA[5] / INT[5] / EXTCLKIN

/EPWM1A/N2HET1_PIN_nDIS

10

Pulldown

Disable selected PWM outputs

GIOA[2] / INT[2] / N2HET2[0] / EQEP2I

GIOA[3] / INT[3] / N2HET2[2]

5

8

N2HET2 timer input capture or output

compare, or GIO.

GIOA[6] / INT[6] / N2HET2[4] / EPWM1B

GIOA[7] / INT[7] / N2HET2[6] / EPWM2A

12

18

Each terminal has a suppression filter with a

programmable duration.

Timer input capture or output compare. The N2HET

applicable terminals can be programmed as

general-purpose input/output (GIO).

4.2.2.2 Enhanced Capture Modules (eCAP)

Table 4-21. PZ Enhanced Capture Modules (eCAP)

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

MIBSPI3SOMI[0] /

AWM1_EXT_ENA / ECAP2

34

35

68

73

I/O

Pullup

Fixed, 20 µA

Enhanced Capture Module 2 I/O

Enhanced Capture Module 3 I/O

Enhanced Capture Module 4 I/O

Enhanced Capture Module 6 I/O

MIBSPI3SIMO[0] /

AWM1_EXT_SEL[0] / ECAP3

MIBSPI1NENA / N2HET1[23] /

ECAP4

MIBSPI1NCS[0] /

MIBSPI1SOMI[1] / ECAP6

22

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4.2.2.3 Enhanced Quadrature Encoder Pulse Modules (eQEP)

Table 4-22. PZ Enhanced Quadrature Encoder Pulse Modules (eQEP)

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

Enhanced QEP1 Input A

100 PZ

SIGNAL NAME

MIBSPI3CLK / AWM1_EXT_SEL[1] /

36

I/O

Pullup

Fixed, 20 µA

EQEP1A

MIBSPI3nENA / MIBSPI3nCS[5] /

N2HET1[31] / EQEP1B

37

38

93

5

Enhanced QEP1 Input B

Enhanced QEP1 Index

Enhanced QEP1 Strobe

Enhanced QEP2 Index

MIBSPI3nCS[0] / AD2EVT / GIOB[2]

/ EQEP1I/N2HET2_PIN_nDIS

MIBSPI1nCS[1] / N2HET1[17] /

EQEP1S

GIOA[2] / INT[2] / N2HET2[0] /

Pulldown

EQEP2I

4.2.2.4 Enhanced Pulse-Width Modulator Modules (ePWM)

Table 4-23. PZ Enhanced Pulse-Width Modulator Modules (ePWM)

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

Enhanced PWM1 Output A

SIGNAL NAME

100 PZ

GIOA[5] / INT[5] / EXTCLKIN /

EPWM1A/N2HET1_PIN_nDIS

10

Output

Pulldown

–

GIOA[6] / INT[6] / N2HET2[4] /

EPWM1B

12

97

18

Enhanced PWM1 Output B

N2HET1[16] / EPWM1SYNCI /

EPWM1SYNCO

Input

Fixed, 20 µA

–

External ePWM Sync Pulse Input

External ePWM Sync Pulse Output

Enhanced PWM2 Output A

N2HET1[16] / EPWM1SYNCI /

EPWM1SYNCO

Output

GIOA[7] / INT[7] / N2HET2[6] /

EPWM2A

N2HET1[0] / SPI4CLK / EPWM2B

N2HET1[2] / SPI4SIMO / EPWM3A

N2HET1[4] / EPWM4B

19

22

25

26

98

83

Enhanced PWM2 Output B

Enhanced PWM3 Output A

Enhanced PWM4 Output B

Enhanced PWM5 Output A

Enhanced PWM6 Output A

Trip Zone 1 input 3

N2HET1[6] / SCIRX / EPWM5A

N2HET1[18] / EPWM6A

N2HET1[10] / nTZ3

Input

Pulldown

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4.2.2.5 General-Purpose Input/Output (GIO)

Table 4-24. PZ General-Purpose Input/Output (GIO)

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

GIOA

GIOA[0] / INT[0]

GIOA[1] / INT[1]

1

2

5

I/O

Pulldown

Programmable,

20 µA

General-purpose input/output

All GPIO terminals are capable of generating

interrupts to the CPU on rising/falling/both edges.

GIOA[2] / INT[2] / N2HET2[0] /

EQEP2I

GIOA[3] / INT[3] / N2HET2[2]

GIOA[4]/ INT[4]

8

9

GIOA[5] / INT[5] / EXTCLKIN /

10

EPWM1A/ N2HET1_PIN_nDIS

GIOA[6] / INT[6] / N2HET2[4] /

EPWM1B

12

18

GIOA[7] / INT[7] / N2HET2[6] /

EPWM2A

GIOB

MIBSPI3nCS[0] / AD2EVT /

GIOB[2] /

38

I/O

General-purpose input/output

EQEP1I/N2HET2_PIN_nDIS

4.2.2.6 Controller Area Network Interface Modules (DCAN1, DCAN2)

Table 4-25. PZ Controller Area Network Interface Modules (DCAN1, DCAN2)

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

DCAN1

CAN1RX

CAN1TX

63

62

I/O

Pullup

Programmable,

20 µA

CAN1 Receive, or general-purpose I/O (GPIO)

CAN1 Transmit, or GPIO

DCAN2

CAN2RX

CAN2TX

92

91

Programmable,

20 µA

CAN2 Receive, or GPIO

CAN2 Transmit, or GPIO

24

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4.2.2.7 Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Table 4-26. PZ Standard Serial Peripheral Interfaces (SPI2 and SPI4)

Terminal

Signal Type Reset Pull

State

Pull Type

Description

Signal Name

100 PZ

SPI2

SPI2CLK

71

23

70

69

I/O

Pullup

Programmable, 20 µA SPI2 Serial Clock, or GPIO

SPI2 Chip Select, or GPIO

SPI2nCS[0]

SPI2SIMO

SPI2SOMI

SPI2 Slave-In-Master-Out, or GPIO

SPI2 Slave-Out-Master-In, or GPIO

The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register

fo SPI2.

SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.

SRS = 1 for 2mA drive (slow)

SPI4

N2HET1[0] / SPI4CLK / EPWM2B

N2HET1[2] / SPI4SIMO / EPWM3A

19

22

I/O

Pulldown

Programmable, 20 µA SPI2 Serial Clock, or GPIO

SPI2 Slave-In-Master-Out, or GPIO

4.2.2.8 Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Table 4-27. PZ Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100 PZ

MibSPI1

Pullup

MIBSPI1CLK

67

73

I/O

Programmable, 20 µA MibSPI1 Serial Clock, or GPIO

MibSPI1 Chip Select, or GPIO

MIBSPI1nCS[0]/MIBSPI1SOMI[1]/

ECAP6

MIBSPI1nCS[1]/N2HET1[17]/

93

EQEP1S

MIBSPI1nCS[2]/N2HET1[19]

MIBSPI1nCS[3]/N2HET1[21]

27

39

68

MIBSPI1nENA/N2HET1[23]/

MibSPI1 Enable, or GPIO

ECAP4

MIBSPI1SIMO[0]

65

74

66

73

MibSPI1 Slave-In-Master-Out, or GPIO

N2HET1[8]/MIBSPI1SIMO[1]

MIBSPI1SOMI[0]

MibSPI1 Slave-Out-Master-In, or GPIO

MIBSPI1nCS[0]/MIBSPI1SOMI[1]/

ECAP6

MibSPI3

Pullup

MIBSPI3CLK/AWM1_EXT_SEL[1]/

EQEP1A

36

38

37

35

34

I/O

Programmable, 20 µA MibSPI3 Serial Clock, or GPIO

MibSPI3 Chip Select, or GPIO

MIBSPI3nCS[0]/AD2EVT/GIOB[2]/

EQEP1I/N2HET2_PIN_nDIS

MIBSPI3nENA/MIBSPI3nCS[5]/

N2HET1[31]/EQEP1B

MIBSPI3nENA/MIBSPI3nCS[5]/

N2HET1[31]/EQEP1B

MibSPI3 Enable, or GPIO

MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/

ECAP3

MibSPI3 Slave-In-Master-Out, or GPIO

MibSPI3 Slave-Out-Master-In, or GPIO

MIBSPI3SOMI[0]/AWM1_EXT_ENA/

ECAP2

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4.2.2.9 Local Interconnect Network Controller (LIN)

Table 4-28. PZ Local Interconnect Network Controller (LIN)

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

SIGNAL NAME

100 PZ

LINRX

LINTX

94

95

I/O

Pullup

Programmable, 20 µA

LIN Receive, or GPIO

LIN Transmit, or GPIO

4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)

Table 4-29. PZ Multibuffered Analog-to-Digital Converter (MibADC)

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

MibADC1

AD1EVT

58

I/O

Pulldown

Programmable,

20 µA

ADC1 Event Trigger or GPIO

Analog Inputs

AD1IN[0]

42

49

51

52

54

55

56

43

57

48

50

53

40

41

44

45

46

Input

–

AD1IN[1]

AD1IN[2]

AD1IN[3]

AD1IN[4]

AD1IN[5]

AD1IN[6]

AD1IN[7]

AD1IN[8]/AD2IN[8]

AD1IN[9]/AD2IN[9]

AD1IN[10]/AD2IN[10]

AD1IN[11]/AD2IN[11]

AD1IN[16]/AD2IN[0]

AD1IN[17]/AD2IN[1]

AD1IN[20]/AD2IN[4]

AD1IN[21]/AD2IN[5]

ADREFHI/VCCAD

Input/

Power

–

ADC High Reference Level/ADC Operating

Supply

ADREFLO/VSSAD

47

34

Input/

Ground

ADC Low Reference Level/ADC Supply Ground

MIBSPI3SOMI[0]/AWM1_EXT_

AWM external analog mux enable

ENA/

ECAP2

MIBSPI3SIMO[0]/AWM1_EXT_

SEL[0]/

ECAP3

35

36

AWM external analog mux select line 0

AWM external analog mux select line1

MIBSPI3CLK/AWM1_EXT_SEL

[1]/

EQEP1A

MibADC2

MIBSPI3nCS[0]/AD2EVT/GIOB[

2]/

38

I/O

ADC2 Event Trigger or GPIO

EQEP1I/N2HET2_PIN_nDIS

26

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4.2.2.11 System Module Interface

Table 4-30. PZ System Module Interface

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

SIGNAL NAME

100 PZ

Power-on reset, cold reset External power supply

monitor circuitry must drive nPORRST low when any of

the supplies to the microcontroller fall out of the

specified range. This terminal has a glitch filter. See

Section 6.8.

nPORRST

31

Input

Pullup

100 µA

The external circuitry can assert a system reset by

driving nRST low. To ensure that an external reset is not

arbitrarily generated, TI recommends that an external

pullup resistor is connected to this terminal. This

terminal has a glitch filter. See Section 6.8.

nRST

81

82

I/O

Pullup

100 µA

20 µA

ESM Error Signal. Indicates error of high severity. See

Section 6.8.

nERROR

Pulldown

4.2.2.12 Clock Inputs and Outputs

Table 4-31. PZ Clock Inputs and Outputs

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

SIGNAL NAME

100 PZ

OSCIN

14

15

16

84

Input

Output

I/O

–

From external crystal/resonator, or external clock input

Dedicated ground for oscillator

KELVIN_GND

OSCOUT

ECLK

–

To external crystal/resonator

Pulldown

Programmable, 20 µA External prescaled clock output, or GIO.

20 µA External Clock In

GIOA[5]/INT[5]/EXTCLKIN/EPWM1A

/N2HET1_PIN_nDIS

10

Input

Pulldown

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4.2.2.13 Test and Debug Modules Interface

Table 4-32. PZ Test and Debug Modules Interface

TERMINAL

RESET

PULL

STATE

SIGNAL

TYPE

PULL TYPE

DESCRIPTION

SIGNAL NAME

100 PZ

nTRST

RTCK

TCK

76

80

79

77

78

75

Input

Output

Input

I/O

Pulldown

–

Fixed, 100 µA

–

JTAG test hardware reset

JTAG return test clock

JTAG test clock

Pulldown

Pullup

Pulldown

Pullup

Fixed, 100 µA

TDI

JTAG test data in

JTAG test data out

JTAG test select

TDO

TMS

I/O

Test enable. This terminal must be connected to ground

directly or via a pulldown resistor.

TEST

24

I/O

Pulldown

Fixed, 100 µA

4.2.2.14 Flash Supply and Test Pads

Table 4-33. PZ Flash Supply and Test Pads

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

VCCP

96

3.3-V

Power

–

Flash external pump voltage (3.3 V). This

terminal is required for both Flash read and Flash

program and erase operations.

FLTP1

FLTP2

3

4

Input

–

Flash Test Pins. For proper operation this

terminal must connect only to a test pad or not be

connected at all [no connect (NC)].

The test pad must not be exposed in the final

product where it might be subjected to an ESD

event.

4.2.2.15 Supply for Core Logic: 1.2-V Nominal

Table 4-34. PZ Supply for Core Logic: 1.2-V Nominal

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

VCC

13

21

30

32

61

88

99

1.2-V

Power

–

Digital logic and RAM supply

4.2.2.16 Supply for I/O Cells: 3.3-V Nominal

Table 4-35. PZ Supply for I/O Cells: 3.3-V Nominal

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

VCCIO

6

3.3-V

Power

–

I/O Supply

28

60

85

28

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4.2.2.17 Ground Reference for All Supplies Except VCCAD

Table 4-36. PZ Ground Reference for All Supplies Except VCCAD

Terminal

Signal

Type

Reset Pull

State

Pull Type

Description

Signal Name

100

PZ

VSS

7

17

20

29

33

59

72

86

87

100

Ground

–

Device Ground Reference. This is a single

ground reference for all supplies except for the

ADC Supply.

4.3 Pin Multiplexing

This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as

required by the target application. The multiplexing is mostly on the output signals. A few inputs are also

multiplexed to allow the same input signal to be driven in from a selected terminal.

4.3.1 Output Multiplexing

Table 4-37 and Table 4-38 show the pin multiplexing control x register (PINMMRx) and the associated bit

fields that control each pin mux function.

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4.3.2 Multiplexing of Inputs

Some signals are connected to more than one terminal, the inputs for these signals can come from any of

the terminals. A multiplexor is implemented to let the application choose the terminal that will be used,

providing the input signal is from among the available options.

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4.4 Buffer Type

Table 4-40. Output Buffer Drive Strengths

Low-level Output Current, I_OLfor V_I= V_OLmax

or

Signals

High-level Output Current, I_OHfor V_I= V_OHmin

MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],

MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],

TMS, TDI, TDO, RTCK,

SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR,

N2HET2[1], N2HET2[3], N2HET2[5], N2HET2[7], N2HET2[9], N2HET2[11],

N2HET2[13], N2HET2[15]

8mA

ECAP1, ECAP4, ECAP5, ECAP6

EQEP1I, EQEP1S, EQEP2I, EQEP2S

EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B,

EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B

TEST,

MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI,

MIBSPI1CLK,

4mA

ECAP2, ECAP3

nRST

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,

GIOA[0-7], GIOB[0-7],

2mA zero-dominant

LINRX, LINTX,

MIBSPI1NCS[0],

MIBSPI1NCS[1-3],

MIBSPI1NENA,

MIBSPI3NCS[0-3],

MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA,

N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6], N2HET2[8],

N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18],

ECLK,

selectable 8mA / 2mA

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8mA for these signals.

Table 4-41. Selectable 8mA/2mA Control

SIGNAL

ECLK

CONTROL BIT

ADDRESS

0xFFFF FF78

0xFFF7 F668

8mA (DEFAULT)

2mA

SYSPC10[0]

SPI2PC9[9]

0

1

SPI2CLK

SPI2SIMO

SPI2SOMI

SPI2PC9[10]

SPI2PC9[11]⁽¹⁾

(1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits

differ, SPI2PC9[11] determines the drive strength.

Terminal Configuration and Functions

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5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

Over Operating Free-Air Temperature Range

MIN

–0.3

MAX

1.43

4.6

UNIT

(2)

V_CC

(2)

Supply voltage range:

V_CCIO, V_CCP

V

(2)

V_CCAD

6.25

4.6

All input pins, with exception of ADC pins

ADC input pins

Input voltage

V

6.25

4.6

Output voltage

All output pins

I_IK(V_I< 0 or V_I> V_CCIO

All pins, except AD1IN[23:0] or AD2IN[15:0]

)

–20

20

Input clamp current

I_IK(V_I< 0 or V_I> V_CCAD

AD1IN[23:0] or AD2IN[15:0]

)

mA

–10

–40

–20

–40

10

40

Total

I_OK(V_O< 0 or V_O> V_CCIO

All pins, except AWM1_EXT_x

)

20

Output clamp current

mA

°C

Total

40

Operating free-air

temperature (T_A)

125

Operating junction

temperature (T_J)

–40

–65

150

°C

Storage temperature (T_stg

)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated

grounds.

5.2 ESD Ratings

VALUE

±2

UNIT

Human Body Model (HBM), per AEC Q100-002⁽¹⁾

All pins

kV

V

±500

Electrostatic discharge (ESD)

performance:

100-pin PZ corner pins (1, 25, 26, 50,

51, 75, 76, 100)

V_(ESD)

Charged Device Model (CDM),

per AEC Q100-011

±750

V

144-pin PGE corner pins (1, 36, 37, 72,

73, 108, 109, 144)

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.

5.3 Power-On Hours (POH)⁽¹⁾⁽²⁾

JUNCTION

TEMPERATURE (Tj)

NOMINAL CVDD VOLTAGE (V)

LIFETIME POH

1.2

105ºC

100K

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms

and conditions for TI semiconductor products.

(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to

equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application

Report (SPNA207).

36

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5.4 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

1.14

3

NOM

1.2

MAX UNIT

V_CC

Digital logic supply voltage (Core)

Digital logic supply voltage (I/O)

MibADC supply voltage

1.32

3.6

V

V_CCIO

V_CCAD

V_CCP

3.3

3

5.25

3.6

Flash pump supply voltage

3

3.3

0

V_SS

Digital logic supply ground

V_SSAD

V_ADREFHI

V_ADREFLO

MibADC supply ground

–0.1

V_SSAD

0.1

V_CCAD

Analog-to-digital high-voltage reference source

Analog-to-digital low-voltage reference source

Maximum positive slew rate for V_CCIO, V_CCADand

V_CPPsupplies

V_SLEW

1

V/μs

V_hys

V_IL

V_IH

T_A

Input hysteresis

All inputs

180

–0.3

2

mV

V

Low-level input voltage

High-level input voltage

Operating free-air temperature

Operating junction temperature⁽²⁾

0.8

V_CCIO+ 0.3

V

–40

125 °C

150 °C

T_J

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

(2) Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.

Specifications

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5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions⁽¹⁾

PARAMETER

TEST CONDITIONS

I_OL= I_OLmax

MIN

TYP

MAX UNIT

0.2V_CCIO

I_OL= 50 µA, standard output mode

0.2

V_OLLow-level output voltage

V

I_OL= 50 µA, low-EMI output mode

(see Section 7.1.2.1)

0.2V_CCIO

I_OH= I_OHmax

0.8V_CCIO

I_OH= 50 µA, standard output mode

V_CCIO- 0.3

V_OHHigh-level output voltage

V

I_OH= 50 µA, low-EMI output mode

(see Section 7.1.2.1)

0.8V_CCIO

–3.5

V_I< V_SSIO- 0.3 or

V_I> V_CCIO+ 0.3

I_IC

Input clamp current (I/O pins)

I_IHPulldown 20 µA

3.5 mA

V_I= V_CCIO

5

40

195

–5 µA

–40

1

I_IHPulldown 100 µA V_I= V_CCIO

I_I

Input current (I/O pins)

I_ILPullup 20 µA

V_I= V_SS

–40

–195

–1

I_ILPullup 100 µA

All other pins

V_I= V_SS

No pullup or pulldown

C_I

Input capacitance

Output capacitance

2

3

pF

C_O

pF

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

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5.6 Power Consumption Over Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

(2)

V_CCdigital supply current (operating mode)

f_VCLK= f_HCLK/2; Flash in pipelined mode;

V_CCmax

f_HCLK= 100 MHz

130

270

mA

(1)

(2)

f_HCLK= 160 MHz

160

300

LBIST/PBIST clock

frequency = 50 MHz

150⁽¹⁾

215⁽¹⁾

240⁽¹⁾

290⁽³⁾⁽⁴⁾

I_CC

LBIST/PBIST clock

frequency = 80 MHz

(3)(4)

V_CCdigital supply current (LBIST/PBIST mode)

360

mA

LBIST/PBIST clock

frequency = 90 MHz

(3)(4)

390

I_CCIO

V_CCIOdigital supply current (operating mode)

V_CCADsupply current (operating mode)

No DC load, V_CCmax

15

mA

Single ADC

operational,

V_CCADmax

I_CCAD

Both ADCs

operational,

V_CCADmax

30

3

Single ADC

operational,

AD_REFHImax

I_CCREFHI

AD_REFHIsupply current (operating mode)

mA

Both ADCs

operational,

AD_REFHImax

6

Read from 1 bank

and program

another bank,

V_CCPmax

I_CCP

V_CCPsupply current

55

(1) The typical value is the average current for the nominal process corner and junction temperature of 25°C.

(2) The maximum I_CC,value can be derated

•

linearly with voltage

by 0.85 mA/MHz for lower operating frequency when f_HCLK= 2 * f_VCLK

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

126 - 0.005 e^{0.024 T}

JK

(3) The maximum I_CC,value can be derated

•

linearly with voltage

by 0.85 mA/MHz for lower operating frequency

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

126 - 0.005 e^{0.024 T}

JK

(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the

device and the voltage regulator.

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5.7 Thermal Resistance Characteristics

Table 5-1 shows the thermal resistance characteristics for the QFP - PGE mechanical package.

Table 5-2 shows the thermal resistance characteristics for the QFP - PZ mechanical package.

Table 5-1. Thermal Resistance Characteristics (PGE Package)

°C/W

Junction-to-free air thermal resistance, still

RΘ_JA

37.5

air using JEDEC 2S2P test board

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Junction-to-package top, Still air

RΘ_JB

RΘ_JC

Ψ_JT

19.7

9.4

0.40

Table 5-2. Thermal Resistance Characteristics (PZ Package)

°C/W

Junction-to-free air thermal resistance, still

43.5

RΘ_JA

air using JEDEC 2S2P test board

RΘ_JB

RΘ_JC

Ψ_JT

Junction-to-board thermal resistance

Junction-to-case thermal resistance

Junction-to-package top, Still air

21.6

11.2

0.50

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5.8 Timing and Switching Characteristics

5.8.1 SYSCLK (Frequencies)

5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains

Table 5-3. Clock Domain Timing Specifications

PARAMETER

DESCRIPTION

HCLK - System clock frequency

GCLK - CPU clock frequency

CONDITIONS

MIN

MAX

100

45

UNIT

Pipeline mode enabled

Pipeline mode disabled

Pipeline mode enabled

Pipeline mode disabled

PZ

f_HCLK

MHz

160

50

PGE

f_GCLK

f_VCLK

f_VCLK2

f_VCLK4

f_VCLKA1

f_RTICLK

f_HCLK

MHz

VCLK - Primary peripheral clock

frequency

100

150

VCLK2 - Secondary peripheral clock

frequency

MHz

VCLK4 - Secondary peripheral clock

frequency

VCLKA1 - Primary asynchronous

peripheral clock frequency

100

MHz

RTICLK - Clock frequency

f_VCLK

Specifications

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5.8.1.2 Wait States Required - PGE and PZ Packages

w!a

!ddress íꢀit {tꢀtes

0 aIz

0

f_I/[Y(mꢀx)

5ꢀtꢀ íꢀit {tꢀtes

0 aIz

f_I/[Y(mꢀx)

Clꢀsh (aꢀin aemory)

!ddress íꢀit {tꢀtes

wí!LÇ {etting

0

1

0 aIz

1ꢁ0aIz f_I/[Y(mꢀx)

0

1

2

3

ꢁ0aIz

2

100aIz

ꢁ

1ꢁ0aIz f_I/[Y(mꢀx)

Clꢀsh (5ꢀtꢀ aemory)

9í!LÇ {etting

1

4

6

7

8

ꢂ

3

f

ꢂ0aIz 10ꢁaIz 120aIz 13ꢁaIz 1ꢁ0aIz

I/[Y(mꢀx)

0 aIz

4ꢁaIz

60aIz

7ꢁaIz

Figure 5-1. Wait States Scheme — PGE, 160 MHz

w!a

!ddress íꢀit {tꢀtes

0

0 aIz

f_I/[Y(mꢀx)

5ꢀtꢀ íꢀit {tꢀtes

0 aIz

f_I/[Y(mꢀx)

Clꢀsh (aꢀin aemory)

!ddress íꢀit {tꢀtes

0

0 aIz

f_I/[Y(mꢀx)

wí!LÇ {etting

0

1

ꢁ0aIz

f_I/[Y(mꢀx)

Clꢀsh (5ꢀtꢀ aemory)

9í!LÇ {etting

1

2

3

4

ꢁ

0 aIz

4ꢁaIz

60aIz

7ꢁaIz

ꢂ0aIz f_I/[Y(mꢀx)

Figure 5-2. Wait States Scheme — PZ, 100 MHz

As shown in Figure 5-1 and Figure 5-2, the TCM RAM can support program and data fetches at full CPU

speed without any address or data wait states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in

nonpipelined mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for

the PGE Package, and 100 MHz for the PZ package.

The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data

wait state.

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6 System Information and Electrical Specifications

6.1 Device Power Domains

The device core logic is split up into multiple power domains to optimize the power for a given application

use case. There are five core power domains: PD1, PD2, PD3, PD5, and RAM_PD1. See Section 1.4 for

more information.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains

can be turned ON/OFF one time during device initialization as per the application requirement. Refer to

the Power Management Module (PMM) chapter of the device technical reference manual for more details.

NOTE

The clocks to a module must be turned off before powering down the core domain that

contains the module.

6.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the

requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.2.1 Important Considerations

•

The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in

reset when the voltage supplies are out of range.

•

The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not

monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for

VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO

signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when

the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and

PGMCU signals being low isolates the core logic as well as the I/O controls during power up or power

down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When

the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output

pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device

enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing

information on this glitch filter.

Table 6-1. Voltage Monitoring Specifications

PARAMETER

VCC low - VCC level below this

MIN

TYP

MAX UNIT

0.75

0.9

1.13

threshold is detected as too low.

Voltage monitoring

thresholds

VCC high - VCC level above this

threshold is detected as too high.

V_MON

1.40

1.85

1.7

2.4

2.1

2.9

V

VCCIO low - VCCIO level below this

threshold is detected as too low.

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6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the

maximum specification cannot be filtered.

Table 6-2. VMON Supply Glitch Filtering Capability

PARAMETER

MIN

250

MAX

1000

UNIT

ns

Width of glitch on VCC that can be filtered

Width of glitch on VCCIO that can be filtered

ns

6.3 Power Sequencing and Power-On Reset

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for

more details), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

Table 6-3. Power-Up Phases

Oscillator start-up and validity check

eFuse autoload

1032 oscillator cycles

1160 oscillator cycles

688 oscillator cycles

617 oscillator cycles

3497 oscillator cycles

Flash pump power-up

Flash bank power-up

Total

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

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6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever any power

supply is outside the specified recommended range. This signal has a glitch filter on it. It also has an

internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

Table 6-4. Electrical Requirements for nPORRST

NO.

MIN

MAX

UNIT

V_CCPORL

V_CCPORH

V_CClow supply level when nPORRST must be active during power up

0.5

V

V_CChigh supply level when nPORRST must remain active during power

up and become active during power down

1.14

V

V_CCIO/ V_CCPlow supply level when nPORRST must be active during

power up

V_CCIOPORL

1.1

V_CCIO/ V_CCPhigh supply level when nPORRST must remain active

during power up and become active during power down

V_CCIOPORH

V_IL(PORRST)

3.0

Low-level input voltage of nPORRST V_CCIO> 2.5 V

Low-level input voltage of nPORRST V_CCIO< 2.5 V

0.2 * V_CCIO

0.5

V

Setup time, nPORRST active before V_CCIOand V_CCP> V_CCIOPORLduring

power up

3

t_su(PORRST)

0

ms

6

7

8

9

t_h(PORRST)

t_su(PORRST)

t_h(PORRST)

Hold time, nPORRST active after V_CC> V_CCPORH

1

2

1

0

ms

µs

Setup time, nPORRST active before V_CC< V_CCPORHduring power down

Hold time, nPORRST active after V_CCIOand V_CCP> V_CCIOPORH

Hold time, nPORRST active after V_CC< V_CCPORL

ms

Filter

time

nPORRST

pin;

t_f(nPORRST)

475

2000

ns

pulses less than MIN will be filtered out, pulses greater than MAX will

generate a reset.

3.3 V

1.2 V

V

V_CCIOPORH

CCIOPORH

V

/ V

CCP

CCIO

8

6

V

CC

V

CCPORH

7

6

V

7

CCIOPORL

V

CCPORL

V

(1.2 V)

CC

V

/ V

(3.3 V)

CCP

CCIO

3

9

V

IL

V

IL(PORRST)

IL

nPORRST

V

IL

A. Figure 6-1 shows that there is no timing dependency between the ramp of the V_CCIOand the V_CCsupply voltages.

Figure 6-1. nPORRST Timing Diagram^(A)

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6.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

6.4.1 Causes of Warm Reset

Table 6-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Exception Status Register, bit 15

Global Status Register, bit 0

Power-Up Reset

Oscillator fail

PLL slip

Global Status Register, bits 8 and 9

Exception Status Register, bit 13

Exception Status Register, bit 5

Exception Status Register, bit 4

Exception Status Register, bit 3

Watchdog exception / Debugger reset

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

6.4.2 nRST Timing Requirements

Table 6-6. nRST Timing Requirements⁽¹⁾

MIN

MAX

UNIT

Valid time, nRST active after nPORRST inactive

2256t_c(OSC)

t_v(RST)

ns

Valid time, nRST active (all other System reset

conditions)

32t_c(VCLK)

Filter

time

nRST

pin;

t_f(nRST)

475

2000

ns

pulses less than MIN will be filtered out, pulses greater

than MAX will generate a reset

(1) Specified values do not include rise/fall times. For rise and fall timings, see Table 7-2.

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6.5 ARM Cortex-R4F CPU Information

6.5.1 Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

•

An integer unit with integral EmbeddedICE-RT logic.

High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)

for Level two (L2) master and slave interfaces.

•

Floating-Point Coprocessor

Dynamic branch prediction with a global history buffer, and a 4-entry return stack

Low interrupt latency.

Nonmaskable interrupt.

A Harvard Level one (L1) memory system with:

–

Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking

memories

–

ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions

•

Dual core logic for fault detection in safety-critical applications.

An L2 memory interface:

–

Single 64-bit master AXI interface

64-bit slave AXI interface to TCM RAM blocks

•

A debug interface to a CoreSight Debug Access Port (DAP).

Six Hardware Breakpoints

Two Watchpoints

A Performance Monitoring Unit (PMU).

A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4F CPU, see www.arm.com.

6.5.2 ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

•

ECC On Tightly-Coupled Memory (TCM) Accesses

Hardware Vectored Interrupt (VIC) Port

Floating-Point Coprocessor

Memory Protection Unit (MPU)

6.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-

R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two

clock cycles as shown in Figure 6-2.

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Output + Control

CCM-R4

2 cycle delay

CCM-R4

compare

error

CPU1CLK

CPU 1

CPU 2

2 cycle delay

CPU2CLK

Input + Control

Figure 6-2. Dual Core Implementation

The CPUs have a diverse CPU placement given by following requirements:

•

different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation

•

dedicated guard ring for each CPU

Flip West

North

F

Figure 6-3. Dual-CPU Orientation

6.5.4 Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU

running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.

6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in

the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in

a different way as shown in Figure 6-2.

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of

both CPUs before the registers are used, including function calls where the register values are pushed

onto the stack.

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6.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the

Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

•

Ability to divide the complete test run into independent test intervals

Capable of running the complete test as well as running few intervals at a time

Ability to continue from the last executed interval (test set) as well as ability to restart from the

beginning (First test set)

•

Complete isolation of the self-tested CPU core from rest of the system during the self-test run

Ability to capture the Failure interval number

Time-out counter for the CPU self-test run as a fail-safe feature

6.5.6.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select number of test intervals to be run.

3. Configure the time-out period for the self-test run.

4. Enable self-test.

5. Wait for CPU reset.

6. In the reset handler, read CPU self-test status to identify any failures.

7. Retrieve CPU state if required.

For more information see the device Technical Reference Manual.

6.5.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is HCLKmax/2. The STCCLK is divided down from the CPU

clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device-specific Technical Reference Manual.

6.5.6.3 CPU Self-Test Coverage

Table 6-7 lists the CPU self-test coverage achieved for each self-test interval. It also lists the cumulative

test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock

period.

Table 6-7. CPU Self-Test Coverage

INTERVALS

TEST COVERAGE, %

STCCLK CYLCES

0

1

0

62.13

70.09

74.49

77.28

79.28

80.90

82.02

83.10

84.08

84.87

85.59

86.11

1365

2

2730

3

4095

4

5460

5

6825

6

8190

7

9555

8

10920

12285

13650

15015

16380

9

10

11

12

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Table 6-7. CPU Self-Test Coverage (continued)

INTERVALS

TEST COVERAGE, %

STCCLK CYLCES

17745

13

14

15

16

17

18

19

20

21

22

23

24

86.67

87.16

87.61

87.98

88.38

88.69

88.98

89.28

89.50

89.76

90.01

90.21

19110

20475

21840

23205

24570

25935

27300

28665

30030

31395

32760

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6.6 Clocks

6.6.1 Clock Sources

Table 6-8 lists the available clock sources on the device. Each clock source can be enabled or disabled

using the CSDISx registers in the system module. The clock source number in the table corresponds to

the control bit in the CSDISx register for that clock source.

Table 6-8 also shows the default state of each clock source.

Table 6-8. Available Clock Sources

CLOCK

SOURCE NO.

NAME

DESCRIPTION

DEFAULT STATE

0

1

2

3

4

OSCIN

PLL1

Main oscillator

Output from PLL1

Reserved

Enabled

Disabled

Enabled

Reserved

EXTCLKIN1

LFLPO

External clock input 1

Low-frequency output of internal reference oscillator

High-frequency output of internal reference

oscillator

5

HFLPO

Enabled

6

7

Reserved

Disabled

EXTCLKIN2

External clock input 2

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors

across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single-stage

inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test

measurement and low power modes.

NOTE

TI strongly encourages each customer to submit samples of the device to the

resonator/crystal vendors for validation. The vendors are equipped to determine which load

capacitors will best tune their resonator/crystal to the microcontroller device for optimum

start-up and operation over temperature and voltage extremes.

An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving

the OSCOUT pin unconnected (open) as shown in Figure 6-4.

(see Note B)

OSCIN

Kelvin_GND

OSCOUT

OSCIN

OSCOUT

C1

C2

External

Clock Signal

(toggling 0 V to 3.3 V)

(see Note A)

Crystal

(a)

(b)

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Note B: Kelvin_GND should not be connected to any other GND.

Figure 6-4. Recommended Crystal/Clock Connection

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6.6.1.1.1 Timing Requirements for Main Oscillator

Table 6-9. Timing Requirements for Main Oscillator

MIN

NOM

MAX

UNIT

tc(OSC)

Cycle time, OSCIN (when using a sine-wave input)

50

200

ns

Pulse duration, OSCIN low (when input to the OSCIN

is a square wave)

tw(OSCIL)

15

ns

Pulse duration, OSCIN high (when input to the OSCIN

is a square wave)

tw(OSCIH)

6.6.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single

macro.

6.6.1.2.1 Features

The main features of the LPO are:

•

Supplies a clock at extremely low power for power-saving modes. This is connected as clock source 4

of the Global Clock Module (GCM).

Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source 5 of

the GCM.

Provides a comparison clock for the crystal oscillator failure detection circuit.

BIAS_EN

LFEN

LFLPO

LF_TRIM

Low-Power

Oscillator

HFEN

HFLPO

HF_TRIM

HFLPO_VALID

nPORRST

Figure 6-5. LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO)

and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

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6.6.1.2.2 LPO Electrical and Timing Specifications

Table 6-10. LPO Specifications

PARAMETER

MIN

TYP

MAX

UNIT

Clock detection

Oscillator fail frequency - lower threshold, using untrimmed

LPO output

1.375

2.4

4.875

MHz

Oscillator fail frequency - higher threshold, using untrimmed

LPO output

22

38.4

78

MHz

LPO - HF oscillator

Untrimmed frequency

Trimmed frequency

5.5

8

9

19.5

11

MHz

9.6

Start-up time from STANDBY (LPO BIAS_EN high for at

least 900 µs)

10

µs

Cold start-up time

900

180

µs

LPO - LF oscillator

Untrimmed frequency

36

85

kHz

Start-up time from STANDBY (LPO BIAS_EN high for at

least 900 µs)

100

µs

Cold start-up time

2000

6.6.1.3 Phase-Locked Loop (PLL) Clock Module

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

•

Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1.

Configurable frequency multipliers and dividers

Built-in PLL Slip monitoring circuit

Option to reset the device on a PLL slip detection

6.6.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

PLLCLK

OSCIN

INTCLK

/NR

/OD

/R

VCOCLK

post_ODCLK

PLL

/1 to /64

/1 to /8

/1 to /32

/NF

f_PLLCLK= (f_OSCIN/ NR) * NF / (OD * R)

/1 to /256

Figure 6-6. PLL Block Diagram

6.6.1.3.2 PLL Timing Specifications

Table 6-11. PLL Timing Specifications

PARAMETER

MIN

MAX

20

UNIT

MHz

f_INTCLK

PLL1 Reference Clock frequency

1

f_{post_ODCLK}

f_VCOCLK

Post-ODCLK – PLL1 Post-divider input clock frequency

VCOCLK – PLL1 Output Divider (OD) input clock frequency

400

550

150

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6.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square-wave input.

Table 6-12 specifies the electrical and timing requirements for these clock inputs. The external clock

sources are not checked for validity. They are assumed valid when enabled.

Table 6-12. External Clock Timing and Electrical Specifications

PARAMETER

MIN

MAX

UNIT

MHz

ns

f_EXTCLKx

External clock input frequency

EXTCLK high-pulse duration

EXTCLK low-pulse duration

Low-level input voltage

80

t_w(EXTCLKIN)H

t_w(EXTCLKIN)L

v_iL(EXTCLKIN)

v_iH(EXTCLKIN)

6

ns

–0.3

2

0.8

V

High-level input voltage

VCCIO + 0.3

V

6.6.2 Clock Domains

6.6.2.1 Clock Domain Descriptions

Table 6-13 lists the device clock domains and their default clock sources. The table also shows the

system module control register that is used to select an available clock source for each clock domain.

Table 6-13. Clock Domain Descriptions

SOURCE

SELECTION

REGISTER

CLOCK

DOMAIN

DEFAULT

SOURCE

SPECIAL CONSIDERATIONS

•

Is disabled through the CDDISx registers bit 1

HCLK

GCLK

OSCIN

GHVSRC

Used for all system modules including DMA,

ESM

•

Always the same frequency as HCLK

In phase with HCLK

Is disabled separately from HCLK through the

CDDISx registers bit 0

•

Can be divided by 1 up to 8 when running CPU

self-test (LBIST) using the CLKDIV field of the

STCCLKDIV register at address 0xFFFFE108

•

Always the same frequency as GCLK

2 cycles delayed from GCLK

Is disabled along with GCLK

GCLK2

VCLK

OSCIN

GHVSRC

Gets divided by the same divider setting as

that for GCLK when running CPU self-test

(LBIST)

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Is disabled separately from HCLK through the

CDDISx registers bit 2

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Frequency must be an integer multiple of

VCLK frequency

VCLK2

VCLK4

•

Is disabled separately from HCLK through the

CDDISx registers bit 3

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Is disabled separately from HCLK through the

CDDISx registers bit 9

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Table 6-13. Clock Domain Descriptions (continued)

SOURCE

SELECTION

REGISTER

CLOCK

DOMAIN

DEFAULT

SOURCE

SPECIAL CONSIDERATIONS

•

Defaults to VCLK as the source

VCLKA1

VCLK

VCLKASRC

RCLKSRC

Is disabled through the CDDISx registers bit 4

•

Defaults to VCLK as the source

If a clock source other than VCLK is selected

for RTICLK, then the RTICLK frequency must

be less than or equal to VCLK/3

RTICLK

–

Application can ensure this by

programming the RTI1DIV field of the

RCLKSRC register, if necessary

•

Is disabled through the CDDISx registers bit 6

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6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in Figure 6-7 .

GCM

0

GCLK, GCLK2 (to CPU)

HCLK (to SYSTEM)

OSCIN

PLL #1 (FMzPLL)

1

X1..256

/1..32

/1..64

/1..8

*

/1..16

VCLK_peri (VCLK toperipherals on PCR1)

VCLK_sys (VCLK to system modules)

VCLK2 (to N2HETx and HTUx)

4

5

80 kHz

Low-Power

Oscillator

10 MHz

VCLK4 (ePWM, eQEP, eCAP)

/1..16

6

Reserved

3

7

* the frequency at this node must not

exceed the maximum HCLK specification.

0

1

3

4

5

6

7

EXTCLKIN1

EXTCLKIN2

VCLKA1 (to DCANx)

VCLK

0

1

3

4

5

6

7

/1, 2, 4, or 8

RTICLK (to RTI, DWWD)

VCLK

VCLKA1

VCLK

VCLK2

HRP

/1..64

/1,2,..256

/2,3..2²⁴

/1,2..32

/1,2..65536

/1,2..256

/1,2,..1024

N2HETx

TU

LRP

/2⁰..2⁵

Prop_seg

Phase_seg2

I2C baud

rate

ECLK

SPI

Baud Rate

ADCLK

LIN / SCI

Baud Rate

Phase_seg1

I2C

Loop

High

Resolution Clock

SPIx,MibSPIx

LIN, SCI

External Clock

MibADCx

EXTCLKIN1

NTU[3]

CAN Baud Rate

DCANx

Reserved

NTU[2]

NTU[1]

NTU[0]

N2HETx

RTI

Figure 6-7. Device Clock Domains

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6.6.3 Clock Test Mode

The platform architecture defines a special mode that allows various clock signals to be selected and

output on the ECLK pin and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very

useful for debugging purposes and can be configured through the CLKTEST register in the system

module. See Table 6-14 for the CLKTEST bits value and signal selection.

Table 6-14. Clock Test Mode Options

SEL_ECP_PIN

SEL_GIO_PIN

=

SIGNAL ON ECLK

SIGNAL ON N2HET1[12]

CLKTEST[4-0]

CLKTEST[11-8]

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

Others

Oscillator

Main PLL free-running clock output

Reserved

EXTCLKIN1

LFLPO

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Oscillator Valid Status

Main PLL Valid status

Reserved

HFLPO

HFLPO Valid status

Reserved

EXTCLKIN2

GCLK

Reserved

LFLPO

RTI Base

Oscillator Valid status

Reserved

VCLKA1

VCLKA2

Reserved

HCLK

Reserved

Oscillator Valid status

VCLK

VCLK2

Reserved

VCLK4

Reserved

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6.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN

frequency falls out of a frequency window, the CLKDET flags this condition in the global status register

(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp

mode clock).

The valid OSCIN frequency range is defined as: f_HFLPO/ 4 < f_OSCIN< f_HFLPO* 4.

6.7.1 Clock Monitor Timings

For more information on LPO and Clock detection, see Table 6-10.

upper

threshold

lower

threshold

fail

pass

fail

f[MHz]

1.375

4.875

22

78

Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO

6.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock.

This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by

counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of

spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the

reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration

allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

An additional use of this module is to measure the frequency of a selectable clock source, using the input

clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a

fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width

pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1

does not reach 0 within the counting window generated by counter 0.

6.7.3.1 Features

•

Takes two different clock sources as input to two independent counter blocks.

One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."

Each counter block is programmable with initial, or seed values.

The counter blocks start counting down from their seed values at the same time; a mismatch from the expected

frequency for the clock under test generates an error signal which is used to interrupt the CPU.

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6.7.3.2 Mapping of DCC Clock Source Inputs

Table 6-15. DCC1 Counter 0 Clock Sources

CLOCK SOURCE[3:0]

CLOCK NAME

Oscillator (OSCIN)

High-frequency LPO

Test clock (TCK)

Others

0x5

0xA

Table 6-16. DCC1 Counter 1 Clock Sources

KEY[3:0]

CLOCK SOURCE[3:0]

CLOCK NAME

Others

–

N2HET1[31]

Main PLL free-running clock

output

0x0

0x1

0x2

Reserved

Low-frequency LPO

High-frequency LPO

Reserved

0xA

0x3

0x4

0x5

EXTCLKIN1

EXTCLKIN2

Reserved

0x6

0x7

0x8 - 0xF

VCLK

Table 6-17. DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0]

CLOCK NAME

Oscillator (OSCIN)

Test clock (TCK)

Others

0xA

Table 6-18. DCC2 Counter 1 Clock Sources

KEY [3:0]

Others

0xA

CLOCK SOURCE [3:0]

CLOCK NAME

–

N2HET2[0]

Reserved

VCLK

00x0 - 0x7

0x8 - 0xF

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6.8 Glitch Filters

A glitch filter is present on the following signals.

Table 6-19. Glitch Filter Timing Specifications

PARAMETER

MIN

MAX UNIT

Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses

greater than MAX will generate a reset⁽¹⁾

nPORRST

t_f(nPORRST)

475

2000

ns

Filter time nRST pin; pulses less than MIN will be filtered out, pulses

greater than MAX will generate a reset

nRST

TEST

t_f(nRST)

475

Filter time TEST pin; pulses less than MIN will be filtered out, pulses

greater than MAX will pass through

t_f(TEST)

(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,

I/O pins, and so forth) without also generating a valid reset signal to the CPU.

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6.9 Device Memory Map

6.9.1 Memory Map Diagram

Figure 6-9 shows the device memory map.

0xFFFFFFFF

SYSTEM Modules

0xFFF80000

Peripherals - Frame 1

0xFF000000

0xFE000000

CRC

RESERVED

0xFCFFFFFF

0xFC000000

Peripherals - Frame 2

RESERVED

0xF07FFFFF

Flash Module Bus2 Interface

(Flash ECC, OTP and

EEPROM Emulation accesses)

0xF0000000

RESERVED

0x200BFFFF

0x20000000

Flash (768KB) (Mirrored Image)

RESERVED

0x0841FFFF

0x08400000

RAM - ECC

RESERVED

0x0801FFFF

0x08000000

RAM (128KB)

RESERVED

0x000BFFFF

0x00000000

Flash (768KB)

Figure 6-9. Memory Map

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash

image is 0x2000 0000.

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6.9.2 Memory Map Table

See Figure 1-1 for block diagrams showing the devices interconnect.

Table 6-20. Device Memory Map

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME

SIZE

ACTUAL

SIZE

MODULE NAME

START

END

Memories tightly coupled to the ARM Cortex-R4F CPU

TCM Flash

TCM RAM + RAM ECC

Mirrored Flash

CS0

0x0000_0000

0x0800_0000

0x2000_0000

0x00FF_FFFF

0x0BFF_FFFF

0x20FF_FFFF

16MB

64MB

16MB

768KB

96KB

CSRAM0

Abort

Flash mirror frame

768KB

Flash Module Bus2 Interface

Customer OTP, TCM

Flash Banks

0xF000_0000

0xF000_1FFF

0xF000_FFFF

0xF004_03FF

0xF004_1FFF

0xF008_1FFF

0xF008_FFFF

0xF00C_03FF

0xF00C_1FFF

8KB

1KB

8KB

1KB

4KB

1KB

Customer OTP,

Bank 7

0xF000_E000

0xF004_0000

0xF004_1C00

0xF008_0000

0xF008_E000

0xF00C_0000

0xF00C_1C00

Customer OTP–ECC,

TCM Flash Banks

512B

128B

4KB

Customer OTP–ECC,

Bank 7

TI OTP, TCM Flash

Banks

TI OTP,

Bank 7

1KB

Abort

TI OTP–ECC, TCM

Flash Banks

512B

128B

TI OTP–ECC,

Bank 7

Bank 7 – ECC

Bank 7

0xF010_0000

0xF020_0000

0xF040_0000

0xF013_FFFF

0xF03F_FFFF

0xF04F_FFFF

256KB

2MB

8KB

64KB

128KB

Flash Data Space ECC

1MB

SCR5: Enhanced Timer Peripherals

0xFCF7_8C00 256B

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

eCAP1

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

eQEP1

eQEP2

0xFCF7_8CFF

0xFCF7_8DFF

0xFCF7_8EFF

0xFCF7_8FFF

0xFCF7_90FF

0xFCF7_91FF

0xFCF7_92FF

0xFCF7_93FF

0xFCF7_94FF

0xFCF7_95FF

0xFCF7_96FF

0xFCF7_97FF

0xFCF7_98FF

0xFCF7_99FF

0xFCF7_9AFF

256B

Abort

0xFCF7_8D00

0xFCF7_8E00

0xFCF7_8F00

0xFCF7_9000

0xFCF7_9100

0xFCF7_9200

0xFCF7_9300

0xFCF7_9400

0xFCF7_9500

0xFCF7_9600

0xFCF7_9700

0xFCF7_9800

0xFCF7_9900

0xFCF7_9A00

256B

Cyclic Redundancy Checker (CRC) Module Registers

CRC

CRC frame

0xFE00_0000

0xFEFF_FFFF

Peripheral Memories

0xFF0B_FFFF

16MB

512B

Accesses above 0x200 generate abort.

MIBSPI5 RAM

MIBSPI3 RAM

MIBSPI1 RAM

PCS[5]

PCS[6]

PCS[7]

0xFF0A_0000

0xFF0C_0000

0xFF0E_0000

128KB

2KB

Abort for accesses above 2KB

0xFF0D_FFFF

0xFF0F_FFFF

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

DCAN3 RAM

PCS[13]

0xFF1A_0000

0xFF1B_FFFF

128KB

2KB

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Table 6-20. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME

SIZE

ACTUAL

SIZE

MODULE NAME

START

END

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

DCAN2 RAM

DCAN1 RAM

MIBADC2 RAM

PCS[14]

PCS[15]

0xFF1C_0000

0xFF1D_FFFF

128KB

2KB

8KB

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

0xFF1E_0000

0xFF3A_0000

0xFF1F_FFFF

0xFF3B_FFFF

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

Look-Up Table for ADC2 wrapper. Starts

at address offset 0x2000 and ends at

address offset 0x217F. Wrap around for

accesses between offsets 0x0180 and

0x3FFF. Abort generated for accesses

beyond offset 0x4000.

PCS[29]

128KB

MIBADC2

Look-Up Table

384B

8KB

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

MIBADC1 RAM

Look-Up Table for ADC1 wrapper. Starts

at address offset 0x2000 and ends at

address offset 0x217F. Wrap around for

accesses between offsets 0x0180 and

0x3FFF. Abort generated for accesses

beyond offset 0x4000.

PCS[31]

0xFF3E_0000

0xFF3F_FFFF

128KB

MibADC1

Look-Up Table

384B

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

N2HET2 RAM

N2HET1 RAM

PCS[34]

PCS[35]

0xFF44_0000

0xFF46_0000

0xFF45_FFFF

0xFF47_FFFF

128KB

16KB

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

N2HET2 TU2 RAM

N2HET1 TU1 RAM

PCS[38]

PCS[39]

0xFF4C_0000

0xFF4E_0000

0xFF4D_FFFF

0xFF4F_FFFF

128KB

1KB

Abort

Debug Components

0xFFA0_0FFF

CoreSight Debug ROM

Cortex-R4F Debug

CSCS0

CSCS1

0xFFA0_0000

0xFFA0_1000

4KB

Reads return zeros, writes have no effect

0xFFA0_1FFF

Peripheral Control Registers

0xFFF7_A400

HTU1

HTU2

PS[22]

PS[17]

PS[16]

PS[15]

PS[10]

PS[8]

0xFFF7_A4FF

0xFFF7_A5FF

0xFFF7_B8FF

0xFFF7_B9FF

0xFFF7_BDFF

0xFFF7_C1FF

0xFFF7_C3FF

0xFFF7_D4FF

0xFFF7_DDFF

0xFFF7_DFFF

0xFFF7_E1FF

0xFFF7_E4FF

0xFFF7_E5FF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_F9FF

0xFFF7_FBFF

0xFFF7_FDFF

256B

512B

256B

512B

256B

512B

256B

512B

256B

512B

256B

512B

Reads return zeros, writes have no effect

0xFFF7_A500

0xFFF7_B800

0xFFF7_B900

0xFFF7_BC00

0xFFF7_C000

0xFFF7_C200

0xFFF7_D400

0xFFF7_DC00

0xFFF7_DE00

0xFFF7_E000

0xFFF7_E400

0xFFF7_E500

0xFFF7_F400

0xFFF7_F600

0xFFF7_F800

0xFFF7_FA00

0xFFF7_FC00

N2HET1

N2HET2

GIO

MIBADC1

MIBADC2

I2C

DCAN1

DCAN2

DCAN3

LIN

PS[8]

PS[7]

PS[6]

SCI

PS[6]

MibSPI1

SPI2

PS[2]

MibSPI3

SPI4

PS[1]

MibSPI5

PS[0]

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Table 6-20. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME

SIZE

ACTUAL

SIZE

MODULE NAME

START END

System Modules Control Registers and Memories

DMA RAM

VIM RAM

PPCS0

PPCS2

0xFFF8_0000

0xFFF8_0FFF

4KB

1KB

Abort

Wrap around for accesses to

unimplemented address offsets between

1KB and 4KB.

0xFFF8_2000

0xFFF8_2FFF

4KB

Flash Module

PPCS7

0xFFF8_7000

0xFFF8_C000

0xFFF8_7FFF

0xFFF8_CFFF

4KB

Abort

eFuse Controller

PPCS12

Power Management

Module (PMM)

PPSE0

PPS0

0xFFFF_0000

0xFFFF_E000

0xFFFF_01FF

0xFFFF_E0FF

512B

256B

512B

256B

Abort

PCR registers

Reads return zeros, writes have no effect

System Module -

Frame 2

PPS0

0xFFFF_E100

0xFFFF_E1FF

256B

Reads return zeros, writes have no effect

(see device TRM)

PBIST

STC

PPS1

0xFFFF_E400

0xFFFF_E600

0xFFFF_E5FF

0xFFFF_E6FF

512B

256B

512B

256B

Reads return zeros, writes have no effect

Generates address error interrupt, if

enabled

IOMM Multiplexing

Control Module

PPS2

0xFFFF_EA00

0xFFFF_EBFF

512B

Reads return zeros, writes have no effect

DCC1

DMA

PPS3

PPS4

PPS5

PPS6

PPS7

0xFFFF_EC00

0xFFFF_F000

0xFFFF_F400

0xFFFF_F500

0xFFFF_F600

0xFFFF_F800

0xFFFF_F900

0xFFFF_FC00

0xFFFF_FD00

0xFFFF_FE00

0xFFFF_ECFF

0xFFFF_F3FF

0xFFFF_F4FF

0xFFFF_F5FF

0xFFFF_F6FF

0xFFFF_F8FF

0xFFFF_F9FF

0xFFFF_FCFF

0xFFFF_FDFF

0xFFFF_FEFF

256B

1KB

256B

1KB

Reads return zeros, writes have no effect

DCC2

256B

ESM

CCMR4

RAM ECC even

RAM ECC odd

RTI + DWWD

VIM Parity

VIM

System Module -

Frame 1

PPS7

0xFFFF_FF00

0xFFFF_FFFF

256B

Reads return zeros, writes have no effect

(see device TRM)

6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an

imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to

handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program

status register (CPSR).

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6.9.4 Master/Slave Access Privileges

Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that

can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. Yes indicates that the module listed in

the MASTERS column can access that slave module.

Table 6-21. Master / Slave Access Matrix

MASTERS

ACCESS MODE

SLAVES ON MAIN SCR

CRC

Flash Module

Bus2 Interface:

OTP, ECC, Bank

7

Non-CPU

Accesses to

Program Flash

and CPU Data

RAM

Slave Interfaces

Peripheral

Control

Registers, All

Peripheral

Memories, And

All System

Module Control

Registers And

Memories

CPU READ

CPU WRITE

DMA

User/Privilege

User

Yes

No

Yes

No

DAP

Privilege

HTU1

Privilege

HTU2

Privilege

No

6.9.5 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU

(master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in

a power domain that has been turned off.

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6.10 Flash Memory

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a

customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense

amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical

construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or

erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Table 6-22. Flash Memory Banks and Sectors

SECTOR

NO.

MEMORY ARRAYS (OR BANKS)

SEGMENT

LOW ADDRESS

HIGH ADDRESS

0

16KB

32KB

128KB

4KB

0x0000_0000

0x0000_4000

0x0000_8000

0x0000_C000

0x0001_0000

0x0001_4000

0x0001_8000

0x0002_0000

0x0004_0000

0x0006_0000

0x0008_0000

0x000A_0000

0xF020_0000

0xF020_1000

0xF020_2000

0xF020_3000

0xF020_4000

0xF020_5000

0xF020_6000

0xF020_7000

0xF020_8000

0xF020_9000

0xF020_A000

0xF020_B000

0xF020_C000

0xF020_D000

0xF020_E000

0xF020_F000

0x0000_3FFF

0x0000_7FFF

0x0000_BFFF

0x0000_FFFF

0x0001_3FFF

0x0001_7FFF

0x0001_FFFF

0x0003_FFFF

0x0005_FFFF

0x0007_FFFF

0x0009_FFFF

0x000B_FFFF

0xF020_0FFF

0xF020_1FFF

0xF020_2FFF

0xF020_3FFF

0xF020_4FFF

0xF020_5FFF

0xF020_6FFF

0xF020_7FFF

0xF020_8FFF

0xF020_9FFF

0xF020_AFFF

0xF020_BFFF

0xF020_CFFF

0xF020_DFFF

0xF020_EFFF

0xF020_FFFF

1

2

3

4

BANK0 (768KB)⁽¹⁾

5

6

7

8

9

10

11

0

1

4KB

2

4KB

3

4KB

4

4KB

5

4KB

6

4KB

7

4KB

BANK7 (64KB) for EEPROM emulation^(2)(3)(4)

8

4KB

9

4KB

10

11

12

13

14

15

4KB

(1) Flash bank0 is a 144-bit-wide bank with ECC support.

(2) Flash bank7 is a 72-bit-wide bank with ECC support.

(3) The flash bank7 can be programmed while executing code from flash bank0.

(4) Code execution is not allowed from flash bank7.

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6.10.2 Main Features of Flash Module

•

Support for multiple flash banks for program and/or data storage

Simultaneous read access on a bank while performing program or erase operation on any other bank

Integrated state machines to automate flash erase and program operations

Pipelined mode operation to improve instruction access interface bandwidth

Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU

–

Error address is captured for host system debugging

•

Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by SECDED logic embedded inside the CPU.

The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash

memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with

the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while

a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling

mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance

Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

;Set 4th bit (‘X’) of PMNC register

The application must also explicitly enable the ECC checking of the CPU for accesses on the CPU ATCM

and BTCM interfaces. These are connected to the program flash and data RAM, respectively. ECC

checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN, and ATCMPCEN

bits of the System Control Coprocessor Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000

DMB

;Enable ECC checking for ATCM and BTCMs

MCR p15, #0, r1, c1, c0, #1

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, see

Section 5.8.1.2.

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6.10.5 Program Flash

Table 6-23. Timing Requirements for Program Flash

MIN

NOM

MAX

300

8

UNIT

µs

t_prog(144bit)

t_prog(Total)

Wide Word (144-bit) programming time

768KB programming time⁽¹⁾

40

–40°C to 125°C

s

0°C to 60°C, for first

25 cycles

2

0.03

16

4

s

–40°C to 125°C

t_erase(bank0)

Sector/Bank erase time⁽²⁾

0°C to 60°C, for first

25 cycles

100

ms

Write/erase cycles with 15-year Data Retention

requirement

t_wec

–40°C to 125°C

1000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase

a sector.

6.10.6 Data Flash

Table 6-24. Timing Requirements for Data Flash

MIN

NOM

MAX

310

2.6

UNIT

µs

t_prog(144bit)

t_prog(Total)

Wide Word (72-bit) programming time

47

–40°C to 125°C

s

EEPROM Emulation (bank 7) 64KByte

programming time⁽¹⁾

0°C to 60°C, for first

25 cycles

775

0.2

14

1435

8

ms

s

–40°C to 125°C

Sector/Bank erase time, EEPROM Emulation

(bank 7)

t_erase(bank7)

0°C to 60°C, for first

25 cycles

100

ms

Write/erase cycles with 15-year Data Retention

requirement

t_wec

–40°C to 125°C

100000

cycles

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 72 bits at a time at the maximum specified operating frequency.

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6.11 Tightly Coupled RAM Interface Module

Figure 6-10 shows the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.

36 Bit

wide

Upper 32-bits data

36-bit-wide

RAM

Cortex R4F™

and 4 ECC bits

RAM

TCM BUS

TCRAM

B0

TCM

36 Bit

wide

Interface 1

72-bit data + ECC

36-bit-wide

RAM

Lower 32-bits data

and 4 ECC bits

RAM

36 Bit

wide

Upper 32-bits data

and 4 ECC bits

36-bit-wide

RAM

TCM BUS

B1

TCM

TCRAM

72-bit data + ECC

Interface 2

36 Bit

wide

36-bit-wide

RAM

Lower 32-bits data

and 4 ECC bits

RAM

Figure 6-10. TCRAM Block Diagram

6.11.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

•

Acts as slave to the BTCM interface of the Cortex-R4F CPU

Supports CPU internal ECC scheme by providing 64-bit data and 8-bit ECC code

Monitors CPU Event Bus and generates single-bit or multibit error interrupts

Stores addresses for single-bit and multibit errors

Supports RAM trace module

Provides CPU address bus integrity checking by supporting parity checking on the address bus

Performs redundant address decoding for the RAM bank chip select and ECC select generation logic

Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks

and generating independent RAM access control signals to the two banks

•

Supports auto-initialization of the RAM banks along with the ECC bits

6.11.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. The

TCRAMW also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to

the RAM. The TCRAMW monitors the CPU event bus and provides registers for indicating single-bit or

multibit errors and also for identifying the address that caused the single or multi-bit error. The event

signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information, see the device-specific Technical Reference Manual.

6.12 Parity Protection for Accesses to Peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the

parity is calculated based on the data read from the peripheral RAM and compared with the good parity

value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates

a parity error signal that is mapped to the Error Signaling Module. The module also captures the

peripheral RAM address that caused the parity error.

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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the

application. Each individual peripheral contains control registers to enable the parity protection for

accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose

to generate an interrupt whenever a peripheral RAM parity error is detected.

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6.13 On-Chip SRAM Initialization and Testing

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.1.1 Features

•

Extensive instruction set to support various memory test algorithms

ROM-based algorithms allow application to run TI production-level memory tests

Independent testing of all on-chip SRAM

6.13.1.2 PBIST RAM Groups

Table 6-25. PBIST RAM Grouping

Test Pattern (Algorithm)

MARCH 13N⁽¹⁾MARCH 13N⁽¹⁾

TRIPLE READ TRIPLE READ

RAM

MEMORY

MEM

TYPE

TWO PORT

(cycles)

SINGLE PORT

(cycles)

TEST CLOCK

SLOW READ

FAST READ

GROUP

ALGO MASK

0x1

ALGO MASK

0x2

ALGO MASK

0x4

ALGO MASK

0x8

PBIST_ROM

STC_ROM

DCAN1

1

2

ROM CLK

VCLK

HCLK

VCLK

HCLK

VCLK

HCLK

ROM

24578

19586

8194

6530

ROM

3

Dual port

Single port

Dual port

Single port

25200

DCAN2

4

DCAN3

5

ESRAM1⁽²⁾

MIBSPI1

MIBSPI3

MIBSPI5

VIM

6

266280

7

33440

12560

4200

8

9

10

11

12

13

14

18

19

20

21

MIBADC1

DMA

18960

31680

6480

N2HET1

HET TU1

MIBADC2

N2HET2

HET TU2

ESRAM5⁽³⁾

4200

31680

6480

266280

(1) Several memory testing algorithms are stored in the PBIST ROM. However, TI recommends the March13N algorithm for application

testing of RAM.

(2) ESRAM1: Address 0x08000000 - 0x0800FFFF

(3) ESRAM5: Address 0x08010000 - 0x0801FFFF

The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if

HCLK <= 100 MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV

field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

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6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware

Initialization mechanism in the system module. This hardware mechanism allows an application to

program the memory arrays with error detection capability to a known state based on their error detection

scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects

the memories that are to be initialized.

For more information on these registers, see the device-specific Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in

Table 6-26.

Table 6-26. Memory Initialization

ADDRESS RANGE

CONNECTING MODULE

MSINENA REGISTER BIT #

BASE ADDRESS

0x08000000

0x08010000

0xFF0A0000

0xFF0C0000

0xFF0E0000

0xFF1A0000

0xFF1C0000

0xFF1E0000

0xFF3A0000

0xFF3E0000

0xFF440000

0xFF460000

0xFF4C0000

0xFF4E0000

0xFFF80000

0xFFF82000

ENDING ADDRESS

0x0800FFFF

0x0801FFFF

0xFF0BFFFF

0xFF0DFFFF

0xFF0FFFFF

0xFF1BFFFF

0xFF1DFFFF

0xFF1FFFFF

0xFF3BFFFF

0xFF3FFFFF

0xFF45FFFF

0xFF47FFFF

0xFF4DFFFF

0xFF4FFFFF

0xFFF80FFF

0xFFF82FFF

RAM (PD#1)

RAM (RAM_PD#1)

MIBSPI5 RAM

MIBSPI3 RAM

MIBSPI1 RAM

DCAN3 RAM

DCAN2 RAM

DCAN1 RAM

MIBADC2 RAM

MIBADC1 RAM

N2HET2 RAM

N2HET1 RAM

HET TU2 RAM

HET TU1 RAM

DMA RAM

0⁽¹⁾

12⁽²⁾

11⁽²⁾

7⁽²⁾

10

6

5

14

8

15

3

16

4

1

VIM RAM

2

(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.

(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset.

This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization

method. The MibSPIx module must be first brought out of its local reset to use the system module auto-initialization method.

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6.14 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the

many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow

of program execution. Normally, these events require a timely response from the CPU; therefore, when an

interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine

(ISR).

6.14.1 VIM Features

The VIM module has the following features:

•

Supports 128 interrupt channels.

Provides programmable priority and enable for interrupt request lines.

–

•

Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.

Provides two software dispatch mechanisms when the CPU VIC port is not used.

–

Index interrupt

Register vectored interrupt

•

Parity protected vector interrupt table against soft errors.

6.14.2 Interrupt Request Assignments

Table 6-27. Interrupt Request Assignments

Modules

Interrupt Sources

Default VIM Interrupt

Channel

ESM

Reserved

RTI

ESM High level interrupt (NMI)

Reserved

0

1

RTI compare interrupt 0

RTI compare interrupt 1

RTI compare interrupt 2

RTI compare interrupt 3

RTI overflow interrupt 0

RTI overflow interrupt 1

RTI time-base interrupt

GIO interrupt A

2

RTI

3

RTI

4

RTI

5

RTI

6

RTI

7

RTI

8

GIO

9

N2HET1

HET TU1

MIBSPI1

LIN

N2HET1 level 0 interrupt

HET TU1 level 0 interrupt

MIBSPI1 level 0 interrupt

LIN level 0 interrupt

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

MIBADC1

DCAN1

SPI2

MIBADC1 event group interrupt

MIBADC1 software group 1 interrupt

DCAN1 level 0 interrupt

SPI2 level 0 interrupt

Reserved

CRC

CRC Interrupt

ESM

ESM low-level interrupt

Software interrupt (SSI)

PMU Interrupt

SYSTEM

CPU

GIO

GIO interrupt B

N2HET1

HET TU1

MIBSPI1

N2HET1 level 1 interrupt

HET TU1 level 1 interrupt

MIBSPI1 level 1 interrupt

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Table 6-27. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

LIN

LIN level 1 interrupt

MIBADC1 software group 2 interrupt

DCAN1 level 1 interrupt

SPI2 level 1 interrupt

MIBADC1 magnitude compare interrupt

Reserved

27

MIBADC1

DCAN1

SPI2

28

29

30

MIBADC1

Reserved

DMA

31

32

FTCA interrupt

33

DMA

LFSA interrupt

34

DCAN2

MIBSPI3

DMA

DCAN2 level 0 interrupt

MIBSPI3 level 0 interrupt

MIBSPI3 level 1 interrupt

HBCA interrupt

35

37

38

39

DMA

BTCA interrupt

40

Reserved

DCAN2

DCAN1

DCAN3

DCAN2

FPU

Reserved

41

DCAN2 level 1 interrupt

DCAN1 IF3 interrupt

DCAN3 level 0 interrupt

DCAN2 IF3 interrupt

FPU interrupt

42

44

45

46

47

Reserved

SPI4

Reserved

48

SPI4 level 0 interrupt

MibADC2 event group interrupt

MibADC2 software group1 interrupt

Reserved

49

MIBADC2

Reserved

MIBSPI5

SPI4

50

51

52

MIBSPI5 level 0 interrupt

SPI4 level 1 interrupt

DCAN3 level 1 interrupt

MIBSPI5 level 1 interrupt

MibADC2 software group2 interrupt

Reserved

53

54

DCAN3

MIBSPI5

MIBADC2

Reserved

MIBADC2

DCAN3

FMC

55

56

57

58

MibADC2 magnitude compare interrupt

DCAN3 IF3 interrupt

FSM_DONE interrupt

Reserved

59

60

61

Reserved

N2HET2

SCI

62

N2HET2 level 0 interrupt

SCI level 0 interrupt

HET TU2 level 0 interrupt

I2C level 0 interrupt

Reserved

63

64

HET TU2

I2C

65

66

Reserved

N2HET2

SCI

67–72

73

N2HET2 level 1 interrupt

SCI level 1 interrupt

HET TU2 level 1 interrupt

Reserved

74

HET TU2

Reserved

HWAG1

HWAG2

DCC1

75

76–79

80

HWA_INT_REQ_H

81

DCC done interrupt

DCC2 done interrupt

82

DCC2

83

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Table 6-27. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

Reserved

PBIST Controller

Reserved

PBIST Done Interrupt

Reserved

84

85

86-87

88

HWAG1

HWA_INT_REQ_L

ePWM1 Interrupt

HWAG2

89

ePWM1INTn

ePWM1TZINTn

ePWM2INTn

ePWM2TZINTn

ePWM3INTn

ePWM3TZINTn

ePWM4INTn

ePWM4TZINTn

ePWM5INTn

ePWM5TZINTn

ePWM6INTn

ePWM6TZINTn

ePWM7INTn

ePWM7TZINTn

eCAP1INTn

eCAP2INTn

eCAP3INTn

eCAP4INTn

eCAP5INTn

eCAP6INTn

eQEP1INTn

eQEP2INTn

Reserved

90

ePWM1 Trip Zone Interrupt

ePWM2 Interrupt

91

92

ePWM2 Trip Zone Interrupt

ePWM3 Interrupt

93

94

ePWM3 Trip Zone Interrupt

ePWM4 Interrupt

95

96

ePWM4 Trip Zone Interrupt

ePWM5 Interrupt

97

98

ePWM5 Trip Zone Interrupt

ePWM6 Interrupt

99

100

101

102

103

104

105

106

107

108

109

110

111

112–127

ePWM6 Trip Zone Interrupt

ePWM7 Interrupt

ePWM7 Trip Zone Interrupt

eCAP1 Interrupt

eCAP2 Interrupt

eCAP3 Interrupt

eCAP4 Interrupt

eCAP5 Interrupt

eCAP6 Interrupt

eQEP1 Interrupt

eQEP2 Interrupt

Reserved

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR

entry; therefore only request channels 0..126 can be used and are offset by one address in

the VIM RAM.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt

channels.

NOTE

The application can change the mapping of interrupt sources to the interrupt channels

through the interrupt channel control registers (CHANCTRLx) inside the VIM module.

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6.15 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background

of CPU operations. Typically, the DMA is used to:

•

Transfer blocks of data between external and internal data memories

Restructure portions of internal data memory

Continually service a peripheral

6.15.1 DMA Features

•

CPU independent data transfer

One 64-bit master port that interfaces to the TMS570 Memory System.

FIFO buffer (four entries deep and each 64 bits wide)

Channel control information is stored in RAM protected by parity

16 channels with individual enable

Channel chaining capability

32 peripheral DMA requests

Hardware and software DMA requests

8-, 16-, 32- or 64-bit transactions supported

Multiple addressing modes for source/destination (fixed, increment, offset)

Auto-initiation

Power-management mode

Memory Protection with four configurable memory regions

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6.15.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The

module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By

default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in Table 6-28. The application must ensure that

only one of these DMA request sources is enabled at any time.

Table 6-28. DMA Request Line Connection

Modules

MIBSPI1

DMA Request Sources

MIBSPI1[1]⁽¹⁾

DMA Request

DMAREQ[0]

DMAREQ[1]

DMAREQ[2]

DMAREQ[3]

DMAREQ[4]

DMAREQ[5]

DMAREQ[6]

DMAREQ[7]

DMAREQ[8]

DMAREQ[9]

DMAREQ[10]

DMAREQ[11]

DMAREQ[12]

DMAREQ[13]

DMAREQ[14]

DMAREQ[15]

DMAREQ[16]

DMAREQ[17]

DMAREQ[18]

DMAREQ[19]

DMAREQ[20]

MIBSPI1

MIBSPI1[0]⁽²⁾

SPI2

SPI2 receive

SPI2

SPI2 transmit

MIBSPI1 / MIBSPI3 / DCAN2

DCAN1 / MIBSPI5

MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3

MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2

DCAN1 IF2 / MIBSPI5[2]

MIBADC1 / MIBSPI5

MIBSPI1 / MIBSPI3 / DCAN1

MIBSPI1 / MIBSPI3 / DCAN2

MIBADC1 / I2C / MIBSPI5

RTI / MIBSPI1 / MIBSPI3

MIBSPI3 / MibADC2 / MIBSPI5

MIBSPI3 / MIBSPI5

MIBADC1 event / MIBSPI5[3]

MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1

MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1

MIBADC1 G1 / I2C receive / MIBSPI5[4]

MIBADC1 G2 / I2C transmit / MIBSPI5[5]

RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]

RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]

MIBSPI3[1]⁽¹⁾/ MibADC2 event / MIBSPI5[6]

MIBSPI3[0]⁽²⁾/ MIBSPI5[7]

MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2

MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2

RTI / MIBSPI5

MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1

MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2

RTI DMAREQ2 / MIBSPI5[8]

RTI / MIBSPI5

RTI DMAREQ3 / MIBSPI5[9]

N2HET1 / N2HET2 / DCAN3

N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3

IF2

N2HET1 / N2HET2 / DCAN3

N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3

IF3

DMAREQ[21]

MIBSPI1 / MIBSPI3 / MIBSPI5

MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]

MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]

DMAREQ[22]

DMAREQ[23]

DMAREQ[24]

N2HET1 / N2HET2 / SPI4 / MIBSPI5

N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4

receive / MIBSPI5[12]

N2HET1 / N2HET2 / SPI4 / MIBSPI5

N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4

transmit / MIBSPI5[13]

DMAREQ[25]

CRC / MIBSPI1 / MIBSPI3

LIN / MIBSPI5

CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]

CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]

LIN receive / MIBSPI5[14]

DMAREQ[26]

DMAREQ[27]

DMAREQ[28]

DMAREQ[29]

DMAREQ[30]

LIN / MIBSPI5

LIN transmit / MIBSPI5[15]

MIBSPI1 / MIBSPI3 / SCI / MIBSPI5

MIBSPI1[14] / MIBSPI3[14] / SCI receive /

MIBSPI5[1]⁽¹⁾

MIBSPI1 / MIBSPI3 / SCI / MIBSPI5

MIBSPI1[15] / MIBSPI3[15] / SCI transmit /

MIBSPI5[0]⁽²⁾

DMAREQ[31]

(1) SPI1, SPI3, SPI5 receive when configured in standard SPI mode

(2) SPI1, SPI3, SPI5 transmit when configured in standard SPI mode

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6.16 Real-Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for

benchmarking code. The RTI module can incorporate several counters that define the time bases needed

for scheduling an operating system.

The timers also let you benchmark certain areas of code by reading the values of the counters at the

beginning and the end of the desired code range and calculating the difference between the values.

6.16.1 Features

The RTI module has the following features:

•

Two independent 64-bit counter blocks

Four configurable compares for generating operating system ticks or DMA requests. Each event can

be driven by either counter block 0 or counter block 1.

•

Fast enabling/disabling of events

Two timestamp (capture) functions for system or peripheral interrupts, one for each counter block

6.16.2 Block Diagrams

Figure 6-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI

module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only

available as time-base inputs for the counter block 0. Figure 6-12 shows the compare unit block diagram

of the RTI module.

31

0

Compare

up counter

RTICPUCx

OVLINTx

31

0

=

Up counter

RTIUCx

31

0

RTICLK

To Compare

Unit

Free-running counter

RTIFRCx

NTU0

NTU1

NTU2

NTU3

31

0

31

0

Capture

up counter

RTICAUCx

Capture

free-running counter

RTICAFRCx

CAP event source 0

CAP event source 1

External

control

Figure 6-11. Counter Block Diagram

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31

Update

compare

0

RTIUDCPy

+

31

0

DMAREQy

INTy

Compare

RTICOMPy

From counter

block 0

=

From counter

block 1

Compare

control

Figure 6-12. Compare Block Diagram

6.16.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the

system module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources, see Table 6-8 and Table 6-13.

6.16.4 Network Time Synchronization Inputs

The RTI module supports four Network Time Unit (NTU) inputs that signal internal system events, and

which can be used to synchronize the time base used by the RTI module. On this device, these NTU

inputs are connected as shown in Table 6-29.

Table 6-29. Network Time Synchronization Inputs

NTU INPUT

SOURCE

0

1

2

3

Reserved

EXTCLKIN1 clock input

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6.17 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.

The error condition is handled based on a fixed severity level assigned to it. Any severe error condition

can be configured to drive a low level on a dedicated device terminal called nERROR. The nERROR can

be used as an indicator to an external monitor circuit to put the system into a safe state.

6.17.1 ESM Features

The features of the ESM are:

•

128 interrupt/error channels are supported, divided into three groups

–

64 channels with maskable interrupt and configurable error pin behavior

32 error channels with nonmaskable interrupt and predefined error pin behavior

32 channels with predefined error pin behavior only

•

Error pin to signal severe device failure

Configurable time base for error signal

Error forcing capability

6.17.2 ESM Channel Assignments

The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is

used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device

response to each error is determined by the severity group it is connected to. Table 6-31 lists the channel

assignment for each group.

Table 6-30. ESM Groups

INFLUENCE ON ERROR

ERROR GROUP

INTERRUPT CHARACTERISTICS

TERMINAL

Configurable

Fixed

Group1

Group2

Group3

Maskable, low or high priority

Nonmaskable, high priority

No interrupt generated

Fixed

Table 6-31. ESM Channel Assignments

ERROR CONDITION

GROUP

CHANNELS

Group1

Reserved

Group1

0

1

2

3

4

5

MibADC2 - RAM parity error

DMA - MPU configuration violation

DMA - control packet RAM parity error

Reserved

DMA - error on DMA read access, imprecise error

FMC - correctable ECC error: bus1 and bus2 interfaces

(does not include accesses to Bank 7)

Group1

6

N2HET1 - RAM parity error

HET TU1/HET TU2 - dual-control packet RAM parity error

HET TU1/HET TU2 - MPU configuration violation

PLL1 - Slip

Group1

7

8

9

10

11

12

13

14

15

16

Clock Monitor - oscillator fail

Reserved

DMA - error on DMA write access, imprecise error

Reserved

VIM RAM - parity error

Reserved

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Table 6-31. ESM Channel Assignments (continued)

ERROR CONDITION

GROUP

Group1

CHANNELS

MibSPI1 - RAM parity error

MibSPI3 - RAM parity error

MibADC1 - RAM parity error

Reserved

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

DCAN1 - RAM parity error

DCAN3 - RAM parity error

DCAN2 - RAM parity error

MibSPI5 - RAM parity error

Reserved

RAM even bank (B0TCM) - correctable ECC error

CPU - self-test failed

RAM odd bank (B1TCM) - correctable ECC error

Reserved

DCC1 - error

CCM-R4 - self-test failed

Reserved

N2HET2 - RAM parity error

FMC - correctable ECC error (Bank 7 access)

FMC - uncorrectable ECC error (Bank 7 access)

IOMM - Access to unimplemented location in IOMM frame, or write access

detected in unprivileged mode

Group1

37

Power domain controller compare error

Power domain controller self-test error

Group1

38

39

eFuse Controller Error – this error signal is generated when any bit in the eFuse

controller error status register is set. The application can choose to generate an

interrupt whenever this bit is set to service any eFuse controller error conditions.

Group1

40

41

eFuse Controller - Self-Test Error. This error signal is generated only when a self-

test on the eFuse controller generates an error condition. When an ECC self-test

error is detected, group 1 channel 40 error signal will also be set.

Reserved

Group1

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

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Table 6-31. ESM Channel Assignments (continued)

ERROR CONDITION

GROUP

Group1

CHANNELS

Reserved

61

62

63

DCC2 - error

Reserved

Group2

Reserved

Group2

0

1

CCMR4 - dual-CPU lock-step error

Reserved

2

3

FMC - uncorrectable address parity error on accesses to main flash

4

Reserved

5

RAM even bank (B0TCM) - uncorrectable redundant address decode error

6

Reserved

7

RAM odd bank (B1TCM) - uncorrectable redundant address decode error

8

Reserved

9

RAM even bank (B0TCM) - address bus parity error

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

RAM odd bank (B1TCM) - address bus parity error

Reserved

TCM - ECC live lock detect

Reserved

Windowed Watchdog (WWD) violation

Reserved

Group3

Reserved

Group3

0

1

2

3

4

5

6

eFuse Farm - autoload error

Reserved

RAM even bank (B0TCM) - ECC uncorrectable error

Reserved

RAM odd bank (B1TCM) - ECC uncorrectable error

Reserved

FMC - uncorrectable ECC error: bus1 and bus2 interfaces

(does not include address parity error and errors on accesses to Bank 7)

Group3

7

Reserved

Group3

8

9

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Table 6-31. ESM Channel Assignments (continued)

ERROR CONDITION

GROUP

Group3

CHANNELS

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

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6.18 Reset/Abort/Error Sources

Table 6-32. Reset/Abort/Error Sources

ESM HOOKUP

GROUP.CHANNE

L

ERROR SOURCE

CPU TRANSACTIONS

CPUMODE

ERROR RESPONSE

Precise write error (NCNB/Strongly Ordered)

Precise read error (NCB/Device or Normal)

Imprecise write error (NCB/Device or Normal)

User/Privilege

Precise Abort (CPU)

Imprecise Abort (CPU)

N/A

Undefined Instruction Trap

(CPU)⁽¹⁾

Illegal instruction

User/Privilege

N/A

MPU access violation

Abort (CPU)

SRAM

B0 TCM (even) ECC single error (correctable)

User/Privilege

ESM

1.26

3.3

Abort (CPU), ESM => →

B0 TCM (even) ECC double error (uncorrectable)

nERROR

B0 TCM (even) uncorrectable error (that is, redundant address

decode)

User/Privilege

ESM => NMI => nERROR

2.6

B0 TCM (even) address bus parity error

User/Privilege

ESM => NMI => nERROR

ESM

2.10

1.28

B1 TCM (odd) ECC single error (correctable)

Abort (CPU), ESM =>

nERROR

B1 TCM (odd) ECC double error (uncorrectable)

User/Privilege

3.5

B1 TCM (odd) uncorrectable error (that is, redundant address

decode)

User/Privilege

ESM => NMI => nERROR

2.8

B1 TCM (odd) address bus parity error

2.12

FLASH WITH CPU BASED ECC

FMC correctable error - Bus1 and Bus2 interfaces (does not

include accesses to Bank 7)

User/Privilege

ESM

1.6

3.7

2.4

FMC uncorrectable error - Bus1 and Bus2 accesses

(does not include address parity error)

Abort (CPU), ESM =>

nERROR

FMC uncorrectable error - address parity error on Bus1

accesses

ESM => NMI => nERROR

FMC correctable error - Accesses to Bank 7

FMC uncorrectable error - Accesses to Bank 7

DMA TRANSACTIONS

User/Privilege

ESM

1.35

1.36

External imprecise error on read (Illegal transaction with ok

response)

User/Privilege

ESM

1.5

External imprecise error on write (Illegal transaction with ok

response)

1.13

Memory access permission violation

Memory parity error

User/Privilege

ESM

1.2

1.3

HET TU1 (HTU1)

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory parity error

User/Privilege

Interrupt => VIM

ESM

N/A

1.9

1.8

ESM

HET TU2 (HTU2)

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Memory parity error

User/Privilege

Interrupt => VIM

ESM

N/A

1.9

1.8

ESM

(1) The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of

the CPU.

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Table 6-32. Reset/Abort/Error Sources (continued)

ESM HOOKUP

GROUP.CHANNE

L

ERROR SOURCE

CPUMODE

ERROR RESPONSE

N2HET1

Memory parity error

N2HET2

User/Privilege

ESM

1.7

Memory parity error

MIBSPI

1.34

MibSPI1 memory parity error

MibSPI3 memory parity error

MibSPI5 memory parity error

MIBADC

User/Privilege

ESM

1.17

1.18

1.24

MibADC1 memory parity error

MibADC2 memory parity error

DCAN

User/Privilege

ESM

1.19

1.1

DCAN1 memory parity error

DCAN2 memory parity error

DCAN3 memory parity error

PLL

User/Privilege

ESM

1.21

1.23

1.22

PLL slip error

User/Privilege

ESM

1.10

1.11

CLOCK MONITOR

Clock monitor interrupt

DCC

DCC1 error

User/Privilege

ESM

1.30

1.62

DCC2 error

CCM-R4

Self-test failure

User/Privilege

ESM

1.31

2.2

Compare failure

ESM => NMI => nERROR

VIM

Memory parity error

User/Privilege

N/A

ESM

Reset

ESM

1.15

N/A

VOLTAGE MONITOR

VMON out of voltage range

CPU SELF-TEST (LBIST)

Cortex-R4F CPU self-test (LBIST) error

PIN MULTIPLEXING CONTROL

Mux configuration error

POWER DOMAIN CONTROL

PSCON compare error

PSCON self-test error

eFuse CONTROLLER

eFuse Controller Autoload error

eFuse Controller - Any bit set in the error status register

eFuse Controller self-test error

WINDOWED WATCHDOG

WWD Nonmaskable Interrupt exception

User/Privilege

1.27

1.37

User/Privilege

ESM

1.38

1.39

User/Privilege

ESM => nERROR

3.1

ESM

1.40

1.41

N/A

ESM => NMI => nERROR

2.24

ERRORS REFLECTED IN THE SYSESR REGISTER

Power-Up Reset

Oscillator fail / PLL slip⁽²⁾

N/A

Reset

N/A

(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

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Table 6-32. Reset/Abort/Error Sources (continued)

ESM HOOKUP

GROUP.CHANNE

L

ERROR SOURCE

CPUMODE

ERROR RESPONSE

Watchdog exception

N/A

Reset

N/A

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

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6.19 Digital Windowed Watchdog

This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code

execution (see Figure 6-13).

The DWWD module allows the application to configure the time window within which the DWWD module

expects the application to service the watchdog. A watchdog violation occurs if the application services the

watchdog outside of this window, or fails to service the watchdog at all. The application can choose to

generate a system reset or an ESM group2 error signal in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog

can only be disabled upon a system reset.

Down

Counter

0

DWWD Preload

100%

Window

Window Open

íindow ꢀpen

Window Open

íindow ꢀpen

=

Down Counter

50%

Window

íindow ꢀpen

25%

Window

í ꢀpen

ꢀp

í ꢀpen

ꢀp

RESET

12.5%

Window

5igital

Digital

Windowed

íindowed

INTERRUPT

ESM

6.25%

Window

WaWtcahtdcohg

íatchdog

ꢀ

Dog

3.125%

Window

ꢀ

Figure 6-13. Digital Windowed Watchdog Example

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6.20 Debug Subsystem

6.20.1 Block Diagram

The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see

Figure 6-14).

Boundary Scan

Interface

BSR/BSDL

Debug

ROM1

TRST

TMS

TCK

RTCK

TDI

TDO

Debug APB

DAP

Secondary Tap 0

APB Mux

AHB-AP

APB slave

Cortex

R4F

POM

To

SCR1

From

PCR Bridge

through A2A

Secondary Tap 2

Test Tap 0

AJSM

eFuse Farm

PSCON

Test Tap 1

Figure 6-14. Debug Subsystem Block Diagram

6.20.2 Debug Components Memory Map

Table 6-33. Debug Components Memory Map

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS

IN FRAME

MODULE

NAME

FRAME CHIP

SELECT

FRAME ACTUAL

SIZE

START

END

CoreSight Debug ROM

Cortex-R4F Debug

CSCS0

CSCS1

0xFFA0_0000

0xFFA0_1000

0xFFA0_0FFF

0xFFA0_1FFF

4KB

Reads return zeros, writes have no effect

6.20.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID

Code per silicon revision, see Table 6-34.

Table 6-34. JTAG ID Code

SILICON REVISION

Rev 0

ID

0x0BB0302F

0x1BB0302F

Rev A

88

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6.20.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-35).

Table 6-35. Debug ROM Table

ADDRESS

0x000

DESCRIPTION

Pointer to Cortex-R4F

Reserved

VALUE

0x0000 1003

0x0000 2002

0x0000 3002

0x0000 4003

0x0000 0000

0x001

0x002

Reserved

0x003

Reserved

0x004

end of table

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6.20.5 JTAG Scan Interface Timings

Table 6-36. JTAG Scan Interface Timing⁽¹⁾

NO.

PARAMETER

MIN

MAX

UNIT

MHz

ns

fTCK

TCK frequency (at HCLKmax)

RTCK frequency (at TCKmax and HCLKmax)

Delay time, TCK to RTCK

12

fRTCK

10

1

2

3

4

5

td(TCK -RTCK)

24

12

tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr)

26

0

ns

th(RTCKr -TDI/TMS)

th(RTCKr -TDO)

td(TCKf -TDO)

Hold time, TDI, TMS after RTCKr

Hold time, TDO after RTCKf

ns

0

ns

Delay time, TDO valid after RTCK fall (RTCKf)

ns

(1) Timings for TDO are specified for a maximum of 50-pF load on TDO.

TCK

RTCK

1

TMS

TDI

2

3

TDO

4

5

Figure 6-15. JTAG Timing

90

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6.20.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides

maximum security to the memory content of the device by letting users secure the device after

programming.

Flash Module Output

OTP Contents

(example)

. . .

H

L

H

L

H

L

H

Unlock By Scan

Register

H

L

Internal Tie-Offs

(example only)

L

H

UNLOCK

128-bit comparator

Internal Tie-Offs

(example only)

H

L

H

L

H

Figure 6-16. AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP

address 0xF0000000. The OTP contents are XOR-ed with the contents of the "Unlock By Scan" register.

The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of

this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the

UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least 1 bit in the visible unlock code from 1 to 0. Changing a

0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP)

flash region. Also, changing all 128 bits to zeros is not a valid condition and will permanently secure the

device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By

Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on

the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-

Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap 2 of the

ICEPick module. All other secondary taps, test taps, and the boundary scan interface are not accessible in

this state.

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6.20.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary

scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-17).

Device Pins (conceptual)

TRST

TMS

TCK

TDI

Boundary

Scan

Boundary Scan Interface

TDO

RTCK

TDI

TDO

BSDL

Figure 6-17. Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.

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7 Peripheral Information and Electrical Specifications

7.1 I/O Timings

7.1.1 Input Timings

t_pw

V_CCIO

Input

V_IH

V_IL

0

Figure 7-1. TTL-Level Inputs

Table 7-1. Timing Requirements for Inputs⁽¹⁾

MIN

t_c(VCLK)+ 10⁽²⁾

MAX

UNIT

ns

t_pw

Input minimum pulse width

t_{in_slew}

Time for input signal to go from V_ILto V_IHor from V_IHto V_IL

1

ns

(1) t_c(VCLK)= peripheral VBUS clock cycle time = 1 / f_(VCLK)

(2) The timing shown above is only valid for pin used in general-purpose input mode.

7.1.2 Output Timings

Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (C_L)

PARAMETER

MIN

MAX

2.5

4

UNIT

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL= 50 pF

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

7.2

12.5

2.5

4

8 mA low-EMI pins

(see Table 4-40)

ns

7.2

12.5

5.6

10.4

16.8

23.2

5.6

10.4

16.8

23.2

8

4 mA low-EMI pins

(see Table 4-40)

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

15

23

33

2 mA-z low-EMI pins

(see Table 4-40)

8

15

23

33

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Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (C_L) (continued)

PARAMETER

MIN

MAX

2.5

4

UNIT

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

CL = 15 pF

CL = 50 pF

CL = 100 pF

CL = 150 pF

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

7.2

12.5

2.5

4

8mA mode

7.2

12.5

8

Selectable 8 mA / 2 mA-z pins

(see Table 4-40)

ns

15

23

33

8

2mA-z mode

15

23

33

t_r

t

f

V_CCIO

Output

V_OH

V_OL

0

Figure 7-2. CMOS-Level Outputs

Table 7-3. Timing Requirements for Outputs⁽¹⁾

MIN

MAX

UNIT

Delay between low-to-high, or high-to-low transition of general-purpose output

signals that can be configured by an application in parallel, for example, all signals in

a GIOA port, or all N2HET1 signals, and so forth

t_{d(parallel_out)}

6

ns

(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check

Table 4-40 for output buffer drive strength information on each signal.

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7.1.2.1 Low-EMI Output Buffers

The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of

emissions from the pins which they drive. This is accomplished by adaptively controlling the output buffer

impedance, and is particularly effective with capacitive loads.

This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the

system module GPCR1 register for the desired module or signal, as shown in Table 7-4. The adaptive

impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates

two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of

VCCIO, respectively.

Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then

the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal

ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,

for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which try to

pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer so as to

maintain the output voltage at or below VREFLOW.

Conversely, once the output buffer has driven the output to a high level, if the output voltage is above

VREFHIGH then the output buffer impedance will again increase to Hi-Z. A high degree of decoupling

between internal power bus ad output pin will occur with capacitive loads or any loads in which no current

is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer

which try to pull the output voltage below VREFHIGH will be opposed by the output buffer impedance so

as to maintain the output voltage at or above VREFHIGH.

The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance

control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this

manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.

Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will

allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a

negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an

issue because the actual clamp current capability is always greater than the IOH / IOL specifications.

The low-EMI output buffers are automatically configured to be in the standard buffer mode when the

device enters a low-power mode.

Table 7-4. Low-EMI Output Buffer Hookup

LOW-EMI OUTPUT BUFFER SIGNAL HOOKUP

MODULE or SIGNAL NAME

LOW-POWER MODE (LPM)

STANDARD BUFFER ENABLE (SBEN)

GPREG1.0

Module: MibSPI1

Reserved

GPREG1.1

GPREG1.2

GPREG1.3

GPREG1.4

GPREG1.5

GPREG1.6

GPREG1.7

GPREG1.8

GPREG1.9

GPREG1.10

GPREG1.11

GPREG1.12

GPREG1.13

GPREG1.14

Module: MibSPI3

Reserved

Module: MibSPI5

Reserved

LPM signal from SYS module

Signal: TMS

Reserved

Signal: TDO

Signal: RTCK

Reserved

Signal: nERROR

Reserved

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7.2 Enhanced PWM Modules (ePWM)

Figure 7-3 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.

PINMMR36[25]

NHET1_LOOP_SYNC

EPWMSYNCI

EPWM1A

EPWM1TZINTn

EPWM1INTn

VIM

EPWM1B

TZ1/2/3n

Mux

Selector

SOCA1, SOCB1

ADC Wrapper

EPWM1

VBus32

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL Slip

EQEP1 + EQEP2

System Module

CPU

TZ4n

VCLK4, SYS_nRST

EPWM1ENCLK

TBCLKSYNC

TZ5n

TZ6n

Debug Mode Entry

EPWM2/3/4/5/6A

EPWM2/3/4/5/6B

EPWM2/3/4/5/6TZINTn

EPWM2/3/4/5/6INTn

VIM

TZ1/2/3n

ADC Wrapper

Mux

Selector

SOCA2/3/4/5/6

SOCB2/3/4/5/6

EPWM

2/3/4/5/6

VBus32

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL Slip

EQEP1 + EQEP2

System Module

CPU

TZ4n

VCLK4, SYS_nRST

EPWM2/3/4/5/6ENCLK

TBCLKSYNC

TZ5n

TZ6n

Debug Mode Entry

EPWM7A

EPWM7TZINTn

EPWM7INTn

VIM

EPWM7B

TZ1/2/3n

Mux

Selector

SOCA7, SOCB7

ADC Wrapper

EPWM

7

VBus32

EQEP1ERR / EQEP2ERR /

EQEP1ERR or EQEP2ERR

OSC FAIL or PLL SLip

EQEP1 + EQEP2

System Module

CPU

TZ4n

TZ5n

TZ6n

VCLK4, SYS_nRST

EPWM7ENCLK

TBCLKSYNC

Debug Mode Entry

Pulse

Stretch,

8 VCLK4

cycles

EPWMSYNCO

ECAP1

VBus32 / VBus32DP

ECAP

1

ECAP1INTn

VIM

A. For more detail on the input synchronization selection of the TZ1/TZ2/TZ3n pins to each ePWMx module, see

Figure 7-4.

Figure 7-3. ePWMx Module Interconnections

Figure 7-4 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double-synchronous + filter width) for ePWMx.

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TZxn

(x = 1, 2, or 3)

double

sync

ePWMx

(x = 1 through 7)

6 VCLK4

Cycles Filter

Figure 7-4. ePWMx Input Synchronization Selection Detail

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7.2.1 ePWM Clocking and Reset

Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active-low, the clock

enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When

SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-5. ePWMx Clock Enable Control

CONTROL REGISTER TO

ePWM MODULE INSTANCE

DEFAULT VALUE

ENABLE CLOCK

PINMMR37[8]

PINMMR37[16]

PINMMR37[24]

PINMMR38[0]

PINMMR38[8]

PINMMR38[16]

PINMMR38[24]

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

1

The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means

that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can

choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control

register bit.

7.2.2 Synchronization of ePWMx Time-Base Counters

A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM

module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The

input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-3 shows the

synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or

ignore the synchronization input. For more information, see the ePWM chapter in the device-specific

Technical Reference Manual (TRM).

7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base

The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented

as shown in Figure 7-5.

N2HET1_LOOP_SYNC

EXT_LOOP_SYNC

N2HET1

N2HET2

ePWM1

2 VCLK4 cycles

Pulse Stretch

SYNCI

EPWM1SYNCI

double

sync

PINMMR36[25]

6 VCLK4

Cycles Filter

PINMMR47[8,9,10]

Figure 7-5. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules

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7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules

The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM

modules on a device. This bit is implemented as PINMMR37 register bit 1.

When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default

condition.

When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.

For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must

be set identically. The proper procedure for enabling the ePWM clocks is as follows:

1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-5.

2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.

3. Configure the prescaler values and desired ePWM modes.

4. Configure TBCLKSYNC = 1.

7.2.5 ePWM Synchronization with External Devices

The output sync from the ePWM1 module is also exported to a device output terminal so that multiple

devices can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being

exported on the terminal as the EPWM1SYNCO signal.

7.2.6 ePWM Trip Zones

7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n

These three trip zone inputs are driven by external circuits and are connected to device-level inputs.

These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-

synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter

before connecting to the ePWMx (see Figure 7-4). By default, the trip zone inputs are asynchronously

connected to the ePWMx modules.

Table 7-6. Connection to ePWMx Modules for Device-Level Trip Zone Inputs

CONTROL FOR

ASYNCHRONOUS

CONNECTION TO ePWMx

CONTROL FOR

DOUBLE-SYNCHRONIZED

CONNECTION TO ePWMx

TRIP ZONE

INPUT

DOUBLE-SYNCHRONIZED AND

FILTERED CONNECTION TO

ePWMx⁽¹⁾

TZ1n

TZ2n

TZ3n

PINMMR46[18:16] = 001

PINMMR46[26:24] = 001

PINMMR47[2:0] = 001

PINMMR46[18:16] = 010

PINMMR46[26:24] = 010

PINMMR47[2:0] = 010

PINMMR46[18:16] = 100

PINMMR46[26:24] = 100

PINMMR47[2:0] = 100

(1) The filter width is 6 VCLK4 cycles.

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7.2.6.2 Trip Zone TZ4n

This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device.

Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control

registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on

the requirements of the application.

Table 7-7. TZ4n Connections for ePWMx Modules

CONTROL FOR TZ4n =

NOT(EQEP1ERR OR EQEP2ERR)

CONTROL FOR TZ4n =

NOT(EQEP1ERR)

CONTROL FOR TZ4n =

NOT(EQEP2ERR)

ePWMx

ePWM1

ePWM2

ePWM3

ePWM4

ePWM5

ePWM6

ePWM7

PINMMR41[2:0] = 001

PINMMR41[10:8] = 001

PINMMR41[18:16] = 001

PINMMR41[26:24] = 001

PINMMR42[2:0] = 001

PINMMR42[10:8] = 001

PINMMR42[18:16] = 001

PINMMR41[2:0] = 010

PINMMR41[2:0] = 100

PINMMR41[10:8] = 010

PINMMR41[18:16] = 010

PINMMR41[26:24] = 010

PINMMR42[2:0] = 010

PINMMR42[10:8] = 010

PINMMR42[18:16] = 010

PINMMR41[10:8] = 100

PINMMR41[18:16] = 100

PINMMR41[26:24] = 100

PINMMR42[2:0] = 100

PINMMR42[10:8] = 100

PINMMR42[18:16] = 100

7.2.6.3 Trip Zone TZ5n

This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted

whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip

zone input for each ePWMx module to prevent the external system from going out of control when the

device clocks are not within expected range (system running at limp clock).

The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the

system module. These level signals are set until cleared by the application.

7.2.6.4 Trip Zone TZ6n

This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,

the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the

external system from going out of control when the CPU is stopped.

7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

A special scheme is implemented to select the actual signal used for triggering the start of conversion on

the two ADCs on this device. This scheme is defined in Section 7.5.2.3.

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7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings

Table 7-8. ePWMx Timing Requirements

TEST CONDITIONS

MIN

2 t_c(VCLK4)

MAX UNIT

Asynchronous

t_w(SYNCIN)

Synchronization input pulse width

Synchronous

2 t_c(VCLK4)

cycles

Synchronous, with input filter

2 t_c(VCLK4)+ filter width⁽¹⁾

(1) The filter width is 6 VCLK4 cycles

Table 7-9. ePWMx Switching Characteristics

TEST

CONDITIONS

PARAMETER

Pulse duration, ePWMx output high or low

MIN

MAX

UNIT

t_w(PWM)

33.33

ns

t_w(SYNCOUT)

Synchronization Output Pulse Width

8 t_c(VCLK4)

cycles

Delay time, trip input active to PWM forced high, or

Delay time, trip input active to PWM forced low

t_d(PWM)tza

No pin load

25

20

ns

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

Table 7-10. ePWMx Trip-Zone Timing Requirements

TEST CONDITIONS

MIN

MAX UNIT

2 * HSPCLKDIV * CLKDIV *

Asynchronous

(1)

t_c(VCLK4)

t_w(TZ)

Pulse duration, TZn input low

cycles

Synchronous

2 t_c(VCLK4)

Synchronous, with input filter

2 t_c(VCLK4)+ filter width

(1) For more information on the clock divider fields: HSPCLKDIV and CLKDIV, see the ePWM chapter of the device-specific Technical

Reference Manual (TRM).

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7.3 Enhanced Capture Modules (eCAP)

Figure 7-6 shows how the eCAP modules are interconnected on this microcontroller.

EPWM1SYNCO

ECAP1SYNCI

ECAP1

ECAP1INTn

ECAP1

VIM

VBus32

VCLK4, SYS_nRST

ECAP1ENCLK

ECAP1SYNCO

ECAP2SYNCI

ECAP2

ECAP

2/3/4/5

ECAP2INTn

VIM

VBus32

VCLK4, SYS_nRST

ECAP2ENCLK

ECAP2SYNCO

ECAP6

ECAP

6

VBus32

VIM

ECAP6INTn

VCLK4, SYS_nRST

ECAP6ENCLK

A. For more detail on the input synchronization selection of the ECAPx pins to each eCAPx module, see Figure 7-7.

Figure 7-6. eCAPx Module Connections

Figure 7-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double-synchronous + filter width) for eCAPx.

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ECAPx

(x = 1, 2, 3, 4, 5, or 6)

double

sync

eCAPx

6 VCLK4

Cycles Filter

(x = 1 through 6)

Figure 7-7. eCAPx Input Synchronization Selection Detail

7.3.1 Clock Enable Control for eCAPx Modules

Each of the eCAPx modules have a clock enable (ECAPxENCLK). These signals must be generated from

a device-level control register. When SYS_nRST is active-low, the clock enables are ignored and the

ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the

state of clock enable is respected.

Table 7-11. eCAPx Clock Enable Control

CONTROL REGISTER TO

eCAP MODULE INSTANCE

DEFAULT VALUE

ENABLE CLOCK

PINMMR39[0]

PINMMR39[8]

PINMMR39[16]

PINMMR39[24]

PINMMR40[0]

PINMMR40[8]

eCAP1

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

1

The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that

the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose

to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register

bit.

7.3.2 PWM Output Capability of eCAPx

When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM

output. This is called the Auxiliary PWM (APWM) mode of operation of the eCAPx modules. For more

information, see the eCAP module chapter of the device-specific TRM.

7.3.3 Input Connection to eCAPx Modules

The input connection to each of the eCAPx modules can be selected between a double-VCLK4-

synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.

Table 7-12. Device-Level Input Connection to eCAPx Modules

CONTROL FOR

INPUT SIGNAL

DOUBLE-SYNCHRONIZED

CONNECTION TO eCAPx

DOUBLE-SYNCHRONIZED AND

FILTERED CONNECTION TO eCAPx⁽¹⁾

eCAP1

eCAP2

eCAP3

eCAP4

eCAP5

eCAP6

PINMMR43[2:0] = 001

PINMMR43[2:0] = 010

PINMMR43[10:8] = 001

PINMMR43[18:16] = 001

PINMMR43[26:24] = 001

PINMMR44[2:0] = 001

PINMMR44[10:8] = 001

PINMMR43[10:8] = 010

PINMMR43[18:16] = 010

PINMMR43[26:24] = 010

PINMMR44[2:0] = 010

PINMMR44[10:8] = 010

(1) The filter width is 6 VCLK4 cycles.

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7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing

Table 7-13. eCAPx Timing Requirements

TEST CONDITIONS

MIN

2 t_c(VCLK4)

2 t_c(VCLK4)+ filter width⁽¹⁾

MAX

UNIT

Synchronous

t_w(CAP)

Pulse width, capture input

cycles

Synchronous with input filter

(1) The filter width is 6 VCLK4 cycles.

Table 7-14. eCAPx Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

t_w(APWM)

Pulse duration, APWMx output high or low

20

ns

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7.4 Enhanced Quadrature Encoder (eQEP)

Figure 7-8 shows the eQEP module interconnections on the device.

VBus32

EQEP1A

EQEP1B

EQEP1ENCLK

VCLK4

SYS_nRST

EQEP1I

EQEP1IO

EQEP1IOE

EQEP1

Module

EPWM1/../7

EQEP1INTn

VIM

EQEP1ERR

EQEP1S

EQEP1SO

EQEP1SOE

IO

Mux

VBus32

EQEP2A

EQEP2B

EQEP2ENCLK

VCLK4

SYS_nRST

EQEP2I

EQEP2IO

EQEP2IOE

EQEP2

Module

EQEP2INTn

VIM

Connection

Selection

Mux

EQEP2ERR

EQEP2S

EQEP2SO

EQEP2SOE

A. For more detail on the eQEP input synchronization selection of the EQEPxA/B pins to each eQEPx module, see

Figure 7-9.

Figure 7-8. eQEP Module Interconnections

Figure 7-9 shows the detailed input synchronization selection (asynchronous, double-synchronous, or

double-synchronous + filter width) for eQEPx.

EQEPxA or EQEPxB

(x = 1 or 2)

double

sync

eQEPx

6 VCLK4

Cycles Filter

(x = 1 or 2)

Figure 7-9. eQEPx Input Synchronization Selection Detail

7.4.1 Clock Enable Control for eQEPx Modules

Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST

is active-low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper

state. When SYS_nRST goes in-active high, the state of clock enable is respected.

The default value of the control registers to enable the clocks to the eQEPx modules is 1 (see Table 7-15).

This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The

application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the

respective control register bit.

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Table 7-15. eQEPx Clock Enable Control

CONTROL REGISTER TO

ENABLE CLOCK

eQEP MODULE INSTANCE

DEFAULT VALUE

eQEP1

eQEP2

PINMMR40[16]

PINMMR40[24]

1

7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs

EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection

multiplexer. This multiplexer is defined in Table 7-7. As shown in Figure 7-3, the output of this selection

multiplexer is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection

allows the application to define the response of each ePWMx module on a phase error indicated by the

eQEP modules.

7.4.3 Input Connections to eQEPx Modules

The input connections to each of the eQEP modules can be selected between a double-VCLK4-

synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-16.

Table 7-16. Device-Level Input Connection to eQEPx Modules

CONTROL FOR

INPUT SIGNAL

DOUBLE-SYNCHRONIZED

CONNECTION TO eQEPx

DOUBLE-SYNCHRONIZED AND

FILTERED CONNECTION TO eQEPx⁽¹⁾

eQEP1A

eQEP1B

eQEP1I

eQEP1S

eQEP2A

eQEP2B

eQEP2I

eQEP2S

PINMMR44[18:16] = 001

PINMMR44[18:16] = 010

PINMMR44[26:24] = 001

PINMMR45[2:0] = 001

PINMMR45[10:8] = 001

PINMMR45[18:16] = 001

PINMMR45[26:24] = 001

PINMMR46[2:0] = 001

PINMMR46[10:8] = 001

PINMMR44[26:24] = 010

PINMMR45[2:0] = 010

PINMMR45[10:8] = 010

PINMMR45[18:16] = 010

PINMMR45[26:24] = 010

PINMMR46[2:0] = 010

PINMMR46[10:8] = 010

(1) The filter width is 6 VCLK4 cycles.

7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 7-17. eQEPx Timing Requirements⁽¹⁾

TEST CONDITIONS

MIN

2 t_c(VCLK4)

MAX UNIT

t_w(QEPP)

QEP input period

Synchronous

cycles

Synchronous with input filter

Synchronous

2 t_c(VCLK4)+ filter width

2 t_c(VCLK4)

t_w(INDEXH)

t_w(INDEXL)

t_w(STROBH)

t_w(STROBL)

QEP Index Input High Time

QEP Index Input Low Time

QEP Strobe Input High Time

QEP Strobe Input Low Time

cycles

Synchronous with input filter

Synchronous

2 t_c(VCLK4)+ filter width

2 t_c(VCLK4)

Synchronous with input filter

Synchronous

2 t_c(VCLK4)+ filter width

2 t_c(VCLK4)

Synchronous with input filter

Synchronous

2 t_c(VCLK4)+ filter width

2 t_c(VCLK4)

Synchronous with input filter

2 t_c(VCLK4)+ filter width

(1) The filter width is 6 VCLK4 cycles.

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Table 7-18. eQEPx Switching Characteristics

PARAMETER

MIN

MAX

4 t_c(VCLK4)

6 t_c(VCLK4)

UNIT

cycles

t_d(CNTR)xin

Delay time, external clock to counter increment

Delay time, QEP input edge to position compare sync output

t_{d(PCS-OUT)QEP}

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7.5 12-Bit Multibuffered Analog-to-Digital Converter (MibADC)

The MibADC has a separate power bus for its analog circuitry that enhances the Analog-to-Digital (A-to-D)

performance by preventing digital switching noise on the logic circuitry which could be present on V_SSand

V_CCfrom coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to

AD_REFLO, unless otherwise noted.

Table 7-19. MibADC Overview

DESCRIPTION

Resolution

VALUE

12 bits

Assured

Monotonic

Output conversion code

00h to 3FFh [00 for V_AI≤ AD_REFLO; 3FFh for V_AI≥ AD_REFHI]

7.5.1 Features

•

12-bit resolution

AD_REFHIand AD_REFLOpins (high and low reference voltages)

Total Sample/Hold/Convert time: 600 ns Minimum at 30 MHz ADCLK

One memory region per conversion group is available (Event Group, Group 1, and Group 2)

Allocation of channels to conversion groups is completely programmable

Supports flexible channel conversion order

Memory regions are serviced either by interrupt or by DMA

Programmable interrupt threshold counter is available for each group

Programmable magnitude threshold interrupt for each group for any one channel

Option to read either 8-, 10-, or 12-bit values from memory regions

Single or continuous conversion modes

Embedded self-test

Embedded calibration logic

Enhanced power-down mode

–

Optional feature to automatically power down ADC core when no conversion is in progress

•

External event pin (ADxEVT) programmable as general-purpose I/O

7.5.2 Event Trigger Options

The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these

three groups can be configured to be triggered by a hardware event. In that case, the application can

select the trigger, from among eight event sources, to convert a group.

7.5.2.1 MibADC1 Event Trigger Hookup

Table 7-20 lists the event sources that can trigger the conversions for the MibADC1 groups.

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NOTE

If ADEVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC1

module trigger input is made from the output side of the input buffer. This way, a trigger

condition can be generated either by configuring the function as output onto the pad (through

the mux control), or by driving the function from an external trigger source as input. If the

mux control module is used to select different functionality instead of the ADEVT, N2HET1[x]

or GIOB[x] signals, then care must be taken to disable these signals from triggering

conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],

N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made

directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered

without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

7.5.2.2 MibADC2 Event Trigger Hookup

Table 7-21 lists the event sources that can trigger the conversions for the MibADC2 groups.

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Notes

If AD2EVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC2

module trigger input is made from the output side of the input buffer. This way, a trigger

condition can be generated either by configuring the function as output onto the pad (through

the mux control), or by driving the function from an external trigger source as input. If the

mux control module is used to select different functionality instead of the AD2EVT,

N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from

triggering conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],

N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made

directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered

without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules

As shown in Figure 7-10, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are

used to generate four signals – ePWM_B, ePWM_A1, ePWM_A2, and ePWM_AB, that are available to

trigger the ADC based on the application requirement.

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SOCAEN, SOCBEN bits

inside ePWMx modules

Controlled by PINMMR

EPWM1SOCA

EPWM1

module

EPWM1SOCB

EPWM2SOCA

EPWM2SOCB

EPWM2

module

EPWM3SOCA

EPWM3SOCB

EPWM3

module

EPWM4SOCA

EPWM4SOCB

EPWM4

module

EPWM5SOCA

EPWM5SOCB

EPWM5

module

EPWM6SOCA

EPWM6SOCB

EPWM6

module

EPWM7SOCA

EPWM7SOCB

EPWM7

module

ePWM_B ePWM_A1 ePWM_A2 ePWM_AB

Figure 7-10. ADC Trigger Source Generation from ePWMx

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Table 7-22. Control Bit to SOC Output

CONTROL BIT

PINMMR35[0]

PINMMR35[8]

PINMMR35[16]

PINMMR35[24]

PINMMR36[0]

PINMMR36[8]

PINMMR36[16]

SOC OUTPUT

SOC1A_SEL

SOC2A_SEL

SOC3A_SEL

SOC4A_SEL

SOC5A_SEL

SOC6A_SEL

SOC7A_SEL

The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-10. This switch

is implemented by using the control registers in the PINMMR module. Figure 7-11 shows an example of

the implementation for the switch on SOC1A. The switches on the other SOCA signals are implemented in

the same way.

0

1

SOC1A

ePWM1

PINMMR164[0]

EPWM1SOCA

From switch on

SOC2A

when PINMMR164[8] = 1

0

1

From switch on

SOC2A

when PINMMR164[8] = 0

Figure 7-11. ePWM1SOC1A Switch Implementation

The logic equations ( Equation 1, Equation 2, Equation 3, and Equation 4) for the four outputs from the

combinational logic shown in Figure 7-10 are:

ePWM_B = SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B

ePWM_A1 = [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or

[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or

[ SOC7A and not(SOC7A_SEL) ]

(1)

(2)

ePWM_A2 = [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or

[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or

[ SOC7A and SOC7A_SEL ]

(3)

(4)

ePWM_AB = ePWM_B or ePWM_A2

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7.5.3 ADC Electrical and Timing Specifications

Table 7-23. MibADC Recommended Operating Conditions

PARAMETER

A-to-D high-voltage reference source

MIN

MAX

UNIT

V

(1)

AD_REFHI

AD_REFLO

V_AI

AD_REFLO

V_CCAD

(1)

A-to-D low-voltage reference source

V_SSAD

AD_REFHI

2

V

Analog input voltage

Analog input clamp current⁽²⁾(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

AD_REFLO

–2

V

I_AIC

mA

(1) For V_CCADand V_SSADrecommended operating conditions, see Section 5.4.

(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 7-24. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER

DESCRIPTION/CONDITIONS

MIN

MAX UNIT

R_mux

R_samp

C_mux

C_samp

Analog input mux on-resistance

ADC sample switch on-resistance

Input mux capacitance

See Figure 7-12

250

16

13

200

500

250

1000

2

Ω

pF

ADC sample capacitance

V

_SSAD≤ V_IN< V_SSAD+ 100 mV

–300

–200

–1000

–250

–8

V_CCAD= 3.6 V

maximum

I_AIL

Analog off-state input leakage current

ADC1 Analog on-state input bias current

ADC2 Analog on-state input bias current

ADC1 Analog on-state input bias current

ADC2 Analog on-state input bias current

V_SSAD+ 100 mV ≤ V_IN≤ V_CCAD– 200 mV

V_CCAD– 200 mV < V_IN≤ V_CCAD

nA

µA

V_SSAD≤ V_IN< V_SSAD+ 300 mV

V_CCAD= 5.25 V

maximum

I_AIL

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD– 300 mV

V_CCAD– 300 mV < V_IN≤ V_CCAD

V_SSAD≤ V_IN< V_SSAD+ 100 mV

V_CCAD= 3.6 V

maximum

(1)

I_AOSB1

I_AOSB2

I_AOSB1

I_AOSB2

V_SSAD+ 100 mV < V_IN< V_CCAD– 200 mV

V_CCAD– 200 mV < V_IN< V_CCAD

–4

2

–4

12

2

V_SSAD≤ V_IN< V_SSAD+ 100 mV

–7

V_CCAD= 3.6 V

maximum

V_SSAD+ 100 mV ≤ V_IN≤ V_CCAD– 200 mV

V_CCAD- 200 mV < V_IN≤ V_CCAD

–4

2

–4

10

3

V_SSAD≤ V_IN< V_SSAD+ 300 mV

–10

–5

V_CCAD= 5.25 V

maximum

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD– 300 mV

V_CCAD– 300 mV < V_IN≤ V_CCAD

3

–5

14

3

V_SSAD≤ V_IN< V_SSAD+ 300 mV

–8

V_CCAD= 5.25 V

maximum

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD– 300 mV

V_CCAD– 300 mV < V_IN≤ V_CCAD

–5

3

–5

12

3

I_ADREFHI

I_CCAD

AD_REFHIinput current

Static supply current

AD_REFHI= V_CCAD, AD_REFLO= V_SSAD

Normal operating mode

mA

µA

15

5

ADC core in power down mode

(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to I_AOSB1+ I_AOSB2

.

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R_ext

P_in

R_mux

S_mux

V_S1

I_AOSB

C_ext

On-State

Bias Current

S_mux

R_ext

P_in

R_mux

V_S2

I_AIL

C_ext

I_AIL

Off-State

Leakages

S_mux

R_ext

P_in

R_mux

S_samp

R_samp

V_S24

I_AIL

C_samp

C_mux

C_ext

I_AIL

Figure 7-12. MibADC Input Equivalent Circuit

Table 7-25. MibADC Timing Specifications

PARAMETER

MIN NOM

MAX UNIT

(1)

t_c(ADCLK)

Cycle time, MibADC clock

0.033

µs

(2)

t_d(SH)

Delay time, sample and hold time

Delay time from ADC power on until first input can be sampled

12-BIT MODE

0.2

1

t_d(PU-ADV)

t_d(C)

Delay time, conversion time

0.4

0.6

µs

(3)

t_d(SHC)

Delay time, total sample/hold and conversion time

10-BIT MODE

t_d(C)

Delay time, conversion time

0.33

0.53

µs

(3)

t_d(SHC)

Delay time, total sample/hold and conversion time

(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register

bits 4:0.

(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each

conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as

well as the internal impedance of the ADC.

(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors (for

example, the prescale settings).

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Table 7-26. MibADC Operating Characteristics Over Full Ranges of Recommended Operating

Conditions⁽¹⁾⁽²⁾

PARAMETER

DESCRIPTION/CONDITIONS

AD_REFHI– AD_REFLO

MIN NOM MAX UNIT

Conversion range over which

specified accuracy is maintained

CR

3

5.25

V

10-bit mode

12-bit mode

10-bit mode

1

2

Difference between the first ideal transition (from

code 000h to 001h) and the actual transition

Z_SET

Zero Scale Offset

LSB

Difference between the range of the measured

code transitions (from first to last) and the range of

the ideal code transitions

F_SET

E_DNL

E_INL

Full Scale Offset

LSB

12-bit mode

3

10-bit mode

12-bit mode

10-bit mode

± 1.5

± 2

Difference between the actual step width and the

ideal value (see Figure 7-13).

Differential nonlinearity error

Integral nonlinearity error

Total unadjusted error

Maximum deviation from the best straight line

through the MibADC. MibADC transfer

characteristics, excluding the quantization error.

± 2

12-bit mode

± 2

10-bit mode

12-bit mode

± 2

± 4

Maximum value of the difference between an

analog value and the ideal midstep value.

E_TOT

(1) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹²for 12-bit mode

(2) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹⁰for 10-bit mode

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7.5.4 Performance (Accuracy) Specifications

7.5.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 7-13 (sometimes referred to as differential linearity) is

the difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

Differential Linearity

Error (–½ LSB)

1 LSB

0 ... 010

Differential Linearity

Error (–½ LSB)

0 ... 001

0 ... 000

1 LSB

0

1

2

3

4

5

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 7-13. Differential Nonlinearity (DNL) Error^(A)

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The integral nonlinearity error shown in Figure 7-14 (sometimes referred to as linearity error) is the

deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Actual

Transition

At Transition

011/100

(–½ LSB)

End-Point Lin. Error

At Transition

001/010 (–1/4 LSB)

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 7-14. Integral Nonlinearity (INL) Error^(A)

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7.5.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 7-15 is the maximum value of the

difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(–1 1/4 LSB)

0 ... 011

0 ... 010

Total Error

At Step

0 ... 001 (1/2 LSB)

0 ... 001

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

A. 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

Figure 7-15. Absolute Accuracy (Total) Error^(A)

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7.6 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and

bit-programmable. Both GIOA and GIOB support external interrupt capability.

7.6.1 Features

The GPIO module has the following features:

•

Each I/O pin can be configured as:

–

Input

Output

Open drain

•

The interrupts have the following characteristics:

–

Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)

Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)

Individual interrupt flags (set in GIOFLG register)

Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers,

respectively

–

Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers

•

Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 7.1.1 and Section 7.1.2.

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7.7 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or general-purpose I/O. The N2HET is especially well suited for applications

requiring multiple sensor information and drive actuators with complex and accurate time pulses.

7.7.1 Features

The N2HET module has the following features:

•

Programmable timer for input and output timing functions

Reduced instruction set (30 instructions) for dedicated time and angle functions

160 words of instruction RAM protected by parity

User-defined number of 25-bit virtual counters for timer, event counters, and angle counters

7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual

counters

•

Up to 32 pins usable for input signal measurements or output signal generation

Programmable suppression filter for each input pin with adjustable limiting frequency

Low CPU overhead and interrupt load

Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)

or DMA

•

Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

7.7.2 N2HET RAM Organization

The timer RAM uses four RAM banks, where each bank has two port access capability. This means that

one RAM address may be written while another address is read. The RAM words are 96 bits wide, which

are split into three 32-bit fields (program, control, and data).

7.7.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

1

N2HETx

3

4

2

Figure 7-16. N2HET Input Capture Timings

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Table 7-27. Dynamic Characteristics for the N2HET Input Capture Functionality

PARAMETER

MIN

MAX UNIT

Input signal period, PCNT or WCAP for rising edge to

rising edge

1

2

3

4

(HRP) (LRP) tc_(VCLK2)+ 2 2²⁵(HRP) (LRP) tc_(VCLK2)– 2

2 (HRP) tc_(VCLK2)+ 2 2²⁵(HRP) (LRP) tc_(VCLK2)– 2

ns

Input signal period, PCNT or WCAP for falling edge to

falling edge

Input signal high phase, PCNT or WCAP for rising edge

to falling edge

Input signal low phase, PCNT or WCAP for falling edge

to rising edge

7.7.4 N2HET1 to N2HET2 Synchronization

In some applications the N2HET resolutions must be synchronized. Some other applications require a

single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures

the N2HET in master or slave mode (default is slave mode). An N2HET in master mode provides a signal

to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to

the loop resolution signal sent by the master. The slave does not require this signal after it receives the

first synchronization signal. However, anytime the slave receives the resynchronization signal from the

master, the slave must synchronize itself again.

N2HET1

N2HET2

NHET_LOOP_SYNC

EXT_LOOP_SYNC

NHET_LOOP_SYNC

EXT_LOOP_SYNC

Figure 7-17. N2HET1 to N2HET2 Synchronization Hookup

7.7.5 N2HET Checking

7.7.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be

used to monitor each other’s signals, as shown in Figure 7-18. The direction of the monitoring is controlled

by the I/O multiplexing control module.

IOMM mux control signal x

N2HET1[1,3,5,7,9,11]

N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]

N2HET1

N2HET2[8,10,12,14,16,18]

N2HET2

Figure 7-18. N2HET Monitoring

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7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the PWM signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to

measure the frequency of the PWM signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection

to the DCC module is made directly from the output of the N2HETx module (from the input of the output

buffer).

For more information on DCC, see Section 6.7.3.

7.7.6 Disabling N2HET Outputs

Some applications require disabling the N2HET outputs under some fault condition. The N2HET module

provides this capability through the Pin Disable input signal. This signal, when driven low, causes the

N2HET outputs identified by a programmable register (HETPINDIS) to be in a high-impedance (tri-state)

state. For more details on the N2HET Pin Disable feature, see the device-specific Terminal Reference

Manual.

GIOA[5] is connected to the Pin Disable input for N2HET1, and GIOB[2] is connected to the Pin Disable

input for N2HET2.

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7.7.7 High-End Timer Transfer Unit (HET)

A High-End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or

from main memory. A Memory Protection Unit (MPU) is built into the HET TU.

7.7.7.1 Features

•

CPU and DMA independent

•

Master port to access system memory

8 control packets supporting dual buffer configuration

Control packet information is stored in RAM protected by parity

Event synchronization (HET transfer requests)

Supports 32- or 64-bit transactions

Addressing modes for HET address (8- or 16-byte) and system memory address (fixed, 32- or 64-bit)

One shot, circular, and auto-switch buffer transfer modes

Request lost detection

7.7.7.2 Trigger Connections

For the transfer request line trigger connections to the N2HET TU when an instruction-specific condition is

true, see Table 7-28 and Table 7-29.

Table 7-28. HET TU1 Request Line Connection

MODULES

N2HET1

REQUEST SOURCE

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU1 REQUEST

HET TU1 DCP[0]

HET TU1 DCP[1]

HET TU1 DCP[2]

HET TU1 DCP[3]

HET TU1 DCP[4]

HET TU1 DCP[5]

HET TU1 DCP[6]

HET TU1 DCP[7]

Table 7-29. HET TU2 Request Line Connection

MODULES

REQUEST SOURCE

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU2 REQUEST

N2HET2

HET TU2 DCP[0]

HET TU2 DCP[1]

HET TU2 DCP[2]

HET TU2 DCP[3]

HET TU2 DCP[4]

HET TU2 DCP[5]

HET TU2 DCP[6]

HET TU2 DCP[7]

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7.8 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,

automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

7.8.1 Features

Features of the DCAN module include:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 Mbps

The CAN kernel can be clocked by the oscillator for baud-rate generation.

64 mailboxes on each DCAN

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM protected by parity

Direct access to message RAM during test mode

CAN RX and TX pins configurable as general-purpose I/O pins

Message RAM Auto Initialization

DMA support

For more information on the DCAN, see the device-specific TRM.

7.8.2 Electrical and Timing Specifications

Table 7-30. Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER

Delay time, transmit shift register to CANnTX pin⁽¹⁾

MIN

MAX

15

UNIT

ns

t_d(CANnTX)

t_d(CANnRX)

Delay time, CANnRX pin to receive shift register

5

ns

(1) These values do not include the rise and fall times of the output buffer.

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7.9 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is

an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn

to zero (NRZ) format. The SCI can be used to communicate, for example, through an RS-232 port or over

a K-line.

The LIN standard is based on the SCI (Universal Asynchronous Receiver/Transmitter [UART]) serial data

link format. The communication concept is single-master/multiple-slave with a message identification for

multicast transmission between any network nodes.

7.9.1 LIN Features

The following are features of the LIN module:

•

Compatible to LIN 1.3, 2.0 and 2.1 protocols

Multibuffered receive and transmit units DMA capability for minimal CPU intervention

Identification masks for message filtering

Automatic Master Header Generation

–

Programmable Synch Break Field

Synch Field

Identifier Field

•

Slave Automatic Synchronization

–

Synch break detection

Optional baudrate update

Synchronization Validation

2³¹programmable transmission rates with 7 fractional bits

•

Error detection

2 interrupt lines with priority encoding

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7.10 Serial Communication Interface (SCI)

7.10.1 Features

•

Standard UART communication

Supports full- or half-duplex operation

Standard NRZ format

Double-buffered receive and transmit functions

Configurable frame format of 3 to 13 bits per character based on the following:

–

Data word length programmable from 1 to 8 bits

Additional address bit in address-bit mode

Parity programmable for 0 or 1 parity bit, odd or even parity

Stop programmable for 1 or 2 stop bits

•

Asynchronous or isosynchronous communication modes

Two multiprocessor communication formats allow communication between more than two devices.

Sleep mode is available to free CPU resources during multiprocessor communication.

The 24-bit programmable baud rate supports 2²⁴different baud rates provide high-accuracy baud rate selection.

Four error flags and five status flags provide detailed information regarding SCI events.

Capability to use DMA for transmit and receive data.

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7.11 Inter-Integrated Circuit (I2C) Module

The I2C module is a multimaster communication module providing an interface between the

microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and

connected by an I2C-bus. This module will support any slave or master I2C compatible device.

7.11.1 Features

The I2C module has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number

9398 393 40011)

–

Bit or Byte format transfer

7- and 10-bit device addressing modes

General call

START byte

Multimaster transmitter or slave receiver mode

Multimaster receiver or slave transmitter mode

Combined master transmit or receive and receive or transmit mode

Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)

•

Free data format

Two DMA events (transmit and receive)

DMA event enable or disable capability

Seven interrupts that can be used by the CPU

Module enable or disable capability

The SDA and SCL are optionally configurable as general-purpose I/O

Slew rate control of the outputs

Open-drain control of the outputs

Programmable pullup or pulldown capability on the inputs

Supports Ignore NACK mode

NOTE

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I2C module sends the slave address

second byte every time it sends the slave address first byte)

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7.11.2 I2C I/O Timing Specifications

Table 7-31. I2C Signals (SDA and SCL) Switching Characteristics⁽¹⁾

STANDARD MODE

FAST MODE

MIN

PARAMETER

UNIT

MIN

MAX

149

Cycle time, internal module clock for I2C,

prescaled from VCLK

t_c(I2CCLK)

75.2

149

100

75.2

ns

f_(SCL)

SCL clock frequency

Cycle time, SCL

0

400

kHz

µs

t_c(SCL)

10

2.5

Setup time, SCL high before SDA low (for a

repeated START condition)

t_{su(SCLH-SDAL)}

t_h(SCLL-SDAL)

4.7

4

0.6

µs

Hold time, SCL low after SDA low (for a repeated

START condition)

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

µs

ns

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

Setup time, SDA valid before SCL high

250

100

Hold time, SDA valid after SCL low (for I2C-bus

devices)

t_h(SDA-SCLL)

t_w(SDAH)

t_{su(SCLH-SDAH)}

t_w(SP)

0

4.7

4.0

3.45⁽²⁾

0

0.9

µs

Pulse duration, SDA high between STOP and

START conditions

1.3

Setup time, SCL high before SDA high (for STOP

condition)

0.6

0

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum t_h(SDA-SCLL)for I2C-bus devices has only to be met if the device does not stretch the low period (t_w(SCLL)) of the SCL

signal.

(3) C_b= The total capacitance of one bus line in pF.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

Figure 7-19. I2C Timings

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NOTE

•

A device must internally provide a hold time of at least 300 ns for the SDA signal

(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

•

The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the low period

(t_w(SCLL)) of the SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the

requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if

the device does not stretch the low period of the SCL signal (t_w(SCLL)). If such a device

does stretch the low period of the SCL signal, it must output the next data bit to the SDA

line within t_rmax + t_su(SDA-SCLH). For the rise time, t_rmax value per load capacitance on the

SDA pin, see Table 7-2, Rise time, t_r, 2-mA-z low-EMI pins MAX values.

•

• C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-

times are allowed.

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7.12 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed

length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical

applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers,

and ADCs.

7.12.1 Features

Both standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

11-bit baud clock generator

SPICLK can be internally generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

SPI I/Os not used in the communication can be used as digital I/O signals

Table 7-32. MibSPI/SPI Configurations

MibSPIx/SPIx

MibSPI1

I/Os

MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA

MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA

MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA

SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA

MibSPI3

MibSPI5

SPI2

SPI4

SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA

7.12.2 MibSPI Transmit and Receive RAM Organization

The multibuffer RAM is comprised of 128 buffers. Each entry in the multibuffer RAM consists of four parts:

a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx

module supports eight transfer groups.

7.12.3 MibSPI Transmit Trigger Events

Each transfer group can be configured individually. For each transfer group, a trigger event and a trigger

source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a

selectable trigger source. For example, up to 15 trigger sources are available which can be used by each

transfer group. These trigger options are listed in Table 7-33 and Section 7.12.3.2 for MibSPI1 and

MibSPI3, respectively.

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7.12.3.1 MibSPI1 Event Trigger Hookup

Table 7-33. MibSPI1 Event Trigger Hookup

EVENT NO.

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

TRIGGER

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

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7.12.3.2 MibSPI3 Event Trigger Hookup

Table 7-34. MibSPI3 Event Trigger Hookup

EVENT NO.

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

TRIGGER

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI3 transfers; there is no multiplexing on the input connections.

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7.12.3.3 MibSPI5 Event Trigger Hookup

Table 7-35. MibSPI5 Event Trigger Hookup

EVENT NO.

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

TRIGGER

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI5 transfers; there is no multiplexing on the input connections.

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7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^(1)(2)(3)

NO.

PARAMETER

MIN

MAX UNIT

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

40

256t_c(VCLK)

ns

Pulse duration, SPICLK high (clock

polarity = 0)

t_w(SPCH)M

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

2⁽⁵⁾

3⁽⁵⁾

4⁽⁵⁾

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

Pulse duration, SPICLK low (clock

polarity = 1)

t_w(SPCL)M

Pulse duration, SPICLK low (clock

polarity = 0)

t_w(SPCL)M

ns

Pulse duration, SPICLK high (clock

polarity = 1)

t_w(SPCH)M

Delay time, SPISIMO valid before

SPICLK low (clock polarity = 0)

t_{d(SPCH-SIMO)M}

t_{d(SPCL-SIMO)M}

t_{v(SPCL-SIMO)M}

t_{v(SPCH-SIMO)M}

t_{su(SOMI-SPCL)M}

t_{su(SOMI-SPCH)M}

t_{h(SPCL-SOMI)M}

t_{h(SPCH-SOMI)M}

Delay time, SPISIMO valid before

SPICLK high (clock polarity = 1)

0.5t_c(SPC)M– 6

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 0)

0.5t_c(SPC)M– t_f(SPC)– 4

0.5t_c(SPC)M– t_r(SPC)– 4

t_f(SPC)+ 2.2

Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 1)

Setup time, SPISOMI before SPICLK

low (clock polarity = 0)

Setup time, SPISOMI before SPICLK

high (clock polarity = 1)

t_r(SPC)+ 2.2

Hold time, SPISOMI data valid after

SPICLK low (clock polarity = 0)

10

Hold time, SPISOMI data valid after

SPICLK high (clock polarity = 1)

10

C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

-

CSHOLD = 0

CSHOLD = 1

CSHOLD = 0

CSHOLD = 1

Setup time CS active

until SPICLK high

(clock polarity = 0)

t_f(SPICS)+ t_r(SPC)+ 5.5

C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_r(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

-

t_f(SPICS)+ t_r(SPC)+ 5.5

8⁽⁶⁾t_C2TDELAY

ns

C2TDELAY*t_c(VCLK)+ 2*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+2) * t_c(VCLK)

-

Setup time CS active

until SPICLK low

(clock polarity = 1)

t_f(SPICS)+ t_f(SPC)+ 5.5

C2TDELAY*t_c(VCLK)+ 3*t_c(VCLK)

- t_f(SPICS)+ t_f(SPC)– 7

(C2TDELAY+3) * t_c(VCLK)

-

t_f(SPICS)+ t_f(SPC)+ 5.5

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

+

-

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

+

-

Hold time SPICLK low until CS inactive

(clock polarity = 0)

t_f(SPC)+ t_r(SPICS)- 7

t_f(SPC)+ t_r(SPICS)+ 11

9⁽⁶⁾t_T2CDELAY

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

+

-

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

+

-

Hold time SPICLK high until CS

inactive (clock polarity = 1)

t_r(SPC)+ tr(SPICS) - 7

(C2TDELAY+1) * t_c(VCLK)

t_f(SPICS)– 29

t_r(SPC)+ t_r(SPICS)+ 11

-

10

11

t_SPIENA

SPIENAn Sample point

(C2TDELAY+1)*t_c(VCLK)

ns

SPIENAn Sample point from write to

buffer

t_SPIENAW

(C2TDELAY+2)*t_c(VCLK)

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 7-2.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40 ns.

The external load on the SPICLK pin must be less than 60 pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

6

7

Master In Data

Must Be Valid

SPISOMI

Figure 7-20. SPI Master Mode External Timing (CLOCK PHASE = 0)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

8

9

10

11

SPIENAn

Figure 7-21. SPI Master Mode Chip-Select Timing (CLOCK PHASE = 0)

Peripheral Information and Electrical Specifications

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Table 7-37. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^(1)(2)(3)

NO.

PARAMETER

MIN

MAX UNIT

(4)

1

t_c(SPC)M

Cycle time, SPICLK

40

256t_c(VCLK)ns

Pulse duration, SPICLK high

(clock polarity = 0)

t_w(SPCH)M

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M+ 3

2⁽⁵⁾

ns

Pulse duration, SPICLK low (clock

polarity = 1)

t_w(SPCL)M

t_w(SPCH)M

0.5t_c(SPC)M+ 3

Pulse duration, SPICLK low (clock

polarity = 0)

3⁽⁵⁾

Pulse duration, SPICLK high

(clock polarity = 1)

Valid time, SPICLK high after

SPISIMO data valid (clock polarity

= 0)

t_{v(SIMO-SPCH)M}

t_{v(SIMO-SPCL)M}

t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

0.5t_c(SPC)M– 6

4⁽⁵⁾

ns

Valid time, SPICLK low after

SPISIMO data valid (clock polarity

= 1)

0.5t_c(SPC)M– 6

Valid time, SPISIMO data valid

after SPICLK high (clock polarity =

0)

0.5t_c(SPC)M– t_r(SPC)– 4

5⁽⁵⁾

6⁽⁵⁾

7⁽⁵⁾

ns

Valid time, SPISIMO data valid

after SPICLK low (clock polarity =

1)

0.5t_c(SPC)M– t_f(SPC)– 4

Setup time, SPISOMI before

SPICLK high (clock polarity = 0)

t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

t_r(SPC)+ 2.2

t_f(SPC)+ 2.2

Setup time, SPISOMI before

SPICLK low (clock polarity = 1)

Valid time, SPISOMI data valid

after SPICLK high (clock polarity =

0)

t_{v(SPCH-SOMI)M}

10

Valid time, SPISOMI data valid

after SPICLK low (clock polarity =

1)

t_{v(SPCL-SOMI)M}

10

0.5*t_c(SPC)M+ (C2TDELAY+2) *

CSHOLD =

t_c(VCLK)

-

t_c(VCLK)-

Setup time CS

0

t_f(SPICS)+ t_r(SPC)– 7

t_f(SPICS)+ t_r(SPC)+ 5.5

active until SPICLK

high (clock polarity =

0.5*t_c(SPC)M+ (C2TDELAY+3) *

CSHOLD =

0)

t_c(VCLK)

-

t_c(VCLK)-

t_f(SPICS)+ t_r(SPC)+ 5.5

1

t_f(SPICS)+ t_r(SPC)– 7

8⁽⁶⁾t_C2TDELAY

ns

0.5*t_c(SPC)M+ (C2TDELAY+2) *

CSHOLD =

t_c(VCLK)

-

t_c(VCLK)-

t_f(SPICS)+ t_f(SPC)+ 5.5

Setup time CS

0

t_f(SPICS)+ t_f(SPC)– 7

active until SPICLK

low (clock polarity =

0.5*t_c(SPC)M+ (C2TDELAY+3) *

CSHOLD =

1)

t_c(VCLK)

-

t_c(VCLK)

-

1

t_f(SPICS)+ t_f(SPC)– 7

t_f(SPICS)+ t_f(SPC)+ 5.5

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)

-

+

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_f(SPC)

-

+

Hold time SPICLK low until CS

inactive (clock polarity = 0)

t_r(SPICS)- 7

t_r(SPICS)+ 11

9⁽⁶⁾t_T2CDELAY

ns

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)

-

+

T2CDELAY*t_c(VCLK)+ t_c(VCLK)

t_r(SPC)

-

+

Hold time SPICLK high until CS

inactive (clock polarity = 1)

t_r(SPICS)- 7

t_r(SPICS)+ 11

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see Table 7-2.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40 ns.

The external load on the SPICLK pin must be less than 60 pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.

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Table 7-37. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,

SPISIMO = output, and SPISOMI = input)^(1)(2)(3)(continued)

NO.

PARAMETER

MIN

MAX UNIT

(C2TDELAY+1)* t_c(VCLK)

-

10 t_SPIENA

SPIENAn Sample Point

(C2TDELAY+1)*t_c(VCLK)ns

t_f(SPICS)– 29

SPIENAn Sample point from write

to buffer

11 t_SPIENAW

(C2TDELAY+2)*t_c(VCLK)ns

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

SPISOMI

6

7

Master In Data

Must Be Valid

Figure 7-22. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

8

9

10

11

SPIENAn

Figure 7-23. SPI Master Mode Chip-Select Timing (CLOCK PHASE = 1)

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7.12.5 SPI Slave Mode I/O Timings

Table 7-38. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,

SPISIMO = input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

PARAMETER

t_c(SPC)S

MIN

40

MAX UNIT

1

Cycle time, SPICLK⁽⁵⁾

ns

t_w(SPCH)S

t_w(SPCL)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

14

2⁽⁶⁾

3⁽⁶⁾

ns

14

t_w(SPCL)S

14

t_w(SPCH)S

14

Delay time, SPISOMI valid after SPICLK high (clock

polarity = 0)

t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

t_{h(SPCL-SIMO)S}

t_{h(SPCH-SIMO)S}

t_{d(SPCL-SENAH)S}

t_{d(SPCH-SENAH)S}

t_{d(SCSL-SENAL)S}

t_rf(SOMI)+ 20

4⁽⁶⁾

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

ns

Delay time, SPISOMI valid after SPICLK low (clock

polarity = 1)

t_rf(SOMI)+ 20

Hold time, SPISOMI data valid after SPICLK high (clock

polarity =0)

2

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

2

Setup time, SPISIMO before SPICLK low (clock polarity

= 0)

4

Setup time, SPISIMO before SPICLK high (clock

polarity = 1)

4

2

Hold time, SPISIMO data valid after SPICLK low (clock

polarity = 0)

Hold time, SPISIMO data valid after S PICLK high

(clock polarity = 1)

2

Delay time, SPIENAn high after last SPICLK low (clock

polarity = 0)

1.5t_c(VCLK)

t_f(ENAn)

2.5t_c(VCLK)+t_r(ENAn)+22

t_c(VCLK)+t_f(ENAn)+27

8

9

ns

Delay time, SPIENAn high after last SPICLK high (clock

polarity = 1)

Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 7-2.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40 ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI Data Is Valid

SPISOMI

SPISIMO

6

7

SPISIMO Data

Must Be Valid

Figure 7-24. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

Figure 7-25. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

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Table 7-39. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

PARAMETER

Cycle time, SPICLK⁽⁵⁾

MIN

40

MAX

UNIT

1

t_c(SPC)S

ns

t_w(SPCH)S

t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

14

2⁽⁶⁾

3⁽⁶⁾

ns

14

Delay time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

t_{d(SOMI-SPCL)S}

t_{d(SOMI-SPCH)S}

t_{h(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

t_{su(SIMO-SPCH)S}

t_{su(SIMO-SPCL)S}

t_{v(SPCH-SIMO)S}

t_{v(SPCL-SIMO)S}

t_{d(SPCH-SENAH)S}

t_{d(SPCL-SENAH)S}

t_{d(SCSL-SENAL)S}

t_{d(SCSL-SOMI)S}

t_rf(SOMI)+ 20

4⁽⁶⁾

5⁽⁶⁾

6⁽⁶⁾

7⁽⁶⁾

8

ns

Delay time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity =0)

2

4

2

Hold time, SPISOMI data valid after SPICLK low (clock

polarity =1)

Setup time, SPISIMO before SPICLK high (clock

polarity = 0)

Setup time, SPISIMO before SPICLK low (clock polarity

= 1)

High time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

High time, SPISIMO data valid after SPICLK low (clock

polarity = 1)

Delay time, SPIENAn high after last SPICLK high

(clock polarity = 0)

1.5t_c(VCLK)2.5t_c(VCLK)+t_r(ENAn)+22

Delay time, SPIENAn high after last SPICLK low (clock

polarity = 1)

Delay time, SPIENAn low after SPICSn low (if new data

has been written to the SPI buffer)

t_c(VCLK)+t_f(ENAn)

9

t_f(ENAn)

t_c(VCLK)

ns

+27

Delay time, SOMI valid after SPICSn low (if new data

has been written to the SPI buffer)

10

2t_c(VCLK)+t_rf(SOMI)+28

(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see Table 7-2.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40 ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

Figure 7-26. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

10

SPISOMI

Slave Out Data Is Valid

Figure 7-27. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

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8 Applications, Implementation, and Layout

NOTE

Information in the following sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

8.1 TI Designs or Reference Designs

TI Designs Reference Design Library is a robust reference design library spanning analog, embedded

processor, and connectivity. Created by TI experts to help you jump start your system design, all TI

Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

Search and download designs at TIDesigns.

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9 Device and Documentation Support

9.1 Getting Started and Next Steps

To get started using a TMS570 Hercules™ ARM® Cortex®-R Microcontroller (MCU):

1. Purchase a TMS570 LaunchPad Development Kit with the LaunchPAD Quickstart Guide included.

From the LaunchPAD Quickstart Guide, the user can easily determine the correct Code Composer

Studio™ (CCS) Integrated Development Environment (IDE) and Hardware Abstraction Layer Code

Generator (HALCoGen™) GUI-based chip configuration tool for any selected Hercules MCU device(s).

2. Download the latest version of CCS IDE for Safety MCUs for the specified host platform (that is,

Windows, Linux, or MacOS) (free as long as using a LaunchPAD or a Hercules MCU Development Kit

[HDK])

3. Under Order Now, download the HALCOGEN: HAL Code Generator tool.

4. For additional tools and software descriptions, web page links, key docs, and so forth, see Tools and

Software.

The Hercules TMS570 family also has TI BoosterPack™ plug-in modules available that fit on top of a

LaunchPad development kit.

9.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of

all devices and support tools. Each commercial family member has one of three prefixes: TMX, TMP,

or TMS (for example,TMS570LS0714). These prefixes represent evolutionary stages of product

development from engineering prototypes (TMX) through fully qualified production devices/tools (TMS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications.

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

Fully-qualified production device.

TMX and TMP devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices

are to be used.

Figure 9-1 shows the numbering and symbol nomenclature for the TMS570LS0714 devices.

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Full Part #

TMS

570

LS 07

07

1

4

A

PGE

Q

Q1

R

Orderable Part #

Prefix: TM

TMS = Fully Qualified

TMP = Prototype

TMX = Samples

Core Technology:

570 = Cortex R4F

Architecture:

LS = Dual CPUs in Lockstep

(not included in orderable part #)

Flash Memory Size:

07 = 768KB

RAM MemorySize:

1 = 128KB

Peripheral Set:

Die Revision:

Blank = Initial Die

A = Die Revision A

Package Type:

PGE = 144-Pin Plastic Quad Flatpack

PZ = 100-Pin Plastic Quad Flatpack

Temperature Range:

Q = œ40^oC to 125^oC

Quality Designator:

Q1 = Automotive

Shipping Options:

R = Tape and Reel

Figure 9-1. TMS570LS0714 Device Numbering Conventions

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9.3 Tools and Software

TI offers an extensive line of tools and software for the Hercules™ Safety generation of MCUs including

development tools to evaluate the performance of the processors, generate code, develop algorithm

implementations, and fully integrate and debug software and hardware modules.

9.3.1 Kits and Evaluation Modules for Hercules TMS570 MCUs

The TMS570 Hercules™ ARM® Cortex®-R Microcontrollers (MCUs) offer a variety of hardware platforms

to help speed development. From low-cost LaunchPad™ development kits to full-featured application

developer platforms, the Hercules TMS570 MCUs provide a wide range of hardware development tools

designed to aid development and get customers to market faster.

Hercules™ TMS570LS12x LaunchPad™ Development Kit

LAUNCHXL2-TMS57012 — The Hercules TMS570LS12x LaunchPad development kit is a low-cost

evaluation platform that helps users get started quickly in evaluating and developing with the Hercules

microcontroller family, which is specifically designed for ISO 26262 and IEC 61508 functional safety

automotive applications. The LaunchPad features onboard emulation for programming and debugging;

push-buttons; LEDs and ambient light sensor; and two standard 40-pin BoosterPack expansion

connectors. Through the expansion connectors, the LaunchPad development kit can support a wide range

of BoosterPack plug-in modules for added functionality (such as displays, wireless sensors, and so forth).

LaunchPad development kits come preprogrammed with a demo code that lets the user easily learn the

key safety, data acquisition, and control features of the Hercules MCU platform. For additional software

downloads and other resources, visit the Hercules LaunchPads wiki.

9.3.2 Development Tools

Development tools includes both hardware and software development tools like integrated development

environment (IDE), compilers, and emulators.

Software

Code Composer Studio™ (CCS) Integrated Development Environment (IDE) – Code Composer Studio is

an integrated development environment (IDE) that supports TI's Microcontroller and Embedded

Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build

environment, debugger, profiler, and many other features. The intuitive IDE provides a single user

interface taking the user through each step of the application development flow. Familiar tools and

interfaces allow users to get started faster than ever before. Code Composer Studio combines the

advantages of the Eclipse software framework with advanced embedded debug capabilities from TI

resulting in a compelling feature-rich development environment for embedded developers.

CCS Uniflash Standalone Flash Tool for TI Microcontrollers (MCUs) [available free of charge] – CCS

Uniflash is a standalone tool used to program the on-chip flash memory available on TI MCUs. The CCS

Uniflash has a GUI, command line, and scripting interface.

SafeTI™ Compiler Qualification Kit – The SafeTI Compiler Qualification Kit was developed to assist

customers in qualifying their use of the TI ARM or C2000 C/C++ Compiler to functional safety standards

such as IEC 61508 SIL 3 and ISO 26262 ASIL D.

High-End Timer Integrated Development Environment (HET IDE) – The HET module available on the

Hercules MCU devices is a programmable timer coprocessor that enables sophisticated functions for real-

time control applications. The HET IDE is a windows-based application that provides an easy way to get

started developing and debugging code for the HET module.

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Hardware

Emulators

Below is a list of some emulators that can be used with the Hercules TMS570 MCU devices. For a full list

of emulators, click on the Emulators link above.

XDS100v2 – Low-cost, low-performance emulator – integrated on Hercules TMS570 MCU Development

Kits. With CCS IDE and IAR support.

XDS200 – The XDS200 is a JTAG emulator for TI embedded processors. Offering a balance of cost and

performance, XDS200 emulator fits between the ultra-low cost XDS100 and the high-performance

XDS560v2 products.

XDS560v2 – The XDS560™ family of emulators is designed to achieve high download speeds and is

ideal for larger applications.

9.3.3 Software

Software includes Real-Time Operating Systems (RTOS), peripheral drivers, libraries, example code, and

connectivity.

Hercules MCU software is designed to simplify and speed development of functional safety applications.

Hardware Abstraction Layer Code Generator (HALCoGen) for Hercules MCUs provides a graphical user

interface that allows the user to configure peripherals, interrupts, clocks, and many other MCU parameters

and can generate driver code which can be easily imported into integrated development environments like

CCS IDE, IAR Workbench, etc. The HALCoGen tool also includes several example projects.

SafeTI HALCoGen Compliance Support Package (CSP) assists customers using HALCoGen to comply

with functional safety standards by providing example documentation, reports, and unit-test capability.

The SafeTI Hercules Diagnostic Library is a software library of functions and response handlers for

various safety features of the Hercules Safety MCUs.

SafeTI Hercules Diagnostic Library CSP assists customers using the SafeTI Diagnostic Library to comply

with functional safety standards by providing documentation and reports.

Hercules™ Safety MCU Cortex^®-R4 CMSIS DSP Library. The ARM^®Cortex^®Microcontroller Software

Interface Standard (CMSIS) includes over 60 functions covering vector operations, matrix computing,

complex arithmetic, filter functions, control functions, PID controller, Fourier transforms, and many other

frequently used DSP algorithms. Most algorithms are available in floating-point and various fixed-point

formats and are optimized for the Cortex-R series processors.

Hercules™ F021 Flash API provides a software library of functions to program, erase, and verify F021 on-

chip flash memory Hercules devices.

The Hercules™ TMS570 MCUs are supported by many different Real-Time Operating Systems (RTOS)

and Connectivity/Middleware options from various providers, some of which are safety certified.

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9.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the

upper right corner, click on Alert me to register and receive a weekly digest of any product information that

has changed. For change details, review the revision history included in any revised document.

The following documents describe the processor, related internal peripherals, and other technical collateral

with respect to the TMS570LS0714 microcontroller.

Errata

TMS570LS09xx/07xx 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision 0)

(SPNZ215) describes the known exceptions to the functional specifications for the device.

TMS570LS09xx/07xx 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision A)

(SPNZ230) describes the known exceptions to the functional specifications for the device.

Technical Reference Manuals

TMS570LS09x/07x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU607)

details the integration, the environment, the functional description, and the programming models for each

peripheral and subsystem in the device.

Applications Reports

Compatibility Considerations: Migrating From TMS570LS31x/21x or TMS570LS12x/11x to

TMS570LS0914/0714 Safety Microcontrollers (SPNA204) provides a summary of the differences

between the TMS570LS0914/0714 versus the TMS570LS31x/21x and TMS570LS12x/11x series of

microcontrollers.

9.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community The TI engineer-ro-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Established to help developers get started with Embedded Processors

from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

Hercules™ Safety Microcontrollers Forum TI's Hercules™ Safety Microcontrollers Forum was created

under the E2E umbrella to foster collaboration among engineers, ask questions, share

knowledge, explore ideas, and help solve problems, specifically relating to the Hercules

Safety MCUs (that is, TMS570 and RM families).

SafeTI™ Documentation Private E2E Forum A private E2E forum to request access to the safety

analysis report; ask questions; share knowledge; and explore ideas to help resolve problems

relating to the safety analysis report. This forum is closely monitored by the TI Safety

experts. The safety analysis report itself includes detailed device-level Failure Modes,

Effects, and Diagnostics Analysis (FMEDA) for ISO 26262 and IEC 61508 functional safety

applications. The report also includes tools for estimating module and device-level failure

rates (fault insertion tests (FIT) rates).

9.6 Trademarks

BoosterPack, Hercules, LaunchPad, XDS560, E2E are trademarks of Texas Instruments.

CoreSight is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights

reserved.

ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.

All other trademarks are the property of their respective owners.

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9.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.8 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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9.9 Device Identification

9.9.1 Device Identification Code Register

The device identification code register at address 0xFFFFFFF0 identifies several aspects of the device

including the silicon version. The details of the device identification code register are shown in Table 9-1.

The device identification code register value for this device is:

•

Rev 0 = 0x8052AD05

Rev A = 0x8052AD0D

Figure 9-2. Device ID Bit Allocation Register

31

CP15

R-1

30

29

13

28

27

26

25

24

23

22

21

20

19

3

18

17

16

TECH

R-0

UNIQUE ID

R-00000000101001

15

14

12

11

10

9

8

7

6

5

4

2

1

0

1

TECH

I/O

PERIPH FLASH ECC

RAM

ECC

REVISION

VOLT PARITY

AGE

R-101

R-0

R-1

R-10

R-1

R-00000

R-1

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9-1. Device ID Bit Allocation Register Field Descriptions

BIT

FIELD

VALUE

DESCRIPTION

Indicates the presence of coprocessor 15

31

CP15

1

CP15 present

Unique device identification number

This bitfield holds a unique number for a dedicated device configuration (die).

30-17

16-13

UNIQUE ID

TECH

101001

Process technology on which the device is manufactured.

0101

F021

I/O voltage of the device.

I/O are 3.3 V

12

11

I/O VOLTAGE

PERIPH PARITY

FLASH ECC

0

1

Peripheral Parity

Parity on peripheral memories

Flash ECC

10-9

10

1

Program memory with ECC

Indicates if RAM ECC is present.

ECC implemented

8

RAM ECC

7-3

2-0

REVISION

101

Revision of the Device.

The platform family ID is always 0b101

9.9.2 Die Identification Registers

The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the

information as shown in Table 9-2.

Table 9-2. Die-ID Registers

ITEM

X Coord. on Wafer

Y Coord. on Wafer

Wafer #

NO. OF BITS

BIT LOCATION

0xFFFFFF7C[11:0]

0xFFFFFF7C[23:12]

0xFFFFFF7C[31:24]

0xFFFFFF80[23:0]

0xFFFFFF80[31:24]

12

8

Lot #

24

8

Reserved

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9.10 Module Certifications

The following communications modules have received certification of adherence to a standard.

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9.10.1 DCAN Certification

Figure 9-3. DCAN Certification

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9.10.2 LIN Certification

9.10.2.1 LIN Master Mode

Figure 9-4. LIN Certification - Master Mode

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9.10.2.2 LIN Slave Mode - Fixed Baud Rate

Figure 9-5. LIN Certification - Slave Mode - Fixed Baud Rate

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9.10.2.3 LIN Slave Mode - Adaptive Baud Rate

Figure 9-6. LIN Certification - Slave Mode - Adaptive Baud Rate

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10 Mechanical Packaging and Orderable Information

10.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and

without revision of this document. For browser-based versions of this data sheet, refer to the left-hand

navigation.

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PACKAGE MATERIALS INFORMATION

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5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

TMS5700714APGEQQ1

TMS5700714APZQQ1

PGE

PZ

LQFP

144

100

60

90

5X12

150

315 135.9 7620 25.4

315 135.9 7620 20.3

17.8 17.55

15.4 15.4

6 x 15

Pack Materials-Page 1

MECHANICAL DATA

MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

M

0,08

0,17

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/C 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMS570LS0714
厂家：	TEXAS INSTRUMENTS
描述：	16/32 位 RISC 闪存 MCU，Arm Cortex-R4F，通过 Q-100 车规认证闪存
文件：	总163页 (文件大小：8884K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS570LS0714 [TI]

相关型号：

TMS570LS0714-S

TMS570LS0914

TMS570LS10106

TMS570LS10106BSPGEQR

TMS570LS10116

TMS570LS10206

TMS570LS10216

TMS570LS1114

TMS570LS1115

TMS570LS1224

TMS570LS1225

TMS570LS1227