TMS570LS3137-EP_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

TMS570LS3137-EP 16 位和 32 位 RISC 闪存微控制器

1 器件概述

1.1 特性

1

• 用于安全关键型应用的高性能微控制器

– 运行在锁步中的双中央处理单元 (CPU)

– 闪存和 RAM 接口上的 ECC

– 内置 CPU 和片上 RAM 自检

– 带有错误引脚的错误信令模块

– 电压和时钟监视

• 跟踪和校准功能

– 嵌入式跟踪宏单元 (ETM-R4)

– 数据修改模块 (DMM)

– RAM 跟踪端口 (RTP)

– 参数覆盖模块 (POM)

• 多通信接口

• ARM^®Cortex™ – R4F 32 位 RISC CPU

– 带有 8 级管线的高效 1.66DMIPS/MHz

– 支持单精度和双精度的浮点运算单元 (FPU)

– 12 区域内存保护单元

– 10/100Mbps 以太网 MAC (EMAC)

•

符合 IEEE 802.3 标准（只适用于 3.3V I/O）

支持媒介独立接口 (MII)，精简媒介独立接口

(RMII) 和管理数据输入输出 (MDIO)

– 带有 2 个通道的 FlexRay 控制器

– 带有第三方支持的开放式架构

• 运行条件

•

带有奇偶检验保护的 8KB 消息 RAM

专用传输单元 (FTU)

– 高达180MHz 系统时钟

– 3 个 CAN 控制器 (DCAN)

– 内核电源电压 (VCC)：标称值 1.2V

– I/O 电源电压 (VCCOI)：标称值 3.3V

– ADC 电源电压 (V_CCAD): 3.0 至 5.25V

•

64 个邮箱，每个邮箱均具有奇偶校验保护

与 CAN 协议 2.0B 版兼容

– 本地互连网络 (LIN) 接口控制器

– 采用 IP 模块门级设计，工作温度范围为 -40°C

至 125°C，仅包含闪存，MibADC 定时

器，nPORRST、N2HET 和 FlexRay

•

与 LIN 协议版本 2.1 兼容

可被配置为第二个 SCI

• 集成存储器

– 标准串行通信接口 (SCI)

– 内部集成电路 (I²C)

– 3 个多通道经缓冲串行外设接口 (MibSPI)

– 支持 ECC 的 3MB 程序闪存

– 256KB 且支持 ECC 的 RAM

– 支持 ECC、用于仿真 EERPOM 的 64KB 闪存

• 16 位外部存储器接口

•

128 个字，每个字具有奇偶校验保护

– 2 个标准串行外设接口 (SPI)

• 2 个高端定时器模块 (N2HET)

– N2HET1：32 个可编程通道

• 通用平台架构

– 系列间一致的存储器映射

– 实时中断定时器 (RTI) 操作系统 (OS) 定时器

– 96 通道矢量中断模块 (VIM)

– 2 通道循环冗余校验器 (CRC)

• 直接内存访问 (DMA) 控制器

– 16 通道和 32 控制数据包

– N2HET2：18 个可编程通道

– 160 个字指令 RAM，每个都带有奇偶校验保护

– 每个 N2HET 包括硬件角发生器

– 针对每个 N2HET (HTU) 的具有 MPU 的专用传

输单元

– 针对控制数据包 RAM 的奇偶校验保护

– 由专用 MPU 保护的 DMA 访问

• 带有内置跳周检测器的调频锁相环 (FMPLL)

• 独立的非调制 PLL

• IEEE 1149.1 JTAG，边界扫描和 ARM CoreSight™

组件

• 2 个 10 或 12 位多通道经缓冲 ADC 模块

– ADC1：24 个通道

– ADC2：与 ADC1 共用的 16 个通道

– 64 个结果缓冲器，每个缓冲器具有奇偶校验保护

• 16 个能够生成中断的通用输入/输出引脚 (GPIO)

• 封装

• JTAG 安全模块

– 337 球状引脚栅格阵列 (SnPb)(GWT)

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SPNS230

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1.2 应用范围

•

刹车系统（防抱死制动系统和电子稳定性控制）

•

支持国防、航天和医疗应用

–

受控基线

电动助力转向

同一组装和测试场所

同一制造场所

混合动力汽车 (HEV) 和电动汽车 (EV) 反向器系统

电池管理系统

主动驾驶员辅助系统

航天和航空电子设备

轨道交通

支持温度范围 –55°C 至 125°C

延长的产品生命周期

延长的产品变更通知

产品可追溯性

越野车

1.3 说明

TMS570LS3137-EP 器件是一款用于安全系统的高性能系列微控制器。此安全架构包括：

•

以锁步模式运行的双核 CPU

CPU 和内存内置自检 (BIST) 逻辑

闪存和数据 SRAM 上的 ECC

外设存储器的奇偶校验

外设 I/O 上的回路功能

TMS570LS3137-EP 器件集成了 ARM Cortex-R4F 浮点 CPU，此 CPU 可提供一个高效的 1.66

DMIPS/MHz，并且具有能够以高达 180 MHz 运行的配置，从而提供高达 298 DMIPS。此器件支持字不变

大端序 [BE32] 格式。

TMS570LS3137-EP 器件具有 3MB 的集成闪存以及 256KB 的数据 RAM，这些闪存和 RAM 支持单位错误

校正和双位错误检测。这个器件上的闪存存储器是一个由 64 位宽数据总线接口实现的非易失性、电可擦除

并且可编程的存储器。为了实现所有读取、编程和擦除操作，此闪存运行在一个 3.3V 电源输入上（与 I/O

电源一样的电平）。当处于管线模式中时，闪存可在高达 180MHz 的系统时钟频率下运行。在字节、半

字、字和双字模式中，SRAM 支持单循环读取和写入访问。

TMS570LS3137-EP 器件特有针对基于实时控制应用的外设，其中包括 2 个下一代高端定时器 (N2HET) 时

序协处理器和 2 个支持多达 24 个输入的 12 位模数转换器 (ADC) 。

N2HET1 是一款高级智能定时器，此定时器能够为实时应用提供精密的计时功能。该定时器为软件控制

型，采用一个精简指令集，并具有一个专用的定时器微级机和一个连接的 I/O 端口。 N2HET 可被用于脉宽

调制输出，捕捉或比较输入，GPIO。 N2HET 特别适合于要求多个传感器信息并且用复杂和准确时间脉冲来

驱动致动器的应用。一个高端定时器传输单元 (HTU) 能够执行 DMA 类型处理来与主存储器之间传输

N2HET 数据。一个内存保护单元 (MPU) 被内置于 HTU 内。

此器件具有 2 个 12 位分辨率 MibADC，每个 MibADC 具有 24 个通道和受 64 字奇偶校验保护的缓冲器

RAM。 MibADC 通道可被独立转换或者可针对顺序转换序列由软件成组。 16 个通道可在两个 MibADC 间

共用。有三个独立的组。当被触发或者针对连续转换模式进行配置后，每个序列可被转换一次。

此器件有多个通信接口：3 个 MibSPI，，1 个 LIN，1 个SCI，3 个 DACN，1 个 I²C。 SPI 为相似移位寄存

器类型器件之间串行高速通信的提供了一个便捷方法。 LIN 支持本地互联标准 2.0 并可被用作一个使用标准

不归零码 (NRZ) 格式的全双工模式 UART。

DCAN 支持 CAN 2.0（A 和 B）协议标准并使用一个串行、多主控通信协议，此协议用高达 1Mbps 的稳健

耐用通信速率有效支持分布式实时控制。 DCAN 非常适合于工作于嘈杂和恶劣环境中的系统（例如，汽车

网络互连和工业领域），此类系统需要可靠的串行通信或多路复用布线。

I2C 模块是一个多主控通信模块，此模块通过 I²C 串行总线在微控制器和一个 I²C 兼容器件之间提供一个接

口。此 I²C 支持 100Kbps 和 400Kbps 的速度。

此调频锁相环 (FMPLL) 时钟模块被用来将外部频率基准与一个内部使用的更高频率相乘。这个器件上有两

个 FMPLL 模块。当被启用时，这些模块提供 7 个可能的时钟源中的两个到全局时钟模块 (GCM)。此

GCM 管理可用时钟源与器件时钟域间的映射。

2

器件概述

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

此器件还有一个外部时钟前置分频器 (ECP) 模块，当被启用时，此模块在 ECLK 引脚/焊球上输出一个连续

外部时钟。 ECLK 频率是一个外设接口时钟 (VCLK) 频率的用户可编程比例。这个可被外部监视的低频输出

作为此器件运行频率的指示器。

直接内存访问 (DMA) 控制器有 16 个通道，32 个控制数据包和针对其内存的奇偶校验保护。在 DMA 中内

置了一个 MPU 来将 DMA 限制在存储器的指定区域，并且保护存储器系统的剩余部分不受 DMA 故障的影

响。

错误信令模块 (ESM) 监控所有器件错误并在检测到一个故障时确定是生成一个中断还是触发一个外部

ERROR 引脚。可从外部监视此 ERROR 引脚，将其作为一个微控制器内故障条件的指示器。

外部存储器接口 (EMIF) 提供芯片外扩展功能，此功能可实现与同步 DRAM (SDRAM) 器件、异步存储器、

外设或现场可编程门阵列 (FPGA) 器件的对接。

执行几个接口来提高应用代码的调试能力。除了内置的 ARM Cortex-R4F CoreSight 调试特性，一个外部跟

踪宏单元 (ETM) 提供程序执行的指令和数据跟踪。为了实现仪器测量的目的，执行了一个 RAM 跟踪端口

模块 (RTP) 来支持由 CPU 或者任何其它主控所访问的 RAM 和外设的高速跟踪。一个数据修改模块

(DMM) 提供向器件内存写入外部数据的功能。 RTP 和 DMM 对于应用代码的程序执行时间没有影响或者只

有很小的影响。一个参数覆盖模块 (POM) 可将闪存访问重新路由至内部存储器或 EMIF。这个重新路由可

对照生产代码对参数和表格进行动态校准，而无需重建代码以明确访问 RAM 或停止处理器来重新编辑数据

闪存。

借助集成的安全特性和通信与控制外设的广泛选择，器件是针对具有安全关键要求的高性能实时控制应用的

理想解决方案。

表 1-1. 器件信息⁽¹⁾

订货编号

TMS5703137CGWTQEP

TMS5703137CGWTMEP

封装

T_A

-40°C 至 105°C

-55°C 至 125°C

NFBGA (337)

(1) 更多信息请参见节 9，机械封装和可订购产品信息。

器件概述

3

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1.4 功能方框图

Color Legend for Power Domains

RAM

Core/RAM

Core

always on

# 1

# 2

# 3

# 4

# 5

# 1

# 2

64K

3M

256K

64K RAM

with

Flash

with

ECC

# 3

64K

ECC

64K

ETM-R4

RTP

DMA

POM

DMM

HTU1

FTU

HTU2

EMAC

Dual Cortex-R4F

CPUs in Lockstep

Switched Central Resource Switched Central Resource Switched Central Resource

Main Cross Bar: Arbitration and Prioritization Control

64 KB Flash

Peripheral Central Resource Bridge

SYS

CRC Switched Central Resource

for EEPROM

Emulation

with ECC

nPORRST

nRST

ECLK

IOMM

EMAC Slaves

nERROR

ESM

EMIF_nWAIT

EMIF_CLK

MDCLK

MDIO

PMM

VIM

CAN1_RX

CAN1_TX

CAN2_RX

CAN2_TX

CAN3_RX

CAN3_TX

MDIO

DCAN1

MII_RXD[3:0]

MII_RXER

MII_TXD[3:0]

MII_TXEN

MII_TXCLK

MII_RXCLK

EMIF_CKE

EMIF_nCS[4:2]

EMIF_nCS[0]

EMIF_ADDR[21:0]

EMIF_BA[1:0]

EMIF_DATA[15:0]

EMIF_nDQM[1:0]

EMIF_nOE

DCAN2

DCAN3

MII

MIBSPI1_CLK

EMIF

MIBSPI1_SIMO[1:0]

MIBSPI1_SOMI[1:0]

MII_CRS

MII_RXDV

MII_COL

MibSPI1

SPI2

RTI

MIBSPI1_nCS[5:0]

MIBSPI1_nENA

EMIF_nWE

EMIF_nRAS

EMIF_nCAS

EMIF_nRW

SPI2_CLK

SPI2_SIMO

SPI2_SOMI

DCC1

SPI2_nCS[1:0]

SPI2_nENA

MIBSPI3_CLK

MIBSPI3_SIMO

MIBSPI3_SOMI

MIBSPI3_nCS[5:0]

MIBSPI3_nENA

MibSPI3

SPI4

DCC2

SPI4_CLK

SPI4_SIMO

SPI4_SOMI

SPI4_nCS0

SPI4_nENA

FlexRay

MibADC1

MibADC2

N2HET1 N2HET2 GIO

I2C

MIBSPI5_SIMO[3:0]

MIBSPI5_SOMI[3:0]

MIBSPI5_nCS[3:0]

MIBSPI5_nENA

MibSPI5

LIN_RX

LIN_TX

LIN

SCI

SCI_RX

SCI_TX

图 1-1. 功能方框图

4

器件概述

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

内容

1

器件概述.................................................... 1

6.11 Tightly-Coupled RAM Interface Module............. 67

6.12 Parity Protection for Peripheral RAMs .............. 67

6.13 On-Chip SRAM Initialization and Testing ........... 69

6.14 External Memory Interface (EMIF) .................. 71

6.15 Vectored Interrupt Manager ......................... 78

6.16 DMA Controller ...................................... 81

6.17 Real Time Interrupt Module ......................... 83

6.18 Error Signaling Module.............................. 85

6.19 Reset / Abort / Error Sources ....................... 89

6.20 Digital Windowed Watchdog ........................ 91

6.21 Debug Subsystem................................... 92

Peripheral Information............................... 103

7.1 Peripheral Legend ................................. 103

1.1 特性 ................................................... 1

1.2 应用范围 .............................................. 2

1.3 说明 ................................................... 2

1.4 功能方框图............................................ 4

修订历史记录............................................... 6

Device Comparison Table.............................. 7

3.1 Device Comparison................................... 7

Pin Configuration and Functions..................... 8

4.1 Pin Diagrams ......................................... 8

Specifications ........................................... 29

5.1 Absolute Maximum Ratings......................... 29

5.2 ESD Ratings ........................................ 29

5.3 Power-On Hours (POH)............................. 29

5.4 Recommended Operating Conditions............... 29

5.5 Power Consumption................................. 31

5.6 Thermal Data........................................ 31

5.7 Switching Characteristics ........................... 32

5.8 Wait States Required ............................... 32

5.9 I/O Electrical Characteristics ........................ 33

5.10 Output Buffer Drive Strengths ...................... 33

5.11 Input Timings........................................ 34

5.12 Output Timings...................................... 35

5.13 Low-EMI Output Buffers ............................ 37

2

3

4

5

7

7.2

Multi-Buffered 12bit Analog-to-Digital Converter .. 103

7.3 General-Purpose Input/Output..................... 114

7.4 Enhanced High-End Timer (N2HET) .............. 115

7.5 FlexRay Interface .................................. 120

7.6 Controller Area Network (DCAN) .................. 122

7.7

Local Interconnect Network Interface (LIN)........ 123

Serial Communication Interface (SCI) ............. 124

7.8

7.9 Inter-Integrated Circuit (I2C) ....................... 125

7.10 Multi-Buffered / Standard Serial Peripheral

Interface............................................ 128

7.11 Ethernet Media Access Controller ................. 141

8

Device and Documentation Support.............. 145

6

System Information and Electrical

Specifications ........................................... 38

8.1

Device and Development-Support Tool

Nomenclature ...................................... 145

6.1 Device Power Domains ............................. 38

6.2 Voltage Monitor Characteristics ..................... 39

8.2 Documentation Support............................ 147

8.3 商标 ................................................ 147

8.4 静电放电警告....................................... 147

8.5 术语表.............................................. 147

8.6 Device Identification................................ 148

8.7 Module Certifications............................... 150

6.3

Power Sequencing and Power On Reset ........... 40

6.4 Warm Reset (nRST)................................. 42

6.5 ARM^©Cortex™-R4F CPU Information.............. 43

6.6 Clocks ............................................... 46

6.7 Clock Monitoring .................................... 54

6.8 Glitch Filters......................................... 56

6.9 Device Memory Map ................................ 57

6.10 Flash Memory ....................................... 64

9

Mechanical, Packaging, and Orderable

Information............................................. 153

9.1 Packaging Information ............................. 153

内容

5

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

2 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (October 2013) to Revision C

Page

•

已将格式更新为新标准版本.......................................................................................................... 1

扩大了支持的温度范围 ............................................................................................................... 2

Updated T_Jminimum and removed T_A.......................................................................................... 29

Changed Lifetime POH from 20k to 100k. ...................................................................................... 29

Updated T_Jminimum ............................................................................................................... 30

Updated test condition temperatures for ........................................................................................ 31

Added conditions ................................................................................................................... 34

Added conditions ................................................................................................................... 36

Added test conditions .............................................................................................................. 41

Added conditions ................................................................................................................... 42

Added conditions ................................................................................................................... 47

Added test conditions .............................................................................................................. 50

Added test conditions .............................................................................................................. 54

Updated Glitch Filter Timing Specifications table. ............................................................................. 56

Updated the minimum timing for ETMDATA parameters to show new orderable part number .......................... 97

Added conditions ................................................................................................................... 98

Added conditions .................................................................................................................. 100

Added conditions to 表 7-8 ...................................................................................................... 108

Added conditions .................................................................................................................. 109

Added conditions .................................................................................................................. 110

Added conditions for 表 7-11 .................................................................................................... 115

Added conditions for 表 7-12 .................................................................................................... 116

Added conditions for t_pw.......................................................................................................... 120

Added conditions for 表 7-17 .................................................................................................... 121

Added conditions for 表 7-24 .................................................................................................... 132

Added conditions to 表 7-25 ..................................................................................................... 135

Added conditions to 表 7-26 ..................................................................................................... 137

Added conditions to 表 7-27 ..................................................................................................... 139

Added conditions to transition time ............................................................................................. 144

Changes from Revision A (October 2013) to Revision B

Page

•

Changed Operation Life Derating Chart ......................................................................................... 30

6

修订历史记录

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

3 Device Comparison Table

3.1 Device Comparison

To compare the TMS570LS3137-EP with other devices, see Compare on the product folder.

Device Comparison Table

7

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4 Pin Configuration and Functions

4.1 Pin Diagrams

337-Ball Grid Array

GWT BGA Package

Top View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

AD1IN[15] AD1IN[22]

AD1IN[11]

/

AD2IN[11]

N2HET1 MIBSPI5 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1

SIMO[0]

DMM_

DATA[0]

AD1IN

[06]

19

18

17

16

15

14

13

12

11

VSS

TMS

CAN3RX AD1EVT

/

AD2IN[15] AD2IN[06]

VSSAD

VSSAD 19

[10]

NCS[0]

SIMO

NENA

CLK

[28]

AD1IN[08] AD1IN[14] AD1IN[13]

N2HET1 MIBSPI1 MIBSPI1 MIBSPI5 MIBSPI5 N2HET1

SOMI[0]

DMM_

DATA[1]

AD1IN

[04]

AD1IN

[02]

VSS

TDI

TCK

TDO

nTRST

CAN3TX

NC

/

AD2IN[08] AD2IN[14] AD2IN[13]

/

VSSAD 18

AD1IN[09]

[08]

CLK

SOMI

NENA

[0]

AD1IN[10]

/

AD2IN[10]

EMIF_

ADDR[21]

EMIF_

nWE

MIBSPI5

SOMI[1]

DMM_

CLK

MIBSPI5 MIBSPI5 N2HET1

[31]

EMIF_

nCS[3]

EMIF_

nCS[2]

EMIF_

nCS[4]

EMIF_

nCS[0]

AD1IN

[05]

AD1IN

[03]

AD1IN

[01]

RST

NC

/

AD2IN[09]

17

SIMO[3] SIMO[2]

AD1IN[23] AD1IN[12] AD1IN[19]

FRAY EMIF_

TXEN1 ADDR[20]

EMIF_

BA[1]

MIBSPI5

SIMO[1]

DMM_

NENA

MIBSPI5 MIBSPI5

SOMI[3] SOMI[2]

DMM_

SYNC

RTCK

NC

/

AD2IN[07] AD2IN[12] AD2IN[03]

/

ADREFLO VSSAD 16

ADREFHI VCCAD 15

ETM

DATA[16] /

EMIF_

ETM

DATA[17] /

EMIF_

ETM

DATA[18] /

EMIF_

ETM

DATA[19] /

EMIF_

AD1IN[21] AD1IN[20]

FRAY

RX1

FRAY

TX1

EMIF_ ETM

ADDR[19] ADDR[18] DATA[06] DATA[05] DATA[04] DATA[03] DATA[02]

EMIF_

ETM

NC

/

AD2IN[05] AD2IN[04]

/

DATA[0]

DATA[1]

DATA[2]

DATA[3]

AD1IN[18]

/

AD2IN[02]

N2HET1

[26]

EMIF_ ETM

ADDR[17] ADDR[16] DATA[07]

EMIF_

AD1IN

[07]

AD1IN

[0]

nERROR

VCCIO

VCC

VCCIO

VCC

VCCIO

VCCPLL

VCC

NC

14

13

12

11

AD1IN[17] AD1IN[16]

/

AD2IN[01] AD2IN[0]

ETM

DATA[12] /

NC

N2HET1 N2HET1

[17]

EMIF_

ADDR[15]

EMIF_BA[0]

ETM

DATA[01]

/

NC

[19]

ETM

DATA[13] /

NC

N2HET1

[04]

EMIF_

ADDR[14]

EMIF_nOE

ETM

DATA[0]

MIBSPI5

NCS[3]

ECLK

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

NC

ETM

ETME

TRACE

CTL

N2HET1 N2HET1

[14] [30]

EMIF_

ADDR[13]

DATA[14] /

EMIF_

nDQM[1]

NC

ETM

TRACE

CLKOUT

EMIF_

ADDR[12]

MIBSPI3

NCS[0]

DATA[15] /

EMIF_

nDQM[0]

10 CAN1TX CAN1RX

NC

GIOB[3] 10

ETM

DATA[08] /

EMIF_

ETM

TRACE

CLKIN

N2HET1

[27]

FRAY EMIF_

TXEN2 ADDR[11]

MIBSPI3 MIBSPI3

NENA

9

8

7

6

5

4

3

2

1

VCC

VCCIO

NC

9

8

7

6

5

4

3

2

1

CLK

ADDR[5]

ETM

DATA[09] /

EMIF_

ETM

FRAY

RX2

FRAY

TX2

EMIF_

ADDR[10]

MIBSPI3 MIBSPI3

SIMO

DATA[31] /

EMIF_

DATA[15]

VCCP

VCCIO

NC

SOMI

ADDR[4]

ETM

DATA[10] /

EMIF_

ETM

EMIF_

ADDR[9]

N2HET1

[09]

DATA[30] /

EMIF_

DATA[14]

nPORRST

LINRX

LINTX

NC

ADDR[3]

ETM

MIBSPI5

NCS[1]

EMIF_

ADDR[8]

N2HET1 MIBSPI5

[05] NCS[2]

DATA[11] /

EMIF_

ADDR[2]

DATA[29] /

EMIF_

DATA[13]

GIOA[4]

NC

VCCIO

FLTP2

VCCIO

FLTP1

VCC

VCCIO

NC

ETM

DATA[20] /

EMIF_

ETM

DATA[21] /

EMIF_

ETM

DATA[22] /

EMIF_

ETM

DATA[23] /

EMIF_

ETM

DATA[24] /

EMIF_

ETM

DATA[25] /

EMIF_

ETM

EMIF_ EMIF_

ADDR[7] ADDR[1]

MIBSPI3 N2HET1

[02]

DATA[26] /

EMIF_

DATA[10]

DATA[27] /

EMIF_

DATA[11]

DATA[28] /

EMIF_

DATA[12]

GIOA[0] GIOA[5]

N2HET1 N2HET1

NC

NCS[1]

DATA[4]

DATA[5]

DATA[6]

DATA[7]

DATA[8]

DATA[9]

EMIF_ EMIF_

ADDR[6] ADDR[0]

N2HET1 N2HET1

[21]

EMIF_

nCAS

NC

[16]

[12]

[23]

N2HET1 N2HET1 MIBSPI3

NCS[3]

SPI2

NENA

N2HET1 MIBSPI1 MIBSPI1

[11] NCS[1] NCS[2]

MIBSPI1

NCS[3]

EMIF_

CLK

EMIF_

CKE

N2HET1

[25]

SPI2

NCS[0]

EMIF_

nWAIT

EMIF_

nRAS

N2HET1

[06]

GIOA[6]

NC

[29]

[22]

MIBSPI3

NCS[2]

SPI2

SOMI

KELVIN_

GND

N2HET1 N2HET1 MIBSPI1

[20]

N2HET1

[01]

VSS

GIOA[1]

SPI2 CLK GIOB[2] GIOB[5] CAN2TX GIOB[6] GIOB[1]

GIOB[0]

TEST

VSS

[13]

NCS[0]

SPI2

SIMO

N2HET1

[18]

N2HET1 N2HET1

[24]

N2HET1 N2HET1

[07]

VSS

A

VSS

B

GIOA[2]

C

GIOA[3] GIOB[7] GIOB[4] CAN2RX

OSCIN

K

OSCOUT GIOA[7]

NC

R

VSS

V

VSS

W

[15]

[03]

D

E

F

G

H

J

L

M

N

P

T

U

NOTE: Balls can have multiplexed functions. Only the default function is depicted in above diagram, except for the EMIF

signals that are multiplexed with ETM signals.

8

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1 Pin Attributes

4.1.1.1 identifies the external signal names, the associated pin/ball numbers along with the mechanical

package designator, the pin/ball type (Input, Output, IO, Power or Ground), whether the pin/ball has any

internal pullup/pulldown, whether the pin/ball can be configured as a GPIO, and a functional pin/ball

description. The first signal name listed is the primary function for that terminal. The signal name in Bold is

the function being described. Refer to the TMS570LS31X/21X Technical Reference Manual (SPNU499)

for information on how to select between different multiplexed functions.

NOTE

All I/O signals except nRST are configured as inputs while nPORRST is low and immediately

after nPORRST goes High.

All output-only signals are configured as inputs while nPORRST is low, and are

configured as outputs immediately after nPORRST goes High.

While nPORRST is low, the input buffers are disabled, and the output buffers are

tri-stated.

In the Pin Functions table below, the "Default Pull State" is the state of the pullup or

pulldown while nPORRST is low and immediately after nPORRST goes High. The

default pull direction may change when software configures the pin for an alternate

function. The "Pull Type" is the type of pull asserted when the signal name in bold

is enabled for the given pin.

Pin Configuration and Functions

9

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1 GWT Package

4.1.1.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

Table 4-1. GWT Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

ADREFHI⁽¹⁾

V15

Input

-

None

ADC high reference

supply

ADREFLO⁽¹⁾

VCCAD⁽¹⁾

VSSAD

V16

W15

V19

Input

Power

Ground

ADC low reference supply

Operating supply for ADC

ADC supply power

None

W16

W18

W19

N19

AD1EVT

I/O

Pull Down Programmable, ADC1 event trigger input,

20uA or GPIO

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS

V10

Pull Up

Programmable, ADC2 event trigger input,

20uA

or GPIO

AD1IN[0]

W14

V17

V18

T17

U18

R17

T19

V14

P18

W17

U17

U19

T16

T18

R18

P19

V13

U13

U14

U16

U15

T15

R19

R16

Input

-

None

ADC1 analog input

AD1IN[1]

AD1IN[2]

AD1IN[3]

AD1IN[4]

AD1IN[5]

AD1IN[6]

AD1IN[7]

AD1IN[8] / AD2IN[8]

AD1IN[9] / AD2IN[9]

AD1IN[10] / AD2IN[10]

AD1IN[11] / AD2IN[11]

AD1IN[12] / AD2IN[12]

AD1IN[13] / AD2IN[13]

AD1IN[14] / AD2IN[14]

AD1IN[15] / AD2IN[15]

AD1IN[16] / AD2IN[0]

AD1IN[17] / AD2IN[1]

AD1IN[18] / AD2IN[2]

AD1IN[19] / AD2IN[3]

AD1IN[20] / AD2IN[4]

AD1IN[21] / AD2IN[5]

AD1IN[22] / AD2IN[6]

AD1IN[23] / AD2IN[7]

Input

-

None

ADC1/ADC2 shared

analog inputs

(1) The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.

10

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.2 Enhanced High-End Timer Modules (N2HET)

Table 4-2. GWT Enhanced High-End Timer Modules (N2HET)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

N2HET1[0]/SPI4CLK

K18

V2

I/O

Pull Down Programmable,

20uA

N2HET1

capture

compare, or GIO.

time

or

input

output

N2HET1[1]/SPI4NENA/N2HET2[8]

N2HET1[2]/SPI4SIMO[0]

N2HET1[3]/SPI4NCS[0]/N2HET2[10]

N2HET1[4]

W5

U1

Each terminal has

suppression filter that

ignores

smaller

programmable duration.

a

B12

V6

input

than

pulses

a

N2HET1[5]/SPI4SOMI[0]/N2HET2[12]

N2HET1[6]/SCIRX

N2HET1[7]/N2HET2[14]

N2HET1[8]/MIBSPI1SIMO[1]

N2HET1[9]/N2HET2[16]

N2HET1[10]

W3

T1

E18

V7

D19

E3

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]

N2HET1[12]

B4

N2HET1[13]/SCITX

N2HET1[14]

N2

A11

N1

N2HET1[15]/MIBSPI1NCS[4]

N2HET1[16]

A4

N2HET1[17]

A13

J1

N2HET1[18]

N2HET1[19]

B13

P2

N2HET1[20]

N2HET1[21]

H4

N2HET1[22]

B3

N2HET1[23]

J4

N2HET1[24]/MIBSPI1NCS[5]

N2HET1[25]

P1

M3

A14

A9

N2HET1[26]/

N2HET1[27]

N2HET1[28]/

K19

A3

N2HET1[29]

N2HET1[30]

B11

J17

B5

N2HET1[31]

GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS

I/O

Pull Down Programmable,

20uA

Pin Configuration and Functions

11

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Table 4-2. GWT Enhanced High-End Timer Modules (N2HET) (continued)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

GIOA[2]/N2HET2[0]

C1

D4

E1

I/O

Pull Down Programmable,

20uA

N2HET2

capture

compare, or GIO.

time

or

input

output

EMIF_ADDR[0]/N2HET2[1]

GIOA[3]/N2HET2[2]

Each terminal has

suppression filter that

a

EMIF_ADDR[1]/N2HET2[3]

D5

H3

D16

M1

N17

V2

GIOA[6]/N2HET2[4]

ignores

smaller

input

than

pulses

a

EMIF_BA[1]/N2HET2[5]

programmable duration.

GIOA[7]/N2HET2[6]

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

N2HET1[1]/SPI4NENA/N2HET2[8]

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

N2HET1[3]/SPI4NCS[0]/N2HET2[10]

EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11]

N2HET1[5]/SPI4SOMI[0]/N2HET2[12]

EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13]

N2HET1[7]/N2HET2[14]

K17

U1

C4

V6

C5

T1

EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15]

N2HET1[9]/N2HET2[16]

C6

V7

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS

E3

V10

I/O

Pull Up

Programmable,

20uA

12

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.3 General-Purpose Input / Output (GPIO)

Table 4-3. GWT General-Purpose Input / Output (GPIO)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

GIOA[0]

A5

C2

C1

E1

I/O

Pull Down Programmable, General-purpose I/O.

20uA

All GPIO terminals are

capable of generating

interrupts to the CPU on

rising / falling / both

edges.

GIOA[1]

GIOA[2]/N2HET2[0]

GIOA[3]/N2HET2[2]

GIOA[4]

A6

GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS

B5

GIOA[6]/N2HET2[4]

H3

M1

M2

K2

GIOA[7]/N2HET2[6]

GIOB[0]

GIOB[1]

GIOB[2]

F2

GIOB[3]

W10

G1

G2

J2

GIOB[4]

GIOB[5]

GIOB[6]

GIOB[7]

F1

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS

V10

Pull Up

Fixed 20uA pull GIOB[2] is input only on

down

this terminal. When

GIOB[2] function is

selected, the pull is a fixed

pull down

4.1.1.1.4 FlexRay Interface Controller (FlexRay)

Table 4-4. FlexRay Interface Controller (FlexRay)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

FRAYRX1

FRAYTX1

A15

B15

B16

A8

Input

Output

Input

Pull Up

None

Fixed, 100uA

-

FlexRay data receive

(channel 1)

FlexRay data transmit

(channel 1)

FRAYTXEN1

FRAYRX2

FRAYTX2

FlexRay transmit enable

(channel 1)

Pull Up

None

Fixed, 100uA

-

FlexRay data receive

(channel 2)

B8

Output

FlexRay data transmit

(channel 2)

FRAYTXEN2

B9

FlexRay transmit enable

(channel 2)

Pin Configuration and Functions

13

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.5 Controller Area Network Controllers (DCAN)

Table 4-5. GWT Controller Area Network Controllers (DCAN)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

CAN1RX

CAN1TX

CAN2RX

CAN2TX

CAN3RX

CAN3TX

B10

A10

H1

I/O

Pull Up

Programmable, CAN1 receive, or GPIO

20uA

CAN1 transmit, or GPIO

CAN2 receive, or GPIO

CAN2 transmit, or GPIO

CAN3 receive, or GPIO

CAN3 transmit, or GPIO

H2

M19

M18

4.1.1.1.6 Local Interconnect Network Interface Module (LIN)

Table 4-6. GWT Local Interconnect Network Interface Module (LIN)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

LINRX

LINTX

A7

B7

I/O

Pull Up

Programmable, LIN receive, or GPIO

20uA

LIN transmit, or GPIO

4.1.1.1.7 Standard Serial Communication Interface (SCI)

Table 4-7. GWT Standard Serial Communication Interface (SCI)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

N2HET1[6]/SCIRX

N2HET1[13]/SCITX

W3

N2

I/O

Pull Down Programmable, SCI receive, or GPIO

20uA

SCI transmit, or GPIO

14

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.8 Inter-Integrated Circuit Interface Module (I2C)

Table 4-8. GWT Inter-Integrated Circuit Interface Module (I2C)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]

MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]

B2

C3

I/O

Pull Up

Programmable, I2C serial data, or GPIO

20uA

I2C serial clock, or GPIO

4.1.1.1.9 Standard Serial Peripheral Interface (SPI)

Table 4-9. GWT Standard Serial Peripheral Interface (SPI)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

SPI2CLK

E2

N3

D3

D1

I/O

Pull Up

Programmable, SPI2 clock, or GPIO

20uA

SPI2NCS[0]

SPI2 chip select, or GPIO

SPI2NENA/SPI2NCS[1]

SPI2SIMO[0]

SPI2 chip select, or GPIO

SPI2 enable, or GPIO

SPI2 slave-input master-

output, or GPIO

SPI2SOMI[0]

D2

SPI2 slave-output master-

input, or GPIO

N2HET1[0]/SPI4CLK

K18

U1

I/O

Pull Down Programmable, SPI4 clock, or GPIO

20uA

N2HET1[3]/SPI4NCS[0]/N2HET2[10]

N2HET1[1]/SPI4NENA/N2HET2[8]

N2HET1[2]/SPI4SIMO[0]

SPI4 chip select, or GPIO

V2

SPI4 enable, or GPIO

W5

SPI4 slave-input master-

output, or GPIO

N2HET1[5]/SPI4SOMI[0]/N2HET2[12]

V6

SPI4 slave-output master-

input, or GPIO

Pin Configuration and Functions

15

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.10 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Table 4-10. GWT Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

MIBSPI1CLK

F18

R2

I/O

Pull Up

Programmable, MibSPI1 clock, or GPIO

20uA

MIBSPI1NCS[0]/MIBSPI1SOMI[1]

MIBSPI1NCS[1]/N2HET1[17]

MIBSPI1NCS[2]/N2HET1[19]

MIBSPI1NCS[3]/N2HET1[21]

N2HET1[15]/MIBSPI1NCS[4]

N2HET1[24]/MIBSPI1NCS[5]

MIBSPI1NENA/N2HET1[23]

MIBSPI1SIMO[0]

MibSPI1 chip select, or

GPIO

F3

G3

J3

N1

Pull Down Programmable, MibSPI1 chip select, or

20uA GPIO

P1

G19

F19

Pull Up

Programmable, MibSPI1 enable, or GPIO

20uA

MibSPI1 slave-in master-

out, or GPIO

N2HET1[8]/MIBSPI1SIMO[1]

E18

Pull Down Programmable, MibSPI1 slave-in master-

20uA out, or GPIO

MIBSPI1SOMI[0]

G18

R2

V9

Pull Up

Programmable, MibSPI1 slave-out master-

20uA in, or GPIO

MIBSPI1NCS[0]/MIBSPI1SOMI[1]

MIBSPI3CLK

I/O

Pull Up

Programmable, MibSPI3 clock, or GPIO

20uA

MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS

MIBSPI3NCS[1]/N2HET1[25]/MDCLK

MIBSPI3NCS[2]/I2C_SDA/N2HET1[27]

MIBSPI3NCS[3]/I2C_SCL/N2HET1[29]

N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]

V10

V5

MibSPI3 chip select, or

GPIO

B2

C3

E3

Pull Down Programmable, MibSPI3 chip select, or

20uA GPIO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]

W9

Pull Up

Programmable, MibSPI3 chip select, or

20uA

GPIO

MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]

W9

W8

MibSPI3 enable, or GPIO

MIBSPI3SIMO[0]

MibSPI3 slave-in master-

out, or GPIO

MIBSPI3SOMI[0]

V8

MibSPI3 slave-out master-

in, or GPIO

MIBSPI5CLK/DMM_DATA[4]

H19

E19

B6

I/O

Pull Up

Programmable, MibSPI5 clock, or GPIO

20uA

MIBSPI5NCS[0]/DMM_DATA[5]

MIBSPI5NCS[1]/DMM_DATA[6]

MIBSPI5NCS[2]/DMM_DATA[2]

MIBSPI5NCS[3]/DMM_DATA[3]

MIBSPI5NENA/DMM_DATA[7]/

MIBSPI5SIMO[0]/DMM_DATA[8]

MIBSPI5SIMO[1]/DMM_DATA[9]

MIBSPI5SIMO[2]/DMM_DATA[10]

MIBSPI5SIMO[3]/DMM_DATA[11]

MIBSPI5SOMI[0]/DMM_DATA[12]

MIBSPI5SOMI[1]/DMM_DATA[13]

MIBSPI5SOMI[2]/DMM_DATA[14]

MIBSPI5SOMI[3]/DMM_DATA[15]

MibSPI5 chip select, or

GPIO

W6

T12

H18

J19

E16

H17

G17

J18

E17

H16

G16

MibSPI5 enable, or GPIO

MibSPI5 slave-in master-

out, or GPIO

16

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.11 Ethernet Controller

Table 4-11. GWT Ethernet Controller: MDIO Interface

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

MIBSPI3NCS[1]/N2HET1[25]/MDCLK

MIBSPI1NCS[2]/N2HET1[19]/MDIO

V5

G3

Output

I/O

Pull Up

-

Serial clock output

Fixed, 20uA

Serial data input/output

Table 4-12. GWT Ethernet Controller: Reduced Media Independent Interface (RMII)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

N2HET1[12]/MII_CRS/RMII_CRS_DV

B4

Input

Pull Down

Fixed, 20uA

RMII carrier sense and

data valid

N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4

K19

RMII synchronous

reference clock for

receive, transmit and

control interface

AD1EVT/MII_RX_ER/RMII_RX_ER

N19

P1

RMII receive error

RMII receive data

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

N2HET1[26]/MII_RXD[1]/RMII_RXD[1]

A14

J18

J19

H19

MIBSPI5SOMI[0]/DMM_DATA[12]/MII_TXD[0]/RMII_TXD[0]

MIBSPI5SIMO[0]/DMM_DATA[8]/MII_TXD[1]/RMII_TXD[1]

MIBSPI5CLK/DMM_DATA[4]/MII_TXEN/RMII_TXEN

Output

Pull Up

-

RMII transmit data

RMII transmit enable

Table 4-13. GWT Ethernet Controller: Media Independent Interface (MII)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

MIBSPI1NCS[1]/N2HET1[17]/MII_COL

N2HET1[12]/MII_CRS/RMII_CRS_DV

F3

B4

Input

Pull Up

-

Collision detect

Pull Down

Fixed, 20uA

Carrier sense and receive

valid

N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4

N2HET1[30]/MII_RX_DV

K19

B11

N19

K19

P1

I/O

Pull Down

-

MII output receive clock

Received data valid

Receive error

Input

Fixed, 20uA

AD1EVT/MII_RX_ER/RMII_RX_ER

N2HET1[28]/MII_RX_CLK/RMII_REFCLK/MII_RX_AVCLK4

N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0]

N2HET1[26]/MII_RXD[1]/RMII_RXD[1]

I/O

Receive clock

Input

Receive data

A14

G19

H18

D19

J18

J19

R2

MIBSPI1NENA/N2HET1[23]/MII_RXD[2]

MIBSPI5NENA/DMM_DATA[7]/

Pull Up

Pull Down

Pull Up

Fixed, 20uA

N2HET1[10]/MII_TX_CLK/MII_TX_AVCLK4

MIBSPI5SOMI[0]/DMM_DATA[12]/RMII_TXD[0]

MIBSPI5SIMO[0]/DMM_DATA[8]/RMII_TXD[1]

MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]

N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3]

MIBSPI5CLK/DMM_DATA[4]/RMII_TXEN

I/O

-

MII output transmit clock

Transmit clock

Output

Transmit data

E18

H19

Pull Down

Pull Up

-

Transmit enable

Pin Configuration and Functions

17

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.12 External Memory Interface (EMIF)

Table 4-14. External Memory Interface (EMIF)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

EMIF_CKE

EMIF_CLK

L3

K3

Output Pull Down Programmable, EMIF Clock Enablen

20uA

I/O

EMIF clock. This is an

output signal in functional

mode. It is gated off by

default, so that the signal

is tri-stated. PINMUX29[8]

must be cleared to enable

this output.

EMIF_nWE/EMIF_RNW

D17

E12

P3

Output

I/O

Pull Up

Programmable, EMIF Read-Not-Write

20uA

ETMDATA[13]/EMIF_nOE

Pull Down Programmable, EMIF Output Enable

20uA

EMIF_nWAIT

Pull Up

Fixed, 20uA

EMIF Extended Wait

Signal

EMIF_nWE/EMIF_RNW

D17

R4

Output

Pull Up

Programmable, EMIF Write Enable.

20uA

EMIF_nCAS

EMIF column address

strobe

EMIF_nRAS

R3

Output

EMIF row address strobe

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

N17

Output Pull Down Programmable, EMIF chip select, SDRAM

20uA

EMIF_nCS[2]

L17

K17

M17

Output

Pull Up

Programmable, EMIF chip selects,

20uA

asynchronous

This applies to chip

selects 2, 3 and 4

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

EMIF_nCS[4]/RTP_DATA[7]

Output Pull Down Programmable,

20uA

Output

Pull Up

Programmable,

20uA

18

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

Table 4-14. External Memory Interface (EMIF) (continued)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

ETMDATA[15]/EMIF_nDQM[0]

ETMDATA[14]/EMIF_nDQM[1]

E10

E11

Output Pull Down Programmable, EMIF Data Mask or Write

20uA

Strobe.

Output

Data mask for SDRAM

devices, write strobe for

connected asynchronous

devices.

ETMDATA[12]/EMIF_BA[0]

EMIF_BA[1]/N2HET2[5]

E13

D16

Output

EMIF bank address or

address line

EMIF bank address or

address line

EMIF_ADDR[0]/N2HET2[1]

D4

D5

Output

Output Pull Down

Output

EMIF address

EMIF_ADDR[1]/N2HET2[3]

ETMDATA[11]/EMIF_ADDR[2]

ETMDATA[10]/EMIF_ADDR[3]

ETMDATA[9]/EMIF_ADDR[4

ETMDATA[8]/EMIF_ADDR[5]

EMIF_ADDR[6]/RTP_DATA[13]

EMIF_ADDR[7]/RTP_DATA[12]

EMIF_ADDR[8]/RTP_DATA[11]

EMIF_ADDR[9]/RTP_DATA[10]

EMIF_ADDR[10]/RTP_DATA[9]

EMIF_ADDR[11]/RTP_DATA[8]

EMIF_ADDR[12]/RTP_DATA[6]

EMIF_ADDR[13]/RTP_DATA[5]

EMIF_ADDR[14]/RTP_DATA[4]

EMIF_ADDR[15]/RTP_DATA[3]

EMIF_ADDR[16]/RTP_DATA[2]

EMIF_ADDR[17]/RTP_DATA[1]

EMIF_ADDR[18]/RTP_DATA[0]

EMIF_ADDR[19]/RTP_nENA

EMIF_ADDR[20]/RTP_nSYNC

EMIF_ADDR[21]/RTP_CLK

E6

E7

E8

E9

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

D14

C14

D15

C15

C16

C17

K15

L15

M15

N15

E5

-

ETMDATA[16]/EMIF_DATA[0]

ETMDATA[17]/EMIF_DATA[1]

ETMDATA[18]/EMIF_DATA[2]

ETMDATA[19]/EMIF_DATA[3]

ETMDATA[20]/EMIF_DATA[4]

ETMDATA[21]/EMIF_DATA[5]

ETMDATA[22]/EMIF_DATA[6]

ETMDATA[23]/EMIF_DATA[7]

ETMDATA[24]/EMIF_DATA[8]

ETMDATA[25]/EMIF_DATA[9]

ETMDATA[26]/EMIF_DATA[10]

ETMDATA[27]/EMIF_DATA[11]

ETMDATA[28]/EMIF_DATA[12]

ETMDATA[29]/EMIF_DATA[13]

ETMDATA[30]/EMIF_DATA[14]

ETMDATA[31]/EMIF_DATA[15]

I/O

Pull Down

Fixed, 20uA

EMIF Data

F5

G5

K5

L5

M5

N5

P5

R5

R6

R7

R8

Pin Configuration and Functions

19

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.13 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)

Table 4-15. Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

ETMTRACECLKIN/EXTCLKIN2

R9

R10

R11

R12

R13

J15

H15

G15

F15

E15

E14

E9

Input Pull Down Fixed, 20uA

ETM Trace Clock Input

ETM Trace Clock Output

ETM trace control

ETM data

ETMTRACECLKOUT

Output Pull Down

-

ETMTRACECTL

ETMDATA[0]

ETMDATA[1]

ETMDATA[2]

ETMDATA[3]

ETMDATA[4]

ETMDATA[5]

ETMDATA[6]

ETMDATA[7]

ETMDATA[8]/EMIF_ADDR[5]

ETMDATA[9]/EMIF_ADDR[4]

ETMDATA[10]/EMIF_ADDR[3]

ETMDATA[11]/EMIF_ADDR[2]

ETMDATA[12]/EMIF_BA[0]

ETMDATA[13]/EMIF_nOE

ETMDATA[14]/EMIF_nDQM[1]

ETMDATA[15]/EMIF_nDQM[0]

ETMDATA[16]/EMIF_DATA[0]

ETMDATA[17]/EMIF_DATA[1]

ETMDATA[18]/EMIF_DATA[2]

ETMDATA[19]/EMIF_DATA[3]

ETMDATA[20]/EMIF_DATA[4]

ETMDATA[21]/EMIF_DATA[5]

ETMDATA[22]/EMIF_DATA[6]

ETMDATA[23]/EMIF_DATA[7]

ETMDATA[24]/EMIF_DATA[8]

ETMDATA[25]/EMIF_DATA[9]

ETMDATA[26]/EMIF_DATA[10]

ETMDATA[27]/EMIF_DATA[11]

ETMDATA[28]/EMIF_DATA[12]

ETMDATA[29]/EMIF_DATA[13]

ETMDATA[30]/EMIF_DATA[14]

ETMDATA[31]/EMIF_DATA[15]

E8

E7

E6

E13

E12

E11

E10

K15

L15

M15

N15

E5

F5

G5

K5

L5

M5

N5

P5

R5

R6

R7

R8

20

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.14 RAM Trace Port (RTP)

Table 4-16. RAM Trace Port (RTP)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

EMIF_ADDR[21]/RTP_CLK

EMIF_ADDR[19]/RTP_nENA

EMIF_ADDR[20]/RTP_nSYNC

C17

C15

C16

I/O

Pull Down Programmable, RTP packet clock, or

20uA

GPIO

RTP packet handshake,

or GPIO

RTP synchronization, or

GPIO

EMIF_ADDR[18]/RTP_DATA[0]

EMIF_ADDR[17]/RTP_DATA[1]

EMIF_ADDR[16]/RTP_DATA[2]

EMIF_ADDR[15]/RTP_DATA[3]

EMIF_ADDR[14]/RTP_DATA[4]

EMIF_ADDR[13]/RTP_DATA[5]

EMIF_ADDR[12]/RTP_DATA[6]

EMIF_nCS[4]/RTP_DATA[7]

D15

C14

D14

C13

C12

C11

C10

M17

RTP packet data, or GPIO

Pull Up

Programmable,

20uA

EMIF_ADDR[11]/RTP_DATA[8]

EMIF_ADDR[10]/RTP_DATA[9]

EMIF_ADDR[9]/RTP_DATA[10]

EMIF_ADDR[8]/RTP_DATA[11]

EMIF_ADDR[7]/RTP_DATA[12]

EMIF_ADDR[6]/RTP_DATA[13]

EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7]

EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9]

C9

C8

Pull Down Programmable,

20uA

C7

C6

C5

C4

N17

K17

Pin Configuration and Functions

21

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.15 Data Modification Module (DMM)

Table 4-17. Data Modification Module (DMM)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

DMM_CLK

DMM_nENA

DMM_SYNC

F17

F16

J16

I/O

Pull Up

Programmable, DMM clock, or GPIO

20uA

DMM handshake, or GPIO

DMM synchronization, or

GPIO

DMM_DATA[0]

DMM_DATA[1]

L19

L18

W6

DMM data, or GPIO

MIBSPI5NCS[2]/DMM_DATA[2]

MIBSPI5NCS[3]/DMM_DATA[3]

MIBSPI5CLK/DMM_DATA[4]

T12

H19

E19

B6

MIBSPI5NCS[0]/DMM_DATA[5]

MIBSPI5NCS[1]/DMM_DATA[6]

MIBSPI5NENA/DMM_DATA[7]

MIBSPI5SIMO[0]/DMM_DATA[8]

MIBSPI5SIMO[1]/DMM_DATA[9]

MIBSPI5SIMO[2]/DMM_DATA[10]

MIBSPI5SIMO[3]/DMM_DATA[11]

MIBSPI5SOMI[0]/DMM_DATA[12]

MIBSPI5SOMI[1]/DMM_DATA[13]

MIBSPI5SOMI[2]/DMM_DATA[14]

MIBSPI5SOMI[3]/DMM_DATA[15]

H18

J19

E16

H17

G17

J18

E17

H16

G16

22

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.16 System Module Interface

Table 4-18. GWT System Module Interface

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

nPORRST

W7

Input

Pull Down

100uA

Power-on reset, cold reset

External power supply

monitor circuitry must

drive nPORRST low when

any of the supplies to the

microcontroller fall out of

the specified range. This

terminal has a glitch filter.

See 节 6.8.

nRST

B17

I/O

Pull Up

100uA

System reset, warm reset,

bidirectional.

The internal circuitry

indicates any reset

condition by driving nRST

low.

The external circuitry can

assert a system reset by

driving nRST low. To

ensure that an external

reset is not arbitrarily

generated, TI

recommends that an

external pull-up resistor is

connected to this terminal.

This terminal has a glitch

filter. See 节 6.8.

nERROR

B14

I/O

Pull Down

20uA

ESM Error Signal

Indicates error of high

severity. See 节 6.18.

4.1.1.1.17 Clock Inputs and Outputs

Table 4-19. GWT Clock Inputs and Outputs

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

OSCIN

K1

Input

-

From external

crystal/resonator, or

external clock input

KELVIN_GND

OSCOUT

L2

L1

Input

Kelvin ground for oscillator

Output

To external

crystal/resonator

ECLK

A12

I/O

Pull Down Programmable, External prescaled clock

20uA

output, or GIO.

GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS

ETMTRACECLKIN/EXTCLKIN2

VCCPLL

B5

R9

Input

Pull Down

20uA

External clock input #1

External clock input #2

P11

1.2V

Power

-

Dedicated core supply for

PLL's

Pin Configuration and Functions

23

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.18 Test and Debug Modules Interface

Table 4-20. GWT Test and Debug Modules Interface

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

TEST

nTRST

RTCK

TCK

U2

I/O

Input

Output

Input

I/O

Pull Down

Fixed, 100uA

Test enable

D18

A16

B18

A17

C18

C19

JTAG test hardware reset

JTAG return test clock

JTAG test clock

-

None

Pull Down

Pull Up

Fixed, 100uA

TDI

JTAG test data in

TDO

I/O

Pull Down

Pull Up

JTAG test data out

JTAG test select

TMS

I/O

4.1.1.1.19 Flash Supply and Test Pads

Table 4-21. GWT Flash Supply and Test Pads

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

VCCP

F8

3.3V

-

None

Flash pump supply

Power

FLTP1

FLTP2

J5

Flash test pads. These

terminals are reserved for

TI use only. For proper

operation these terminals

must connect only to a

test pad or not be

H5

connected at all [no

connect (NC)].

24

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.20 No Connects

Table 4-22. No Connects

Signal Name

Signal

Type

Default

Pull State

Pull Type

Description

337

GWT

NC

A8

B8

-

No Connects. These balls

are not connected to any

internal logic and can be

connected to the PCB

ground without affecting

the functionality of the

device. Any other ball

marked as "NC" may be

internally connected to

some functionality. It is

recommended for such

balls to be left

B9

D6

D7

D8

D9

D10

D11

D12

D13

E4

unconnected.

F4

G4

K4

K16

L4

L16

M4

M16

N4

N16

N18

P4

P15

P16

P17

R1

R14

R15

T3

T4

T5

T6

T7

T8

T9

T10

T11

T13

T14

U3

U4

Pin Configuration and Functions

25

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Table 4-22. No Connects (continued)

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

NC

U6

U7

-

No Connects. These balls

are not connected to any

internal logic and can be

connected to the PCB

ground without affecting

the functionality of the

device. Any other ball

marked as "NC" may be

internally connected to

some functionality. It is

recommended for such

balls to be left

U8

U9

U10

U11

V3

V4

V11

V12

W4

W11

W12

W13

unconnected.

4.1.1.1.21 Supply for Core Logic: 1.2V nominal

Table 4-23. GWT Supply for Core Logic: 1.2V nominal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

VCC

F9

F10

H10

J14

K6

1.2V

Power

-

None

Core supply

K8

K12

K14

L6

M10

P10

26

Pin Configuration and Functions

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

4.1.1.1.22 Supply for I/O Cells: 3.3V nominal

Table 4-24. GWT Supply for I/O Cells: 3.3V nominal

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

VCCIO

F6

F7

3.3V

Power

-

None

Operating supply for I/Os

F11

F12

F13

F14

G6

G14

H6

H14

J6

L14

M6

M14

N6

N14

P6

P7

P8

P9

P12

P13

P14

Pin Configuration and Functions

27

Submit Documentation Feedback

Product Folder Links: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

4.1.1.1.23 Ground Reference for All Supplies Except VCCAD

Table 4-25. GWT Ground Reference for All Supplies Except VCCAD

Signal

Type

Default

Pull State

Pull Type

Description

Signal Name

337

GWT

VSS

A1

A2

Ground

-

None

Ground reference

A18

A19

B1

B19

H8

H9

H11

H12

J8

J9

J10

J11

J12

K9

K10

K11

L8

L9

L10

L11

L12

M8

M9

M11

M12

V1

W1

W2

28

Pin Configuration and Functions

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature⁽¹⁾

MIN

–0.3

MAX

1.43

4.6

UNIT

(2)

V_CC

(2)

Supply voltage

Input voltage

V_CCIO, V_CCP

V

V_CCAD

5.5

All input pins

ADC input pins

I_IK(V_I< 0 or V_I> V_CCIO

4.6

V

5.5

)

–20

–10

20

10

All pins, except AD1IN[23:0] and AD2IN[15:0]

Input clamp current

I_IK(V_I< 0 or V_I> V_CCAD

AD1IN[23:0] and AD2IN[15:0]

)

mA

Total

–40

–55

–65

40

T_J

Operating junction temperature

Storage temperature

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated

grounds.

5.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human Body Model (HBM), per AEC Q100-002⁽¹⁾

V_ESD

Electrostatic discharge

All pins

V

Charged Device Model (CDM),

per AEC Q100-011

Corner pins

±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS‑001 specification.

5.3 Power-On Hours (POH)

POH is a function of voltage and temperature. Usage at higher voltages and temperatures will result in a reduction in POH to

achieve the same reliability performance.^(1)(2)(3)(4)

JUNCTION

TEMPERATURE (T_J)

NOMINAL CVDD VOLTAGE (V)

LIFETIME POH⁽⁵⁾

1.2

105 °C

100K

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms

and conditions for TI semiconductor products.

(2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table.

(3) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

(4) Notations in this table cannot be deemed a warranty or deemed to extend or modify the warranty under TI's standard terms and

conditions for TI semiconductor products.

(5) POH represent device operation under the specified nominal conditions continuously for the duration of the calculated lifetime.

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

1.14

3

NOM

1.2

MAX UNIT

V_CC

Digital logic supply voltage (Core)

PLL supply voltage

1.32

3.6

V

V_CCPLL

V_CCIO

V_CCAD

V_CCP

V_SS

1.2

Digital logic supply voltage (I/O)

MibADC supply voltage

3.3

3

3.3/5.0

3.3

5.25

3.6

Flash pump supply voltage

Digital logic supply ground

3

0

(1) All voltages are with respect to V_SS, except V_CCAD, which is with respect to V_SSAD

提交文档反馈意见

Specifications

29

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.1

NOM

MAX UNIT

V_SSAD

V_ADREFHI

V_ADREFLO

V_SLEW

T_A

MibADC supply ground

0.1

V_CCAD

1

V

A-to-D high-voltage reference source

A-to-D low-voltage reference source

Maximum positive slew rate for V_CCIO, V_CCADand V_CCPsupplies

Operating free-air temperature

V_SSAD

V

V/µs

°C

–55

125

T_J

Operating junction temperature⁽²⁾

150

(2) Reliability data is based upon a temperature profile that is equivalent to 100000 power-on hours at 105°C junction temperature. See

图 5-1 for more details.

1000000

100000

10000

1000

90

100

110

120

130

140

150

160

Operation Junction Temperature (°C)

(1) Silicon operating life design goal is 100000 power-on hours (POH) at 105°C junction temperature (does not include package

interconnect life).

(2) The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant

failure mechanism affecting device wearout for the specific device process and design characteristics.

图 5-1. TMS570LS3137-EP Operating Life Derating Chart

30

Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

5.5 Power Consumption

over Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

f_HCLK= 180 MHz

MIN

TYP

MAX UNIT

V_CCDigital supply current (operating mode)

220⁽¹⁾

440⁽²⁾

mA

f_VCLK= 90 MHz, Flash in pipelined

mode, V_CCmax

V_CCDigital supply current (LBIST mode)

V_CCDigital supply current (PBIST mode)

700⁽³⁾⁽⁴⁾

mA

LBIST clock rate = 90 MHz

PBIST ROM clock frequency = 90

MHz

I_CC,I_CCPLL

f_HCLK= 160 MHz

V_CCDigital supply current (operating mode)

V_CCDigital supply current (LBIST mode)

200⁽¹⁾

420⁽²⁾

mA

f_VCLK= 80 MHz, Flash in pipelined

mode, V_CCmax(–40°C to 125°C)

665⁽³⁾⁽⁴⁾

LBIST clock rate = 80 MHz (–40°C

to 125°C)

PBIST ROM clock frequency = 80

MHz (–40°C to 125°C)

V_CCDigital supply current (PBIST mode)

V_CCIOsupply current (operating mode)

665⁽³⁾⁽⁴⁾

10

mA

I_CCIO

No DC load, V_CCmax

Single ADC operational, V_CCADmax

(–40°C to 125°C)

15

I_CCAD

V_CCADsupply current (operating mode)

mA

Both ADCs operational, V_CCADmax

(–40°C to 125°C)

30

Single ADC operational, AD_REFHImax

(–40°C to 125°C)

3

6

I_ADREFHI

AD_REFHIsupply current (operating mode)

V_CCPpump supply current

mA

Both ADCs operational, AD_REFHImax

Read from 1 bank and program or

erase another bank, V_CCPmax

(–40°C to 125°C)

I_CCP

60

(1) The typical value is the average current for the nominal process corner and junction temperature of 25°C.

(2) The maximum I_CC,value can be derated

•

linearly with voltage

by 1 ma/MHz for lower operating frequency when f_HCLK= 2 × f_VCLK

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

235 - 0.15 e^{0.0174 T}

JK

(3) The maximum I_CC,value can be derated

•

linearly with voltage

by 1.7 ma/MHz for lower operating frequency when f_HCLK= 2 × f_VCLK

for lower junction temperature by the equation below where T_JKis the junction temperature in Kelvin and the result is in milliamperes.

235 - 0.15 e^{0.0174 T}

JK

(4) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the

device and the voltage regulator

5.6 Thermal Data

表 5-1 shows the thermal resistance characteristics for the BGA - GWT mechanical package.

表 5-1. Thermal Resistance Characteristics

(GWT Package)

PARAMETER

R_ΘJA

°C/W

18.8

14.1

7.1

R_ΘJB

R_ΘJC

Specifications

31

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

5.7 Switching Characteristics

over Recommended Operating Conditions for clock domains

表 5-2. Clock Domain Timing Specifications

PARAMETER

TEST CONDITIONS

Pipeline mode enabled

Pipeline mode disabled

MIN

MAX

180

50

UNIT

f_HCLK

HCLK - System clock frequency

MHz

f_GCLK

f_VCLK

GCLK - CPU clock frequency

f_HCLK

100

MHz

VCLK - Primary peripheral clock

frequency

f_VCLK2

VCLK2 - Secondary peripheral clock

frequency

100

50

MHz

f_VCLK3

VCLK3 - Secondary peripheral clock

frequency

f_VCLKA1

f_VCLKA2

f_VCLKA4

f_RTICLK

VCLKA1 - Primary asynchronous

peripheral clock frequency

VCLKA2 - Secondary asynchronous

peripheral clock frequency

VCLKA4 - Secondary asynchronous

peripheral clock frequency

RTICLK - clock frequency

f_VCLK

5.8 Wait States Required

RAM

0

Address Waitstates

0MHz

f_HCLK(max)

Data Waitstates

0MHz

f_HCLK(max)

Flash

1

Address Waitstates

0

1

150MHz

0MHz

f_HCLK(max)

Data Waitstates

0

2

3

0MHz

50MHz

100MHz

f_HCLK(max)

图 5-2. Wait States Scheme

As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait

states required.

The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in non-pipelined mode. The flash supports a

maximum CPU clock speed of 180MHz for the GWT package, with one address wait state and three data wait states.

The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait state.

32

Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

5.9 I/O Electrical Characteristics

over recommended operating conditions⁽¹⁾

TMS5703137CGWTQEP

TMS5703137CGWTMEP

TEST

CONDITIONS

PARAMETER

UNIT

MIN

TYP

MAX

0.2 V_CCIO

0.2

MIN

MAX

I_OL= I_OLmax

0.2 V_CCIO

0.2

I_OL= 50 µA,

standard output

mode

V_OLLow-level output voltage

V

I_OL= 50 µA, low-

EMI output mode

(see 节 5.13)

0.2 V_CCIO

I_OH= I_OHmax

0.8 V_CCIO

I_OH= 50 µA,

standard output

mode

V_CCIO– 0.3

V_O

H

High-level output voltage

V

I_OH= 50 µA, low-

EMI output mode

(see 节 5.13)

0.8 V_CCIO

–3.5

V_I< V_SSIO- 0.3 or

V_I> V_CCIO+ 0.3

-3.5

3.5

40

I_ICInput clamp current (I/O pins)

mA

µA

I_IHPulldown 20 µA

V_I= V_CCIO

5

40

195

-5

I_IHPulldown 100 µA V_I= V_CCIO

30

Input current

(I/O pins)

I_ILPullup 20 µA

I_ILPullup 100 µA

V_I= V_SS

-40

-195

-1

–60

–2

I_I

-40

1

No pullup or

pulldown

–1.5

1.5

All other pins

Input

capacitance

2

3

C_I

pF

Output

capacitance

C_O

(1) Source currents (out of the device) are negative while sink currents (into the device) are positive.

5.10 Output Buffer Drive Strengths

表 5-3. Output Buffer Drive Strengths

Low-Level Output Current,

I_OLfor V_I= V_OLmax

or

Signals

High-Level Output Current,

I_OHfor V_I= V_OHmin

FRAYTX2, FRAYTX1, FRAYTXEN1, FRAYTXEN2,

MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],

MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],

8 mA

4 mA

TMS, TDI, TDO, RTCK,

SPI4CLK, SPI4SIMO, SPI4SOMI, nERROR,

N2HET2[1], N2HET2[3],

All EMIF Outputs and I/Os, All ETM Outputs

MIBSPI3SOMI, MIBSPI3SIMO, MIBSPI3CLK, MIBSPI1SIMO, MIBSPI1SOMI, MIBSPI1CLK,

nRST

Specifications

33

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 5-3. Output Buffer Drive Strengths (continued)

Low-Level Output Current,

I_OLfor V_I= V_OLmax

or

Signals

High-Level Output Current,

I_OHfor V_I= V_OHmin

AD1EVT,

CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,

DMM_CLK, DMM_DATA[0], DMM_DATA[1], DMM_nENA, DMM_SYNC,

GIOA[0-7], GIOB[0-7],

LINRX, LINTX,

2 mA zero-dominant

MIBSPI1NCS[0], MIBSPI1NCS[1-3], MIBSPI1NENA, MIBSPI3NCS[0-3], MIBSPI3NENA,

MIBSPI5NCS[0-3], MIBSPI5NENA,

N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[5], N2HET2[6], N2HET2[7],

N2HET2[8], N2HET2[9], N2HET2[10], N2HET2[11], N2HET2[12], N2HET2[13], N2HET2[14],

N2HET2[15], N2HET2[16], N2HET2[18],

SPI4NCS[0], SPI4NENA

ECLK,

selectable 8 mA / 2 mA

SPI2CLK, SPI2SIMO, SPI2SOMI

The default output buffer drive strength is 8mA for these signals.

表 5-4. Selectable 8 mA/2 mA Control

Signal

ECLK

Control Bit

Address

8 mA

2 mA

SYSPC10[0]

SPI2PC9[9]

SPI2PC9[10]

SPI2PC9[11]

0xFFFF FF78

0xFFF7 F668

0

1

SPI2CLK

SPI2SIMO

SPI2SOMI

5.11 Input Timings

t_pw

V_CCIO

Input

V_IH

V_IL

0

图 5-3. TTL-Level Inputs

表 5-5. Timing Requirements for Inputs⁽¹⁾

MIN

t_c(VCLK)+ 10⁽²⁾

MAX

UNIT

ns

t_pw

Input minimum pulse width

–40°C to 125°C

(1) t_c(VCLK)= peripheral VBUS clock cycle time = 1 / f_(VCLK)

(2) The timing shown above is only valid for pin used in GPIO mode.

34

Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

5.12 Output Timings

表 5-6. Switching Characteristics for Output Timings versus Load Capacitance (C_L)

C_L= 15 pF, CL=50pF, C_L= 100 pF T_A= T_J= -40°C to 125°C, but for C_L= 150 pF load T_A= T_J= –55°C to 125°C

PARAMETER

MIN

MAX

2.5

4

UNIT

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

Rise time, t_r

Fall time, t_f

8 mA low EMI pins

(see 表 5-3)

CL = 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

C_L= 15 pF

C_L= 50 pF

C_L= 100 pF

C_L= 150 pF

ns

7.2

12.5

2.5

4

ns

7.2

12.5

5.6

10.4

16.8

23.2

5.6

10.4

16.8

23.2

8

4 mA low EMI pins

(see 表 5-3)

2 mA-z low EMI pins

(see 表 5-3)

15

23

33

8

15

23

33

Selectable 8 mA / 2 mA-z 8mA mode

pins

(see 表 5-3)

2.5

4

7.2

12.5

2.5

4

7.2

12.5

8

2mA-z mode

15

23

33

8

15

23

33

Specifications

35

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

t_r

t

f

V_CCIO

Output

V_OH

V_OL

0

图 5-4. CMOS-Level Outputs

表 5-7. Timing Requirements for Outputs⁽¹⁾

MIN

MAX UNIT

ns

t_{d(parallel_out)}

Delay between low to high, or high to low transition of

–40°C to 125°C

5

general-purpose output signals that can be configured by an

application in parallel, for example, all signals in a GIOA

port, or all N2HET1 signals, and so forth

(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check

表 5-3 for output buffer drive strength information on each signal.

36

Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

5.13 Low-EMI Output Buffers

The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of

emissions from the pins which they drive. This is accomplished by adaptively controlling the impedance of

the output buffer, and is particularly effective with capacitive loads.

This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the

system module GPCR1 register for the desired module or signal, as shown in 表 5-8. The adaptive

impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates

two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of

VCCIO, respectively.

Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then

the output buffer’s impedance will increase to hi-Z. A high degree of decoupling between the internal

ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,

e.g. the buffer is driving low on a resistive path to ground. Current loads on the buffer which attempt to pull

the output voltage above VREFLOW will be opposed by the buffer’s output impedance so as to maintain

the output voltage at or below VREFLOW.

Conversely, once the output buffer has driven the output to a high level, if the output voltage is above

VREFHIGH then the output buffer’s impedance will again increase to hi-Z. A high degree of decoupling

between internal power bus ad output pin will occur with capacitive loads or any loads in which no current

is flowing, e.g. buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which

attempt to pull the output voltage below VREFHIGH will be opposed by the buffer’s output impedance so

as to maintain the output voltage at or above VREFHIGH.

The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance

control mode cannot respond to high-frequency noise coupling into the buffer’s power buses. In this

manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.

Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will

allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a

negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an

issue since the actual clamp current capability is always greater than the IOH / IOL specifications.

The low-EMI output buffers are automatically configured to be in the standard buffer mode when the

device enters a low-power mode.

表 5-8. Low-EMI Output Buffer Hookup

Module or Signal Name

Control Register to Enable Low-EMI Mode

GPREG1.0

Module: MibSPI1

GPREG1.1

Module: MibSPI3

Reserved

GPREG1.2

GPREG1.3

Module: MibSPI5

Signal: TMS

Signal: TDI

GPREG1.4

GPREG1.8

GPREG1.9

Signal: TDO

Signal: RTCK

Signal: TEST

Signal: nERROR

Reserved

GPREG1.10

GPREG1.11

GPREG1.12

GPREG1.13

GPREG1.14

Specifications

37

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6 System Information and Electrical Specifications

6.1 Device Power Domains

The device core logic is split up into multiple power domains in order to optimize the power for a given

application use case. There are 8 core power domains in total: PD1, PD2, PD3, PD4, PD5, RAM_PD1,

RAM_PD2, and RAM_PD3.

The actual contents of these power domains are indicated in 节 1.4.

PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains

can be turned ON/OFF one time during device initialization as per the application requirement. Refer to

the Power Management Module (PMM) chapter of TMS570LS31X/21X Technical Reference Manual

(SPNU499) for more details.

注

The clocks to a module must be turned off before powering down the core domain that

contains the module.

注

The logic in the modules that are powered down lose power completely. Any access to

modules that are powered down results in an abort being generated. When power is

restored, the modules power-up to their default states (after normal power-up). No register or

memory contents are preserved in the core domains that are turned off.

38

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.2 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the

requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.2.1 Important Considerations

•

The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the

device is held in reset when the voltage supplies are out of range.

•

The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other

supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a

source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and

VCCP supplies.

6.2.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO

signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when

the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and

PGMCU being low isolates the core logic as well as the I/O controls during the power-up or power-down

of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When

the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output

pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device

enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to 节 6.3.3.1 for the timing

information on this glitch filter.

表 6-1. Voltage Monitoring Specifications

PARAMETER

MIN

TYP

MAX

UNIT

VCC low - VCC level below this threshold is detected as too

low.

0.75

0.9

1.13

V

Voltage monitoring VCC high - VCC level above this threshold is detected as too

1.40

1.85

1.7

2.4

2.1

2.9

V_MON

thresholds

high.

VCCIO low - VCCIO level below this threshold is detected as

too low.

6.2.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the

maximum specification cannot be filtered.

表 6-2. VMON Supply Glitch Filtering Capability

PARAMETER

Width of glitch on VCC that can be filtered

MIN

250

MAX

1000

UNIT

ns

Width of glitch on VCCIO that can be filtered

System Information and Electrical Specifications

39

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.3 Power Sequencing and Power On Reset

6.3.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-

up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see 表 6-4 for

more details), core voltage rising above the minimum core supply threshold and the release of power-on

reset. The high frequency oscillator will start up first and its amplitude will grow to an acceptable level. The

oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. The

different supplies to the device can be powered up in any order.

The device goes through the following sequential phases during power up.

表 6-3. Power-Up Phases

Phases

Oscillator start-up and validity check

eFuse autoload

Oscillator Cycles

1032 oscillator cycles

1180 oscillator cycles

688 oscillator cycles

617 oscillator cycles

3517 oscillator cycles

Flash pump power-up

Flash bank power-up

Total

The CPU reset is released at the end of the above sequence and fetches the first instruction from address

0x00000000.

40

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.3.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.3.3 Power-On Reset: nPORRST

This is the power-on reset. This reset must be asserted by an external circuitry whenever the I/O or core

supplies are outside the specified recommended range. This signal has a glitch filter on it. It also has an

internal pulldown.

6.3.3.1 nPORRST Electrical and Timing Requirements

表 6-4. Electrical Requirements for nPORRST

NO.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V_CCPORL

V_CCPORH

V_CClow supply level when nPORRST must be active –40°C to 125°C

during power-up

0.5

V

V_CChigh supply level when nPORRST must remain

active during power-up and become active during

power down

–40°C to 125°C

1.14

V

V_CCIOPORL

V_CCIOPORH

V_CCIO/ V_CCPlow supply level when nPORRST must –40°C to 125°C

be active during power-up

1.1

V

V_CCIO/ V_CCPhigh supply level when nPORRST must –40°C to 125°C

remain active during power-up and become active

during power down

3.0

V_IL(PORRST)

Low-level input voltage of nPORRST V_CCIO> 2.5 V

Low-level input voltage of nPORRST V_CCIO< 2.5 V

–40°C to 125°C

0.2 × V_CCIO

0.5

V

3

t_su(PORRST)

Setup time, nPORRST active before V_CCIOand V_CCP–40°C to 125°C

> V_CCIOPORLduring power-up

0

ms

6

7

t_h(PORRST)

t_su(PORRST)

Hold time, nPORRST active after V_CC> V_CCPORH

–40°C to 125°C

1

2

ms

µs

Setup time, nPORRST active before V_CC< V_CCPORH–40°C to 125°C

during power down

8

9

t_h(PORRST)

Hold time, nPORRST active after V_CCIOand V_CCP

V_CCIOPORH

>

–40°C to 125°C

1

ms

t_h(PORRST)

t_f(nPORRST)

Hold time, nPORRST active after V_CC< V_CCPORL

–40°C to 125°C

0

ms

ns

Filter time nPORRST pin;

500

2000

Pulses less than MIN will be filtered out, pulses

greater than MAX will generate a reset.

3.3 V

V_CCIOPORH

V_CCIO/ V_CCP

8

6

1.2 V

V_CCPORH

V_CC

V_CCPORH

7

6

V_CCIOPORL

7

V_CCIOPORL

V_CCPORL

V_CC(1.2 V)

V_CCIO/ V_CCP(3.3 V)

3

9

V_IL

V_IL(PORRST)

nPORRST

NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing.

图 6-1. nPORRST Timing Diagram

System Information and Electrical Specifications

41

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.4 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset

condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the

output buffer is implemented as an open drain (drives low only). To ensure an external reset is not

arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

6.4.1 Causes of Warm Reset

表 6-5. Causes of Warm Reset

DEVICE EVENT

SYSTEM STATUS FLAG

Exception Status Register, bit 15

Global Status Register, bit 0

Power-Up Reset

Oscillator fail

PLL slip

Global Status Register, bits 8 and 9

Exception Status Register, bit 13

Exception Status Register, bit 5

Exception Status Register, bit 4

Exception Status Register, bit 3

Watchdog exception / Debugger reset

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

6.4.2 nRST Timing Requirements

表 6-6. nRST Timing Requirements⁽¹⁾

MIN

2252 × t_c(OSC)

32 × t_c(VCLK)

MAX UNIT

t_v(RST)

Valid time, nRST active after nPORRST inactive

Valid time, nRST active (all other system reset conditions)

Filter time nRST pin;

–40°C to 125°C

ns

t_f(nRST)

475

2000

ns

Pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

(1) Specified values do NOT include rise/fall times. For rise and fall timings, see 表 5-6.

42

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.5 ARM^©Cortex™-R4F CPU Information

6.5.1 Summary of ARM Cortex-R4F CPU Features

The features of the ARM Cortex-R4F CPU include:

•

An integer unit with integral EmbeddedICE-RT logic

High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)

for Level two (L2) master and slave interfaces

•

Floating Point Coprocessor

Dynamic branch prediction with a global history buffer, and a 4-entry return stack

Low interrupt latency

Non-maskable interrupt

A Harvard Level one (L1) memory system with:

–

Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking

memories

–

ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions

•

Dual core logic for fault detection in safety-critical applications

An L2 memory interface:

–

Single 64-bit master AXI interface

64-bit slave AXI interface to TCM RAM blocks

•

A debug interface to a CoreSight Debug Access Port (DAP)

A trace interface to a CoreSight ETM-R4

A Performance Monitoring Unit (PMU)

A Vectored Interrupt Controller (VIC) port

For more information on the ARM Cortex-R4F CPU, see www.arm.com.

6.5.2 ARM Cortex-R4F CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

•

ECC On Tightly-Coupled Memory (TCM) Accesses

Harware Vectored Interrupt (VIC) Port

Floating Point Coprocessor

Memory Protection Unit (MPU)

6.5.3 Dual Core Implementation

The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-

R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock

cycles as shown in 图 6-3.

The CPUs have a diverse CPU placement given by following requirements:

•

Different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation

Dedicated guard ring for each CPU

Flip West

North

F

图 6-2. Dual - CPU Orientation

System Information and Electrical Specifications

43

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.5.4 Duplicate Clock Tree After GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU

running at the same frequency and in phase to the clock of CPU1. See 图 6-3.

6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety

This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in

the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in

a different way as shown in the figure below.

Output + Control

CCM-R4

2 cycle delay

CCM-R4

compare

error

CPU1CLK

CPU 1

CPU 2

2 cycle delay

CPU2CLK

Input + Control

图 6-3. Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of

both CPUs before the registers are used, including function calls where the register values are pushed

onto the stack.

6.5.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the

Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

•

Ability to divide the complete test run into independent test intervals

Capable of running the complete test as well as running few intervals at a time

Ability to continue from the last executed interval (test set) as well as ability to restart from the

beginning (First test set)

•

Complete isolation of the self-tested CPU core from rest of the system during the self-test run

Ability to capture the Failure interval number

Timeout counter for the CPU self-test run as a fail-safe feature

44

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.5.6.1 Application Sequence for CPU Self-Test

1. Configure clock domain frequencies.

2. Select number of test intervals to be run.

3. Configure the timeout period for the self-test run.

4. Enable self-test.

5. Wait for CPU reset.

6. In the reset handler, read CPU self-test status to identify any failures.

7. Retrieve CPU state if required.

For more information see the device specific technical reference manual.

6.5.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 90MHz. The STCCLK is divided down from the CPU clock.

This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

For more information see the device specific technical reference manual.

6.5.6.3 CPU Self-Test Coverage

表 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test

cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

表 6-7. CPU Self-Test Coverage

INTERVALS

TEST COVERAGE (%)

0

TEST CYCLES

0

1

62.13

70.09

74.49

77.28

79.28

80.90

82.02

83.10

84.08

84.87

85.59

86.11

86.67

87.16

87.61

87.98

88.38

88.69

88.98

89.28

89.50

89.76

90.01

90.21

1365

2

2730

3

4095

4

5460

5

6825

6

8190

7

9555

8

10920

12285

13650

15015

16380

17745

19110

20475

21840

23205

24570

25935

27300

28665

30030

31395

32760

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

System Information and Electrical Specifications

45

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.6 Clocks

6.6.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled

or disabled using the CSDISx registers in the system module. The clock source number in the table

corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

表 6-8. Available Clock Sources

Clock Source

Number

Name

Description

Default State

0

1

2

3

4

5

6

7

OSCIN

PLL1

Main oscillator

Output from PLL1

Reserved

Enabled

Disabled

Enabled

Disabled

Reserved

EXTCLKIN1

CLK80K

CLK10M

PLL2

External clock input 1

Low frequency output of internal reference oscillator

High frequency output of internal reference oscillator

Output from PLL2

EXTCLKIN2

Reserved

External clock input 2

Reserved

6.6.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors

across the external OSCIN and OSCOUT pins as shown in 图 6-4. The oscillator is a single stage inverter

held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and

low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal

vendors for validation. The vendors are equipped to determine what load capacitors will best tune

their resonator/crystal to the microcontroller device for optimum start-up and operation over

temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3V clock signal to the OSCIN pin and leaving

the OSCOUT pin unconnected (open) as shown in the figure below.

(see Note B)

OSCIN

Kelvin_GND

OSCOUT

OSCIN

OSCOUT

C1

C2

External

Clock Signal

(toggling 0-3.3V)

(see Note A)

Crystal

(a)

(b)

Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.

Note B: Kelvin_GND should not be connected to any other GND.

图 6-4. Recommended Crystal/Clock Connection

46

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.6.1.1.1 Timing Requirements for Main Oscillator

表 6-9. Timing Requirements for Main Oscillator

MIN

50

MAX

200

UNIT

ns

t_c(OSC)

Cycle time, OSCIN (when using a sine-wave input)

t_{c(OSC_SQR)}

Cycle time, OSCIN, (when input to the OSCIN is a

square wave)

50

200

ns

t_w(OSCIL)

t_w(OSCIH)

Pulse duration, OSCIN low (when input to the OSCIN –40°C to 125°C

is a square wave)

6

ns

Pulse duration, OSCIN high (when input to the

OSCIN is a square wave)

–40°C to 125°C

System Information and Electrical Specifications

47

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.6.1.2 Low Power Oscillator (LPO)

The LPO is comprised of two oscillators — HF LPO and LF LPO, in a single macro.

6.6.1.2.1 Features

The main features of the LPO are:

•

Supplies a clock at extremely low power for power-saving modes. This is connected as clock source #

4 of the Global Clock Module.

Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source # 5

of the Global Clock Module.

Provides a comparison clock for the crystal oscillator failure detection circuit.

BIAS_EN

LFEN

CLK80K

LF_TRIM

Low

Power

Oscillator

HFEN

CLK10M

HF_TRIM

CLK10M_VALID

nPORRST

图 6-5. LPO Block Diagram

图 6-5 shows a block diagram of the internal reference oscillator. This is a low power oscillator (LPO) and

provides two clock sources: one nominally 80KHz and one nominally 10MHz.

6.6.1.2.2 LPO Electrical and Timing Specifications

表 6-10. LPO Specifications

MIN

NOM

MAX UNIT

LPO - HF oscillator

LPO - LF oscillator

Untrimmed frequency

5.5

9.6

19.5 MHz

Startup time from STANDBY (LPO BIAS_EN High for at least

900 µs)

10

µs

Cold startup time

900

µs

Untrimmed frequency

36

85

180 kHz

Startup time from STANDBY (LPO BIAS_EN High for at least

900 µs)

100

µs

Cold startup time

2000

µs

48

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.6.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

•

Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The

frequency modulation capability of PLL2 is permanently disabled.

•

Configurable frequency multipliers and dividers.

Built-in PLL Slip monitoring circuit.

Option to reset the device on a PLL slip detection.

6.6.1.3.1 Block Diagram

The 图 6-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and

PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the

multiplier and dividers for PLL2.

/NR

/OD

/R

PLLCLK

OSCIN

INTCLK

VCOCLK

post_ODCLK

PLL

/1 to /64

/1 to /8

/1 to /32

f_PLLCLK= (f_OSCIN/ NR) * NF / (OD * R)

/NF

/1 to /256

/NR2

/OD2

/R2

PLL2CLK

OSCIN

VCOCLK2

INTCLK2

post_ODCLK2

/1 to /64

PLL#2

/1 to /8

/1 to /32

f_PLL2CLK= (f_OSCIN/ NR2) * NF2 / (OD2 * R2)

/NF2

/1 to /256

图 6-6. GWT PLLx Block Diagram

表 6-11. PLL Timing Specifications

6.6.1.3.2 PLL Timing Specifications

MIN

MAX

20

UNIT

MHz

f_INTCLK

PLL1 reference clock frequency

1

f_{post_ODCLK}

f_VCOCLK

Post-ODCLK – PLL1 post-divider input clock frequency

VCOCLK – PLL1 output divider (OD) input clock frequency

PLL2 reference clock frequency

400

550

20

150

1

f_INTCLK2

f_{post_ODCLK2}

f_VCOCLK2

Post-ODCLK – PLL2 post-divider input clock frequency

VCOCLK – PLL2 output divider (OD) input clock frequency

400

550

150

System Information and Electrical Specifications

49

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.6.1.4 External Clock Inputs

The device supports up to two external clock inputs. This clock input must be a square wave input. The

electrical and timing requirements for these clock inputs are specified below. The external clock sources

are not checked for validity. They are assumed valid when enabled.

表 6-12. External Clock Timing and Electrical Specifications

PARAMETER

TEST CONDITIONS

–40°C to 125°C

MIN

MAX UNIT

f_EXTCLKx

External clock input frequency

EXTCLK high-pulse duration

EXTCLK low-pulse duration

Low-level input voltage

High-level input voltage

80

MHz

ns

V

t_w(EXTCLKIN)H

t_w(EXTCLKIN)L

v_iL(EXTCLKIN)

v_iH(EXTCLKIN)

–40°C to 125°C

6

–0.3

2

0.8

VCCIO + 0.3

V

6.6.2 Clock Domains

6.6.2.1 Clock Domain Descriptions

表 6-13 lists the device clock domains and their default clock sources. The table also shows the system

module control register that is used to select an available clock source for each clock domain.

表 6-13. Clock Domain Descriptions

Default Clock

Source

Clock Source

Selection Register

Clock Domain Name

Description

HCLK

OSCIN

GHVSRC

•

Is disabled via the CDDISx registers bit 1

Used for all system modules including DMA, ESM

GCLK

OSCIN

GHVSRC

•

Always the same frequency as HCLK

In phase with HCLK

Is disabled separately from HCLK via the CDDISx registers bit 0

Can be divided by 1up to 8 when running CPU self-test (LBIST)

using the CLKDIV field of the STCCLKDIV register at address

0xFFFFE108

GCLK2

OSCIN

GHVSRC

•

Always the same frequency as GCLK

2 cycles delayed from GCLK

Is disabled along with GCLK

Gets divided by the same divider setting as that for GCLK when

running CPU self-test (LBIST)

VCLK

OSCIN

GHVSRC

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Is disabled separately from HCLK via the CDDISx registers bit 2

VCLK2

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Frequency must be an integer multiple of VCLK frequency

Is disabled separately from HCLK via the CDDISx registers bit 3

VCLK3

OSCIN

GHVSRC

•

Divided down from HCLK

Can be HCLK/1, HCLK/2, ... or HCLK/16

Is disabled separately from HCLK via the CDDISx registers bit 8

VCLKA1

VCLKA2

VCLK

VCLKASRC

•

Defaults to VCLK as the source

Is disabled via the CDDISx registers bit 4

•

Defaults to VCLK as the source

Is disabled via the CDDISx registers bit 5

50

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-13. Clock Domain Descriptions (continued)

Default Clock

Source

Clock Source

Selection Register

Clock Domain Name

Description

VCLKA3_S

VCLK

VCLKACON

•

Defaults to VCLK as the source

Frequency can be as fast as HCLK frequency.

Is disabled via the CDDISx registers bit 10

VCLKA3_DIVR

VCLK

VCLKACON1

•

Divided down from the VCLKA3_S using the VCLKA3R field of

the VCLKACON1 register at address 0xFFFFE140

Frequency can be VCLKA3_S/1, VCLKA3_S/2, ..., or

VCLKA3_S/8

•

Default frequency is VCLKA3_S/2

Is disabled separately via the VCLKACON1 register

VCLKA3_DIV_CDDIS bit only if the VCLKA3_S clock is not

disabled

VCLKA4

RTICLK

VCLK

VCLKACON1

RCLKSRC

•

Defaults to VCLK as the source

Is disabled via the CDDISx registers bit 11

•

Defaults to VCLK as the source

If a clock source other than VCLK is selected for RTICLK, then

the RTICLK frequency must be less than or equal to VCLK/3

–

Application can ensure this by programming the RTI1DIV

field of the RCLKSRC register, if necessary

•

Is disabled via the CDDISx registers bit 6

System Information and Electrical Specifications

51

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.6.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figures below.

GCM

0

GCLK, GCLK2 (to CPU)

HCLK (to SYSTEM)

OSCIN

FMzPLL

X1..256

(SSPLL)

/1..8

1

/1..32

/1..64

*

VCLK_peri (VCLK to peripherals on PCR1)

VCLK_sys (VCLK to system modules)

VCLK2 (to N2HETx and HTUx)

/1..16

4

5

80kHz

/1..16

Low Power

Oscillator

10MHz

VCLK3 (to EMIF, and Ethernet)

PLL # 2 (SSPLL)

6

/1..32

*

/1..64 X1..256

/1..8

0

1

3

4

5

6

3

7

* the frequency at this node must not

exceed the maximum HCLK specifiation.

EXTCLKIN1

EXTCLKIN2

VCLKA1 (to DCANx)

7

VCLK

VCLK3

0

1

3

VCLKA4

4

5

6

VCLKA2 (to FlexRay)

7

VCLK

Ethernet

0

1

3

4

VCLKA4 (to Ethernet, as alternate

for MIITXCLK and/or MIIRXCLK)

5

6

7

0

1

VCLK

3

4

/1, 2, 4, or 8

5

6

7

RTICLK (to RTI, DWWD)

EMIF

VCLK

VCLKA1

VCLK

VCLK2

VCLKA2

VCLK2

VCLKA2

HRP

/1..64

/2,3..2²⁴

/1,2..32

/1,2..65536

/1,2..256

/1,2,..4

/1,2,..256

/1,2,..1024

N2HETx

TU

FlexRay

TU

GTUC1,2

LRP

/2⁰..2⁵

Prop_seg

Phase_seg2

FlexRay

Baud

Rate

I2C baud

rate

ECLK

SPI

Baud Rate

ADCLK

LIN / SCI

Baud Rate

Phase_seg1

I2C

Loop

High

Resolution Clock

SPIx,MibSPIx

LIN, SCI

External Clock

MibADCx

FlexRay

EXTCLKIN1

NTU[3]

CAN Baud Rate

DCANx

PLL#2 output

Start of cycle

Macro Tick

NTU[2]

NTU[1]

NTU[0]

N2HETx

RTI

图 6-7. Device Clock Domains

52

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.6.3 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be brought

out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is

very useful for debugging purposes and can be configured via the CLKTEST register in the system

module.

表 6-14. Clock Test Mode Options

SEL_ECP_PIN

SEL_GIO_PIN

=

SIGNAL ON ECLK

SIGNAL ON N2HET1[12]

CLKTEST[3-0]

CLKTEST[11-8]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Oscillator

Main PLL free-running clock output

Reserved

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Oscillator Valid Status

Main PLL Valid status

Reserved

EXTCLKIN1

Reserved

CLK80K

Reserved

CLK10M

CLK10M Valid status

Secondary PLL Valid Status

Reserved

Secondary PLL free-running clock output

GCLK

CLK80K

RTI Base

Reserved

VCLKA1

VCLKA2

Reserved

VCLKA4

Reserved

System Information and Electrical Specifications

53

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.7 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low

power oscillator (LPO).

The LPO provides two different clock sources – a low frequency (CLK80K) and a high frequency

(CLK10M).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN

frequency falls out of a frequency window, the CLKDET flags this condition in the global status register

(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the CLK10M clock (limp

mode clock).

The valid OSCIN frequency range is defined as: f_CLK10M/ 4 < f_OSCIN< f_CLK10M* 4.

6.7.1 Clock Monitor Timings

表 6-15. LPO and Clock Detection

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Clock Detection

oscillator fail frequency - lower threshold,

using untrimmed LPO output

1.375

2.4

4.875

MHz

oscillator fail frequency - higher threshold,

using untrimmed LPO output

22

38.4

9.6

78

MHz

LPO - HF oscillator untrimmed frequency

5.5

19.5

10

MHz

µs

startup time from STANDBY (LPO BIAS_EN

High for at least 900ms)

cold startup time

900

150

180

100

µs

µA

kHz

µs

ICC, CLK10M and CLK80K active

–40°C to 125°C

LPO - LF oscillator untrimmed frequency

36

85

startup time from STANDBY (LPO BIAS_EN

High for at least 900ms)

cold startup time

2000

27

µs

µA

ICC, only CLK80K active

total ICC STANDBY current

–40°C to 125°C

LPO

20

upper

threshold

lower

threshold

guaranteed fail

guaranteed pass

guaranteed fail

f[MHz]

1.375

4.875

22

78

图 6-8. LPO and Clock Detection, Untrimmed CLK10M

6.7.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a pre-scaled clock signal indicative of an internal device clock.

This output can be externally monitored as a safety diagnostic.

6.7.3 Dual Clock Comparators

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by

counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of

spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the

reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration

allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.

54

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

An additional use of this module is to measure the frequency of a selectable clock source, using the input

clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a

fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width

pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1

does not reach 0 within the counting window generated by counter 0.

6.7.3.1 Features

Takes two different clock sources as input to two independent counter blocks.

•

One of the clock sources is the known-good, or reference clock; the second clock source is the "clock

under test."

•

Each counter block is programmable with initial, or seed values.

The counter blocks start counting down from their seed values at the same time; a mismatch from the

expected frequency for the clock under test generates an error signal which is used to interrupt the

CPU.

6.7.3.2 Mapping of DCC Clock Source Inputs

表 6-16. DCC1 Counter 0 Clock Sources

CLOCK SOURCE [3:0]

CLOCK NAME

oscillator (OSCIN)

high frequency LPO

test clock (TCK)

others

0x5

0xA

表 6-17. DCC1 Counter 1 Clock Sources

KEY [3:0]

CLOCK SOURCE [3:0]

CLOCK NAME

N2HET1[31]

others

—

0x0

Main PLL free-running clock output

0x1

0x2

low frequency LPO

high frequency LPO

flash HD pump oscillator

EXTCLKIN1

0xA

0x3

0x4

0x5

0x6

0x7

ring oscillator

VCLK

0x8 - 0xF

表 6-18. DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0]

CLOCK NAME

oscillator (OSCIN)

test clock (TCK)

others

0xA

表 6-19. DCC2 Counter 1 Clock Sources

KEY [3:0]

others

0xA

CLOCK SOURCE [3:0]

CLOCK NAME

N2HET2[0]

Reserved

VCLK

—

00x0 - 0x7

0x8 - 0xF

System Information and Electrical Specifications

55

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.8 Glitch Filters

A glitch filter is present on the following signals.

表 6-20. Glitch Filter Timing Specifications

PARAMETER

TMS5703137CGWTQEP

TMS5703137CGWTMEP

UNIT

MIN

TYP

MAX

MIN

MAX

tf(nPORRST)

500

2000

475

2000

ns

Filter time nPORRST pin;

pulses less than MIN will be filtered out,

pulses greater than MAX will generate a

reset⁽¹⁾

tf(nRST)

tf(TEST)

475

500

2000

450

475

2000

ns

Filter time nRST pin;

pulses less than MIN will be filtered out,

pulses greater than MAX will generate a

reset

Filter time TEST pin;

pulses less than MIN will be filtered out,

pulses greater than MAX will pass through

(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,

I/O pins, etc.) without also generating a valid reset signal to the CPU.

56

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.9 Device Memory Map

6.9.1 Memory Map Diagram

The figure below shows the device memory map.

0xFFFFFFFF

SYSTEM Modules

0xFFF80000

Peripherals - Frame 1

0xFF000000

0xFE000000

CRC

RESERVED

0xFCFFFFFF

0xFC000000

Peripherals - Frame 2

RESERVED

0xF07FFFFF

Flash Module Bus2 Interface

(Flash ECC, OTP and EEPROM accesses)

0xF0000000

RESERVED

0x87FFFFFF

0x80000000

EMIF (128MB)

SDRAM

CS0

RESERVED

reserved

CS4

0x6FFFFFFF

0x60000000

0x6C000000

0x68000000

0x64000000

EMIF (16MB * 3)

Async RAM

CS3

CS2

RESERVED

0x202FFFFF

0x20000000

Flash (3MB) (Mirrored Image)

RESERVED

0x0843FFFF

0x08400000

RAM - ECC

RESERVED

0x0803FFFF

0x08000000

RAM (256KB)

RESERVED

Flash (3MB)

0x002FFFFF

0x00000000

图 6-9. Memory Map

The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash

image is 0x2000 0000.

System Information and Electrical Specifications

57

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.9.2 Memory Map Table

表 6-21. Device Memory Map

FRAME ADDRESS RANGE

START END

Memories Tightly Coupled to the ARM Cortex-R4F CPU

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

SIZE L SIZE

MODULE NAME

TCM Flash

CS0

0x0000_0000

0x00FF_FFFF

16MB

3MB

TCM RAM + RAM

ECC

CSRAM0

0x0800_0000

0x0BFF_FFFF

64MB

KB

Abort

Flash mirror

frame

Mirrored Flash

0x2000_0000

0x20FF_FFFF

16MB

MB

External Memory Accesses

EMIF Chip Select

2 (asynchronous)

EMIF select 2

EMIF select 3

EMIF select 4

EMIF select 0

0x6000_0000

0x6400_0000

0x6800_0000

0x8000_0000

0x63FF_FFFF

0x67FF_FFFF

0x6BFF_FFFF

0x87FF_FFFF

64MB

16MB

EMIF Chip Select

3 (asynchronous)

64MB

Access to "Reserved" space will

generate Abort

EMIF Chip Select

4 (asynchronous)

EMIF Chip Select

0 (synchronous)

128MB 128MB

Flash Module Bus2 Interface

Customer OTP,

TCM Flash Bank

0

0xF000_0000

0xF000_1FFF

8KB

4KB

Customer OTP,

TCM Flash Bank

1

0xF000_2000

0xF000_E000

0xF004_0000

0xF000_3FFF

0xF000_FFFF

0xF004_03FF

8KB

1KB

4KB

Customer OTP,

EEPROM Bank 7

Customer

OTP–ECC, TCM

Flash Bank 0

512B

Customer

OTP–ECC, TCM

Flash Bank 1

0xF004_0400

0xF004_1C00

0xF004_07FF

0xF004_1FFF

1KB

512B

1KB

Customer

OTP–ECC,

EEPROM Bank 7

TI OTP, TCM

Flash Bank 0

0xF008_0000

0xF008_2000

0xF008_E000

0xF008_1FFF

0xF008_3FFF

0xF008_FFFF

8KB

4KB

Abort

TI OTP, TCM

Flash Bank 1

TI OTP, EEPROM

Bank 7

TI OTP–ECC,

TCM Flash Bank

0

0xF00C_0000

0xF00C_03FF

1KB

512B

TI OTP–ECC,

TCM Flash Bank

1

0xF00C_0400

0xF00C_1C00

0xF00C_07FF

0xF00C_1FFF

1KB

512B

1KB

TI OTP–ECC,

EEPROM Bank 7

EEPROM

Bank–ECC

0xF010_0000

0xF020_0000

0xF040_0000

0xF013_FFFF

0xF03F_FFFF

0xF04F_FFFF

256KB

2MB

8KB

64KB

384KB

EEPROM Bank

Flash Data Space

ECC

1MB

58

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-21. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

L SIZE

START

END

EMIF Slave Interfaces

CPPI Memory

Slave (Ethernet

RAM)

0xFC52_0000

0xFCF7_8000

0xFC52_1FFF

0xFCF7_87FF

8KB

2KB

8KB

2KB

Abort

EMAC Slave

(Ethernet Slave)

No error

EMACSS

Wrapper

(Ethernet

Wrapper)

0xFCF7_8800

0xFCF7_88FF

256B

No error

Ethernet MDIO

Interface

0xFCF7_8900

0xFCFF_E800

0xFCF7_89FF

0xFCFF_E8FF

256B

No error

Abort

EMIF Registers

Cyclic Redundancy Checker (CRC) Module Registers

CRC

CRC frame

0xFE00_0000

0xFEFF_FFFF

Peripheral Memories

0xFF0B_FFFF

16MB

512B

Accesses above 0x200 generate abort.

MIBSPI5 RAM

MIBSPI3 RAM

MIBSPI1 RAM

PCS[5]

PCS[6]

PCS[7]

0xFF0A_0000

0xFF0C_0000

0xFF0E_0000

128KB

2KB

Abort for accesses above 2KB

0xFF0D_FFFF

0xFF0F_FFFF

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

DCAN3 RAM

DCAN2 RAM

DCAN1 RAM

MIBADC2 RAM

MIBADC1 RAM

N2HET2 RAM

N2HET1 RAM

PCS[13]

PCS[14]

PCS[15]

PCS[29]

PCS[31]

PCS[34]

0xFF1A_0000

0xFF1C_0000

0xFF1E_0000

0xFF3A_0000

0xFF3E_0000

0xFF44_0000

0xFF1B_FFFF

0xFF1D_FFFF

0xFF1F_FFFF

0xFF3B_FFFF

0xFF3F_FFFF

0xFF45_FFFF

0xFF47_FFFF

128KB

2KB

8KB

16KB

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

Wrap around for accesses to

unimplemented address offsets lower

than 0x7FF. Abort generated for

accesses beyond offset 0x800.

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

Wrap around for accesses to

unimplemented address offsets lower

than 0x1FFF. Abort generated for

accesses beyond 0x1FFF.

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

Wrap around for accesses to

unimplemented address offsets lower

than 0x3FFF. Abort generated for

accesses beyond 0x3FFF.

PCS[35]

PCS[38]

0xFF46_0000

0xFF4C_0000

128KB

16KB

1KB

N2HET2 TU2

RAM

0xFF4D_FFFF

0xFF4F_FFFF

Abort

N2HET1 TU1

RAM

PCS[39]

PCS[40]

0xFF4E_0000

0xFF50_0000

128KB

1KB

Abort

FlexRay TU RAM

0xFF51_FFFF

Debug Components

CoreSight Debug

ROM

CSCS0

0xFFA0_0000

0xFFA0_0FFF

4KB

Reads: 0, writes: no effect

System Information and Electrical Specifications

59

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-21. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

L SIZE

START

END

Cortex-R4F

Debug

CSCS1

0xFFA0_1000

0xFFA0_1FFF

4KB

Reads: 0, writes: no effect

ETM-R4

CoreSight TPIU

POM

CSCS2

CSCS3

CSCS4

0xFFA0_2000

0xFFA0_3000

0xFFA0_4000

0xFFA0_2FFF

0xFFA0_3FFF

0xFFA0_4FFF

4KB

Reads: 0, writes: no effect

Abort

Peripheral Control Registers

0xFFF7_A400 256B

HTU1

HTU2

PS[22]

PS[17]

PS[16]

PS[15]

PS[12]+PS[13]

PS[10]

PS[8]

0xFFF7_A4FF

0xFFF7_A5FF

0xFFF7_B8FF

0xFFF7_B9FF

0xFFF7_BCFF

0xFFF7_C1FF

0xFFF7_C3FF

0xFFF7_CFFF

0xFFF7_D4FF

0xFFF7_DDFF

0xFFF7_DFFF

0xFFF7_E1FF

0xFFF7_E4FF

0xFFF7_E5FF

0xFFF7_F5FF

0xFFF7_F7FF

0xFFF7_F9FF

0xFFF7_FBFF

0xFFF7_FDFF

256B

512B

2KB

Reads: 0, writes: no effect

0xFFF7_A500

0xFFF7_B800

0xFFF7_B900

0xFFF7_BC00

0xFFF7_C000

0xFFF7_C200

0xFFF7_C800

0xFFF7_D400

0xFFF7_DC00

0xFFF7_DE00

0xFFF7_E000

0xFFF7_E400

0xFFF7_E500

0xFFF7_F400

0xFFF7_F600

0xFFF7_F800

0xFFF7_FA00

0xFFF7_FC00

256B

512B

2KB

N2HET1

N2HET2

GPIO

MIBADC1

MIBADC2

FlexRay

I2C

256B

512B

256B

512B

256B

512B

256B

512B

DCAN1

DCAN2

DCAN3

LIN

PS[8]

PS[7]

PS[6]

SCI

PS[6]

MibSPI1

SPI2

PS[2]

MibSPI3

SPI4

PS[1]

MibSPI5

PS[0]

System Modules Control Registers and Memories

DMA RAM

VIM RAM

PPCS0

PPCS2

0xFFF8_0000

0xFFF8_0FFF

4KB

Abort

Wrap around for accesses to

unimplemented address offsets

between 1kB and 4kB.

0xFFF8_2000

0xFFF8_2FFF

4KB

1KB

RTP RAM

Flash Module

eFuse Controller

PPCS3

PPCS7

PPCS12

0xFFF8_3000

0xFFF8_7000

0xFFF8_C000

0xFFF8_3FFF

0xFFF8_7FFF

0xFFF8_CFFF

4KB

Abort

Power

Management

Module (PMM)

PPSE0

0xFFFF_0000

0xFFFF_01FF

512B

Abort

Test Controller

(FMTM)

PPSE1

PPS0

0xFFFF_0400

0xFFFF_E000

0xFFFF_07FF

0xFFFF_E0FF

1KB

Reads: 0, writes: no effect

PCR registers

256B

System Module -

Frame 2 (see

device TRM)

PPS0

0xFFFF_E100

0xFFFF_E1FF

256B

Reads: 0, writes: no effect

PBIST

PPS1

0xFFFF_E400

0xFFFF_E600

0xFFFF_E5FF

0xFFFF_E6FF

512B

256B

512B

256B

Generates address error interrupt, if

enabled

STC

IOMM

Multiplexing

Control Module

PPS2

PPS3

0xFFFF_EA00

0xFFFF_EC00

0xFFFF_EBFF

0xFFFF_ECFF

512B

256B

512B

256B

Reads: 0, writes: no effect

DCC1

60

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-21. Device Memory Map (continued)

FRAME ADDRESS RANGE

RESPONSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

L SIZE

START

END

DMA

DCC2

PPS4

PPS5

PPS6

PPS7

0xFFFF_F000

0xFFFF_F400

0xFFFF_F500

0xFFFF_F600

0xFFFF_F700

0xFFFF_F800

0xFFFF_F900

0xFFFF_FC00

0xFFFF_FD00

0xFFFF_FE00

0xFFFF_F3FF

0xFFFF_F4FF

0xFFFF_F5FF

0xFFFF_F6FF

0xFFFF_F7FF

0xFFFF_F8FF

0xFFFF_F9FF

0xFFFF_FCFF

0xFFFF_FDFF

0xFFFF_FEFF

1KB

256B

1KB

256B

Reads: 0, writes: no effect

ESM

CCMR4

DMM

RAM ECC even

RAM ECC odd

RTI + DWWD

VIM Parity

VIM

System Module -

Frame 1 (see

device TRM)

PPS7

0xFFFF_FF00

0xFFFF_FFFF

256B

Reads: 0, writes: no effect

System Information and Electrical Specifications

61

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.9.3 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module

that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed

in the "MASTERS" column can access that slave module.

表 6-22. Master / Slave Access Matrix

SLAVES ON MAIN SCR

Flash Module

Bus2 Interface:

OTP, ECC,

Non-CPU

Accesses to

Program Flash and

CPU Data RAM

Peripheral Control Registers,

All Peripheral Memories, and

All System Module Control

Registers and Memories

MASTERS

ACCESS MODE

Slave

Interfaces

CRC

EEPROM Bank

CPU READ

CPU WRITE

DMA

User/Privilege

User

Yes

No

Yes

No

POM

User

DAP

Privilege

HTU1

HTU2

No

6.9.3.1 Special Notes on Accesses to Certain Slaves

Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU

(master id = 1). The other masters can only read from these registers.

A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.

The device contains dedicated logic to generate a bus error response on any access to a module that is in

a power domain that has been turned OFF.

62

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.9.4 POM Overlay Considerations

•

The POM overlay can map onto up to 8MB of the internal or external memory space. The starting

address and the size of the memory overlay are configurable via the POM module control registers.

Care must be taken to ensure that the overlay is mapped on to available memory.

•

ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors

will be generated.

POM overlay must not be enabled when the flash and internal RAM memories are swapped via the

MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).

When POM is used to overlay the flash onto internal or external RAM, there is a bus contention

possibility when another master accesses the TCM flash. This results in a system hang.

–

The POM module implements a timeout feature to detect this exact scenario. The timeout needs to

be enabled whenever POM overlay is enabled.

The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global

Control register (POMGLBCTRL, address = 0xFFA04000).

In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)

flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is

generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a

data fetch.

–

The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module

is set. If so, then the application can assume that the timeout is caused by a bus contention

between the POM transaction and another master accessing the same memory region. The abort

handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been

caused due to a timeout from the POM.

System Information and Electrical Specifications

63

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.10 Flash Memory

6.10.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a

customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense

amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical

construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or

erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

表 6-23. Flash Memory Banks and Sectors

Memory Arrays (or Banks)⁽¹⁾

Sector

No.

Segment

Low Address

High Address

BANK0 (1.5MBytes)

0

1

32K Bytes

128K Bytes

16K Bytes

0x0000_0000

0x0000_8000

0x0001_0000

0x0001_8000

0x0002_0000

0x0004_0000

0x0006_0000

0x0008_0000

0x000A_0000

0x000C_0000

0x000E_0000

0x0010_0000

0x0012_0000

0x0014_0000

0x0016_0000

0x0018_0000

0x001A_0000

0x001C_0000

0x001E_0000

0x0020_0000

0x0022_0000

0x0024_0000

0x0026_0000

0x0028_0000

0x002A_0000

0x002C_0000

0x002E_0000

0xF020_0000

0xF020_4000

0xF020_8000

0xF020_C000

0x0000_7FFF

0x0000_FFFF

0x0001_7FFF

0x0001_FFFF

0x0003_FFFF

0x0005_FFFF

0x0007_FFFF

0x0009_FFFF

0x000B_FFFF

0x000D_FFFF

0x000F_FFFF

0x0011_FFFF

0x0013_FFFF

0x0015_FFFF

0x0017_FFFF

0x0019_FFFF

0x001B_FFFF

0x001D_FFFF

0x001F_FFFF

0x0021_FFFF

0x0023_FFFF

0x0025_FFFF

0x0027_FFFF

0x0029_FFFF

0x002B_FFFF

0x002D_FFFF

0x002F_FFFF

0xF020_3FFF

0xF020_7FFF

0xF020_BFFF

0xF020_FFFF

2

3

4

5

6

7

8

9

10

11

12

13

14

0

BANK1 (1.5MBytes)

1

2

3

4

5

6

7

8

9

10

11

0

BANK7 (64kBytes) for EEPROM emulation⁽²⁾⁽³⁾

1

2

3

(1) The Flash banks are 144-bit wide bank with ECC support.

(2) The flash bank7 can be programmed while executing code from flash bank0 or bank1.

(3) Code execution is not allowed from flash bank7.

64

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.10.2 Main Features of Flash Module

•

Support for multiple flash banks for program and/or data storage

Simultaneous read access on a bank while performing program or erase operation on any other bank

Integrated state machines to automate flash erase and program operations

Software interface for flash program and erase operations

Pipelined mode operation to improve instruction access interface bandwidth

Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU

–

Error address is captured for host system debugging

•

Support for a rich set of diagnostic features

6.10.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection

(SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of

instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on

the 64 bits received and compares it with the ECC code returned by the flash module. A signle-bit error is

corrected and flagged by the CPU, while a multi-bit error is only flagged. The CPU signals an ECC error

via its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the

"X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0

ORR r1, r1, #0x00000010

MCR p15,#0,r1,c9,c12,#0

MRC p15,#0,r1,c9,c12,#0

;Enabling Event monitor states

;Set 4th bit (‘X’) of PMNC register

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM

and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC

checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN

bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1

ORR r1, r1, #0x0e000000

DMB

;Enable ECC checking for ATCM and BTCMs

MCR p15, #0, r1, c1, c0, #1

6.10.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, refer to 节 5.8.

6.10.5 Flash Program and Erase Timings for Program Flash

表 6-24. Timing Specifications for Program Flash

MIN

NOM

MAX

300

32

UNIT

t_prog(144 bit)

t_prog(Total)

Wide Word (144 bit) programming time

3MByte programming time⁽¹⁾

40

µs

s

-40°C to 125°C

0°C to 60°C, for first

25 cycles

8

16

s

t_erase

Sector/Bank erase time⁽²⁾

-40°C to 125°C

0.03

16

4

s

0°C to 60°C, for first

25 cycles

100

ms

t_wec

t_ret

Write/erase cycles

Data retention⁽³⁾

-40°C to 125°C

125°C

1000

5

cycles

years

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase

a sector.

(3) The data retention specification is based on process qualification testing at 250°C for 168 hours and using an Arrhenius model with

activation energy of 0.8 eV.

System Information and Electrical Specifications

65

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.10.6 Flash Program and Erase Timings for Data Flash

表 6-25. Timing Specifications for Data Flash

MIN

NOM

MAX

UNIT

µs

t_prog(144 bit)

t_prog(Total)

Wide Word (144 bit) programming time

64KB programming time⁽¹⁾

40

300

660

330

-40°C to 125°C

ms

0°C to 60°C, for first

25 cycles

165

ms

t_erase

Sector/Bank erase time⁽²⁾

--40°C to 125°C

0.2

14

8

s

0°C to 60°C, for first

25 cycles

100

ms

t_wec

t_ret

Write/erase cycles

Data retention⁽³⁾

-40°C to 125°C

125°C

100000

5

cycles

years

(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes

programming 144 bits at a time at the maximum specified operating frequency.

(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase

a sector.

(3) The data retention specification is based on process qualification testing at 250°C for 168 hours and using an Arrhenius model with

activation energy of 0.8 eV.

66

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.11 Tightly-Coupled RAM Interface Module

图 6-10 illustrates the connection of the tightly coupled RAM (TCRAM) to the Cortex-R4F CPU.

VBUSP I/F PMT I/F

36 Bit

Upper 32 bits data &

4 ECC bits

wide

RAM

Cortex R4F™

EVEN Address

TCM BUS

TCRAM

B0

TCM

36 Bit

Interface 1

wide

RAM

64 Bit data bus

RAM

Lower32 bits data &

4 ECC bits

A

TCM

36 Bit

36 Bwitide

wideRAM

RAM

Upper 32 bits data &

4 ECC bits

wide

B1

TCM

ODD Address

TCM BUS

TCRAM

Interface 2

36 Bit

64 Bit data bus

36 Bit

wide

RAM

Lower32 bits data &

4 ECC bits

VBUSP I/F PMT I/F

图 6-10. TCRAM Block Diagram

6.11.1 Features

The features of the Tightly Coupled RAM (TCRAM) Module are:

•

Acts as slave to the Cortex-R4F CPU's BTCM interface

Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code

Monitors CPU Event Bus and generates single or multi-bit error interrupts

Stores addresses for single and multi-bit errors

Supports RAM trace module

Provides CPU address bus integrity checking by supporting parity checking on the address bus

Performs redundant address decoding for the RAM bank chip select and ECC select generation logic

Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved

RAM banks and generating independent RAM access control signals to the two banks

•

Supports auto-initialization of the RAM banks along with the ECC bits

No support for bit-wise RAM accesses

6.11.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also

stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The

TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and

also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC

checking for the RAM accesses must be enabled inside the CPU.

For more information see the device specific technical reference manual.

6.12 Parity Protection for Peripheral RAMs

Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is

calculated based on the data read from the peripheral RAM and compared with the good parity value

stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a

parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral

RAM address that caused the parity error.

System Information and Electrical Specifications

67

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the

application. Each individual peripheral contains control registers to enable the parity protection for

accesses to its RAM.

注

The CPU read access gets the actual data from the peripheral. The application can choose

to generate an interrupt whenever a peripheral RAM parity error is detected.

68

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.13 On-Chip SRAM Initialization and Testing

6.13.1 On-Chip SRAM Self-Test Using PBIST

6.13.1.1 Features

•

Extensive instruction set to support various memory test algorithms

ROM-based algorithms allow application to run TI production-level memory tests

Independent testing of all on-chip SRAM

6.13.1.2 PBIST RAM Groups

表 6-26. PBIST RAM Grouping

Test Pattern (Algorithm)

March 13N⁽¹⁾

two port

(cycles)

March 13N⁽¹⁾

single port

(cycles)

triple read

slow read

triple read

fast read

Memory

RAM Group

Test Clock

MEM Type

ALGO MASK

0x1

ALGO MASK

0x2

ALGO MASK

0x4

ALGO MASK

0x8

PBIST_ROM

STC_ROM

DCAN1

DCAN2

DCAN3

ESRAM1

MIBSPI1

MIBSPI3

MIBSPI5

VIM

1

ROM CLK

VCLK

HCLK

VCLK

HCLK

VCLK

HCLK

VCLK

ROM

24578

19586

8194

6530

2

ROM

3

Dual Port

Single Port

Dual Port

Single Port

Dual Port

Single Port

25200

4

5

6

266280

7

33440

12560

4200

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

28

MIBADC1

DMA

18960

31680

6480

N2HET1

HET TU1

RTP

37800

75400

FLEXRAY

133160

MIBADC2

N2HET2

HET TU2

ESRAM5

ESRAM6

VCLK

HCLK

4200

31680

6480

266280

8700

6360

Dual Port

ETHERNET

ESRAM8

VCLK3

HCLK

Single Port

133160

266280

(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for

application testing.

The PBIST ROM clock frequency is limited to 90MHz, if 90MHz < HCLK ≤ HCLKmax, or HCLK, if HCLK ≤

90MHz.

The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV

field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

System Information and Electrical Specifications

69

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.13.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized to zero via the Memory

Hardware Initialization mechanism in the System module. This hardware mechanism allows an application

to program the memory arrays with error detection capability to a known state based on their error

detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects

the memories that are to be initialized.

For more information on these registers see the device specific technical reference manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in

表 6-27.

表 6-27. Memory Initialization

ADDRESS RANGE

CONNECTING MODULE

MSINENA REGISTER BIT #

BASE ADDRESS

0x08000000

0x08010000

0x08020000

0xFF0A0000

0xFF0C0000

0xFF0E0000

0xFF1A0000

0xFF1C0000

0xFF1E0000

ENDING ADDRESS

0x0800FFFF

0x0801FFFF

0x0802FFFF

0xFF0BFFFF

0xFF0DFFFF

0xFF0FFFFF

0xFF1BFFFF

0xFF1DFFFF

0xFF1FFFFF

RAM (PD#1)

RAM (RAM_PD#1)

RAM (RAM_PD#2)

MIBSPI5 RAM

MIBSPI3 RAM

MIBSPI1 RAM

DCAN3 RAM

DCAN2 RAM

DCAN1 RAM

FlexRay RAM

MIBADC2 RAM

MIBADC1 RAM

N2HET2 RAM

N2HET1 RAM

HET TU2 RAM

HET TU1 RAM

DMA RAM

0⁽¹⁾

12⁽²⁾

11⁽²⁾

7⁽²⁾

10

6

5

RAM is not CPU-Addressable

n/a⁽³⁾

14

8

0xFF3A0000

0xFF3E0000

0xFF440000

0xFF460000

0xFF4C0000

0xFF4E0000

0xFFF80000

0xFFF82000

0xFFF83000

0xFF500000

0xFF3BFFFF

0xFF3FFFFF

0xFF57FFFF

0xFF47FFFF

0xFF4DFFFF

0xFF4FFFFF

0xFFF80FFF

0xFFF82FFF

0xFFF83FFF

0xFF51FFFF

15

3

16

4

1

VIM RAM

2

RTP RAM

n/a

13

FlexRay TU RAM

Ethernet RAM (CPPI Memory

Slave)

0xFC520000

0xFC521FFF

n/a

(1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized.

(2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset

via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system

module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (i) The

module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG

register to become cleared (zero)

(3) Reserved only. The FlexRay RAM has its own initialization mechanism.

70

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.14 External Memory Interface (EMIF)

6.14.1 Features

The EMIF includes many features to enhance the ease and flexibility of connecting to external

asynchronous memories or SDRAM devices. The EMIF features includes support for:

•

3 addressable chip select for asynchronous memories of up to 16MB each

1 addressable chip select space for SDRAMs up to 128MB

8 or 16-bit data bus width

Programmable cycle timings such as setup, strobe, and hold times as well as turnaround time

Select strobe mode

Extended Wait mode

Data bus parking

6.14.2 Electrical and Timing Specifications

6.14.2.1 Asynchronous RAM

3

1

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_nDQM[1:0]

4

8

5

9

6

7

29

30

10

EMIF_nOE

13

12

EMIF_DATA[15:0]

EMIF_nWE

图 6-11. Asynchronous Memory Read Timing

System Information and Electrical Specifications

71

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Extended Due to EMIF_WAIT

SETUP

STROBE

STROBE HOLD

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

14

11

EMIF_nOE

EMIF_WAIT

2

Asserted

Deasserted

图 6-12. EMIFnWAIT Read Timing Requirements

15

1

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_nDQM[1:0]

16

17

19

21

23

18

20

22

24

EMIF_nWE

27

26

EMIF_DATA[15:0]

EMIF_nOE

图 6-13. Asynchronous Memory Write Timing

72

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

Extended Due to EMIF_WAIT

SETUP

STROBE

STROBE HOLD

EMIF_nCS[3:2]

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

28

25

EMIF_nWE

EMIF_WAIT

2

Asserted

Deasserted

图 6-14. EMIFnWAIT Write Timing Requirements

表 6-28. EMIF Asynchronous Memory Timing Requirements

NO.

MIN

NOM

MAX

UNIT

Reads and Writes

E

EMIF clock period

ns

2

t_{w(EM_WAIT)}

Pulse duration, EMIFnWAIT assertion and

deassertion

2E

Reads

12

13

14

t_{su(EMDV-EMOEH)}

t_{h(EMOEH-EMDIV)}

t_{su(EMOEL-EMWAIT)}

Setup time, EMIFDATA[15:0] valid before EMIFnOE

high

30

0.5

ns

Hold time, EMIFDATA[15:0] valid after EMIFnOE

high

Setup Time, EMIFnWAIT asserted before end of

Strobe Phase⁽¹⁾

4E+30

Writes

28

t_{su(EMWEL-EMWAIT)}

Setup Time, EMIFnWAIT asserted before end of

Strobe Phase⁽¹⁾

4E+30

ns

(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure 图 6-12 and Figure 图 6-14 describe EMIF transactions that include extended wait states inserted during the

STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start

of where the HOLD phase would begin if there were no extended wait cycles.

表 6-29. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)

NO.

PARAMETER

MIN

NOM

MAX

UNIT

Reads and Writes

(TA) × E - 4

1

t_{d(TURNAROUND)}

Turn around time

(TA) × E

(TA) × E + 3

ns

Reads

(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle

Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],

WH[8–1], and MEWC[1–256]. See the for more information.

(2) E = EMIF_CLK period in ns.

(3) EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note

that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See

the for more information.

System Information and Electrical Specifications

73

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-29. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)(continued)

NO.

PARAMETER

EMIF read cycle time (EW = 0)

MIN

(RS+RST+RH) (RS+RST+RH) (RS+RST+RH)

× E -3 × E × E + 3

NOM

MAX

UNIT

3

t_c(EMRCYCLE)

ns

EMIF read cycle time (EW = 1)

(RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+(

EWC × 16)) × E EWC × 16)) × E EWC × 16)) × E

ns

-3

+ 3

4

5

t_{su(EMCEL-EMOEL)}

Output setup time,

EMIFnCS[4:2] low to EMIFnOE

low (SS = 0)

(RS) × E-4

(RS) × E

0

(RS) × E+3

Output setup time,

-3

+3

EMIFnCS[4:2] low to EMIFnOE

low (SS = 1)

t_{h(EMOEH-EMCEH)}

Output hold time, EMIFnOE high

to EMIFnCS[4:2] high (SS = 0)

(RH) × E -4

-3

(RH) × E

0

(RH) × E + 3

+3

ns

Output hold time, EMIFnOE high

to EMIFnCS[4:2] high (SS = 1)

6

7

8

t_{su(EMBAV-EMOEL)}

t_{h(EMOEH-EMBAIV)}

t_{su(EMAV-EMOEL)}

Output setup time, EMIFBA[1:0]

valid to EMIFnOE low

(RS) × E-4

(RH) × E-4

(RS) × E-4

(RS) × E

(RH) × E

(RS) × E

(RS) × E+3

(RH) × E+3

(RS) × E+3

Output hold time, EMIFnOE high

to EMIFBA[1:0] invalid

Output setup time,

EMIFADDR[21:0] valid to

EMIFnOE low

9

t_{h(EMOEH-EMAIV)}

t_w(EMOEL)

Output hold time, EMIFnOE high

to EMIFADDR[21:0] invalid

(RH) × E-4

(RH) × E

(RH) × E+3

ns

10

EMIFnOE active low width (EW

= 0)

(RST) × E-3

(RST) × E

(RST) × E+3

EMIFnOE active low width (EW

= 1)

(RST+(EWC ×

16)) × E-3

(RST+(EWC ×

16)) × E

(RST+(EWC ×

16)) × E+3

11

29

t_{d(EMWAITH-EMOEH)}

t_{su(EMDQMV-EMOEL)}

Delay time from EMIFnWAIT

deasserted to EMIFnOE high

3E-3

4E

4E+30

Output setup time,

EMIFnDQM[1:0] valid to

EMIFnOE low

(RS) × E-4

(RS) × E

(RS) × E+3

30

15

t_{h(EMOEH-EMDQMIV)}

Output hold time, EMIFnOE high

to EMIFnDQM[1:0] invalid

(RH) × E-4

(RH) × E

(RH) × E+3

ns

Writes

(WS+WST+WH (WS+WST+WH (WS+WST+WH

) × E-3 ) × E ) × E+3

(WS+WST+WH (WS+WST+WH (WS+WST+WH

t_c(EMWCYCLE)

EMIF write cycle time (EW = 0)

EMIF write cycle time (EW = 1)

ns

+( EWC × 16))

× E -3

+(E WC × 16))

× E

+( EWC × 16))

× E + 3

16

17

t_{su(EMCEL-EMWEL)}

Output setup time,

EMIFnCS[4:2] low to EMIFnWE

low (SS = 0)

(WS) × E -4

(WS) × E

(WS) × E + 3

ns

Output setup time,

EMIFnCS[4:2] low to EMIFnWE

low (SS = 1)

-4

(WH) × E-4

-4

0

(WH) × E

0

+3

(WH) × E+3

+3

t_{h(EMWEH-EMCEH)}

Output hold time, EMIFnWE

high to EMIFnCS[4:2] high (SS =

0)

Output hold time, EMIFnWE

high to EMIFCS[4:2] high (SS =

1)

18

19

t_{su(EMDQMV-EMWEL)}

t_{h(EMWEH-EMDQMIV)}

Output setup time, EMIFBA[1:0]

valid to EMIFnWE low

(WS) × E-4

(WH) × E-4

(WS) × E

(WH) × E

(WS) × E+3

(WH) × E+3

ns

Output hold time, EMIFnWE

high to EMIFBA[1:0] invalid

74

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-29. EMIF Asynchronous Memory Switching Characteristics^(1)(2)(3)(continued)

NO.

PARAMETER

MIN

NOM

MAX

UNIT

20

21

22

t_{su(EMBAV-EMWEL)}

t_{h(EMWEH-EMBAIV)}

t_{su(EMAV-EMWEL)}

Output setup time, EMIFBA[1:0]

valid to EMIFnWE low

(WS) × E-4

(WS) × E

(WS) × E+3

ns

Output hold time, EMIFnWE

high to EMIFBA[1:0] invalid

(WH) × E-4

(WS) × E-4

(WH) × E

(WS) × E

(WH) × E+3

(WS) × E+3

ns

Output setup time,

EMIFADDR[21:0] valid to

EMIFnWE low

23

24

t_{h(EMWEH-EMAIV)}

t_w(EMWEL)

Output hold time, EMIFnWE

high to EMIFADDR[21:0] invalid

(WH) × E-4

(WH) × E

(WH) × E+3

ns

EMIFnWE active low width (EW

= 0)

(WST) × E-3

(WST) × E

(WST) × E+3

EMIFnWE active low width (EW

= 1)

(WST+(EWC × (WST+(EWC × (WST+(EWC ×

16)) × E-3

16)) × E

16)) × E+3

25

26

t_{d(EMWAITH-EMWEH)}

t_{su(EMDV-EMWEL)}

Delay time from EMIFnWAIT

deasserted to EMIFnWE high

3E-4

4E

4E+30

Output setup time,

EMIFDATA[15:0] valid to

EMIFnWE low

(WS) × E-4

(WS) × E

(WS) × E+3

27

31

t_{h(EMWEH-EMDIV)}

Output hold time, EMIFnWE

high to EMIFDATA[15:0] invalid

(WH) × E-4

(WH) × E

(WH) × E+3

ns

t_{su(EMDQMV-EMWEL)}

Output setup time,

EMIFnDQM[1:0] valid to

EMIFnWE low

32

t_{h(EMWEH-EMDQMIV)}

Output hold time, EMIFnWE

(WH) × E-4

(WH) × E

(WH) × E+3

ns

hight to EMIFnDQM[1:0] invalid

6.14.2.2 Synchronous Timing

BASIC SDRAM

1

READ OPERATION

2

EMIF_CLK

4

3

5

7

EMIF_nCS[0]

6

EMIF_nDQM[1:0]

EMIF_BA[1:0]

8

EMIF_ADDR[21:0]

19

20

2 EM_CLK Delay

18

17

EMIF_DATA[15:0]

EMIF_nRAS

11

12

13

14

EMIF_nCAS

EMIF_nWE

图 6-15. Basic SDRAM Read Operation

System Information and Electrical Specifications

75

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1

BASIC SDRAM

WRITE OPERATION

2

EMIF_CLK

EMIF_CS[0]

3

5

7

9

4

6

EMIF_DQM[1:0]

EMIF_BA[1:0]

8

EMIF_ADDR[21:0]

10

EMIF_DATA[15:0]

EMIF_nRAS

EMIF_nCAS

EMIF_nWE

11

12

13

15

16

图 6-16. Basic SDRAM Write Operation

表 6-30. EMIF Synchronous Memory Timing Requirements

NO.

PARAMETER

MIN

MAX

UNIT

19

t_{su(EMIFDV-EM_CLKH)}

t_h(CLKH-DIV)

Input setup time, read data valid on EMIFDATA[15:0] before

EMIF_CLK rising

2

ns

20

Input hold time, read data valid on EMIFDATA[15:0] after

EMIF_CLK rising

1.5

ns

表 6-31. EMIF Synchronous Memory Switching Characteristics

NO.

1

PARAMETER

MIN

MAX

UNIT

ns

t_c(CLK)

Cycle time, EMIF clock EMIF_CLK

2

t_w(CLK)

Pulse width, EMIF clock EMIF_CLK high or low

Delay time, EMIF_CLK rising to EMIFnCS[0] valid

Output hold time, EMIF_CLK rising to EMIFnCS[0] invalid

Delay time, EMIF_CLK rising to EMIFnDQM[1:0] valid

Output hold time, EMIF_CLK rising to EMIFnDQM[1:0] invalid

5

1

ns

3

t_d(CLKH-CSV)

t_{oh(CLKH-CSIV)}

t_d(CLKH-DQMV)

t_{oh(CLKH-DQMIV)}

t_d(CLKH-AV)

13

ns

4

ns

5

ns

6

ns

7

Delay time, EMIF_CLK rising to EMIFADDR[21:0] and EMIFBA[1:0]

valid

ns

8

t_oh(CLKH-AIV)

Output hold time, EMIF_CLK rising to EMIFADDR[21:0] and

EMIFBA[1:0] invalid

1

ns

9

t_d(CLKH-DV)

Delay time, EMIF_CLK rising to EMIFDATA[15:0] valid

Output hold time, EMIF_CLK rising to EMIFDATA[15:0] invalid

Delay time, EMIF_CLK rising to EMIFnRAS valid

13

ns

10

11

12

13

t_oh(CLKH-DIV)

t_d(CLKH-RASV)

t_{oh(CLKH-RASIV)}

t_d(CLKH-CASV)

1

Output hold time, EMIF_CLK rising to EMIFnRAS invalid

Delay time, EMIF_CLK rising to EMIFnCAS valid

76

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-31. EMIF Synchronous Memory Switching Characteristics (continued)

NO.

PARAMETER

MIN

MAX

13

UNIT

ns

14

15

16

17

18

t_{oh(CLKH-CASIV)}

Output hold time, EMIF_CLK rising to EMIFnCAS invalid

Delay time, EMIF_CLK rising to EMIFnWE valid

Output hold time, EMIF_CLK rising to EMIFnWE invalid

Delay time, EMIF_CLK rising to EMIFDATA[15:0] tri-stated

Output hold time, EMIF_CLK rising to EMIFDATA[15:0] driving

1

t_d(CLKH-WEV)

t_{oh(CLKH-WEIV)}

t_{dis(CLKH-DHZ)}

t_{ena(CLKH-DLZ)}

ns

1

ns

7

ns

System Information and Electrical Specifications

77

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the

many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow

of program execution. Normally, these events require a timely response from the central processing unit

(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to

an interrupt service routine (ISR).

6.15.1 VIM Features

The VIM module has the following features:

•

Supports 96 interrupt channels.

Provides programmable priority and enable for interrupt request lines.

–

•

Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.

Provides two software dispatch mechanisms when the CPU VIC port is not used.

–

Index interrupt

Register vectored interrupt

•

Parity protected vector interrupt table

6.15.2 Interrupt Request Assignments

表 6-32. Interrupt Request Assignments

Modules

Interrupt Sources

Default VIM Interrupt

Channel

ESM

Reserved

RTI

ESM High level interrupt (NMI)

Reserved

0

1

RTI compare interrupt 0

RTI compare interrupt 1

RTI compare interrupt 2

RTI compare interrupt 3

RTI overflow interrupt 0

RTI overflow interrupt 1

RTI timebase interrupt

GPIO interrupt A

2

RTI

3

RTI

4

RTI

5

RTI

6

RTI

7

RTI

8

GPIO

9

N2HET1

HET TU1

MIBSPI1

LIN

N2HET1 level 0 interrupt

HET TU1 level 0 interrupt

MIBSPI1 level 0 interrupt

LIN level 0 interrupt

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

MIBADC1

DCAN1

SPI2

MIBADC1 event group interrupt

MIBADC1 sw group 1 interrupt

DCAN1 level 0 interrupt

SPI2 level 0 interrupt

FlexRay level 0 interrupt

CRC Interrupt

FlexRay

CRC

ESM

ESM Low level interrupt

Software interrupt (SSI)

PMU Interrupt

SYSTEM

CPU

GPIO

GPIO interrupt B

N2HET1

HET TU1

MIBSPI1

N2HET1 level 1 interrupt

HET TU1 level 1 interrupt

MIBSPI1 level 1 interrupt

78

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-32. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

LIN

MIBADC1

DCAN1

SPI2

LIN level 1 interrupt

MIBADC1 sw group 2 interrupt

DCAN1 level 1 interrupt

SPI2 level 1 interrupt

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67-72

73

74

75

76

77

78

MIBADC1

FlexRay

DMA

MIBADC1 magnitude compare interrupt

FlexRay level 1 interrupt

FTCA interrupt

DMA

LFSA interrupt

DCAN2

DMM

DCAN2 level 0 interrupt

DMM level 0 interrupt

MIBSPI3 level 0 interrupt

MIBSPI3 level 1 interrupt

HBCA interrupt

MIBSPI3

DMA

BTCA interrupt

EMIF

AEMIFINT3

DCAN2

DMM

DCAN2 level 1 interrupt

DMM level 1 interrupt

DCAN1 IF3 interrupt

DCAN1

DCAN3

DCAN2

FPU

DCAN3 level 0 interrupt

DCAN2 IF3 interrupt

"OR" of the six Cortex R4F FPU Exceptions

FlexRay TU Transfer Status interrupt

SPI4 level 0 interrupt

FlexRay TU

SPI4

MIBADC2

FlexRay

MIBSPI5

SPI4

MibADC2 event group interrupt

MibADC2 sw group1 interrupt

FlexRay T0C interrupt

MIBSPI5 level 0 interrupt

SPI4 level 1 interrupt

DCAN3

MIBSPI5

MIBADC2

FlexRay TU

MIBADC2

DCAN3

FMC

DCAN3 level 1 interrupt

MIBSPI5 level 1 interrupt

MibADC2 sw group2 interrupt

FlexRay TU Error interrupt

MibADC2 magnitude compare interrupt

DCAN3 IF3 interrupt

FSM_DONE interrupt

FlexRay

N2HET2

SCI

FlexRay T1C interrupt

N2HET2 level 0 interrupt

SCI level 0 interrupt

HET TU2

I2C

HET TU2 level 0 interrupt

I2C level 0 interrupt

Reserved

N2HET2

SCI

Reserved

N2HET2 level 1 interrupt

SCI level 1 interrupt

HET TU2

Ethernet

HET TU2 level 1 interrupt

C0_MISC_PULSE

C0_TX_PULSE

C0_THRESH_PULSE

System Information and Electrical Specifications

79

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-32. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

Ethernet

HWAG1

HWAG2

DCC1

C0_RX_PULSE

HWA_INT_REQ_H

DCC1 done interrupt

DCC2 done interrupt

Reserved

79

80

81

82

DCC2

83

Reserved

PBIST

84

PBIST_DONE

85

Reserved

HWAG1

HWAG2

Reserved

86

Reserved

87

HWA_INT_REQ_L

Reserved

88

89

90-95

注

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR

entry; therefore only request channels 0..94 can be used and are offset by 1 address in the

VIM RAM.

注

The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"

interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt

condition is indicated as soon as the device is powered up. This can be ignored if the

EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used

in the application, then the external slave memory must always drive the EMIF_nWAIT signal

such that an interrupt is not caused due to the default pull-up on this signal.

注

The lower-order interrupt channels are higher priority channels than the higher-order interrupt

channels.

注

The application can change the mapping of interrupt sources to the interrupt channels via the

interrupt channel control registers (CHANCTRLx) inside the VIM module.

80

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.16 DMA Controller

The DMA controller is used to transfer data between two locations in the memory map in the background

of CPU operations. Typically, the DMA is used to:

•

Transfer blocks of data between external and internal data memories

Restructure portions of internal data memory

Continually service a peripheral

6.16.1 DMA Features

•

CPU independent data transfer

One master port - PortB (64 bits wide) that interfaces to the TMS570 Memory System.

FIFO buffer(4 entries deep and each 64bit wide)

Channel control information is stored in RAM protected by parity

16 channels with individual enable

Channel chaining capability

32 peripheral DMA requests

Hardware and Software DMA requests

8, 16, 32 or 64-bit transactions supported

Multiple addressing modes for source/destination (fixed, increment, offset)

Auto-initiation

Power-management mode

Memory Protection with four configurable memory regions

System Information and Electrical Specifications

81

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.16.2 Default DMA Request Map

The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The

module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By

default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.

Some DMA requests have multiple sources, as shown in 表 6-33. The application must ensure that only

one of these DMA request sources is enabled at any time.

表 6-33. DMA Request Line Connection

Modules

MIBSPI1

DMA Request Sources

MIBSPI1[1]⁽¹⁾

DMA Request

DMAREQ[0]

DMAREQ[1]

DMAREQ[2]

DMAREQ[3]

DMAREQ[4]

DMAREQ[5]

DMAREQ[6]

DMAREQ[7]

DMAREQ[8]

DMAREQ[9]

DMAREQ[10]

DMAREQ[11]

DMAREQ[12]

DMAREQ[13]

DMAREQ[14]

DMAREQ[15]

DMAREQ[16]

DMAREQ[17]

DMAREQ[18]

DMAREQ[19]

DMAREQ[20]

MIBSPI1

MIBSPI1[0]⁽²⁾

SPI2

SPI2 receive

SPI2

SPI2 transmit

MIBSPI1 / MIBSPI3 / DCAN2

DCAN1 / MIBSPI5

MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3

MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2

DCAN1 IF2 / MIBSPI5[2]

MIBADC1 / MIBSPI5

MIBSPI1 / MIBSPI3 / DCAN1

MIBSPI1 / MIBSPI3 / DCAN2

MIBADC1 / I2C / MIBSPI5

RTI / MIBSPI1 / MIBSPI3

MIBSPI3 / MibADC2 / MIBSPI5

MIBSPI3 / MIBSPI5

MIBADC1 event / MIBSPI5[3]

MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1

MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1

MIBADC1 G1 / I2C receive / MIBSPI5[4]

MIBADC1 G2 / I2C transmit / MIBSPI5[5]

RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6]

RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7]

MIBSPI3[1]⁽¹⁾/ MibADC2 event / MIBSPI5[6]

MIBSPI3[0]⁽²⁾/ MIBSPI5[7]

MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2

MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2

RTI / MIBSPI5

MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1

MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2

RTI DMAREQ2 / MIBSPI5[8]

RTI / MIBSPI5

RTI DMAREQ3 / MIBSPI5[9]

N2HET1 / N2HET2 / DCAN3

N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3

IF2

N2HET1 / N2HET2 / DCAN3

N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3

IF3

DMAREQ[21]

MIBSPI1 / MIBSPI3 / MIBSPI5

MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10]

MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11]

DMAREQ[22]

DMAREQ[23]

DMAREQ[24]

N2HET1 / N2HET2 / SPI4 / MIBSPI5

N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4

receive / MIBSPI5[12]

N2HET1 / N2HET2 / SPI4 / MIBSPI5

N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4

transmit / MIBSPI5[13]

DMAREQ[25]

CRC / MIBSPI1 / MIBSPI3

LIN / MIBSPI5

CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12]

CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13]

LIN receive / MIBSPI5[14]

DMAREQ[26]

DMAREQ[27]

DMAREQ[28]

DMAREQ[29]

DMAREQ[30]

LIN / MIBSPI5

LIN transmit / MIBSPI5[15]

MIBSPI1 / MIBSPI3 / SCI / MIBSPI5

MIBSPI1[14] / MIBSPI3[14] / SCI receive /

MIBSPI5[1]⁽¹⁾

MIBSPI1 / MIBSPI3 / SCI / MIBSPI5

MIBSPI1[15] / MIBSPI3[15] / SCI transmit /

MIBSPI5[0]⁽²⁾

DMAREQ[31]

(1) SPI1, SPI3, SPI5 receive in standard SPI mode

(2) SPI1, SPI3, SPI5 transmit in standard SPI mode

82

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.17 Real Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for

benchmarking code. The RTI module can incorporate several counters that define the timebases needed

for scheduling an operating system.

The timers also allow you to benchmark certain areas of code by reading the values of the counters at the

beginning and the end of the desired code range and calculating the difference between the values.

In addition the RTI provides a mechanism to synchronize the operating system to the FlexRay

communication cycle. Clock supervision can detect issues on the FlexRay bus with an automatic switch to

an internally generated timebase.

6.17.1 Features

The RTI module has the following features:

•

Two independent 64 bit counter blocks

Four configurable compares for generating operating system ticks or DMA requests. Each event can

be driven by either counter block 0 or counter block 1.

•

One counter block usable for application synchronization to FlexRay network including clock

supervision

•

Fast enabling/disabling of events

Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.17.2 Block Diagrams

图 6-17 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module.

Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as

time base inputs for the counter block 0.

31

0

Compare

up counter

RTICPUCx

OVLINTx

31

0

=

Up counter

RTIUCx

31

0

RTICLK

To Compare

Unit

Free running counter

RTIFRCx

NTU0

NTU1

NTU2

NTU3

31

0

31

0

Capture

up counter

RTICAUCx

Capture

free running counter

RTICAFRCx

CAP event source 0

CAP event source 1

External

control

图 6-17. Counter Block Diagram

System Information and Electrical Specifications

83

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

31

Update

compare

0

RTIUDCPy

+

31

0

DMAREQy

INTy

Compare

RTICOMPy

From counter

block 0

=

From counter

block 1

Compare

control

图 6-18. Compare Block Diagram

6.17.3 Clock Source Options

The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the

System module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.

For more information on clock sources refer to 表 6-8 and 表 6-13.

6.17.4 Network Time Synchronization Inputs

The RTI module supports 4 Network Time Unit (NTU) inputs that signal internal system events, and which

can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are

connected as shown below.

表 6-34. Network Time Synchronization Inputs

NTU Input

Source

Macrotick

0

1

2

3

Start of Cycle

PLL2 Clock output

EXTCLKIN1 clock input

84

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.18 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller.

The error condition is handled based on a fixed severity level assigned to it. Any severe error condition

can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used

as an indicator to an external monitor circuit to put the system into a safe state.

6.18.1 Features

The features of the Error Signaling Module are:

•

128 interrupt/error channels are supported, divided into 3 different groups

–

64 channels with maskable interrupt and configurable error pin behavior

32 error channels with non-maskable interrupt and predefined error pin behavior

32 channels with predefined error pin behavior only

•

Error pin to signal severe device failure

Configurable timebase for error signal

Error forcing capability

6.18.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order

of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest

severity. The device response to each error is determined by the severity group it is connected to. 表 6-36

shows the channel assignment for each group.

表 6-35. ESM Groups

ERROR GROUP

Group1

INTERRUPT CHARACTERISTICS

maskable, low or high priority

non-maskable, high priority

no interrupt generated

INFLUENCE ON ERROR PIN

configurable

fixed

Group2

Group3

fixed

表 6-36. ESM Channel Assignments

ERROR SOURCES

GROUP

Group1

CHANNELS

Reserved

MibADC2 - parity

DMA - MPU

0

1

2

3

4

5

DMA - parity

Reserved

DMA - imprecise read error

FMC - correctable error: bus1 and bus2 interfaces

(does not include accesses to EEPROM bank)

Group1

6

N2HET1/N2HET2 - parity

HET TU1/HET TU2 - parity

HET TU1/HET TU2 - MPU

PLL - Slip

Group1

7

8

9

10

11

12

13

14

15

16

17

Clock Monitor - interrupt

FlexRay - parity

DMA - imprecise write error

FlexRay TU - parity

VIM RAM - parity

FlexRay TU - MPU

MibSPI1 - parity

System Information and Electrical Specifications

85

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-36. ESM Channel Assignments (continued)

ERROR SOURCES

MibSPI3 - parity

GROUP

Group1

CHANNELS

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

MibADC1 - parity

Reserved

DCAN1 - parity

DCAN3 - parity

DCAN2 - parity

MibSPI5 - parity

Reserved

RAM even bank (B0TCM) - correctable error

CPU - selftest

RAM odd bank (B1TCM) - correctable error

Reserved

DCC1 - error

CCM-R4 - selftest

Reserved

FMC - correctable error (EEPROM bank access)

FMC - uncorrectable error (EEPROM bank access)

IOMM - Mux configuration error

Power domain controller compare error

Power domain controller self-test error

eFuse Controller Error – this error signal is generated when any bit in the eFuse

controller error status register is set. The application can choose to generate an

interrupt whenever this bit is set to service any eFuse controller error conditions.

Group1

40

41

eFuse Controller - Self Test Error. This error signal is generated only when a self

test on the eFuse controller generates an error condition. When an ECC self test

error is detected, group 1 channel 40 error signal will also be set.

PLL2 - Slip

Ethernet Controller master interface

Reserved

Group1

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

Reserved

86

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-36. ESM Channel Assignments (continued)

ERROR SOURCES

DCC2 - error

GROUP

Group1

CHANNELS

62

63

Reserved

Group1

GROUP 2

Reserved

Group2

0

1

CCMR4 - compare

Reserved

2

3

FMC - uncorrectable error (address parity on bus1 accesses)

4

Reserved

5

RAM even bank (B0TCM) - uncorrectable error

6

Reserved

7

RAM odd bank (B1TCM) - uncorrectable error

8

Reserved

9

RAM even bank (B0TCM) - address bus parity error

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Reserved

RAM odd bank (B1TCM) - address bus parity error

Reserved

TCM - ECC live lock detect

Reserved

RTI_WWD_NMI

Reserved

GROUP 3

Reserved

eFuse Controller - autoload error

Reserved

Group3

0

1

2

3

4

5

6

RAM even bank (B0TCM) - ECC uncorrectable error

Reserved

RAM odd bank (B1TCM) - ECC uncorrectable error

Reserved

FMC - uncorrectable error: bus1 and bus2 interfaces

(does not include address parity error and errors on accesses to EEPROM bank)

Group3

7

Reserved

Group3

8

9

10

System Information and Electrical Specifications

87

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-36. ESM Channel Assignments (continued)

ERROR SOURCES

Reserved

GROUP

Group3

CHANNELS

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

88

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.19 Reset / Abort / Error Sources

表 6-37. Reset/Abort/Error Sources

ESM HOOKUP

group.channel

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

CPU TRANSACTIONS

User/Privilege

Precise write error (NCNB/Strongly Ordered)

Precise read error (NCB/Device or Normal)

Imprecise write error (NCB/Device or Normal)

Precise Abort (CPU)

Imprecise Abort (CPU)

n/a

User/Privilege

Undefined Instruction Trap

(CPU)⁽¹⁾

Illegal instruction

User/Privilege

n/a

MPU access violation

User/Privilege

SRAM

Abort (CPU)

B0 TCM (even) ECC single error (correctable)

User/Privilege

ESM

1.26

3.3

Abort (CPU), ESM =>

nERROR

B0 TCM (even) ECC double error (non-correctable)

User/Privilege

B0 TCM (even) uncorrectable error (i.e. redundant address

decode)

ESM => NMI => nERROR

2.6

B0 TCM (even) address bus parity error

User/Privilege

ESM => NMI => nERROR

ESM

2.10

1.28

B1 TCM (odd) ECC single error (correctable)

Abort (CPU), ESM =>

nERROR

B1 TCM (odd) ECC double error (non-correctable)

User/Privilege

3.5

B1 TCM (odd) uncorrectable error (i.e. redundant address

decode)

ESM => NMI => nERROR

2.8

B1 TCM (odd) address bus parity error

User/Privilege

2.12

FLASH

FMC correctable error - Bus1 and Bus2 interfaces (does not

include accesses to EEPROM bank)

User/Privilege

ESM

1.6

3.7

FMC uncorrectable error - Bus1 accesses

(does not include address parity error)

Abort (CPU), ESM =>

nERROR

FMC uncorrectable error - Bus2 accesses

(does not include address parity error and EEPROM bank

accesses)

User/Privilege

ESM => nERROR

3.7

FMC uncorrectable error - address parity error on Bus1

accesses

User/Privilege

ESM => NMI => nERROR

2.4

FMC correctable error - Accesses to EEPROM bank

FMC uncorrectable error - Accesses to EEPROM bank

User/Privilege

ESM

1.35

1.36

DMA TRANSACTIONS

External imprecise error on read (Illegal transaction with ok

response)

User/Privilege

ESM

1.5

External imprecise error on write (Illegal transaction with ok

response)

User/Privilege

1.13

Memory access permission violation

Memory parity error

User/Privilege

ESM

1.2

1.3

DMM TRANSACTIONS

External imprecise error on read (Illegal transaction with ok

response)

User/Privilege

ESM

1.5

External imprecise error on write (Illegal transaction with ok

response)

User/Privilege

1.13

HET TU1 (HTU1)

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

User/Privilege

Interrupt => VIM

ESM

n/a

1.9

(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage

of the CPU.

System Information and Electrical Specifications

89

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 6-37. Reset/Abort/Error Sources (continued)

ESM HOOKUP

group.channel

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

Memory parity error

User/Privilege

ESM

1.8

HET TU2 (HTU2)

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

User/Privilege

N2HET1

Interrupt => VIM

ESM

n/a

1.9

1.8

Memory parity error

ESM

Memory parity error

User/Privilege

N2HET2

ESM

1.7

User/Privilege

FLEXRAY

User/Privilege

FLEXRAY TU

User/Privilege

1.12

NCNB (Strongly Ordered) transaction with slave error response

External imprecise error (Illegal transaction with ok response)

Memory access permission violation

Interrupt => VIM

ESM

n/a

1.16

1.14

Memory parity error

ESM

ETHERNET MASTER INTERFACE

User/Privilege

MIBSPI

Any error reported by slave being accessed

ESM

1.43

MibSPI1 memory parity error

MibSPI3 memory parity error

MibSPI5 memory parity error

User/Privilege

MIBADC

ESM

1.17

1.18

1.24

MibADC1 Memory parity error

MibADC2 Memory parity error

User/Privilege

DCAN

ESM

1.19

1.1

DCAN1 memory parity error

DCAN2 memory parity error

DCAN3 memory parity error

User/Privilege

PLL

ESM

1.21

1.23

1.22

PLL slip error

User/Privilege

CLOCK MONITOR

User/Privilege

DCC

ESM

1.10

1.42

PLL #2 slip error

Clock monitor interrupt

ESM

1.11

DCC1 error

DCC2 error

User/Privilege

CCM-R4

ESM

1.30

1.62

Self test failure

Compare failure

User/Privilege

VIM

ESM

1.31

2.2

ESM => NMI => nERROR

Memory parity error

User/Privilege

VOLTAGE MONITOR

n/a

ESM

Reset

ESM

1.15

n/a

VMON out of voltage range

CPU Selftest (LBIST) error

CPU SELFTEST (LBIST)

User/Privilege

1.27

90

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 6-37. Reset/Abort/Error Sources (continued)

ESM HOOKUP

group.channel

ERROR SOURCE

SYSTEM MODE

ERROR RESPONSE

PIN MULTIPLEXING CONTROL

User/Privilege

Mux configuration error

ESM

1.37

POWER DOMAIN CONTROL

User/Privilege

PSCON compare error

PSCON self-test error

ESM

1.38

1.39

User/Privilege

eFuse Controller

User/Privilege

eFuse Controller Autoload error

ESM => nERROR

3.1

eFuse Controller - Any bit set in the error status register

eFuse Controller self-test error

User/Privilege

ESM

1.40

1.41

WINDOWED WATCHDOG

n/a

WWD Non-Maskable Interrupt exception

ESM => NMI => nERROR

2.24

ERRORS REFLECTED IN THE SYSESR REGISTER

Power-Up Reset

n/a

Reset

n/a

Oscillator fail / PLL slip⁽²⁾

Watchdog exception

CPU Reset (driven by the CPU STC)

Software Reset

External Reset

(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

6.20 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code

execution.

The DWWD module allows the application to configure the time window within which the DWWD module

expects the application to service the watchdog. A watchdog violation occurs if the application services the

watchdog outside of this window, or fails to service the watchdog at all. The application can choose to

generate a system reset or a non-maskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog

can only be disabled upon a system reset.

System Information and Electrical Specifications

91

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21 Debug Subsystem

6.21.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains.

Boundary Scan

Boundary Scan I/F

BSR/BSDL

Debug

ROM1

TRST

TMS

TCK

RTCK

TDI

TDO

Debug APB

DAP

Secondary Tap 0

APB Mux

AHB-AP

APB slave

Cortex

R4F

POM

ETM

TPIU

from

PCR1/Bridge

to SCR1 via A2A

RTP

DMM

TAP 0

Secondary Tap 1

TAP 1

Secondary Tap 2

AJSM

图 6-19. Debug Subsystem Block Diagram

6.21.2 Debug Components Memory Map

表 6-38. Debug Components Memory Map

FRAME ADDRESS RANGE

RESPNSE FOR ACCESS TO

UNIMPLEMENTED LOCATIONS IN

FRAME

FRAME CHIP

SELECT

FRAME ACTUA

MODULE NAME

SIZE

4KB

L SIZE

START

END

CoreSight Debug

ROM

CSCS0

CSCS1

0xFFA0_0000

0xFFA0_0FFF

4KB

Reads: 0, writes: no effect

Cortex-R4F

Debug

0xFFA0_1000

0xFFA0_1FFF

4KB

ETM-R4

CSCS2

CSCS3

0xFFA0_2000

0xFFA0_3000

0xFFA0_2FFF

0xFFA0_3FFF

4KB

Reads: 0, writes: no effect

CoreSight TPIU

6.21.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

JTAG ID Code

Silicon Revision

ID

Rev A

0x0D8A002F

92

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

JTAG ID Code (continued)

Silicon Revision

Rev B

ID

0x2D8A002F

0x3D8A002F

Rev C

6.21.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

表 6-39. Debug ROM table

ADDRESS

0x000

DESCRIPTION

pointer to Cortex-R4F

ETM-R4

VALUE

0x0000 1003

0x0000 2003

0x0000 3003

0x0000 4003

0x0000 0000

0x001

0x002

TPIU

0x003

POM

0x004

end of table

System Information and Electrical Specifications

93

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21.5 JTAG Scan Interface Timings

表 6-40. JTAG Scan Interface Timing⁽¹⁾

NO.

MIN

MAX

UNIT

MHz

ns

f_TCK

TCK frequency (at HCLKmax)

12

f_RTCK

RTCK frequency (at TCKmax and HCLKmax)

Delay time, TCK to RTCK

10

1

2

3

4

5

t_{d(TCK -RTCK)}

t_{su(TDI/TMS - RTCKr)}

t_{h(RTCKr -TDI/TMS)}

t_{h(RTCKr -TDO)}

t_{d(TCKf -TDO)}

24

12

Setup time, TDI, TMS before RTCK rise (RTCKr)

Hold time, TDI, TMS after RTCKr

26

0

ns

Hold time, TDO after RTCKf

0

ns

Delay time, TDO valid after RTCK fall (RTCKf)

ns

(1) Timings for TDO are specified for a maximum of 50pF load on TDO

TCK

RTCK

1

TMS

TDI

2

3

TDO

4

5

图 6-20. JTAG Timing

94

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

6.21.6 Advanced JTAG Security Module

This device includes an Advanced JTAG Security Module (AJSM). which provides maximum security to

the device’s memory content by allowing users to secure the device after programming.

Flash Module Output

OTP Contents

(example)

. . .

H

L

H

L

H

L

H

Unlock By Scan

Register

H

L

Internal Tie-Offs

(example only)

L

H

UNLOCK

128-bit comparator

Internal Tie-Offs

(example only)

H

L

H

L

H

图 6-21. AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP

address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The

outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this

combinational logic is compared against a secret hard-wired 128-bit value. A match results in the

UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing

a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash

region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the

device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By

Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents

and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap 2 of the

ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in

this state.

System Information and Electrical Specifications

95

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21.7 Embedded Trace Macrocell (ETM-R4)

The device contains a ETM-R4 module with a 32-bit internal data port. The ETM-R4 module is connected

to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data, 3-bit control) external interface

for trace. The ETM-R4 is CoreSight compliant and follows the ETM v3 specification; for more details see

ARM CoreSight ETM-R4 TRM specification.

6.21.7.1 ETM TRACECLKIN Selection

The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The

selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. The address of this

register is TPIU base address + 0x404.

Before you begin accessing TPIU registers, TPIU should be unlocked via coresight key and 1 or 2 should

be written to this register.

表 6-41. TPIU / TRACECLKIN Selection

EXTCTRLOUT[1:0]

TPIU/TRACECLKIN

tied-zero

00

01

10

11

VCLK

ETMTRACECLKIN

tied-zero

6.21.7.2 Timing Specifications

t_l(ETM)

t_h(ETM)

t_r(ETM)

t_f(ETM)

t_cyc(ETM)

图 6-22. ETMTRACECLKOUT Timing

表 6-42. ETMTRACECLK Timing

MIN

MAX

UNIT

t_cyc(ETM)

t_l(ETM)

Clock period

t_(HCLK)× 4

Low pulse width

20

ns

t_h(ETM)

t_r(ETM)

t_f(ETM)

High pulse width

Clock and data rise time

Clock and data fall time

3

96

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

图 6-23. ETMDATA Timing

表 6-43. ETMDATA Timing

TMS5703137CGWTQEP

TMS5703137CGWTMEP

UNIT

MIN

MAX

MIN

MAX

t_{d(ETMTRACECLKH-}Delay time from ETM trace clock high to ETM

1.5

7

1.3

7

ns

data valid

ETMDATAV)

t_{d(ETMTRACECLKl-}Delay time from ETM trace clock low to ETM

1.5

7

1.3

7

data valid

ETMDATAV)

SPACE

注

The ETMTRACECLK and ETMDATA timing is based on a 15pF load and for ambient

temperature lower than 85°C.

System Information and Electrical Specifications

97

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21.8 RAM Trace Port (RTP)

The RTP provides the ability to datalog the RAM contents of the devices or accesses to peripherals

without program intrusion. It can trace all data write or read accesses to internal RAM. In addition, it

provides the capability to directly transfer data to a FIFO to support a CPU-controlled transmission of the

data. The trace data is transmitted over a dedicated external interface.

6.21.8.1 Features

The RTP offers the following features:

•

Two modes of operation - Trace Mode and Direct Data Mode

–

Trace Mode

•

Non-intrusive data trace on write or read operation

Visibility of RAM content at any time on external capture hardware

Trace of peripheral accesses

Two configurable trace regions for each RAM module to limit amount of data to be traced

FIFO to store data and address of data of multiple read/write operations

Trace of CPU and/or DMA accesses with indication of the master in the transmitted data packet

–

Direct Data Mode

•

Directly write data with the CPU or trace read operations to a FIFO, without transmitting header

and address information

•

Dedicated synchronous interface to transmit data to external devices

Free-running clock generation or clock stop mode between transmissions

Up to 100 Mbit per sec/pin transfer rate for transmitting data

Pins not used in functional mode can be used as GIOs

6.21.8.2 Timing Specifications

表 6-44. RTPCLK Timing

MIN

UNIT

t_cyc(RTP)

Clock period, prescaled from HCLK; must not be

–40°C to 125°C

11 (90 MHz)

ns

faster than HCLK / 2

High pulse width

Low pulse width

t_h(RTP)

t_l(RTP)

–40°C to 125°C

((t_cyc(RTP)) / 2) – ((t_r+ t_f) / 2)

t_l(RTP)

t_h(RTP)

t_f

t_r

t_cyc(RTP)

图 6-24. RTPCLK Timing

表 6-45. RTPDATA Timing

MIN

–5

MAX

UNIT

t_{d(RTPCLKH-RTPSYNCV)}

t_{d(RTPCLKH-RTPDATAV)}

SYNC delay time

Data delay time

4

ns

–5

98

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

图 6-25. RTPDATA Timing

表 6-46. RTPnENA Timing

MIN

MAX

UNIT

t_dis(RTP)

Time RTPnENA must go high before what would be the 3t_c(HCLK)+ t_r(RTPSYNC)+ 12 ns

next RTPSYNC, to ensure delaying the next packet

t_ena(RTP)Time after RTPnENA goes low before a packet that has

been halted, resumes

4t_c(HCLK)+ t_r(RTPSYNC)

5t_c(HCLK)+ t_r(RTPSYNC)

+

12 ns

t_ena(RTP)

t_dis(RTP)

1

2

3

4

5

6

7

8

9

10 11

12 13

14

15 16

HCLK

RTPCLK

RTPnENA

RTPENA

RTPSYNC

RTPDATA

d1

d2

d3

d4

Divide by 1

d5

d6

d7

d8

图 6-26. RTPnENA Timing

System Information and Electrical Specifications

99

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21.9 Data Modification Module (DMM)

The DMM provides the capability to modify data in the entire 4 GB address space of the devices from an

external peripheral, with minimal interruption of the application.

6.21.9.1 Features

The DMM module has the following features:

•

Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention

Writes to memory locations specified in the received packet (leverages packets defined by trace mode

of the RAM trace port (RTP) module

•

Writes received data to consecutive addresses, which are specified by the DMM module (leverages

packets defined by direct data mode of RTP module)

•

Configurable port width (1, 2, 4, 8, 16 pins)

Up to 100 Mbit/s pin data rate

Unused pins configurable as GPIO pins

6.21.9.2 Timing Specifications

表 6-47. DMMCLK Timing

MIN

t_c(HCLK)× 2

UNIT

t_cyc(DMM)

t_h(DMM)

t_l(DMM)

Clock period

High pulse width

Low pulse width

–40°C to 125°C

((t_cyc(DMM)) / 2) – ((t_r+ t_f) / 2)

t_l(DMM)

t_h(DMM)

t_f

t_r

t_cyc(DMM)

图 6-27. DMMCLK Timing

表 6-48. DMMDATA Timing

PARAMETER

MIN

2 ns

3 ns

2 ns

3 ns

UNIT

ns

t_ssu(DMM)

t_sh(DMM)

t_dsu(DMM)

t_dh(DMM)

SYNC active to clk falling edge setup time

clk falling edge to SYNC deactive hold time

DATA to clk falling edge setup time

clk falling edge to DATA hold time

100

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

t_ssu(DMM)

t_sh(DMM)

DMMSYNC

DMMCLK

DMMDATA

t_dsu(DMM)

t_dh(DMM)

图 6-28. DMMDATA Timing

图 6-29 shows a case with 1 DMM packet per 2 DMMCLK cycles (Mode = Direct Data Mode, data width =

8, portwidth = 4) where none of the packets received by the DMM are sent out, leading to filling up of the

internal buffers. The DMMnENA signal is shown asserted, after the first two packets have been received

and synchronised to the HCLK domain. Here, the DMM has the capacity to accept packets D4x, D5x, D6x,

D7x. Packet D8 would result in an overflow. Once DMMnENA is asserted, the DMM expects to stop

receiving packets after 4 HCLK cycles; once DMMnENA is de-asserted, the DMM can handle packets

immediately (after 0 HCLK cycles).

HCLK

DMMCLK

DMMSYNC

D00

D01

D10

D11

D20

D21

D30

D31

D40

D41

D50

DMMDATA

DMMnENA

图 6-29. DMMnENA Timing

System Information and Electrical Specifications

101

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

6.21.10 Boundary Scan Chain

The device supports IEEE1149.1-compliant boundary scan for testing pin-to-pin compatibility. The

boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

Device Pins (conceptual)

TRST

TMS

TCK

TDI

Boundary

Scan

Boundary Scan Interface

TDO

RTCK

TDI

TDO

BSDL

图 6-30. Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers via TDI, and out via TDO.

102

System Information and Electrical Specifications

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7 Peripheral Information

7.1 Peripheral Legend

表 7-1. Peripheral Legend

Abbreviation

MibADC

CCM-R4F

CRC

Full Name

Analog To Digital Converter

CPU Compare Module - CortexR4F

Cyclic Redundancy Check

Controller Area Network

Dual Clock Comparator

Direct Memory Access

DCAN

DCC

DMA

DMM

EMIF

ESM

Data Modification Module

External Memory Interface

Error Signaling Module

ETM-R4F

FTU

Embedded Trace Macrocell - CortexR4F

FlexRay Transfer Unit

GPIO

HTU

General-Purpose Input/Output

High End Timer Transfer Unit

Inter-Integrated Circuit

I2C

LIN

Local Interconnect Network

Multibuffer Serial Peripheral Interface

Platform High-End Timer

MIBSPI

N2HET

POM

Parameter Overlay Module

Real-Time Interrupt Module

RAM Trace Port

RTI

RTP

SCI

Serial Communications Interface

Serial Peripheral Interface

Vectored Interrupt Manager

SPI

VIM

7.2 Multi-Buffered 12bit Analog-to-Digital Converter

The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that

enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could

be present on V_SSand V_CCfrom coupling into the A-to-D analog stage. All A-to-D specifications are given

with respect to AD_REFLOunless otherwise noted.

表 7-2. MibADC Overview

Description

Resolution

Value

12 bits

Assured

Monotonic

Output conversion code

00h to FFFh [00 for V_AI≤ AD_REFLO; FFF for V_AI≥ AD_REFHI]

7.2.1 Features

•

10-/12-bit resolution

AD_REFHIand AD_REFLOpins (high and low reference voltages)

Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK

One memory region per conversion group is available (event, group 1, group 2)

Allocation of channels to conversion groups is completely programmable

Memory regions are serviced either by interrupt or by DMA

Peripheral Information

103

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

•

Programmable interrupt threshold counter is available for each group

Programmable magnitude threshold interrupt for each group for any one channel

Option to read either 8-bit, 10-bit or 12-bit values from memory regions

Single or continuous conversion modes

Embedded self-test

Embedded calibration logic

Enhanced power-down mode

–

Optional feature to automatically power down ADC core when no conversion is in progress

•

External event pin (ADEVT) programmable as general-purpose I/O

7.2.2 Event Trigger Options

The ADC module supports 3 conversion groups: Event Group, Group1 and Group2. Each of these 3

groups can be configured to be hardware event-triggered. In that case, the application can select from

among 8 event sources to be the trigger for a group's conversions.

7.2.2.1 Default MIBADC1 Event Trigger Hookup

表 7-3. MIBADC1 Event Trigger Hookup

Event Number

Source Select Bits For G1, G2 Or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

1

2

3

4

5

6

7

8

000

001

010

011

100

101

110

111

ADEVT

N2HET1[8]

N2HET1[10]

RTI compare 0 interrupt

N2HET1[12]

N2HET1[14]

GIOB[0]

GIOB[1]

注

For ADEVT, N2HET1 and GIOB trigger sources, the connection to the MibADC1 module

trigger input is made from the output side of the input buffer. This way, a trigger condition

can be generated either by configuring the function as output onto the pad (via the mux

control), or by driving the function from an external trigger source as input. If the mux control

module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x]

signals, then care must be taken to disable these signals from triggering conversions; there

is no multiplexing on the input connections.

注

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

7.2.2.2 Alternate MIBADC1 Event Trigger Hookup

表 7-4. Alternate MIBADC1 Event Trigger Hookup

Event Number

Source Select Bits for G1, G2 or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

1

2

000

001

ADEVT

N2HET2[5]

104

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-4. Alternate MIBADC1 Event Trigger Hookup (continued)

Event Number

Source Select Bits for G1, G2 or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

3

4

5

6

7

8

010

011

100

101

110

111

N2HET1[27]

RTI compare 0 interrupt

N2HET1[17]

N2HET1[19]

N2HET1[11]

N2HET2[13]

The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger hook-

up is done by multiplexing control module register 30 bits 0 and 1.

If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.

If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.

注

For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

configuring ADEVT as an output function on to the pad (via the mux control), or by driving

the ADEVT signal from an external trigger source as input. If the mux control module is used

to select different functionality instead of the ADEVT signal, then care must be taken to

disable ADEVT from triggering conversions; there is no multiplexing on the input connection.

注

For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made

from the input side of the output buffer (at the N2HETx module boundary). This way, a

trigger condition can be generated even if the N2HETx signal is not selected to be output on

the pad.

注

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

7.2.2.3 Default MIBADC2 Event Trigger Hookup

表 7-5. MIBADC2 Event Trigger Hookup

Event Number

Source Select Bits for G1, G2 or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

1

2

3

4

5

6

7

8

000

001

010

011

100

101

110

111

AD2EVT

N2HET1[8]

N2HET1[10]

RTI compare 0

N2HET1[12]

N2HET1[14]

GIOB[0]

GIOB[1]

Peripheral Information

105

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

注

For AD2EVT, N2HET1 and GIOB trigger sources, the connection to the MibADC2 module

trigger input is made from the output side of the input buffer. This way, a trigger condition

can be generated either by configuring the function as output onto the pad (via the mux

control), or by driving the function from an external trigger source as input. If the mux control

module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x]

signals, then care must be taken to disable these signals from triggering conversions; there

is no multiplexing on the input connections.

注

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

7.2.2.4 Alternate MIBADC2 Event Trigger Hookup

表 7-6. Alternate MIBADC2 Event Trigger Hookup

Event Number

Source Select Bits for G1, G2 or Event

(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])

Trigger

1

2

3

4

5

6

7

8

000

001

010

011

100

101

110

111

AD2EVT

N2HET2[5]

N2HET1[27]

RTI compare 0

N2HET1[17]

N2HET1[19]

N2HET1[11]

N2HET2[13]

The selection between the default MIBADC2 event trigger hook-up versus the alternate event trigger hook-

up is done by multiplexing control module register 30 bits 0 and 1.

If 30[0] = 1, then the default MibADC2 event trigger hook-up is used.

If 30[0] = 0 and 30[1] = 1, then the alternate MibADC2 event trigger hook-up is used.

注

For AD2EVT trigger source, the connection to the MibADC2 module trigger input is made

from the output side of the input buffer. This way, a trigger condition can be generated either

by configuring AD2EVT as an output function on to the pad (via the mux control), or by

driving the AD2EVT signal from an external trigger source as input. If the mux control module

is used to select different functionality instead of the AD2EVT signal, then care must be

taken to disable AD2EVT from triggering conversions; there is no multiplexing on the input

connections.

注

For N2HETx trigger sources, the connection to the MibADC2 module trigger input is made

from the input side of the output buffer (at the N2HETx module boundary). This way, a

trigger condition can be generated even if the N2HETx signal is not selected to be output on

the pad.

106

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

注

For the RTI compare 0 interrupt source, the connection is made directly from the output of

the RTI module. That is, the interrupt condition can be used as a trigger source even if the

actual interrupt is not signaled to the CPU.

Peripheral Information

107

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.2.3 ADC Electrical and Timing Specifications

表 7-7. MibADC Recommended Operating Conditions

MIN

AD_REFLO

V_SSAD

MAX

V_CCAD

AD_REFHI

2

UNIT

V

AD_REFHI

AD_REFLO

V_AI

A-to-D high-voltage reference source

A-to-D low-voltage reference source

Analog input voltage

V

AD_REFLO

–2

V

I_AIC

Analog input clamp current

mA

(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)

表 7-8. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER

DESCRIPTION / TEST CONDITIONS

MIN

TYP

MAX UNIT

R_mux

Analog input mux on-

resistance

See 图 7-1

250

Ω

R_samp

ADC sample switch on-

resistance

See 图 7-1

250

Ω

C_mux

C_samp

I_AIL

Input mux capacitance

See 图 7-1

16

13

pF

nA

ADC sample capacitance

Analog off-state input

leakage current

V_CCAD= 3.6 V

maximum

V

_SSAD≤ V_IN< V_SSAD+ 100 mV

-300

-200

200

V_SSAD+ 100 mV ≤ V_IN≤ V_CCAD- 200

mV

V_CCAD- 200 mV < V_IN≤ V_CCAD

-200

-1000

-250

500

250

nA

Analog off-state input

leakage current

V_CCAD= 5.5 V

maximum

V_SSAD≤ V_IN< V_SSAD+ 300 mV

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD- 300

mV

V_CCAD- 300 mV < V_IN≤ V_CCAD

-250

-8

1000

2

nA

µA

V_SSAD≤ V_IN< V_SSAD+ 100 mV

ADC1 Analog on-state input V_CCAD= 3.6 V

bias current maximum

V_SSAD+ 100 mV < V_IN< V_CCAD- 200

mV

(1)

I_AOSB1

I_AOSB2

I_AOSB1

I_AOSB2

-4

2

V_CCAD- 200 mV < V_IN< V_CCAD

-4

-7

12

2

V_SSAD≤ V_IN< V_SSAD+ 100 mV

ADC2 Analog on-state input V_CCAD= 3.6V

bias current maximum

V_SSAD+ 100 mV ≤ V_IN≤ V_CCAD- 200

mV

-4

2

µA

V_CCAD- 200 mV < V_IN≤ V_CCAD

-4

10

3

V_SSAD≤ V_IN< V_SSAD+ 300 mV

-10

ADC1 Analog on-state input V_CCAD= 5.5V

bias current maximum

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD-

300mV

-5

3

V_CCAD- 300 mV < V_IN≤ V_CCAD

-5

-8

14

3

V_SSAD≤ V_IN< V_SSAD+ 300 mV

ADC2 Analog on-state input V_CCAD= 5.5V

V_SSAD+ 300 mV ≤ V_IN≤ V_CCAD- 300

mV

-5

3

12

3

µA

bias current

maximum

V_CCAD- 300 mV < V_IN≤ V_CCAD

AD_REFHIinput

current

AD_REFHI= V_CCAD, AD_REFLO= V_SSAD

;

I_ADREFHI

I_CCAD

mA

–40°C to 125°C

Normal operating mode; –40°C to 125°C

15 mA

µA

Static supply current

ADC core in power down mode; –40°C to 125°C

5

(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to I_AOSL1+ I_AOSL2

108

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

R_ext

P_in

R_mux

S_mux

V_S1

I_AOSB

C_ext

On-State

Bias Current

S_mux

R_ext

P_in

R_mux

V_S2

I_AIL

C_ext

I_AIL

Off-State

Leakages

S_mux

R_ext

P_in

R_mux

S_samp

R_samp

V_S24

I_AIL

C_samp

C_mux

C_ext

I_AIL

图 7-1. MibADC Input Equivalent Circuit

表 7-9. MibADC Timing Specifications

MIN

NOM

MAX

UNIT

(1)

t_c(ADCLK)

Cycle time, MibADC clock

–40°C to 125°C

0.033

µs

(2)

t_d(SH)

Delay time, sample and hold time

0.2

1

t_d(PU-ADV)

Delay time from ADC power on until first

input can be sampled

12-bit mode

t_d(c)

Delay time, conversion time

–40°C to 125°C

0.4

0.6

µs

(3)

t_d(SHC)

Delay time, total sample/hold and

conversion time

10-bit mode

t_d(c)

Delay time, conversion time

–40°C to 125°C

0.33

0.53

µs

(3)

t_d(SHC)

Delay time, total sample/hold and

conversion time

(1) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits

4:0.

(2) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each

conversion group. The sample time needs to be determined by accounting for the external impedance connected to the input channel as

well as the ADC’s internal impedance.

(3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors, e.g the

prescale settings.

Peripheral Information

109

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 7-10. MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER

DESCRIPTION / TEST CONDITIONS

MIN

NOM

MAX

UNIT

CR

Conversion range

over which specified

accuracy is

AD_REFHI– AD_REFLO

–40°C to 125°C

3

5.5

V

maintained

Z_SET

Zero Scale Offset

Difference between the first ideal

transition (from code 000h to 001h) and –40°C to 125°C

the actual transition

10-bit mode;

1

2

3

LSB⁽¹⁾

LSB⁽²⁾

LSB

12-bit mode;

–40°C to 125°C

F_SET

Full Scale Offset

Difference between the range of the

measured code transitions (from first to –40°C to 125°C

last) and the range of the ideal code

transitions

10-bit mode;

12-bit mode;

–40°C to 125°C

LSB

E_DNL

Differential

nonlinearity error

Difference between the actual step width 10-bit mode

±1.5

±2

LSB

and the ideal value. (See Figure 76)

12-bit mode

E_INL

Integral nonlinearity

error

Maximum deviation from the best

straight line through the MibADC.

MibADC transfer characteristics,

excluding the quantization error.

10-bit mode

12-bit mode

±2

E_TOT

Total unadjusted error Maximum value of the difference

between an analog value and the ideal

midstep value.

10-bit mode

12-bit mode

±2

±4

LSB

(1) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹⁰for 10-bit mode

(2) 1 LSB = (AD_REFHI– AD_REFLO)/ 2¹²for 12-bit mode

110

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.2.4 Performance (Accuracy) Specifications

7.2.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 图 7-2 (sometimes referred to as differential linearity) is

the difference between an actual step width and the ideal value of 1 LSB.

0 ... 110

0 ... 101

0 ... 100

0 ... 011

Differential Linearity

Error (–½ LSB)

1 LSB

0 ... 010

Differential Linearity

Error (–½ LSB)

0 ... 001

0 ... 000

1 LSB

0

1

2

3

4

5

Analog Input Value (LSB)

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

图 7-2. Differential Nonlinearity (DNL) Error

Peripheral Information

111

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

The integral nonlinearity error shown in Figure 图 7-3 (sometimes referred to as linearity error) is the

deviation of the values on the actual transfer function from a straight line.

0 ... 111

0 ... 110

Ideal

Transition

0 ... 101

0 ... 100

0 ... 011

0 ... 010

0 ... 001

0 ... 000

Actual

Transition

At Transition

011/100

(–½ LSB)

End-Point Lin. Error

At Transition

001/010 (–1/4 LSB)

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

图 7-3. Integral Nonlinearity (INL) Error

112

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.2.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 图 7-4 is the maximum value of the

difference between an analog value and the ideal midstep value.

0 ... 111

0 ... 110

0 ... 101

0 ... 100

Total Error

At Step 0 ... 101

(–1 1/4 LSB)

0 ... 011

0 ... 010

Total Error

At Step

0 ... 001 (1/2 LSB)

0 ... 001

0 ... 000

0

1

2

3

4

5

6

7

Analog Input Value (LSB)

NOTE A: 1 LSB = (AD_REFHI– AD_REFLO)/2¹²

图 7-4. Absolute Accuracy (Total) Error

Peripheral Information

113

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.3 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and

bit-programmable. Both GIOA and GIOB support external interrupt capability.

7.3.1 Features

The GPIO module has the following features:

•

Each IO pin can be configured as:

–

Input

Output

Open Drain

•

The interrupts have the following characteristics:

–

Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)

Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)

Individual interrupt flags (set in GIOFLG register)

Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers

respectively

–

Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers

•

Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see 节 5.11 and 节 5.12

114

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.4 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,

capture or compare inputs, or general-purpose I/O.. It is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses.

7.4.1 Features

The N2HET module has the following features:

•

Programmable timer for input and output timing functions

Reduced instruction set (30 instructions) for dedicated time and angle functions

160 words of instruction RAM protected by parity

User defined number of 25-bit virtual counters for timer, event counters and angle counters

7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual

counters

•

Up to 32 pins usable for input signal measurements or output signal generation

Programmable suppression filter for each input pin with adjustable limiting frequency

Low CPU overhead and interrupt load

Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)

or DMA

•

Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

7.4.2 N2HET RAM Organization

The timer RAM uses 4 RAM banks, where each bank has two port access capability. This means that one

RAM address may be written while another address is read. The RAM words are 96-bits wide, which are

split into three 32-bit fields (program, control, and data).

7.4.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

表 7-11. Input Timing Requirements for the N2HET Input Capture Functionality

MIN^{(1) (2)}

MAX^{(1) (2)}UNI

T

1

2

3

4

Input signal period, PCNT or WCAP –40°C to 125°C

for rising edge to rising edge

2 (hr) (lr) tc_(VCLK2)+ 2 2²⁵(hr) (lr) tc_(VCLK2)- 2 ns

(hr) (lr) tc_(VCLK2)+ 2 2²⁵(hr) (lr) tc_(VCLK2)- 2 ns

Input signal period, PCNT or WCAP –40°C to 125°C

for falling edge to falling edge

Input signal high phase, PCNT or

WCAP for rising edge to falling edge

–40°C to 125°C

Input signal low phase, PCNT or

–40°C to 125°C

WCAP for falling edge to rising edge

(1) hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).

(2) lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)

Peripheral Information

115

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1

N2HETx

3

4

2

图 7-5. N2HET Input Capture Timings

Both N2HET1 and N2HET2 have channels that are enhanced to be able to capture inputs with smaller

pulse widths than that specified in 表 7-11. See 表 7-13 for a list of which pins support small pulse

capture.

The input capture capability for these channels is specified in the following table.

表 7-12. Input Timing Requirements for N2HET Channels With Enhanced Pulse Capture

MIN

MAX UNIT

1

2

3

4

Input signal period, PCNT or WCAP for rising

edge to rising edge

–40°C to 125°C

(hr) (lr) tc_(VCLK2)+ 2 2²⁵(hr) (lr) tc_(VCLK2)- 2

2 (hr) tc_(VCLK2)+ 2 2²⁵(hr) (lr) tc_(VCLK2)- 2

ns

Input signal period, PCNT or WCAP for falling

edge to falling edge

Input signal high phase, PCNT or WCAP for

rising edge to falling edge

Input signal low phase, PCNT or WCAP for

falling edge to rising edge

表 7-13. Input Capture Pin Capability

Channel

Supports 32-bit Capture

Enhanced Pulse Capture

N2HET1[00]

N2HET1[01]

N2HET1[02]

N2HET1[03]

N2HET1[04]

N2HET1[05]

N2HET1[06]

N2HET1[07]

N2HET1[08]

N2HET1[09]

N2HET1[10]

N2HET1[11]

N2HET1[12]

N2HET1[13]

N2HET1[14]

N2HET1[15]

N2HET1[16]

N2HET1[17]

N2HET1[18]

N2HET1[19]

N2HET1[20]

Yes

No

Yes

No

Yes

116

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-13. Input Capture Pin Capability (continued)

Channel

Supports 32-bit Capture

Enhanced Pulse Capture

N2HET1[21]

N2HET1[22]

N2HET1[23]

N2HET1[24]

N2HET1[25]

N2HET1[26]

N2HET1[27]

N2HET1[28]

N2HET1[29]

N2HET1[30]

N2HET1[31]

N2HET2[00]

N2HET2[01]

N2HET2[02]

N2HET2[03]

N2HET2[04]

N2HET2[05]

N2HET2[06]

N2HET2[07]

N2HET2[08]

N2HET2[09]

N2HET2[10]

N2HET2[11]

N2HET2[12]

N2HET2[13]

N2HET2[14]

N2HET2[15]

N2HET2[16]

N2HET2[18]

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

7.4.4 N2HET1-N2HET2 Interconnections

In some applications the N2HET resolutions must be synchronized. Some other applications require a

single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures

the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal

to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to

the loop resolution signal sent by the master. The slave does not require this signal after it receives the

first synchronization signal. However, anytime the slave receives the re-synchronization signal from the

master, the slave must synchronize itself again..

N2HET1

N2HET2

NHET_LOOP_SYNC

EXT_LOOP_SYNC

NHET_LOOP_SYNC

EXT_LOOP_SYNC

图 7-6. N2HET1 – N2HET2 Synchronization Hookup

Peripheral Information

117

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.4.5 N2HET Checking

7.4.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be

used to monitor each other’s signals as shown in 图 7-7. The direction of the monitoring is controlled by

the I/O multiplexing control module.

IOMM mux control signal x

N2HET1[1,3,5,7,9,11]

N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]

N2HET1

N2HET2[8,10,12,14,16,18]

N2HET2

图 7-7. N2HET Monitoring

7.4.5.2 Output Monitoring using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to

measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection

to the DCC module is made directly from the output of the N2HETx module (from the input of the output

buffer).

For more information on DCC see 节 6.7.3.

7.4.6 Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET

module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the

N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the

device specific technical reference manual for more details on the "N2HET Pin Disable" feature.

GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin

Disable" input for N2HET2.

118

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.4.7 High-End Timer Transfer Unit (HET-TU)

A High End Timer Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to

or from main memory. A Memory Protection Unit (MPU) is built into the HET-TU.

7.4.7.1 Features

CPU and DMA independent

•

Master Port to access system memory

8 control packets supporting dual buffer configuration

Control packet information is stored in RAM protected by parity

Event synchronization (HET transfer requests)

Supports 32 or 64 bit transactions

Addressing modes for HET address (8 byte or 16 byte) and system memory address (fixed, 32 bit or

64bit)

•

One shot, circular and auto switch buffer transfer modes

Request lost detection

7.4.7.2 Trigger Connections

表 7-14. HET TU1 Request Line Connection

Modules

N2HET1

Request Source

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU1 Request

HET TU1 DCP[0]

HET TU1 DCP[1]

HET TU1 DCP[2]

HET TU1 DCP[3]

HET TU1 DCP[4]

HET TU1 DCP[5]

HET TU1 DCP[6]

HET TU1 DCP[7]

表 7-15. HET TU2 Request Line Connection

Modules

N2HET2

Request Source

HTUREQ[0]

HTUREQ[1]

HTUREQ[2]

HTUREQ[3]

HTUREQ[4]

HTUREQ[5]

HTUREQ[6]

HTUREQ[7]

HET TU2 Request

HET TU2 DCP[0]

HET TU2 DCP[1]

HET TU2 DCP[2]

HET TU2 DCP[3]

HET TU2 DCP[4]

HET TU2 DCP[5]

HET TU2 DCP[6]

HET TU2 DCP[7]

Peripheral Information

119

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.5 FlexRay Interface

The FlexRay module performs communication according to the FlexRay protocol specification v2.1. The

sample clock bitrate can be programmed to values up to 10 MBit per second. Additional bus driver (BD)

hardware is required for connection to the physical layer.

For communication on a FlexRay network, individual message buffers with up to 254 data bytes are

configurable. The message storage consists of a single-ported message RAM that holds up to 128

message buffers. All functions concerning the handling of messages are implemented in the message

handler. Those functions are the acceptance filtering, the transfer of messages between the two FlexRay

Channel Protocol Controllers and the message RAM, maintaining the transmission schedule as well as

providing message status information.

The register set of the FlexRay module can be accessed directly by the CPU via the VBUS interface.

These registers are used to control, configure and monitor the FlexRay channel protocol controllers,

message handler, global time unit, system universal control, frame/symbol processing, network

management, interrupt control, and to access the message RAM via the input / output buffer.

7.5.1 Features

The FlexRay module has the following features:

•

Conformance with FlexRay protocol specification v2.1

Data rates of up to 10 Mb/s on each channel

Up to 128 message buffers

8 Kbyte of message RAM for storage of, for example, 128 message buffers with max 48 byte data

section or up to 30 message buffers with 254 byte data section

•

Configuration of message buffers with different payload lengths

One configurable receive FIFO

Each message buffer can be configured as receive buffer, as transmit buffer or as part of the receive

FIFO

•

CPU access to message buffers via input and output buffer

FlexRay transfer unit (FTU) for automatic data transfer between data memory and message buffers

without CPU interaction

•

Filtering for slot counter, cycle counter, and channel ID

Maskable module interrupts

Supports Network Management

7.5.2 Electrical and Timing Specifications

表 7-16. Timing Requirements for FlexRay Inputs

MIN

t_c(AVCLK2)+ 2.5⁽¹⁾

MAX

UNIT

t_pw

Input minimum pulse width to meet the FlexRay sampling

requirement

–40°C to 125°C

ns

(1) t_RxAsymDelayparameter

t_pw

V_CCIO

Input

0.4*V_CCIO

0.6*V_CCIO

0.4*V_CCIO

0

图 7-8. FlexRay Inputs

120

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-17. FlexRay Jitter Timing

MIN

98

MAX

102

UNIT

ns

t_Tx1bit

Clock jitter and signal symmetry

FlexRay BSS (byte start sequence) to BSS –40°C to 125°C

Average over 10000 samples –40°C to 125°C

t_Tx10bit

999

999.5

—

1001

1000.5

2.5

ns

t_Tx10bitAvg

t_RxAsymDelay

ns

Delay difference between rise and fall from –40°C to 125°C

Rx pin to sample point in FlexRay core

ns

t_jit(SCLK)

Jitter for the 80MHz Sample Clock

generated by the PLL

–40°C to 125°C

—

0.5

ns

7.5.3 FlexRay Transfer Unit

The FlexRay Transfer Unit is able to transfer data between the input buffer (IBF) and output buffer (OBF)

of the communication controller and the system memory without CPU interaction.

Because the FlexRay module is accessed through the FTU, the FTU must be powered up by the setting

bit 23 in the Peripheral Power Down Registers of the System Module before accessing any FlexRay

module register.

For more information on the FTU see the TMS570LS31X/TMS570LS21X Technical Reference Manual

(SPNU499).

Peripheral Information

121

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.6 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication

protocol that efficiently supports distributed real-time control with robust communication rates of up to 1

megabit per second (Mbps). The DCAN is ideal for applications operating in noisy and harsh

environments (e.g., automotive and industrial fields) that require reliable serial communication or

multiplexed wiring.

7.6.1 Features

Features of the DCAN module include:

•

Supports CAN protocol version 2.0 part A, B

Bit rates up to 1 MBit/s

The CAN kernel can be clocked by the oscillator for baud-rate generation.

64 mailboxes on each DCAN

Individual identifier mask for each message object

Programmable FIFO mode for message objects

Programmable loop-back modes for self-test operation

Automatic bus on after Bus-Off state by a programmable 32-bit timer

Message RAM protected by parity

Direct access to Message RAM during test mode

CAN Rx / Tx pins configurable as general purpose IO pins

Message RAM Auto Initialization

DMA support

For more information on the DCAN see the TMS570LS31X/21X Technical Reference Manual (SPNU499).

7.6.2 Electrical and Timing Specifications

表 7-18. Dynamic Characteristics for the DCANx TX and RX pins

PARAMETER

Delay time, transmit shift register to CANnTX pin⁽¹⁾

MIN

MAX

15

UNIT

ns

t_d(CANnTX)

t_d(CANnRX)

Delay time, CANnRX pin to receive shift register

5

ns

(1) These values do not include rise/fall times of the output buffer.

122

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.7 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is

an SCI. The SCI’s hardware features are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn

to zero format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-

line.

The LIN standard is based on the SCI (UART) serial data link format. The communication concept is

single-master/multiple-slave with a message identification for multi-cast transmission between any network

nodes.

7.7.1 LIN Features

The following are features of the LIN module:

•

Compatible to LIN 1.3, 2.0 and 2.1 protocols

Multi-buffered receive and transmit units DMA capability for minimal CPU intervention

Identification masks for message filtering

Automatic Master Header Generation

–

Programmable Synch Break Field

Synch Field

Identifier Field

•

Slave Automatic Synchronization

–

Synch break detection

Optional baudrate update

Synchronization Validation

2³¹programmable transmission rates with 7 fractional bits

•

Error detection

2 Interrupt lines with priority encoding

Peripheral Information

123

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.8 Serial Communication Interface (SCI)

7.8.1 Features

•

Standard universal asynchronous receiver-transmitter (UART) communication

Supports full- or half-duplex operation

Standard nonreturn to zero (NRZ) format

Double-buffered receive and transmit functions

Configurable frame format of 3 to 13 bits per character based on the following:

–

Data word length programmable from one to eight bits

Additional address bit in address-bit mode

Parity programmable for zero or one parity bit, odd or even parity

Stop programmable for one or two stop bits

•

Asynchronous or isosynchronous communication modes

Two multiprocessor communication formats allow communication between more than two devices.

Sleep mode is available to free CPU resources during multiprocessor communication.

The 24-bit programmable baud rate supports 2²⁴different baud rates provide high accuracy baud rate

selection.

•

Four error flags and Five status flags provide detailed information regarding SCI events.

Capability to use DMA for transmit and receive data.

124

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.9 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module is a multi-master communication module providing an interface

between the microcontroller and devices compliant with Philips Semiconductor I2C-bus specification

version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible

device.

7.9.1 Features

The I2C has the following features:

•

Compliance to the Philips I2C bus specification, v2.1 (The I²C Specification, Philips document number

9398 393 40011)

–

Bit/Byte format transfer

7-bit and 10-bit device addressing modes

General call

START byte

Multi-master transmitter/ slave receiver mode

Multi-master receiver/ slave transmitter mode

Combined master transmit/receive and receive/transmit mode

Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)

•

Free data format

Two DMA events (transmit and receive)

DMA event enable/disable capability

Seven interrupts that can be used by the CPU

Module enable/disable capability

The SDA and SCL are optionally configurable as general purpose I/O

Slew rate control of the outputs

Open drain control of the outputs

Programmable pullup/pulldown capability on the inputs

Supports Ignore NACK mode

注

This I2C module does not support:

•

High-speed (HS) mode

C-bus compatibility mode

The combined format in 10-bit address mode (the I²C sends the slave address second

byte every time it sends the slave address first byte)

Peripheral Information

125

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.9.2 I²C I/O Timing Specifications

表 7-19. I²C Signals (SDA and SCL) Switching Characteristics⁽¹⁾

STANDARD MODE

FAST MODE

MIN MAX

PARAMETER

UNIT

MIN

MAX

t_c(I2CCLK)

Cycle time, internal module clock for I²C,

prescaled from VCLK

75.2

149

75.2

149

ns

f_(SCL)

SCL clock frequency

Cycle time, SCL

0

10

100

0

2.5

0.6

400

kHz

µs

t_c(SCL)

t_{su(SCLH-SDAL)}

Setup time, SCL high before SDA low (for a

repeated START condition)

4.7

µs

t_h(SCLL-SDAL)

Hold time, SCL low after SDA low (for a repeated

START condition)

4

0.6

µs

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_su(SDA-SCLH)

t_h(SDA-SCLL)

Setup time, SDA valid before SCL high

250

0

Hold time, SDA valid after SCL low (for I2C bus

devices)

3.45⁽²⁾

0.9

t_w(SDAH)

Pulse duration, SDA high between STOP and

START conditions

4.7

4.0

1.3

0.6

0

µs

t_{su(SCLH-SDAH)}

Setup time, SCL high before SDA high (for STOP

condition)

t_w(SP)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

50

ns

(3)

C_b

400

pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) The maximum t_h(SDA-SCLL)for I2C bus devices has only to be met if the device does not stretch the low period (t_w(SCLL)) of the SCL

signal.

(3) C_b= The total capacitance of one bus line in pF.

SDA

t_w(SDAH)

t_su(SDA-SCLH)

t_w(SP)

t_w(SCLL)

t_r(SCL)

t_{su(SCLH-SDAH)}

t_w(SCLH)

SCL

t_c(SCL)

t_h(SCLL-SDAL)

t_f(SCL)

t_h(SCLL-SDAL)

t_{su(SCLH-SDAL)}

t_h(SDA-SCLL)

Stop

Start

Repeated Start

Stop

图 7-9. I²C Timings

126

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

注

•

A device must internally provide a hold time of at least 300 ns for the SDA signal

(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling

edge of SCL.

•

The maximum t_h(SDA-SCLL)has only to be met if the device does not stretch the LOW

period (t_w(SCLL)) of the SCL signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the

requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if

the device does not stretch the LOW period of the SCL signal. If such a device does

stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line

tr max + t_su(SDA-SCLH)

.

•

C_b= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-

times are allowed.

Peripheral Information

127

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.10 Multi-Buffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of

programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate.

Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display

drivers, and analog-to-digital converters.

7.10.1 Features

Both Standard and MibSPI modules have the following features:

•

16-bit shift register

Receive buffer register

5-bit baud clock generator

SPICLK can be internally-generated (master mode) or received from an external clock source (slave

mode)

•

Each word transferred can have a unique format

SPI I/Os not used in the communication can be used as digital input/output signals

表 7-20. MibSPI/SPI Configurations

MibSPIx/SPIx

MibSPI1

I/Os

MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:0], MIBSPI1nENA

MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA

MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA

SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA

MibSPI3

MibSPI5

SPI2

SPI4

SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA

7.10.2 MibSPI Transmit and Receive RAM Organization

The Multibuffer RAM is comprised of 128 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a

16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer

RAM can be partitioned into multiple transfer group with variable number of buffers each.

7.10.3 MibSPI Transmit Trigger Events

Each of the transfer groups can be configured individually. For each of the transfer groups a trigger event

and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low

level at a selectable trigger source. For example, up to 15 trigger sources are available which can be

utilized by each transfer group. These trigger options are listed in 表 7-21 for MIBSPI1, 节 7.10.3.2 for

MIBSPI3 and 节 7.10.3.3 for MibSPI5.

128

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.10.3.1 MIBSPI1 Event Trigger Hookup

表 7-21. MIBSPI1 Event Trigger Hookup

Event Number

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Internal Tick counter

space

注

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

注

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

7.10.3.2 MIBSPI3 Event Trigger Hookup

表 7-22. MIBSPI3 Event Trigger Hookup

Event Number

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

TGxCTRL TRIGSRC[3:0]

Trigger

No trigger source

GIOA[0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

Peripheral Information

129

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 7-22. MIBSPI3 Event Trigger Hookup (continued)

Event Number

EVENT8

TGxCTRL TRIGSRC[3:0]

Trigger

1001

1010

1011

1100

1101

1110

1111

HET[8]

EVENT9

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

Internal Tick counter

注

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

注

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin plus selecting the pin to be a GIOx pin, or by driving

the GIOx pin from an external trigger source. If the mux control module is used to select

different functionality instead of the GIOx signal, then care must be taken to disable GIOx

from triggering MibSPI3 transfers; there is no multiplexing on the input connections.

7.10.3.3 MIBSPI5 Event Trigger Hookup

表 7-23. MIBSPI5 Event Trigger Hookup

Event Number

Disabled

EVENT0

EVENT1

EVENT2

EVENT3

EVENT4

EVENT5

EVENT6

EVENT7

EVENT8

EVENT9

EVENT10

EVENT11

EVENT12

EVENT13

EVENT14

TGxCTRL TRIGSRC[3:0]

Trigger

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

No trigger source

GIOA[0]

GIOA[1]

GIOA[2]

GIOA[3]

GIOA[4]

GIOA[5]

GIOA[6]

GIOA[7]

N2HET1[8]

N2HET1[10]

N2HET1[12]

N2HET1[14]

N2HET1[16]

N2HET1[18]

Internal Tick counter

注

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made

from the input side of the output buffer (at the N2HET1 module boundary). This way, a

trigger condition can be generated even if the N2HET1 signal is not selected to be output on

the pad.

130

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

注

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from

the output side of the input buffer. This way, a trigger condition can be generated either by

selecting the GIOx pin as an output pin + selecting the pin to be a GIOx pin, or by driving the

GIOx pin from an external trigger source. If the mux control module is used to select different

functionality instead of the GIOx signal, then care must be taken to disable GIOx from

triggering MibSPI5 transfers; there is no multiplexing on the input connections.

Peripheral Information

131

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications

表 7-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO =

output, and SPISOMI = input)^(1)(2)(3)

NO.

MIN

40

MAX UNIT

256t_c(VCLK)ns

1

t_c(SPC)M

Cycle time, SPICLK⁽⁴⁾

2⁽⁵⁾t_w(SPCH)M

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high

(clock polarity = 0)

–40°C to 125°C

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M+ 3 ns

Pulse duration, SPICLK low

(clock polarity = 1)

0.5t_c(SPC)M– t_f(SPC)M– 3

0.5t_c(SPC)M– t_r(SPC)M– 3

0.5t_c(SPC)M– 6

0.5t_c(SPC)M+ 3

0.5t_c(SPC)M+ 3 ns

0.5t_c(SPC)M+ 3

ns

Pulse duration, SPICLK low

(clock polarity = 0)

Pulse duration, SPICLK high

(clock polarity = 1)

4⁽⁵⁾t_d(SPCH-

Delay time, SPISIMO valid

before SPICLK low (clock

polarity = 0)

SIMO)M

t_d(SPCL-

SIMO)M

Delay time, SPISIMO valid

before SPICLK high (clock

polarity = 1)

0.5t_c(SPC)M– 6

0.5t_c(SPC)M– t_f(SPC)– 4

0.5t_c(SPC)M– t_r(SPC)– 4

5⁽⁵⁾t_v(SPCL-

Valid time, SPISIMO data valid

after SPICLK low (clock polarity

= 0)

ns

SIMO)M

t_v(SPCH-

SIMO)M

Valid time, SPISIMO data valid

after SPICLK high (clock polarity

= 1)

6⁽⁵⁾t_su(SOMI-

SPCL)M

Setup time, SPISOMI before

SPICLK low (clock polarity = 0)

t_f(SPC)+ 2.2

t_r(SPC)+ 2.2

10

ns

t_su(SOMI-

SPCH)M

7⁽⁵⁾t_h(SPCL-

SOMI)M

Setup time, SPISOMI before

SPICLK high (clock polarity = 1)

Hold time, SPISOMI data valid

after SPICLK low (clock polarity

= 0)

t_h(SPCH-

SOMI)M

Hold time, SPISOMI data valid

after SPICLK high (clock polarity

= 1)

10

8⁽⁶⁾t_C2TDELAY

Setup time CS

active until SPICLK

high (clock polarity

= 0)

CSHOLD =

0

C2TDELAY*t_c(VCLK)

2*t_c(VCLK)- t_f(SPICS)

+

(C2TDELAY+2) * t_c(VCLK)

-

ns

t_f(SPICS)+ t_r(SPC)+ 5.5

t_r(SPC)– 7

CSHOLD =

1

C2TDELAY*t_c(VCLK)

3*t_c(VCLK)- t_f(SPICS)

+

(C2TDELAY+3) * t_c(VCLK)

-

t_f(SPICS)+ t_r(SPC)+ 5.5

t_r(SPC)– 7

Setup time CS

active until SPICLK

low (clock polarity

= 1)

CSHOLD =

0

C2TDELAY*t_c(VCLK)

2*t_c(VCLK)- t_f(SPICS)

+

(C2TDELAY+2) * t_c(VCLK)

-

t_f(SPICS)+ t_f(SPC)+ 5.5

t_f(SPC)– 7

CSHOLD =

1

C2TDELAY*t_c(VCLK)

3*t_c(VCLK)- t_f(SPICS)

+

(C2TDELAY+3) * t_c(VCLK)

-

t_f(SPICS)+ t_f(SPC)+ 5.5

t_f(SPC)– 7

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see 表 5-6.

(4) When the SPI is in master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1) t_c(VCLK)≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40 ns.

The external load on the SPICLK pin must be less than 60 pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

132

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO =

output, and SPISOMI = input)^(1)(2)(3)(continued)

NO.

MIN

MAX UNIT

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS

inactive (clock polarity = 0)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

+

-

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)+ t_r(SPICS)

+ 11

+

ns

7

Hold time SPICLK high until CS

inactive (clock polarity = 1)

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)

+

0.5*t_c(SPC)M

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)+ t_r(SPICS)

+ 11

+

ns

tr(SPICS) - 7

(C2TDELAY+1) * t_c(VCLK)

t_f(SPICS)– 29

10 t_SPIENA

SPIENAn Sample point

-

(C2TDELAY+1)*t_c(VCLK)ns

11 t_SPIENAW

SPIENAn Sample point from

write to buffer

–40°C to 125°C

(C2TDELAY+2)*t_c(VCLK)ns

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

6

7

Master In Data

Must Be Valid

SPISOMI

图 7-10. SPI Master Mode External Timing (CLOCK PHASE = 0)

Peripheral Information

133

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

Master Out Data Is Valid

8

9

SPICSn

10

11

SPIENAn

图 7-11. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)

134

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-25. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO =

output, and SPISOMI = input)^(1)(2)(3)

NO.

MIN

MAX UNIT

256t_c(VCLK)ns

(4)

1

t_c(SPC)M

Cycle time, SPICLK

40

2⁽⁵⁾t_w(SPCH)M

t_w(SPCL)M

3⁽⁵⁾t_w(SPCL)M

t_w(SPCH)M

Pulse duration, SPICLK high (clock –40°C to 125°C

polarity = 0)

0.5t_c(SPC)M– t_r(SPC)M

–

3

0.5t_c(SPC)M+ 3 ns

Pulse duration, SPICLK low (clock

polarity = 1)

–40°C to 125°C

0.5t_c(SPC)M– t_f(SPC)M

0.5t_c(SPC)M– t_r(SPC)M

–

3

0.5t_c(SPC)M+ 3

0.5t_c(SPC)M+ 3 ns

0.5t_c(SPC)M+ 3

ns

Pulse duration, SPICLK low (clock

polarity = 0)

–40°C to 125°C

–

3

Pulse duration, SPICLK high (clock –40°C to 125°C

polarity = 1)

–

3

4⁽⁵⁾t_{v(SIMO-SPCH)M}

Valid time, SPICLK high after

0.5t_c(SPC)M– 6

SPISIMO data valid (clock polarity =

0)

t_{v(SIMO-SPCL)M}

Valid time, SPICLK low after

0.5t_c(SPC)M– 6

SPISIMO data valid (clock polarity =

1)

5⁽⁵⁾t_{v(SPCH-SIMO)M}

t_{v(SPCL-SIMO)M}

6⁽⁵⁾t_{su(SOMI-SPCH)M}

t_{su(SOMI-SPCL)M}

7⁽⁵⁾t_{v(SPCH-SOMI)M}

t_{v(SPCL-SOMI)M}

Valid time, SPISIMO data valid after

SPICLK high (clock polarity = 0)

0.5t_c(SPC)M– t_r(SPC)– 4

ns

Valid time, SPISIMO data valid after

SPICLK low (clock polarity = 1)

0.5t_c(SPC)M– t_f(SPC)– 4

Setup time, SPISOMI before

SPICLK high (clock polarity = 0)

t_r(SPC)+ 2.2

t_f(SPC)+ 2.2

10

Setup time, SPISOMI before

SPICLK low (clock polarity = 1)

Valid time, SPISOMI data valid after

SPICLK high (clock polarity = 0)

Valid time, SPISOMI data valid after

SPICLK low (clock polarity = 1)

10

8⁽⁶⁾t_C2TDELAY

Setup time CS active

until SPICLK high

(clock polarity = 0)

CSHOLD

= 0

0.5*t_c(SPC)M

(C2TDELAY+2) *

t_c(VCLK)- t_f(SPICS)

t_r(SPC)– 7

+

0.5*t_c(SPC)M

(C2TDELAY+2) *

t_c(VCLK)- t_f(SPICS)

t_r(SPC)+ 5.5

+

ns

+

CSHOLD

= 1

0.5*t_c(SPC)M

(C2TDELAY+3) *

t_c(VCLK)- t_f(SPICS)

t_r(SPC)– 7

+

0.5*t_c(SPC)M

(C2TDELAY+3) *

t_c(VCLK)- t_f(SPICS)

t_r(SPC)+ 5.5

+

Setup time CS active

until SPICLK low (clock

polarity = 1)

CSHOLD

= 0

0.5*t_c(SPC)M

(C2TDELAY+2) *

t_c(VCLK)- t_f(SPICS)

t_f(SPC)– 7

+

0.5*t_c(SPC)M

(C2TDELAY+2) *

t_c(VCLK)- t_f(SPICS)

t_f(SPC)+ 5.5

+

ns

+

CSHOLD

= 1

0.5*t_c(SPC)M

(C2TDELAY+3) *

t_c(VCLK)- t_f(SPICS)

t_f(SPC)– 7

+

0.5*t_c(SPC)M

(C2TDELAY+3) *

t_c(VCLK)- t_f(SPICS)

t_f(SPC)+ 5.5

+

9⁽⁶⁾t_T2CDELAY

Hold time SPICLK low until CS

inactive (clock polarity = 0)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_f(SPC)

+

ns

t_r(SPICS)- 7

t_r(SPICS)+ 11

Hold time SPICLK high until CS

inactive (clock polarity = 1)

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)

+

T2CDELAY*t_c(VCLK)

t_c(VCLK)- t_r(SPC)

+

t_r(SPICS)- 7

t_r(SPICS)+ 11

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) t_c(VCLK)= interface clock cycle time = 1 / f_(VCLK)

(3) For rise and fall timings, see the 表 5-6.

(4) When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)M≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)M= 2t_c(VCLK)≥ 40ns.

The external load on the SPICLK pin must be less than 60pF.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Peripheral Information

135

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

表 7-25. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO =

output, and SPISOMI = input)^(1)(2)(3)(continued)

NO.

MIN

MAX UNIT

10 t_SPIENA

SPIENAn Sample Point

(C2TDELAY+1)* (C2TDELAY+1)*t_c(VCLK)ns

t_c(VCLK)- t_f(SPICS)– 29

11 t_SPIENAW

SPIENAn Sample point from write to –40°C to 125°C

buffer

(C2TDELAY+2)*t_c(VCLK)ns

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

Master Out Data Is Valid

Data Valid

SPISIMO

SPISOMI

6

7

Master In Data

Must Be Valid

图 7-12. SPI Master Mode External Timing (CLOCK PHASE = 1)

Write to buffer

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

SPISIMO

SPICSn

Master Out Data Is Valid

8

9

10

11

SPIENAn

图 7-13. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)

136

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.10.5 SPI Slave Mode I/O Timings

表 7-26. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

MIN

40

MAX UNIT

1

t_c(SPC)S

Cycle time, SPICLK⁽⁵⁾

ns

2⁽⁶⁾t_w(SPCH)S

t_w(SPCL)S

3⁽⁶⁾t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0) –40°C to 125°C

14

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

–40°C to 125°C

14

ns

Pulse duration, SPICLK high (clock polarity = 1) –40°C to 125°C

14

4⁽⁶⁾t_{d(SPCH-SOMI)S}

Delay time, SPISOMI valid after SPICLK high

(clock polarity = 0)

t_rf(SOMI)+ 20

ns

t_{d(SPCL-SOMI)S}

5⁽⁶⁾t_{h(SPCH-SOMI)S}

t_{h(SPCL-SOMI)S}

Delay time, SPISOMI valid after SPICLK low

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK

high (clock polarity =0)

2

4

2

Hold time, SPISOMI data valid after SPICLK low

(clock polarity =1)

6⁽⁶⁾t_{su(SIMO-SPCL)S}Setup time, SPISIMO before SPICLK low (clock

polarity = 0)

t_{su(SIMO-SPCH)S}Setup time, SPISIMO before SPICLK high (clock

polarity = 1)

7⁽⁶⁾t_{h(SPCL-SIMO)S}

Hold time, SPISIMO data valid after SPICLK low

(clock polarity = 0)

t_{h(SPCH-SIMO)S}

Hold time, SPISIMO data valid after S PICLK

high (clock polarity = 1)

8

9

t_{d(SPCL-SENAH)S}Delay time, SPIENAn high after last SPICLK low

(clock polarity = 0)

1.5t_c(VCLK)2.5t_c(VCLK)+t_r(ENA

_n)+ 22

t_{d(SPCH-SENAH)S}Delay time, SPIENAn high after last SPICLK

high (clock polarity = 1)

1.5t_c(VCLK)

2.5t_c(VCLK)

+

t_r(ENAn)+ 22

t_{d(SCSL-SENAL)S}Delay time, SPIENAn low after SPICSn low (if

new data has been written to the SPI buffer)

t_f(ENAn)t_c(VCLK)+t_f(ENAn)

+

27

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: t_c(SPC)S≥ (PS + 1) t_c(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see 表 5-6.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information

137

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI Data Is Valid

SPISOMI

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图 7-14. SPI Slave Mode External Timing (CLOCK PHASE = 0)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

图 7-15. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

138

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

表 7-27. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =

input, and SPISOMI = output)^(1)(2)(3)(4)

NO.

MIN

40

MAX UNIT

1

t_c(SPC)S

Cycle time, SPICLK⁽⁵⁾

ns

2⁽⁶⁾t_w(SPCH)S

t_w(SPCL)S

3⁽⁶⁾t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

–40°C to 125°C

14

ns

14

4⁽⁶⁾t_{d(SOMI-SPCL)S}

Dealy time, SPISOMI data valid after SPICLK low

(clock polarity = 0)

t_rf(SOMI)+ 20

ns

t_{d(SOMI-SPCH)S}

5⁽⁶⁾t_{h(SPCL-SOMI)S}

t_{h(SPCH-SOMI)S}

Delay time, SPISOMI data valid after SPICLK high

(clock polarity = 1)

Hold time, SPISOMI data valid after SPICLK high

(clock polarity =0)

2

4

2

Hold time, SPISOMI data valid after SPICLK low

(clock polarity =1)

6⁽⁶⁾t_{su(SIMO-SPCH)S}Setup time, SPISIMO before SPICLK high (clock

polarity = 0)

t_{su(SIMO-SPCL)S}Setup time, SPISIMO before SPICLK low (clock

polarity = 1)

7⁽⁶⁾t_{v(SPCH-SIMO)S}

High time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

t_{v(SPCL-SIMO)S}

High time, SPISIMO data valid after SPICLK low

(clock polarity = 1)

8

9

t_{d(SPCH-SENAH)S}Delay time, SPIENAn high after last SPICLK high

(clock polarity = 0)

1.5t_c(VCLK)2.5t_c(VCLK)+t_r(

_ENAn)+ 22

t_{d(SPCL-SENAH)S}Delay time, SPIENAn high after last SPICLK low

(clock polarity = 1)

1.5t_c(VCLK)2.5t_c(VCLK)+t_r(

_ENAn)+ 22

t_{d(SCSL-SENAL)S}Delay time, SPIENAn low after SPICSn low (if new

data has been written to the SPI buffer)

t_f(ENAn)t_c(VCLK)+t_f(ENA

_n)+ 27

ns

10 t_{d(SCSL-SOMI)S}

Delay time, SOMI valid after SPICSn low (if new

data has been written to the SPI buffer)

t_c(VCLK)2t_c(VCLK)+t_rf(S

_OMI)+ 28

(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.

(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].

(3) For rise and fall timings, see 表 5-6.

(4) t_c(VCLK)= interface clock cycle time = 1 /f_(VCLK)

(5) When the SPI is in Slave mode, the following must be true:

For PS values from 1 to 255: t_c(SPC)S≥ (PS +1)t_c(VCLK)≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: t_c(SPC)S= 2t_c(VCLK)≥ 40ns.

(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

Peripheral Information

139

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

5

4

SPISOMI

SPISOMI Data Is Valid

6

7

SPISIMO Data

Must Be Valid

SPISIMO

图 7-16. SPI Slave Mode External Timing (CLOCK PHASE = 1)

SPICLK

(clock polarity=0)

SPICLK

(clock polarity=1)

8

SPIENAn

SPICSn

9

10

SPISOMI

Slave Out Data Is Valid

图 7-17. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)

140

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.11 Ethernet Media Access Controller

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the CPU and the

network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps

in either half- or full-duplex mode, with hardware flow control and quality of service (QoS) support.

The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY

configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the device through a custom interface that allows

efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

multiplex and control interrupts.

7.11.1 Ethernet MII Electrical and Timing Specifications

1

2

MII_MRCLK

MII_MRXD

MII_MRXDV

MII_MRXER

VALID

图 7-18. MII Receive Timing

表 7-28. MII Receive Timing

MIN

8

MAX

UNIT

ns

t_su(MIIMRXD)

t_su(MIIMRXDV)

t_su(MIIMRXER)

t_h(MIIMRXD)

Setup time, MIIMRXD to MIIMRCLK rising edge

Setup time, MIIMRXDV to MIIMRCLK rising edge

Setup time, MIIMRXER to MIIMRCLK rising edge

Hold time, MIIMRXD valid after MIIRCLK rising edge

Hold time, MIIMRXDV valid after MIIRCLK rising edge

8

ns

8

ns

8

ns

t_h(MIIMRXDV)

t_h(MIIMRXER)

8

ns

8

ns

Peripheral Information

141

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

1

MII_MTCLK

MII_MTXD

VALID

MII_MTXEN

图 7-19. MII Transmit Timing

表 7-29. MII Transmit Timing

MIN

5

MAX

25

UNIT

ns

t_d(MIIMTXD)

Delay time, MIIMTCLK rising edge to MIIMTXD

Delay time, MIIMTCLK rising edge to MIIMTXEN

t_d(MIIMTXEN)

5

25

ns

142

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

7.11.2 Ethernet RMII Timing

1

2

3

RMII_MHz_50_CLK

5

RMII_TXEN

4

RMII_TXD[1:0]

6

7

RMII_RXD[1:0]

RMII_CRS_DV

9

8

10

11

RMII_RXER

图 7-20. RMII Timing Diagram

表 7-30. RMII Timing Requirements

NO.

MIN

—

7

NOM

20

MAX

—

UNIT

ns

1

2

3

6

tc(REFCLK)

Cycle time, RMII_REF_CLK

tw(REFCLKH)

tw(REFCLKL)

tsu(RXD-REFCLK)

Pulse width, RMII_REF_CLK High

Pulse width, RMII_REF_CLK Low

—

13

ns

7

—

13

ns

Input setup time, RMII_RXD valid before

RMII_REF_CLK High

4

—

ns

7

8

th(REFCLK-RXD)

Input hold time, RMII_RXD valid after

RMII_REF_CLK High

2

4

2

4

2

—

ns

tsu(CRSDV-REFCLK)

th(REFCLK-CRSDV)

tsu(RXER-REFCLK)

th(REFCLK-RXER)

td(REFCLK-TXD)

Input setup time, RMII_CRSDV valid before

RMII_REF_CLK High

9

Input hold time, RMII_CRSDV valid after

RMII_REF_CLK High

10

11

4

Input setup time, RMII_RXER valid before

RMII_REF_CLK High

Input hold time, RMII_RXER valid after

RMII_REF_CLK High

Output delay time, RMII_REF_CLK High to

RMII_TXD valid

5

td(REFCLK-TXEN)

Output delay time, RMII_REF_CLK High to

RMII_TX_EN valid

Peripheral Information

143

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

7.11.3 Management Data Input/Output (MDIO)

1

3

MDCLK

4

5

MDIO

(input)

图 7-21. MDIO Input Timing

表 7-31. MDIO Input Timing Requirements

NO.

1

MIN

400

180

—

MAX

UNIT

ns

tc(MDCLK)

tw(MDCLK)

tt(MDCLK)

Cycle time, MDCLK

—

5

2

Pulse duration, MDCLK high/low

ns

3

Transition time, MDCLK

–40°C to 125°C

ns

4

tsu(MDIO-

MDCLKH)

Setup time, MDIO data input valid before MDCLK high

33⁽¹⁾

—

ns

5

th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high

10

—

ns

(1) This is a discrepancy to IEEE 802.3, but is compatible with many PHY devices.

1

MDCLK

7

MDIO

(output)

图 7-22. MDIO Output Timing

表 7-32. MDIO Output Timing Requirements

NO.

1

MIN

400

–7

MAX

—

UNIT

ns

tc(MDCLK)

Cycle time, MDCLK

7

td(MDCLKL-MDIO)

Delay time, MDCLK low to MDIO data output valid

100

ns

144

Peripheral Information

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

8 Device and Documentation Support

8.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

devices. Each commercial family member has one of three prefixes: TMX, TMP, or TMS (for example,

TMS570LS3137). These prefixes represent evolutionary stages of product development from engineering

prototypes (TMX) through fully qualified production devices/tools (TMS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications.

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

Fully-qualified production device.

TMX and TMP devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices have been characterized fully, and the quality and reliability of the device have been

demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

Device and Documentation Support

145

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

Full Part Number

TMS

570

LS 31

31

3

7

C

GWT

Q

EP

Orderable Part Number

Prefix: TM

TMS = Fully Qualified

TMP = Prototype

TMX = Samples

Core Technology:

570 = Cortex R4F

Architecture:

LS = Dual CPUs in Lockstep

(not included in orderable part number)

Flash Memory Size:

31 = 3MB

RAM MemorySize:

3 = 256kB

Peripheral Set:

7 = FlexRay, Ethernet

Die Revision:

Blank = Initial Die

A = First Die Revision

B = Second Die Revision

C = Third Die Revision

Package Type:

GWT = 337 BGA Package

Temperature Range:

Q = –40 to 125^oC

M = –55 to 125^oC

Quality Designator:

EP = HiRel

图 8-1. TMS570LS3137-EP Device Numbering Conventions

146

Device and Documentation Support

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

8.2 Documentation Support

8.2.1 Related Documentation from Texas Instruments

The following documents describe the TMS570LS3137-EP microcontroller.

SPNU499

TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference

Manual details the integration, the environment, the functional description, and the

programming models for each peripheral and subsytem in the device.

SPNZ195

TMS570LS31x/21x Microcontroller Silicon Errata (Silicon Revision C) describes the

known exceptions to the functional specifications for the device silicon revision(s).

8.2.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术

规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。

TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在

e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。

德州仪器 (TI) 嵌入式处理器维基网站德州仪器 (TI) 嵌入式处理器维基网站。此网站的建立是为了帮助开发

人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体

知识的创新和增长。

8.3 商标

E2E is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

8.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

8.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

提交文档反馈意见

Device and Documentation Support

147

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

8.6 Device Identification

8.6.1 Device Identification Code Register

The device identification code register identifies several aspects of the device including the silicon version.

The details of the device identification code register are shown in 表 8-1. The device identification code

register value for this device is:

•

Rev A = 0x802AAD05

Rev B = 0x802AAD15

Rev C = 0x802AAD1D

图 8-2. Device ID Bit Allocation Register

31

CP-15

R-1

30

22

29

21

13

28

27

26

18

10

25

17

9

24

UNIQUE ID

R-0000000

23

20

19

16

TECH

R-0

UNIQUE ID

R-0010101

15

14

12

11

8

TECH

I/O VOLTAGE

PERIPH

PARITY

FLASH ECC

R-10

RAM ECC

R-101

6

R-0

4

R-1

3

R-1

7

5

2

1

0

1

VERSION

R-00000

R-1

R-0

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 8-1. Device ID Bit Allocation Register Field Descriptions

Bit

Field

Value

Description

31

CP15

Indicates the presence of coprocessor 15

CP15 present

1

30-17

UNIQUE ID

10101

Silicon version (revision) bits.

This bitfield holds a unique number for a dedicated device configuration (die).

16-13

12

TECH

Process technology on which the device is manufactured.

0101

0

F021

I/O VOLTAGE

I/O voltage of the device.

I/O are 3.3v

11

PERIPHERAL

PARITY

Peripheral Parity

1

10

1

Parity on peripheral memories

Flash ECC

10-9

8

FLASH ECC

RAM ECC

Program memory with ECC

Indicates if RAM memory ECC is present.

ECC implemented

7-3

2-0

REVISION

101

Revision of the Device.

The platform family ID is always 0b101

148

Device and Documentation Support

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

8.6.2 Die Identification Registers

The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a

128-bit dieid with the information as shown in 表 8-2.

表 8-2. Die-ID Registers

Item

Number of Bits

Bit Location

0xFFFFE1F0[11:0]

X-coordinate on wafer

Y-coordinate on wafer

Wafer number

Lot number

12

8

0xFFFFE1F0[23:12]

0xFFFFE1F0[31:24]

24

72

0xFFFFE1F4[23:0]

Reserved

0xFFFFE1F4[31:24], 0xFFFFE1F8[31:0], 0xFFFFE1FC[31:0]

Device and Documentation Support

149

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

8.7 Module Certifications

The following communications modules have received certification of adherence to a standard.

150

Device and Documentation Support

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

FlexRay™ Certifications

图 8-3. Flexray Certification for GWT Package

Device and Documentation Support

151

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

www.ti.com.cn

DCAN Certification

图 8-4. DCAN Certification

152

Device and Documentation Support

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

TMS570LS3137-EP

www.ti.com.cn

ZHCSBS0C –OCTOBER 2013–REVISED JANUARY 2015

9 Mechanical, Packaging, and Orderable Information

9.1 Packaging Information

The following packaging information reflects the most current released data available for the designated

device(s). This data is subject to change without notice and without revision of this document.

Mechanical, Packaging, and Orderable Information

153

提交文档反馈意见

产品主页链接: TMS570LS3137-EP

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

TMS5703137CGWTME

P

GWT

NFBGA

337

90

6 X 15

150

315 135.9 7620

20

17.5 15.45

TMS5703137CGWTQEP

V62/13629-01XE

GWT

NFBGA

337

90

6 X 15

150

315 135.9 7620

20

17.5 15.45

V62/13629-02XE

Pack Materials-Page 1

PACKAGE OUTLINE

GWT0337A

NFBGA - 1.4 mm max height

S

C

A

L

E

1

.

0

PLASTIC BALL GRID ARRAY

16.1

15.9

A

B

BALL A1

CORNER

16.1

15.9

0.95

0.84

0.23

0.15

C

SEATING PLANE

0.12 C

1.40

1.19

14.4 TYP

SYMM

0.45

0.35

(0.8)

W

V

U

T

(0.8)

R

P

N

M

L

SYMM

K

14.4 TYP

J

H

G

F

E

D

C

0.55

337X

0.45

0.15

0.05

C A B

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

0.8 TYP

4229175/A 11/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

GWT0337A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

337X ( 0.4)

(0.8) TYP

9

10

11

12 13

14

15

16

17

18

19

7

8

1

2

3

4

5

6

A

B

C

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

U

V

W

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 7X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL UNDER

SOLDER MASK

EXPOSED METAL

(

0.4)

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

METAL EDGE

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4229175/A 11/2022

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).

www.ti.com

EXAMPLE STENCIL DESIGN

GWT0337A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

337X ( 0.4)

(0.8) TYP

9

10

11

12 13

14

15

16

17

18

19

7

8

1

2

3

4

5

6

A

B

C

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

U

V

W

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.150 mm THICK STENCIL

SCALE: 7X

4229175/A 11/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMS570LS3137-EP
厂家：	TEXAS INSTRUMENTS
描述：	增强型产品 16/32 位 RISC 闪存 Arm Cortex-R4F、EMAC、FlexRay 闪存
文件：	总160页 (文件大小：6061K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS570LS3137-EP [TI]

相关型号：

TMS570LS3137_12

TMS570LS31_12

TMS570_14

TMS57535A

TMS62256L-10DH

TMS62256L-10NW

TMS62256L-12DH

TMS62256L-12NW

TMS62256L-15DH

TMS62256L-15NW

TMS62256L-85DH

TMS62256L-85NW