TMS626162-12ADGE [TI]
1MX16 SYNCHRONOUS DRAM, 9ns, PDSO50, 0.400 INCH, PLASTIC, TSOP-50;
| 型号： | TMS626162-12ADGE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1MX16 SYNCHRONOUS DRAM, 9ns, PDSO50, 0.400 INCH, PLASTIC, TSOP-50 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总91页 (文件大小：486K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Technical
Reference
1996
MOS Memory Products
Printed in U.S.A., April 1996
SMOU002
TMS626162, TMS626812
16M-Bit Synchronous DRAMs
Technical Reference
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TIwarrantsperformanceofitssemiconductorproductsandrelatedsoftwaretothespecifications
applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright 1996, Texas Instruments Incorporated
Preface
Read This First
About This Manual
The purpose of this technical reference is to give you detailed operational in-
formation about Texas Instruments (TI ) synchronous dynamic random-ac-
cess memories (SDRAMs). It is intended to be used with the specific device
data sheets (listed below), which contain the electrical characteristics, operat-
ing requirements and conditions, as well as timing and switching information.
Notational Conventions
This document uses the following conventions:
The TMS626162 and TMS626812 SDRAM devices are included by the
term TMS626xx2.
The TMS626xx2 devices are available as TMS626xx2-12 and
TMS626xx2-15. Throughout this document, the device speed indicator is
used as an abbreviation of the full device name and applies to the
TMS626162 and the TMS626812 (for example, the -15 specification al-
lows read latency of one, two, or three cycles to be used).
Related Documentation From Texas Instruments
The following data sheets describe the Synchronous DRAM and related sup-
port tools. To obtain a copy of any of these TI documents, call the Texas Instru-
ments Literature Response Center at (800) 477–8924. When ordering, please
identify the data sheet by its title and literature number.
TMS626162 Synchronous DRAM Data Sheet (literature number
SMOS683B) describes the 512K-word by 16-bit by 2-bank SDRAM.
TMS626812 Synchronous DRAM Data Sheet (literature number SMOS687)
describes the 1M-word by 8-bit by 2-bank SDRAM.
TI is a trademark of Texas Instruments Incorporated.
Read This First
iii
Preface
Other Related Documentation
Configurations for Solid State Memories, JEDEC Standard No. 21-C, Re-
lease 4, Electronic Industries Association, November 1993.
If You Need Assistance. . .
If you want to. . .
Do this. . .
Order Texas Instruments
documentation
Call the TI Literature Response Center:
(800) 477–8924
Ask questions about product
operation or report suspected
problems
Call the Semiconductor Information Center:
(214) 644–5580
iv
Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
1.3
Synchronous DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Functional Comparison: SDRAM Versus DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Multiple Product Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
General Description of the 16M-Bit SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
2.3
2.4
Overview of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Two-Bank Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4.1 Two-Bank Row-Access Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4.2 Two-Bank Column-Access Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Bank Deactivation (Precharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Data/Output Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
CLK Suspend/Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Mode-Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.5
2.6
2.7
2.8
2.9
2.10 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.10.1 CAS-Before-RAS (CBR) Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.10.2 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.11 Interrupted Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.12 Design Comparison: JEDEC-Standard Versus TI’s SDRAM . . . . . . . . . . . . . . . . . . . . . 2-10
3
Detailed Operations on the 16M-Bit SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Seamless Read With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Read With Bank Interleaving – Random Row Address, Autodeactivate . . . . . . . . . . . . 3-9
Write With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Write With Bank Interleaving – Random Row Address, Autodeactivate . . . . . . . . . . . . 3-17
Read Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Read Burst Interrupted by a WRT Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Read Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
Read Burst Interrupted by a DEAC/DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.10 Write Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.11 Write Burst Interrupted by a WRT Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.12 Write Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
v
Contents
3.13 Write Burst Interrupted by a DEAC/DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
3.14 Single-Bit Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.15 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.16 Power-Down-Mode Entry — Both Banks Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.17 Power-Down-Mode Entry — Both Banks Deactivated . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.18 Self-Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.19 Data-Masking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
A
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
vi
Figures
2–1.
2–2.
3–1.
3–2.
3–3.
3–4.
3–5.
3–6.
3–7.
3–8.
3–9.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Mode-Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Seamless Read With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Read With Bank Interleaving – Random Row Address, Autodeactivate . . . . . . . . . . . . . . 3-11
Write With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Write With Bank Interleaving – Random Row Address, Autodeactivate . . . . . . . . . . . . . . 3-19
Read Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Read Burst Interrupted by a WRT Command in the Same Bank . . . . . . . . . . . . . . . . . . . . 3-24
Read Burst Interrupted by a WRT Command in a Different Bank . . . . . . . . . . . . . . . . . . . 3-25
Read Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3–10. Read Burst Interrupted by a DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3–11. Write Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3–12. Write Burst Interrupted by a WRT Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3–13. Write Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3–14. Write Burst Interrupted by a DEAC Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
3–15. Single-Bit Write (Read Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3–16. Clock Suspend During a Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3–17. Clock Suspend During a Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3–18. Power-Down-Entry Operation, Both Banks Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3–19. Power-Down-Entry Operation, Both Banks Deactivated . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3–20. Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
3–21. Data-Masking Operation (TMS626812) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
3–22. Data-Masking Operation With Upper- and Lower-Byte Control (TMS626162) . . . . . . . . 3-52
Contents
vii
Tables
1–1.
1–2.
1–3.
2–1.
2–2.
2–3.
Functional Differences Between the DRAM and the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Raw Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
TMS626xx2 Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Bit-Burst Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Read Latencies for Different Operating Frequencies and Clock Speeds . . . . . . . . . . . . . . 2-4
Comparison of JEDEC-Standard Features With Features on TI’s TMS626162 and
TMS626812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2–4.
Comparison of Pipeline and Prefetch Versus JEDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
viii
Chapter 1
Introduction
This chapter introduces the synchronous dynamic random-access memory
(SDRAM) and compares it with the standard DRAM.
Topic
Page
1.1 Synchronous DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Comparison: SDRAM Versus DRAM . . . . . . . . . . . . . . . . . 1-2
1.3 Multiple Product Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1-1
Synchronous DRAM/Functional Comparison: SDRAM Versus DRAM
1.1 Synchronous DRAM
As the speed of processors and memory buses continues to increase, the
speed of the standard DRAM (dynamic random-access memory) becomes in-
creasingly inadequate. In order to improve the overall system performance,
the DRAM operations have been synchronized to the system clock, creating
asynchronousDRAM(SDRAM). Thisdocument, inconjunctionwiththeTexas
†
Instruments TMS626xx2 16M-bit SDRAM data sheets (see related docu-
ments in the preface), helps you use SDRAMs efficiently.
1.2 Functional Comparison: SDRAM Versus DRAM
Some major differences between the SDRAM and the DRAM make the
SDRAM easier to control than the DRAM. There are also functional differ-
ences, some of which are summarized in Table 1–1.
Table 1–1.Functional Differences Between the DRAM and the SDRAM
DRAM
No system clock
SDRAM
Runs off system clock
Pulsed RAS control
Level RAS control
1-bank operation
2 banks for on-chip interleaving
1 transfer per column address
Burst of 1, 2, 4, 8 or 256 transfers per column
address
Read latency is nonprogrammable Read latency is programmable
A DRAM is an asynchronous device. Systems using DRAMs are required to
incorporate wait states that match the performance specifications of the
DRAM. Timing of commands is dependent upon the speed of the DRAM and
not necessarily upon system speeds. To facilitate better interaction between
theSDRAMandthesystem, allcommandsarereferencedtothesystemclock;
therefore, the wait-state times needed to match the asynchronous DRAM tim-
ing with the system clock are avoided.
TokeepaDRAMrowactive, itisnecessarytoprovidecircuitrytoholdRASlow.
Precharge of the row is initiated by bringing RAS high. The SDRAM accepts
commands on the rising edge of the system clock. To activate a row, RAS
needs to be held low only for the setup and hold times relative to that clock
edge. To deactivate the row, a deactivate command is given on a rising clock
edge. The deactivate command initiates the precharge of the row. The pulsed
RASallowstheSDRAMtohavetwoindependentmemorybanksonthedevice
with only one RAS terminal.
†
TMS626xx2 devices are compatible with the low-voltage TTL (LVTTL) interface.
1-2
Synchronous DRAM/Functional Comparison: SDRAM Versus DRAM
The two independent banks allow each SDRAM to have two different rows ac-
tive at the same time. This allows the reading or writing of data to one bank
while the other is being readied. The delay normally associated with precharg-
ing and activating a row can be hidden by interleaving the bank accesses.
The SDRAM can achieve a greater data throughput than a DRAM (see
Table 1–2). One reason for this is the bursting capability of the SDRAM. The
SDRAM can burst a series of addresses (1, 2, 4, 8, or 256) based on a given
starting address. The length of the burst can be programmed by the system.
UnlikeconventionalDRAMs, whichrequirethateachaddressfetchbeinitiated
by a column address sent to the chip, up to 256 consecutive addresses can
be fetched internally before another column address has to be sent, unlike
conventional DRAMs, which require that each address fetch be initiated by a
column address sent to the chip. This allows consecutive addresses to be
transferred sequentially in a very short period of time after the initial column
address has been sent. This means that any time data is being transferred in
sequential blocks, the SDRAM performs at a much faster rate than a conven-
tional DRAM. The SDRAM also uses a wider internal data bus to achieve the
greater data rate.
The amount of time needed to have valid data output from a DRAM depends
on when the column-address command is given. This causes the system con-
trol to be more complicated and can cause delay to accommodate the various
timings. The SDRAM has the delay between column entry and data valid pro-
grammed by the system; this is known as the readlatency. Read latency is pro-
grammed to be from one to three clock cycles. The read latency used for a giv-
en system depends on the frequency of the system clock.
Table 1–2.Raw Data Throughput
Bytes Per Transfer
SDRAM Time Delay (ns)
DRAM Time Delays (ns)
2
4
70
82
60
100
8
106
154
250
442
826
1594
180
16
32
64
128
256
340
660
1300
2580
5140
Introduction
1-3
Multiple Product Offerings
1.3 Multiple Product Offerings
The shaded area in Table 1–3 indicates that this technical reference is applica-
ble to these part numbers.
Table 1–3.TMS626xx2 Product Information
Device Description
Part
Number
Supply
Voltage
Maximum
Speed
Organization
4Mx4
Architecture
Refresh
4K
Banks
TMS626402
TMS626802
TMS626162
TMS626812
3.3 V
3.3 V
3.3 V
3.3 V
2-bit prefetch
2-bit prefetch
Pipeline
2
2
2
2
100 MHz
100 MHz
83 MHz
83 MHz
2Mx8
4K
1Mx16
2Mx8
4K
Pipeline
4K
NOTE: Thin small-outline package (TSOP)
1-4
Chapter 2
General Description of the 16M-Bit SDRAM
This chapter contains an overview of the SDRAM and its functions.
Topic
Page
2.1 Overview of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 Two-Bank Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 Bank Deactivation (Precharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 Data/Output Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8 CLK Suspend/Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.9 Mode-Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.10 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.11 Interrupted Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.12 Design Comparison: JEDEC-Standard Versus TI’s SDRAM . . . . . . 2-10
2-1
Overview of the SDRAM
2.1 Overview of the SDRAM
The Texas Instruments SDRAM devices are high-speed 16777216-bit syn-
chronous dynamic random-access memories. All inputs and outputs are syn-
chronized with the system clock (CLK) input to simplify system design with
high-speedmicroprocessors. AllinputsoftheSDRAMarelatchedontherising
edge of CLK. The SDRAM outputs also are referenced to the rising edge of
CLK.
TheSDRAMarrayisdividedintotwobanks, whichareaccessedindependent-
ly. Either bank must be activated before it can be accessed (that is, read from
or written to). Refresh cycles refresh both banks alternately. Figure 2–1 is the
functional block diagram for the SDRAM.
Figure 2–1. Block Diagram
CLK
CKE
AND
Array Bank T
Array Bank B
CS
†
DQ
DQs
8 or 16
Buffer
DQM
RAS
CAS
W
Control
A0 – A11
12
Mode Register
†
DQML and DQMU for the TMS626162 SDRAM
The following basic commands or functions control most operations of the
SDRAM:
Row-address entry/bank activate
Column-address entry/write
Column-address entry/read
Bank deactivate
CAS-before-RAS (CBR) refresh
Self refresh
2-2
Overview of the SDRAM/Burst Sequence
In addition to these basic commands or functions, three methods control the
operation of the SDRAM:
CS to select/deselect the chip
DQM to enable/mask the DQ signals on a cycle-by-cycle basis. For the
x16 SDRAM, upper- and lower-byte control are used to enable and mask
DQ signals.
CKE to suspend (or gate) the CLK input
2.2 Burst Sequence
All data for the SDRAM is written or read in burst fashion. Given a single start-
ing address, the SDRAM internally accesses a sequence of locations based
on that starting address. Some of the subsequent accesses can be at preced-
ing column addresses and some can be at succeeding column addresses, de-
pending on the starting address entered. The sequence can be programmed
to follow either a serial- or an interleaved-burst sequence. The length of the
burst sequence is user-programmable to be any of 1, 2, 4, 8, or 256 accesses.
The TMS626162 and TMS626182 SDRAMs have a single-bit-write option.
This allows the user to program the SDRAM to read a burst of 1, 2, 4, 8, or 256
bits, but write a burst of only 1 bit. In the case where this option is not used,
the read and write burst lengths are equal.
Table 2–1.Bit-Burst Sequences
Internal Column Address A1 A0
Decimal
Binary
Burst Type
Serial
Start
2nd
1
3rd
2
4th
3
Start
00
01
10
11
2nd
01
10
11
3rd
10
11
00
01
10
11
00
01
4th
11
00
01
10
11
10
01
00
0
1
2
3
0
1
2
3
2
3
0
3
0
1
0
1
2
00
01
00
11
Interleaved
1
2
3
00
01
10
11
0
3
2
3
0
1
2
1
0
10
General Description of the 16M-Bit SDRAM
2-3
Latency
2.3 Latency
The delay between the read command (READ) and the first output burst is
known as the read latency (also referred to as CAS latency). The first data out-
put cycle of a read burst can be programmed to occur one, two, or three CLK
cycles after the read command. Minimum read latency is based on the particu-
lar maximum frequency rating of the SDRAM. This maximum frequency rating
is provided in the data sheet as the minimum clock period, t . Table 2–2 sum-
CK
marizes read-latency requirements for the two speeds of the TMS626162 and
TMS626812 SDRAMs.
Table 2–2.Read Latencies for Different Operating Frequencies and Clock Speeds
Device Speed Indicator
-12
-15
Clock
Clock
Speed Frequency Speed Frequency
Read Latency (Cycles)
(ns)
(MHz)
(ns)
(MHz)
1
2
3
36
≤28
40
≤25
18
≤56
20
≤50
12
≤83
15
≤66
For example, a -15 device can operate over three ranges of frequencies
(≤25 MHz, 25–50 MHz, and 50–66 MHz), but the allowable read latency in
each case is different. At frequencies of 25 MHz and below, the -15 specifica-
tion allows a read latency of one, two, or three cycles to be used. At frequen-
cies between 25 MHz and 50 MHz, the read latency can be either two or three
cycles. Finally, at frequencies between 50 MHz and 66 MHz, the read latency
must be three cycles. The programmable read-latency feature is provided to
allow efficient use of the SDRAM over a wide range of clock frequencies.
There is no latency for data-in cycles (write latency). The first data-in cycle of
a write burst is entered at the same rising edge of CLK on which the write com-
mand (WRT) is entered. Note that the write latency is fixed and is not deter-
mined by the contents of the mode register.
2-4
Two-Bank Operation
2.4 Two-Bank Operation
The SDRAM contains two independent array banks that can be accessed indi-
vidually or in an interleaved, or seamless, fashion. Each bank can have one
row activated at any given time. This is achieved by executing a bank-activate
command (ACTV) with the bank selected by the state of address terminal A11
and the specific row selected by the state of address terminals A0–A10. Each
bank must be deactivated before it can be activated again with a new row ad-
dress. A bank can be deactivated automatically by using the READ-P or
WRT-P commands, or deactivated by using the DEAC command during a
READ or WRT operation. Both banks can be deactivated simultaneously by
use of the DCAB command.
Theavailabilityoftwobanksallowsenhancedperformanceandawidervariety
of choices of possible combinations and methods of data access from which
to choose, based on system needs.
2.4.1 Two-Bank Row-Access Operation
The two-bank design allows you to access information on random rows at a
higher rate of operation than is possible with a standard DRAM. Accomplish
this by activating one bank with a row address as described previously, then,
while the data stream is being accessed to/from the bank, activate the second
bank with another row address. When the data stream to/from the first bank
is complete, the data stream to/from the second bank commences without in-
terruption. After the second bank is activated, you can deactivate the first bank
toallowtheentryofnewrowaddressforthenextroundofaccesses. Operation
can continue in this interleaved “ping-pong” fashion.
2.4.2 Two-Bank Column-Access Operation
The availability of two banks also allows you to access data between banks
from random starting columns at a higher rate of operation. After activating
each bank with an ACTV command, use A11 to alternate READ or WRT com-
mands between the banks to provide gapless accesses at the CLK frequency,
provided all specified timing requirements are met.
General Description of the 16M-Bit SDRAM
2-5
Bank Deactivation (Precharge) / Chip Select
2.5 Bank Deactivation (Precharge)
Both banks can be deactivated simultaneously, or placed in precharge, by use
of the DCAB command. A single bank can be deactivated by use of the DEAC
command. The DEAC command and the DCAB command are differentiated
from one another by the use of the A10 terminal. When A10 is held high during
a deactivate command, the DCAB command is executed and both banks are
deactivated. When A10 is held low, the DEAC command is executed and the
state of A11 determines which bank is deactivated. Each bank can also be
deactivated automatically by using the autodeactivate read (READ-P) and au-
todeactivate write (WRT-P) commands. The READ-P and WRT-P commands
are distinguished from the standard read and write operations by the state of
A10. Autodeactivate commands are selected when A10 is held high at the
entry of a read or write operation.
2.6 Chip Select
The SDRAM features a chip-select input, CS, that can be used to select or de-
select the SDRAM for command entry. This provides a means for using the
SDRAM in memory systems that require multiple memory device decoding.
Hold the CS input high on the rising edge of CLK to deselect the device. This
is a DESL command and affects only the RAS, CAS, and W inputs. The device
remains in its present state until CS is brought low and a valid command is in-
put. Use of CS does not affect an access burst that is in progress. The DESL
command is equivalent to the NOOP command and the two can be used inter-
changeably. The device can be selected or deselected on a cycle-by-cycle ba-
sis.
2-6
Data/Output Mask / CLK Suspend/Power-Down Mode
2.7 Data/Output Mask
Masking of individual data cycles within a burst sequence is accomplished by
†
use of the MASK command. During a write burst, if DQM (DQMU or DQML)
is held high on the rising edge of CLK, then the incident (referenced to the
same rising edge of CLK) input on the DQs is ignored. For a read burst, if DQM
(DQMU or DQML) is held high on the rising edge of CLK, the output data on
the DQs is referenced to the second rising edge of CLK and is placed in the
high-impedance state. Therefore, the application of DQM (DQMU or DQML)
to data-output cycles (read bursts) involves a latency of two CLK cycles, while
the application of DQM (DQMU or DQML) to data-in cycles (write bursts) has
no latency. Furthermore, the MASK command (or its opposite, the ENBL com-
mand) is performed on a cycle-by-cycle basis, allowing you to gate any individ-
ualdatacycle, ormultiplecycles, withineitherareadorawriteburstsequence.
2.8 CLK Suspend/Power-Down Mode
For normal device operation, CKE should be held high to enable CLK. If CKE
is brought low during the execution of a read or write operation, the state of the
DQ bus occurring at the immediate next rising edge of CLK is frozen and no
further inputs are accepted until CKE is returned high. This is known as a CLK-
suspend operation and it is executed with a HOLD command. The device re-
sumes operation from the point at which it was placed in suspension, begin-
ning with the second rising edge of CLK after CKE is returned high.
The device enters power-down mode if CKE is brought low when no read or
write command is in progress (PDE command). If both banks are deactivated
when power-down mode is entered, the power consumption is reduced to the
minimum. Power-down mode can be used during row-active periods or CAS-
before-RAS refreshes to reduce input-buffer power. After power-down mode
is entered, no further inputs are accepted until CKE is returned high. When
power-down mode is exited, new commands can be entered on the first CLK
edge after CKE is returned high, provided that the setup time for CKE (t
)
CESP
is satisfied. If t
> t , then NOOP or DESL commands must be entered
CESP
CK
untilt
ismet.CLKmustbeactiveandstable(ifCLKwasturnedoffforpow-
CESP
er-down) before CKE is returned high.
†
The TMS626162 SDRAM has DQ mask capability with upper- and lower-byte (DQMU and
DQML) control.
General Description of the 16M-Bit SDRAM
2-7
Mode-Register Set
2.9 Mode-Register Set
The SDRAM contains a mode register that you can program the read latency,
thebursttype, andtheburstlength. ThisisaccomplishedbyexecutinganMRS
command with the informatin entered on the address lines A0–A9. A logic 0
must be entered on A7 and A8, but A10–A11 are don’t care entries for the
SDRAM. When A9 = 1, the write burst length is always 1. When A9 = 0, the
write burst length is defined by A2–A0. Figure 2–2 shows the valid combina-
tions for a successful MRS command. Only valid addresses allow the mode
register to be changed.
Figure 2–2. Mode-Register Programming
A11
A10
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
Reserved
Register
bit A9
Write burst
length
Burst Type
0 = Serial
1 = Interleave
A2–A0
1
0
1
†
Register Bits
Register Bits§
Read
Latency
Burst Length
‡
A6
A5
A4
A2
A1
A0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
4
8
256
0
0
0
0
1
1
1
0
1
1
2
3
†
‡
§
All other combinations are
reserved.
Refer to timing requirements
for minimum valid read
latencies based on maximum
frequency rating.
All other combinations are
reserved.
2-8
Refresh
2.10 Refresh
The SDRAM, as the name implies, is still a dynamic RAM and must be re-
freshed, just as all other dynamic RAMs must be. All rows of the SDRAM must
be refreshed at intervals not exceeding the refresh-period specification, t
,
REF
to ensure data retention. The SDRAM offers two commands to accomplishthis
task: REFR and SLFR. In addition to these commands, refresh can be accom-
plished manually by performing an ACTV operation in each of the 4096 rows
within the refresh period. Because the SDRAM is divided into two independent
and equal banks, 2048 of the read or write operations must be performed in
each bank. The use of the REFR and SLFR commands is discussed in more
detail in following subsections.
2.10.1 CAS-Before-RAS (CBR) Refresh
Before performing a CAS-before-RAS refresh, both banks must be deacti-
vated. The refresh address is generated internally such that after 4096 REFR
commands, both banks of the SDRAM have been refreshed. The external ad-
dress and bank-select (A11) inputs are ignored. The execution of a REFR
command automatically deactivates both banks upon completion of the inter-
nal CBR cycle. This allows consecutive REFR-only commands to be executed
without any intervening DEAC commands. The REFR commands do not nec-
essarily have to be consecutive, but 4096 of them must be completed before
the refresh interval t
expires.
REF
2.10.2 Self Refresh
Toenterselfrefresh, youmustdeactivatebothbanksoftheSDRAM. Following
this deactivation, execute a SLFR command. For proper entry of the SLFR
command, bring CKE low for the same rising edge of CLK that RAS and CAS
are brought low and W is brought high. The CKE input must remain low for the
device to stay in the self-refresh mode. In the self-refresh mode, all refresh sig-
nals are generated internally, and all inputs except CKE are ignored. Power
consumption is reduced to a minimum and data is retained by the device for
an indefinite period as long as power is maintained. To exit the self-refresh
mode, return CKE high. You can issue new commands after waiting for the
timeintervalt . IfCLKismadeinactiveduringselfrefresh, itmustbereturned
RC
to an active and stable condition before CKE is brought high to exit self refresh.
General Description of the 16M-Bit SDRAM
2-9
Interrupted Bursts/Design Comparison: JEDEC-Standard Versus TI’s SDRAM
2.11 Interrupted Bursts
A read or write operation can be interrupted before the burst sequence has
beencompletedwithnoadverseperformancebyenteringcertainsuperseding
commands, provided that all timing requirements are met. The command in-
terrupting either a read or a write burst can be entered any number of cycles
from the initial burst command as determined by the specification nCCD. Burst
interruptions on autodeactivate read and write operations are not supported.
2.12 Design Comparison: JEDEC-Standard Versus TI’s SDRAM
The minimum feature set and the implementation-dependent parameters are
summarized in Table 2–3 and Table 2–4.
Table 2–3.Comparison of JEDEC-Standard Features With Features on TI’s TMS626162
and TMS626812
TMS626162
Features
JEDEC
TMS626812
Burst stop (STOP command)
Yes
(optional)
Burst lengths
1
2
Yes
Yes
Yes
Yes
Yes
(optional)
(optional)
Yes
4
8
Yes
256
(optional)
2-10
Design Comparison: JEDEC-Standard Versus TI’s SDRAM
Table 2–4.Comparison of Pipeline and Prefetch Versus JEDEC
Prefetch
Pipeline
TMS626402
TMS626802
TMS626162
TMS626812
Feature
Burst Length
Latency
JEDEC
Column-to-Column Address Delay
nCCD
Precharge Timing
nEP
n/a
1
n/a
2n
1n
2n
1
2
1
0
0
n/a
n/a
n/a
0
–1
–1
0
3
–1
0
>1
1
1
2
–1
–2
–1
–1
–1
3
–1
t
1
t
t
t
+ t
t
n/a
n/a
n/a
APR
RP
CK
CK
CK
RP
– t
2
t
t
t
RP
– t
RP
CK
CK
3
– t
RP
t
RP
t
>1
1
t
RP
– t
RP
– t
RP
– t
2
t
t
t
t
RP
RP
CK
CK
RP
CK
CK
3
t
– 2t
– t
– t
RP
†
CK
RP
RP
†
x
t
1
>1
1
n/a
n/a
n/a
n/a
x + t
n/a
RWL
CK
†
x
†
x
†
x
†
†
y
t
y + t
n/a
APW
CK
†
y
†
y
†
y
>1
†
x and y values are dependent on the speed version of product selected. Refer to the data sheets for actual values.
General Description of the 16M-Bit SDRAM
2-11
2-12
Chapter 3
Detailed Operations on the 16M-Bit SDRAM
This chapter describes specific operations on the 16M-bit SDRAM. Each sec-
tion discusses a different operation, but all operations use the following as-
sumptions:
SDRAM device speed indicator = -15 (15-ns CLK cycle time)
Read latency = 3
System-clock frequency = 66 MHz
Burst length = 4
Topic
Page
3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Seamless Read With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3 Read With Bank Interleaving — Random Row Address,
Autodeactivate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Write With Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.5 Write With Bank Interleaving — Random Row Address,
Autodeactivate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.6 Read Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . 3-21
3.7 Read Burst Interrupted by a WRT Command . . . . . . . . . . . . . . . . . . . 3-23
3.8 Read Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . 3-26
3.9 Read Burst Interrupted by a DEAC/DCAB Command . . . . . . . . . . . 3-28
3.10 Write Burst Interrupted by a READ Command . . . . . . . . . . . . . . . . . . 3-30
3.11 Write Burst Interrupted by a WRT Command . . . . . . . . . . . . . . . . . . . 3-32
3.12 Write Burst Interrupted by a STOP Command . . . . . . . . . . . . . . . . . . 3-34
3.13 Write Burst Interrupted by a DEAC/DCAB Command . . . . . . . . . . . 3-36
3.14 Single-Bit Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.15 Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.16 Power-Down-Mode Entry — Both Banks Active . . . . . . . . . . . . . . . . . 3-44
3.17 Power-Down-Mode Entry — Both Banks Deactivated . . . . . . . . . . . 3-46
3.18 Self-Refresh Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.19 Data-Masking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3-1
Power-Up Sequence
3.1 Power-Up Sequence
The power-up sequence ensures that all the internal logic circuits for the
SDRAM are initialized to the proper state. After the device is powered up to
the full V level, all device inputs must be held stable at a valid logic 0 or
CC
logic 1 level for 200 µs. The inputs should be set such that NOOP commands
are entered during the power-up period. After waiting for 200 µs, both banks
must be deactivated. In the example shown in Figure 3–1, a DCAB command
is used, however, two DEAC commands, one for each bank, also are accept-
able. Next, eight REFR commands must be performed. The timing specifica-
tion t must be satisfied before the first REFR command. For the -15 device,
RP
the clock-cycle equivalent of t
is calculated by:
RP
tRP tCK
45 ns
15 ns
3
This calculation of 3 cycles agrees with Figure 3–1. The timing specification
that determines the number of cycles that must occur between each succes-
sive REFR command is proportional to t . From the TMS626162 data sheet,
RC
t
is 125 ns. A calculation similar to that used for t
yields a result of
RC
RP
9 cycles. After the last REFR command and its associated cycle time have
elapsed, the SDRAM is ready to be programmed. This is accomplished by set-
ting the mode register for the desired read latency, burst length, and burst se-
quence. In the example, the read latency is 3, the burst length is 4, and the
burst sequence is serial. The correct address to be entered on inputs A0–A7
is 0x32 (hexadecimal). The MRS command with this address programs the
SDRAM to operate in the desired mode. The final step in the power-up se-
quence is to wait for a time given by the specification nRSA. This specification
determines the minimum number of cycles that must elapse between entry of
the MRS command and entry of any other valid command. Once this number
of cycles has elapsed, the SDRAM is ready for operation.
3-2
Figure 3–1. Power-Up Sequence
Device Speed Indicator = -15
Read Latency=3
t
=15 ns
Burst Length=4
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
REFR
#1
REFR
#8
–
DCAB
MRS
ACTV
CLK
†
t
t
t
RC
RP
CK
nRSA
200
s
V
CC
V
CCQ
t
CS
RAS
CAS
W
e
t
CH
R0
R0
A10
A11
Mode
A0–A9
DQ
A9 = Don’t Care
A7, A8 = 0x0
Hi-Z
A0–A6 = 0x32
‡
DQM
Power
CS
-UpSequence
CKE
Time Lapse
Time Lapse
Time Lapse
†
‡
This time period contains 6 cycles.
DQML and DQMU for the TMS626162 SDRAM
Seamless Read With Bank Interleaving
3.2 Seamless Read With Bank Interleaving
Figure 3–2 illustrates a seamless read with two banks. It assumes that both
banks are deactivated at the beginning of the time interval shown. The first
step is to activate row R0 in bank B. This is accomplished by performing an
ACTV command. According to the data sheet, a time interval t
is required
RCD
before a READ command can be executed. Given a clock period of 15 ns and
t
= 40 ns, it follows that a READ command must wait at least until the third
RCD
cycle after the ACTV command before execution:
number of cycles (in whole numbers)
tRCD tCK
40 15
3
number of cycles
number of cycles
2.67
DataisavailableonthethirdcycleaftertheREADcommand. Dataisvalidafter
a time t measured from the rising-clock edge previous to the data-out cycle.
AC
After the read latency, the SDRAM outputs data from a number of locations
equal to the burst length. In this example, it is four consecutive locations.
Additional READ commands can be executed before the burst is completed.
In order to achieve seamless data in single-bank operations, the next READ
command must be executed “burst” number of cycles after the previous READ
command cycle. For example, read commands with burst length = 8 should
be 8 cycles apart for seamless operation. READ commands can be executed
in this manner to achieve seamless data within the limits of t
max.
RAS
In this particular example, the objective is to achieve seamless data using both
banks instead of just one bank. In order for this to occur, you must activate
bank T. With the SDRAM, it is possible to have a row in both banks active at
the same time. However, data from only one bank can be output at any given
timebecauseoftheshareddatabus. Commandsaredirectedtoonlyonebank
at a time using A11. Because you want data to begin on bank T as soon as the
data on bank B is finished, a READ command must be issued “burst” cycles
(four cycles) after the previous READ command cycle on bank B. In order to
issue a READ command on the correct cycle, an ACTV command must be is-
sued at least a time t
previous to that READ command cycle on bank T.
RCD
This is possible because no other command is being issued on that cycle.
Therefore, seamless data is achieved using two banks.
In this example, bank B is deactivated to demonstrate the issues surrounding
the DEAC command, not because it is necessary. Deactivating bank B also
illustrates that it is possible to change rows and still maintain seamless data
when using both banks. If you want to get data from a different row in the same
3-4
Seamless Read With Bank Interleaving
bank, then you must wait a specified number of cycles, as shown by the follow-
ing calculation:
(
(
tRCD tCK) read latency
number of cycles delayed
tRP tCK)
where the quotients of the two divisions are rounded up to the next whole num-
ber.
In this particular example, t
is equivalent to four cycles, t
is equivalent
RP
RCD
to three cycles, and the read latency is three cycles. This means the delay
would be ten cycles after the DEAC command was issued. For this reason, it
isdesirabletoissuetheDEACcommandassoonaspossible. TheDEACcom-
mandisrestrictedbytheparameternEP. Forthisexample, themaximumvalue
allowedfornEPis–2cycles;however, at–2cycles, aREADcommandisbeing
issued in bank T. Therefore, the earliest the DEAC command can be issued
is one cycle before the last data-out cycle as shown in Figure 3–2. In order to
achieve seamless data with the specified conditions, two or more bursts must
be completed per row address. This is because of the delay required from the
DEAC command to the first data output as discussed previously. If the burst
length was set to eight, only one burst is required per row.
Detailed Operations on the 16M-Bit SDRAM
3-5
Seamless Read With Bank Interleaving
3-6
Seamless Read With Bank Interleaving
Figure 3–2. Seamless Read With Bank Interleaving
Device Speed Indicator = -15
Read Latency=3
t
=15 ns
Burst Length=4
CK
D
D
OUT
w/DEAC
OUT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
ACTV
READ
D
D
D
D
D
D
OUT
–
OUT
OUT
–
OUT
–
OUT
OUT
–
w/READ
D
D
OUT
w/DEAC
OUT
w/READ
ACTV
READ
D
D
D
D
D
–
–
D
ACTV
READ
D
D
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CLK
t
t
nEP = –1
RCD
CK
t
RP
t
RAS
t
RC
t
CS
t
CH
RAS
CAS
W
R0
R0
R1
R1
R2
R2
A10
A11
C0
C1
C2
C3
C4
A0–A9
DQ
t
AC
R0C0+0 R0C0+1 R0C0+2 R0C0+3 R0C1+0 R0C1+1 R0C1+2 R0C1+3 R1C2+0 R1C2+1 R1C2+2 R1C2+3 R1C3+0 R1C3+1 R1C3+2 R1C3+3 R2C4+0 R2C4+1
DQM
CS
CKE
Notes: 1) Timing relationships shown are for bank B operations.
2) Seamless for two or more bursts per row address
3) DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-7
Seamless Read With Bank Interleaving
3-8
Read With Bank Interleaving — Random Row Address, Autodeactivate
3.3 Read With Bank Interleaving – Random Row Address, Autodeactivate
Figure 3–3 illustrates how the autodeactivate feature is used to maximize the
databandwidthoftheSDRAMinsituationswhentherow-addresscharacteris-
tics of an application are random. This allows you to deactivate automatically
the current row after the data has been output. In this example, the READ-P
command is entered for the first access in each row of each bank.
The considerations for the placement of the ACTV and READ-P commands
are the same as in Figure 3–2. The minimum cycle time for one bank is deter-
mined by the specification t
, which is a combination of the nonautodeacti-
APR
vate specifications nEP and t . The number of cycles for t
is calculated
RP
APR
as follows:
(
)
tAPR
tRP
nEP tCK
45 ns
–2 15 ns
15 ns, or 1 cycle
In the previous case, the minimum time from the last data out to the entry of
the DEAC command was limited to –1 cycle because of a conflict with the entry
of the READ command in the opposite bank. In this example, the conflict is
eliminated with the use of the autodeactivate function, and the cycle time for
a read operation is reduced by one clock cycle. The penalty for changing rows
after only one access is two null cycles for every eight data-access cycles.
Detailed Operations on the 16M-Bit SDRAM
3-9
Read With Bank Interleaving — Random Row Address, Autodeactivate
3-10
Read With Bank Interleaving — Random Row Address, Autodeactivate
Figure 3–3. Read With Bank Interleaving – Random Row Address, Autodeactivate
t
=15 ns
–
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
READ-P
READ-P
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
ACTV
–
D
D
D
D
ACTV
–
–
–
D
D
D
OUT
–
OUT
OUT
–
OUT
–
OUT
–
OUT
–
OUT
–
READ-P
READ-P
†
ACTV
D
D
D
D
ACTV
D
D
D
D
OUT
Bank B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CLK
t
APR
t
t
CK
RCD
t
RC
t
CS
t
CH
RAS
CAS
W
R0
R1
R1
R2
R2
R3
R3
A10
A11
R0
C0
C1
C2
C3
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C0+3 R1C1+0 R1C1+1 R1C1+2 R1C1+3
R2C2+0 R2C2+1 R2C2+2 R2C2+3 R3C3+0 R3C3+1 R3C3+2
‡
DQM
CS
CKE
†
‡
Timing relationships shown are for bank B operations.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-11
Read With Bank Interleaving — Random Row Address, Autodeactivate
3-12
Write With Bank Interleaving
3.4 Write With Bank Interleaving
In using the bank interleaving feature with the WRT command, the timing con-
siderations for bank activation are the same as for the read operation
(Section 3.2). One difference between the read and write operations is in the
latency associated with each operation. There is a delay from the time the
READcommandisenteredtothetimethatdataisavailableattheSDRAMout-
put. This is not the case for a write operation. The applicable specification that
determines the time from a WRT command to the time when data is first ac-
cepted is nWCD, which is 0. This means that the first bit of data is presented
at the SDRAM inputs at the same time that the write command is entered. This
is illustrated in Figure 3–4.
Another timing parameter that is specific to the write operation is t
. This
RWL
parameter defines the minimum time required between the last data in and
entry of a bank-deactivation command. The number of cycles for t
example is calculated as follows:
in this
RWL
number of cycles
tRWL tCK
30 ns
15 ns, or 2 cycles
A bank can be deactivated before the last data has been output by the SDRAM
(see Section 3.2). This is not the case for write operations. You must wait until
the final bit of data has been entered and two additional cycles before deacti-
vating a bank. Therefore, read operations are more effective than write opera-
tions at hiding the latency associated with the row-deactivate operation.
Detailed Operations on the 16M-Bit SDRAM
3-13
Write With Bank Interleaving
3-14
Write With Bank Interleaving
Figure 3–4. Write With Bank Interleaving
Device Speed Indicator = -15
Read Latency=3
t
=15 ns
Burst Length=4
CK
WRT
D
WRT
w/D
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
ACTV
D
D
D
D
D
IN
DEAC
IN
IN
IN
IN
IN
w/D
IN
IN
WRT
w/D
WRT
w/D
WRT
w/D
WRT
w/D
†
–
–
–
–
–
–
Bank B
ACTV
D
D
D
D
D
ACTV
D
D
D
IN
D
DEAC
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
CLK
t
t
t
RWL
RCD
CK
t
RP
t
RAS
t
CS
t
CH
RAS
CAS
W
R2
R2
R0
R0
R1
R1
A10
A11
C0
C1
C2
C3
C4
C5
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C0+3 R0C1+0 R0C1+1 R0C1+2
R1C3+0 R1C3+1 R1C3+2 R1C3+3 R1C4+0 R1C4+1 R1C4+2 R1C4+3 R2C5+0
R0C1+3 R1C2+0 R1C2+1 R1C2+2 R1C2+3
‡
DQM
CS
CKE
†
‡
Timing relationships shown are for bank B operations.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-15
Write With Bank Interleaving
3-16
Write With Bank Interleaving — Random Row Address, Autodeactivate
3.5 Write With Bank Interleaving – Random Row Address, Autodeactivate
Similar to a read operation with bank interleaving and autodeactivate
(Section 3.3), the write-with-autodeactivate feature can eliminate conflict be-
tween the DEAC command in one bank and other commands in the opposite
bank. As Figure 3–5 shows, the placement of the ACTV and WRT-P com-
mands is the same as in the previous examples. The new specification that
must be considered when developing a write cycle that uses the WRT-P com-
mand is t
, the minimum time from the last data in to the activation of the
APW
next row in that bank. This specification is best understood by realizing that it
is based on combining the two relevant specifications that were discussed in
Section3.4 (Write with Bank Interleaving), t
and t . This is precisely how
RWL
RP
the value for t
was derived. For our example, the minimum number of
APW
cycles for t
is calculated as follows:
APW
(
(
)
tAPW in number of cycles
tRWL tRP
tCK
)
30 ns 45 ns
15 ns
5 cycles
The benefit of using the autodeactivate command can be seen by observing
that the minimum number of cycles for t and for t can be less than the
RWL
RP
number of cycles when calculated independently (for some speed configura-
tion); therefore, the use of the WRT-P command can save one cycle in the total
write cycle time for one bank. Even without the capability to precharge before
the completion of a write burst, the data-in throughput is the same as in the
read case in Section 3.2. This is because the write operation does not incur
any latency from command entry to data-in entry, whereas the read operation
does.
Detailed Operations on the 16M-Bit SDRAM
3-17
Write With Bank Interleaving — Random Row Address, Autodeactivate
3-18
Write With Bank Interleaving — Random Row Address, Autodeactivate
Figure 3–5. Write With Bank Interleaving – Random Row Address, Autodeactivate
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
WRT-P
Read Latency=3
CK
WRT-P
Bank T
–
–
–
–
–
–
ACTV
–
–
D
D
D
–
–
–
–
–
ACTV
–
–
D
D
D
IN
–
–
IN
IN
IN
IN
IN
w/D
w/D
IN
IN
WRT-P
WRT-P
†
Bank B
ACTV
D
D
D
–
–
–
–
ACTV
D
D
D
IN
–
–
–
–
IN
IN
IN
IN
IN
w/D
w/D
IN
IN
CLK
t
t
CK
RCD
t
APW
t
CH
t
CS
RAS
CAS
W
R0
R0
R1
R1
R2
R2
R3
R3
A10
A11
C0
C1
C2
C3
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C0+3 R1C1+0 R1C1+1 R1C1+2 R1C1+3
R2C2+0 R2C2+1 R2C2+2 R2C2+3 R3C3+0 R3C3+1 R3C3+2 R3C3+3
‡
DQM
CS
CKE
†
‡
Timing relationships shown are for bank B operations.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-19
Write With Bank Interleaving — Random Row Address, Autodeactivate
3-20
Read Burst Interrupted by a READ Command
3.6 Read Burst Interrupted by a READ Command
The interruption of read bursts is permitted as described in Section 2.11, Inter-
rupted Bursts. The interrupting command can be entered any number of
cycles following the entry of the read. There is one restriction on interrupting
a read burst: The interruption of a READ-P command is not allowed.
In the interruption of a read operation by another read operation, an interesting
issue is the distinction between an interrupting read and a normal read. As dis-
cussed in Section 3.2 (Seamless Read With Bank Interleaving), a new READ
command begins a normal read operation if it is entered “burst” cycles or more
after the previous READ command. If, however, the new READ command is
entered before “burst” cycles are complete, it interrupts the read operation in
progress. Figure 3–6 shows an example of a read burst interrupted by a READ
command.
The first READ command is interrupted by another READ command in the
samebank. TheinterruptedREADcommandcontinuesnormalexecutionuntil
thereadlatencyoftheinterruptingREADhasbeensatisfied. Withareadlaten-
cy of three cycles, the first two portions of data are output by the first read. At
this time, the interrupting read takes effect, but it is interrupted also by a READ
command in the opposite bank. As in the previous case, only the first two por-
tions of the second read operation are output. The third read operation inter-
rupts the last two portions of the second read and outputs the full four portions
without further interruption. As demonstrated by the second and third READ
commands, the operation of the SDRAM during interrupted bursts is not de-
pendent on the bank in which the interrupting command is entered.
Detailed Operations on the 16M-Bit SDRAM
3-21
ReadBurstInterruptedbyaEADCommand
Figure 3–6. Read Burst Interrupted by a READ Command
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
READ
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
–
D
D
D
D
D
ACTV
–
–
–
OUT
OUT
–
OUT
OUT
–
READ
ACTV
READ
D
D
D
OUT
DEAC
OUT
OUT
OUT
CLK
nCCD = 2
nCCD = 1
RAS
CAS
W
R0
R0
R1
R1
A10
A11
C0
C1
C2
A0–A9
DQ
R0C2+3
R0C0+0 R0C0+1 R0C1+0 R0C2+0 R0C2+1 R0C2+2
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Read Burst Interrupted by a WRT Command
3.7 Read Burst Interrupted by a WRT Command
The READ command also can be interrupted by a write operation with two
additional considerations. The first consideration is that there is no latency
associated with a write operation, so the read operation is interrupted immedi-
ately by the entry of a WRT or WRT-P command. The second consideration
is the possibility of data contention. Because of the immediacy of the write op-
eration, it is possible for the SDRAM to output data on one rising edge of the
clock, and for the system to send a write operation on the next rising edge of
the clock. The resulting data contention causes erroneous data to be written
to the SDRAM. This problem can be avoided by the use of the DQM input.
In Figure 3–7, the first read in bank B is interrupted after nCCD = 4 cycles. The
DQM input must be brought high nDOD + 1 cycles prior to the entry of the inter-
rupting write operation, as specified in Table 7 of the TMS626162 data sheet
(Read-Burst Interruption). With the DQM input at a high-logic level, the outputs
of the SDRAM are turned off. The first READ causes data to be available after
three cycles, but because of the high state of the DQM two cycles prior to the
D
, no data is output. In Figure 3–8, a read operation is executed in
OUT
bank T and is interrupted by a write in bank B after nCCD = 5 cycles. This case
is a clearer demonstration of the need to avoid data contention. The first two
bits of data are due to be clocked out on the two clock cycles before the inter-
rupting write command is entered. The first bit does not cause contention, but
the second one can. To mask this data from being output, the DQM input must
be high nDOD + 1 cycles prior to the write operation. To mask the second and
third data bits of the read burst, the DQM must be high two cycles prior to the
second data-bit output and held high for the next cycle to mask the third bit.
This provides one cycle to clear the DQ bus and avoids any data contention.
Detailed Operations on the 16M-Bit SDRAM
3-23
Read Burst Interrupted by a WRT Command
Figure 3–7. Read Burst Interrupted by a WRT Command in the Same Bank
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT
w/D
ACTV
READ
D
D
D
D
IN
OUT
IN
IN
IN
CLK
nCCD = 4
nDOD+1 = 3
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
DQ
R0C1+0 R0C1+1 R0C1+2 R0C1+3
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
3-24
Read Burst Interrupted by a WRT Command
Figure 3–8. Read Burst Interrupted by a WRT Command in a Different Bank
Device Speed Indicator = -15
Read Latency=3
t
=15 ns
Burst Length=4
CK
†
–
–
–
Bank T
Bank B
READ
–
–
–
–
–
–
D
D
D
OUT
–
OUT
–
OUT
WRT
w/D
IN
–
D
D
D
IN
‡
IN
IN
CLK
nCCD = 5
nDOD+1 = 3
RAS
CAS
W
A10
A11
C2
C3
A0–A9
DQ
R1C2+1
R0C3+0 R0C3+1 R0C3+2 R0C3+3
§
DQM
CS
CKE
†
‡
§
A previous ACTV instruction activated row R1 in bank T.
A previous ACTV instruction activated row R0 in bank B.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-25
Read Burst Interrupted by a STOP Command
3.8 Read Burst Interrupted by a STOP Command
To understand the effects of the interrupting STOP command, it is helpful to
refer to Table 7 in the TMS626162 data sheet (Read-Burst Interruption).
There are three points that determine the effect of the STOP command. The
first point is that there is a 2-cycle latency from the time the STOP command
is entered to the time the SDRAM outputs are placed in the high-impedance
state. The data-sheet specification that determines the time required to return
the outputs to high impedance is t , which in this case is 11 ns. It is possible,
HZ
then, that in certain situations the STOP command has no effect on the data
being output by the current read operation. Therefore, the effect of the inter-
rupting STOP command depends on where the command is entered. In
Figure 3–9, the first STOP command is input on cycle nCCD = 2 after the
READ command; therefore, the first bit of data is output as normal, and the
STOP command causes the SDRAM output to turn off on the next cycle. Only
one bit of the 4-bit burst is output. The second STOP command is input on
cycle nCCD = 3. The first two bits of data are output as normal and the third
and fourth bits are stopped.
The second point is that the STOP command affects only the output of data.
The row in the bank in which the STOP was executed remains active.
The last point involves when the next new command in that bank can be
executed. The next read or write operation must wait for a minimum of two
clock cycles after the entry of the STOP command. The new READ command
following the first STOP command can be input after the minimum number of
cycles because there is no data contention on the bus. This is not necessarily
true for the new WRT command following the second STOP command. Ac-
cording to the specification, the output returns to the high-impedance state a
maximum of 11 ns after the last rising clock edge, and the data to be written
must be valid at least 2 ns before the next rising clock edge. For the example,
this leaves 2 ns of margin to avoid data contention. Because of this, one addi-
tional delay cycle is shown to ensure that there is no bus contention due to the
switch from a read cycle to a write cycle.
The 2-cycle delay between entry of the STOP command and the next READ
or WRT command means that there is a penalty associated with using the
STOP command. This is an important point to keep in mind when determining
the best way to prevent the SDRAM from sending or receiving data in incre-
ments that arelessthantheprogrammed-burstlength. AMASKcommandcan
be more efficient in some cases. See Section 3.19 (Data-Masking Operation)
for a full description of data-masking features of the SDRAM.
3-26
Figure 3–9. Read Burst Interrupted by a STOP Command
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
D
WRT
w/D
OUT
w/STOP
D
ACTV
READ
STOP
D
READ
D
D
IN
IN
OUT
OUT
IN
CLK
nCCD = 3
1 cycle
nCCD = 2
nBSD = 2
nBSD = 2
(min)
RAS
CAS
W
e
R0
R0
A10
ReadBurstInterruptedbyaST
A11
C0
C1
C2
A0–A9
t
t
t
HZ
DS
HZ
R0C0+1
R0C1+0 R0C1+1
R1C2+0 R1C2+1 R1C2+2
DQ
†
DQM
CS
P
CKE
Command
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Read Burst Interrupted by a DEAC/DCAB Command
3.9 Read Burst Interrupted by a DEAC/DCAB Command
A read burst can be interrupted by a deactivate operation by using either the
DCAB command or the DEAC command. A cycle-by-cycle analysis of the tim-
ing diagram in Figure 3–10 is used to study the relevant specifications. In the
first case, the interrupting command, DEAC, is entered on the second cycle
following the READ command. This DEAC command takes effect after nHZP
cycles have elapsed. The value of nHZP is always equal to the read latency;
in this example, three cycles. The SDRAM outputs two bits of the 4-bit burst
before the interrupting DEAC command takes effect. It is also possible for a
deactivate operation to have no effect on the interrupted read operation. This
would have been the case in the example if the DEAC command had been en-
tered after nCCD = 4 cycles. In either case, the selected bank is deactivated.
The second instance of a DEAC command is included to illustrate the relation-
ship between nCCD and nEP. In this case, the DEAC command is entered
nCCD = 5 cycles after the READ command. The specification for nEP takes
precedence over the specification for nCCD. Therefore, the DEAC command
is not an interrupt, the read operation completes normally, and the selected
bank is placed in the precharge state. The precharge time, t , must be satis-
RP
fiedbeforethenextcommandcanbeinput. TheeffectoftheinterruptingDEAC
(or DCAB) is specified in Table 7 of the TMS626162 data sheet (Read-Burst
Interruption).
3-28
Figure 3–10. Read Burst Interrupted by a DEAC Command
t
= 15 ns
Burst Length = 4
Device Speed Indicator = -15
Read Latency = 3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
D
OUT
w/DEAC
†
READ
–
–
D
D
D
OUT
Bank B READ
CLK
D
D
ACTV
DEAC
OUT
OUT
OUT
OUT
nEP = –1
nCCD = 2
t
RP
nHZP = 3
RAS
CAS
W
e
ReadBurstInterruptedbyaDEAC
R1
R1
A10
A11
C0
C1
A0–A9
DQ
R0C0+0 R0C0+1
R1C1+0 R1C1+1 R1C1+2 R1C1+3
‡
DQM
CS
DCABCommand
CKE
†
‡
A previous ACTV instruction activated row R0 in bank B.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Write Burst Interrupted by a READ Command
3.10 Write Burst Interrupted by a READ Command
The write operation can be interrupted by the same commands that are al-
lowed to interrupt read operations. The same restrictions that apply to read in-
terrupts also apply for write interrupts. The interrupting command can be en-
tered any number of clock cycles after the WRT command is entered; the
WRT-P command cannot be interrupted.
The write operation can be interrupted by a read operation. This case is rela-
tively straightforward to implement (see Figure 3–11). The write operation is
interrupted after nCCD = 2 cycles by a READ command in bank B. As de-
scribed in Table 8 of the TMS626162 data sheet (Write-Burst Interruption), the
data input on the previous cycle is written by the SDRAM. The READ com-
mand immediately supersedes the data input and the SDRAM accepts no fur-
ther data. The read operation executes as described in Section 3.2 (Seamless
Read With Bank Interleaving).
3-30
Write Burst Interrupted by a READ Command
Figure 3–11. Write Burst Interrupted by a READ Command
Device Speed Indicator = -15
Read Latency=3
t
=15 ns
–
Burst Length=4
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT
ACTV
D
READ
D
D
D
D
OUT
IN
OUT
OUT
OUT
w/D
IN
CLK
nCCD = 2
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
DQ
R0C1+0 R0C1+1 R0C1+2 R0C1+3
R0C0+0 R0C0+1
Ignore
Ignore
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-31
Write Burst Interrupted by a WRT Command
3.11 Write Burst Interrupted by a WRT Command
The write operation also can be interrupted by another write operation as
shown in Figure 3–12. The WRT command is interrupted after nCCD = 3
cycles by a WRT-P command. The interrupting-write operation immediately
supersedes the write that is in process. The result is that only the first three bits
of the WRT command are written to the SDRAM. The next four data bits are
written into the SDRAM at the column address specified at the time the inter-
rupting WRT-P command is entered.
3-32
Figure 3–12. Write Burst Interrupted by a WRT Command
Device Speed Indicator = -15
Read Latency=3
t
= 15 ns
Burst Length=4
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT
w/D
WRT-P
w/D
–
ACTV
D
D
D
D
D
IN
ACTV
IN
IN
IN
IN
IN
IN
CLK
nCCD = 3
t
APW
RAS
CAS
W
e
R0
R0
R1
R1
A10
A11
WriteBurstInterruptedbyaR
C0
C1
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C1+0 R0C1+1 R0C1+2 R0C1+3
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Command
Write Burst Interrupted by a STOP Command
3.12 Write Burst Interrupted by a STOP Command
The example in Figure 3–13 shows the result of a write operation that is inter-
rupted by a STOP command. Unlike the case for a read operation interrupted
by a STOP, the effect of the interrupting STOP command is immediate. The
data on the cycle interrupted by the STOP command is ignored. The SDRAM
ignores all remaining data-in cycles of the write burst. In the example, the
STOP command is entered nCCD = 2 cycles after the WRT command. The
first two data bits of the burst are written by the SDRAM normally. The last two
data bits of the burst are ignored. Because the data is ignored as soon as the
STOP command is recognized, it is possible for the system-memory controller
to withhold the last two data bits without jeopardizing the data integrity of the
SDRAM.
The final consideration for the write interrupted by a STOP command is the
same as the read case. The next command must not be entered until two clock
cycles after the STOP command.
3-34
Write Burst Interrupted by a STOP Command
Figure 3–13. Write Burst Interrupted by a STOP Command
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT/
WRT/
D
IN
ACTV
D
STOP
D
D
D
IN
IN
IN
IN
D
IN
CLK
nBSD
nCCD = 2
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
DQ
R0C0+0 R0C0+1
Ignore
Ignore
R0C1+0 R0C1+1 R0C1+2 R0C1+3
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-35
Write Burst Interrupted by a DEAC/DCAB Command
3.13 Write Burst Interrupted by a DEAC/DCAB Command
The final operation that can be used to interrupt a WRT command is a bank
deactivate. Either of the two bank-deactivate commands, DEAC or DCAB, can
be used in this case. A DEAC command entered in bank T does not interrupt
an operation in bank B. The DCAB command interrupts an operation ongoing
in either bank.
The implementation of a write operation interrupted by a DEAC is complicated
by the write-recovery specification, t
. This is the specification that deter-
RWL
mines the time that must elapse from the last data-in cycle to the entry of a
deactivate operation. As indicated in Table 7 of the TMS626162 data sheet
(Write-BurstInterruption), theDQMinputmustbeusedtomaskthedatainputs
so that this specification is not violated. The specific details are shown in
Figure 3–14. The WRT command is interrupted after nCCD = 2 cycles by the
DEACcommand. Theminimumnumberofcyclesrequiredtomeett
inthis
RWL
case is two cycles. The DQM input must be brought high one cycle before the
DEAC command is entered in order to satisfy the conditions for interrupting a
write operation. The result is that only one cycle of data is written to the
SDRAM.
3-36
Write Burst Interrupted by a DEAC/DCAB Command
Figure 3–14. Write Burst Interrupted by a DEAC Command
Device Speed Indicator = -15 Read Latency = 3
t
= 15 ns Burst Length = 4
CK
–
–
–
–
–
–
–
–
–
–
Bank T
WRT
w/D
Bank B ACTV
CLK
Masked DEAC
IN
nCCD = 2
t
RWL
RAS
CAS
W
R0
R0
A10
A11
C0
A0–A9
DQ
R0C0+0
Masked
Ignore
†
DQM
CS
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Detailed Operations on the 16M-Bit SDRAM
3-37
Single-Bit Write
3.14 Single-Bit Write
The read latency, burst length and burst type are defined by the user when pro-
gramming the mode-register set. A burst length of 1, 2, 4, 8, or 256 bits is en-
coded on address lines A0–A2 during execution of the MRS command. If A9
is held low during execution of the MRS command, then the write- and read-
burst lengths are equal. The TMS626162 and TMS626812 SDRAMs also
have a single-bit-write option. If A9 is held high during execution of the MRS
command, then the write-burst length is set to one and the read-burst length,
specified by A0–A2, can be 1, 2, 4, 8, or 256 bits.
See Figure 3–15 for an example of a single-bit write.
3-38
Figure 3–15. Single-Bit Write (Read Burst)
Burst Length = 4
Read Latency = 3
Bank T
Bank B
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
WRT-P/
ACTV
Read
D
D
D
D
OUT
OUT
OUT
OUT
–
–
D
IN
CLK
RAS
CAS
W
A10
R0
R0
1
A11
A9–A0
C0
C1
R0C0 + 0 R0C0 + 1 R0C0 + 2 R0C0 + 3 R0C1 + 0 R0C1 + 1
DQ
†
DQM
CS
CKE
Single-BitWrite
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
3.15 Clock Suspend
This section and the next section (Power-Down-Mode Entry – Both Banks Ac-
tive), discuss the clock-gating features of the clock enable terminal, CKE. The
two uses of CKE are clock suspension and reduced-power consumption. In
both cases, while CKE is held low, the SDRAM does not recognize any activity
on CLK. The effect of bringing CKE low is dependent on the state of the
SDRAM. The SDRAM is placed in clock-suspend mode if CKE is brought low
while a read or write operation is in progress. If no read or write operation is
in progress at the time CKE is brought low, the SDRAM enters the power-down
mode.
There are two keys to understanding the effect of a clock-suspend operation
that is accomplished by the entry of the HOLD command. The first is that there
is a latency associated with the execution of a HOLD command. This latency
is determined by the timing specification, nCLE. This parameter defines the
number of clock cycles that must elapse before the clock-suspend operation
takeseffect, andalsothenumberofclockcyclesthatmustelapsebeforeanew
command can be entered after the clock-suspend operation is exited. The val-
ue of nCLE is always one clock cycle. The second point is that the clock input
is not recognized by the SDRAM while clock suspend is in effect. The use of
the HOLD command is shown in Figure 3–16 for a write and in Figure 3–17
for a read.
The clock is suspended twice during the write cycle of Figure 3–16. This is
done to illustrate the effect of varying the length of a clock-suspend operation.
CKE is first brought low before the rising clock edge of the second data bit of
the 4-bit burst. The clock-suspend operation is valid after nCLE cycles, pro-
vided that the specification for CKE setup time, t
= 2 ns, is satisfied. Be-
CES
cause there is a one-cycle latency from the time CKE is brought low to the time
theSDRAMrespondstotheclock-suspendrequest, theseconddatabitiswrit-
ten to the SDRAM. The clock input is inhibited for as many cycles as CKE is
heldlow. Inthiscase, CKEisheldlowfortwocycles, sothatthedatapresented
to the SDRAM inputs is ignored on the two cycles after nCLE is satisfied. Be-
cause of the entry and exit latency associated with the HOLD command, the
clock edges, and hence the data inputs, that are ignored do not correspond
to the time CKE is held low. The offset is equal to nCLE. Therefore, the second
clock suspend during the write operation is entered during the same cycle that
the third data bit is written, and is effective during the next cycle. The fourth and
final data bit is written on the following cycle. With a total of three clock-sus-
pend cycles, the write operation for a burst length of four takes seven cycles
to complete.
Figure 3–17 shows that clock suspend has a similar effect on the read opera-
tion. Thefirstclocksuspendinthereadcycleoccursduringthesamecyclethat
3-40
Clock Suspend
the first cycle in the read latency is counted. The second and third cycles of
the read latency are delayed for two cycles because CKE is held low. The ef-
fective access time from the start of the read operation is extended to five
cycles. The first two bits of the read operation are output normally. However,
CKE is held low for another two cycles, causing the fourth data bit to remain
on the SDRAM outputs for as many cycles.
This example also points out the different effect that CKE has on the read and
write operations. In the write operation, the data that is to be input to the
SDRAM on the first cycle after nCLE is satisfied is not written. However, the
data that is output by the SDRAM on the first cycle after nCLE is satisfied is
output and held. This is because of the difference in how the SDRAM handles
the read and write operation. In the discussion of the read latency in
Section 3.2: the data actually is output by the SDRAM one clock cycle before
it is valid. In the example, the clock-suspend command does not take effect
until after the SDRAM already has sent the fourth data bit out. The next two
clock cycles are ignored so that the SDRAM does not advance the next data
bit until nCLE cycles after CKE is brought high. Data is written to the SDRAM
in the same clock cycle it is presented. Therefore, the clock suspend affects
the data input immediately.
Detailed Operations on the 16M-Bit SDRAM
3-41
Clock Suspend
Figure 3–16. Clock Suspend During a Write Cycle
t
= 15 ns
Burst Length = 4
Device Speed Indicator = -15 Read Latency = 3
CK
–
–
–
–
–
–
–
–
–
–
–
Bank T
ACTV
WRT
w/D
Clock Clock
Ignored Ignored
Clock
Bank B ACTV
CLK
D
D
D
IN
Ignored
IN
IN
IN
RAS
CAS
W
R0
R0
R1
R1
A10
A11
C0
A0–A9
DQ
R0C0+0 R0C0+1 Ignore
Ignore R0C0+2 Ignore R0C0+3
†
DQM
CS
t
t
CES
CEH
CES
t
CEH
t
CKE
nCLE
DQM includes DQML and DQMU for the TMS626162 SDRAM.
†
3-42
Figure 3–17. Clock Suspend During a Read Cycle
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Clock Clock
Ignored Ignored
Clock Clock
Ignored Ignored
Bank B ACTV
CLK
READ
D
D
D
D
OUT
OUT
OUT
OUT
t
CS
RAS
CAS
W
R0
R0
A10
A11
h
C1
A0–A9
DQ
R0C1+0 R0C1+1 R0C1+2
R0C1+3
†
DQM
CS
nCLE
t
CEH
t
CES
CKE
t
CES
t
CEH
DQM includes DQML and DQMU for the TMS626162 SDRAM.
p
†
Power-Down-Mode Entry — Both Banks Active
3.16 Power-Down-Mode Entry — Both Banks Active
The second clock-gating function of the SDRAM provides a reduced-power
operating mode. This mode is entered when CKE is brought low when a bank
is active and no read or write operations are in progress. The effect of holding
CKE low in a power-down operation is similar to the clock-suspend case in its
effect on the clock input buffer. In both cases, the external-clock signal is ig-
nored by the SDRAM. However, for a power-down operation, all of the input
buffers of the SDRAM are turned off, including the clock-input buffer, resulting
in significant power savings. The standby current consumed by the SDRAM
is reduced by 14 mA when the device is placed in power-down mode.
The example in Figure 3–18 shows a power-down entry and exit sequence for
the case when both banks of the SDRAM are active. The power-down mode
is entered, as opposed to the clock-suspend mode, because the last data out-
put in the read burst was completed on the cycle previous to the entry of the
PDE command and the timing parameter t
= 2 ns was satisfied. Like the
CES
clock-suspend case, the power-down mode takes one cycle before taking ef-
fect. Therefore, the clock must remain valid for at least one cycle after the PDE
command has been entered. Once the SDRAM has entered power-down
mode, the external clock can be stopped for the duration of the power-down
period. However, if the clock is turned off, it must be restarted and be stable
beforebringingCKEhigh. Toexitthepower-downmode, CKEmustbebrought
high t
= 12 ns before the rising edge of the clock. If this time is met, a new
CESP
command can be input to the SDRAM. In cases where the time t
is not
CESP
met, a new command can be input on the following rising edge of the clock.
3-44
Figure 3–18. Power-Down-Entry Operation, Both Banks Active
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
READ Latency=3
CK
Bank
T
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ACTV
READ
D
D
D
D
OUT
–
OUT
–
OUT
–
OUT
–
Bank
B
†
READ
–
D
D
D
D
READ
PDE
OUT
OUT
OUT
OUT
CLK
t
CK
No READ(-P) or WRT(-P) in progress
Enter power-down
CLK must be active and stable before returning CKE high
Exit power-down (new commands can be issued)
t
CH
RAS
CAS
W
e
Power
R1
R1
A10
A11
—
A0–
A9
C0
C1
C3
R0C0+0 R0C0+1 R0C0+2 R0C0+3 R1C1+0 R1C1+1 R1C1+2 R1C1+3
DQ
‡
DQM
CS
t
CESP
t
CES
CKE
t
CEH
i
Time Lapse
†
‡
A previous ACTV instruction activated row R0 in bank B.
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Power-Down-Mode Entry — Both Banks Deactivated
3.17 Power-Down-Mode Entry — Both Banks Deactivated
The last example of theSDRAM’s power-down mode is for the case when both
banks are inactive. As explained in the section “Power-Down-Mode Entry –
Both Banks Active”, the reduction in power consumption is different depending
on the state of the SDRAM. As shown in Figure 3–19, an autodeactivate write
operation is used to deactivate bank B. It is assumed that bank T is already
inactive. Also, from the description of the PDE command given in the “Both
Banks Active” section, there must be one NOOP or DESL cycle preceding a
PDE command entry. Because of this one-cycle delay, the SDRAM has
enough time to complete the write operation and turn off the internal row-ad-
dress circuitry. Therefore, both banks are inactive at the time the power-down
operationcommences. Therestofthepower-downoperationcontinuesasde-
scribed previously.
3-46
Figure 3–19. Power-Down-Entry Operation, Both Banks Deactivated
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT-P
w/D
ACTV
PDE
ACTV
D
D
D
IN
IN
IN
IN
CLK
RAS
t
APW
t
CS
CAS
W
e
R1
R1
R0
A10
Power
A11
-DownModeEntry—BothBanksDeactivated
R0
C0
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C0+3
†
DQM
CS
t
CEH
t
CESP
t
CES
CKE
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Self-Refresh Operation
3.18 Self-Refresh Operation
In addition to the power-down feature, the self-refresh feature provides the ca-
pability to reduce the power consumption of the SDRAM during refresh opera-
tions. The conditions for proper execution of the SLFR command are similar
to those of the power-down mode. Both modes of operation require that CKE
be held low, but there are two additional constraints on the self-refresh opera-
tion. The first constraint is that both banks must be deactivated and fully pre-
charged prior to the SLFR command entry. The second constraint is that the
first command after the self-refresh exit must wait for a time specified by t
before it can be entered. These constraints are illustrated in Figure 3–20.
RC
In this example, bank T is considered to be precharged fully. To meet the first
constraint as described in the previous paragraph, entry of the SLFR com-
mand must wait until the time t
has expired. A valid SLFR command is en-
APW
tered on the cycle shown, provided that CKE is held high for a time determined
bythehold-timespecificationt andisbroughtlowintimetomeetthesetup-
CEH
time specification t
. The device remains in the self-refresh mode as long
CES
as CKE is held low. As is the case during a power-down operation, CLK and
all other inputs are ignored while the device is in the self-refresh mode. To exit
the self-refresh mode, CKE must be brought high in time to meet the specifica-
tion for t
. If the system clock is off, it must be returned to an active and
CESP
stable state prior to bringing CKE high. To meet the second constraint de-
scribed in the previous paragraph, entry of the next command must wait for a
time determined by the specification t . After this time, a valid command can
RC
be entered.
Upon exiting self refresh, you must begin the normal-refresh scheme immedi-
ately. If you are using a burst-refresh scheme, then 4096 REFR commands
must be executed before continuing with normal device operations. If a distrib-
uted-refresh scheme using CBR is employed (for example, two rows every
32 µs), then you must perform the first set of refreshes before continuing with
normal device operation. This ensures that the SDRAM is fully refreshed.
3-48
Figure 3–20. Self Refresh
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT-P
w/D
ACTV
D
D
D
IN
SLFR
REFR
IN
IN
IN
CLK
t
t
RC
APW
CLK is a Don’t Care
for this period
t
CS
RAS
CAS
W
e
R0
A10
A11
R0
C0
A0–A9
DQ
R0C0+0 R0C0+1 R0C0+2 R0C0+3
†
DQM
Self-RefreshOperation
CS
t
CESP
CKE
Time Lapse
t
CES
t
CEH
Time Lapse
Time Lapse
†
DQM includes DQML and DQMU for the TMS626162 SDRAM.
Data-Masking Operation
3.19 Data-Masking Operation
The data-masking feature of the SDRAM provides another way to perform
read or write operations that are shorter than the programmed-burst length.
This feature is useful in situations where the majority of data accesses are four
bits in duration but a small percentage of the accesses are only two bits long.
A data-masking operation can be performed on both read and write cycles,
and is effective on a cycle-by-cycle basis. This allows the user to mask any
single data cycle in a burst sequence. The DQM input is used to signal whether
the data in a given cycle is to be masked or enabled. The data to be read or
written is enabled by keeping DQM at a logic-low level during the appropriate
cycle. The data is masked when DQM is held high, and the data is enabled
when DQM is held low. These operations are performed by the MASK and
ENBL commands, respectively. For write operations, the state of the input, ei-
ther masked or enabled, is determined by the logic level of DQM in that same
cycle. In other words, there is no latency associated with DQM input for write
operations.
The TMS626162 allows the data-masking operation with upper- and lower-
byte control. The control signals are DQML (lower byte) and DQMU (upper
byte). The upper/lower byte is masked when DQMU/DQML is held high and
upper/lowerbyteisenabledwhenDQMU/DQMLisheldlow. See Figure 3–22
for an example of the data-masking operation with upper- and lower-byte con-
trol.
Thereis, however, alatencyassociatedwiththeDQMforreadoperations. This
delay is specified by the timing parameter nDOD and is always two cycles.
Therefore, the state of the output during a read operation is determined by the
logic level of the DQM input two cycles before the expected data output cycle.
The reason for the two-cycle delay is related to the way the SDRAM outputs
data. Since data is output by the rising-clock edge of the cycle before the data
is to be valid, the MASK command must be recognized one cycle before that
in order to stop the data from being output. The result is the two-cycle latency
for the MASK and ENBL commands.
The example in Figure 3–21 shows the timing relationships for both the mask
and enable operations during write and read cycles. The first and last bits of
both the read and write bursts are masked by bringing DQM high. As dis-
cussed previously, the data input on the write cycles when DQM is high is ig-
nored by the SDRAM. For the read cycles, the outputs of the SDRAM are
placed in the high-impedance state in the second cycle after DQM is brought
high.
3-50
Figure 3–21. Data-Masking Operation (TMS626812)
t
=15 ns
Burst Length=4
Device Speed Indicator = -15
Read Latency=3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
WRT
Masked
ACTV
READ
D
D
Masked
Masked
D
D
Masked
IN
IN
OUT
OUT
CLK
nDOD
nDOD
RAS
CAS
W
t
CH
t
CS
R0
R0
A10
M
A11
C0
C1
A0–A9
DQ
Masked R0C0+1 R0C0+2 Masked
R0C1+1 R0C1+2
DQM
Data-MaskingOperation
CS
CKE
Data-MaskingOperation
Figure 3–22. Data-Masking Operation With Upper- and Lower-Byte Control (TMS626162)
t
= 15 ns
–
Burst Length = 4
Read Latency = 3
CK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Bank T
Bank B
ACTV
WRT
DEAC
–
–
–
–
–
DEAC
ACTV
READ
CLK
DQ0-
DQ7
R1C1
R1C1 + 1 R1C1 + 2 R1C1 + 3
DQ8-
DQ15
R0C0
R0C0 + 1 R0C0 + 2 R0C0 + 3
DQMU
DQML
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0-
A9
C1
C0
CS
CKE
Appendix A
Glossary
A
B
ACTV command: See bank activation.
autodeactivate read (READ-P command): Banks are automatically deac-
tivatedattheendofthereadaccess;aseparatecommanddoesnothave
to be issued.
autodeactivate write (WRT-P command): Banks are automatically deacti-
vated at the end of the write access; a separate command does not have
to be issued.
bank activation (ACTV command): Command sequence that causes one
or both memory banks to be in the active state.
bank deactivation (DCAB, DEAC commands): Banks can be active only
for a certain length of time. Bank deactivation is a command sequence
that causes one or both banks to be in the inactive or precharge state.
burst: The capability of a memory device to fetch multiple addresses given
only the starting address.
burst interrupt, burst interruption: A command issued after the beginning
of a burst sequence but before the completion of the burst, which begins
a new transaction without causing adverse effects. This interrupting
command sequence should be entered only on even numbers of cycles
from the initial burst command.
burst length: The number of addresses that can be fetched internally by the
SDRAM before the next column address is sent.
burst sequence: Defines the amount and type of data the SDRAM can han-
dle without requiring a secondary instruction. Burst sequences can be 8,
4, 2, or 1 unit in length and specify either serial or interleavedaddressing.
A-1
Glossary
C
CLK suspend: The state the SDRAM enters when CKE goes low during a
read or write operation. Clocks are ignored and the operation in progress
is put in hold. The SDRAM resumes operation from the point at which it
was placed in suspension once CKE is returned high. If CLK suspend is
entered while both banks are deactivated, the SDRAM enters the power-
down mode.
D
datamaskinginput(DQM): Inhibitsread/writeforthecycle. Dataisnotout-
put/input during cycle, rather in the high-impedance state.
DCAB command: Deactivate both memory banks. See bank deactivation.
DEAC command: Deactivate one memory bank. See bank deactivation.
DESL command: Deselect command. The device remains in its current
state or continues the active process for each clock cycle without need
for a new command. If no process is active, the SDRAM is idle and banks
are precharging. DESL is equivalent to the NOOP command.
H
I
HOLD command: Command that initiates CLK-suspend/power-down
mode.
interrupted bursts: See burst interruption.
interleaving: Process by which transfer operations can occur by switching
back and forth between the two banks internal to the SDRAM.
J
JEDEC: Solid State Products Engineering Council (formerly Joint Electron
Device Engineering Council) of the Electronic Industries Association
(EIA). This council operates under EIA administrative and legal proce-
dures and publishes JEDEC standards and publications. This council
also continuously develops and maintains these standards as required
by the industry.
A-2
Glossary
L
latency: Number of clock cycles until command takes effect. The state of the
device changes after the latency period.
M
MASK command: Command that initiates data or output masking; see
masking.
masking: Process by which individual data cycles within a burst sequence
can be ignored or disabled (placed in the high-impedance state).
mode-registerset: Thecommandprocessbywhichtheprogrammablefea-
tures of the SDRAM are defined. Such features include serial or inter-
leave burst type, defining system read latency and defining burst length.
MRS command: Mode-register set command. See mode-register set.
N
nBSD: Number of cycles from entry of STOP command to entry of next com-
mand.
nCCD: Column-to-column address delay, or initial-command-burst-to-inter-
rupting-command delay (in cycles).
nCLE: Number of cycles from either the HOLD command entry to the sus-
pended CLK edge or from CLK-suspend exit to entry of any valid com-
mand.
nEP: Number of cycles from final data out to bank deactivation.
nDOD: Number of cycles from an ENBL or MASK command to output data
valid.
nHZP: Number of cycles from bank-deactivation (DEAC or DCAB) interrupt
of a read burst to the data outputs going into the high-impedance state.
NOOP command: Similar to DESL command. See DESL command.
nRSA: TheminimumnumberofcyclesthatmustelapsebetweenMRScom-
mand entry and entry of any other valid command.
nWCD: The number of cycles from a valid WRT command to the first valid
data at the inputs.
Glossary
A-3
Glossary
P
PDE command: See power-down enable command.
precharge: The state of the memory bank when deactivated.
ping-pong operation: Process of interleaving accesses in both banks by
going back and forth between bank T and bank B.
power-down enable command (PDE): Puts part into low power consump-
tion mode, thereby saving stand-by power.
power-down mode: The power-saving mode the SDRAM enters if CKE
goes low while both banks are inactive. To ensure validity of data during
power-down mode, execute the SLFR command concurrently with the
PDE command to activate self refresh.
R
READ command: Initiates a read access to the activated bank of the
SDRAM.
read latency: The delay between the read command (READ) and the first
output burst (also referred to as CAS latency).
READ-P command: See autodeactivate read.
REFR command: Initiates a CAS-before-RAS refresh of the SDRAM after
both banks have been deactivated. RAS and CAS must be low and W
must be high on the rising edge of CLK.
refresh: DRAM or SDRAM operation by which data is retained in the
memory. In the SDRAM, refresh can be accomplished by performing an
activate/deactivate command sequence to every row in both banks, by
performing 4096 REFR commands, or by placing the device in self re-
fresh.
S
SDRAM: Synchronous dynamic random-access memory. A memory device
in which DRAM operations are synchronized to the system clock.
seamless (gapless) operation: Process by which interleaved operations
of the SDRAM tightly coincide such that data is transferred each clock
cycle without a gap or interruption. This is the fast mode of operation the
SDRAM can perform with potential rates of 100 MHz depending on the
device speed indicator of the product selected.
A-4
Glossary
SLFR command: See self refresh.
STOP command: Discontinues acceptance of data at the inputs during a
write access, or completes only the read access in process, whichever
is applicable. The bank remains active, but a new command must be en-
tered to start any operation.
self refresh: Type of memory refresh that requires CKE to be held low in
addition to CAS and RAS being low and W being high for one cycle. Sus-
taining the self-refresh action for subsequent cycles requires only that
CKE remain low. Data is retained indefinitely while power is maintained.
Power consumption is reduced to a minimum in self refresh.
W
write latency: The delay between the write command (WRT) and the time
data is accepted at the memory inputs. There is no write latency for the
SDRAM.
WRT command: Initiates a write access to the activated bank of the
SDRAM.
WRT-P command: See autodeactivate write.
Glossary
A-5
A-6
This template is for the “See” and “See also” references in your index. Since these en-
tries do not have a page number associated with them, it’s extremely difficult to locate
one if you need to modify or delete it and you don’t remember which chapter it’s in.
By using this template, you can alphabetize your entries according to the first letter
of the first level entry.
A
B
C
D
E
F
G
H
I
J
1-1
K
L
M
N
O
P
Q
R
interrupting a read burst,
S
T
U
V
W
X
Y
Z
1-3
Index
DESL command 2-6, 3-44
A
detailed operations on the 16M-bit
SDRAM 3-1 to 3-50
ACTV command 2-5, 2-9, 3-4, 3-9, 3-17
differences between the SDRAM and the
DRAM 1-2
autodeactivate read (READ-P) 2-6, 3-9 to 3-11
autodeactivate write (WRT-P) 2-6, 3-17 to 3-19,
3-44
DQM input 3-23
E
B
ENBL command 2-7, 3-48
bank activate command (ACTV) 2-5
bank activation 1-3, 2-5
bank deactivation (precharge) 1-2, 2-6
block diagram 2-2
F
functional comparison: SDRAM versus
burst interruptions 2-10
burst length 1-3
DRAM 1-2 to 1-4
burst sequence 2-3
G
gapless (seamless) accesses 2-5, 3-5, 3-21
C
general description of 16M-bit SDRAM 2-1 to 2-12
CAS-before-RAS (CBR) refresh 2-9
chip select (CS) 2-6
H
CLK-suspend mode 2-7, 3-38 to 3-40
clock suspend 3-38 to 3-40
HOLD command 2-7, 3-38
D
I
data throughput 1-3
interleaving operation 1-2, 1-3, 2-3, 2-5, 3-4, 3-9,
data-masking operation 3-48
data/output mask 2-7
3-13, 3-17
interrupted bursts 2-10
DCAB command 2-5, 2-6, 3-2, 3-28, 3-36
interrupting a read burst 3-21 to 3-30
See also read burst
DEAC command 2-5, 2-6, 2-9, 3-2, 3-4 to 3-8,
3-17 to 3-20, 3-28, 3-36
interrupting a write burst 3-30 to 3-37
See also write burst
design comparison: JEDEC-standard versus TI’s
SDRAM 2-10 to 2-12
introduction 1-1 to 1-4
Index-1
Index
precharge (bank deactivation), 1-2, 2-6
J
program features
burst sequence 2-3
burst type 2-3
JEDEC-standard SDRAM features 2-10
prefetch and pipeline comparison 2-11
versus TI SDRAM 2-10
R
read
L
with bank interleaving — random row
address autodeactivate 3-9 to 3-10
with bank interleaving — seamless 3-4 to 3-11
latency 2-4, 2-7, 3-4, 3-13, 3-17, 3-26, 3-38, 3-48
M
read burst
interrupted by a DEAC/DCAB command 3-28
interrupted by a READ command 3-21
interrupted by a STOP command 3-26
interrupted by a WRT command 3-23 to 3-25
MASK command 2-7, 3-26, 3-48
masking 2-7, 3-23, 3-48
mode-register set 2-8
MRS command 2-8, 3-2
READ command 3-4 to 3-8, 3-21, 3-23,
3-26 to 3-28, 3-28 to 3-31
read latency 1-3, 3-4
N
READ-P command 2-6, 3-9 to 3-12
interruption not allowed 3-21
nCCD specification 2-10, 3-21, 3-23, 3-26, 3-28,
3-30, 3-32, 3-34, 3-36
reduced-power operating mode 3-42
See also power-down mode
nCLE specification 3-38, 3-39
nDOD specification 3-23, 3-48
nEP specification 3-5 to 3-8, 3-9 to 3-12, 3-28
nHZP specification 3-28
REFR command 2-9, 3-2, 3-46
refresh 2-9
CAS-before-RAS (CBR) refresh 2-9
self refresh 2-9 to 2-12
NOOP command 2-6, 3-2, 3-44
nRSA specification 3-2
row-address entry. See bank activation
nWCD specification 3-13
S
SDRAM
O
overview of the SDRAM 2-2 to 2-3
block diagram 2-2
overview 2-2
versus DRAM 1-2
P
seamless (gapless) operation 2-5, 3-4, 3-5, 3-21
seamless read with bank interleaving 3-4 to 3-6
self-refresh operation 2-9, 3-46
PDE command 2-7, 3-42, 3-44
ping-pong operation 2-5
SLFR command 2-9, 3-46
power-down mode (PDE command) 2-7, 3-38
power-down-mode entry — both banks active 3-42
STOP command 3-26, 3-34
penalty associated with 3-26
power-down-mode entry — both banks
deactivated 3-44 to 3-46
synchronous DRAM definition 1-2
system clock input (CLK) 2-2
power-up sequence 3-2 to 3-4
Index-2
Index
write burst
interrupted by a DEAC/DCAB
command 3-36 to 3-37
T
throughput 1-3
interrupted by a READ command 3-30 to 3-31
interrupted by a STOP command 3-34 to 3-35
interrupted by a WRT command 3-32
two-bank column-access operation 2-5
two-bank operation 2-5
two-bank row-access operation 2-5
WRT command 2-5, 3-13, 3-23, 3-26, 3-32, 3-36
WRT-P command 2-6, 3-17, 3-23, 3-30, 3-32
interruption not allowed 3-30
W
write
with bank interleaving 3-13 to 3-14
with bank interleaving — random row
address autodeactivate 3-17 to 3-18
Index-3
Index-4
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