TMSDVC5402PGE100G4 [TI]
数字信号处理器 | PGE | 144 | 0 to 0;
| 型号： | TMSDVC5402PGE100G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 数字信号处理器 | PGE | 144 | 0 to 0 控制器 微控制器 微控制器和处理器 数字信号处理器 |
| 文件： | 总68页 (文件大小：939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T MS 32 0V C5 40 2
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
D
D
D
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
– Two 16-Bit Timers
– Six-Channel Direct Memory Access
(DMA) Controller
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D
D
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 1M × 16-Bit
Maximum Addressable External Program
Space
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
D
D
D
D
D
D
4K x 16-Bit On-Chip ROM
Logic
16K x 16-Bit Dual-Access On-Chip RAM
D
D
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for
Efficient Program and Data Management
Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2000, Texas Instruments Incorporated
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PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
TABLE OF CONTENTS
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Software-Programmable Wait-State Generator . . . . . . . . . 16
Programmable Bank-Switching Wait States . . . . . . . . . . . . 18
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Enhanced 8-Bit Host-Port Interface . . . . . . . . . . . . . . . . . . . 19
Multichannel Buffered Serial Ports . . . . . . . . . . . . . . . . . . . . 20
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27
McBSP Control Registers And Subaddresses . . . . . . . . . . 29
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . 29
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Recommended Operating Conditions . . . . . . . . . . . . . . . . . 34
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Parameter Measurement Information . . . . . . . . . . . . . . . . . . 35
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . 36
Divide-By-Two Clock Option (PLL Disabled) . . . . . . . . . . . . 37
Multiply-By-N Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . 39
Ready Timing For Externally Generated Wait States . . . . . 45
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . 50
Instruction Acquisition (IAQ), Interrupt Acknowledge
(IACK), External Flag (XF), and TOUT Timings . . . . . 52
Multichannel Buffered Serial Port Timing . . . . . . . . . . . . . . . 54
HPI8 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
October 1998
Advanced Information
Original
A
B
C
D
April 1999
Advanced Information
Advanced Information
Advanced Information
Production Data
Revised to update characteristic data
Revised to update characteristic data
Revised to update characteristic data
Revised to release production data.
July 1999
September 1999
January 2000
Added Table of Contents, Revision History, and corrected IDLE3
current on page 35.
E
August 2000
Production Data
2
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
description
The TMS320VC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5402 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition,
the ’5402 includes the control mechanisms to manage interrupts, repeated operations, and function calls.
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PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
description (continued)
†‡
TMS320VC5402 PGE PACKAGE
(TOP VIEW)
1
108
107
106
105
104
103
102
101
100
99
NC
NC
A18
A17
2
3
V
V
SS
DD
SS
4
DV
A16
D5
5
A10
HD7
A11
A12
A13
A14
A15
NC
6
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
7
8
9
10
11
12
13
14
15
16
17
18
98
97
96
HAS
V
NC
95
SS
94
CV
HCS
93
V
DD
SS
HPIENA
92
HR/W
91
CV
NC
DD
READY 19
PS 20
90
89
TMS
DS 21
88
TCK
IS 22
R/W 23
87
TRST
TDI
86
MSTRB 24
IOSTRB 25
MSC 26
XF 27
HOLDA 28
IAQ 29
85
TDO
84
EMU1/OFF
EMU0
TOUT0
HD2
83
82
81
80
NC
HOLD 30
BIO 31
MP/MC 32
79
CLKMD3
CLKMD2
CLKMD1
78
77
DV
V
NC 35
NC 36
33
76
V
DD
SS
SS
DD
34
75
DV
NC
NC
74
73
†
‡
NC = No internal connection
DV
is the power supply for the I/O pins while CV
DD
is the power supply for the core CPU. V is the ground for both the I/O
SS
DD
pins and the core CPU.
The TMS320VC5402PGE (144-pin LQFP) package is footprint-compatible with the ’LC548, ’LC/VC549, and
’VC5410 devices.
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
description (continued)
TMS320VC5402 GGU PACKAGE
(BOTTOM VIEW)
13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
The pin assignments table to follow lists each signal quadrant and BGA ball number for the
TMS320VC5402GGU (144-pin BGA) package which is footprint-compatible with the ’LC548 and ’LC/VC549
devices.
5
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T M S3 2 0 VC5 402
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
†
Pin Assignments for the TMS320VC5402GGU (144-Pin BGA) Package
SIGNAL
NAME
SIGNAL
NAME
SIGNAL
NAME
SIGNAL
NAME
BGA BALL #
BGA BALL #
BGA BALL #
BGA BALL #
NC
NC
A1
B1
C2
C1
D4
D3
D2
D1
E4
E3
E2
E1
F4
F3
F2
F1
G2
G1
G3
G4
H1
H2
H3
H4
J1
NC
NC
N13
M13
L12
L13
K10
K11
K12
K13
J10
J11
NC
NC
N1
N2
M3
N3
K4
A19
NC
A13
A12
B11
A11
D10
C10
B10
A10
D9
C9
B9
V
DV
HCNTL0
V
SS
DV
DD
SS
DV
V
SS
V
SS
DD
A10
DD
D6
CLKMD1
CLKMD2
CLKMD3
NC
BCLKR0
BCLKR1
BFSR0
BFSR1
BDR0
HD7
A11
A12
A13
A14
A15
NC
L4
D7
D8
M4
N4
K5
D9
HD2
D10
D11
D12
HD4
D13
D14
D15
HD5
TOUT0
EMU0
EMU1/OFF
TDO
HCNTL1
BDR1
L5
J12
J13
H10
H11
H12
H13
G12
G13
G11
G10
F13
F12
F11
F10
E13
E12
E11
E10
D13
D12
D11
C13
C12
C11
B13
B12
M5
N5
K6
BCLKX0
BCLKX1
A9
HAS
D8
C8
B8
V
TDI
V
L6
SS
NC
CV
SS
HINT/TOUT1
CV
TRST
TCK
M6
N6
M7
N7
L7
A8
DD
DD
HCS
HR/W
READY
PS
TMS
BFSX0
BFSX1
HRDY
CV
B7
DD
NC
NC
A7
CV
DD
HPIENA
HDS1
C7
D7
A6
DV
K7
V
DD
SS
HDS2
DV
DS
V
SS
V
SS
N8
M8
L8
IS
CLKOUT
HD3
X1
HD0
BDX0
BDX1
IACK
HBIL
NMI
B6
DD
A0
R/W
C6
D6
A5
MSTRB
IOSTRB
MSC
XF
K8
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
X2/CLKIN
RS
N9
M9
L9
J2
B5
J3
D0
C5
D5
A4
HOLDA
IAQ
J4
D1
INT0
INT1
INT2
INT3
K9
K1
K2
K3
L1
D2
N10
M10
L10
N11
M11
L11
N12
M12
HOLD
BIO
D3
B4
D4
C4
A3
MP/MC
D5
CV
DD
DV
L2
A16
HD1
B3
DD
V
SS
L3
V
SS
V
SS
CV
C3
A2
DD
NC
NC
M1
M2
A17
A18
NC
NC
is the power supply for the core CPU. V
NC
NC
B2
†
DV
is the power supply for the I/O pins while CV
DD
is the ground for both the I/O pins and the core
SS
DD
CPU.
6
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
terminal functions
The following table lists each signal, function, and operating mode(s) grouped by function.
Terminal Functions
TERMINAL
NAME
†
TYPE
DESCRIPTION
DATA SIGNALS
A19 (MSB)
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
O/Z
Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen
address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper
four address pins (A16 to A19) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF is low.
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer
data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the
high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus
holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven
by the ’5402, the bus holders keep the pins at the previous logic level. The data bus holders on the ’5402 are
disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
IACK
O/Z
INT0
INT1
INT2
INT3
External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register (IMR) and
the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
NMI
I
†
‡
I = input, O = output, Z = high impedance, S = supply
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CV ), rather than the 3V I/O supply (DV ).
DD
DD
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
7
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Terminal Functions (Continued)
TERMINAL
NAME
†
TYPE
DESCRIPTION
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the
CPU and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
RS
I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MP/MC
I
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the
pipeline; all other instructions sample BIO during the read phase of the pipeline.
BIO
XF
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is
low, and is set high at reset.
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing
a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are
placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when
OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
MSTRB
READY
R/W
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in
the high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the
’C54x, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates that the ’5402 is in a hold state and that the address, data, and control lines
are in the high-impedance state, allowing the external memory interface to be accessed by other devices.
HOLDA also goes into the high-impedance state when OFF is low.
HOLDA
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
MSC
IAQ
O/Z
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus. IAQ goes into the high-impedance state when OFF is low.
†
‡
I = input, O = output, Z = high impedance, S = supply
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CV ), rather than the 3V I/O supply (DV ).
DD
DD
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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Terminal Functions (Continued)
TERMINAL
NAME
†
TYPE
DESCRIPTION
OSCILLATOR/TIMER SIGNALS
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.
CLKOUT
O/Z
I
Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The
logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized
to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select
signals have no effect until the device is reset again.
CLKMD1
CLKMD2
CLKMD3
Oscillator input. This is the input to the on-chip oscillator.
X2/CLKIN
X1
I
If the internal oscillator is not used, X2/CLKIN functions as the clock input, and can be driven by an external clock
source.
‡
Output pin from the internal oscillator for the crystal.
O
If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state
‡
when OFF is low.
Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT
cycle wide. TOUT0 also goes into the high-impedance state when OFF is low.
TOUT0
TOUT1
O/Z
O/Z
Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one
CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when
the HPI is disabled. TOUT1 also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
BCLKR0
BCLKR1
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
I/O/Z
I
BDR0
BDR1
Serial data receive input
BFSR0
BFSR1
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
I/O/Z
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BCLKX0
BCLKX1
I/O/Z
O/Z
BDX0
BDX1
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX
can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the
high-impedance state when OFF is low.
BFSX0
BFSX1
I/O/Z
MISCELLANEOUS SIGNAL
No connection
NC
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the ’5402, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR.
HD0–HD7
I/O/Z
HCNTL0
HCNTL1
Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have
internal pullup resistors that are only enabled when HPIENA = 0.
I
†
‡
I = input, O = output, Z = high impedance, S = supply
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CV ), rather than the 3V I/O supply (DV ).
DD
DD
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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Terminal Functions (Continued)
TERMINAL
NAME
†
TYPE
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup
resistor that is only enabled when HPIENA = 0.
HBIL
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
HCS
I
HDS1
HDS2
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs
have internal pullup resistors that are only enabled when HPIENA = 0.
I
Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA
register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.
HAS
I
I
Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
HR/W
HRDY
Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the
high-impedance state when OFF is low.
O/Z
Host interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can
also be configured as the timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the
high-impedance state when OFF is low.
HINT
O/Z
I
HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor
is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low
during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’5402
is reset.
HPIENA
SUPPLY PNS
CV
DV
S
S
S
+V . Dedicated 1.8-V power supply for the core CPU
DD
DD
DD
+V . Dedicated 3.3-V power supply for the I/O pins
DD
V
SS
Ground
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.
TCK
I
IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDI
I
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TDO
TMS
TRST
O/Z
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
I
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode,
and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
†
‡
I = input, O = output, Z = high impedance, S = supply
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CV ), rather than the 3V I/O supply (DV ).
DD
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Terminal Functions (Continued)
TERMINAL
NAME
†
TYPE
DESCRIPTION
TEST PINS (CONTINUED)
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of the IEEE standard 1149.1 scan system.
EMU0
I/O/Z
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST
is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers
into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). The OFF feature is selected by the following pin combinations:
TRST = low
EMU1/OFF
EMU0 = high
EMU1/OFF = low
†
‡
I = input, O = output, Z = high impedance, S = supply
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN
pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CV ), rather than the 3V I/O supply (DV ).
DD
DD
Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
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memory
The ’5402 device provides both on-chip ROM and RAM memories to aid in system performance and integration.
on-chip ROM with bootloader
The ’5402 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the
’5402 programmed with contents unique to any particular application. A security option is available to protect
a custom ROM. This security option is described in the TMS320C54x DSP CPU and Peripherals Reference Set,
Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,
is available on the ’5402 .
A bootloader is available in the standard ’5402 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin
is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location
contains a branch instruction to the start of the bootloader program. The standard ’5402 bootloader provides
different ways to download the code to accomodate various system requirements:
D
D
D
D
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space 8-bit or 16-bit mode
Serial boot from serial ports 8-bit or 16-bit mode
Host-port interface boot
The standard on-chip ROM layout is shown in Table 1.
†
Table 1. Standard On-Chip ROM Layout
ADDRESS RANGE
DESCRIPTION
F000h – F7FFh
Reserved
F800h – FBFFh
FC00h – FCFFh
FD00h – FDFFh
FE00h – FEFFh
FF00h – FF7Fh
FF80h – FFFFh
Bootloader
µ-law expansion table
A-law expansion table
Sine look-up table
Reserved
Interrupt vector table
†
In the ’VC5402 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The ’5402 device contains 16K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of
two blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a
write in one cycle. The DARAM is located in the address range 0060h–3FFFh in data space, and can be mapped
into program/data space by setting the OVLY bit to one.
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memory map
Page 0 Program
Page 0 Program
Data
Hex
Hex
0000
Hex
0000
0000
Memory
Mapped
Registers
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
005F
0060
Scratch-Pad
RAM
007F
0080
007F
0080
007F
0080
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(16K x 16-bit)
External
(OVLY = 0)
External
(OVLY = 0)
3FFF
4000
3FFF
4000
3FFF
4000
External
External
EFFF
F000
EFFF
F000
External
ROM (DROM=1)
or External
On-Chip ROM
(4K x 16-bit)
(DROM=0)
FEFF
FF00
FEFF
FF00
Reserved
Reserved
(DROM=1)
or External
(DROM=0)
FF7F
FF80
FF7F
FF80
Interrupts
(External)
Interrupts
(On-Chip)
FFFF
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Figure 1. Memory Map
relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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relocatable interrupt vector table (continued)
15
7
6
5
4
AVIS
R
3
DROM
R
2
1
0
CLK
OFF
IPTR
R/W
MP/MC
R/W
OVLY
R/W
SMUL
R/W
SST
R/W
R
LEGEND: R = Read, W = Write
Figure 2. Processor Mode Status (PMST) Registers
extended program memory
The ’5402 uses a paged extended memory scheme in program space to allow access of up to 1024K program
memory locations. In order to implement this scheme, the ’5402 includes several features that are also present
on the ’548/’549 devices:
D
Twenty address lines, instead of sixteen
D
An extra memory-mapped register, the XPC register, defines the page selection. This register is
memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
Six extra instructions for addressing extended program space. These six instructions affect the XPC.
D
–
–
FB[D] pmad (20 bits) – Far branch
FBACC[D] Accu[19:0] – Far branch to the location specified by the value in accumulator A or
accumulator B
–
–
–
–
FCALL[D] pmad (20 bits) – Far call
FCALA[D] Accu[19:0] – Far call to the location specified by the value in accumulator A or accumulator B
FRET[D] – Far return
FRETE[D] – Far return with interrupts enabled
D
In addition to these new instructions, two ’54x instructions are extended to use 20 bits in the ’5402:
–
–
READA data_memory (using 20-bit accumulator address)
WRITA data_memory (using 20-bit accumulator address)
All other instructions, software interrupts and hardware interrupts do not modify the XPC register and access
only memory within the current page.
Program memory in the ’5402 is organized into 16 pages that are each 64K in length, as shown in Figure 3.
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0 0000
1 0000
2 0000
F 0000
Page 1
Lower
16K}
Page 2
Lower
16K}
. . .
. . .
. . .
Page 15
Lower
16K}
1 3FFF
1 4000
2 3FFF
2 4000
F 3FFF
F 4000
External
External
External
Page 0
Page 1
Upper
48K
Page 2
Upper
48K
Page 15
Upper
48K
64K
Words{
External
External
External
2 FFFF
F FFFF
0 FFFF
1 FFFF
. . .
†
‡
See Figure 1
The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM
is mapped to the lower 16K words of all program space pages.
Figure 3. Extended Program Memory
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on-chip peripherals
The ’5402 device has the following peripherals:
D
D
D
D
D
D
Software-programmable wait-state generator with programmable bank-switching wait states
An enhanced 8-bit host-port interface (HPI8)
Two multichannel buffered serial ports (McBSPs)
Two hardware timers
A clock generator with a phase-locked loop (PLL)
A direct memory access (DMA) controller
software-programmable wait-state generator
The software wait-state generator of the ’5402 can extend external bus cycles by up to fourteen machine cycles.
Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When
all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are
automatically disabled. Disabling the wait-state generator clocks reduces the power comsumption of the ’5402.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of
the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized
to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 4
and described in Table 2.
15
14
12 11
9
8
6
5
3
2
0
XPA
I/O
R/W-111
Data
R/W-111
Data
Program
R/W-111
Program
R/W-111
R/W-0
R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 4. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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software-programmable wait-state generator (continued)
Table 2. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
15
XPA
0
I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14–12
11–9
8–6
I/O
1
1
1
Upper data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
Lower data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x8000 – xFFFFh
5–3
2–0
Program
Program
1
1
XPA = 1: The upper program space bit field has no effect on wait states.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
Program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: x0000–x7FFFh
XPA = 1: 00000–FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 5 and described
in Table 3.
15
1
0
SWSM
Reserved
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Figure 5. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3. Software Wait-State Control Register (SWCR) Bit Fields
PIN
NAME
RESET
VALUE
FUNCTION
NO.
15–1
Reserved
0
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are mulitplied by 2 for a maximum of 14 wait states.
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programmable bank-switching wait states
The programmable bank-switching logic of the ’5402 is functionally equivalent to that of the ’548/’549 devices.
This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or
data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the
data space boundary into program space.
The bank-switching control register (BSCR) defines the bank size for bank-switching wait states. Figure 6
shows the BSCR and its bits are described in Table 4.
15
12
11
10
3
2
1
0
BNKCMP
R/W-1111
PS-DS
Reserved
R-0
HBH
BH
EXIO
R/W-1
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Figure 6. Bank-Switching Control Register (BSCR), MMR Address 0029h
Table 4. Bank-Switching Control Register (BSCR) Fields
BIT
NAME
RESET
VALUE
FUNCTION
NO.
Bank compare. Determines the external memory-bank size. BNKCMP is used to mask the four MSBs of
15–12 BNKCMP
1111
an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting in a
bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.
Program read – data read access. Inserts an extra cycle between consecutive accesses of program read
and data read or data read and program read.
11
10–3
2
PS - DS
Reserved
HBH
1
0
0
PS-DS = 0
PS-DS = 1
No extra cycles are inserted by this feature.
One extra cycle is inserted between consecutive data and program reads.
These bits are reserved and are unaffected by writes.
HPI Bus holder. Controls the HPI bus holder feature. HBH is cleared to 0 at reset.
HBH = 0
HBH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the
previous logic level.
Bus holder. Controls the data bus holder feature. BH is cleared to 0 at reset.
BH = 0
BH = 1
The bus holder is disabled.
The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the
previous logic level.
1
0
BH
0
0
External bus interface off. The EXIO bit controls the external bus-off function.
EXIO = 0
EXIO = 1
The external bus interface functions as usual.
The address bus, data bus, and control signals become inactive after completing the
current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM
bit of ST1 cannot be modified when the interface is disabled.
EXIO
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parallel I/O ports
The ’5402 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The ’5402 can interface easily
with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced 8-bit host-port interface
The ’5402 host-port interface, also referred to as the HPI8, is an enhanced version of the standard 8-bit HPI
found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8 include:
Standard features:
D
D
D
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and ’54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the ’5402 HPI8:
D
D
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
The HPI8 functions as a slave and enables the host processor to access the on-chip memory of the ’5402. A
major enhancement to the ’5402 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8 memory map is identical to that of the DMA controller shown in Figure 7.
The host and the DSP both have access to the on-chip RAM at all times and host accesses are always
synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has
priority, and the DSP waits for one HPI8 cycle. Note that since host accesses are always synchronized to the
’5402 clock, an active input clock (CLKIN) is required for HPI8 accesses during IDLE states, and host accesses
are not allowed while the ’5402 reset pin is asserted.
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data register (HPID), and an
HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register
is accessible by both the host and the ’5402.
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multichannel buffered serial ports
The ’5402 device includes two high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow
direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based
on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:
D
D
D
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
D
Direct interface to:
–
–
–
–
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
Serial peripheral interface devices
D
D
D
D
D
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
D
D
D
D
D
D
BCLKX
BDX
BFSX
BCLKR
BDR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
BFSR
Receive frame synchronization
The six pins listed are functionally equivalent to previous serial port interface pins in the ’C5000 family of DSPs.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
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multichannel buffered serial ports (continued)
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on
the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR
is available. This structure allows storage of the two previous words while the reception of the current word is
in progress.
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial port functions, the McBSP provides programmable clock and frame
synchronization signals. The programmable functions include:
D
D
D
D
D
D
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received data
is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using
TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,
multichannel selection allows independent enabling of particular channels for transmission and reception. Up
to 32 channels in a stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit
operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate
together as a master or as a slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
hardware timer
The ’5402 device features two 16-bit timing circuits with 4-bit prescalers. The main counter of each timer is
decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timers can be stopped, restarted, reset, or disabled by specific control bits.
clock generator
The clock generator provides clocks to the ’5402 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
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clock generator (continued)
The reference clock input is then divided by two (DIV mode) to generate clocks for the ’5402 device, or the PLL
circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by
a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive
circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’5402
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
D
D
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the ’5402 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage
levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8V
power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended operating conditions
section of this document for the allowable voltage levels of the X2/CLKIN pin.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
D
D
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the configuration of the PLL clock module. Upon reset,
the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 –
CLKMD3 pins as shown in Table 5.
Table 5. Clock Mode Settings at Reset
CLKMD
RESET VALUE
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
0
0
0
0
1
E007h
PLL x 15
PLL x 10
9007h
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
1
1
1
4007h
1007h
F007h
0000h
F000h
—
PLL x 5
PLL x 2
PLL x 1
1/2 (PLL disabled)
1/4 (PLL disabled)
Reserved (bypass mode)
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DMA controller
The ’5402 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA controller allows movements of data to and from internal program/data
memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA
has six independent programmable channels allowing six different contexts for DMA operation.
features
The DMA has the following features:
D
D
D
D
D
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for internal accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
post-decremented, or be adjusted by a programmable value.
D
D
D
Each read or write transfer may be initialized by selected events.
Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the
CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
DMA memory map
The DMA memory map is shown in Figure 7 to allow DMA transfers to be unaffected by the status of the MPMC,
DROM, and OVLY bits.
Hex
0000
Reserved
001F
0020
McBSP
Registers
0023
0024
Reserved
005F
0060
Scratch-Pad
RAM
007F
0080
(16K x 16-bit)
On-Chip DARAM
3FFF
4000
Reserved
FFFF
Figure 7. ’5402 DMA Memory Map
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DMA priority level
Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
DMA source/destination address modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
DMA in autoinitialization mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can
be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
D
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfer; but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
D
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA transfer counting
The DMA channel element count register (DMCTRx) and the frame count register (DMSFCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
D
D
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number
of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read
transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with
the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default
value) means the block transfer contains a single frame.
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded
with the DMA global count reload register (DMGCR).
DMA transfers in double-word mode
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
DMA channel index registers
The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by
the selected DMA frame index register, either DMFRI0 or DMFRI1.
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DMA channel index registers (continued)
The element index and the frame index affect address adjustment as follows:
D
Element index: For all except the last transfer in the frame, the element index determines the amount to be
added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by
the SIND/DIND bits.
D
Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.
DMA interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 6.
Table 6. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multi-Frame
Either
Either
No interrupt generated
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event
for a channel. The list of possible events and the DSYN values are shown in Table 7.
Table 7. DMA Synchronization Events
DSYN VALUE
0000b
DMA SYNCHRONIZATION EVENT
No synchronization used
0001b
McBSP0 receive event
McBSP0 transmit event
Reserved
0010b
0011–0100b
0101b
McBSP1 receive event
McBSP1 transmit event
Reserved
0110b
0111b–0110b
1101b
Timer0 interrupt
1110b
External interrupt 3
Timer1 interrupt
1111b
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DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the ’5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
Reserved
Reserved
DMAC0
IMR/IFR[7]
TINT1
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
TINT1
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
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memory-mapped registers
The ’5402 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to
1Fh. Table 9 gives a list of CPU memory-mapped registers (MMRs) available on ’5402. The device also has
a set of memory-mapped registers associated with peripherals. Table 10, Table 11, and Table 12 show
additional peripheral MMRs associated with the ’5402.
Table 9. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
–
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2–5
6
2–5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15–0)
AH
9
9
Accumulator A high word (31–16)
Accumulator A guard bits (39–32)
Accumulator B low word (15–0)
Accumulator B high word (31–16)
Accumulator B guard bits (39–32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
–
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
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memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
DESCRIPTION
NAME
DRR20
ADDRESS
20h
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer0
McBSP0 data receive register 2
McBSP0 data receive register 1
McBSP0 data transmit register 2
McBSP0 data transmit register 1
Timer0 register
DRR10
DXR20
DXR10
TIM
21h
22h
23h
24h
PRD
25h
Timer0 period counter
Timer0 control register
Reserved
Timer0
TCR
26h
Timer0
–
27h
SWWSR
BSCR
–
28h
Software wait-state register
Bank-switching control register
Reserved
External Bus
External Bus
29h
2Ah
SWCR
HPIC
–
2Bh
Software wait-state control register
HPI control register
External Bus
HPI
2Ch
2Dh–2Fh
30h
Reserved
TIM1
PRD1
TCR1
–
Timer1 register
Timer1
Timer1
Timer1
31h
Timer1 period counter
Timer1 control register
Reserved
32h
33h–37h
38h
†
SPSA0
SPSD0
–
McBSP0 subbank address register
McBSP #0
McBSP #0
†
39h
McBSP0 subbank data register
3Ah–3Bh
3Ch
Reserved
GPIOCR
GPIOSR
–
General-purpose I/O pins control register
General-purpose I/O pins status register
Reserved
GPIO
GPIO
3Dh
3Eh–3Fh
40h
DRR21
DRR11
DXR21
DXR11
–
McBSP1 data receive register 2
McBSP1 data receive register 1
McBSP1 data transmit register 2
McBSP1 data transmit register 1
Reserved
McBSP #1
McBSP #1
McBSP #1
McBSP #1
41h
42h
43h
44h–47h
48h
†
SPSA1
SPSD1
–
McBSP1 subbank address register
McBSP #1
McBSP #1
†
49h
McBSP1 subbank data register
4Ah–53h
54h
Reserved
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
–
DMA channel priority and enable control register
DMA
DMA
DMA
DMA
PLL
‡
55h
DMA subbank address register
‡
56h
DMA subbank data register with autoincrement
‡
57h
DMA subbank data register
Clock mode register
Reserved
58h
59h–5Fh
†
‡
See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.
See Table 12 for a detailed description of the DMA subbank addressed registers.
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McBSP control registers and subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.
The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the
subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.
Table 11 shows the McBSP control registers and their corresponding sub-addresses.
Table 11. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
SUB-
ADDRESS
NAME
ADDRESS
NAME
ADDRESS
DESCRIPTION
Serial port control register 1
SPCR10
SPCR20
RCR10
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
SPCR11
SPCR21
RCR11
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 2
Receive control register 1
RCR20
RCR21
Receive control register 2
XCR10
XCR11
Transmit control register 1
XCR20
XCR21
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
Multichannel register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
DMA subbank addressed registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register
within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with
autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
post-incremented so that a subsequent access affects the next register within the subbank. This autoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 12 shows the DMA controller
subbank addressed registers and their corresponding subaddresses.
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DMA subbank addressed registers (continued)
Table 12. DMA Subbank Addressed Registers
DMA
SUB-
NAME
ADDRESS
DESCRIPTION
DMA channel 0 source address register
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
DMIDX1
DMFRI0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA
DMA global source address reload register
DMA global destination address reload register
DMA global count reload register
DMGDA
DMGCR
DMGFR
DMA global frame count reload register
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interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.
Table 13. Interrupt Locations and Priorities
LOCATION
DECIMAL
NAME
PRIORITY
FUNCTION
HEX
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
RS, SINTR
NMI, SINT16
SINT17
0
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer0 interrupt
4
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
SINT18
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT0, SINT3
4
5
6
BRINT0, SINT4
BXINT0, SINT5
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
8
Reserved (default) or DMA channel 0 inter-
rupt. The selection is made in the DMPREC
register.
Reserved(DMAC0), SINT6
TINT1(DMAC1), SINT7
88
92
58
9
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
5C
10
INT3, SINT8
96
60
64
11
12
External user interrupt #3
HPI interrupt
HPINT, SINT9
100
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BRINT1(DMAC2), SINT10
BXINT1(DMAC3), SINT11
104
108
68
13
14
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
6C
DMAC4,SINT12
DMAC5,SINT13
Reserved
112
116
70
74
15
16
—
DMA channel 4 interrupt
DMA channel 5 interrupt
Reserved
120–127
78–7F
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interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8.
15–14
RES
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAC5
DMAC4
BXINT1 BRINT1 HPINT
or or
DMAC3 DMAC2
INT3
TINT1
or
DMAC1 DMAC0
RES
or
BXINT0 BRINT0
TINT0
INT2
INT1
INT0
Figure 8. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
15–14
13
–
Reserved for future expansion
DMAC5
DMAC4
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
12
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
11
10
BXINT1/DMAC3
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
8
HPINT
INT3
Host to ’54x interrupt flag/mask
External interrupt 3 flag/mask
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
7
6
TINT1/DMAC1
DMAC0
This bit can be configured as either reserved, or the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
5
4
3
2
1
0
BXINT0
BRINT0
TINT0
INT2
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer 0 interrupt flag/mask bit
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
INT1
INT0
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documentation support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the TMS320C5000 platform of DSPs:
D
D
D
D
D
D
TMS320C5000 DSP Family Functional Overview (literature number SPRU307)
Silicon Updates for the TMS320VC5402/TMS320UC5402 DSP (literature number SPRZ155)
Device-specific data sheets (such as this document)
Complete User Guides
Development-support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
D
D
D
D
D
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP generation of TMS320 DSP products currently
available and the hardware and software applications, including algorithms, for fixed-point TMS320 DSP
devices.
For general background information on DSPs and Texas Instruments (TI) devices, see the three-volume
publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012,
SPRA016, and SPRA017).
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320, TMS320C5000, and TMS320C54x are trademarks of Texas Instruments.
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†
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V
DD
DD
‡
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.4 V
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
I
O
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
§
Device supply voltage, I/O
DV
CV
DD
DD
§
Device supply voltage, core
Supply voltage, GND
1.71
1.8
1.98
V
V
SS
0
V
RS, INTn, NMI, BIO, BCLKR0, BCLKR1,
BCLKX0, BCLKX1, HCS, HDS1, HDS2, TDI,
TMS, CLKMDn
2.2
DV
+ 0.3
DD
High-level input voltage
¶
V
V
X2/CLKIN
1.35
2.5
2
CV +0.3
DD
IH
IL
DV
= 3.3"0.3 V
DD
TCK, TRST
DV
DV
+ 0.3
+ 0.3
DD
DD
All other inputs
¶
RS, INTn, NMI, X2/CLKIN , BIO, BCLKR0,
BCLKR1, BCLKX0, BCLKX1, HCS, HDS1,
HDS2, TCK, CLKMDn
–0.3
–0.3
0.6
Low-level input voltage
DV = 3.3"0.3 V
V
V
DD
All other inputs
0.8
I
I
High-level output current
Low-level output current
–300
1.5
µA
mA
°C
OH
OL
T
Operating case temperature
–40
100
C
§
Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior to the I/O
buffers and then powered down after the I/O buffers.
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
¶
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electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
†
TYP
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
2.4
MAX
UNIT
V
V
I
I
= MAX
= MAX
V
OH
OH
0.4
V
OL
OL
Bus holders enabled, DV
DD
= MAX,
Input current for
outputs in high
impedance
D[15:0], HD[7:0]
–175
175
V = V
to DV
I
SS
DD
I
IZ
µA
All other inputs
DV
= MAX, V = V
SS
to DV
DD
–5
5
DD
O
}
X2/CLKIN
–40
40
TRST
With internal pulldown
With internal pulldown
–5
–5
300
300
Input current
HPIENA
(V = V
I
SS
I
I
µA
to DV
)
DD
With internal pullups,
HPIENA = 0
w
TMS, TCK, TDI, HPI
–300
–5
5
5
All other input-only pins
¶
#
||
I
I
Supply current, core CPU
Supply current, pins
CV
DV
= 1.8 V, f
= 3.3 V, f
= 100 MHz , T = 25°C
45
mA
DDC
DD
DD
clock
C
¶
= 100 MHz , T = 25°C
30
2
mA
mA
DDP
clock
C
IDLE2
IDLE3
PLL × 1 mode, 100 MHz input
Supply current,
standby
I
DD
Divide-by-two mode, CLKIN stopped
20
µA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
All values are typical unless otherwise specified.
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
HPI input signals except for HPIENA.
§
¶
#
Clock mode: PLL × 1 with external source
This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this
calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164).
||
PARAMETER MEASUREMENT INFORMATION
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 40 pF typical load circuit capacitance
T
Figure 9. 3.3-V Test Load Circuit
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internal oscillator with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT
is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance
of 30 Ω and power dissipation of 1 mW.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 10.
The load capacitors, C and C , should be chosen such that the equation below is satisfied. C in the equation
1
2
L
is the load specified for the crystal.
C1C2
(C1 ) C2)
CL +
recommended operating conditions of internal oscillator with external crystal (see Figure 10)
MIN
MAX
UNIT
f
Input clock frequency
10
20
MHz
clock
X1
X2/CLKIN
Crystal
C
C
2
1
Figure 10. Internal Oscillator With External Crystal
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divide-by-two clock option (PLL disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate
the internal machine cycle. The selection of the clock mode is described in the clock generator section.
When an external clock source is used, the frequency injected must conform to specifications listed in the timing
requirements table.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
timing requirements (see Figure 11)
MIN
MAX
UNIT
ns
†
t
t
t
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
20
c(CI)
f(CI)
r(CI)
8
8
ns
ns
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
†
switching characteristics over recommended operating conditions [H = 0.5t
Figure 11, and the recommended operating conditions table)
] (see Figure 10,
c(CO)
PARAMETER
MIN
TYP
MAX
UNIT
ns
‡
10
†
t
Cycle time, CLKOUT
2t
c(CI)
10
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
17
ns
d(CIH-CO)
t
2
2
ns
f(CO)
t
t
t
Rise time, CLKOUT
ns
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H–2
H–2
H
H
ns
w(COL)
w(COH)
ns
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
approaching ∞. The device is characterized at frequencies
c(CI)
‡
t
r(CI)
t
f(CI)
t
c(CI)
X2/CLKIN
CLKOUT
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
Figure 11. External Divide-by-Two Clock Timing
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multiply-by-N clock option
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in the clock generator
section.
When an external clock source is used, the external frequency injected must conform to specifications listed
in the timing requirements table.
NOTE:All revisions of the ’5402 can be operated with an external clock source, provided that the proper
voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to
the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to the recommended
operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
†
timing requirements (see Figure 12)
MIN
MAX
200
100
50
UNIT
‡
20
‡
20
‡
20
Integer PLL multiplier N (N = 1–15)
PLL multiplier N = x.5
t
Cycle time, X2/CLKIN
ns
c(CI)
PLL multiplier N = x.25, x.75
t
t
Fall time, X2/CLKIN
Rise time, X2/CLKIN
8
8
ns
ns
f(CI)
r(CI)
†
‡
N = Multiplication factor
The multiplication factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified
range (tc(CO))
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 10 and Figure 12)
]
c(CO)
PARAMETER
MIN
10
4
TYP
MAX
UNIT
ns
†
t
Cycle time, CLKOUT
t
c(CO)
c(CI)/N
10
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
17
ns
d(CI-CO)
t
2
2
ns
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
ns
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock up time
H–2
H–2
H
H
ns
ns
30
ms
†
N = Multiplication factor
t
f(CI)
t
r(CI)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
tp
r(CO)
Unstable
CLKOUT
Figure 12. External Multiply-by-One Clock Timing
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t
†
] (see Figure 13)
c(CO)
MIN
MAX
2H–7
2H–8
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from MSTRB low
Setup time, read data before CLKOUT low
Hold time, read data after CLKOUT low
a(A)M
ns
a(MSTRBL)
su(D)R
6
–2
0
ns
ns
h(D)R
Hold time, read data after address invalid
ns
h(A-D)R
t
Hold time, read data after MSTRB high
0
ns
h(D)MSTRBH
†
Address, PS, and DS timings are all included in timings referenced as address.
switching characteristics over recommended operating conditions for a memory read
†
(MSTRB = 0) (see Figure 13)
PARAMETER
MIN
–2
–2
–1
–1
–2
–2
MAX
UNIT
ns
‡
t
t
Delay time, CLKOUT low to address valid
3
3
3
3
3
3
d(CLKL-A)
§
Delay time, CLKOUT high (transition) to address valid
Delay time, CLKOUT low to MSTRB low
ns
d(CLKH-A)
t
ns
d(CLKL-MSL)
t
Delay time, CLKOUT low to MSTRB high
ns
d(CLKL-MSH)
‡
t
Hold time, address valid after CLKOUT low
ns
h(CLKL-A)R
h(CLKH-A)R
§
t
Hold time, address valid after CLKOUT high
ns
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory read preceded by a memory read
In the case of a memory read preceded by a memory write
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKL-A)
t
h(CLKL-A)R
A[19:0]
t
h(A-D)R
t
su(D)R
t
a(A)M
t
h(D)R
D[15:0]
t
h(D)MSTRBH
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(MSTRBL)
MSTRB
R/W
PS, DS
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 13. Memory Read (MSTRB = 0)
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O
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a memory write
†
(MSTRB = 0) [H = 0.5 t
] (see Figure 14)
c(CO)
PARAMETER
MIN
–2
MAX
UNIT
ns
‡
t
t
Delay time, CLKOUT high to address valid
3
d(CLKH-A)
§
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to data valid
Delay time, CLKOUT low to MSTRB high
Delay time, CLKOUT high to R/W low
Delay time, CLKOUT high to R/W high
Delay time, R/W low to MSTRB low
–2
3
ns
d(CLKL-A)
t
–1
3
ns
d(CLKL-MSL)
t
0
6
ns
d(CLKL-D)W
t
–1
3
ns
d(CLKL-MSH)
t
–1
3
3
ns
d(CLKH-RWL)
t
–1
ns
d(CLKH-RWH)
t
H – 2
1
H + 1
3
ns
d(RWL-MSTRBL)
‡
t
Hold time, address valid after CLKOUT high
ns
h(A)W
§
t
t
t
t
t
t
Hold time, write data valid after MSTRB high
Pulse duration, MSTRB low
H–3 H+6
ns
ns
ns
ns
ns
ns
h(D)MSH
w(SL)MS
su(A)W
2H–2
Setup time, address valid before MSTRB low
Setup time, write data valid before MSTRB high
Enable time, data bus driven after R/W low
Disable time, R/W high to data bus high impedance
2H–2
§
2H–6 2H+5
H–5
su(D)MSH
en(D–RWL)
dis(RWH–D)
0
†
‡
§
Address, PS, and DS timings are all included in timings referenced as address.
In the case of a memory write preceded by a memory write
In the case of a memory write preceded by an I/O cycle
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKH-A)
t
d(CLKL-A)
t
h(A)W
A[19:0]
D[15:0]
MSTRB
R/W
t
d(CLKL-D)W
t
h(D)MSH
t
su(D)MSH
t
d(CLKL-MSL)
t
dis(RWH-D)
t
d(CLKL-MSH)
t
su(A)W
t
t
d(CLKH-RWL)
d(CLKH-RWH)
t
t
w(SL)MS
en(D-RWL)
t
d(RWL-MSTRBL)
PS, DS
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 14. Memory Write (MSTRB = 0)
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t
†
] (see Figure 15)
c(CO)
MIN
MAX
3H–7
2H–7
UNIT
ns
t
t
t
t
t
Access time, read data access from address valid
Access time, read data access from IOSTRB low
Setup time, read data before CLKOUT high
Hold time, read data after CLKOUT high
a(A)IO
ns
a(ISTRBL)IO
su(D)IOR
6
0
0
ns
ns
h(D)IOR
Hold time, read data after IOSTRB high
ns
h(ISTRBH-D)R
†
Address and IS timings are included in timings referenced as address.
switching characteristics over recommended operating conditions for a parallel I/O port read
†
(IOSTRB = 0) (see Figure 15)
PARAMETER
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to IOSTRB high
Hold time, address after CLKOUT low
MIN
–2
–2
–2
0
MAX
UNIT
ns
t
3
3
3
3
d(CLKL-A)
t
ns
d(CLKH-ISTRBL)
t
ns
d(CLKH-ISTRBH)
t
ns
h(A)IOR
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
t
h(A)IOR
d(CLKL-A)
A[19:0]
t
h(D)IOR
t
su(D)IOR
t
a(A)IO
D[15:0]
t
h(ISTRBH-D)R
d(CLKH-ISTRBH)
t
a(ISTRBL)IO
t
t
d(CLKH-ISTRBL)
IOSTRB
R/W
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 15. Parallel I/O Port Read (IOSTRB = 0)
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory and parallel I/O interface timing (continued)
switching characteristics over recommended operating conditions for a parallel I/O port write
†
(IOSTRB = 0) [H = 0.5 t
] (see Figure 16)
c(CO)
PARAMETER
MIN MAX
UNIT
ns
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT high to IOSTRB low
Delay time, CLKOUT high to write data valid
Delay time, CLKOUT high to IOSTRB high
Delay time, CLKOUT low to R/W low
–2
–2
3
3
d(CLKL-A)
t
ns
d(CLKH-ISTRBL)
t
H–5
–2
H+8
3
ns
d(CLKH-D)IOW
t
ns
d(CLKH-ISTRBH)
t
–1
3
ns
d(CLKL-RWL)
d(CLKL-RWH)
t
t
t
t
t
Delay time, CLKOUT low to R/W high
–1
3
ns
Hold time, address valid after CLKOUT low
Hold time, write data after IOSTRB high
Setup time, write data before IOSTRB high
Setup time, address valid before IOSTRB low
0
H–3
H–7
H–2
3
H+7
H+1
H+2
ns
ns
ns
ns
h(A)IOW
h(D)IOW
su(D)IOSTRBH
su(A)IOSTRBL
†
Address and IS timings are included in timings referenced as address.
CLKOUT
t
su(A)IOSTRBL
t
h(A)IOW
t
d(CLKL-A)
A[19:0]
t
d(CLKH-D)IOW
t
h(D)IOW
D[15:0]
t
d(CLKH-ISTRBL)
t
d(CLKH-ISTRBH)
t
su(D)IOSTRBH
t
IOSTRB
R/W
t
d(CLKL-RWL)
d(CLKL-RWH)
IS
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 16. Parallel I/O Port Write (IOSTRB = 0)
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ready timing for externally generated wait states
†
timing requirements for externally generated wait states [H = 0.5 t
Figure 19, and Figure 20)
] (see Figure 17, Figure 18,
c(CO)
MIN
6
MAX
UNIT
ns
t
t
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
su(RDY)
0
ns
h(RDY)
‡
Valid time, READY after MSTRB low
4H–8
5H–8
ns
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
v(MSCL)
‡
Hold time, READY after MSTRB low
4H
ns
‡
Valid time, READY after IOSTRB low
ns
‡
Hold time, READY after IOSTRB low
5H
–1
–1
ns
Valid time, MSC low after CLKOUT low
Valid time, MSC high after CLKOUT low
3
3
ns
ns
v(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using
READY, at least two software wait states must be programmed.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
CLKOUT
A[19:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait State
Generated
by READY
Wait States
Generated Internally
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 17. Memory Read With Externally Generated Wait States
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
D[15:0]
t
h(RDY)
t
su(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
v(MSCH)
t
v(MSCL)
Wait States
Generated Internally
Wait State Generated
by READY
NOTE A: A[19:16] are always driven low during accesses to external data space.
Figure 18. Memory Write With Externally Generated Wait States
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
t
h(RDY)
t
su(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
v(MSCH)
t
v(MSCL)
Wait State Generated
by READY
Wait
States
Generated
Internally
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 19. I/O Read With Externally Generated Wait States
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[19:0]
D[15:0]
t
h(RDY)
t
su(RDY)
READY
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
IOSTRB
MSC
t
v(MSCH)
t
v(MSCL)
Wait State Generated
by READY
Wait States
Generated
Internally
NOTE A: A[19:16] are always driven low during accesses to I/O space.
Figure 20. I/O Write With Externally Generated Wait States
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HOLD and HOLDA timings
timing requirements for memory control signals and HOLDA, [H = 0.5 t
] (see Figure 21)
c(CO)
MIN
4H+7
7
MAX
UNIT
ns
t
t
Pulse duration, HOLD low
w(HOLD)
Setup time, HOLD low/high before CLKOUT low
ns
su(HOLD)
switching characteristics over recommended operating conditions for memory control signals
and HOLDA, [H = 0.5 t
] (see Figure 21)
c(CO)
PARAMETER
MIN
MAX
5
UNIT
ns
t
t
t
t
t
t
Disable time, address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, address, PS, DS, IS from CLKOUT low
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
5
ns
5
ns
2H+5
2H+5
2H+5
ns
Enable time, R/W enabled from CLKOUT low
ns
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
–1
ns
2
2
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
–1
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H–1
w(HOLDA)
CLKOUT
t
su(HOLD)
t
su(HOLD)
t
w(HOLD)
HOLD
t
v(HOLDA)
t
t
v(HOLDA)
t
w(HOLDA)
HOLDA
dis(CLKL-A)
t
en(CLKL-A)
A[19:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL-RW)
dis(CLKL-S)
dis(CLKL-S)
en(CLKL-RW)
t
en(CLKL-S)
MSTRB
IOSTRB
t
en(CLKL-S)
Figure 21. HOLD and HOLDA Timings (HM = 1)
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reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t
and Figure 24)
] (see Figure 22, Figure 23,
c(CO)
MIN
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
Hold time, MP/MC after CLKOUT low
h(RS)
0
h(BIO)
†
0
h(INT)
0
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+5
2H+2
4H
2H
4H
2H+2
4H
10
5
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
Setup time, BIO before CLKOUT low
7
10
10
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
7
su(INT)
5
su(MPMC)
†
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is
corresponding to three CLKOUT sampling sequences.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
‡
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
Divide-by-two mode
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
reset, BIO, interrupt, and MP/MC timings (continued)
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
t
su(INT)
t
h(RS)
CLKOUT
t
su(BIO)
t
h(BIO)
BIO
t
w(BIO)S
Figure 22. Reset and BIO Timings
CLKOUT
t
t
t
su(INT)
su(INT)
h(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 23. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 24. MP/MC Timing
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PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 t
] (see Figure 25)
c(CO)
PARAMETER
MIN
–1
MAX
UNIT
ns
t
Delay time, CLKOUT low to IAQ low
Delay time, CLKOUT low to IAQ high
Delay time, address valid to IAQ low
Delay time, CLKOUT low to IACK low
Delay time , CLKOUT low to IACK high
Delay time, address valid to IACK low
Hold time, IAQ high after address invalid
Hold time, IACK high after address invalid
Pulse duration, IAQ low
3
3
1
3
3
3
d(CLKL-IAQL)
t
t
–1
ns
d(CLKL-IAQH)
ns
d(A)IAQ
t
–1
–1
ns
d(CLKL-IACKL)
t
ns
d(CLKL-IACKH)
d(A)IACK
h(A)IAQ
t
t
t
t
t
ns
–2
–2
ns
ns
h(A)IACK
w(IAQL)
2H–2
2H–2
ns
Pulse duration, IACK low
ns
w(IACKL)
CLKOUT
A[19:0]
IAQ
t
t
t
d(CLKL-IAQH)
d(CLKL-IAQL)
t
h(A)IAQ
t
d(A)IAQ
t
w(IAQL)
t
d(CLKL-IACKH)
d(CLKL-IACKL)
t
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
MSTRB
Figure 25. IAQ and IACK Timings
52
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
(continued)
switching characteristics over recommended operating conditions for XF and TOUT
[H = 0.5 t
] (see Figure 26 and Figure 27)
c(CO)
PARAMETER
MIN
–1
MAX
UNIT
Delay time, CLKOUT low to XF high
Delay time, CLKOUT low to XF low
3
3
t
ns
d(XF)
–1
t
t
t
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
0
0
4
4
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
2H
CLKOUT
t
d(XF)
XF
Figure 26. XF Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 27. TOUT Timing
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PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing
timing requirements for McBSP [H=0.5t
†
] (see Figure 28 and Figure 29)
c(CO)
MIN
MAX
UNIT
ns
t
t
Cycle time, BCLKR/X
BCLKR/X ext
4H
c(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
2H–2
ns
w(BCKRX)
8
1
0
3
5
0
0
4
7
0
0
3
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
†
switching characteristics for McBSP [H=0.5t
] (see Figure 28 and Figure 29)
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4H
c(BCKRX)
‡
‡
‡
Pulse duration, BCLKR/X high
D – 2
C – 2
D + 2
ns
w(BCKRXH)
‡
t
Pulse duration, BCLKR/X low
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
C + 2
ns
ns
ns
w(BCKRXL)
–2
3
2
9
4
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
0
t
ns
ns
ns
d(BCKXH-BFXV)
8
11
4
–1
3
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
t
dis(BCKXH-BDXHZ)
9
¶
0
7
§
t
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
d(BCKXH-BDXV)
d(BFXH-BDXV)
3
¶
11
BFSX int
BFSX ext
–1
3
t
ns
3
13
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
The transmit delay enable (DXENA) and A–bis mode (ABIS) features of the McBSP are not implemented on the TMS320VC5402.
Minimum delay times also represent minimum output hold times.
§
¶
54
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P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
t
t
t
c(BCKRX)
w(BCKRXH)
w(BCKRXL)
t
r(BCKRX)
BCLKR
BFSR (int)
BFSR (ext)
t
d(BCKRH–BFRV)
t
d(BCKRH–BFRV)
t
r(BCKRX)
tsu(BFRH–BCKRL)
t
h(BCKRL–BFRH)
t
h(BCKRL–BDRV)
(n–2)
t
su(BDRV–BCKRL)
t
BDR
Bit (n–1)
(n–3)
(n–4)
(n–3)
(RDATDLY=00b)
su(BDRV–BCKRL)
t
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=01b)
Bit (n–1)
t
t
su(BDRV–BCKRL)
h(BCKRL–BDRV)
(n–2)
BDR
(RDATDLY=10b)
Bit (n–1)
Figure 28. McBSP Receive Timings
t
t
c(BCKRX)
w(BCKRXH)
t
r(BCKRX)
t
f(BCKRX)
t
w(BCKRXL)
BCLKX
BFSX (int)
BFSX (ext)
t
d(BCKXH–BFXV)
t
d(BCKXH–BFXV)
t
su(BFXH–BCKXL)
t
h(BCKXL–BFXH)
t
d(BDFXH–BDXV)
Bit (n–1)
t
t
d(BCKXH–BDXV)
(n–3)
BDX
Bit 0
Bit 0
(n–2)
(n–4)
(n–3)
(n–2)
(XDATDLY=00b)
d(BCKXH–BDXV)
(n–2)
BDX
(XDATDLY=01b)
Bit (n–1)
t
d(BCKXH–BDXV)
Bit (n–1)
t
dis(BCKXH–BDXHZ)
Bit 0
BDX
(XDATDLY=10b)
Figure 29. McBSP Transmit Timings
55
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S
O
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SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP general-purpose I/O (see Figure 30)
MIN
9
MAX
UNIT
ns
†
Setup time, BGPIOx input mode before CLKOUT high
t
t
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
ns
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
switching characteristics for McBSP general-purpose I/O (see Figure 30)
PARAMETER
MIN
MAX
UNIT
‡
t
Delay time, CLKOUT high to BGPIOx output mode
0
5
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
su(BGPIO-COH)
t
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 30. McBSP General-Purpose I/O Timings
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 31)
] CLKSTP = 10b, CLKXP = 0
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
9
MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
– 12H
ns
ns
su(BDRV-BCKXL)
0
5 + 12H
h(BCKXL-BDRV)
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXH)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 0† (see Figure 31)
] CLKSTP = 10b,
c(CO)
‡
MASTER
SLAVE
UNIT
PARAMETER
MIN MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
T – 3 T + 4
C – 5 C + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX high to BDX valid
–2
6
6H + 5 10H + 15
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C – 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H+ 4
4H – 2
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
MSB
c(BCKX)
LSB
t
su(BFXL-BCKXH)
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 32)
] CLKSTP = 11b, CLKXP = 0
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 – 12H
5 + 12H
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
t
t
Setup time, BFSX low before BCLKX high
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXH)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 0 (see Figure 32)
] CLKSTP = 11b,
c(CO)
†
‡
MASTER
SLAVE
UNIT
PARAMETER
MIN MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX low
C – 3 C + 4
T – 5 T + 3
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
–2
6
6H + 5 10H + 15
6H + 3 10H + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
–2
4
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D – 2 D + 4
4H – 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
c(BCKX)
MSB
LSB
t
su(BFXL-BCKXH)
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 32. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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A
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P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 33)
] CLKSTP = 10b, CLKXP = 1
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 – 12H
5 + 12H
ns
ns
su(BDRV-BCKXH)
h(BCKXH-BDRV)
t
t
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXL)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 1 (see Figure 33)
] CLKSTP = 10b,
c(CO)
†‡
MASTER
SLAVE
UNIT
PARAMETER
MIN
MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
T – 3 T + 4
D – 5 D + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid
–2
6
6H + 5 10H + 15
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D – 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
t
t
2H + 3
4H – 2
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
t
c(BCKX)
LSB
su(BFXL-BCKXL)
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 34)
] CLKSTP = 11b, CLKXP = 1
c(CO)
MASTER
SLAVE
MIN MAX
UNIT
MIN
9
MAX
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
– 12H
ns
ns
su(BDRV-BCKXL)
0
5 + 12H
h(BCKXL-BDRV)
t
t
Setup time, BFSX low before BCLKX low
Cycle time, BCLKX
10
ns
ns
su(BFXL-BCKXL)
12H
32H
c(BCKX)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 1 (see Figure 34)
] CLKSTP = 11b,
c(CO)
†‡
‡
MASTER
SLAVE
UNIT
PARAMETER
MIN MAX
MIN
MAX
§
t
t
t
Hold time, BFSX low after BCLKX high
D – 3 D + 4
T – 5 T + 3
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
¶
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid
–2
6
6H + 5 10H + 15
6H + 3 10H + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
–2
4
ns
ns
dis(BCKXH-BDXHZ)
t
Delay time, BFSX low to BDX valid
C – 2 C + 4
4H – 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
t
t
c(BCKX)
su(BFXL-BCKXL)
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
BFSX
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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HPI8 timing
†‡§¶
switching characteristics over recommended operating conditions
(see Figure 35, Figure 36, Figure 37, and Figure 38)
[H = 0.5t
]
c(CO)
PARAMETER
MIN
2
MAX
UNIT
t
Enable time, HD driven from DS low
16
ns
en(DSL-HD)
Case 1a: Memory accesses when
DMAC is active in 16-bit mode and
18H+16 – t
w(DSH)
t
< 18H
w(DSH)
Case 1b: Memory accesses when
DMAC is active in 16-bit mode and
16
26H+16 – t
16
t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode and
w(DSH)
t
< 26H
Delay time, DS low to HDx valid for
first byte of an HPI read
w(DSH)
t
ns
d(DSL-HDV1)
Case 1d: Memory access when
DMAC is active in 32-bit mode and
t
≥ 26H
w(DSH)
Case 2a: Memory accesses when
DMAC is inactive and t < 10H
10H+16 – t
16
w(DSH)
w(DSH)
Case 2b: Memory accesses when
DMAC is inactive and t ≥ 10H
w(DSH)
Case 3: Register accesses
16
16
5
t
t
t
t
Delay time, DS low to HDx valid for second byte of an HPI read
Hold time, HDx valid after DS high, for a HPI read
Valid time, HDx valid after HRDY high
ns
ns
d(DSL-HDV2)
h(DSH-HDV)R
v(HYH-HDV)
d(DSH-HYL)
3
9
Delay time, DS high to HRDY low (see Note 1)
16
ns
ns
Case 1a: Memory accesses when
DMAC is active in 16-bit mode
18H+16
Case 1b: Memory accesses when
DMAC is active in 32-bit mode
26H+16
10H+16
6H+16
ns
ns
t
Delay time, DS high to HRDY high
d(DSH-HYH)
Case 2: Memory accesses when
DMAC is inactive
Case 3: Write accesses to HPIC
register (see Note 2)
16
3
ns
ns
ns
t
t
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
)
d(COH-HYH
5
d(COH-HTX)
d(COH-GPIO)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output.
t
6
ns
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronoulsy, and do not cause HRDY to be deasserted.
DS refers to the logical OR of HCS, HDS1, and HDS2.
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
†
‡
§
¶
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
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HPI8 timing (continued)
†‡§
timing requirements
(see Figure 35, Figure 36, Figure 37, and Figure 38)
MIN
5
MAX
UNIT
ns
¶#
Setup time, HBIL and HAD valid before DS low or before HAS low
t
t
su(HBV-DSL)
¶#
Hold time, HBIL and HAD valid after DS low or after HAS low
5
ns
h(DSL-HBV)
t
t
t
t
t
t
t
Setup time, HAS low before DS low
Pulse duration, DS low
10
20
10
2
ns
ns
ns
ns
ns
ns
ns
su(HSL-DSL)
w(DSL)
Pulse duration, DS high
w(DSH)
Setup time, HDx valid before DS high, HPI write
Hold time, HDx valid after DS high, HPI write
su(HDV-DSH)
h(DSH-HDV)W
su(GPIO-COH)
h(GPIO-COH)
3
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input
6
0
†
DS refers to the logical OR of HCS, HDS1, and HDS2.
‡
§
¶
#
HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
GPIO refers to the HD pins when they are configured as general-purpose input/outputs.
HAD refers to HCNTL0, HCNTL1, and H/RW.
When the HAS signal is used to latch the control signals, this timing refers to the falling edge of the HAS signal. Otherwise, when HAS is not used
(always high), this timing refers to the falling edge of DS.
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HPI8 timing (continued)
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
Valid
t
h(DSH-HDV)R
HD READ
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
Valid
t
h(DSH-HDV)W
HD WRITE
CLKOUT
Valid
Valid
t
d(COH-HYH)
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
Figure 35. Using HDS to Control Accesses (HCS Always Low)
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HPI8 timing (continued)
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 36. Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 37. HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
†
GPIOx Input Mode
t
d(COH-GPIO)
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 38. GPIOx Timings
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MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
R
56
ΘJA
ΘJC
R
5
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MECHANICAL DATA
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY PACKAGE
12,10
SQ
9,60 TYP
0,80
11,90
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
0,08
0,45
0,35
4073221-2/B 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Thermal Resistance Characteristics
PARAMETER
°C/W
R
38
ΘJA
ΘJC
R
5
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DSG5402PGE100
ACTIVE
LQFP
PGE
144
60 Green (RoHS & CU NIPDAU Level-2-260C-1YR
no Sb/Br)
TMS320VC5402GGU100
TMS320VC5402GGUR10
TMS320VC5402PGE100
ACTIVE
ACTIVE
ACTIVE
BGA
BGA
GGU
GGU
PGE
144
144
144
160
TBD
TBD
SNPB
SNPB
Level-3-220C-168HR
Level-3-220C-168HR
1000
LQFP
60 Green (RoHS & CU NIPDAU Level-2-260C-1YR
no Sb/Br)
TMS320VC5402PGER10
TMS320VC5402ZGU100
TMS32C5402PGER10G4
ACTIVE
ACTIVE
ACTIVE
LQFP
BGA
PGE
ZGU
PGE
144
144
144
500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
160 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168HR
LQFP
500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMX320VC5402GGU100
TMX320VC5402PGE100
OBSOLETE
OBSOLETE
BGA
GGU
PGE
144
144
TBD
TBD
Call TI
Call TI
Call TI
Call TI
LQFP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 1
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