TMUX1101DBVR [TI]
3pA 导通状态漏电流、5V、1:1 (SPST)、单通道精密开关（高电平有效） | DBV | 5 | -40 to 125;
| 型号： | TMUX1101DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3pA 导通状态漏电流、5V、1:1 (SPST)、单通道精密开关（高电平有效） | DBV | 5 | -40 to 125 开关 |
| 文件： | 总41页 (文件大小：1187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
TMUX110x 5V、低泄漏电流、1:1 (SPST) 精密开关
1 特性
3 说明
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宽电源电压范围：1.08V 至 5.5V
TMUX1101 和 TMUX1102 是精密互补金属氧化物半
导体 (CMOS) 单极单投 (SPST) 开关。1.08V 至 5.5V
的宽电源电压工作范围 可支持 医疗设备到工业系统的
大量应用。这些器件可支持源极 (S) 和漏极 (D) 引脚上
GND 到 VDD 范围的双向模拟和数字信号。
低泄漏电流：3pA
低电荷注入：–1.5pC
低导通电阻：1.8Ω
–40°C 至 +125°C 工作温度
1.8V 逻辑兼容
逻辑控制输入 (SEL) 具有兼容 1.8V 逻辑电平的阈值。
当器件在有效电源电压范围内运行时，该阈值可确保
TTL 和 CMOS 的逻辑兼容性。SEL 为逻辑 1
时，TMUX1101 的开关打开，而 SEL 为逻辑 0
时，TMUX1102 打开。失效防护逻辑电路要求先在
SEL 引脚上施加电压，然后在电源引脚上施加电压，
从而保护器件免受潜在的损害。
失效防护逻辑
轨至轨运行
双向信号路径
先断后合开关
ESD 保护 HBM：2000V
2 应用
TMUX110x 器件是精密开关和多路复用器器件系列中
的一部分。这些器件具有非常低的导通和关断泄漏电流
以及较低的电荷注入，因此可用于高精度测量 应用提
供了出色的功能性与安全性。
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采样保持电路
反馈增益开关
信号隔离
现场变送器
3nA 的低电源电流和小型封装选项使其可用于便携式
应用标准。
可编程逻辑控制器 (PLC)
工厂自动化和控制
超声波扫描仪
器件信息(1)
患者监护和诊断
心电图 (ECG)
器件型号
TMUX1101
封装
封装尺寸（标称值）
2.00mm × 1.25mm
2.90mm x 1.60mm
SC70 (5) (DCK)
SOT-23 (5) (DBV)
TMUX1102
数据采集系统 (DAQ)
ATE 测试设备
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
电池测试设备
仪表：实验室、分析、便携
智能仪表：水表和燃气表
光纤网络
光学测试设备
TMUX110x 方框图
TMUX1101
TMUX1102
S
D
S
D
SEL
SEL
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS410
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
目录
8.7 Bandwidth ............................................................... 19
Detailed Description ............................................ 20
9.1 Overview ................................................................. 20
9.2 Functional Block Diagram ....................................... 20
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 22
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics (VDD = 5 V ±10 %)............ 5
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)......... 7
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)......... 9
7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)....... 11
7.9 Typical Characteristics............................................ 13
Parameter Measurement Information ................ 16
8.1 On-resistance.......................................................... 16
8.2 Off-leakage current ................................................. 16
8.3 On-leakage current ................................................. 17
8.4 Transition time......................................................... 17
8.5 Charge injection ...................................................... 18
8.6 Off isolation ............................................................. 18
9
10 Application and Implementation........................ 23
10.1 Application Information.......................................... 23
10.2 Typical Application - Sample-and-Hold Circuit .... 23
10.3 Typical Application - Switched Gain Amplifier ...... 25
11 Power Supply Recommendations ..................... 27
12 Layout................................................................... 27
12.1 Layout Guidelines ................................................. 27
12.2 Layout Example .................................................... 28
13 器件和文档支持 ..................................................... 29
13.1 文档支持................................................................ 29
13.2 相关链接................................................................ 29
13.3 接收文档更新通知 ................................................. 29
13.4 社区资源................................................................ 29
13.5 商标....................................................................... 29
13.6 静电放电警告......................................................... 29
13.7 Glossary................................................................ 29
14 机械、封装和可订购信息....................................... 30
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (July 2019) to Revision B
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删除了器件信息 表中的产品预览 说明 .................................................................................................................................... 1
Deleted the Product Preview note from the Device Comparison Table table ........................................................................ 3
Added DBV (SOT-23) thermal values to Thermal Information ............................................................................................. 4
Changes from Original (March 2019) to Revision A
Page
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将文档从预告信息更改为混合状态。 ...................................................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
5 Device Comparison Table
PRODUCT
TMUX1101
TMUX1102
DESCRIPTION
Low-Leakage-Current, 1:1 (SPST), Precision Switch (Logic High)
Low-Leakage-Current, 1:1 (SPST), Precision Switch (Logic Low)
6 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
DBV Package
5-Pin SOT-23
Top View
D
S
1
2
3
5
VDD
SEL
D
S
1
2
3
5
4
VDD
SEL
GND
4
GND
Not to scale
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
D
NO.
1
I/O
I/O
P
Drain pin. Can be an input or output.
Source pin. Can be an input or output.
Ground (0 V) reference
S
2
GND
SEL
3
4
I
Logic control input. Controls the switch state as shown in Truth Tables.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
5
P
(1) I = input, O = output, I/O = input and output, P = power
Copyright © 2019, Texas Instruments Incorporated
3
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
–0.5
–0.5
–30
–0.5
–30
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL
Logic control input pin voltage (SEL)
Logic control input pin current (SEL)
Source or drain voltage (S, D)
Source or drain continuous current (S, D)
Storage temperature
V
ISEL
30
mA
V
VS or VD
IS or ID (CONT)
Tstg
VDD+0.5
30
mA
°C
°C
150
TJ
Junction temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002, all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
0
NOM
MAX
5.5
UNIT
VDD
Supply voltage
V
V
VS or VD
VSEL
TA
Signal path input/output voltage (source or drain pin) (S, D)
Logic control input pin voltage (SEL)
Ambient temperature
VDD
5.5
0
V
–40
125
°C
7.4 Thermal Information
TMUX1101 / TMUX1102
THERMAL METRIC(1)
DCK (SC70)
DBV (SOT-23)
5 PINS
224.9
UNIT
5 PINS
348.5
238.3
205.7
141.4
204.7
N/A
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
150.6
130.0
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
74.8
ΨJB
129.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
7.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
1.8
4
4.5
4.9
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
0.85
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
1.6
1.6
Ω
Ω
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-leakage current
25°C
–0.08 ±0.005
–0.3
0.08
0.3
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-leakage current
25°C
–0.025 ±0.003
–0.2
0.025
0.2
nA
nA
ID(ON)
–40°C to +85°C
Channel on leakage current
IS(ON)
–40°C to +125°C
–0.95
0.95
nA
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-leakage current
25°C
–0.1
±0.01
0.1
nA
nA
ID(ON)
–40°C to +85°C
–0.35
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SEL)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.49
0
5.5
V
V
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.06
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.003
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
1
(1) When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
Copyright © 2019, Texas Instruments Incorporated
5
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
12
ns
VS = 3 V
tTRAN
Transition time from control input RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
17
18
ns
ns
Refer to Transition time
VS = 1 V
QC
Charge Injection
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
–1.5
–62
pC
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
Off Isolation
Bandwidth
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
25°C
–40
300
dB
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
6
Copyright © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
7.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
3.7
8.8
9.5
9.8
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
1.9
2
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-resistance
RON
FLAT
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
Ω
2.2
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VS = 1 V / 3 V
Refer to Off-leakage current
–40°C to +125°C
–0.9
0.9
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
VS = 1 V / 3 V
Refer to Off-leakage current
–40°C to +125°C
–0.9
0.9
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SEL)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.35
0
5.5
0.8
V
V
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.002
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.65
(1) When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
Copyright © 2019, Texas Instruments Incorporated
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TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
tTRAN
Transition time from control input RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
20
22
ns
ns
Refer to Transition time
VS = 1 V
QC
Charge Injection
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
–1.5
–62
pC
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
Off Isolation
Bandwidth
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
25°C
–40
300
dB
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
8
Copyright © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
7.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
40
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
80
80
Ω
Ω
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-leakage current
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SEL)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
1.07
0
5.5
V
V
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.001
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.45
(1) When VS is 1.62 V, VD is 1 V or when VS is 1 V, VD is 1.62 V.
Copyright © 2019, Texas Instruments Incorporated
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TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
25
ns
VS = 1 V
tTRAN
Transition time from control input RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
44
44
ns
ns
Refer to Transition time
VS = 1 V
QC
Charge Injection
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
–1.5
–62
pC
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
Off Isolation
Bandwidth
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
25°C
–40
300
dB
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
10
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7.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
RON
On-resistance
ISD = 10 mA
Refer to On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
105
105
0.05
0.2
Ω
Ω
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
–0.05 ±0.001
–0.2
nA
nA
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-leakage current
25°C
–0.05 ±0.001
–0.2
0.05
0.2
nA
nA
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
–40°C to +125°C
–0.9
0.9
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-leakage current
25°C
–0.1 ±0.005
–0.35
0.1
nA
nA
ID(ON)
–40°C to +85°C
0.35
Channel on leakage current
IS(ON)
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (SEL)
VIH
VIL
Input logic high
Input logic low
–40°C to +125°C
–40°C to +125°C
0.96
0
5.5
V
V
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
µA
µA
IIH
IIL
–40°C to +125°C
±0.05
2
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
1
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.001
µA
µA
IDD VDD supply current
Logic inputs = 0 V or 5.5 V
–40°C to +125°C
0.38
(1) When VS is 1 V, VD is 0.8 V or when VS is 0.8 V, VD is 1 V.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
55
ns
VS = 1 V
tTRAN
Transition time from control input RL = 200 Ω, CL = 15 pF
–40°C to +85°C
–40°C to +125°C
190
190
ns
ns
Refer to Transition time
VS = 1 V
QC
Charge Injection
RS = 0 Ω, CL = 1 nF
Refer to Charge injection
25°C
25°C
–1.5
–62
pC
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off isolation
OISO
Off Isolation
Bandwidth
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off isolation
25°C
25°C
–42
300
dB
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
BW
MHz
CSOFF
CDOFF
Source off capacitance
Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
6
pF
pF
10
CSON
CDON
On capacitance
f = 1 MHz
25°C
17
pF
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7.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
4.5
4
VDD = 3 V
VDD = 3.63 V
VDD = 4.5 V
VDD = 5.5 V
TA = 125°C
TA = 85°C
TA = 25°C
TA = -40°C
5
4
3
2
1
0
3.5
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
5.5
0
0
0
1
2
3
4
5
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
D001
D002
TA = 25°C
VDD = 5 V
图 1. On-Resistance vs Source or Drain Voltage
图 2. On-Resistance vs Temperature
8
7
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
0
VDD = 1.08 V
TA = 125°C
TA = 85°C
TA = 25°C
TA = -40°C
VDD = 1.32 V
VDD = 1.62 V
VDD = 1.98 V
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.5
1
1.5
2
2.5
3
3.5
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
D004
D003
TA = 25°C
VDD = 3.3 V
图 4. On-Resistance vs Source or Drain Voltage
图 3. On-Resistance vs Temperature
20
15
10
5
80
60
40
VDD = 1.98 V
VDD = 3.63 V
VDD = 1.32 V
20
0
0
-5
-20
-40
-60
-80
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
1
2
3
4
5
VS or VD - Source or Drain Voltage (V)
VS or VD - Source or Drain Voltage (V)
D005
D006
TA = 25°C
VDD = 5 V
图 5. On-Leakage vs Source or Drain Voltage
图 6. On-Leakage vs Source or Drain Voltage
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Typical Characteristics (接下页)
1
0.75
0.5
2
1.5
1
IOFF
ION
IOFF
ION
0.25
0
0.5
0
-0.25
-0.5
-0.75
-1
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D007
D008
VDD = 3.3 V
VDD = 5 V
图 7. Leakage Current vs Temperature
图 8. Leakage Current vs Temperature
500
400
300
200
100
0
0.4
0.3
0.2
0.1
0
VDD = 5 V
VDD = 5 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
VDD = 3.3 V
VDD = 1.8 V
VDD = 1.2 V
-0.1
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (èC)
Logic Voltage (V)
D009
D010
VSEL = 5.5 V
图 9. Supply Current vs Temperature
TA = 25°C
图 10. Supply Current vs Logic Voltage
20
8
6
VDD = 3.3 V
VDD = 5 V
VDD = 1.2 V
VDD = 1.8 V
15
10
5
4
2
0
0
-5
-2
-4
-6
-8
-10
-15
-20
0
1
2
3
4
5
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
VS - Source Voltage (V)
Source Voltage (V)
D011
D012
TA = -40°C to 125°C
TA = –40°C to 125°C
图 11. Charge Injection vs Source Voltage
图 12. Charge Injection vs Source Voltage
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Typical Characteristics (接下页)
26
24
22
20
18
16
14
12
10
8
10
0
Transition ON
Transition OFF
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1.5
2
2.5
3
3.5
4
4.5
5
5.5
100k
1M
10M
100M
VDD - Supply Voltage (V)
Frequency (Hz)
D013
D014
TA = -40°C to +125°C
TA = -40°C to +125°C
图 13. Output TTRANSITION vs Supply Voltage
图 14. Off-Isolation vs Frequency
0
-1
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D015
TA = -40°C to +125°C
图 15. On Response vs Frequency
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8 Parameter Measurement Information
8.1 On-resistance
The on-resistance of a device is the ohmic resistance between the source (S) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in 图 16. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD
:
V
ISD
S
D
VS
图 16. On-Resistance measurement setup
8.2 Off-leakage current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 17.
VDD
VDD
VDD
VDD
IS (OFF)
A
ID (OFF)
A
S
D
D
S
VS
VD
VD
VS
GND
GND
图 17. Off-leakage measurement setup
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8.3 On-leakage current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 18 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
A
ID (ON)
S1
D1
D1
S1
N.C.
N.C.
A
VS
VD
GND
GND
图 18. On-leakage measurement setup
8.4 Transition time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图 19 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
tf < 5ns
tr < 5ns
DRIVE
(VSEL
VIH
)
VIL
0 V
OUTPUT
RL
S
D
VS
CL
tTRANSITION
tTRANSITION
90%
SEL
OUTPUT
VSEL
GND
10%
0 V
图 19. Transition-time measurement setup
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8.5 Charge injection
The TMUX110x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QC. 图 20 shows the setup used to measure charge injection from source (S) to
drain (D).
VDD
0.1ꢀF
VDD
VDD
VSEL
OUTPUT
S
D
VOUT
CL
VS
0 V
Output
VS
VOUT
QC = CL
×
VOUT
SEL
VSEL
GND
图 20. Charge-injection measurement setup
8.6 Off isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (S) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 21 shows
the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
50Ω
GND
图 21. Off isolation measurement setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
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8.7 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (S) of an on-channel, and the output is measured at the drain pin (D) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 22 shows the setup used to measure bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
50Ω
GND
图 22. Bandwidth measurement setup
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9 Detailed Description
9.1 Overview
The TMUX1101 and TMUX1102 are 1:1 (SPST) switches. The TMUX110x devices have a controllable single-
pole, single-throw switch that is turned on or off based on the state of the select pin. The switch of the
TMUX1101 is turned on with a Logic 1 on the select pin, while a Logic 0 is required to turn on switch in the
TMUX1102. 图 23 shows the functional block diagram for the TMUX110x devices.
9.2 Functional Block Diagram
TMUX1101
TMUX1102
S
D
S
D
SEL
SEL
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
图 23. TMUX110x Functional Block Diagram
9.3 Feature Description
9.3.1 Bidirectional operation
The TMUX110x conducts equally well from source (S) to drain (D) or from drain (D) to source (S). Each channel
has very similar characteristics in both directions and supports both analog and digital signals.
9.3.2 Rail to rail operation
The valid signal path input/output voltage for TMUX110x ranges from GND to VDD
.
9.3.3 1.8 V Logic compatible inputs
The TMUX110x devices have 1.8-V logic compatible control for all logic control inputs. The logic input thresholds
scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level
inputs allows the TMUX110x devices to interface with processors that have lower logic I/O rails and eliminates
the need for an external translator, which saves both space and BOM cost. The current consumption of the
TMUX110x devices increase when using 1.8V logic with higher supply voltage as shown in 图 10. For more
information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.4 Fail-safe logic
The TMUX110x supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pin. For example, the Fail-Safe Logic feature
allows the select pin of the TMUX110x devices to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX110x with VDD = 1.2 V while allowing the select pin to interface with a logic level
of another device up to 5.5 V.
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Feature Description (接下页)
9.3.5 Ultra-low Leakage Current
The TMUX110x devices provide extremely low on-leakage and off-leakage currents. The TMUX110x devices are
capable of switching signals from high source-impedance inputs into a high input-impedance op amp with
minimal offset error because of the ultra-low leakage currents. 图 24 shows typical leakage currents of the
TMUX110x devices versus temperature at VDD = 5V.
2
IOFF
ION
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D008
图 24. Leakage Current vs Temperature
9.3.6 Ultra-low Charge Injection
The TMUX110x devices have a transmission gate topology, as shown in 图 25. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
The TMUX110x devices have special charge-injection cancellation circuitry that reduces the source-to-drain
charge injection to -1.5 pC at VS = 1 V as shown in 图 26.
20
15
10
5
OFF ON
VDD = 3.3 V
VDD = 5 V
CGDN
CGSN
0
D
S
-5
-10
-15
-20
CGSP
CGDP
0
1
2
3
4
5
OFF ON
VS - Source Voltage (V)
D011
图 25. Transmission Gate Topology
图 26. Charge Injection vs Source Voltage
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9.4 Device Functional Modes
The TMUX110x devices have a controllable single-pole, single-throw switch that is turned on or turned off based
on the state of the corresponding select pin. The control pin can be as high as 5.5 V.
The TMUX110x devices can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins should be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (Sx or Dx) should be connection to GND.
9.4.1 Truth Tables
表 1 and 表 2 show the truth tables for the TMUX1101 and TMUX1102 respectively.
表 1. TMUX1101 Truth table
SEL
0
SWITCH STATE
OFF (HI-Z)
ON
1
表 2. TMUX1102 Truth table
SEL
0
SWITCH STATE
ON
1
OFF (HI-Z)
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX110x
have a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These
features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for low-
voltage applications.
10.2 Typical Application - Sample-and-Hold Circuit
One useful application to take advantage of the TMUX1101 and TMUX1102's performance is the sample-and-
hold circuit. A sample-and-hold circuit can be useful for an analog to digital converter (ADC) to sample a varying
input voltage with improved reliability and stability. It can also be used to store the output samples from a single
digital-to-analog converter (DAC) in a multi-output application. A simple sample-and-hold circuit can be realized
using an analog switch such as the TMUX1101, and TMUX1102 analog switches. 图 27 shows a single channel
sample-and hold circuit using either of the TMUX110x devices.
TMUX110x
DAC
+
OP AMP
+
RL
VOUT
CL
œ
OP AMP
CH
SEL
œ
(1.8V Capable Control Logic)
图 27. Single Channel Sample-and-Hold Circuit Example
An optional op amp is used before the switch since driving large capacitive loads is a typical limitation of buffered
DACs. The additional buffer stage is included following the DAC to prevent potential stability problems from
driving a large capacitive load.
Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch is toggled,
some amount of charge is transferred to the switch output in the form of charge injection, resulting in a pedestal
sampling error. The TMUX1101 and TMUX1102 switches have excellent charge injection performance of only
-1.5 pC, making them ideal choices for this implementation to minimize sampling error. The pedestal error
voltage is indirectly related to the size of the capacitance on the output, for better precision a larger capacitor is
required due to charge injection.
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Typical Application - Sample-and-Hold Circuit (接下页)
10.2.1 Design Requirements
The purpose of this precision design is to implement an optimized single channel sample-and-hold circuit using a
precision 1:1 (SPST) CMOS switch. The sample-and-hold circuit needs to be capable of supporting high
accuracy with minimized pedestal error and fast settling time.
10.2.2 Detailed Design Procedure
The TMUX1101 or TMUX1102 switch is used in conjunction with the voltage holding capacitors (CH) to
implement the sample-and-hold circuit. The basic operation is:
1. When the switch is closed, it samples the input voltage and charges the holding capacitors (CH) to the input
voltage values.
2. When the switch is open, the holding capacitors (CH) holds its previous value, maintaining stable voltage at
the amplifier output (VOUT).
Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors
droops with time. The TMUX1101 and TMUX1102 minimize the droops due to its ultra-low leakage performance.
At 25°C, the TMUX1101 and TMUX1102 have extremely low leakage current of 3pA typical.
Refer to Sample & Hold Glitch Reduction for Precision Outputs Reference Design for more information on
sample-and-hold circuits.
10.2.3 Application Curve
TMUX1101 and TMUX1102 have excellent charge injection performance and ultra-low leakage current, making
them ideal choices to minimize sampling error for the sample-and-hold application. The charge injection and
leakage performance are shown in 图 28 and 图 29 respectively.
20
15
10
5
80
VDD = 3.3 V
VDD = 5 V
60
40
20
0
0
-20
-40
-60
-80
-5
-10
-15
-20
0
1
2
3
4
5
0
1
2
3
4
5
VS or VD - Source or Drain Voltage (V)
VS - Source Voltage (V)
D006
D011
VDD = 5 V
TA = –40°C to +125°C
图 28. Charge Injection vs Source Voltage
图 29. On-Leakage vs Source or Drain Voltage
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10.3 Typical Application - Switched Gain Amplifier
Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable
gain control. By using various resistor values on the switch path, the TMUX110x allows the system to have
multiple gain settings. An external resistor ensures the amplifier isn't operating in an open loop configuration. A
transimpedance amplifier (TIA) for photodiode inputs is a common circuit that requires gain control using a switch
to convert the output current of the photodiode into a voltage for the MCU or processor. The amount of light
present during a photodiode measurement is dependent on the time of day and available light source. An
external switch such as the TMUX110x can be utilized to increase the gain when a smaller photodiode current is
present. The leakage current, capacitance, and charge injection performance of the TMUX110x are key
specifications to evaluate when selecting a device for gain control. An example switched gain amplifier circuit is
shown in 图 30.
VI/O
VDD
VDD
0.1µF
Processor
1.8V Logic I/O
SEL
Digital Processing
RF_2
RF_1
VDD
VDD
-
OP
AMP
Gain / Filter
Network
ADC
+
图 30. Configurable Gain Setting of a TIA circuit
10.3.1 Design Requirements
For this design example, use the parameters listed in 表 3.
表 3. Design parameters
PARAMETERS
Supply (VDD
VALUES
3.3 V
)
Input / Output signal range
Control logic thresholds
0 µA to 10 µA
1.8 V compatible
版权 © 2019, Texas Instruments Incorporated
25
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
10.3.2 Detailed Design Procedure
The TMUX110x devices can be operated without any external components except for the supply decoupling
capacitors. All inputs signals passing through the switch must fall within the recommended operating conditions
of the TMUX110x, including signal range and continuous current. For this design example, with a supply of 3.3 V,
the signals can range from 0 V to 3.3 V when the device is powered. The max continuous current can be 30 mA.
Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps
based on the amount of light being absorbed. The TMUX110x devices have a typical On-leakage current of less
than 10 pA, which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF
capacitance of the TMUX110x improves system stability by minimizing the total capacitance on the output of the
amplifier. Lower capacitance leads to less overshoot and ringing in the system, which can cause the amplifier
circuit to become unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low CON
Multiplexers for more information on calculating the phase margin vs. percent overshoot.
10.3.3 Application Curve
The TMUX110x devices are capable of switching signals from high source-impedance inputs into a high input-
impedance op amp with minimal offset error because of the ultra-low leakage currents.
20
15
10
VDD = 1.98 V
VDD = 3.63 V
VDD = 1.32 V
5
0
-5
-10
-15
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
VS or VD - Source or Drain Voltage (V)
D005
TA = 25°C
图 31. On-Leakage vs Source or Drain Voltage
26
版权 © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
11 Power Supply Recommendations
The TMUX110x devices operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute
maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
12 Layout
12.1 Layout Guidelines
12.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.图 32 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
图 32. Trace example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-
hole pins are not recommended at high frequencies.
版权 © 2019, Texas Instruments Incorporated
27
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
Layout Guidelines (接下页)
图 33 illustrates an example of a PCB layout with the TMUX110x. Some key considerations are:
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
•
•
•
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
C
Wide (low inductance)
trace for power
TMUX110x
Via to
GND plane
图 33. TMUX110x Layout example
28
版权 © 2019, Texas Instruments Incorporated
TMUX1101, TMUX1102
www.ti.com.cn
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
德州仪器 (TI)，《通过采样保持减少干扰实现精密输出的参考设计》。
德州仪器 (TI)，《真差分 4 x 2 多路复用器、模拟前端、同步采样 ADC 电路》。
德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。
德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。
德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。
德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 4. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TMUX1101
TMUX1102
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2019, Texas Instruments Incorporated
29
TMUX1101, TMUX1102
ZHCSJG7B –MARCH 2019–REVISED AUGUST 2019
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1101DBVR
TMUX1101DCKR
TMUX1102DBVR
TMUX1102DCKR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DBV
DCK
5
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1W1F
101
NIPDAU
NIPDAU
NIPDAU
SOT-23
SC70
1W3F
102
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1101DBVR
TMUX1101DCKR
TMUX1102DBVR
TMUX1102DCKR
SOT-23
SC70
DBV
DCK
DBV
DCK
5
5
5
5
3000
3000
3000
3000
180.0
178.0
180.0
178.0
8.4
9.0
8.4
9.0
3.2
2.4
3.2
2.4
3.2
2.5
3.2
2.5
1.4
1.2
1.4
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
SOT-23
SC70
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1101DBVR
TMUX1101DCKR
TMUX1102DBVR
TMUX1102DCKR
SOT-23
SC70
DBV
DCK
DBV
DCK
5
5
5
5
3000
3000
3000
3000
210.0
180.0
210.0
180.0
185.0
180.0
185.0
180.0
35.0
18.0
35.0
18.0
SOT-23
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
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TI
TMUX1104DQAR
3pA 导通状态泄漏电流、5V、4:1、单通道精密多路复用器 | DQA | 10 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TMUX1108
3pA 导通状态泄漏电流、5V、±2.5V、8:1、单通道精密多路复用器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TMUX1108PWR
3pA 导通状态泄漏电流、5V、±2.5V、8:1、单通道精密多路复用器 | PW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TMUX1108RSVR
3pA 导通状态泄漏电流、5V、±2.5V、8:1、单通道精密多路复用器 | RSV | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TMUX1109
3pA 导通状态泄漏电流、5V、±2.5V、4:1、2 通道精密多路复用器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TMUX1109PWR
3pA 导通状态泄漏电流、5V、±2.5V、4:1、2 通道精密多路复用器 | PW | 16 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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