TMUX1122DGKR [TI]

3pA 导通状态泄漏电流、5V、1:1 (SPST)、2 通道精密开关（低电平有效） | DGK | 8 | -40 to 125;


型号：	TMUX1122DGKR
厂家：	TEXAS INSTRUMENTS
描述：	3pA 导通状态泄漏电流、5V、1:1 (SPST)、2 通道精密开关（低电平有效） \| DGK \| 8 \| -40 to 125 开关
文件：	总38页 (文件大小：1554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

TMUX112x 5V、低泄漏电流、1:1 (SPST)、2 通道精密开关

1 特性

3 说明

•

宽电源电压范围：1.08V 至 5.5V

低泄漏电流：3pA

TMUX1121、TMUX1122 和 TMUX1123 是精密互补

金属氧化物半导体 (CMOS) 器件，具有两个独立可选

1:1、单极单投 (SPST) 开关。1.08V 至 5.5V 的宽电源

电压工作范围可支持医疗设备到工业系统的大量应

用。该器件可在源极 (Sx) 和漏极 (Dx) 引脚上支持从

GND 到 V_DD范围的双向模拟和数字信号。

•

低电荷注入：–1.5pC

低导通电阻：1.9Ω

–40°C 至 +125°C 工作温度

1.8V 逻辑兼容

失效防护逻辑

TMUX1121 的开关可在恰当的逻辑控制输入下通过逻

辑 1 打开，而要打开 TMUX1122 中的开关，则需逻辑

0。TMUX1123 的两个通道分别支持逻辑 1 和逻辑 0。

TMUX1123 具有先断后合开关，因此该器件可用于交

叉点开关应用。

轨至轨运行

双向信号路径

先断后合开关

ESD 保护 HBM：2000V

2 应用

TMUX112x 器件是精密开关和多路复用器器件系列中

的一部分。这些器件具有非常低的导通和关断泄漏电流

以及较低的电荷注入，因此可用于高精度测量应用。

7nA 的低电源电流和小型封装选项使其可用于便携式

应用。

•

采样保持电路

反馈增益开关

信号隔离

现场变送器

可编程逻辑控制器 (PLC)

工厂自动化和控制

超声波扫描仪

器件信息⁽¹⁾

器件型号

TMUX1121

封装

封装尺寸（标称值）

TMUX1122

TMUX1123

VSSOP (8) (DGK)

3.00mm × 3.00mm

患者监护和诊断

心电图 (ECG)

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

数据采集系统 (DAQ)

半导体测试设备

电池测试设备

SPACER

空白

仪表：实验室、分析、便携

超声波智能仪表：水表和燃气表

光纤网络

SPACER

光学测试设备

TMUX112x 方框图

CHANNEL 1

CHANNEL 2

CHANNEL 1

CHANNEL 2

SEL1

SEL2

SEL1

SEL2

SEL1

SEL2

TMUX1121

TMUX1122

TMUX1123

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS413

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

8.8 Channel-to-Channel Crosstalk................................ 19

8.9 Bandwidth ............................................................... 20

Detailed Description ............................................ 21

9.1 Overview ................................................................. 21

9.2 Functional Block Diagram ....................................... 21

9.3 Feature Description................................................. 21

9.4 Device Functional Modes........................................ 23

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics (V_DD= 5 V ±10 %)............ 5

7.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)......... 7

7.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)......... 9

7.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)....... 11

7.9 Typical Characteristics............................................ 13

Parameter Measurement Information ................ 16

8.1 On-resistance.......................................................... 16

8.2 Off-leakage current ................................................. 16

8.3 On-leakage current ................................................. 17

8.4 Transition time......................................................... 17

8.5 Break-before-make ................................................. 18

8.6 Charge injection ...................................................... 18

8.7 Off isolation ............................................................. 19

10 Application and Implementation........................ 24

10.1 Application Information.......................................... 24

10.2 Typical Application - Sample-and-Hold Circuit .... 24

10.3 Typical Application - Switched Gain Amplifier ..... 26

11 Power Supply Recommendations ..................... 28

12 Layout................................................................... 28

12.1 Layout Guidelines ................................................. 28

12.2 Layout Example .................................................... 29

13 器件和文档支持 ..................................................... 30

13.1 文档支持................................................................ 30

13.2 相关链接................................................................ 30

13.3 接收文档更新通知 ................................................. 30

13.4 社区资源................................................................ 30

13.5 商标....................................................................... 30

13.6 静电放电警告......................................................... 30

13.7 Glossary................................................................ 30

14 机械、封装和可订购信息....................................... 30

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (August 2019) to Revision A

Page

•

将文档从预告信息更改为生产数据........................................................................................................................................ 1

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

5 Device Comparison Table

PRODUCT

TMUX1121

TMUX1122

DESCRIPTION

Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active High)

Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active Low)

TMUX1123

Low-Leakage-Current, 1:1 (SPST), 2-Channel Precision Switches (Active High + Active Low)

6 Pin Configuration and Functions

DGK Package

8-Pin VSSOP

Top View

SEL1

SEL2

GND

Not to scale

Pin Functions

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

NO.

I/O

Source pin 1. Can be an input or output.

Drain pin 1. Can be an input or output.

SEL2

GND

Logic control select pin 2. Controls channel 2 state as shown in Truth Tables.

Ground (0 V) reference

I/O

Source pin 2. Can be an input or output.

Drain pin 2. Can be an input or output.

SEL1

Logic control select pin 1. Controls channel 1 state as shown in Truth Tables.

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

V_DD

(1) I = input, O = output, I/O = input and output, P = power

(2) Refer to Device Functional Modes for what to do with unused pins

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

–0.5

–30

–0.5

–30

–65

MAX

UNIT

V_DD

Supply voltage

V_SEL

Logic control input pin voltage (SELx)

Logic control input pin current (SELx)

Source or drain voltage (Sx, Dx)

Source or drain continuous current (Sx, Dx)

Storage temperature

I_SEL

V_Sor V_D

I_Sor I_{D (CONT)}

T_stg

V_DD+0.5

°C

150

T_J

Junction temperature

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

±2000

ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.08

NOM

MAX

5.5

UNIT

V_DD

Positive power supply voltage

V_Sor V_D

V_SEL

Signal path input/output voltage (source or drain pins: Sx, Dx)

Logic control input pin voltage (SELx)

V_DD

5.5

I_Sor I_D

T_A

Signal path continuous current (source or drain pins: Sx, Dx)

Ambient temperature

–30

–40

°C

125

7.4 Thermal Information

TMUX1121 / TMUX1122 /

TMUX1123

THERMAL METRIC⁽¹⁾

UNIT

DGK (VSSOP)

8 PINS

205.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

91.7

127.0

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

25.9

Ψ_JB

125.3

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

7.5 Electrical Characteristics (V_DD= 5 V ±10 %)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

1.9

4.5

4.9

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.13

0.85

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

0.4

0.5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

1.6

V_DD= 5 V

Switch Off

V_D= 4.5 V / 1.5 V

V_S= 1.5 V / 4.5 V

Refer to Off-leakage current

–0.08 ±0.003

–0.3

0.08

0.3

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 5 V

Switch Off

V_D= 4.5 V / 1.5 V

V_S= 1.5 V / 4.5 V

Refer to Off-leakage current

25°C

–0.08 ±0.003

–0.3

0.08

0.3

–40°C to +85°C

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 5 V

Switch On

V_D= V_S= 4.5 V / 1.5 V

Refer to On-leakage current

25°C

–0.1 ±0.003

–0.35

0.1

I_D(ON)

–40°C to +85°C

0.35

Channel on leakage current

I_S(ON)

–40°C to +125°C

–2

LOGIC INPUTS (SELx)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.49

5.5

0.87

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.007

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

(1) When V_Sis 4.5 V, V_Dis 1.5 V or when V_Sis 1.5 V, V_Dis 4.5 V.

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 5 V ±10 %) (continued)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 3 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition time

V_S= 3 V

Break before make time

t_OPEN

(BBM)

R_L= 200 Ω, C_L= 15 pF

Refer to Break-before-make

–40°C to +85°C

–40°C to +125°C

(TMUX1123 Only)

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge injection

25°C

–1.5

–62

–40

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Channel-to-Channel

Crosstalk

25°C

–100

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–90

300

Refer to Channel-to-Channel

Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

7.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

3.7

8.8

9.5

9.8

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.13

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

0.4

0.5

1.9

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

2.2

V_DD= 3.3 V

Switch Off

V_D= 3 V / 1 V

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_S= 1 V / 3 V

Refer to Off-leakage current

–40°C to +125°C

–0.9

0.9

V_DD= 3.3 V

Switch Off

V_D= 3 V / 1 V

25°C

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_D(OFF)Drain off leakage current⁽¹⁾

V_S= 1 V / 3 V

Refer to Off-leakage current

–40°C to +125°C

–0.9

0.9

V_DD= 3.3 V

Switch On

V_D= V_S= 3 V / 1 V

Refer to On-leakage current

25°C

–0.1 ±0.003

–0.35

0.1

I_D(ON)

–40°C to +85°C

0.35

Channel on leakage current

I_S(ON)

–40°C to +125°C

–2

LOGIC INPUTS (SELx)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.35

5.5

0.8

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.004

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

(1) When V_Sis 3 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 3 V.

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 3.3 V ±10 %) (continued)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 2 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition time

V_S= 2 V

Break before make time

t_OPEN

(BBM)

R_L= 200 Ω, C_L= 15 pF

Refer to Break-before-make

–40°C to +85°C

–40°C to +125°C

(TMUX1123 Only)

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge injection

25°C

–1.5

–62

–40

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Channel-to-Channel

Crosstalk

25°C

–100

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–90

300

Refer to Channel-to-Channel

Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

7.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.4

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.98 V

Switch Off

V_D= 1.62 V / 1 V

V_S= 1 V / 1.62 V

Refer to Off-leakage current

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 1.98 V

Switch Off

V_D= 1.62 V / 1 V

V_S= 1 V / 1.62 V

Refer to Off-leakage current

25°C

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 1.98 V

Switch On

V_D= V_S= 1.62 V / 1 V

Refer to On-leakage current

25°C

–0.1 ±0.003

–0.35

0.1

I_D(ON)

–40°C to +85°C

0.35

Channel on leakage current

I_S(ON)

–40°C to +125°C

–2

LOGIC INPUTS (SELx)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.07

5.5

0.68

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.001

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.85

(1) When V_Sis 1.62 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 1.62 V.

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 1.8 V ±10 %) (continued)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition time

V_S= 1 V

Break before make time

t_OPEN

(BBM)

R_L= 200 Ω, C_L= 15 pF

Refer to Break-before-make

–40°C to +85°C

–40°C to +125°C

(TMUX1123 Only)

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge injection

25°C

–0.5

–62

–40

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Channel-to-Channel

Crosstalk

25°C

–100

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–90

300

Refer to Channel-to-Channel

Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1121, TMUX1122, TMUX1123

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7.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

105

0.4

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.32 V

Switch Off

V_D= 1 V / 0.8 V

V_S= 0.8 V / 1 V

Refer to Off-leakage current

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 1.32 V

Switch Off

V_D= 1 V / 0.8 V

V_S= 0.8 V / 1 V

Refer to Off-leakage current

25°C

–0.05 ±0.001

–0.2

0.05

0.2

–40°C to +85°C

I_D(OFF)Drain off leakage current⁽¹⁾

–40°C to +125°C

–0.9

0.9

V_DD= 1.32 V

Switch On

V_D= V_S= 1 V / 0.8 V

Refer to On-leakage current

25°C

–0.1 ±0.003

–0.35

0.1

I_D(ON)

–40°C to +85°C

0.35

Channel on leakage current

I_S(ON)

–40°C to +125°C

–2

LOGIC INPUTS (SELx)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

0.96

5.5

0.36

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.001

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.7

(1) When V_Sis 1 V, V_Dis 0.8 V or when V_Sis 0.8 V, V_Dis 1 V.

TMUX1121, TMUX1122, TMUX1123

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Electrical Characteristics (V_DD= 1.2 V ±10 %) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

190

Refer to Transition time

V_S= 1 V

Break before make time

t_OPEN

(BBM)

R_L= 200 Ω, C_L= 15 pF

Refer to Break-before-make

–40°C to +85°C

–40°C to +125°C

(TMUX1123 Only)

V_S= 1 V

Q_C

Charge Injection

Off Isolation

R_S= 0 Ω, C_L= 1 nF

Refer to Charge injection

25°C

–0.5

–62

–40

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off isolation

O_ISO

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Channel-to-Channel

Crosstalk

25°C

–100

X_TALK

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

25°C

–90

300

Refer to Channel-to-Channel

Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

MHz

C_SOFF

C_DOFF

Source off capacitance

Drain off capacitance

f = 1 MHz

25°C

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

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7.9 Typical Characteristics

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

4.5

V_DD= 3 V

V_DD= 3.63 V

V_DD= 4.5 V

T_A= 125°C

T_A= 85°C

T_A= 25°C

T_A= -40°C

V_DD= 5.5 V

3.5

2.5

1.5

0.5

V_Sor V_D- Source or Drain Voltage (V)

5.5

V_Sor V_D- Source or Drain Voltage (V)

D001

D002

T_A= 25°C

V_DD= 5 V

图 1. On-Resistance vs Source or Drain Voltage

图 2. On-Resistance vs Temperature

T_A= 125°C

T_A= 85°C

T_A= 25°C

T_A= -40°C

V_DD= 1.08 V

V_DD= 1.32 V

V_DD= 1.62 V

V_DD= 1.98 V

0.5

1.5

2.5

V_Sor V_D- Source or Drain Voltage (V)

3.5

0.2 0.4 0.6 0.8 1

V_Sor V_D- Source or Drain Voltage (V)

1.2 1.4 1.6 1.8

D003

D004

V_DD= 3.3 V

T_A= 25°C

图 3. On-Resistance vs Temperature

图 4. On-Resistance vs Source or Drain Voltage

VDD = 3.63 V

VDD = 1.98V

VDD = 1.32V

VDD = 5 V

-5

-20

-40

-60

-80

-10

-15

-20

0.5

V_Sor V_D- Source or Drain Voltage (V)

1.5

2.5

3.5

V_Sor V_D- Source or Drain Voltage (V)

D005

D006

T_A= 25°C

图 5. On-Leakage vs Source or Drain Voltage

图 6. On-Leakage vs Source or Drain Voltage

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Typical Characteristics (接下页)

0.75

0.5

1.5

I_OFF

I_ON

I_OFF

I_ON

0.25

0.5

-0.25

-0.5

-0.75

-1

-0.5

-1

-1.5

-2

-40

-20

100

120

-40

-20

100

120

Temperature (èC)

D007

D008

V_DD= 3.3 V

V_DD= 5 V

图 7. Leakage Current vs Temperature

图 8. Leakage Current vs Temperature

0.4

0.3

0.2

0.1

500

400

300

200

100

V_DD= 5 V

V_DD= 3.3 V

V_DD= 1.8 V

V_DD= 1.2 V

V_DD= 3.3 V

V_DD= 1.8 V

V_DD= 1.2 V

-0.1

-40

-20

100 120 140

0.5

1.5

2.5

Logic Voltage (V)

3.5

4.5

Temperature (èC)

D009

D010

V_SEL= 5.5 V

图 9. Supply Current vs Temperature

T_A= 25°C

图 10. Supply Current vs Logic Voltage

V_DD= 3.3 V

V_DD= 5 V

V_DD= 1.2 V

V_DD= 1.8 V

-5

-2

-4

-6

-8

-10

-15

-20

V_S- Source Voltage (V)

0.25

0.5

0.75

Source Voltage (V)

1.25

1.5

1.75

D011

D012

T_A= -40°C to 125°C

T_A= –40°C to 125°C

图 11. Charge Injection vs Source Voltage

图 12. Charge Injection vs Source Voltage

TMUX1121, TMUX1122, TMUX1123

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ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

Typical Characteristics (接下页)

Transition OFF

Transition ON

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

Off-Isolation

Crosstalk

1.5

2.5

3.5

V_DD- Supply Voltage (V)

4.5

5.5

100k

10M

Frequency (Hz)

100M

D013

D014

T_A= -40°C to +125°C

图 13. Output T_TRANSITIONvs Supply Voltage

图 14. Off-Isolation vs Frequency

-1

-2

-3

-4

-5

-6

10M

Frequency (Hz)

100M

D015

T_A= -40°C to +125°C

图 15. On Response vs Frequency

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8 Parameter Measurement Information

8.1 On-resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-resistance.

The measurement setup used to measure R_ONis shown in 图 16. Voltage (V) and current (I_SD) are measured

using this setup, and R_ONis computed with R_ON= V / I_SD

I_SD

V_S

图 16. On-Resistance measurement setup

8.2 Off-leakage current

There are two types of leakage currents associated with a switch during the off state:

1. Source off-leakage current

2. Drain off-leakage current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

The setup used to measure both off-leakage currents is shown in 图 17.

V_DD

I_{S (OFF)}

I_{D (OFF)}

V_S

V_D

V_S

I_{S (OFF)}

I_{D (OFF)}

V_S

V_D

V_S

GND

图 17. Off-leakage measurement setup

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8.3 On-leakage current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

Either the source pin or drain pin is left floating during the measurement. 图 18 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

V_DD

I_{S (ON)}

I_{D (ON)}

N.C.

V_S

V_D

I_{S (ON)}

I_{D (ON)}

N.C.

V_S

V_D

GND

图 18. On-leakage measurement setup

8.4 Transition time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal

has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of

the device. System level timing can then account for the time constant added from the load resistance and load

capacitance. 图 19 shows the setup used to measure transition time, denoted by the symbol t_TRANSITION

V_DD

0.1ꢀF

V_DD

t_f< 5ns

t_r< 5ns

V_SEL

V_IH

V_IL

OUTPUT

R_L

0 V

V_S

C_L

t_TRANSITION

OUTPUT

R_L

V_S

90%

C_L

SEL1 œ SEL2

OUTPUT

V_SEL

GND

10%

0 V

图 19. Transition-time measurement setup

TMUX1121, TMUX1122, TMUX1123

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8.5 Break-before-make

The TMUX1123 has break-before-make delay which allows the device to be used in cross-point switching

application. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. 图 20 shows the

setup used to measure break-before-make delay, denoted by the symbol t_OPEN(BBM)

V_DD

0.1ꢀF

V_DD

V_IH

V_SEL

V_IL

0 V

OUTPUT 1

C_L

V_S

90%

R_L

Output 2

0 V

OUTPUT 2

C_L

V_S

90%

Output 1

t_BBM2

R_L

t_BBM1

SEL1 œ SEL2

0 V

V_SEL

GND

t_BBM= min (t_BBM1,t_BBM2

)

图 20. Break-before-make delay measurement setup

8.6 Charge injection

The TMUX112x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS

and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the

gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,

and is denoted by the symbol Q_C. 图 21 shows the setup used to measure charge injection from source (Sx) to

drain (Dx).

V_DD

0.1ꢀF

V_DD

V_SEL

OUTPUT

V_OUT

C_L

V_S

0 V

Output

V_S

OUTPUT

V_OUT

C_L

V_S

Q_C= C_L

V_OUT

SEL1 œ SEL2

V_SEL

GND

图 21. Charge-injection measurement setup

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8.7 Off isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the

source pin (Sx) of an off-channel. The characteristic impedance, Z₀, for the measurement is 50 Ω. 图 22 shows

the setup used to measure off isolation. Use off isolation equation to compute off isolation.

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Ω

V_SIG

V_OUT

R_L

50Ω

S_X/D_X

GND

R_L

50Ω

图 22. Off isolation measurement setup

≈

∆

’

◊

V_OUT

V_S

Off Isolation = 20 ∂ Log

(1)

8.8 Channel-to-Channel Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. The characteristic impedance, Z₀, for the measurement is 50 Ω. 图 23

shows the setup used to measure, and the equation used to compute crosstalk.

V_DD

0.1µF

NETWORK

V_DD

ANALYZER

V_OUT

R_L

50Ω

V_S

R_L

50Ω

V_SIG= 200 mVpp

V_BIAS= V_DD/ 2

GND

图 23. Channel-to-Channel Crosstalk Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Channel-to-Channel Crosstalk = 20 ∂ Log

(2)

TMUX1121, TMUX1122, TMUX1123

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8.9 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The

characteristic impedance, Z₀, for the measurement is 50 Ω. 图 24 shows the setup used to measure bandwidth.

V_DD

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Ω

V_SIG

V_OUT

R_L

50Ω

GND

图 24. Bandwidth measurement setup

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9 Detailed Description

9.1 Overview

The TMUX1121, TMUX1122, and TMUX1123 are 1:1 (SPST), 2-Channel switches. The devices have two

independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of

the corresponding select pin.

9.2 Functional Block Diagram

CHANNEL 1

CHANNEL 2

CHANNEL 1

CHANNEL 2

CHANNEL 1

CHANNEL 2

SEL1

SEL2

SEL1

SEL2

SEL1

SEL2

TMUX1121

TMUX1122

TMUX1123

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

图 25. TMUX112x Functional Block Diagram

9.3 Feature Description

9.3.1 Bidirectional operation

The TMUX112x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

9.3.2 Rail to rail operation

The valid signal path input/output voltage for TMUX112x ranges from GND to V_DD

9.3.3 1.8 V Logic compatible inputs

The TMUX112x devices have 1.8-V logic compatible control for all logic control inputs. The logic input thresholds

scale with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level

inputs allows the TMUX112x devices to interface with processors that have lower logic I/O rails and eliminates

the need for an external translator, which saves both space and BOM cost. The current consumption of the

TMUX112x devices increase when using 1.8V logic with higher supply voltage as shown in 图 10. For more

information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches

9.3.4 Fail-safe logic

The TMUX112x supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5

V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before

the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by

removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the select pins of the TMUX112x to be ramped to 5.5 V while V_DD= 0 V. Additionally, the feature

enables operation of the TMUX112x with V_DD= 1.2 V while allowing the select pins to interface with a logic level

of another device up to 5.5 V.

TMUX1121, TMUX1122, TMUX1123

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Feature Description (接下页)

9.3.5 Ultra-low Leakage Current

The TMUX112x devices provide extremely low on-leakage and off-leakage currents. The TMUX112x devices are

capable of switching signals from high source-impedance inputs into a high input-impedance op amp with

minimal offset error because of the ultra-low leakage currents. 图 26 shows typical leakage currents of the

TMUX112x devices versus temperature at V_DD= 5V.

I_OFF

I_ON

1.5

0.5

-0.5

-1

-1.5

-2

-40

-20

100

120

Temperature (èC)

D008

图 26. Leakage Current vs Temperature

9.3.6 Ultra-low Charge Injection

The TMUX112x devices have a transmission gate topology, as shown in 图 27. Any mismatch in the stray

capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is

opened or closed.

The TMUX112x devices have special charge-injection cancellation circuitry that reduces the source-to-drain

charge injection to -1.5 pC at V_S= 1 V as shown in 图 28.

SPACER

OFF ON

V_DD= 3.3 V

V_DD= 5 V

C_GDN

C_GSN

-5

-10

-15

-20

C_GSP

C_GDP

V_S- Source Voltage (V)

OFF ON

D011

图 28. Charge Injection vs Source Voltage

图 27. Transmission Gate Topology

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9.4 Device Functional Modes

The TMUX112x devices have two independently selectable single-pole, single-throw switches that are turned-on

or turned-off based on the state of the corresponding select pin. The control pins can be as high as 5.5 V.

The TMUX112x devices can be operated without any external components except for the supply decoupling

capacitors. Unused logic control pins should be tied to GND or V_DDin order to ensure the device does not

consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path

inputs (Sx or Dx) should be connected to GND.

9.4.1 Truth Tables

表 1, 表 2, and 表 3 show the truth tables for the TMUX1121, TMUX1122, and TMUX1123, respectively.

表 1. TMUX1121 Truth table⁽¹⁾

SEL1

SEL2

CHANNEL STATE

Channel 1 OFF

Channel 1 ON

Channel 2 OFF

Channel 2 ON

(1) X denotes don't care.

表 2. TMUX1122 Truth table⁽¹⁾

SEL1

SEL2

CHANNEL STATE

Channel 1 ON

Channel 1 OFF

Channel 2 ON

Channel 2 OFF

(1) X denotes don't care.

表 3. TMUX1123 Truth table⁽¹⁾

SEL1

SEL2

CHANNEL STATE

Channel 1 OFF

Channel 1 ON

Channel 2 ON

Channel 2 OFF

(1) X denotes don't care.

TMUX1121, TMUX1122, TMUX1123

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices

operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX112x

have a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These

features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for low-

voltage applications.

10.2 Typical Application - Sample-and-Hold Circuit

One useful application to take advantage of the TMUX1121, TMUX1122, and TMUX1123 performance is the

sample-and-hold circuit. A sample-and-hold circuit can be useful for an analog to digital converter (ADC) to

sample a varying input voltage with improved reliability and stability. It can also be used to store the output

samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample-and-hold

circuit can be realized using an analog switch such as the TMUX1121, TMUX1122, and TMUX1123 analog

switches. 图 29 shows a single channel sample-and hold circuit using only 1 of 2 channels in the TMUX112x

devices.

TMUX112x

DAC

OP AMP

R_L

V_OUT

C_L

OP AMP

C_H

SEL1

2 Channels

(1.8V Capable Control Logic)

SEL2

图 29. Single Channel Sample-and-Hold Circuit Example

An optional operational amplifier is used before the switch since buffered DACs typically have limitations in

driving capacitive loads. The additional buffer stage is included following the DAC to prevent potential stability

problems from driving a large capacitive load.

Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets

toggled, some amount of charge also gets transferred to the switch output in the form of charge injection,

resulting in a pedestal sampling error. The TMUX1121, TMUX1122, and TMUX1123 switches have excellent

charge injection performance of only -1.5 pC, making them ideal choices for this implementation to minimize

sampling error. The pedestal error voltage is indirectly related to the size of the capacitance on the output, for

better precision a larger capacitor is required due to charge injection. Larger capacitance limits the system

settling time which may not be acceptable in some applications. 图 30 shows a TMUX112x device configured for

a 2-channel sample-and-hold circuit with pedestal error compensation.

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Typical Application - Sample-and-Hold Circuit (接下页)

C_H

V_DD

SW1

R_L

C_C

R_C

V_OUT1

C_L

V_IN1

OPA2192

DAC9881

SW2

OPA2192

SEL1/

SEL2

C_H

TMUX112x

图 30. 2-Channel Sample-and-Hold Circuit with Pedestal Error Compensation

10.2.1 Design Requirements

The purpose of this precision design is to implement an optimized 2-output sample-and-hold circuit using a 2-

channel 1:1 (SPST) switch. The sample and hold circuit needs to be capable of supporting high accuracy with

minimized pedestal error and fast settling time..

10.2.2 Detailed Design Procedure

The TMUX1121, TMUX1122, or TMUX1123 switch is used in conjunction with the voltage holding capacitors

(C_H) to implement the sample-and-hold circuit. The basic operation is:

1. When the switch (SW2) is closed, it samples the input voltage and charges the holding capacitors (C_H) to the

input voltages values.

2. When the switch (SW2) is open, the holding capacitors (C_H) holds its previous value, maintaining stable

voltage at the amplifier output (V_OUT).

Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors

droops with time. The TMUX1121, TMUX1122, or TMUX1123 minimize the droops due to its ultra-low leakage

performance. At 25°C, the TMUX1121, TMUX1122, andTMUX1123 have extremely low leakage current at 3 pA

typical.

A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch

toggling. Because both switches are driven at the same potential, they act as common-mode signal to the op-

amp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation network

consisting of R_Cand C_Cis also added to further reduce the pedestal error, whiling reducing the hold-time glitch

and improving the settling time of the circuit. Refer to Sample & Hold Glitch Reduction for Precision Outputs

Reference Design for more information on sample-and-hold circuits.

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

Typical Application - Sample-and-Hold Circuit (接下页)

10.2.3 Application Curve

TMUX1121, TMUX1122, andTMUX1123 have excellent charge injection performance and ultra-low leakage

current, making them ideal choices to minimize sampling error for the sample and hold application.

V_DD= 3.3 V

V_DD= 5 V

VDD = 5 V

-20

-40

-60

-80

-5

-10

-15

-20

V_Sor V_D- Source or Drain Voltage (V)

V_S- Source Voltage (V)

D006

D011

V_DD= 5 V

T_A= -40°C to +125°C

图 31. Charge Injection vs Source Voltage

图 32. On-Leakage vs Source or Drain Voltage

10.3 Typical Application - Switched Gain Amplifier

Switches and multiplexers are commonly used in the feedback path of amplifier circuits to provide configurable

gain control. By using various resistor values on each switch path the TMUX112x allows the system to have

multiple gain settings. An external resistor, or utilizing 1 channel always being closed, ensures the amplifier isn't

operating in an open loop configuration. A transimpedance amplifier (TIA) for photodiode inputs is a common

circuit that requires gain control using a multi-channel switch to convert the output current of the photodiode into

a voltage for the MCU or processor. The leakage current, capacitance, and charge injection performance of the

TMUX112x are key specifications to evaluate when selecting a device for gain control.

V_I/O

V_DD

0.1µF

Processor

SEL1

SEL2

1.8V Logic I/O

R_{F_1}

R_{F_2}

Digital Processing

V_DD

Gain / Filter

Network

ADC

AMP

I_PD

图 33. Switching Gain Settings of a TIA circuit

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

Typical Application - Switched Gain Amplifier (接下页)

10.3.1 Design Requirements

For this design example, use the parameters listed in 表 4.

表 4. Design parameters

PARAMETERS

VALUES

3.3 V

Supply (V_DD

)

Input / Output signal range

Control logic thresholds

0 µA to 10 µA

1.8 V compatible

10.3.2 Detailed Design Procedure

The TMUX112x devices can be operated without any external components except for the supply decoupling

capacitors. All inputs signals passing through the switch must fall within the recommend operating conditions of

the TMUX112x including signal range and continuous current. For this design example, with a supply of 3.3 V,

the signals can range from 0 V to 3.3 V when the device is powered. The max continuous current can be 30 mA.

Photodiodes commonly have a current output that ranges from a few hundred picoamps to tens of microamps

based on the amount of light being absorbed. The TMUX112x have a typical On-leakage current of less than 10

pA which would lead to an accuracy well within 1% of a full scale 10 µA signal. The low ON and OFF

capacitance of the TMUX112x improves system stability by minimizing the total capacitance on the output of the

amplifier. Lower capacitance leads to less overshoot and ringing in the system which can cause the amplifier

circuit to go unstable if the phase margin is not at least 45°. Refer to Improve Stability Issues with Low C_ON

Multiplexers for more information on calculating the phase margin vs. percent overshoot.

10.3.3 Application Curve

The TMUX1121 is capable of switching signals from high source-impedance inputs into a high input-impedance

op amp with minimal offset error because of the ultra-low leakage currents.

VDD = 3.63 V

VDD = 1.98V

VDD = 1.32V

-5

-10

-15

-20

0.5

1.5

2.5

V_Sor V_D- Source or Drain Voltage (V)

3.5

D005

T_A= 25°C

图 34. On-Leakage vs Source or Drain Voltage

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

11 Power Supply Recommendations

The TMUX112x operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum

ratings because stresses beyond the listed ratings can cause permanent damage to the devices.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the V_DDsupply to

other components. Good power-supply decoupling is important to achieve optimum performance. For improved

supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from V_DDto ground.

Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance

connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series

resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive

systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to

the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall

inductance and is beneficial for connections to ground planes.

12 Layout

12.1 Layout Guidelines

12.1.1 Layout Information

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight, and therefore; some traces must

turn corners.图 35 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

图 35. Trace example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points, through-

hole pins are not recommended at high frequencies.

TMUX1121, TMUX1122, TMUX1123

www.ti.com.cn

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

Layout Guidelines (接下页)

图 36 illustrates an example of a PCB layout with the TMUX112x. Some key considerations are:

•

Decouple the V_DDpin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the V_DDsupply.

•

Keep the input lines as short as possible.

Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

12.2 Layout Example

Wide (low inductance)

trace for power

VDD

SEL1

TMUX112x

SEL2 3

GND 4

Via to

GND plane

Not to scale

图 36. TMUX112x Layout example

TMUX1121, TMUX1122, TMUX1123

ZHCSK59A –AUGUST 2019–REVISED SEPTEMBER 2019

www.ti.com.cn

13 器件和文档支持

13.1 文档支持

13.1.1 相关文档

德州仪器 (TI)，《通过采样保持减少干扰实现精密输出的参考设计》。

德州仪器 (TI)，《真差分 4 x 2 多路复用器、模拟前端、同步采样 ADC 电路》。

德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。

德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。

德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。

德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。

13.2 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 5. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具与软件

单击此处

支持和社区

单击此处

TMUX1121

TMUX1122

TMUX1123

13.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.4 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.5 商标

E2E is a trademark of Texas Instruments.

13.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TMUX1121DGKR

TMUX1122DGKR

TMUX1123DGKR

ACTIVE

VSSOP

DGK

2500 RoHS & Green

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

121

122

123

NIPDAUAG

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMUX1121DGKR

TMUX1122DGKR

TMUX1123DGKR

VSSOP

DGK

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMUX1121DGKR

TMUX1122DGKR

TMUX1123DGKR

VSSOP

DGK

2500

364.0

27.0

Pack Materials-Page 2

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TMUX1122DGKR [TI]

相关型号：

TMUX1123

TMUX1123DGKR

TMUX1133

TMUX1133PWR

TMUX1134

TMUX1134PWR

TMUX1136

TMUX1136DGSR

TMUX1136DQAR

TMUX1204

TMUX1204DGSR

TMUX1204DQAR