TMUX7201_技术文档

TMUX7201, TMUX7202

ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

TMUX720x 具有闩锁效应抑制和1.8V 逻辑电平的44V、低RON、1:1 (SPST)、单

通道精密开关

1 特性

3 说明

• 闩锁效应抑制

TMUX720x 是一款具有闩锁效应抑制特性的互补金属

氧化物半导体 (CMOS) 开关，采用单通道 1:1 (SPST)

配置。此器件在单电源（4.5 V 至 44 V）、双电源

（±4.5 V 至 ±22 V）或非对称电源（例如 V_DD= 12

V，V_SS= –5 V）供电时均能正常运行。TMUX720x

可在源极 (S) 和漏极 (D) 引脚上支持从 V_SS到 V_DD的

双向模拟和数字信号。

• 双电源电压范围：±4.5 V 至±22 V

• 单电源电压范围：4.5 V 至44 V

• 低导通电阻：1.2Ω

• 低电荷注入：-10 pC

• –40°C 至+125°C 工作温度

• 逻辑引脚上带有集成下拉电阻器

• 兼容1.8V 逻辑电平

• 失效防护逻辑

可以通过控制 SEL 引脚来启用或禁用 TMUX720x。当

禁用时，两个信号路径开关都被关闭。所有逻辑控制输

入均支持 1.8V 至V_DD的逻辑电平，当器件在有效电源

电压范围内运行时，可与TTL 和CMOS 逻辑兼容。失

效防护逻辑电路允许先在控制引脚上施加电压，然后在

电源引脚上施加电压，从而保护器件免受潜在的损害。

• 轨到轨运行

• 双向信号路径

• 先断后合开关

2 应用

• 光纤网络

• 光学测试设备

• 有线网络

• 工厂自动化和工业控制

• 可编程逻辑控制器(PLC)

• 半导体测试

TMUX72xx 系列具有闩锁效应抑制特性，可防止器件

内寄生结构之间通常由过压事件引起的大电流不良事

件。闩锁状态通常会一直持续到电源轨关闭为止，并可

能导致器件故障。闩锁效应抑制特性使得 TMUX72xx

系列开关和多路复用器能够在恶劣的环境中使用。

封装信息⁽¹⁾

• 超声波扫描仪

• 患者监护和诊断

• 远程无线电单元

• 数据采集系统

封装尺寸（标称值）

器件型号

TMUX7202

封装

DGK（VSSOP，8） 3.00mm × 3.00mm

RQX（WQFN，8） 3.00mm × 2.00mm

TMUX7201

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

V_DDV_SS

V_DD

V_SS

SW

D

S

SEL

TMUX7201

TMUX7202

(SELx = Logic 1)

方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS443

TMUX7201, TMUX7202

ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

www.ti.com.cn

Table of Contents

7.6 Propagation Delay.................................................... 21

7.7 Charge Injection........................................................22

7.8 Off Isolation...............................................................22

7.9 Bandwidth................................................................. 23

7.10 THD + Noise........................................................... 23

7.11 Power Supply Rejection Ratio (PSRR)................... 24

8 Detailed Description......................................................24

8.1 Overview...................................................................24

8.2 Functional Block Diagram.........................................24

8.3 Feature Description...................................................25

8.4 Device Functional Modes..........................................27

8.5 Truth Tables.............................................................. 27

9 Application and Implementation..................................28

9.1 Application Information............................................. 28

9.2 Typical Applications.................................................. 28

9.3 Power Supply Recommendations.............................30

9.4 Layout....................................................................... 30

10 Device and Documentation Support..........................32

10.1 Documentation Support.......................................... 32

10.2 接收文档更新通知................................................... 32

10.3 支持资源..................................................................32

10.4 Trademarks.............................................................32

10.5 静电放电警告.......................................................... 32

10.6 术语表..................................................................... 32

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Thermal Information....................................................5

6.4 Recommended Operating Conditions.........................5

6.5 Source or Drain Continuous Current...........................5

6.6 ±15 V Dual Supply: Electrical Characteristics ............6

6.7 ±15 V Dual Supply: Switching Characteristics ...........7

6.8 ±20 V Dual Supply: Electrical Characteristics.............8

6.9 ±20 V Dual Supply: Switching Characteristics............9

6.10 44 V Single Supply: Electrical Characteristics ....... 10

6.11 44 V Single Supply: Switching Characteristics .......11

6.12 12 V Single Supply: Electrical Characteristics ....... 12

6.13 12 V Single Supply: Switching Characteristics ...... 13

6.14 Typical Characteristics............................................14

7 Parameter Measurement Information..........................19

7.1 On-Resistance.......................................................... 19

7.2 Off-Leakage Current................................................. 19

7.3 On-Leakage Current................................................. 20

7.4 t_ONand t_OFFTime......................................................20

7.5 t_{ON (VDD)}Time............................................................21

Information.................................................................... 32

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (October 2022) to Revision A (March 2023)

Page

• 将数据表的状态从预告信息更改为量产数据 .....................................................................................................1

English Data Sheet: SCDS443

2

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5 Pin Configuration and Functions

S

NC

1

2

3

4

8

7

6

5

D

S

NC

1

2

3

4

8

7

6

5

D

VSS

SEL

NC

VSS

SEL

NC

Thermal

Pad

GND

VDD

GND

VDD

Not to scale

图5-2. RQX Package, 8-Pin WSON (Top View)

图5-1. DGK Package, 8-Pin VSSOP (Top View)

表5-1. Pin Functions

DGK

1

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

S

RQX

1

2

3

I/O

NC

P

Source pin. Can be an input or output.

NC

2

No connection. Not internally connected.

Ground (0 V) reference

GND

3

Positive power supply. This pin is the most positive power-supply potential. For reliable

operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand

GND.

V_DD

4

P

NC

5

6

5

6

NC

I

No connection. Not internally connected.

Logic control input, has internal Pull-Down resistor. For information about the switch

connection controls, see 节8.5.

SEL

Negative power supply. This pin is the most negative power-supply potential. In single-supply

applications, this pin can be connected to ground. For reliable operation, connect a decoupling

capacitor ranging from 0.1 µF to 10 µF between V_SSand GND.

V_SS

7

8

7

8

P

D

I/O

Drain pin. Can be an input or output.

The thermal pad is not connected internally. No requirement to solder this pad, if connected it

is recommended that the pad be left floating or tied to GND

Thermal Pad

—

(1) I = input, O = output, I/O = input or output, P = power, NC = no connection.

(2) For what to do with unused pins, refer to 节8.4.

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English Data Sheet: SCDS443

TMUX7201, TMUX7202

ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

V

48

V_DD–V_SS

V_DD

Supply voltage

48

V

–0.5

–48

V_SS

0.5

V

V_SELor V_EN

I_SELor I_EN

V_Sor V_D

I_IK

Logic control input pin voltage (SELx)

Logic control input pin current (SELx)

Source or drain voltage (Sx, Dx)

Diode clamp current⁽³⁾

48

V

–0.5

30

V_DD+0.5

30

mA

V

–30

V_SS–0.5

–30

mA

°C

I_Sor I_{D (CONT)}

T_A

Source or drain continuous current (Sx, Dx)

Ambient temperature

I_DC+ 10 %⁽⁴⁾

150

–55

–65

T_stg

Storage temperature

150

T_J

Junction temperature

150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Absolute Maximum Ratings. If used

outside the Absolute Maximum Ratings but within the Absolute Maximum Ratings, the device may not be fully functional, and this may

affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

(4) Refer to Source or Drain Continuous Current table for I_DCspecifications.

6.2 ESD Ratings

VALUE

UNIT

TMUX720x

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

English Data Sheet: SCDS443

4

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6.3 Thermal Information

TMUX720x

THERMAL METRIC⁽¹⁾

DGK (VSSOP)

8 PINS

152.1

48.4

RQX (WQFN)

8 PINS

62.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

54.0

73.2

31.0

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.1

0.8

Ψ_JT

71.8

30.9

Ψ_JB

R_θJC(bot)

N/A

23.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

V_SS

0

NOM

MAX

44

UNIT

V

(1)

Power supply voltage differential

V_DD–V_SS

V_DD

Positive power supply voltage

44

V

V_Sor V_D

V_SELor V_EN

Signal path input/output voltage (source or drain pin) (Sx, D)

Address or enable pin voltage

V_DD

44

V

(2)

I_Sor I_{D (CONT)}Source or drain continuous current (Sx, D)

T_AAmbient temperature

I_DC

mA

°C

125

–40

(1) V_DDand V_SScan be any value as long as 4.5 V ≤(V_DD–V_SS) ≤44 V, and the minimum V_DDis met.

(2) Refer to Source or Drain Continuous Current table for I_DCspecifications.

6.5 Source or Drain Continuous Current

at supply voltage of V_DD± 10%, V_SS± 10 % (unless otherwise noted)

(2)

CONTINUOUS CURRENT PER CHANNEL (I_DC

PACKAGE TEST CONDITIONS

+44 V Dual Supply⁽¹⁾

)

T_A= 25°C

T_A= 85°C

T_A= 125°C

UNIT

440

420

330

300

650

600

500

450

280

260

210

200

350

340

300

265

140

130

125

120

165

150

145

135

mA

±15 V Dual Supply

+12 V Single Supply

±5 V Dual Supply

DSK (VSSOP)

+44 V Single Supply⁽¹⁾

±15 V Dual Supply

+12 V Single Supply

±5 V Dual Supply

RQX (WQFN)

(1) Specified for nominal supply voltage only.

(2) Refer to Total power dissipation (P_tot) limits in Absolute Maximum Ratings table that must be followed with max continuous current

specification.

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English Data Sheet: SCDS443

TMUX7201, TMUX7202

ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

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MAX UNIT

6.6 ±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

1.2

1.7

2

Ω

V_S= –10 V to +10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

2.5

0.5

0.7

0.8

Ω

0.3

Ω

V_S= –10 V to +10 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.01

0.05

V_S= 0 V, I_S= –10 mA

Ω/°C

nA

0.3

3.4

33

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

–0.3

–3.4

–33

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

0.05

0.3

3.4

33

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

–0.3

–3.4

–33

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

0.65

2

–0.65

–2

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

16

–16

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.4

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

30

7

45

50

55

12

15

17

µA

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS443

6

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6.7 ±15 V Dual Supply: Switching Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ± 10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

120

140

155

170

150

160

190

ns

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

130

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

0.2

ms

–40°C to +125°C

t_PD

Propagation delay

Charge injection

25°C

450

-15

ps

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 0 V, C_L= 100 pF

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

BW

I_L

Off-isolation

25°C

dB

–70

–46

22

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Off-isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

MHz

dB

–3 dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

–0.11

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–40

V_PP= 15 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0007

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

45

65

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

240

pF

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English Data Sheet: SCDS443

TMUX7201, TMUX7202

ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

www.ti.com.cn

MAX UNIT

6.8 ±20 V Dual Supply: Electrical Characteristics

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

1

1.5

1.8

2.3

0.5

0.7

0.8

Ω

V_S= –15 V to +15 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.3

Ω

V_S= –15 V to +15 V

I_S= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.009

0.05

V_S= 0 V, I_S= –10 mA

Ω/°C

nA

0.4

5

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

V_D= –15 V / + 15 V

–0.4

–5

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

35

0.4

5

–35

–0.4

–5

0.05

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

V_D= –15 V / + 15 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

35

0.7

2

–35

–0.7

–2

V_DD= 22 V, V_SS= –22 V

Switch state is on

V_S= V_D= ±15 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

18

–18

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.4

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

38

8

50

60

70

15

19

23

µA

V_DD= 22 V, V_SS= –22 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 22 V, V_SS= –22 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS443

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6.9 ±20 V Dual Supply: Switching Characteristics

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

120

140

155

190

150

160

190

ns

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

120

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

0.2

ms

–40°C to +125°C

t_PD

Propagation delay

Charge injection

25°C

400

-20

ps

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 0 V, C_L= 100 pF

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

BW

I_L

Off-isolation

25°C

dB

–65

–45

22

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Off-isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

MHz

dB

–3 dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

–0.10

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–40

V_PP= 20 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0008

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

42

62

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

240

pF

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English Data Sheet: SCDS443

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ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

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MAX UNIT

6.10 44 V Single Supply: Electrical Characteristics

V_DD= +44 V, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +44 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

1.2

1.6

2

Ω

V_S= 0 V to 40 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

2.4

0.9

1.1

1.3

Ω

0.25

Ω

V_S= 0 V to 40 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.008

0.05

V_S= 22 V, I_S= –10 mA

Ω/°C

nA

1

10

60

1

V_DD= 44 V, V_SS= 0 V

Switch state is off

V_S= 40 V / 1 V

–1

–10

–60

–1

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 40 V

0.05

V_DD= 44 V, V_SS= 0 V

Switch state is off

V_S= 40 V / 1 V

I_D(OFF)

10

60

2

–40°C to +85°C

–40°C to +125°C

25°C

–10

–60

–2

V_D= 1 V / 40 V

V_DD= 44 V, V_SS= 0 V

Switch state is on

V_S= V_D= 40 V or 1 V

I_S(ON)

I_D(ON)

5

–40°C to +85°C

–40°C to +125°C

–5

30

–30

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.6

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

30

56

64

68

µA

V_DD= 44 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS443

10

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6.11 44 V Single Supply: Switching Characteristics

V_DD= +44 V, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +44 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

100

140

150

180

150

160

180

ns

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

125

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

0.17

ms

–40°C to +125°C

t_PD

Propagation delay

Charge injection

25°C

1000

-20

ps

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 22 V, C_L= 100 pF

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

O_ISO

BW

I_L

Off-isolation

25°C

dB

–66

–46

22

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Off-isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

MHz

dB

–3 dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

–0.11

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–36

V_PP= 22 V, V_BIAS= 22 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0008

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 22 V, f = 1 MHz

25°C

45

66

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 22 V, f = 1 MHz

25°C

240

pF

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English Data Sheet: SCDS443

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ZHCSNN0A –OCTOBER 2022 –REVISED MARCH 2023

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MAX UNIT

6.12 12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

ANALOG SWITCH

25°C

2.1

3.2

3.8

4.2

1.2

1.4

1.6

Ω

V_S= 0 V to 10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.5

Ω

V_S= 0 V to 10 V

I_S= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

Ω

0.017

0.05

V_S= 6 V, I_S= –10 mA

Ω/°C

nA

0.4

3

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

–0.4

–3

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

25

0.4

3

–25

–0.4

–3

0.05

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

I_D(OFF)

–40°C to +85°C

–40°C to +125°C

25°C

V_D= 1 V / 10 V

25

0.65

2

–25

–0.65

–2

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

12

–12

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.4

µA

pF

I_IL

–0.1 –0.005

C_IN

3.5

POWER SUPPLY

25°C

27

35

40

45

µA

V_DD= 13.2 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

English Data Sheet: SCDS443

12

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6.13 12 V Single Supply: Switching Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

125

145

160

180

205

220

ns

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

–40°C to +85°C

–40°C to +125°C

25°C

150

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

V_DDrise time = 1 µs

R_L= 300 Ω, C_L= 35 pF

Device turn on time

(V_DDto output)

t_{ON (VDD)}

0.2

ms

–40°C to +125°C

t_PD

Propagation delay

Charge injection

25°C

1000

-4

ps

R_L= 50 Ω, C_L= 5 pF

Q_INJ

V_S= 6 V, C_L= 100 pF

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

O_ISO

BW

I_L

Off-isolation

25°C

dB

–65

–45

23

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Off-isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

MHz

dB

–3 dB Bandwidth

Insertion loss

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

–0.18

V_PP= 0.62 V on V_DDand V_SS

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–40

V_PP= 6 V, V_BIAS= 6 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0009

C_S(OFF)

C_D(OFF)

C_S(ON)

C_D(ON)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

53

75

pF

,

On capacitance

V_S= 6 V, f = 1 MHz

25°C

240

pF

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6.14 Typical Characteristics

at T_A= 25°C

2

4

3.5

3

V_DD= 15 V, V_SS= -15 V

V_DD= 5 V, V_SS= -5 V

V_DD= 18 V, V_SS= -18 V

V_DD= 20 V, V_SS= -20 V

V_DD= 22 V, V_SS= -22 V

V_DD= 10 V, V_SS= -10 V

V_DD= 12 V, V_SS= -12 V

V_DD= 13.5 V, V_SS= -13.5 V

1.75

1.5

2.5

2

1.25

1

1.5

0.75

1

-25 -20 -15 -10

-5

0

5

10

15

20

25

-15 -12

-9

-6

-3

0

3

6

9

12

15

V_Sor V_D- Source or Drain Voltage (V)

图6-1. On-Resistance vs Source or Drain Voltage –Dual

图6-2. On-Resistance vs Source or Drain Voltage –Dual

Supply

2.25

6

V_DD= 18 V, V_SS= 0 V

V_DD= 24 V, V_SS= 0 V

V_DD= 36 V, V_SS= 0 V

V_DD= 44 V, V_SS= 0 V

V_DD= 5 V, V_SS= 0 V

V_DD= 8 V, V_SS= 0 V

V_DD= 10.8 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

5.5

2

1.75

1.5

5

V_DD= 15 V, V_SS= 0 V

4.5

4

3.5

3

1.25

1

2.5

2

0.75

1.5

0

4

8

12 16 20 24 28 32 36 40 44

0

1.5

3

4.5

6

7.5

9

10.5 12 13.5 15

V_Sor V_D- Source or Drain Voltage (V)

图6-3. On-Resistance vs Source or Drain Voltage –Single

图6-4. On-Resistance vs Source or Drain Voltage –Single

Supply

3

T_A= -40C

T_A= 25C

T_A= -40C

T_A= 25C

T_A= 85C

2.5

T_A= 125C

2

1.5

1

1.5

1

0.5

-15

-10

-5

0

5

10

15

-20 -16 -12

-8

-4

0

4

8

12

16

20

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

图6-5. On-Resistance vs Temperature

图6-6. On-Resistance vs Temperature

English Data Sheet: SCDS443

14

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6.14 Typical Characteristics (continued)

at T_A= 25°C

5.5

3

2.5

2

T_A= -40C

T_A= 25C

T_A= 85C

T_A= 125C

T_A= 25C

T_A= 85C

T_A= 125C

4.5

3.5

2.5

1.5

0.5

1.5

1

0.5

0

4

8

12

0

4

8

12

16

20

24

28

32

36

V_Sor V_D- Source or Drain Voltage (V)

V_DD= 12 V, V_SS= 0 V

V_DD= 36 V, V_SS= 0 V

图6-7. On-Resistance vs Temperature

图6-8. On-Resistance vs Temperature

20

12

I_ON-10 V

I_ON-15 V

10.5

9

7.5

6

4.5

3

1.5

0

16

12

8

I_DOFFV_S= -10 V, V_D= 10 V

I_SOFFV_S= -10 V, V_D= 10 V

I_DOFFV_S= 10 V, V_D= -10 V

I_SOFFV_S= 10 V, V_D= -10 V

I_ON10 V

I_DOFFV_S= -15 V, V_D= 15 V

I_SOFFV_S= -15 V, V_D= 15 V

I_DOFFV_S= 15 V, V_D= -15 V

I_SOFFV_S= 15 V, V_D= -15 V

I_ON15 V

4

0

-1.5

-3

-4

-4.5

-6

-8

-7.5

-9

-10.5

-12

-16

-20

0

25

50

75

100

125

0

25

50

75

100

125

Temperature (C)

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

图6-10. Leakage Current vs Temperature

图6-9. Leakage Current vs Temperature

20

16

12

8

10

8

I_ON1 V

I_DOFFV_S= 1 V, V_D= 30 V

I_SOFFV_S= 1 V, V_D= 30 V

I_DOFFV_S= 30 V, V_D= 1 V

I_SOFFV_S= 30 V, V_D= 1 V

I_ON30 V

I_DOFFV_S= 1 V, V_D= 10 V

I_SOFFV_S= 1 V, V_D= 10 V

I_DOFFV_S= 10 V, V_D= 1 V

I_SOFFV_S= 10 V, V_D= 1 V

I_ON10 V

6

4

2

0

-4

-2

-4

-6

-8

-12

-16

-20

-10

0

25

50

75

100

125

25

50

75

100

125

Temperature (C)

V_DD= 36 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

图6-11. Leakage Current vs Temperature

图6-12. Leakage Current vs Temperature

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6.14 Typical Characteristics (continued)

at T_A= 25°C

60

250

225

200

175

150

125

100

75

50

25

0

-25

-50

-75

-100

-125

-150

V_DD= 5 V, V_SS= -5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

V_DD= 5 V, V_SS= 0 V

V_DD= 5 V, V_SS= -5 V

V_DD= 12 V, V_SS= 0 V

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

55

50

45

40

35

30

25

20

-20 -16 -12

-8

-4

0

4

8

12

16

20

0

5

10

15

20

25

30

35

40 44

V_S- Source Voltage (V)

Logic Voltage (V)

图6-14. Charge Injection vs Source Voltage –Dual Supplies

图6-13. Supply Current vs Logic Voltage

125

100

75

250

V_DD= 5 V, V_SS= -5 V

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

V_DD= 5 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 20 V, V_SS= 0 V

210

170

V_DD= 36 V, V_SS= 0 V

130

90

50

25

50

0

10

-25

-50

-75

-100

-30

-70

-110

-150

-20 -16 -12

-8

-4

0

4

8

12

16

20

0

4

8

12

16

20

24

28

32

36

V_D- DrainVoltage (V)

V_S- Source Voltage (V)

图6-15. Charge Injection vs Drain Voltage –Dual Supplies

图6-16. Charge Injection vs Source Voltage –Single Supplies

180

160

V_DD= 5 V, V_SS= 0 V

T_OFF

V_DD= 12 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 20 V, V_SS= 0 V

T_ON

140

150

100

60

140

130

120

110

100

90

V_DD= 36 V, V_SS= 0 V

20

-20

-60

-100

0

4

8

12

16

20

24

28

32

36

-40

-15

10

35

60

85

110 125

V_D- Drain Voltage (V)

Temperature (C)

V_DD= 15 V, V_SS= -15 V

图6-18. T_ONand T_OFFvs Temperature

图6-17. Charge Injection vs Drain Voltage –Single Supplies

English Data Sheet: SCDS443

16

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6.14 Typical Characteristics (continued)

at T_A= 25°C

150

0

-20

T_OFF

T_ON

145

140

135

130

125

120

115

110

-40

-60

-80

-100

-120

-140

-40

-15

10

35

60

85

110 125

100

1k

10k

100k

1M

10M

100M

Temperature (C)

Frequency(Hz)

V_DD= 44 V, V_SS= 0 V

图6-19. T_ONand T_OFFvs Temperature

图6-20. Off-Isolation vs Frequency

0.01

0.007

0.005

0.01

0.007

0.005

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

V_DD= 12 V, V_SS= 0 V

V_DD= 36 V, V_SS= 0 V

0.003

0.002

0.003

0.002

0.001

0.0007

0.0005

0.001

0.0007

0.0005

0.0003

0.0002

0.0003

0.0002

0.0001

20

100

1k

10k 20k

20

100

1k

10k 20k

Frequency (Hz)

图6-21. THD+N vs Frequency (Dual Supplies)

图6-22. THD+N vs Frequency (Single Supplies)

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

10k

100k

1M

10M

100M

Frequency(Hz)

V_DD= +15 V, V_SS= -15 V

V_DD= 15 V, V_SS= -15 V

图6-24. ACPSRR vs Frequency

图6-23. On Response vs Frequency

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6.14 Typical Characteristics (continued)

at T_A= 25°C

320

280

240

200

160

120

80

C_DOFF

C_ON

C_SOFF

C_DOFF

C_ON

C_SOFF

280

240

200

160

120

80

40

-15

-10

-5

0

5

10

15

0

2

4

6

8

10

12

V_Sor V_D- Source or Drain Voltage (V)

V_DD= +15 V, V_SS= -15 V

V_DD= 12 V, V_SS= 0 V

图6-25. Capacitance vs Source Voltage or Drain Voltage

图6-26. Capacitance vs Source Voltage or Drain Voltage

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7 Parameter Measurement Information

7.1 On-Resistance

The On-Resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the

device. The On-Resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote On-

Resistance. 图 7-1 shows the measurement setup used to measure R_ON. Voltage (V) and current (I_SD) are

measured using this setup, and R_ONis computed with R_ON= V / I_SD

.

V

I_SD

S

D

V_S

图7-1. On-Resistance Measurement Setup

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

1. Source Off-Leakage current.

2. Drain Off-Leakage current.

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

图7-2 shows the setup used to measure both Off-Leakage currents.

.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

S

D

A

GND

V_S

V_D

I_D(OFF)

I_S(OFF)

图7-2. Off-Leakage Measurement Setup

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7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

.

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

.

Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

.

V_DD

V_SS

V_DD

V_SS

I_{s (ON)}

I_{D (ON)}

S

D

N.C.

A

N.C.

V_S

V_D

GND

I_S(ON)

I_D(ON)

图7-3. On-Leakage Measurement Setup

7.4 t_ONand t_OFFTime

Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen

past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4

shows the setup used to measure turn-on time, denoted by the symbol t_ON

.

Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen

past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-4

shows the setup used to measure turn-off time, denoted by the symbol t_OFF

.

V_DD

V_SS

0.1 µF

3 V

V_DD

V_SS

t_r< 20 ns

t_f< 20 ns

50%

V_SEL

0 V

V_S

Output

S

D

t_ON

t_OFF

R_L

C_L

90%

SEL

Output

0 V

10%

GND

V_SEL

图7-4. Turn-On and Turn-Off Time Measurement Setup

English Data Sheet: SCDS443

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7.5 t_{ON (VDD)}Time

The t_{ON (VDD)}time is defined as the time taken by the output of the device to rise to 90% after the supply has

risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in

the system. 图7-5 shows the setup used to measure turn on time, denoted by the symbol t_{ON (VDD)}

.

V_SS

0.1 µF

V_DD

Supply

V_DD

V_SS

t_r= 10 µs

4.5 V

Ramp

Output

V_S

S

D

0 V

t_ON

R_L

C_L

90%

SEL

Output

0 V

3 V

GND

图7-5. t_{ON (VDD)}Time Measurement Setup

7.6 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal

has risen or fallen past the 50% threshold. 图 7-6 and 方程式 1 shows the setup used to measure propagation

delay, denoted by the symbol t_PD

.

V_DD

V_SS

0.1 µF

250 mV

Input

V_DD

V_SS

50%

t_r< 40 ps

t_f< 40 ps

(V_S)

0 V

50 Ω

Output

D

S

V_S

t_PD

1

t_{PD 2}

R_L

C_L

Output

0 V

50%

GND

图7-6. Propagation Delay Measurement Setup

t

= max t 1, t 2

PD

(1)

Prop Delay

PD

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7.7 Charge Injection

The TMUX720x devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS

and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the

gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,

and is denoted by the symbol Q_C. 图 7-7 shows the setup used to measure charge injection from source (Sx) to

drain (Dx).

V_DD

V_SS

0.1 µF

3 V

V_SEL

V_DD

V_SS

t_r< 20 ns

t_f< 20 ns

S

Output

D

0 V

V_S

C_L

Output

V_D

SEL

V_OUT

Q_INJ= C_L×

V_OUT

V_SEL

GND

图7-7. Charge-Injection Measurement Setup

7.8 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the

source pin (Sx) of an off-channel. The characteristic impedance, Z₀, for the measurement is 50 Ω. 图7-8 and 方

程式2 shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S1

D

50

V_OUT

V_SIG

50

GND

图7-8. Off Isolation Measurement Setup

V

OUT

Off − Isolation = 20 × Log

(2)

V

S

English Data Sheet: SCDS443

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7.9 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The

characteristic impedance, Z₀, for the measurement is 50 Ω. 图 7-9 and 方程式 3 shows the setup used to

measure bandwidth.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S

D

50

V_OUT

V_SIG

50

S2

GND

图7-9. Bandwidth Measurement Setup

V

OUT

Bandwidtℎ = 20 × Log

(3)

V

S

7.10 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the

mux output. The On-Resistance of the device varies with the amplitude of the input signal and results in

distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is

denoted as THD + N.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Audio Precision

S

D

40 Ω

V_OUT

V_S

R_L

GND

图7-10. THD + N Measurement Setup

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7.11 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage

pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave

of 100 mV_PP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the

AC PSRR.

V_DD

Network Analyzer

V_SS

DC Bias

Injector

With and Without

Capacitor

50 Ω

0.1 µF

V_DD

V_SS

620 mV_PP

V_IN

S

V_BIAS

50 Ω

V_OUT

D

R_L

GND

C_L

图7-11. AC PSRR Measurement Setup

V

OUT

PSRR = 20 × Log

(4)

V

IN

8 Detailed Description

8.1 Overview

The TMUX720x are 1:1, 1-channel switches. The switch is turned on or turned off based on the state of the

select pin.

8.2 Functional Block Diagram

V_DD

V_SS

V_DD

V_SS

SW

D

S

SEL

TMUX7201

(SELx = Logic 1)

TMUX7202

(SELx = Logic 1)

English Data Sheet: SCDS443

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8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX720x conducts equally well from source (S) to drain (D) or from drain (D) to source (S). The switch

has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX720x ranges from V_SSto V_DD

.

8.3.3 1.8 V Logic Compatible Inputs

The TMUX720x has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the

device to interface with processors that have lower logic I/O rails and eliminates the need for an external

translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations, refer to

Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Integrated Pull-Down Resistor on Logic Pins

The TMUX7201 and TMUX7202 have internal weak Pull-Down resistors to GND to ensure the logic pins are not

left floating. The value of this Pull-Down resistor is approximately 4 MΩ, but is clamped to about 1 µA at higher

voltages. This feature integrates an external component and reduces system size and cost.

8.3.5 Fail-Safe Logic

The TMUX720x supports Fail-Safe Logic on the control input pins (SEL) allowing for operation up to 44 V above

ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be applied

before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity

by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the logic input pins of the TMUX720x to be ramped to +44 V while V_DDand V_SS= 0 V. The logic

control inputs are protected against positive faults of up to +44 V in powered-off condition, but do not offer

protection against negative overvoltage conditions.

8.3.6 Latch-Up Immune

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX720x family of devices are constructed on silicon-on-insulator (SOI) based process where an oxide

layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures

from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events

due to overvoltage or current injections. The Latch-Up immunity feature allows the TMUX720x family of switches

and multiplexers to be used in harsh environments.

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8.3.7 Ultra-Low Charge Injection

图 8-1 shows how the TMUX720x devices have a transmission gate topology. Any mismatch in the stray

capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is

opened or closed.

OFF ON

C_GDN

C_GSN

D

S

C_GSP

C_GDP

OFF ON

图8-1. Transmission Gate Topology

The TMUX720x contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce

charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (S). By

design, the excess charge from the switch transition will be pushed into the compensation capacitor on the

Source (S) instead of the Drain (D). As a general rule, Cp should be 20x larger than the equivalent load

capacitance on the Drain (D). 图 8-2 shows charge injection variation with different compensation capacitors on

the Source side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a 100 pF load

capacitance.

图8-2. Charge Injection Compensation

English Data Sheet: SCDS443

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8.4 Device Functional Modes

When the SEL pin of the TMUX720x is pulled high, the switches will close. When the SEL pin is pulled low, the

switches will open. The control pins can be as high as 44 V.

The TMUX720x can operate without any external components except for the supply decoupling capacitors. The

SEL pin has an internal Pull-Down resistor of 4 MΩ. If unused, then the SEL pin must be tied to GND so the

device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs.

8.5 Truth Tables

表8-1 provides the truth tables for the TMUX720x.

表8-1. TMUX720x Truth Table

Selected Source Connected Selected Source Connected

SEL

To Drain (D) –TMUX7201

To Drain (D) –TMUX7202

0

1

All sources are off (HI-Z)

S

All sources are off (HI-Z)

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

TMUX720x is part of the precision switches and multiplexers family of devices. TMUX720x offers low RON, low

on and off leakage currents and Ultra-Low charge injection performance. These properties make TMUX720x

ideal for implementing high precision industrial systems requiring selection of one of two inputs or outputs.

9.2 Typical Applications

9.2.1 TIA Feedback Gain Switch

One application of the TMUX720x is to configure the feedback on a discrete transimpedance amplifier (TIA)

implementation. Often, TIAs are used in applications such as photodiode inputs, which then feeds into an ADC

or MCU/processor. Depending on the expected strength of the photodiode input, and the needed accuracy,

multiple gain levels are needed. A switch like the TMUX720x allows for different gain values to be selected,

changing the level of amplifications. This solution can be scaled, but as much as needed for multiple gain

options.

图9-1 shows the TMUX720x configured with a precision op amp to enable multiple gains.

Processor

V_SS

V_DD

0.1 µF

1.8 V Logic I/O

0.1 µF

SEL

Digital Processing

R_{F_S}

R_F

V_DD

R_IN

-

Gain / Filter

Network

TIA

ADC

I_PD

+

V_SS

图9-1. TIA Feedback Control

English Data Sheet: SCDS443

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9.2.1.1 Design Requirements

For this design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

PARAMETERS

Supply (V_DD

Supply (V_SS

VALUES

)

15 V

−15 V

)

MUX I/O signal range

Control logic thresholds

−15 V to 15 V (Rail-to-Rail)

1.8 V compatible (up to V_DD

)

9.2.1.2 Detailed Design Procedure

图 9-1 shows an application that demonstrates how the TMUX720x can be used to select the gain of a TIA

amplifier. Here R_Fis used to prevent any open loop configuration. For the lowest error, the R_ONof the switch

should be much smaller than R_{F_S}, as this will scale linearly with the potential error.

The TMUX720x can support 1.8 V logic signals on the control input, allowing the device to interface with low

logic controls of an FPGA or MCU. The TMUX720x can operate without any external components except for the

supply decoupling capacitors. The select pin has an internal Pull-Down resistor to prevent floating input logic. All

inputs to the switch must fall within the recommend operating conditions of the TMUX720x including signal range

and continuous current. For this design with a positive supply of 15 V on V_DDand negative supply of -15 V on

V

_SS, the signal range can be 15 V to -15 V. The maximum continuous current (I_DC) can be up to 330 mA (for

wide-range current measurement, see the Recommended Operating Conditions section).

9.2.1.3 Application Curves

The low on and off leakage currents of TMUX720x and Ultra-Low charge injection performance make this device

ideal for implementing high precision industrial systems. The TMUX720x contains specialized architecture to

reduce charge injection on the source (Sx) (for more details, see 节 8.3.7). 图 9-2 shows the plot for the charge

injection versus source voltage for the TMUX720x.

图9-2. Charge Injection vs Source Voltage

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9.3 Power Supply Recommendations

The TMUX720x operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-supply mode).

The device also performs well with asymmetrical supplies such as V_DD= 12 V and V_SS= –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails

to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the

V_DDand V_SSpins to ground. Place the bypass capacitors as close to the power supply pins of the device as

possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)

that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply

decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use

of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple

vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.

Always ensure the ground (GND) connection is established before supplies are ramped.

9.4 Layout

9.4.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. 图 9-3 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

2W

1W min.

W

图9-3. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

图9-4 shows an example of a PCB layout with the TMUX720x. Some key considerations are as follows:

• For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and

GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as

possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

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9.4.2 Layout Example

D

S

VSS

SEL

NC

GND

VDD

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

Via to ground plane

S

D

TMUX720x

NC

VSS

SEL

NC

GND

VDD

Wide (low inductance)

trace for power

C

Wide (low inductance)

trace for power

Via to ground plane

图9-4. TMUX720x Layout Example

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10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief

• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief

• Texas Instruments, Multiplexers and Signal Switches Glossary application note

• Texas Instruments, QFN/SON PCB Attachment application note

• Texas Instruments, Quad Flatpack No-Lead Logic Packages application note

• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief

• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application notes

• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit

circuit design

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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型号：	TMUX7201
厂家：	TEXAS INSTRUMENTS
描述：	具有 1.8V 逻辑电平和闩锁效应抑制的 44V、1:1 (SPST) 单通道精密开关（高电平有效）开关
文件：	总35页 (文件大小：1601K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX7201 [TI]

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