TMUX7462F [TI]
具有可调节故障阈值、1.8V 逻辑电平和闩锁效应抑制的 ±60V 故障保护、4 通道保护器;
| 型号： | TMUX7462F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可调节故障阈值、1.8V 逻辑电平和闩锁效应抑制的 ±60V 故障保护、4 通道保护器 |
| 文件： | 总46页 (文件大小：2060K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUX7462F
ZHCSNM9B –MARCH 2021 –REVISED JUNE 2023
TMUX7462F 具有可调节故障阈值、1.8V 逻辑电平和闩锁效应抑制的±60V 故障
保护、4 通道保护器
1 特性
3 说明
• 宽电源电压范围：8V 至44V 单电源
±5V 至22V 双电源
• 通道保护器，无需为每通道设置专用选择引脚
– 减少整个PCB 布线的控制逻辑信号数量
• 集成故障保护：
TMUX7462F 是一款四通道保护器，可置于信号路径的
前端，保护下游敏感元件不会因过压故障受损。4 个通
道中均有内部开关，可在发生过压故障时自动关闭，无
需外部控制。它使器件的每个通道不再需要控制信号，
可简化稳健系统级保护设计。TMUX7462F 在通电和断
电情况下均提供过压保护，适用于无法精确控制电源定
序的应用。
– 过压保护（从源极到电源或到漏极）：±85V
– 过压保护：±60V
– 断电保护：±60V
– 指示故障状态的中断标志
– 可调节过压触发阈值
如果器件电源浮动、接地或低于欠压 (UV) 阈值，开关
通道都将保持高阻抗状态（无论开关输入条件如何）。
如果任何 Sx 引脚上的信号电平超过故障电压（VFP 或
VFN）一个阈值电压 (VT)，Sx 引脚将变为高阻态，一
个输出故障标志将置于低电平，指示正常运行中的故障
情况。漏极引脚 (Dx) 将被拉至超出范围的故障电源电
压或保持悬空，具体取决于DR 控制逻辑。
• VFP：3V 至VDD，VFN：0V 至VSS
– 故障期间的可调节输出行为（钳位或开路）
• 器件构造可实现闩锁效应抑制
• 6kV 人体放电模型(HBM) ESD 等级
• 低导通电阻：8.3Ω典型值
该器件在双电源（±5V 至 ±22V）、单电源（8V 至
44V ） 或 非 对 称 电 源 供 电 时 均 能 正 常 运 行 。
TMUX7462F 具有平缓的低导通电阻，因此非常适合出
色线性度和低失真至关重要的数据采集应用。
• 平缓的导通电阻：5mΩ典型值
• 业界通用TSSOP 封装和较小的WQFN 封装
2 应用
• 工厂自动化和控制
• 可编程逻辑控制器(PLC)
• 模拟输入模块
• 半导体测试设备
• 电池测试设备
封装信息
封装(1)
封装尺寸(2)
器件型号
TMUX7462F
PW（TSSOP，16） 5 mm × 6.4 mm
RRP（WQFN，16） 4mm x 4mm
• 伺服驱动器控制模块
• 数据采集系统(DAQ)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
VDD VSS
VFP VFN
SW
SW
SW
SW
S1
S2
S3
S4
D1
D2
D3
D4
Input
Output
Fault Detection/
Switch Driver
DR
FF
GND
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS394
TMUX7462F
ZHCSNM9B –MARCH 2021 –REVISED JUNE 2023
www.ti.com.cn
Table of Contents
7.7 Fault Flag Recovery Time.........................................24
7.8 Fault Drain Enable Time........................................... 25
7.9 Inter-Channel Crosstalk............................................ 25
7.10 Bandwidth............................................................... 26
7.11 THD + Noise............................................................26
8 Detailed Description......................................................27
8.1 Overview...................................................................27
8.2 Functional Block Diagram.........................................27
8.3 Feature Description...................................................27
8.4 Device Functional Modes..........................................30
9 Application and Implementation..................................31
9.1 Application Information............................................. 31
9.2 Typical Application.................................................... 31
9.3 Power Supply Recommendations.............................33
9.4 Layout....................................................................... 33
10 Device and Documentation Support..........................35
10.1 Documentation Support.......................................... 35
10.2 接收文档更新通知................................................... 35
10.3 支持资源..................................................................35
10.4 Trademarks.............................................................35
10.5 静电放电警告.......................................................... 35
10.6 术语表..................................................................... 35
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Thermal Information....................................................5
6.4 Recommended Operating Conditions.........................5
6.5 Electrical Characteristics (Global)...............................5
6.6 ±15 V Dual Supply: Electrical Characteristics.............6
6.7 ±20 V Dual Supply: Electrical Characteristics.............8
6.8 12 V Single Supply: Electrical Characteristics.......... 10
6.9 36 V Single Supply: Electrical Characteristics.......... 12
6.10 Typical Characteristics............................................15
7 Parameter Measurement Information..........................21
7.1 On-Resistance.......................................................... 21
7.2 On-Leakage Current................................................. 21
7.3 Input and Output Leakage Current under
Overvoltage Fault........................................................22
7.4 Fault Response Time................................................23
7.5 Fault Recovery Time.................................................23
7.6 Fault Flag Response Time........................................24
Information.................................................................... 35
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2021) to Revision B (November 2022)
Page
• 将PW 封装状态从预发布 更改为正在供货 ........................................................................................................1
• 更新了封装信息 表的格式以包含封装引线..........................................................................................................1
Changes from Revision * (March 2021) to Revision A (October 2021)
Page
• 将数据表的状态从预告信息 更改为量产数据 .....................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCDS394
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ZHCSNM9B –MARCH 2021 –REVISED JUNE 2023
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5 Pin Configuration and Functions
VFN
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VFP
D2
S1
S2
S1
VSS
GND
S4
1
2
3
4
12
11
10
9
S2
VSS
GND
S4
VDD
FF
VDD
FF
Thermal
Pad
S3
S3
D4
D3
DR
NC
Not to scale
Not to scale
图5-1. PW Package, 16-Pin TSSOP (Top View)
图5-2. RRP Package, 16-Pin WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
TSSOP
WQFN
Drain pin 1 can be an input or output. The drain pin is not overvoltage protected and shall remain within the
recommended operating range.
D1
2
15
10
7
16
I/O
I/O
I/O
I/O
Drain pin 2 can be an input or output. The drain pin is not overvoltage protected and shall remain within the
recommended operating range.
D2
D3
D4
13
8
Drain pin 3 can be an input or output. The drain pin is not overvoltage protected and shall remain within the
recommended operating range.
Drain pin 4 can be an input or output. The drain pin is not overvoltage protected and shall remain within the
recommended operating range.
5
Drain Response (DR) input. Tying the DR pin to GND enables the drain to be pulled to VFP or VFN through a
40 kΩresistor during an overvoltage fault event. The drain pin becomes open circuit when the DR pin is a
logic high or left floating.
DR
FF
8
6
I
General fault flag. This pin is an open drain output and is asserted low when overvoltage condition is
detected on any of the source (Sx) pins. Connect this pin to an external supply (1.8 V to 5.5 V) through a 1
kΩpull-up resistor.
12
10
O
P
GND
N.C.
S1
5
9
3
7
Ground (0 V) reference.
No internal connection
—
3
1
I/O
I/O
I/O
I/O
Overvoltage protected source pin 1 can be an input or output.
Overvoltage protected source pin 2 can be an input or output.
Overvoltage protected source pin 3 can be an input or output.
Overvoltage protected source pin 4 can be an input or output.
S2
14
11
6
12
9
S3
S4
4
Positive power supply. This pin is the most positive power-supply potential. Connect a decoupling capacitor
ranging from 0.1 µF to 10 µF between VDD and GND for reliable operation.
VDD
13
16
11
14
P
P
Positive fault voltage supply that determines the overvoltage protection triggering threshold on the positive
side. Connect to VDD if the triggering threshold is the same as the device's positive supply. Connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VFP and GND for reliable operation.
VFP
Negative fault voltage supply that determines the overvoltage protection triggering threshold on the negative
side. Connect to VSS if the triggering threshold is the same as the device's negative supply. Connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VFN and GND for reliable operation.
VFN
1
15
2
P
Negative power supply. This pin is the most negative power-supply potential. This pin can be connected to
ground in single-supply applications. Connect a decoupling capacitor ranging from 0.1 µF to 10 µF between
VSS and GND for reliable operation.
VSS
4
P
The thermal pad is not connected internally. No requirement to solder this pad. For best performance it is
recommended that the pad be tied to GND or VSS.
Thermal Pad
—
(1) I = input, O = output, I/O = input and output, P = power.
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English Data Sheet: SCDS394
TMUX7462F
ZHCSNM9B –MARCH 2021 –REVISED JUNE 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VDD to VSS
48
48
VDD to GND
VSS to GND
VFP to GND
VFN to GND
VS to GND
VS to VDD
VS to VSS
VD
V
Supply voltage
–0.3
–48
0.3
V
VDD + 0.3
0.3
V
–0.3
Fault clamping voltage
V
VSS –0.3
–65
Source input pin (Sx) voltage to GND
Source input pin (Sx) voltage to VDD or VD
Source input pin (Sx) voltage to VSS or VD
Drain pin (Dx) voltage
65
V
V
–90
90
V
VFP+0.7
V
V
FN–0.7
VDR
Logic input pin (DR) voltage(2)
Logic output pin (FF) voltage(2)
Logic input pin (DR) current(2)
Logic output pin (FF) current(2)
Source or drain continuous current (Sx or Dx)
Storage temperature
48
V
GND –0.7
GND –0.7
–30
VFF
6
V
IDR
30
mA
mA
mA
°C
°C
°C
mW
IFF
10
IDC ± 10 %(3)
150
–10
IS or ID (CONT)
Tstg
IDC ± 10 %(3)
–65
TA
Ambient temperature
150
–55
TJ
Junction temperature
150
(4)
Ptot
Total power dissipation (QFN)
1600
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Stresses have to be kept at or below both voltage and current ratings at all time.
(3) Refer to Recommended Operating Conditions for IDC ratings.
(4) For QFN package: Ptot derates linearly above TA = 70°C by 23.5 mW/°C
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±6000
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins(2)
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCDS394
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6.3 Thermal Information
TMUX7462F
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
100.4
31.3
RRP (WQFN)
16 PINS
42.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
28.5
46.4
17.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.7
0.3
ΨJT
45.8
17.9
ΨJB
RθJC(bot)
N/A
4.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX UNIT
(1)
Power supply voltage differential
Positive power supply voltage
44
V
DD –VSS
VDD
5
44
V
VDD
VFP
Positive fault clamping voltage
3
VFN
Negative fault clamping voltage
VSS
VFN
–60
–85
0
VFP
60
VS
Source pin (Sx) voltage (non-fault condition)
Source pin (Sx) voltage to GND (fault condition)
Source pin (Sx) voltage to VDD or VD (fault condition)
Source pin (Sx) voltage to VSS or VD (fault condition)
Drain pin (Dx) voltage
VS to GND
(2)
V
VS to VDD
VS to VSS
VD
(2)
85
VFN
GND
GND
–40
VFP
VDR
Logic input pin (DR) voltage
44
V
5.5
(3)
VFF
Logic output pin (FF) voltage
TA
Ambient temperature
125
150
°C
TA = 25°C
TA = 85°C
TA = 125°C
IDC
Continuous current through switch, WQFN package
100 mA
60
(1) VDD and VSS can be any value as long as 8 V ≤(VDD –VSS) ≤44 V, and the minimum VDD is met.
(2) Source pin voltage (Sx) under a fault condition may not exceed 85 V from supply pins (VDD and VSS.) or drain pins (D, Dx).
(3) Logic output pin (FF) is an open drain output and should be pulled up to a voltage within the max ratings
6.5 Electrical Characteristics (Global)
at TA = 25°C (unless otherwise noted)
Typical at VDD = 15 V, VSS = –15 V, GND = 0 V (unless otherwise noted)
PARAMETER
ANALOG SWITCH
VT Threshold voltage for fault detector
LOGIC INPUT/ OUTPUT
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
0.7
V
VIH
High-level input voltage
DR pin
DR pin
1.3
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
VIL
Low-level input voltage
High-level input current
Low-level input current
Low-level output voltage
0.8
3
V
µA
µA
V
IIH
VDR = logic high
VDR = logic low
FF pin, IO = 5 mA
0.4
IIL
–1 –0.65
VOL(FLAG)
0.35
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English Data Sheet: SCDS394
TMUX7462F
ZHCSNM9B –MARCH 2021 –REVISED JUNE 2023
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MAX UNIT
6.5 Electrical Characteristics (Global) (continued)
at TA = 25°C (unless otherwise noted)
Typical at VDD = 15 V, VSS = –15 V, GND = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
POWER SUPPLY
Rising edge, single supply
5.1
5
5.8
5.7
6.4
6.3
V
V
–40°C to +125°C
–40°C to +125°C
Undervoltage lockout (UVLO)
threshold voltage (VDD –VSS
VUVLO
)
Falling edge, single supply
Single supply
VDD Undervoltage lockout
(UVLO) hysteresis
VHYS
0.2
40
V
–40°C to +125°C
Drain resistance to fault supply during overvoltage protection
when enabled by DR pin
RD(OVP)
25°C
kΩ
6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
10.7
VS = –10 V to +10 V
ID = –10 mA
13.5
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
16
0.05
0.45
On-resistance mismatch between VS = –10 V to +10 V
0.5
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
ID = –10 mA
0.6
0.4
0.005
VS = –10 V to +10 V
ID = –10 mA
0.4
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
0.4
RON_DRIFT
0.04
0.1
VS = 0 V, IS = –10 mA
Ω/°C
0.7
–0.7
–2
Switch state is on,
VDD = 16.5 V, VSS = –16.5 V,
VS = VD = ±10 V
IS(ON)
,
Channel on leakage current (1)
2
nA
–40°C to +85°C
–40°C to +125°C
ID(ON)
15
–15
FAULT CONDITION
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V
Input leakage current
during overvoltage
IS(FA)
±110
±135
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN= floating,
IS(FA) Floating
±140
±0.1
µA
nA
–40°C to +125°C
25°C
20
30
60
30
50
90
–20
–30
–60
–30
–50
–90
VS = ± 60 V, GND = 0 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V, –40°C to +85°C
VDR = 5 V or floating
Output leakage current
during overvoltage
ID(FA)
–40°C to +125°C
25°C
±0.01
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
ID(FA) Grounded
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
±0.6
±1.2
±2.2
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCDS394
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6.6 ±15 V Dual Supply: Electrical Characteristics (continued)
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
100
350
VFP = 10 V, VFN = –10 V,
RL = 300 Ω, CL= 12 pF
380
400
tRESPONSE
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
1600
4500
4800
4800
VFP = 10 V, VFN = –10 V,
RL = 300 Ω, CL= 12 pF
tRECOVERY
–40°C to +85°C
–40°C to +125°C
VFP = 10 V, VFN = –10 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
25°C
25°C
25°C
25°C
25°C
25°C
25°C
250
ns
µs
VFP = 10 V, VFN = –10 V,
VPU = 5 V, RPU = 1 kΩ, CL= 15 pF
1.2
2.7
VFP = 10 V, VFN = –10 V,
VPU = 5 V, CL= 12 pF
tRESPONSE(DR)
Fault output response time
Intra-channel crosstalk
µs
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
dB
–100
650
–3 dB bandwidth (WQFN
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
MHz
MHz
dB
–3 dB bandwidth (TSSOP
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
580
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
Insertion loss
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 15 VPP, VBIAS = 0 V,
f = 20 Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
25°C
0.0006
14
%
CS(ON)
,
Input/Output on-capacitance
f = 1 MHz, VS = 0 V
pF
CD(ON)
POWER SUPPLY
25°C
0.32
0.26
0.5
0.5
0.6
0.4
0.4
0.5
VDD = VFP = 16.5 V,
VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
IDD
VDD supply current
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 16.5 V,
VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
ISS
–40°C to +85°C
–40°C to +125°C
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
IGND
GND current
25°C
25°C
25°C
0.06
10
mA
µA
µA
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
IFP
VFP supply current
VFN supply current
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
IFN
10
25°C
0.27
0.5
0.5
0.6
0.3
0.3
0.4
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
VSS supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.2
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
ISS(FA)
–40°C to +85°C
–40°C to +125°C
25°C
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
0.15
10
mA
µA
µA
VS = ± 60 V,
VDD = VFP = 16.5 V, VSS = VFN = –16.5 V,
VDR = 0 V, 5 V, or VDD
VFP supply current under fault
VFN supply current under fault
25°C
25°C
10
(1) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.7 ±20 V Dual Supply: Electrical Characteristics
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
10.5
VS = –15 V to +15 V
ID = –10 mA
14
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
17
0.05
0.35
On-resistance mismatch between VS = –15 V to +15 V
0.5
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
channels
ID = –10 mA
0.5
0.4
0.006
VS = –15 V to +15 V
ID = –10 mA
0.5
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
0.5
RON_DRIFT
0.04
0.1
VS = 0 V, IS = –10 mA
Ω/°C
0.7
–0.7
–2
Switch state is on,
VDD = 22 V, VSS = –22 V
VS = VD = ±15 V
IS(ON)
,
Channel on leakage current (1)
2
nA
–40°C to +85°C
–40°C to +125°C
ID(ON)
15
–15
FAULT CONDITION
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V
Input leakage current
during overvoltage
IS(FA)
±95
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0V,
VDD = VSS = VFP = VFN = 0 V
IS(FA) Grounded
±135
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0V,
VDD = VSS = VFP = VFN = floating
IS(FA) Floating
±140
±10
µA
–40°C to +125°C
25°C
50
70
nA
nA
nA
nA
nA
nA
µA
µA
µA
–50
–70
VS = ± 60 V, GND = 0 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 5 V or floating
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
90
–90
±500
700
700
700
–700
–700
–700
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
ID(FA) Grounded
–40°C to +85°C
–40°C to +125°C
25°C
±0.6
±1.3
±2.3
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
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6.7 ±20 V Dual Supply: Electrical Characteristics (continued)
VDD = +20 V ± 10%, VSS = –20 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +20 V, VSS = –20 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
150
400
VFP = 10 V, VFN = –10 V,
RL = 300 Ω, CL= 12 pF
430
450
tRESPONSE
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
1100
4500
4900
4900
VFP = 10 V, VFN = –10 V,
RL = 300 Ω, CL= 12 pF
tRECOVERY
–40°C to +85°C
–40°C to +125°C
VFP = 10 V, VFN = –10 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
220
ns
µs
–40°C to +125°C
VFP = 10 V, VFN = –10 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
1.1
2.7
–40°C to +125°C
VFP = 10 V, VFN = –10 V, VPU = 5 V, CL=
12 pF
tRESPONSE(DR)
Fault output response time
Intra-channel crosstalk
µs
–40°C to +125°C
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
XTALK
25°C
25°C
25°C
25°C
dB
–100
650
–3 dB bandwidth (WQFN
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
MHz
MHz
dB
–3 dB bandwidth (TSSOP
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V
BW
590
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 0 V, f = 1 MHz
ILOSS
Insertion loss
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 20 VPP, VBIAS = 0 V,
f = 20 Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
25°C
0.0006
14
%
CS(ON)
,
Input/Output on-capacitance
f = 1 MHz, VS = 0 V
pF
CD(ON)
POWER SUPPLY
25°C
0.32
0.26
0.5
0.5
0.6
0.4
0.4
0.5
VDD = VFP = 22 V,
VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
IDD
VDD supply current
VSS supply current
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
VDD = VFP = 22 V,
VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
ISS
–40°C to +85°C
–40°C to +125°C
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
IGND
GND current
25°C
25°C
25°C
0.07
10
mA
µA
µA
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
IFP
VFP supply current
VFN supply current
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
IFN
10
25°C
0.27
0.5
0.5
0.6
0.3
0.3
0.4
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
VSS supply current under fault
–40°C to +85°C
–40°C to +125°C
25°C
mA
mA
0.2
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
ISS(FA)
–40°C to +85°C
–40°C to +125°C
25°C
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
0.15
10
mA
µA
µA
VS = ± 60 V,
VDD = VFP = 22 V, VSS = VFN = –22 V,
VDR = 0 V, 5 V, or VDD
VFP supply current under fault
VFN supply current under fault
25°C
25°C
10
(1) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.8 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
VS = 0 V to 7.8 V,
IS = –10 mA
25°C
8.3
11
Ω
RON
On-resistance
15
18
VS = 0 V to 7.8 V, IS = –10 mA
VS = 0 V to 7.8 V, IS = –10 mA
–40°C to +85°C
–40°C to +125°C
25°C
Ω
Ω
0.05
0.05
0.5
0.6
0.7
0.4
0.5
0.5
VS = 0 V to 7.8 V,
IS = –10 mA
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
VS = 0 V to 7.8 V,
IS = –10 mA
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
RON_DRIFT
0.04
0.1
VS = 6 V, IS = –10 mA
Ω/°C
nA
0.7
2
–0.7
–2
Switch state is on,
VDD = 13.2 V, VSS = 0 V,
VS = VD = 1 V/ 10 V,
IS(ON)
ID(ON)
,
Output on leakage current(1)
–40°C to +85°C
–40°C to +125°C
14
–14
FAULT CONDITION
Input leakage current
during overvoltage
VS = ± 60 V, GND = 0 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
IS(FA)
±145
±135
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
IS(FA) Grounded
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
IS(FA) Floating
±140
±2
µA
nA
–40°C to +125°C
25°C
20
30
50
30
50
90
–20
–30
–50
–30
–50
–90
VS = ± 60 V, GND = 0V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VDR = 5 V or floating
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
±10
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
ID(FA) Grounded
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
±0.6
±1.3
±2.3
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
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6.8 12 V Single Supply: Electrical Characteristics (continued)
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
500
600
VFP = 8 V, VFN = 0 V,
RL = 300 Ω, CL= 12 pF
650
700
tRESPONSE
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
850
2400
2900
2900
VFP = 8 V, VFN = 0 V,
RL = 300 Ω, CL= 12 pF
tRECOVERY
–40°C to +85°C
–40°C to +125°C
VFP = 8 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
110
0.8
ns
µs
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
25°C
VFP = 8 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
VFP = 8 V, VFN = 0 V, RL = 1 kΩ, CL= 12
pF
tRESPONSE(DR)
Fault output response time
Inter-channel crosstalk
3
µs
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V, f = 1 MHz
XTALK
dB
–100
620
–3 dB bandwidth (WQFN
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V
BW
25°C
MHz
MHz
dB
–3 dB bandwidth (TSSOP
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V
BW
25°C
560
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 6 VPP, VBIAS = 6 V,
f = 20 Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
25°C
0.0007
16
%
CS(ON), CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 6 V
pF
POWER SUPPLY
25°C
0.3
0.5
0.5
0.6
mA
mA
mA
VDD = VFP = 13.2 V,
VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
VDD = VFP = 13.2 V,
VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IGND
GND current
25°C
25°C
25°C
0.06
10
mA
µA
µA
VDD = VFP = 13.2 V,
VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IFP
VFP supply current
VFN supply current
VDD = VFP = 13.2 V,
VSS = VFN = 0 V,
IFN
10
VDR = 0 V, 5 V, or VDD
25°C
0.32
0.5
0.5
0.6
mA
mA
mA
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
VS = ± 60 V,
IGND(FA)
IFP(FA)
IFN(FA)
GND current under fault
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
25°C
25°C
25°C
0.16
10
mA
µA
µA
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
VFP supply current under fault
VFN supply current under fault
VS = ± 60 V,
VDD = VFP = 13.2 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
10
(1) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.9 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
8.3
11
VS = 0 V to 30 V,
IS = –10 mA
14
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
17
0.05
0.06
0.5
VS = 0 V to 30 V,
IS = –10 mA
On-resistance mismatch between
channels
0.6
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
0.7
0.9
VS = 0 V to 30 V,
IS = –10 mA
1.1
RFLAT
On-resistance flatness
On-resistance drift
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
25°C
Ω
1.3
RON_DRIFT
0.04
0.2
VS = 18 V, IS = –10 mA
Ω/°C
0.7
–0.7
–2
Switch state is on,
VDD = 39.6 V, VSS = 0 V,
VS = VD = 1 V/ 30 V
IS(ON)
,
Output on leakage current(1)
2
nA
–40°C to +85°C
–40°C to +125°C
ID(ON)
15
–15
FAULT CONDITION
Input leakage current
during overvoltage
VS = 60 / –40 V, GND = 0 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V
IS(FA)
±98
µA
µA
–40°C to +125°C
–40°C to +125°C
Input leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
IS(FA) Grounded
±135
Input leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
IS(FA) Floating
±140
±2
µA
nA
–40°C to +125°C
25°C
20
30
50
30
50
90
–20
–30
–50
–30
–50
–90
VS = 60 / –40 V, GND = 0 V,
VDD = VFP = 39.2 V, VSS = VFN = 0 V,
VDR = 5 V or floating
Output leakage current
during overvoltage
ID(FA)
–40°C to +85°C
–40°C to +125°C
25°C
±10
Output leakage current
during overvoltage with
grounded supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = 0 V
ID(FA) Grounded
nA
µA
–40°C to +85°C
–40°C to +125°C
25°C
±0.6
±1.3
±2.3
Output leakage current
during overvoltage with
floating supply voltages
VS = ± 60 V, GND = 0 V,
VDD = VSS = VFP = VFN = floating
ID(FA) Floating
–40°C to +85°C
–40°C to +125°C
Copyright © 2023 Texas Instruments Incorporated
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6.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS
25°C
150
310
VFP = 18 V, VFN = 0 V,
RL = 300 Ω, CL= 12 pF
330
350
tRESPONSE
Fault response time
Fault recovery time
–40°C to +85°C
–40°C to +125°C
25°C
ns
ns
1100
2200
2700
2700
VFP = 18 V, VFN = 0 V,
RL = 300 Ω, CL= 12 pF
tRECOVERY
–40°C to +85°C
–40°C to +125°C
VFP = 18 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
tRESPONSE(FLAG) Fault flag response time
tRECOVERY(FLAG) Fault flag recovery time
110
0.8
ns
µs
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
25°C
VFP = 18 V, VFN = 0 V,
VPU = 5 V, RPU = 1 kΩ, CL= 12 pF
VFP = 8 V, VFN = 0 V,
RL = 1 kΩ, CL= 12 pF
tRESPONSE(DR)
Fault output response time
Inter-channel crosstalk
2.7
µs
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200m VRMS, VBIAS = 2 V, f = 1 MHz
XTALK
dB
–100
600
–3 dB bandwidth (WQFN
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V
BW
25°C
MHz
MHz
dB
–3 dB bandwidth (TSSOP
Package)
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V
BW
25°C
580
RS = 50 Ω, RL = 50 Ω, CL = 5 pF,
VS = 200 mVRMS, VBIAS = 2 V, f = 1 MHz
ILOSS
Insertion loss
25°C
–0.7
RS = 50 Ω, RL = 10 kΩ,
VS = 18 VPP, VBIAS = 18 V,
f = 20 Hz to 20 kHz
Total harmonic distortion plus
noise
THD+N
25°C
25°C
0.0006
17
%
CS(ON), CD(ON)
Input/Output on-capacitance
f = 1 MHz, VS = 18 V
pF
POWER SUPPLY
25°C
0.3
0.5
0.5
0.6
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
mA
VDD = VFP = 39.6 V VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
ISS
VSS supply current
GND current
25°C
25°C
25°C
25°C
0.25
0.07
10
mA
mA
µA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 5 V, or VDD
IGND
IFP
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 5 V, or VDD
VFP supply current
VFN supply current
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 5 V, or VDD
IFN
10
µA
25°C
0.32
0.5
0.5
0.6
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
IDD(FA)
VDD supply current under fault
–40°C to +85°C
–40°C to +125°C
mA
VS = 60 / –40 V,
ISS(FA)
IGND(FA)
IFP(FA)
VSS supply current under fault
GND current under fault
25°C
25°C
25°C
0.18
0.12
10
mA
mA
µA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
VS = 60 / –40 V,
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
VFP supply current under fault
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6.9 36 V Single Supply: Electrical Characteristics (continued)
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
VS = 60 / –40 V,
IFN(FA)
VFN supply current under fault
25°C
10
µA
VDD = VFP = 39.6 V, VSS = VFN = 0 V,
VDR = 0 V, 5 V, or VDD
(1) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.10 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
Dual Supply Flat Ron Region
Dual Supply Voltages
图6-2. On-Resistance vs Source or Drain Voltage
图6-1. On-Resistance vs Source or Drain Voltage
Flattest RON region for all supply voltages shown
±15 V Supply Flattest Ron Region
图6-3. On-Resistance vs Source or Drain Voltage
图6-4. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
±20 V Supply Flattest Ron Region
图6-6. On-Resistance vs Source or Drain Voltage
图6-5. On-Resistance vs Source or Drain Voltage
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6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
Single Supply Flat Ron Region
12 V VDD Flattest Ron Region
图6-7. On-Resistance vs Source or Drain Voltage
图6-8. On-Resistance vs Source or Drain Voltage
Single Supply Voltages
Single Supply Flat Ron Region
图6-9. On-Resistance vs Source or Drain Voltage
图6-10. On-Resistance vs Source or Drain Voltage
36 V VDD Flattest Ron Region
44 V VDD Flattest Ron Region
图6-11. On-Resistance vs Source or Drain Voltage
图6-12. On-Resistance vs Source or Drain Voltage
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6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
VDD = 12 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
图6-13. ION Leakage Current vs Temperature
图6-14. ION Leakage Current vs Temperature
VDD = 36 V, VSS = 0 V
VDD = +20 V, VSS = -20 V
图6-15. ION Leakage Current vs Temperature
图6-16. ION Leakage Current vs Temperature
±20 V Dual Supply
±15 V Dual Supply
图6-18. ID(FA) Overvoltage Leakage Current vs Temperature
图6-17. ID(FA) Overvoltage Leakage Current vs Temperature
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6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
VDD = 12 V Single Supply
VDD = 36 V Single Supply
图6-19. ID(FA) Overvoltage Leakage Current vs Temperature
图6-20. ID(FA) Overvoltage Leakage Current vs Temperature
±15 V Dual Supply
.
图6-21. Crosstalk vs Frequency
图6-22. Insertion Loss vs Frequency
.
.
图6-24. Threshold Voltage vs Temperature
图6-23. THD+N vs Frequency
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6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
VDD = VFP = 15 V
VDD = 15 V, VFP = 10 V
图6-25. Drain Output Response - Positive Overvoltage
图6-26. Drain Output Response - Positive Overvoltage
.
.
图6-27. Drain Output Recovery - Positive Overvoltage
图6-28. Drain Output Recovery - Negative Overvoltage
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6.10 Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
.
图6-29. Drain Output Response - Negative Overvoltage
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7 Parameter Measurement Information
7.1 On-Resistance
The TMUX7462F's on-resistance is the ohmic resistance across the source (Sx) and drain (Dx) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown in 图 7-1. ΔRON represents the difference
between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the difference
between the maximum and minimum value of on-resistance measured over the specified analog signal range.
V
VDD
VSS
8
410
=
+
5
VDD
VSS
IS
SW
Sx
Dx
VS
GND
图7-1. On-Resistance Measurement Setup
7.2 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denotes the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. 图7-2 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
A
SW
SW
S1
S1
D1
D4
D1
D4
N.C. N.C.
VS
VS
GND
GND
GND
Is (OFF)
A
ID (OFF)
A
SW
SW
S4
S4
N.C. N.C.
VS
VS
GND
GND
GND
IS(ON)
ID(ON)
图7-2. On-Leakage Measurement Setup
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7.3 Input and Output Leakage Current under Overvoltage Fault
If any of the source pin voltage goes above the fault supplies (VFP or VFN) by one threshold voltage (VT), the
TMUX7462F's overvoltage protection feature is triggered to turn off the switch under fault, keeping the fault
channel in the high-impedance state. IS(FA) and ID(FA) denotes the input and output leakage current under
overvoltage fault conditions, respectively. The supply (or supplies) can either be in normal operating condition
(图7-3) or abnormal operating condition (图7-4) when the overvoltage fault occurs. The supply (or supplies) can
either be unpowered (VDD= VSS = VFN = VFP = 0 V), floating (VDD= VSS = VFN = VFP = No Connection), or at any
level that is below the undervoltage (UV) threshold during abnormal operating conditions.
VDD VSS
VFP VFN
Is (FA)
A
ID (FA)
A
VD
SW
S1
D1
VS
GND
ID (FA)
GND
Is (FA)
A
SW
D4
S4
A
VD
VS
GND
GND
GND
IS(FA) / ID(FA)
( |VS| > |VFP + VT| or |VFN - VT| , DR = Floating or VDD
)
图7-3. Measurement Setup for Input and Output Leakage Current Under Overvoltage Fault with Normal
Supplies
N.C.
GND
VDD VSS
VFP VFN
VDD VSS
SW
VFP VFN
D1
Is (FA)
A
Is (FA)
A
ID (FA)
A
ID (FA)
A
SW
SW
S1
S4
S1
S4
D1
D4
RL
RL
VS
VS
GND
GND
GND
GND
GND
GND
Is (FA)
A
ID (FA)
A
Is (FA)
A
ID (FA)
A
SW
D4
RL
RL
VS
VS
GND
GND
GND
GND
Unpowered
(VDD = VSS = VFN = VFP = 0 V)
Floating
(VDD = VSS = VFN = VFP = N.C.)
图7-4. Measurement Setup for Input and Output Leakage Current Under Overvoltage Fault with
Unpowered or Floating Supplies
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7.4 Fault Response Time
Fault response time (tRESPONSE) measures the delay between the source voltage exceeding the fault supply
voltage (VFP or VFN) by 0.5V and the drain voltage failing to 90% of the fault supply voltage exceeded. 图 7-5
shows the setup used to measure tRESPONSE
.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
Max positive fault
0 V
VDD
VFN
VFP + 0.5 V
60V/µs
ramp
60V/µs
ramp
VS
VS
0.1 µF
GND
0.1 µF
VFN - 0.5 V
0 V
VDD VSS
VFP VFN
Max negative fault
GND
tRESPONSE (FP)
VFP
tRESPONSE (FN)
SW
0 V
Sx
Dx
Output
Output × 90%
Output
Output
VS
Output × 90%
RL
CL
VFN
tRESPONSE = max ( tRESPONSE(FP), tRESPONSE(FN)
All other source &
drain pins
0 V
GND
GND
GND
)
GND
GND
图7-5. Fault Response Time Measurement Setup
7.5 Fault Recovery Time
Fault recovery time (tRECOVERY) measures the delay between the source voltage falling from overvoltage
condition to below fault supply voltage (VFP or VFN) plus 0.5 V and the drain voltage rising from 0V to 50% of the
fault supply voltage exceeded. 图7-6 shows the setup used to measure tRECOVERY
.
VSS
VFP
0.1 µF
0.1 µF
GND
VDD
VFN
0 V
GND
VFN + 2 V
VFP + 0.5 V
VFN - 0.5 V
VFP - 2 V
0.1 µF
GND
0.1 µF
VS
VS
tRECOVERY (FN)
0 V
VDD VSS
VFP VFN
0 V
tRECOVERY (FP)
GND
SW
Sx
Dx
Output
All other
source &
drain pins
VS
Output
VFN × 0.5
VFP × 0.5
RL
CL
Output
0 V
GND
GND
GND
tRECOVERY = max ( tRECOVERY(FP), tRECOVERY(FN)
)
GND
GND
图7-6. Fault Recovery Time Measurement Setup
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7.6 Fault Flag Response Time
Fault flag response time (tRESPONSE(FLAG)) measures the delay between the source voltage exceeding the fault
supply voltage (VFP or VFN) by 0.5 V and the general fault flag (FF) pin to go below 10% of its original value. 图
7-7 shows the setup used to measure tRESPONSE(FLAG)
.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0 V
0.1 µF
GND
0.1 µF
GND
VFP + 0.5 V
VDD VSS
VFP VFN
VS
VS
VFN - 0.5 V
tRESPONSE(FLAG)_FN
0 V
SW
Sx
Dx
tRESPONSE(FLAG)_FP
5 V
5 V
VS
5V
RL
CL
VFF
VFF
All other
source &
drain pins
GND
RPU
0.5 V
0.5 V
GND
GND
0 V
0 V
tRESPONSE(FLAG) = max ( tRESPONSE(FLAG)_FP, tRESPONSE(FLAG)_FN
)
FF
GND
CL_FF
GND
GND
图7-7. Fault Flag Response Time Measurement Setup
7.7 Fault Flag Recovery Time
Fault flag recovery time (tRECOVERY(FLAG)) measures the delay between the source voltage falling from the
overvoltage condition to below the fault supply voltage (VFP or VFN) plus 0.5 V and the general fault flag (FF) pin
to rise above 3 V with 5 V external pull-up. 图7-8 shows the setup used to measure tRECOVERY(FLAG)
.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0 V
0.1 µF
GND
0.1 µF
GND
VFP + 0.5 V
VFN - 0.5 V
VDD VSS
VFP VFN
VS
VS
SW
0 V
Sx
Dx
tRECOVERY(FLAG)_FN
tRECOVERY(FLAG)_FP
VS
5 V
VFF
5 V
5V
RL
CL
3 V
3 V
All other
source &
drain pins
VFF
GND
RPU
GND
GND
0 V
0 V
tRECOVERY(FLAG) = max ( tRECOVERY(FLAG)_FP, tRECOVERY(FLAG)_FN
)
FF
GND
CL_FF
GND
GND
图7-8. Fault Flag Recovery Time Measurement Setup
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7.8 Fault Drain Enable Time
tRESPONSE(DR) represents the delay between the voltage at the DR pin falling from a high to low signal and the
output of the drain pin reaching 90% of the fault supplies (VFP or VFN). tRESPONSE(DR) is a measure of how quickly
the internal pull-up engages in response to the DR pin. 图7-9 shows the setup used to measure tRESPONSE(DR)
.
VSS
VFP
0.1 µF
GND
0.1 µF
VDD
VFN
GND
3 V
3 V
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
VDR
1.5V
VDR
1.5V
SW
Sx
Dx
0 V
tRESPONSE(DR)_FP
tRESPONSE(DR)_FN
0 V
Output (VD)
VS
CL
VFP
VFP x 0.9
Output (VD)
GND
GND
All other
source &
drain pins
0 V
VFN x 0.9
DR
VFN
VDR
GND
tRESPONSE(DR) = max ( tRESPONSE(DR)_FP, tRESPONSE(DR)_FN
)
GND
GND
VS > VFP + VT (to measure tRECOVERY(DR)_FP) or
VS < VFN - VT (to measure tRECOVERY(DR)_FN
)
图7-9. Fault Drain Enable Time Measurement Setup
7.9 Inter-Channel Crosstalk
图 7-10 and 方程式 1 shows how the inter-channel crosstalk (XTALK(INTER)) is measured as the voltage at the
source pin (Sx) of an on-switch input, when a 1-VRMS signal is applied at the source pin of an on-switch input in a
different channel.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Network Analyzer
SW
SW
SX
SY
DX
DY
Other
50
RS
VOUT
Sx/ Dx
pins
50
VS
50
GND
50
图7-10. Inter-Channel Crosstalk Measurement Setup
V
OUT
Inter − cℎannel Crosstalk = 20 × Log
(1)
V
S
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7.10 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the TMUX7462F's drain pin (D or Dx). 图
7-11 and 方程式2 shows the setup used to measure bandwidth of the switch.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Network Analyzer
SW
SX
VOUT
RS
Dx
Other
Sx/ Dx
pins
VS
50
50
GND
图7-11. Bandwidth Measurement Setup
V
OUT
Bandwidtℎ = 20 × Log
(2)
V
S
7.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
multiplexer output. The on-resistance of the TMUX7462F varies with the amplitude of the input signal and results
in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is
denoted as THD+N. 图7-12 shows the setup used to measure THD+N of the devices.
VSS
VFP
0.1 µF
GND
0.1 µF
GND
VDD
VFN
0.1 µF
GND
0.1 µF
GND
VDD VSS
VFP VFN
Audio Precision
SW
SX
RS
Dx
VOUT
VS
RL
Other
Sx/ Dx
pins
GND
50Ω
图7-12. THD+N Measurement Setup
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8 Detailed Description
8.1 Overview
The TMUX7462F is a four-channel protector that can be placed in series with the signal path to protect sensitive
components downstream from overvoltage faults. The channel protector prevents overvoltages in both powered
and powered-off conditions, making it suitable for applications where correct power supply sequencing cannot be
precisely controlled. The powered-off condition includes floating power supplies, grounded power supplies, or
power supplies at any level that are below the undervoltage (UV) threshold. The internal switch is turned-on and
turned-off autonomously based on the fault situation without the need of external controls, making the device
extremely easy to implement in the system. The primary supply voltages define the on-resistance profile, while
the secondary supply voltages define the voltage level at which the overvoltage protection engages. The device
works well with dual supplies (±5 V to ±22 V), a single supply (8 V to 44 V), or asymmetric supplies (such as VDD
= 12 V, VSS = –5 V).
8.2 Functional Block Diagram
VDD VSS
VFP VFN
SW
SW
SW
SW
S1
S2
S3
S4
D1
D2
D3
D4
Input
Output
Fault Detection/
Switch Driver
DR
FF
GND
8.3 Feature Description
8.3.1 Flat ON-Resistance
The TMUX7462F are designed with a special switch architecture to produce ultra-flat on-resistance (RON) across
most of the switch input operation region. The flat RON response allows the device to be used in precision sensor
applications since the RON is controlled regardless of the signals sampled. The architecture is implemented
without a charge pump so no unwanted noise is produced from the device to affect sampling accuracy.
8.3.2 Protection Features
The TMUX7462F offers a number of protection features to enable robust system implementations.
8.3.2.1 Input Voltage Tolerance
The maximum voltage that can be applied to any source input pin is +60 V or -60 V, allowing the device to
handle typical voltage fault conditions in industrial applications. Take caution: the device has different maximum
stress ratings across different pin combinations and are defined as the following:
1. Between source pins and supply rails: 85 V
For example, if the device is powered by VDD supply of 25 V, then the maximum negative signal level on any
source pin is –60 V. If the device is powered by VDD supply of 40 V, then the maximum negative signal level
on any source pin is reduced to –45 V to maintain the 85 V maximum rating across the source pin and the
supply.
2. Between source pins and drain pin of the same channel: 85 V
For example, if the DR pin is left floating and an overvoltage voltage fault of –60 V occurs on the source pin
S1, then the maximum positive voltage signal level driven on the drain pin channel D1 is 25 V to maintain the
85 V maximum rating across the source pin and the drain pin.
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8.3.2.2 Powered-Off Protection
The source (Sx) pins of the device remain in the high impedance (Hi-Z) state, and the device performance
remains within the leakage performance specifications when the supplies of TMUX7462F are removed (VDD/ VSS
= 0 V or floating) or at a level that is below the undervoltage (UV) threshold. Powered-off protection minimizes
system design complexity by removing the need to control the system's power supply sequencing. The feature
prevents errant voltages on the input source pins from reaching the rest of the system and maintains isolation
when the system is powering up. Without powered-off protection, signal on the input source pins can back-power
the supply rails through internal ESD diodes and cause potential damage to the system.
A GND reference must always be present to for proper operation. Source and drain voltage levels of up to ±60 V
are blocked in the powered-off condition.
8.3.2.3 Fail-Safe Logic
Fail-Safe logic circuitry allows voltages on the control input pin (DR) to be applied before the supply pins. This
eliminates the need for power sequencing of the logic signals and protects the device from potential damage.
The control inputs are protected against positive faults of up to +44 V in the powered-off condition, but do not
offer protection against a negative overvoltage condition.
8.3.2.4 Overvoltage Protection and Detection
The TMUX7462F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the fault
supplies (VFP and VFN). A signal is considered overvoltage if it exceeds the fault supply voltages by the threshold
voltage (VT).
The switch automatically turns OFF and the source pin becomes high impedance so that only small leakage
currents flow through the switch when an overvoltage is detected. The drain pin (Dx) behavior can be adjusted
by controlling the drain response (DR) pin in the following ways:
1. DR pin floating or driven above VIH:
If the DR pin is driven about VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon
overvoltage fault.
2. DR driven below VIL:
If the DR pin is driven below VIL level of the pin, then the drain pin (Dx) is pulled to the supply that was
exceeded. For example, if the source voltage exceeds VFP, then the drain output is pulled to VFP. If the
source voltage exceeds VFN, then the drain output is pulled to VFN. The pull-up impedance is approximately
40 kΩ, and as a result, the drain current is limited to roughly 1 mA during a shorted load (to GND) condition.
图 8-1 shows a detailed view of the how the DR pin controls the output state of the drain pin under a fault
scenario.
VDD VSS
VFP
DR
Logic
Fault
Detection
40 kꢀ
Sx
Dx
40 kꢀ
ESD
Protection
VFN
GND
图8-1. Detailed Functional Diagram
VFP and VFN are required fault supplies that set the level at which the overvoltage protection is engaged. VFP can
be supplied from 3 V to VDD, while the VFN can be supplied from VSS to 0 V. If the fault supplies are not available
in the system, then the VFP pin must be connected to VDD, while the VFN pin must be connected to VSS. In this
case, the overvoltage protection then engages at the primary supply voltages VDD and VSS
.
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8.3.2.5 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The Latch-up condition typically requires a power cycle to eliminate the
low impedance path.
An insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming
in the TMUX7462F devices. As a result, the devices are latch-up immune under all circumstances by device
construction.
8.3.2.6 EMC Protection
The TMUX7462F is not intended for standalone electromagnetic compatibility (EMC) protection in industrial
applications. There are three common high voltage transient specifications that govern industrial high voltage
transient specifications: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5 (surge immunity). A
transient voltage suppressor (TVS), along with some low-value series current limiting resistor, are required to
prevent source input voltages from going above the rated ±60 V limits.
It is critical to ensure that the maximum working voltage is greater than the normal operating range of the input
source pins protected and any known system common-mode overvoltage that may be present due to incorrect
wiring, loss of power, or short circuit when selecting a TVS protection device. 图 8-2 shows an example of the
proper design window when selecting a TVS device.
Region 1 denotes the normal operation region of TMUX7462F, where the input source voltages stay below the
fault supplies VFP and VFN. Region 2 represents the range of possible persistent DC (or long duration AC
overvoltage fault) presented on the source input pins. Region 3 represents the margin between any known DC
overvoltage level and the absolute maximum rating of the TMUX7462F. The TVS breakdown voltage must be
selected to be less than the absolute maximum rating of the TMUX7462F, but greater than any known possible
persistent DC or long duration AC overvoltage fault to avoid triggering the TVS inadvertently. Region 4
represents the margin the system designers must impose when selecting the TVS protection device to prevent
accidental triggering the ESD cells of the TMUX7462F.
Internal ESD
Trigger Voltage
4
Device Absolute
Max Rating
TVS
Breakdown
Voltage
3
2
System
Overvoltage
Overvoltage
Protection Window
Fault Voltage
Supply VFP
0 V
1
Normal Operation
Fault Voltage
Supply VFN
2
3
4
System
Overvoltage
Overvoltage
Protection Window
TVS
Breakdown
Voltage
Device Absolute
Max Rating
Internal ESD
Trigger Voltage
图8-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device
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8.3.3 Overvoltage Fault Flags
The voltages on TMUX7462F's source input pins are continuously monitored, and the status of whether an
overvoltage condition occurs is indicated by an active low general fault flag (FF). The voltage on the FF pin
indicates if any of the source input pins are experiencing an overvoltage condition. If any source pin voltage
exceeds the fault supply voltages by a VT, the FF output is pulled-down to below VOL. The FF pin is an open-
drain output, and external pull-up resistors of 1 kΩ are recommended. The pull-up voltage can be in the range of
1.8 V to 5.5 V, depending on the controller voltage the device interfaces with.
8.3.4 Bidirectional Operation
The TMUX7462F conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
signal path has very similar characteristics in both directions; however, it is noted that the overvoltage protection
is implemented only on the source (Sx) side. The voltage on the drain is only allowed to swing between VFP and
VFN and no overvoltage protection is available on the drain side.
The primary supplies (VDD and VSS) define the on-resistance profile of the switch channel, whereas the fault
voltage supplies (VFP and VFN) define the signal range that can be passed through from source to drain of the
device. It is good practice to use voltages on VFP and VFN that are lower than VDD and VSS to take advantage of
the flat on-resistance region of the device for better input-to-output linearity. The flattest on-resistance region
extends from VSS to roughly 3 V below VDD. Once the signal is within 3 V of VDD the on-resistance will
exponentially increase and may impact desired signal transmission.
8.4 Device Functional Modes
The TMUX7462F offers two modes of operation (Normal mode and Fault mode) depending on whether any of
the input pins experience an overvoltage condition.
8.4.1 Normal Mode
In Normal mode operation, signals of up to VFP and VFN can be passed through the switch from source (Sx) to
drain (Dx) or from drain (Dx) to source (Sx). The following conditions must be satisfied for the switch to stay in
the ON condition:
• The difference between the primary supplies (VDD –VSS) must be higher or equal to 8 V.
• VFP must be between 3 V and VDD, and VFN must be between VSS and 0 V.
• The input signals on the source (Sx) or the drain (Dx) must be between VFP+ VT and VFN –VT.
8.4.2 Fault Mode
The TMUX7462F enters into the Fault mode when any of the input signals on the source (Sx) pins exceed VFP
or VFN by a threshold voltage VT. The switch input experiencing the fault automatically turns off, and the source
pin becomes high impedance with negligible amount of leakage current flowing through the switch under the
overvoltage condition. For how the drain pin (Dx) behavior under the Fault mode can be programmed, refer to 节
8.3.2.4. The general fault flag (FF) is asserted low in the Fault mode.
The overvoltage protection is provided only for the source (Sx) input pins. The drain (Dx) pin, if used as signal
input, must stay in between VFP and VFN at all time since no overvoltage protection is implemented on the drain
pin.
8.4.3 Truth Table
表 8-1 provides the truth tables for the TMUX7462F. Each switch is independently controlled by its own select
pin.
表8-1. TMUX7462F Truth Table
Dx State During Fault
DR PIN STATE
Condition
0
1
Pulled up to VFP or VFN
Open (HI-Z)
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TMUX7462F is part of the fault protected switches and multiplexers family of devices. The ability to protect
downstream components from overvoltage events up to ±60 V and latch-up immunity features makes these
switches and multiplexers suitable for harsh environments.
9.2 Typical Application
The need to monitor remote sensors is common among factory automation control systems. For example, an
analog input module or mixed module (AI, AO, DI, and DO) of a programmable logic controller (PLC) will
interface to a field transmitter to monitor various process sensors at remote locations around the factory. A
switch or multiplexer is often used to connect multiple inputs from the system and reduce the number of
downstream channels.
There are a number of fault cases that may occur that can be damaging to many of the integrated circuits. Such
fault conditions may include, but are not limited to, human error due to miswiring, component failure, wire shorts,
electromagnetic interference (EMI), transient disturbances, and more.
Field Module
PLC Anaog Input / Output Module
Fault
Protected
Mux Inputs
+15 V
TMUX7462F
+24 V
–
+
-15 V
+15 V-15 V
+10 V-10 V
VFP VFN
VSense
VOUT
VDD VSS
DAC
Wire
Fault!
Short
S1
D1
D2
D3
D4
Analog Input
Signals
DAC
S2
S3
S4
+10 V
+
-
Analog Output
Signals
High voltage
offset shift
+10 V
IN1
Fault!
-10 V
+
-
ADC
-10 V
IN2
V
Does not require logic control
pins from MCU/processor
图9-1. Typical Application
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9.2.1 Design Requirements
表9-1. Design Parameters
PARAMETER
VALUE
+15 V
Positive supply (VDD) mux
Negative supply (VSS) mux
Power board supply voltage
-15 V
24 V
Input or output signal range non-faulted
Overvoltage protection levels
Control logic thresholds
-10 V to 10 V
-60 V to 60 V
1.8 V compatible, up to 44 V
-40°C to +125°C
Temperature range
9.2.2 Detailed Design Procedure
The TMUX7462F device's normal operation is to provide fault protection for the system while minimizing the
control logic signals required to route across the PCB. The device works as a channel protector by allowing the
signals to pass when in the valid voltage range, and opening the switch if there is a fault case. A fault protected
switch can add extra robustness to the system against fault conditions while also reducing the number of
components required to interface with the physical input channels.
The application shows two channels of the TMUX7462F connected as analog outputs and two channels
connected as analog inputs to the PLC system. The analog input channels utilize the TMUX7462F to protect
down stream operational amplifiers that are operating at a lower supply voltage than the multiplexer. The
TMUX7462F only has overvoltage protection on the source pins, therefore these pins are connected to the
external system connector on the analog output channels. If there is a miswiring or wire short issue on the
connectors, the channel protector will open the switch channel to help prevent long term fault conditions from
damaging the DAC.
If there is a fault condition, the drain pin of the channels can either be pulled up to the fault supply voltage (VFP
and VFN) through a 40 kΩ resistor or be left floating depending on the state of the DR pin. This can be
configured to match the system requirements on how to handle a fault condition.
9.2.3 Application Curves
The example application utilizes adjustable fault threshold voltages of the TMUX7462F to allow for protection of
downstream components operating on lower supply voltages. 图 9-2 shows an example of positive overvoltage
fault response with a fast fault ramp rate of 60 V/us. 图9-3 shows the extremely flat on-resistance across source
voltage while operating within the fault threshold voltage levels for many supply voltage scenarios. These
features make the TMUX7462F an excellent solution for data acquisition applications that may face various fault
conditions but also require excellent linearity and low distortion.
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VDD = 15 V, VFP = 10 V
VFP = 10 V, VFN = -10 V
图9-2. Positive Overvoltage Response
图9-3. RON Flatness in Non-Fault Region
9.3 Power Supply Recommendations
The TMUX7462F operates across a wide supply range of ±5 V to ±22 V (8 V to 44 V in single-supply mode). The
device also performs well with asymmetrical supplies such as VDD = 12 V and VSS= –5 V. For improved supply
noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at the VDD and VSS pins to
ground. Always ensure the ground (GND) connection is established before supplies are ramped.
The fault supplies (VFP and VFN) provide the current required to operate the fault protection, and thus, must be
low impedance supplies. They can be derived from the primary supplies by using a resistor divider and buffer or
be an independent supply rail. The fault supplies must not exceed the primary supplies as it might cause
unexpected behavior of the switch. Use a supply decoupling capacitor ranging from 1 µF to 10 µF at the VFP and
VFN pins to ground for improved supply noise immunity.
The positive supply, VDD, must be ramped before the positive fault rail, VFP, for proper power sequencing of the
TMUX7462F. Similarly, the negative supply, VSS, must be ramped before the negative fault voltage rail, VFN
.
9.4 Layout
9.4.1 Layout Guidelines
The following images shows an example of a PCB layout with the TMUX7462F. Some key considerations are as
follows:
• Decouple the VDD and VSS pins with a 1-µF capacitor, placed as close to the pin as possible. Make sure that
the capacitor voltage rating is sufficient for the supplies.
• Multiple decoupling capacitors can be used if their is a lot of noise in the system. For example, a 0.1-µF and
1-µF can be placed on the supply pins. If multiple capacitors are used, then it is recommended to place the
lowest value capacitor closest to the supply pin.
• Keep the input lines as short as possible.
• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
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9.4.2 Layout Example
To VFN supply
C
To VFP supply
C
VFN
D1
VFP
Wide (low inductance)
trace for VSS
D2
S2
Wide (low inductance)
trace for VDD
S1
VSS
GND
S4
VDD
FF
TMUX7462F
To Pull-up resistor
S3
D3
D4
DR
N.C.
Via to ground plane
图9-4. TSSOP Layout Example
C
C
S2
VDD
FF
S1
VSS
GND
S4
C
To Pull-up resistor
S3
Via to ground plane
Via to power plane
图9-5. WQFN Layout Example
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
• Texas Instruments, Multiplexers and Signal Switches Glossary
• Texas Instruments, Protection Against Overvoltage Events, Miswiring, and Common Mode Voltages
• Texas Instruments, Improving Analog Input Modules Reliability Using Fault Protected Multiplexers
• Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX7462FPWR
TMUX7462FRRPR
ACTIVE
ACTIVE
TSSOP
WQFN
PW
16
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TM7462F
Samples
Samples
RRP
NIPDAU
TMUX
7462F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jul-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX7462FRRPR
WQFN
RRP
16
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN RRP 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TMUX7462FRRPR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RRP0016A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
A
B
PIN 1 INDEX AREA
4.1
3.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 1.95
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
2X 1.95
SYMM
17
2.6 0.1
12X 0.65
1
12
0.35
16X
PIN 1 ID
0.25
13
16
0.1
C A B
0.45
0.35
0.05
16X
4224816/A 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
SEE SOLDER MASK
DETAIL
13
16
16X (0.6)
1
12
16X (0.3)
17
SYMM
12X (0.65)
(3.8)
(1.05)
4
9
(R0.05) TYP
(
0.2) TYP
VIA
5
8
(1.05)
(3.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
SOLDER MASK DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224816/A 02/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RRP0016A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.675) TYP
13
16
16X (0.6)
1
12
16X (0.3)
(0.675) TYP
(3.8)
17
SYMM
12X (0.65)
4X ( 1.15)
9
4
(R0.05) TYP
8
5
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224816/A 02/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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