TMUXHS4412 [TI]
TMUXHS4412 4-Channel 20 Gbps Differential 2:1/1:2 Mux/Demux;
| 型号： | TMUXHS4412 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMUXHS4412 4-Channel 20 Gbps Differential 2:1/1:2 Mux/Demux |
| 文件： | 总30页 (文件大小：3980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMUXHS4412
SLASEW5 – DECEMBER 2020
TMUXHS4412 4-Channel 20 Gbps Differential 2:1/1:2 Mux/Demux
1 Features
3 Description
•
Provides bidirectional passive 2:1 MUX / 1:2
DEMUX for four differential channels
Data rate support up to 20 Gbps
Supports PCI Express 4.0 up to 16 Gbps
Also supports USB 3.2, USB 4.0, TBT 3.0, DP 2.0,
SATA, SAS, MIPI DSI/CSI, FPD-Link III, LVDS, SFI
and Ethernet Interfaces
–3-dB differential BW of 13 GHz
Excellent dynamic characteristics for PCIe 4.0
signaling
The TMUXHS4412 is a high-speed bidirectional
passive switch which can be used for both multiplexer
(mux) and demultiplexer (demux) configurations. The
TMUXHS4412 is a analog differential passive mux or
demux that works for many high-speed differential
interfaces for data rates up to 20 Gbps including PCI
Express 4.0. The device can be used for higher data
rates where electrical channel has signal integrity
margins. The TMUXHS4412 supports differential
signaling with common mode voltage range (CMV) of
up to 0 to 1.8 V and with differential amplitude up to
1800 mVpp. Adaptive CMV tracking ensures the
channel through the device remains unchanged for
the entire common mode voltage range.
•
•
•
•
•
– Insertion loss = -1.3 dB at 8 GHz
– Return loss = –22 dB at 8 GHz
– Cross-talk = -58 dB at 8 Ghz
•
•
•
•
Adaptive common mode voltage tracking
Supports common mode voltage up to 0 to 1.8 V
Single supply voltage VCC of 3.3 or 1.8 V
Ultra low active (320 μA) and standby power
consumption (0.1 μA)
Industrial temperature option with –40° to 105°C
Pin-to-pin PCIe 4.0 linear redriver option with
DS160PR421 and DS160PR412
The excellent dynamic characteristics of the
TMUXHS4412 result minimum attenuation to the
signal eye diagram with very little added jitter. The
device's silicon design is optimized for excellent
frequency response at higher frequency spectrum of
the signals. Its silicon signal traces and switch
network are matched for best intra-pair skew
performance.
•
•
•
Available in 3.5 mm x 9 mm QFN package
The TMUXHS4412 has an extended industrial
temperature range that suits many rugged
applications including industrial and high reliability use
cases.
2 Applications
•
•
•
•
•
•
•
•
•
PC and notebooks
Gaming, Home theater & entertainment and TV
Data center and enterprise computing
Medical applications
Test and measurements
Factory automation and control
Aerospace and defense
Device Information (1)
PART NUMBER
TMUXHS4412
TMUXHS4412I
PACKAGE
BODY SIZE (NOM)
3.5 mm × 9.0 mm ×
0.5-mm pitch
WQFN (42)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Electronic point of sale (EPOS)
Wireless infrastructure
PCIe Card
x16
Slot
x8
Connector-B
RXB 8-ch
4-Ch
4-Ch
x8
RX 8-ch
TMUXHS4412
4 Ch 2:1 Mux
CPU
4-Ch
4-Ch
TXB 8-ch
TMUXHS4412
4 Ch 1:2 demux
TX 8-ch
h
c
h
c
PCIe Card
-
-
4-Ch
4-Ch
8
8
XA
T
RXA
x8
Slot
Connector-A
x8
PCIe 3.0/4.0 Lane Switching
De-multiplexer
Multiplexer
Application Use Cases
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUXHS4412
SLASEW5 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 High-Speed Performance Parameters .......................6
6.7 Switching Characteristics ...........................................7
6.8 Typical Characteristics................................................8
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation..................................13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 14
8.3 Systems Examples................................................... 19
9 Power Supply Recommendations................................20
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................22
11.1 Receiving Notification of Documentation Updates..22
11.2 Support Resources................................................. 22
11.3 Trademarks............................................................. 22
11.4 Electrostatic Discharge Caution..............................22
11.5 Glossary..................................................................22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial release
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5 Pin Configuration and Functions
1
38 DA0P
38
NC
NC
1
2
2
37 DA0N
37
D0P
D0N
3
36 DB0P
36
3
4
4
35 DB0N
35
5
34 DA1P
34
VCC
GND
D1P
5
6
6
33 DA1N
33
7
7
32 DB1P
32
D1N
GND
8
31 DB1N
31
8
EP=GND
9
9
30 GND
30
DA2P
10
10
29
29
D2P
D2N
NC
11
11
28 DA2N
28
12
12
27 DB2P
27
VCC 13
13
26 DB2N
26
D3P 14
14
25 DA3P
25
15
15
24
DA3N
24
D3N
GND
16
16
23 DB3P
23
SEL 17
17
22 DB3N
22
Figure 5-1. RUA package 42-Pin WQFN Top View (not to scale)
Pin Functions
PIN
NAME
D0P
TYPE
DESCRIPTION
NO.
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Common Port (D), channel 0, high-speed positive signal
Common Port, channel 0, high-speed negative signal
Common Port, channel 1, high-speed positive signal
Common Port, channel 1, high-speed negative signal
Common Port, channel 2, high-speed positive signal
Common Port, channel 2, high-speed negative signal
Common Port, channel 3, high-speed positive signal
Common Port, channel 3, high-speed negative signal
Port A (DA), channel 0, high-speed positive signal
Port A, channel 0, high-speed negative signal
Port A, channel 1, high-speed positive signal
D0N
4
D1P
7
D1N
8
D2P
10
11
14
15
38
37
34
33
29
28
25
D2N
D3P
D3N
DA0P
DA0N
DA1P
DA1N
DA2P
DA2N
DA3P
Port A, channel 1, high-speed negative signal
Port A, channel 2, high-speed positive signal
Port A, channel 2, high-speed negative signal
Port A, channel 3, high-speed positive signal
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PIN
TYPE
DESCRIPTION
Port A, channel 3, high-speed negative signal
NAME
DA3N
NO.
24
36
35
32
31
27
26
23
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DB0P
DB0N
DB1P
DB1N
DB2P
DB2N
DB3P
DB3N
Port B (DB), channel 0, high-speed positive signal
Port B, channel 0, high-speed negative signal
Port B, channel 1, high-speed positive signal
Port B, channel 1, high-speed negative signal
Port B, channel 2, high-speed positive signal
Port B, channel 2, high-speed negative signal
Port B, channel 3, high-speed positive signal
Port B, channel 3, high-speed negative signal
6, 9, 16,
21,30, 39
GND
PD
G
I
Ground
Active-low chip enable.
H: Shutdown
18
1, 2, 12, 19,
20, 40, 41
NC
NA
NA
Leave unconnected
RSVD
42
Reserved - TI test mode. Pull-down to GND using a resistor such as 4.7 kΩ
Port select pin.
SEL
VCC
17
I
L: Common Port (D) to Port A (DA)
H: Common Port (D) to Port B (DB)
5, 13
P
3.3 or 1.8 V power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC-
Supply voltage
–0.5
4
V
ABSMA
X
VHS-
Voltage
Voltage
Differential I/O pins
Control pins
–0.5
2.4
V
ABSMA
X
VCTR-
–0.5
–65
VCC+0.4
150
V
ABSMA
X
TSTG Storage temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
VESD
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
3.0
TYP
1.8
MAX
1.98
3.6
UNIT
V
1.8 V supply voltage mode
3.3 V supply voltage mode
VCC
Supply voltage
3.3
V
VCC-
Supply voltage ramp time
0.1
100
ms
RAMP
VIH
Input high voltage
SEL, PD pins
SEL, PD pins
0.75VCC
V
V
VIL
Input low voltage
0.25VCC
1.8
VDIFF
High-speed signal pins differential voltage
0
0
Vpp
1.8 V supply voltage mode,
biased from common port (D)
0.9
1.8
V
V
VCM
High speed signal pins common mode voltage
Operating free-air/ambient temperature
3.3 V supply voltage mode,
biased from D or DA/DB ports.
0
TMUXHS4412
TMUXHS4412I
0
70
°C
°C
TA
-40
105
6.4 Thermal Information
TMUXHS4412
RUA (WQFN)
42 PINS
32.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance - High K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
21.8
14.4
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UNIT
SLASEW5 – DECEMBER 2020
TMUXHS4412
RUA (WQFN)
42 PINS
1.4
THERMAL METRIC(1)
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ψJB
14.3
RθJC(bot)
7.8
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature and supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
480
2
UNIT
PD = 0; 0 V ≤ VCM ≤ 1.8; SEL = 0 or
VCC
ICC
Device active current
320
µA
ISTDN
CON
Device shutdown current
PD = VCC
0.1
0.45
5
µA
pF
Ω
Output ON capacitance to GND
Output ON resistance
PD = 0; f = 8 Ghz
0 V ≤ VCM ≤ 1.8 V; IO = –8 mA
VIN = 3.6 V
RON
8
2
1
IIH,CTRL
IIL,CTRL
Input high current, control pins (SEL, PD)
Input low current, control pins (SEL, PD)
µA
µA
VIN = 0 V
Common mode resistance to ground on D
pins (Dx[P/N])
RCM,HS
Each pin to GND
1.0
1.4
5
MΩ
µA
VIN = 1.8 V for selected port, D and
DA pins with SEL = 0, and D and DB
pins with SEL = VCC
Input high current, high-speed pins [Dx/DAx/
DBx][P/N]
IIH,HS,SEL
VIN = 1.8 V for non-selected port, DB
with SEL = 0, and DA with SEL =
VCC
Input high current, high-speed pins [Dx/DAx/
DBx][P/N]
IIH,HS,NSEL
150
4
µA
(1)
PD = VCC; Dx[P/N] = 1.8 V, [DA/
DB]x[P/N] = 0 V and Dx[P/N] = 0 V,
[DA/DB]x[P/N] = 1.8 V
Leakage current through turned off switch
between Dx[P/N] and [DA/DB]x[P/N]
IHIZ,HS
µA
DC Impedance between Dx[P] and Dx[N]
pins
RA,p2n
PD = 0 and VCC
20
KΩ
(1) There is a 20-kΩ pull-down in non-selected port.
6.6 High-Speed Performance Parameters
PARAMETER
ƒ = 10 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
TEST CONDITION
MIN
TYP
MAX
UNIT
-0.4
-0.7
-0.8
-0.9
-1.3
-1.8
13
IL
Differential insertion loss
dB
GHz
dB
ƒ = 5 GHz
ƒ = 8 GHz
ƒ = 10 GHz
BW
RL
–3-dB bandwidth
ƒ = 10 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 8 GHz
ƒ = 10 GHz
-30
-23
-23
-22
-22
-15
Differential return loss
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PARAMETER
TEST CONDITION
ƒ = 10 MHz
MIN
TYP
-57
-27
-22
-20
-15
-12
-73
-64
-61
-61
-58
-54
MAX
UNIT
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 8 GHz
ƒ = 10 GHz
ƒ = 10 MHz
ƒ = 2.5 GHz
ƒ = 4 GHz
ƒ = 5 GHz
ƒ = 8 GHz
ƒ = 10 GHz
OIRR
Differential OFF isolation
dB
XTALK
Differential crosstalk
dB
Mode conversion - differential
to common mode
SCD11,22
SCD21,12
SDC11,22
SDC21,12
ƒ = 8 GHz
ƒ = 8 GHz
ƒ = 8 GHz
ƒ = 8 GHz
-29
-25
-29
-25
dB
dB
dB
dB
Mode conversion - differential
to common mode
Mode conversion - common
mode to differential
Mode conversion - common
mode to differential
6.7 Switching Characteristics
PARAMETER
MIN
TYP
MAX UNIT
tPD
Switch propagation delay
f = 1 Ghz
50
ps
Biased from DA/DB
side with CMV
difference is
<100mV, DA/DB
pins at 90% of final
value
tSW_ON
Switching time SEL-to-Switch ON
Switching time SEL-to-Switch OFF
130
100
ns
ns
Biased from DA/DB
side with CMV
difference is
<100mV, DA/DB
pins at 90% of final
value
tSW_OFF
Intra-pair output skew between P and N pins for
same channel
tSK_INTRA
tSK_INTER
f = 1 Ghz
f = 1 Ghz
4.0
4.0
ps
ps
Inter-pair output skew between channels
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6.8 Typical Characteristics
Figure 6-1 shows differential insertion loss on the top plot and return loss on the bottom plot of a typical
TMUXHS4412 channel. Note measurements are performed in TI evaluation board with board and equipment
parasitics calibrated out.
Differential Insertion Loss
0
-1
-2
-3
-4
-5
-6
100000000
1E+09
1E+10
Frequency (Hz)
Differential Return Loss
0
-5
-10
-15
-20
-25
-30
100000000
1E+09
1E+10
Frequency (Hz)
Figure 6-1. S-parameter plots for a TMUXHS4412 channel - top: differential insertion loss, and bottom:
return loss vs frequency
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Figure 6-2 shows side by side comparison of 10 Gbps signals through calibration traces and a typical
TMUXHS4412 channels.
Figure 6-2. Jitter decomposition of 10 Gbps PRBS-7 signals in TI evaluation board - Top: through
calibration traces, Bottom: through a typical TMUXHS4412 channels
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Figure 6-3 shows side by side comparison of 20 Gbps signals through calibration traces and a typical
TMUXHS4412 channels.
Figure 6-3. Jitter decomposition of 20 Gbps PRBS-7 signals in TI evaluation board - Top: through
calibration traces, Bottom: through a typical TMUXHS4412 channels
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7 Detailed Description
7.1 Overview
The TMUXHS4412 is a analog passive mux/demux that can work for any high-speed interface as long as its
signaling is differential, has a common mode voltage (CMV) that is within valid range (0 to 1.8 V for 3.3 V supply
voltage mode), and has amplitude up to 1800 mVpp-differential. It employs adaptive input voltage tracking that
ensures the channel remains unchanged for the entire common mode voltage range. Two channels of the device
can be used for electrical signals that have different CMV between them. Two channels can also be used such a
way that the device switches two different interface signals with different data and electrical characteristics.
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. While the device is recommended for the interfaces up to 20
Gbps, actual data rate where the device can be used highly depends on the electrical channels. For low loss
channels where adequate margin is maintained the device can potentially be used for higher data rates.
The TMUXHS4412 is only recommended for differential signaling. If the two signals on differential lines are
completely un-correlated, then internal circuits can create certain artifacts. It is recommended to analyze the
data line biasing of the device for such single ended use cases. The device parameters are characterized for
differential signaling only.
7.2 Functional Block Diagram
DA0P
DA0N
D0P
D0N
DB0P
CMV
tracking
Gate driver
buffer
DB0N
SEL
DA1P
DA1N
D1P
D1N
DB1P
DB1N
CMV
tracking
Gate driver
buffer
SEL
Switch
Regulation
& Bias
VCC
PD
TMUXHS4412
SEL
Circuits
GND
DA2P
DA2N
D2P
D2N
DB2P
DB2N
CMV
tracking
Gate driver
buffer
SEL
DA3P
DA3N
D3P
D3N
DB3P
DB3N
CMV
tracking
Gate driver
buffer
SEL
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7.3 Feature Description
7.3.1 Output Enable and Power Savings
The TMUXHS4412 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very-little current to achieve ultra low power in systems where power
saving is critical. To enter standby mode, the PD control pin is pulled high through a resistor and must remain
high. For active/normal operation, the PD control pin should be pulled low to GND or dynamically controlled to
switch between H or L.
7.3.2 Data Line Biasing
The TMUXHS4412 has a weak pull-down of 1MΩ from D[0/1/2/3][P/N] pins to GND. While these resistors biases
the device data channels to common mode voltage (CMV) of 0 V with very weak strength, it is recommended
that the device is biased by a stronger impedance from either side of the device to a valid value. To avoid double
biasing appropriate AC coupling capacitors should be ensured on either side of the device.
In certain use cases if both side of the TMUXHS4412 is ac coupled, it is recommended that appropriate CMV
biasing is used for the device. 10 kΩ to GND or any other bias voltage in the CMV range for each D[0/1/2/3][P/N]
pin will suffice for most use cases.
The high-speed data ports incorporate 20 kΩ pull-down resistors that are switched in when a port is not selected
and switched out when the port is selected. For example when SEL = L, the DB[0/1/2/3][P/N] pins have 20 kΩ
resistors to GND. The feature ensures that unselected port is always biased to a known voltage for long term
reliability of the device and the electrical channel.
The positive and negative terminals of data pins D[0/1/2/3] have a weak (20 kΩ) differential resistor in between
them for device switch regulation operation. This does not impact signal integrity or functionality of high speed
differential signaling that typically has much stronger differential impedance (such as 100 Ω).
7.4 Device Functional Modes
Table 7-1. Port Select Control Logic (1)
PORT DA OR PORT DB CHANNEL CONNECTED TO PORT D CHANNEL
PORT D CHANNEL
SEL = L
DA0P
DA0N
DA1P
DA1N
DA2P
DA2N
DA3P
DA3N
SEL = H
DB0P
DB0N
DB1P
DB1N
DB2P
DB2N
DB3P
DB3N
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
(1) The TMUXHS4412 can tolerate polarity inversions for all differential signals on Ports D, DA, and
DB. In such flexible implementation one must ensure that the same polarity is maintained on Port D
versus Ports DA/DB.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TMUXHS4412 is an analog 4-channel high-speed mux/demux type of switch that can be used for routing
high-speed signals between two different locations on a circuit board. The TMUXHS4412 can be used for many
high speed interfaces including:
•
•
•
•
•
•
•
•
•
•
•
Peripheral Component Interconnect Express (PCIe) Gen 1.0, 2.0, 3.0, 4.0
USB 4.0
Universal Serial Bus (USB) 3.2 Gen 1.0, 2.0
Serial ATA (SATA/eSATA)
Serial Attached SCSI (SAS)
Display Port (DP) 1.4, 2.0
Thunderbolt (TBT) 3.0
Mipi Camera Serial Interface (CSI-2), Display Serial Interface (DSI)
Low Voltage Differential Signalling (LVDS)
Serdes Framer Interface (SFI)
Ethenet Interfaces
The device’s mux/demux selection pin SEL can easily be controlled by an available GPIO pin of a controller or
hard tie to voltage level H or L as an application requires.
The TMUXHS4412 with adaptive voltage tracking technology can support applications where the common mode
is different between the RX and TX pair. The switch paths of the TMUXHS4412 have internal weak pull-down
resistors of 1 MΩ on the common port pins. While these resistors biases the device data channels to common
mode voltage (CMV) of 0 V with a weak strength, it is recommended that the device is biased from either side of
the device to a valid value (in the range of 0 - 1.8 V in 3.3 V supply voltage mode). It is expected that the system/
host controller and Device/End point common mode bias impedances are much stronger (smaller) than the
TMUXHS4412 internal pull-down resistors; therefore, they are not impacted.
Many interfaces require AC coupling between the transmitter and receiver. The 0201 or 0402 capacitors are the
preferred option to provide AC coupling. Avoid the 0603, 0805 size capacitors and C-packs. When placing AC
coupling capacitors, symmetric placement is best. The capacitor value must be chosen according to the specific
interface the device is being used. The value of the capacitor should match for the positive and negative signal
pair. For many interfaces such as USB 3.2 and PCIe, the designer should place them along the TX pairs on the
system board, which are usually routed on the top layer of the board. Depending upon the application and
interface specifications, use the appropriate value for AC coupling capacitors.
The AC coupling capacitors have several placement options. Typical use cases warrant that the capacitors are
placed on one side of the TMUXHS4412. In certain use cases, if both side of the TMUXHS4412 is ac coupled, it
is recommended that appropriate CMV biasing is used for the device. 10 kΩ to GND or any other bias voltage in
the valid CMV range for each D[0/1/2/3][P/N] pin of the common port suffice for most use cases. Figure 8-1
shows a few placement options. Note for brevity not all channels are illustrated in the block diagrams. Some
interfaces such as USB SS and PCIe recommends AC coupling capacitors on the TX signals before it goes to a
connector. Option (a) features TX AC coupling capacitors on the connector side of the TMUXHS4412. Option (b)
illustrates the capacitors on the host of the TMUXHS4412. Option (c) showcases where the TMUXHS4412 is ac
coupled on both sides. VBIAS must be within the valid CMV of the device.
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Device/EndPoint Board
Device/EndPoint Board
RX
RX
RX
RX
TX
Device/
EndPoint
Device/
EndPoint
TX
RX
TX
TX
TX
TX
TX
TX
Host
Host
RX
RX
RX
RX
RX
RX
TX
RX
TX
Device/
EndPoint
Device/
EndPoint
TX
TX
Host Board
Host Board
Device/EndPoint Board
Device/EndPoint Board
(a)
(b)
Device/EndPoint Board
VBIAS
RX
Device/
EndPoint
TX
TX
Host
RX
RX
Device/
EndPoint
VBIAS
TX
Host Board
Device/EndPoint Board
(c)
Figure 8-1. AC Coupling Capacitors Placement Options between Host and Device / Endpoint
8.2 Typical Applications
8.2.1 PCIe Lane Muxing
The TMUXHS4412 can be used to switch PCIe lanes between two slots. In many PC and server motherboards,
the CPU does not have enough PCIe lanes to provide desired system flexibility for end customers. In such
applications, the TMUXHS4412 can be used to switch PCIe TX and RX lanes between two slots. Figure 8-2
provides a schematic where four TMUXHS4412 are used to switch eight PCIe lanes (8-TX and 8-RX channels).
Note the common mode voltage (CMV) bias for the TMUXHS4412 must be within the valid range. In
implementations where receiver CMV bias of a PCIe root complex or an end point can not be ensured within the
CMV range, additional DC blocking capacitors and appropriate CMV biasing must be implemented. One side of
the device has AC coupling capacitors. Additionally the PD pin must be low for device to work. This pin can be
driven by a processor.
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D0P
D0N
D1P
D1N
DA0P
DA0N
DB0P
DB0N
DA1P
DA1N
DB1P
DB1N
TX0_1
TX1_1
TX0
TX1
TX0_2
VCC
0.1 µF
SEL
PD
TX1_2
D2P
D2N
D3P
D3N
DA2P
DA2N
DB2P
DB2N
DA3P
DA3N
DB3P
DB3N
TX2_1
TX3_1
TX2
TX3
TX2_2
TX3_2
D0P
D0N
D1P
D1N
DA0P
DA0N
DB0P
DB0N
DA1P
DA1N
DB1P
DB1N
TX4_1
TX5_1
TX4
TX5
TX4_2
TX5_2
SEL
PD
D2P
D2N
D3P
D3N
DA2P
DA2N
DB2P
DB2N
DA3P
DA3N
DB3P
DB3N
TX6_1
TX7_1
TX6
TX7
TX6_2
TX7_2
D0P
D0N
D1P
D1N
DA0P
DA0N
DB0P
DB0N
DA1P
DA1N
DB1P
DB1N
RX0_1
RX1_1
RX0
RX1
RX0_2
RX1_2
SEL
PD
D2P
D2N
D3P
D3N
DA2P
DA2N
DB2P
DB2N
DA3P
DA3N
DB3P
DB3N
RX2
RX3
RX2_1
RX3_1
RX2_2
RX3_2
D0P
D0N
D1P
D1N
DA0P
DA0N
DB0P
DB0N
DA1P
DA1N
DB1P
DB1N
RX4
RX5
RX4_1
RX5_1
RX4_2
RX5_2
SEL
PD
D2P
D2N
D3P
D3N
DA2P
DA2N
DB2P
DB2N
DA3P
DA3N
DB3P
DB3N
RX6
RX7
RX6_1
RX7_1
RX6_2
RX7_2
10 kW
Controller
GND
Figure 8-2. PCIe Lane Muxing
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8.2.1.1 Design Requirements
Table 8-1 provide various parameters and their expected values to implement the PCIe lane switching topology.
Note the recommendation is for illustration purpose only.
Table 8-1. Design Parameters
DESIGN PARAMETER
VALUE
VALUE
(VCC = 3.3 V)
(VCC = 1.8 V)
Dx[P/N], DAx[P/N], DBx[P/N] CM
input voltage
0 V to 1.8 V
0 V to 0.9V
Must be biased
from Dx[P/N]
side)
SEL/PD pin max voltage for low
SEL/PD pin min voltage for high
<0.25*VCC
>0.75*VCC
AC coupling capacitor for PCIe
TX pins
75 nF to 265 nF
Decoupling capacitor for VCC
0.1 uF
8.2.1.2 Detailed Design Procedure
The TMUXHS4412 is a high-speed passive switch device that can behave as a mux or demux. Because this is a
passive switch, signal integrity is important because the device provides no signal conditioning capability. To
implement PCIe lane swithing topology, the designer needs to understand the following.
•
•
•
•
•
Determine the loss profile between circuits that are to be muxed or demuxed.
Provide clean impedance and electrical length matched board traces.
Provide a control signal for the SEL and PD pins.
The thermal pad must be connected to ground.
See the application schematics on recommended decouple capacitors from VCC pins to ground.
8.2.1.3 Pin-to-pin Passive versus Redriver Option
For eight lane PCIe lane muxing application a topology with four TMUXHS4412 devices is illustrated.
TMUXHS4412 is a passive mux/demux component that does not provide any signal conditioning. If a specific
board implementation has too much loss from CPU to PCIe CEM connectors, a signal conditioning device such
as linear redriver might be required for best fidelity of the PCIe link. DS160PR421 is a PCIe 4.0 linear redriver
with intergrated mux and DS160PR412 is a PCIe 4.0 linear redriver with integrated demux. Both of these
devices are pin-to-pin (p2p) compatible with TMUXHS4412 allowing easy transition if signal conditioing function
is needed to extend the PCIe link reach. Figure 8-3 illustrates p2p passive vs redriver option to implement PCIe
lane switching.
PCIe Card
PCIe Card
x16
Slot
x16
Slot
x8
x8
Connector-B
RXB 8-ch
Connector-B
RXB 8-ch
x8
x8
RX 8-ch
RX 8-ch
TMUXHS4412
4 Ch 2:1 Mux
DS160PR421
4 Ch 2:1 redriver mux
CPU
CPU
TX 8-ch
TX 8-ch
TXB 8-ch
TXB 8-ch
TMUXHS4412
4 Ch 1:2 demux
DS160PR412
4 Ch 1:2 redriver demux
Pin-2-pin
h
c
h
h
c
h
c
-
PCIe Card
PCIe Card
c
-
-
-
8
8
8
8
XA
XA
T
RXA
T
RXA
x8
x8
Slot
Connector-A
Slot
Connector-A
x8
x8
Passive option
Redriver option
Figure 8-3. Pin-to-pin passive vs redriver option for PCIe lane switching
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8.2.1.4 Application Curves
Figure 8-4 and Figure 8-5 show eye diagrams for PRBS-7 signals though calibration trace and TMUXHS4412 for
PCIe 3.0 (8 Gbps) and PCIe 4.0 (16 Gbps) respectively.
Figure 8-4. 8 Gbps PRBS-7 signals in TI evaluation board - Top: through calibration traces, Bottom:
through a typical TMUXHS4412 channel
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Figure 8-5. 16 Gbps PRBS-7 signals in TI evaluation board - Top: through calibration traces, Bottom:
through a typical TMUXHS4412 channel
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8.3 Systems Examples
8.3.1 PCIe Muxing for Hybrid SSD
Figure 8-6 illustrate a use case where a hybrid SSD is shared by CPU and an IO expander (PCH).
TX
0
1
2
3
0
1
0
RX
TX
RX
1
CPU
PCH
TX
RX
M.2
TX
RX
2
3
TX
RX
TX
RX
TX
RX
TX
RX
TMUXHS4412
Figure 8-6. PCIe muxing to M.2 connectivitivity for hybrid SSD
8.3.2 DisplayPort Main Link
Figure 8-7 shows an application block diagram to implement DisplayPort (DP) main link switch either in mux or
demux configuration. Note DP link also has sideband signals such as Auxiliary (AUX) and Hot Plug Detect
(HPD) which must be switched outside of this device.
SEL
SEL
DxP
DxN
DAxP
DAxN
DAxP
DAxN
DxP
DxN
DP
Source
DP Sink
A
DP
DP Sink
Source A
DBxP
DBxN
DBxP
DBxN
DP Sink
B
DP
Source B
PD
PD
AUX/HPD muxing are done outside of
the device. For brevity not shown.
TMUXHS4412
Demultiplexer
TMUXHS4412
Multiplexer
Figure 8-7. DisplayPort Main Link Demuxing/muxing
8.3.3 USB 4.0 / TBT 3.0 Demuxing
Figure 8-8 shows an application block diagram where TMUXHS4412 is used to demultiplex USB 4.0 / TBT 3.0
TX and TX signals. Note SBU signals within USB-C interface must be switched outside of this device.
SEL
TX1_A
RX1_A
USB-C
PortA
TX2_A
TX1
RX2_A
RX1
CPU
TX2
RX2
TX1_B
RX1_B
TX2_B
USB-C
PortB
RX2_B
PD
TMUXHS4412
Figure 8-8. USB 4.0 / TBT 3.0 Demuxing
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9 Power Supply Recommendations
The TMUXHS4412 does not require a power supply sequence. However, TI recommends that PD is asserted
low after device supply VCC is stable and in specification. TI also recommends to place ample decoupling
capacitors at the device VCC near the pin.
10 Layout
10.1 Layout Guidelines
On a high-K board, TI always recommends to solder the Power-pad™ onto the thermal land. A thermal land is
the area of solder-tinned-copper underneath the Power-pad package. On a high-K board, the TMUXHS4412 can
operate over the full temperature range by soldering the Power-pad onto the thermal land without vias.
For high speed layout guidelines refer to High-Speed Layout Guidelines for Signal Conditioners and USB Hubs,
SLLA414.
On a low-K board, for the device to operate across the temperature range, the designer must use a 1-oz Cu
trace connecting the GND pins to the thermal land. A general PCB design guide for Power-pad packages is
provided in Power-pad Thermally-Enhanced Package, SLMA002.
10.2 Layout Example
Figure 10-1 shows TMUXHS4412 layout example.
Figure 10-1. TMUXHS4412 layout example
Figure 10-2 shows a layout illustration here four TMUXHS4412 is used to switch eight PCIe lanes between two
PCIe connectors.
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Figure 10-2. Layout example for PCIe lane muxing application
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUXHS4412IRUAR
TMUXHS4412IRUAT
TMUXHS4412RUAR
TMUXHS4412RUAT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RUA
RUA
RUA
RUA
42
42
42
42
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 105
0 to 70
HS4412
NIPDAU
NIPDAU
NIPDAU
HS4412
HS4412
HS4412
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUXHS4412IRUAR
TMUXHS4412IRUAT
TMUXHS4412RUAR
WQFN
WQFN
WQFN
RUA
RUA
RUA
42
42
42
3000
250
330.0
180.0
330.0
16.4
16.4
16.4
3.8
3.8
3.8
9.3
9.3
9.3
1.0
1.0
1.0
8.0
8.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUXHS4412IRUAR
TMUXHS4412IRUAT
TMUXHS4412RUAR
WQFN
WQFN
WQFN
RUA
RUA
RUA
42
42
42
3000
250
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RUA0042A
WQFN - 0.8 mm max height
S
C
A
L
E
1
.
8
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
9.1
8.9
0.8
0.6
C
SEATING PLANE
0.08 C
0.05
0.00
2.05 0.1
2X 1.5
SYMM
(0.1) TYP
EXPOSED
THERMAL PAD
21
18
17
22
SYMM
43
2X 8
7.55 0.1
0.3
0.2
1
38
42X
42
39
38X 0.5
0.1
C A B
0.5
0.3
42X
PIN 1 ID
0.05
4219139/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
SEE SOLDER MASK
DETAIL
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(3.525) TYP
(R0.05) TYP
(
0.2) TYP
VIA
1.17 TYP
SYMM
43
(7.55) (8.8)
17
22
18
21
(0.775)
TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219139/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RUA0042A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.56) TYP
42X (0.6)
42X (0.25)
42
39
1
38X (0.5)
38
(R0.05) TYP
(0.585)
TYP
43
SYMM
(8.8)
12X (0.97)
22
17
21
18
12X (0.92)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 12X
EXPOSED PAD 43
69% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219139/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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TMUXHS4412RUAT
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TMV-EN
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TMV-EN_07
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TMV0503SHI
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TMV0505
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TMV0505D
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TMV0505DEN
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TMV0505DHI
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