TMX320C6411ZLZ [TI]
FIXED POINT DIGITAL SIGNAL PROCESSOR; 定点数字信号处理器
| 型号： | TMX320C6411ZLZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| 文件： | 总119页 (文件大小：1727K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
D
D
Low-Cost, High-Performance Fixed-Point
DSP − TMS320C6411
− 3.33-ns Instruction Cycle Time
− 300-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 2400 MIPS
− Fully Software-Compatible With
TMS320C62x
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
D
D
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
− Access to Entire Memory Map
D
32-Bit/33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2
− Access to Entire Memory Map
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
D
Three 32-Bit General-Purpose Timers
D
D
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache (Flexible RAM/Cache
Allocation)
Sixteen General-Purpose I/O (GPIO) Pins
− Programmable Interrupt/Event
Generation Modes
D
D
D
D
D
Flexible PLL Clock Generator
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package
(GLZ and ZLZ Suffix), 0.8-mm Ball Pitch
0.13-µm/6-Level Copper Metal Process
− CMOS Technology
3.3-V I/Os, 1.2-V Internal
D
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 512M-Byte Total Addressable External
Memory Space
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
ꢐꢖ ꢑ ꢎꢗ ꢆ ꢀꢋ ꢑ ꢒ ꢎ ꢔꢀꢔ ꢘꢙ ꢚ ꢛꢜ ꢝ ꢞꢟ ꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟ ꢘꢛꢙ ꢧꢞ ꢟꢣ ꢨ
ꢐꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛ ꢜ ꢝ ꢟ ꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘ ꢛꢙꢠ ꢤꢣ ꢜ ꢟꢩ ꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢀꢣꢪ ꢞꢠ ꢋꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ
ꢠ ꢟ ꢞ ꢙꢧ ꢞ ꢜꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢐꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
Copyright 2004, Texas Instruments Incorporated
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
GLZ and ZLZ BGA packages (bottom view) . . . . . . . . . . . . . 6
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
functional block and CPU (DSP core) diagram . . . . . . . . . . 10
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 11
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 16
EDMA channel synchronization event . . . . . . . . . . . . . . . . . 26
interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 27
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 60
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 67
recommended operating conditions . . . . . . . . . . . . . . . . 67
electrical characteristics over recommended ranges of
supply voltage and operating case temperature . 68
recommended clock and control signal transition
behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
parameter measurement information . . . . . . . . . . . . . . . 69
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 75
programmable synchronous interface timing . . . . . . . . 78
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 82
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 93
host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . . 94
peripheral component interconnect (PCI) timing . . . . . . 99
multichannel buffered serial port (McBSP) timing . . . . 102
timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
general-purpose input/output (GPIO) port timing . . . . 114
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 65
EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS196G device-specific data
sheet to make it an SPRS196H revision.
Scope: Applicable updates to the C64x device family, specifically relating to the C6411 devices, have been incor-
porated. Added C6411A silicon revision 2.0 devices and associated device-specific information at the product
data (PD) stage of development.
The extended temperature devices for silicon revision 2.0 (C641x A-5E0, C641xA-6E3) are at the advance infor-
mation (AI) stage of development. All other devices are at the Production Data (PD) stage of development.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
6
GLZ and ZLZ BGA packages (bottom view) section:
Added “and ZLZ” to the “GLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)” figure title
Added a ZLZ clarification footnote to the GLZ and ZLZ BGA packages (bottom view) figure
7
Description section:
“With performance of up to 2400 million instructions per second (MIPS) ...” paragraph
Changed “The C6411 can produce two 32-bit multiply-accumulates (MACs) per ...” sentence to “The C6411 can produce
four 16-bit multiply-accumulates (MACs) per ...”
8
Table 1, Characteristics of the C6411 Processor:
Changed the EDMA INTERNAL CLOCK SOURCE reference from “CPU Clock Frequency” to “CPU/2 Clock Frequency”
15
L2 architecture expanded section:
Added new section
Added Figure 2, TMS320C6411 L2 Architecture Memory Configuration
17
20
Peripheral register descriptions section:
Table 5, L2 Cache Registers:
Added “Reserved” row “0184 1004 − 0184 1FFC”
Changed “Reserved” row “0184 4050 −0184 4FFF” to “0184 4050 −0184 4FFC”
Peripheral register descriptions section:
EDMA Parameter RAM table:
Updated associated table footnote from “The C64x device ...” to “The C6411 device ...”
55
Added “device support” section title (new)
55−56
Device and development-support tool nomenclature section:
Updated/changed “Table 1 displays the device part numbers and ordering information for ...” paragraph
Deleted the “TMX and TMP devices and TMDX development-support tools are shipped with ...” paragraph
Figure 5, TMS320C6411 DSP Device Nomenclature:
Updated/changed the “For the actual device part number (P/N), ...” footnote
Added, below Figure 5, “For additional information, see the TMS320C6411 Digital Signal Processor Silicon Errata (literature
number SPRZ194)” paragraph (new)
57
Documentation support section:
Deleted “See the Worldwide Web URL for Texas Instruments” from the SPRA718 and SPRA374 reference paragraph
Moved the SPRA718 and SPRA374 reference paragraph up
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
64
Power-supply decoupling section:
Updated/changed the “In order to properly decouple the supply planes from system noise, place as many capacitors ...”
paragraph
Added two subsequent paragraphs
65
66
75
IEEE 1149.1 JTAG compatibility statement section:
Updated/added paragraphs for clarity
Reset section:
Added new section
Asynchronous Memory Timing section:
Timing Requirements for Asynchronous Memory Cycles table:
Added/split silicon revisions “Rev 1.1” and “Rev 2.0” for the MIN value of parameter #7 “t
valid after ECLKOUTx high”
, Hold time, ARDY
h(EKO1H-ARDY)
Added the MIN value of “1.3” ns for “Rev 2.0”
89
91
HOLD/HOLDA Timing section:
Timing Requirements for the HOLD/HOLDA Cycles table:
Changed parameter NO. 3 from “t
” to “t ”
oh(HOLDAL-HOLDL) h(HOLDAL-HOLDL)
Reset Timing section:
Timing Requirements for Reset table:
Changed the MIN value of parameter No. 16, t
from “4P” to “4E or 4C” ns
su(boot)
Added associated footnote to identify “E” and “C”
Added parameter NO. 18, “t Delay time, PCLK active to RESET high” with a MIN value of “32N” ns
d(PCLK−RSTH)
Changed parameter NO. 18 description from “t
Delay time, PCLK active to RESET high” to “t ,
su(PCLK-RSTH)
d(PCLK−RSTH)
Setup time, PCLK active before RESET high”
Added associated footnote to identify “N” and restraints
Switching Characteristics Over Recommended Operating Conditions During Reset table:
Moved parameter NO. 18, “t
table
Delay time, PCLK active to RESET high” to the Timing Requirements for Reset
d(PCLK−RSTH)
Updated footnote symbols
94
Host-Port Interface (HPI) Timing section:
Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles table:
Added “mode, 2nd half-word” to parameter NO. 16 “t , Delay time, HSTROBE low to HD valid (HPI16 only)”
d(HSTBL-HDV)
103−104 Multichannel Buffered Serial Port (McBSP) Timing section:
Switching Characteristics Over Recommended Operating Conditions for McBSP table:
Changed the MIN value of parameter #12 “t , Disable time, DX high impedance following last data bit from
dis(CKXH-DXHZ)
CLKX high, CLKX ext” from “−2.1” to “2.0” ns
Changed the MIN value of parameter #13 “t
“2.0 + D1” ns
, Delay time, CLKX high to DX valid, CLKX ext” from “−2.1 + D1” to
d(CKXH-DXV)
Changed the MIN value of parameter #14 “t
, Delay time, FSX high to DX valid, FSX int” from “−2.3” to
d(FXH-DXV)
h
“−2.3 + D1 ” ns
Changed the MAX value of parameter #14 “t
, Delay time, FSX high to DX valid, FSX int” from “5.6” to
d(FXH-DXV)
h
“5.6 + D2 ” ns
Changed the MIN value of parameter #14 “t
, Delay time, FSX high to DX valid, FSX ext” from “1.9” to
d(FXH-DXV)
h
“1.9 + D1 ” ns
h
Changed the MAX value of parameter #14 “t
, Delay time, FSX high to DX valid, FSX ext” from “9” to “9 + D2 ” ns
d(FXH-DXV)
Added associated footnote
Figure 51, McBSP Timing:
Added footnote for clarity
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PAGE(S)
NO.
ADDITIONS/CHANGES/DELETIONS
101
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING section:
Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM Interface table:
Changed parameter NO. 6 description from “t , Output setup time, XSP_DO valid after XSP_CLK high” to
osu(DOV-CLKH)
, Output setup time, XSP_DO valid before XSP_CLK high”
“t
osu(DOV-CLKH)
114
General-Purpose Input/Output (GPIO) Port Timing section:
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs table:
Changed the MIN value of parameter #3 “t
Changed the MIN value of parameter #4 “t
Added associated footnote
, Pulse duration, GPOx high” from “32P” to “24P − 8” ns
w(GPOH)
, Pulse duration, GPOx low” from “32P” to “24P − 8” ns
w(GPOL)
116
MECHANICAL DATA section:
Deleted the “GLZ and ZLZ (S-PBGA-N532), PLASTIC BALL GRID ARRAY” mechanical data package diagram; now an
automated merged process
Added the “thermal resistance characteristics (S-PBGA package) [ZLZ]” table
Added lead-in sentence for the thermal resistance characteristics table(s) and the “merged” mechanical data packages
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
GLZ and ZLZ BGA packages (bottom view)
GLZ and ZLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE
†
(BOTTOM VIEW)
AF
AD
AB
Y
AE
AC
AA
W
U
V
T
R
P
N
M
K
L
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24 26
†
The ZLZ mechanical package designator represents the version of the GLZ package with lead-free balls. For more detailed information
see the Mechanical Data section of this document.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
description
The TMS320C64x DSPs (including the TMS320C6411 device) are the highest-performance fixed-point DSP
generation in the TMS320C6000 DSP platform. The TMS320C6411 (C6411) device is based on the
second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture
(VelocTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel
and multifunction applications. The C64x is a code-compatible member of the C6000 DSP platform.
With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6411
device offers cost-effective solutions to high-performance DSP programming challenges. The C6411 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with
VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to
accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The
C6411 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second
(MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. The C6411 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other
C6000 DSP platform devices.
The C6411 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 2-Mbit memory space that is shared
between program and data space. L2 memory can be configured as mapped memory or combinations of cache
(up to 256K bytes) and mapped memory. The peripheral set includes two multichannel buffered serial ports
(McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface
(HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with
16 GPIO pins; and a glueless external memory interface (32-bit EMIF), which is capable of interfacing to
synchronous and asynchronous memories and peripherals.
The C6411 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
device characteristics
Table 1 provides an overview of the C6411 DSP. The table shows significant features of the C6411 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 1. Characteristics of the C6411 Processor
INTERNAL CLOCK
HARDWARE FEATURES
EMIF (32-bit bus width)
C6411
SOURCE
Peripherals
ECLKIN
1
EDMA (64 independent channels) CPU/2 Clock Frequency
HPI (32- or 16-bit user selectable) CPU/4 Clock Frequency
1
Not all peripherals pins are
available at the same time.
(For more details, see the
Device Configuration
section.)
1 (HPI16 or HPI32)
PCI (32-bit)
PCLK
1
2
3
McBSPs (McBSP0 and McBSP1)
32-Bit Timers
CPU/4 Clock Frequency
CPU/8 Clock Frequency
Peripheral performance is
dependent on chip-level
configuration.
General-Purpose Input/Outputs
(GPIOs)
CPU/8 Clock Frequency
16
Size (Bytes)
288K
16K-Byte (16KB) L1 Program (L1P)
Cache
16KB L1 Data (L1D) Cache
256KB Unified Mapped RAM/Cache (L2)
On-Chip Memory
Organization
CPU ID + CPU Rev ID
Device_ID
Control Status Register (CSR.[31:16])
0x0C01
Silicon Revision Identification Register
(DEVICE_REV [19:16])
Address: 0x01B0 0200
DEVICE_REV[19:16] Silicon Revision
0010 or 0000
0011
1.1
2.0
Frequency
Cycle Time
MHz
300
ns
3.33 ns
1.2 V
Core (V)
Voltage
I/O (V)
3.3 V
PLL Options
CLKIN frequency multiplier
Bypass (x1), x6
532-Pin BGA (GLZ and ZLZ)
0.13 µm
BGA Package
23 x 23 mm
Process Technology
µm
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
†
Product Status
PD (1.1, 2.0)
(For more details on the C64x DSP part numbering, see
Figure 5)
TMS320C6411GLZ
TMS320C6411AGLZ
Device Part Numbers
†
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
device compatibility
The C64x family of devices has a diverse and powerful set of peripherals. The common peripheral set that
the C6411 and C6415 devices offer lead to easier system designs and faster time to market.
The C6411 device is a low-cost C64x device which features significant enhancements from the C6211/C6211B
devices and can be considered a subset of the C6415 device. Table 2 identifies the C6411 features in
comparison with the C6211 and C6415 devices.
†‡
Table 2. C6211, C6411, and C6415 Device Comparison
CPU/PERIPHERALS
C6211/C6211B
C62x
C6411
C64x
C6415
C64x
DSP Core
L1P (Program Cache)
4 KB
16 KB
16 KB
256 KB
16 KB
16 KB
1024 KB
L1D (Data Cache)
4 KB
L2 (Unified Mapped RAM/Cache)
64 KB
(1) 64-Bit(1) [EMIFA]
(1) 16-Bit [EMIFB]
programmable
(1) 32-Bit EMIF
programmable
synchronous mode
EMIF (64-, 32-, 16-bit bus width)
(1) 32-Bit
synchronous mode
EDMA
16
64
64
(# of independent channels)
HPI (32- or 16-bit user selectable)
PCI (32-bit)
16-Bit
—
32-/16-Bit
32-Bit, 33 MHz
2 Enhanced
32-/16-Bit
32-Bit, 33 MHz
3 Enhanced
McBSPs (McBSP0, McBSP1, and McBSP2)
2
(1) Transmit
(1) Receive
UTOPIA
—
2
—
3
Timers (32-bit)
[TIMER0, TIMER1, TIMER2]
3
GPIOs (GP[15:0])
Core Frequency (MHz)
Core Voltage (V)
—
16
16
150-, 167-MHz
1.8 V
300-MHz
1.2 V
500-, 600-MHz
1.2 V to 1.4 V
PLL Modes
(x1 [Bypass], x4, x6, x12)
x1, x4
x1, x6
x1, x6, x12
256-pin BGA
27 x 27 mm
GFN suffix
532-pin BGA
23 x 23 mm
GLZ suffix
532-pin BGA
23 x 23 mm
GLZ suffix
Package
Process Technology
0.18 µm
0.13 µm
0.13 µm
†
‡
— denotes peripheral/coprocessor is not available on this device.
Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.)
For more detailed information on the device compatibility and similarities/differences among the C6211, C6411,
and C6415 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and
TMS320C6416 DSPs application report (literature number SPRA718) and How To Begin Development Today
With the TMS320C6411 DSP application report (literature number SPRA374).
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
functional block and CPU (DSP core) diagram
C6411 Digital Signal Processor
SDRAM
SBSRAM
L1P Cache
Direct-Mapped
16K Bytes Total
ZBT SRAM
FIFO
32
EMIF
SRAM
C64x DSP Core
ROM/FLASH
I/O Devices
Instruction Fetch
Control
Registers
Instruction Dispatch
Advanced Instruction Packet
Control
Logic
Timer 2
Timer 1
Timer 0
Instruction Decode
Data Path A
Data Path B
Test
A Register File
A31−A16
B Register File
B31−B16
Advanced
In-Circuit
Emulation
A15−A0
B15−B0
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
L2
Memory
256K
Enhanced
DMA
Controller
(64-channel)
McBSP1
McBSP0
McBSPs:
Bytes
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
L1D Cache
2-Way Set-Associative
16K Bytes Total
9
7
GPIO[8:0]
†
GPIO[15:9]
32
32
†
HPI
or
Boot Configuration
†
PCI
Power-Down
Logic
PLL
(x1, x6)
Interrupt
Selector
†
The PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these
peripherals, see the Device Configurations section of this data sheet.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP
VelociTI architecture. These enhancements include:
D
D
D
D
D
D
Register file enhancements
Data path extensions
Quad 8-bit and dual 16-bit extensions with data flow enhancements
Additional functional unit hardware
Increased orthogonality of the instruction set
Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed
16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register
files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with
two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram,
and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to
that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers
on the other side, by which the two sets of functional units can access data from the register files on the opposite
side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same
register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All
functional units in the C64x CPU can access operands via the data cross path. Register access by functional
units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x
CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that
register was updated in the previous clock cycle.
In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of
quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to
operate directly on packed data to streamline data flow and increase instruction set efficiency.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction.
And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single
instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and
doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either
linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any
one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to
hold the condition for conditional instructions (if the condition is not automatically “true”).
TMS320C62x is a trademark of Texas Instruments.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
CPU (DSP core) description (continued)
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the
next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x
DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added
to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a
fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at
the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from
the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active
functional units for a maximum execution rate of eight instructions every clock cycle. While most results are
stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or
doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
TMS320C64x Technical Overview (literature number SPRU395)
How To Begin Development Today With the TMS320C6411 DSP application report (literature number
SPRA374)
TMS320C67x is a trademark of Texas Instruments.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
CPU (DSP core) description (continued)
src1
.L1
src2
dst
8
long dst
long src
8
32 MSBs
32 LSBs
ST1b (Store Data)
ST1a (Store Data)
8
long src
long dst
dst
8
Register
File A
src1
(A0−A31)
.S1
Data Path A
src2
See Note A
See Note A
long dst
dst
src1
.M1
src2
32 MSBs
32 LSBs
LD1b (Load Data)
LD1a (Load Data)
dst
DA1 (Address)
src1
.D1
.D2
src2
2X
1X
src2
src1
dst
DA2 (Address)
32 LSBs
32 MSBs
LD2a (Load Data)
LD2b (Load Data)
src2
src1
dst
.M2
See Note A
See Note A
long dst
Register
File B
(B0− B31)
src2
Data Path B
.S2
src1
dst
long dst
long src
8
8
32 MSBs
32 LSBs
ST2a (Store Data)
ST2b (Store Data)
8
long src
long dst
dst
8
src2
.L2
src1
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1. TMS320C64x CPU (DSP Core) Data Paths
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
memory map summary
Table 3 shows the memory map address ranges of the C6411 device. Internal memory is always located at
address 0 and can be used as both program and data memory. The external memory address range in the
C6411 device begins at the hex address location 0x8000 0000 for the EMIF.
Table 3. TMS320C6411 Memory Map Summary
BLOCK SIZE
(BYTES)
MEMORY BLOCK DESCRIPTION
Internal RAM (L2)
HEX ADDRESS RANGE
256K
0000 0000 – 0003 FFFF
0004 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 FFFF
01B4 0000 – 01BF FFFF
01C0 0000 – 01C3 FFFF
01C4 0000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
Reserved
24M − 256K
256K
External Memory Interface (EMIF) Registers
L2 Registers
256K
HPI Registers
256K
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
EDMA RAM and EDMA Registers
Reserved
256K
256K
256K
256K
256K
256K
512K
Timer 2 Registers
GPIO Registers
Reserved
256K
256K
768K
PCI Registers
256K
Reserved
4M – 256K
52
QDMA Registers
Reserved
736M – 52
64M
McBSP 0 Data
McBSP 1 Data
64M
Reserved
1G + 128M
256M
256M
256M
256M
1G
†
†
†
†
EMIF CE0
EMIF CE1
EMIF CE2
EMIF CE3
Reserved
†
The number of EMIF address pins (EA[22:3]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.
To get 256MB of addressable memory, an additional general-purpose output pin or external logic is required.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
L2 architecture expanded
Figure 2 shows the detail of the L2 architecture on the TMS320C6411 device. For more information on the
L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x
Two-Level Internal Memory Reference Guide (literature number SPRU610).
L2MODE
010
L2 Memory
Block Base Address
000
001
011
111
0x0000 0000
128K-Byte SRAM
0x0002 0000
64K-Byte RAM
0x0003 0000
32K-Byte RAM
32K-Byte RAM
0x0003 8000
0x0003 FFFF
Figure 2. TMS320C6411 L2 Architecture Memory Configuration
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions
Table 4 through Table 17 identify the peripheral registers for the C6411 device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP
Peripherals Overview Reference Guide (literature number SPRU190).
Table 4. EMIF Registers
HEX ADDRESS RANGE
0180 0000
ACRONYM
GBLCTL
CECTL1
CECTL0
−
REGISTER NAME
EMIF global control
EMIF CE1 space control
EMIF CE0 space control
Reserved
0180 0004
0180 0008
0180 000C
0180 0010
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
EMIF CE2 space control
EMIF CE3 space control
EMIF SDRAM control
EMIF SDRAM refresh control
EMIF SDRAM extension
Reserved
0180 0014
0180 0018
0180 001C
0180 0020
0180 0024 − 0180 003C
0180 0040
PDTCTL
CESEC1
CESEC0
−
Peripheral device transfer (PDT) control
EMIF CE1 space secondary control
EMIF CE0 space secondary control
Reserved
0180 0044
0180 0048
0180 004C
0180 0050
CESEC2
CESEC3
–
EMIF CE2 space secondary control
EMIF CE3 space secondary control
Reserved
0180 0054
0180 0058 − 0183 FFFF
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 5. L2 Cache Registers
HEX ADDRESS RANGE
0184 0000
ACRONYM
CCFG
REGISTER NAME
Cache configuration register
Reserved
COMMENTS
0184 0004 −0184 0FFC
0184 1000
−
EDMAWEIGHT
−
L2 EDMA access control register
Reserved
0184 1004 − 0184 1FFC
0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
−
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
0184 2004
0184 2008
0184 200C
0184 2010 −0184 3FFF
0184 4000
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L2 writeback base address register
L2 writeback word count register
0184 4004
0184 4010
L2 writeback-invalidate base address register
L2 writeback-invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
0184 4014
0184 4018
0184 401C
0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
−
L1P invalidate base address register
L1P invalidate word count register
0184 4024
0184 4030
L1D writeback-invalidate base address register
L1D writeback-invalidate word count register
Reserved
0184 4034
0184 4038 −0184 4044
0184 4048
L1DIBAR
L1DIWC
−
L1D invalidate base address register
L1D invalidate word count register
Reserved
0184 404C
0184 4050 −0184 4FFC
0184 5000
L2WB
L2 writeback all register
0184 5004
L2WBINV
−
L2 writeback-invalidate all register
Reserved
0184 5008 −0184 7FFF
MAR0 to
MAR127
0184 8000 −0184 81FC
Reserved
0184 8200
0184 8204
0184 8208
0184 820C
0184 8210
0184 8214
0184 8218
0184 821C
0184 8220
0184 8224
0184 8228
0184 822C
MAR128
MAR129
MAR130
MAR131
MAR132
MAR133
MAR134
MAR135
MAR136
MAR137
MAR138
MAR139
Controls EMIF CE0 range 8000 0000 − 80FF FFFF
Controls EMIF CE0 range 8100 0000 − 81FF FFFF
Controls EMIF CE0 range 8200 0000 − 82FF FFFF
Controls EMIF CE0 range 8300 0000 − 83FF FFFF
Controls EMIF CE0 range 8400 0000 − 84FF FFFF
Controls EMIF CE0 range 8500 0000 − 85FF FFFF
Controls EMIF CE0 range 8600 0000 − 86FF FFFF
Controls EMIF CE0 range 8700 0000 − 87FF FFFF
Controls EMIF CE0 range 8800 0000 − 88FF FFFF
Controls EMIF CE0 range 8900 0000 − 89FF FFFF
Controls EMIF CE0 range 8A00 0000 − 8AFF FFFF
Controls EMIF CE0 range 8B00 0000 − 8BFF FFFF
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 5. L2 Cache Registers (Continued)
HEX ADDRESS RANGE
0184 8230
0184 8234
0184 8238
0184 823C
0184 8240
0184 8244
0184 8248
0184 824C
0184 8250
0184 8254
0184 8258
0184 825C
0184 8260
0184 8264
0184 8268
0184 826C
0184 8270
0184 8274
0184 8278
0184 827C
0184 8280
0184 8284
0184 8288
0184 828C
0184 8290
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
ACRONYM
REGISTER NAME
COMMENTS
MAR140
MAR141
MAR142
MAR143
MAR144
MAR145
MAR146
MAR147
MAR148
MAR149
MAR150
MAR151
MAR152
MAR153
MAR154
MAR155
MAR156
MAR157
MAR158
MAR159
MAR160
MAR161
MAR162
MAR163
MAR164
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
Controls EMIF CE0 range 8C00 0000 − 8CFF FFFF
Controls EMIF CE0 range 8D00 0000 − 8DFF FFFF
Controls EMIF CE0 range 8E00 0000 − 8EFF FFFF
Controls EMIF CE0 range 8F00 0000 − 8FFF FFFF
Controls EMIF CE1 range 9000 0000 − 90FF FFFF
Controls EMIF CE1 range 9100 0000 − 91FF FFFF
Controls EMIF CE1 range 9200 0000 − 92FF FFFF
Controls EMIF CE1 range 9300 0000 − 93FF FFFF
Controls EMIF CE1 range 9400 0000 − 94FF FFFF
Controls EMIF CE1 range 9500 0000 − 95FF FFFF
Controls EMIF CE1 range 9600 0000 − 96FF FFFF
Controls EMIF CE1 range 9700 0000 − 97FF FFFF
Controls EMIF CE1 range 9800 0000 − 98FF FFFF
Controls EMIF CE1 range 9900 0000 − 99FF FFFF
Controls EMIF CE1 range 9A00 0000 − 9AFF FFFF
Controls EMIF CE1 range 9B00 0000 − 9BFF FFFF
Controls EMIF CE1 range 9C00 0000 − 9CFF FFFF
Controls EMIF CE1 range 9D00 0000 − 9DFF FFFF
Controls EMIF CE1 range 9E00 0000 − 9EFF FFFF
Controls EMIF CE1 range 9F00 0000 − 9FFF FFFF
Controls EMIF CE2 range A000 0000 − A0FF FFFF
Controls EMIF CE2 range A100 0000 − A1FF FFFF
Controls EMIF CE2 range A200 0000 − A2FF FFFF
Controls EMIF CE2 range A300 0000 − A3FF FFFF
Controls EMIF CE2 range A400 0000 − A4FF FFFF
Controls EMIF CE2 range A500 0000 − A5FF FFFF
Controls EMIF CE2 range A600 0000 − A6FF FFFF
Controls EMIF CE2 range A700 0000 − A7FF FFFF
Controls EMIF CE2 range A800 0000 − A8FF FFFF
Controls EMIF CE2 range A900 0000 − A9FF FFFF
Controls EMIF CE2 range AA00 0000 − AAFF FFFF
Controls EMIF CE2 range AB00 0000 − ABFF FFFF
Controls EMIF CE2 range AC00 0000 − ACFF FFFF
Controls EMIF CE2 range AD00 0000 − ADFF FFFF
Controls EMIF CE2 range AE00 0000 − AEFF FFFF
Controls EMIF CE2 range AF00 0000 − AFFF FFFF
Controls EMIF CE3 range B000 0000 − B0FF FFFF
Controls EMIF CE3 range B100 0000 − B1FF FFFF
Controls EMIF CE3 range B200 0000 − B2FF FFFF
Controls EMIF CE3 range B300 0000 − B3FF FFFF
Controls EMIF CE3 range B400 0000 − B4FF FFFF
Controls EMIF CE3 range B500 0000 − B5FF FFFF
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 5. L2 Cache Registers (Continued)
HEX ADDRESS RANGE
0184 82D8
ACRONYM
REGISTER NAME
COMMENTS
MAR182
MAR183
MAR184
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
Controls EMIF CE3 range B600 0000 − B6FF FFFF
Controls EMIF CE3 range B700 0000 − B7FF FFFF
Controls EMIF CE3 range B800 0000 − B8FF FFFF
Controls EMIF CE3 range B900 0000 − B9FF FFFF
Controls EMIF CE3 range BA00 0000 − BAFF FFFF
Controls EMIF CE3 range BB00 0000 − BBFF FFFF
Controls EMIF CE3 range BC00 0000 − BCFF FFFF
Controls EMIF CE3 range BD00 0000 − BDFF FFFF
Controls EMIF CE3 range BE00 0000 − BEFF FFFF
Controls EMIF CE3 range BF00 0000 − BFFF FFFF
0184 82DC
0184 82E0
0184 82E4
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
MAR192 to
MAR255
0184 8300 −0184 83FC
0184 8400 −0187 FFFF
Reserved
Reserved
−
Table 6. EDMA Registers
HEX ADDRESS RANGE
01A0 FF9C
01A0 FFA4
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
01A0 FFB8
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
01A0 FFF8
01A0 FFFC
ACRONYM
EPRH
CIPRH
CIERH
CCERH
ERH
REGISTER NAME
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
Event enable high register
Event clear high register
Event set high register
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
PQSR
CIPRL
CIERL
CCERL
ERL
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
EERL
Event enable low register
ECRL
Event clear low register
ESRL
Event set low register
01A1 0000 − 01A3 FFFF
–
Reserved
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
†
Table 7. EDMA Parameter RAM
HEX ADDRESS RANGE
01A0 0000 − 01A0 0017
01A0 0018 − 01A0 002F
01A0 0030 − 01A0 0047
01A0 0048 − 01A0 005F
01A0 0060 − 01A0 0077
01A0 0078 − 01A0 008F
01A0 0090 − 01A0 00A7
01A0 00A8 − 01A0 00BF
01A0 00C0 − 01A0 00D7
01A0 00D8 − 01A0 00EF
01A0 00F0 − 01A0 00107
01A0 0108 − 01A0 011F
01A0 0120 − 01A0 0137
01A0 0138 − 01A0 014F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
...
ACRONYM
REGISTER NAME
Parameters for Event 0 (6 words)
Parameters for Event 1 (6 words)
Parameters for Event 2 (6 words)
Parameters for Event 3 (6 words)
Parameters for Event 4 (6 words)
Parameters for Event 5 (6 words)
Parameters for Event 6 (6 words)
Parameters for Event 7 (6 words)
Parameters for Event 8 (6 words)
Parameters for Event 9 (6 words)
Parameters for Event 10 (6 words)
Parameters for Event 11 (6 words)
Parameters for Event 12 (6 words)
Parameters for Event 13 (6 words)
Parameters for Event 14 (6 words)
Parameters for Event 15 (6 words)
Parameters for Event 16 (6 words)
Parameters for Event 17 (6 words)
...
COMMENTS
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
...
...
01A0 05D0 − 01A0 05E7
01A0 05E8 − 01A0 05FF
01A0 0600 − 01A0 0617
01A0 0618 − 01A0 062F
...
−
−
−
−
Parameters for Event 62 (6 words)
Parameters for Event 63 (6 words)
Reload/link parameters for Event M (6 words)
Reload/link parameters for Event N (6 words)
...
01A0 07E0 − 01A0 07F7
01A0 07F8 − 01A0 07FF
−
−
Reload/link parameters for Event Z (6 words)
Scratch pad area (2 words)
†
The C6411 device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
Table 8. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
0200 0000
ACRONYM
QOPT
REGISTER NAME
QDMA options parameter register
0200 0004
QSRC
QCNT
QDMA source address register
QDMA frame count register
QDMA destination address register
QDMA index register
0200 0008
0200 000C
QDST
0200 0010
QIDX
0200 0014 − 0200 001C
0200 0020
Reserved
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
QDMA pseudo options register
QDMA psuedo source address register
QDMA psuedo frame count register
QDMA destination address register
QDMA psuedo index register
0200 0024
0200 0028
0200 002C
0200 0030
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 9. Interrupt Selector Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
019C 0004
MUXL
Interrupt multiplexer low
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 0008
EXTPOL
−
External interrupt polarity
Reserved
019C 000C − 019C 01FF
Table 10. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA
controller can only read this
register; they cannot write to
it.
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
DRR0
DXR0
McBSP0 data receive register via Peripheral Data Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Data Bus
McBSP0 serial port control register
0x3000 0000 − 0x33FF FFFF
018C 0008
DXR0
SPCR0
RCR0
018C 000C
McBSP0 receive control register
018C 0010
XCR0
McBSP0 transmit control register
018C 0014
SRGR0
MCR0
McBSP0 sample rate generator register
018C 0018
McBSP0 multichannel control register
018C 001C
RCERE00
XCERE00
PCR0
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
018C 0020
018C 0024
018C 0028
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 − 018F FFFF
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 11. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA
controller can only read this
register; they cannot write to
it.
0190 0000
DRR1
Data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF
0190 0004
DRR1
DXR1
McBSP1 data receive register via Peripheral Data Bus
McBSP1 data transmit register via Configuration Bus
McBSP1 data transmit register via Peripheral Data Bus
McBSP1 serial port control register
0x3400 0000 − 0x37FF FFFF
0190 0008
DXR1
SPCR1
RCR1
0190 000C
McBSP1 receive control register
0190 0010
XCR1
McBSP1 transmit control register
0190 0014
SRGR1
MCR1
McBSP1 sample rate generator register
0190 0018
McBSP1 multichannel control register
0190 001C
RCERE01
XCERE01
PCR1
McBSP1 enhanced receive channel enable register 0
McBSP1 enhanced transmit channel enable register 0
McBSP1 pin control register
0190 0020
0190 0024
0190 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
–
McBSP1 enhanced receive channel enable register 1
McBSP1 enhanced transmit channel enable register 1
McBSP1 enhanced receive channel enable register 2
McBSP1 enhanced transmit channel enable register 2
McBSP1 enhanced receive channel enable register 3
McBSP1 enhanced transmit channel enable register 3
Reserved
0190 002C
0190 0030
0190 0034
0190 0038
0190 003C
0190 0040 − 0193 FFFF
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 12. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0194 0000
CTL0
Timer 0 control register
Timer 0 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0194 0004
PRD0
Contains the current value of
the incrementing counter.
0194 0008
CNT0
−
Timer 0 counter register
Reserved
0194 000C − 0197 FFFF
Table 13. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0198 0000
CTL1
Timer 1 control register
Timer 1 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0198 0004
PRD1
Contains the current value of
the incrementing counter.
0198 0008
CNT1
−
Timer 1 counter register
Reserved
0198 000C − 019B FFFF
Table 14. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
01AC 0000
CTL2
Timer 2 control register
Timer 2 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
01AC 0004
PRD2
Contains the current value of
the incrementing counter.
01AC 0008
CNT2
−
Timer 2 counter register
Reserved
01AC 000C − 01AF FFFF
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 15. HPI Registers
HEX ADDRESS RANGE
−
ACRONYM
REGISTER NAME
COMMENTS
HPID
HPI data register
Host read/write access only
HPIC has both Host/CPU
read/write access
0188 0000
0188 0004
0188 0008
HPIC
HPIA
HPI control register
HPI address register
(Write)
†
(HPIAW)
HPIA has both Host/CPU
read/write access
HPIA
(HPIAR)
HPI address register
(Read)
†
0188 000C − 0189 FFFF
018A 0000
−
TRCTL
−
Reserved
HPI transfer request control register
Reserved
018A 0004 − 018B FFFF
†
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
Table 16. GPIO Registers
HEX ADDRESS RANGE
01B0 0000
ACRONYM
GPEN
GPDIR
GPVAL
−
REGISTER NAME
GPIO enable register
01B0 0004
GPIO direction register
GPIO value register
Reserved
01B0 0008
01B0 000C
01B0 0010
GPDH
GPHM
GPDL
GPLM
GPGC
GPPOL
−
GPIO delta high register
GPIO high mask register
GPIO delta low register
GPIO low mask register
GPIO global control register
GPIO interrupt polarity register
Reserved
01B0 0014
01B0 0018
01B0 001C
01B0 0020
01B0 0024
01B0 0028 − 01B0 01FF
Silicon Revision Identification Register
(For more details, see the device characteristics listed in Table 1.)
01B0 0200
DEVICE_REV
−
01B0 0204 − 01B3 FFFF
Reserved
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
peripheral register descriptions (continued)
Table 17. PCI Peripheral Registers
HEX ADDRESS RANGE
01C0 0000
ACRONYM
RSTSRC
–
REGISTER NAME
DSP Reset source/status register
Reserved
01C0 0004
01C0 0008
PCIIS
PCIIEN
DSPMA
PCIMA
PCIMC
CDSPA
CPCIA
CCNT
−
PCI interrupt source register
PCI interrupt enable register
DSP master address register
PCI master address register
PCI master control register
Current DSP address register
Current PCI address register
Current byte count register
Reserved
01C0 000C
01C0 0010
01C0 0014
01C0 0018
01C0 001C
01C0 0020
01C0 0024
01C0 0028
01C0 002C − 01C1 FFEF
0x01C1 FFF0
0x01C1 FFF4
0x01C1 FFF8
0x01C1 FFFC
01C2 0000
–
Reserved
HSR
Host status register
HDCR
DSPP
−
Host-to-DSP control register
DSP page register
Reserved
EEADD
EEDAT
EECTL
–
EEPROM address register
EEPROM data register
EEPROM control register
Reserved
01C2 0004
01C2 0008
01C2 000C − 01C2 FFFF
01C3 0000
TRCTL
PCI transfer request control register
01C3 0004 − 01C3 FFFF
–
Reserved
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
EDMA channel synchronization events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 18 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the C6411 device, the association of an event to a channel is fixed; each of the EDMA
channels has one specific event associated with it. These specific events are captured in the EDMA event
registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The
priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter
RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access
(EDMA) Controller Reference Guide (literature number SPRU234).
†
Table 18. TMS320C6411 EDMA Channel Synchronization Events
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0
1
DSP_INT
TINT0
HPI/PCI-to-DSP interrupt
Timer 0 interrupt
2
TINT1
Timer 1 interrupt
3
SD_INT
EMIF SDRAM timer interrupt
GPIO event 4/External interrupt pin 4
GPIO event 5/External interrupt pin 5
GPIO event 6/External interrupt pin 6
GPIO event 7/External interrupt pin 7
GPIO event 0
4
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
GPINT0
5
6
7
8
9
GPINT1
GPIO event 1
10
11
12
13
14
15
16−18
19
20−47
48
49
50
51
52
53
54
55
56−63
GPINT2
GPIO event 2
GPINT3
GPIO event 3
XEVT0
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
None
REVT0
XEVT1
REVT1
–
TINT2
Timer 2 interrupt
–
None
GPINT8
GPIO event 8
GPINT9
GPIO event 9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
–
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
None
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
interrupt sources and interrupt selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 19. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 19. The interrupt source for interrupts 4−15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 19. C6411 DSP Interrupts
INTERRUPT
CPU
INTERRUPT
NUMBER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
SELECTOR
CONTROL
REGISTER
INTERRUPT SOURCE
†
†
†
†
‡
‡
‡
‡
‡
‡
‡
INT_00
INT_01
INT_02
INT_03
INT_04
INT_05
INT_06
INT_07
INT_08
INT_09
INT_10
−
−
RESET
NMI
−
−
−
−
Reserved
Reserved
Reserved. Do not use.
Reserved. Do not use.
−
−
MUXL[4:0]
MUXL[9:5]
MUXL[14:10]
MUXL[20:16]
MUXL[25:21]
MUXL[30:26]
MUXH[4:0]
00100
00101
00110
00111
01000
01001
00011
GPINT4/EXT_INT4 GPIO interrupt 4/External interrupt pin 4
GPINT5/EXT_INT5 GPIO interrupt 5/External interrupt pin 5
GPINT6/EXT_INT6 GPIO interrupt 6/External interrupt pin 6
GPINT7/EXT_INT7 GPIO interrupt 7/External interrupt pin 7
EDMA_INT
EMU_DTDMA
SD_INT
EDMA channel (0 through 63) interrupt
EMU DTDMA
EMIF SDRAM timer interrupt
EMU real-time data exchange (RTDX)
receive
‡
INT_11
MUXH[9:5]
01010
EMU_RTDXRX
‡
‡
‡
‡
INT_12
MUXH[14:10]
01011
00000
EMU_RTDXTX
DSP_INT
TINT0
EMU RTDX transmit
HPI/PCI-to-DSP interrupt
Timer 0 interrupt
INT_13
MUXH[20:16]
INT_14
MUXH[25:21]
00001
INT_15
MUXH[30:26]
00010
TINT1
Timer 1 interrupt
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
01100
XINT0
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
GPIO interrupt 0
01101
RINT0
01110
XINT1
01111
RINT1
10000
GPINT0
Reserved
Reserved
TINT2
10001
Reserved. Do not use.
Reserved. Do not use.
Timer 2 interrupt
10010
10011
10100 − 11111
Reserved
Reserved. Do not use.
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 19 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed
information on interrupt sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature
number SPRU646).
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
signal groups description
RESET
NMI
CLKIN
†
‡
‡
‡
‡
CLKOUT4/GP1
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
Reset and
Interrupts
†
CLKOUT6/GP2
Clock/PLL
CLKMODE0
PLLV
RSV
RSV
RSV
RSV
RSV
RSV
TMS
TDO
TDI
TCK
Reserved
•
•
•
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
IEEE Standard
1149.1
(JTAG)
Emulation
RSV
RSV
RSV
Peripheral
Control and
Configuration
PCI_EN
LEND
BOOTMODE [1:0]
ECLKIN_SEL[1:0]
EEAI
HD5/AD5
Control/Status
‡
§
GP7/EXT_INT7
GP15/PRST
‡
§
§
GP6/EXT_INT6
GP14/PCLK
‡
GP5/EXT_INT5
GP13/PINTA
‡
§
GP4/EXT_INT4
GP12/PGNT
GPIO
§
GP3
GP11/PREQ
†
§
CLKOUT6/GP2
GP10/PCBE3
†
§
CLKOUT4/GP1
GP9/PIDSEL
GP0
GP8
General-Purpose Input/Output (GPIO) Port
†
These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use
these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and
configured. For more details, see the Device Configurations section of this data sheet.
‡
§
These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
These GPIO pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with both the GPIO
and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 3. CPU and Peripheral Signals
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
signal groups description (continued)
32
Data
ED[31:0]
ECLKIN
ECLKOUT1
CE3
CE2
ECLKOUT2
SDCKE
Memory Map
Space Select
External
Memory I/F
Control
ARE/SDCAS/SADS/SRE
CE1
CE0
AOE/SDRAS/SOE
AWE/SDWE/SWE
ARDY
20
Address
EA[22:3]
SOE3
PDT
BE3
BE2
BE1
BE0
Byte Enables
HOLD
Bus
Arbitration
HOLDA
BUSREQ
EMIF (32-bit)
Figure 4. Peripheral Signals
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
signal groups description (continued)
†
HPI
(Host-Port Interface)
32
Data
HD[31:0]/AD[31:0]
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Register Select
Control
Half-Word
Select
HHWIL/PTRDY
(HPI16 ONLY)
HINT/PFRAME
32
HD[31:0]/AD[31:0]
Data/Address
Clock
GP14/PCLK
GP9/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
GP13/PINTA
HAS/PPAR
GP15/PRST
GP10/PCBE3
HR/W/PCBE2
HDS2/PCBE1
PCBE0
Command
Byte Enable
Control
HRDY/PIRDY
HCNTL0/PSTOP
HHWIL/PTRDY
GP12/PGNT
GP11/PREQ
Arbitration
HDS1/PSERR
HCS/PPERR
Error
XSP_DO
XSP_CS
XSP_CLK
XSP_DI
Serial
EEPROM
‡
PCI Interface
†
‡
These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins,
see the Device Configurations section of this data sheet.
These PCI pins (excluding PCBE0 , XSP_DO, XSP_CLK, XSP_DI, and XSP_CS) are muxed with the HPI or GPIO peripherals. By
default, these signals function as HPI and no function, respectively. For more details on these muxed pins, see the Device
Configurations section of this data sheet.
Figure 4. Peripheral Signals (Continued)
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
signal groups description (continued)
McBSP1
Transmit
McBSP0
Transmit
CLKX0
FSX0
DX0
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKR0
FSR0
Receive
Clock
Receive
Clock
DR0
CLKS0
CLKS1
McBSPs
(Multichannel Buffered
Serial Ports)
TOUT1
TOUT0
TINP0
Timer 0
Timers
Timer 1
TINP1
TOUT2
TINP2
Timer 2
Figure 4. Peripheral Signals (Continued)
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
DEVICE CONFIGURATIONS
The C6411 peripheral selections and other device configurations are determined by external pullup/pulldown
resistors on the following pins (all of which are latched during device reset):
D peripherals selection
−
PCI_EN
D other device configurations
−
−
−
−
−
LEND
BOOTMODE [1:0]
ECLKIN_SEL[1:0]
EEAI
HD5/AD5
peripherals selection
Some C6411 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,
general-purpose input/output pins GP[15:9], and PCI). Other C6411 peripherals (i.e., EMIF, three Timers, two
McBSPs, and the GP[8:0] pins), are always available.
D
HPI/GP[15:9] versus PCI
The PCI_EN pin is latched at reset. This pin determines the HPI/GP[15:9] versus the PCI peripheral
selection, summarized in Table 20.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
DEVICE CONFIGURATIONS (CONTINUED)
Table 20. PCI_EN Peripheral Selection (HPI/GP[15:9] or PCI)
PERIPHERALS SELECTED
PCI_EN Pin
[AA4]
†
HPI
GP[15:9]
PCI
DESCRIPTION
[default] HPI is enabled, GP[15:9] pins can be programmed as GPIO, PCI is
disabled.
This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI
pins (PCBE0, XSP_DO, XSP_DI, XSP_CLK, and XSP_CS) are tied-off (Hi-Z).
Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper
software configuration of the GPIO enable (GPxEN) and direction (GPxDIR)
registers (for more details, see Table 22).
0
√
√
PCI is enabled, HPI/GP[15:9] are disabled.
This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed
GPIO/PCI pins function as PCI pins (for more details, see Table 22).
1
√
Auto-initialization through PCI EEPROM or initialization via specified PCI default
values is controlled by the EEAI pin, see Table 21.
†
The PCI_EN pin is latched at reset and must be driven valid at all times and the user must not switch values throughout device operation.
other device configurations
Table 21 describes the C6411 device configuration pins, which are set up via external pullup/pulldown resistors
through the specified pins. For more details on these device configuration pins, see the Terminal Functions table
and the Debugging Considerations section.
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
DEVICE CONFIGURATIONS (CONTINUED)
Table 21. Device Configuration Pins (LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5)
CONFIGURATION
NO.
FUNCTIONAL DESCRIPTION
PIN
Device Endian mode (LEND)
LEND
E16
0
1
–
−
System operates in Big Endian mode
System operates in Little Endian mode (default)
Bootmode [1:0]. Default is reserved. External pullup and/or pulldown resistors must be used to select a
valid bootmode configuration.
[D18,
C18]
00 – No boot
01 − HPI boot
BOOTMODE[1:0]
ECLKIN_SEL[1:0]
10 − Reserved
11 − EMIF 8-bit ROM boot with default timings (default mode)
EMIF input clock select
Clock mode select for EMIF (ECLKIN_SEL[1:0])
00 – ECLKIN (default mode)
01 − CPU/4 Clock Rate
[B18,
A18]
10 − CPU/6 Clock Rate
11 − Reserved
PCI EEPROM Auto-Initialization (EEAI)
PCI auto-initialization via external EEPROM
0
1
−
−
PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified
PCI default values (default).
PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured
through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
EEAI
B17
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral
Component Interconnect (PCI) Reference Guide (literature number SPRU581).
HPI configuration bus width (HPI_WIDTH)
0
−
HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the Hi-Z state.)
HD5/AD5
Y1
1
−
HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
DEVICE CONFIGURATIONS (CONTINUED)
multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of
these pins are configured by software, and the others are configured by external pullup/pulldown resistors only
at reset. Those muxed pins that are configured by software can be programmed to switch functionalities at any
time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only
one peripheral has primary control of the function of these pins after reset. Table 22 identifies the multiplexed
pins on the C6411 device; shows the default (primary) function and the default settings after reset; and describes
the pins, registers, etc. necessary to configure specific multiplexed functions.
debugging considerations
It is recommended that external connections be provided to device configuration pins, including CLKMODE0,
LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0]. EEAI, HD5/AD5, and PCI_EN. Although internal pullup/pulldown
resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and
flexibility in switching operating modes.
Internal pullup/pulldown resistors also exist on specified reserved (RSV) pins. Do not oppose the internal
pullup/pulldown resistors, unless otherwised noted, on these RSV pins.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
DEVICE CONFIGURATIONS (CONTINUED)
†
Table 22. C6411 Device Multiplexed Pins
MULTIPLEXED PINS
NAME
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
NO.
These pins are software-configurable.
To use these pins as GPIO pins, the
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO Direction Register must be
properly configured.
CLKOUT4/GP1
AE6
CLKOUT4
GP1EN = 0 (disabled)
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
CLKOUT6/GP2
AD6
CLKOUT6
GP2EN = 0 (disabled)
GP9/PIDSEL
GP10/PCBE3
GP11/PREQ
M3
L2
F1
J3
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO Direction Register must be
properly configured.
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)
†
GP12/PGNT
None
GP13/PINTA
G4
F2
G3
‡
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
GP14/PCLK
GP15/PRST
HD[31:0]/AD[31:0]
HAS/PPAR
HD[31:0]
HAS
T3
R1
T4
T1
T2
P1
R3
R4
R2
P4
HCNTL1/PDEVSEL
HCNTL0/PSTOP
HDS1/PSERR
HDS2/PCBE1
HR/W/PCBE2
HHWIL/PTRDY
HINT/PFRAME
HCS/PPERR
HRDY/PIRDY
HCNTL1
HCNTL0
HDS1
By default, HPI is enabled upon reset
(PCI is disabled).
To enable the PCI peripheral an external
pullup resistor (1 kΩ) must be provided
on the PCI_EN pin (setting PCI_EN = 1
at reset and keeping valid “1” after
reset).
†
PCI_EN = 0 (disabled)
HDS2
HR/W
HHWIL (HPI16 only)
HINT
HCS
HRDY
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the
on-chip PLL.
CLKIN
H4
I
IPD
Clock output at 1/4 of the device speed
(O/Z) [default] or this pin can be pro-
grammed as a GPIO 1 pin (I/O/Z).
§
§
CLKOUT4/GP1
AE6
I/O/Z
IPD
Clock output at 1/6 of the device speed
(O/Z) [default] or this pin can be pro-
grammed as a GPIO 2 pin (I/O/Z).
CLKOUT6/GP2
AD6
I/O/Z
IPD
†
‡
All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
CLOCK/PLL CONFIGURATION (CONTINUED)
Clock mode select
•
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass) [default] or
x6.
For more details on the CLKMODE0 pin and the PLL multiply factors, see the Clock PLL
section of this data sheet.
CLKMODE0
H2
J6
I
IPD
¶
#
A
PLLV
PLL voltage supply
JTAG EMULATION
TMS
TDO
TDI
AB16
AE19
AF18
AF16
I
IPU
IPU
IPU
IPU
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet.
TRST
AB15
I
IPD
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
AC18
AD18
AE18
AC17
AF17
AD17
AE17
AC16
AD16
AE16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 11. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation [1:0] pins
•
Select the device functional mode of operation
EMU[1:0]
Operation
00
01
10
11
Boundary Scan/Normal Mode (see Note)
Reserved
Reserved
Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet)
EMU1
EMU0
AC15
AF15
I/O/Z
IPU
Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The
DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for
either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown
(IPD) on the TRST signal must not be opposed in order to operate in Normal mode.
For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resister.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
A = Analog signal (PLL Filter)
†
‡
§
¶
#
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NAME
NO.
DEVICE CONFIGURATION
Device Endian mode
LEND
E16
I/O/Z
I/O/Z
IPU
LEND:
0
1
–
−
Big Endian
Little Endian (default mode)
Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor
pullup/pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
§
HD5/AD5
Y1
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals. For more details, see the Device Configurations section of this data sheet.
PCI_EN
EEAI
AA4
B17
I
IPD
IPD
PCI EEPROM Auto-Initialization (EEAI) via external EEPROM
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
I/O/Z
EEAI: 0
1
−
−
PCI auto-initialization through EEPROM is disabled (default).
PCI auto-initialization through EEPROM is enabled.
Boot mode. Default is reserved. External pullup and/or pulldown resistors must be used to
select a valid bootmode configuration.
BOOTMODE1
BOOTMODE0
D18
C18
IPU
IPD
BOOTMODE[1:0]: 00 – No boot
01 − HPI boot
I/O/Z
I/O/Z
10 − Reserved
11 − EMIF 8-bit ROM boot with default timings (default mode)
EMIF clock mode select
ECLKIN_SEL1
ECLKIN_SEL0
B18
A18
ECLKIN_SEL[1:0]: 00 – ECLKIN (default mode)
01 − CPU/4 Clock Rate
IPD
10 − CPU/6 Clock Rate
11 − Reserved
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
B4
I
Device reset
NMI
I
IPD
IPU
Nonmaskable interrupt, edge-driven (rising edge)
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
AF4
AD5
AE5
AF5
G3
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
default after reset setting is GPIO enabled as input-only.
•
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently
selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
I/O/Z
§
GP15/PRST
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
F2
§
GP13/PINTA
G4
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
GPIO 3 pin (I/O/Z).
§
§
GP12/PGNT
J3
I/O/Z
GP11/PREQ
F1
§
GP10/PCBE3
L2
§
GP9/PIDSEL
GP3
M3
AC6
IPD
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
§
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED)
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)
[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)
signal (output only).
GP0
AF6
I/O/Z
IPD
This pin has no function at default [default] or this pin can be programmed as a GPIO 8 pin
(I/O/Z).
GP8
AE4
AD6
AE6
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
§
§
CLKOUT6/GP2
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
CLKOUT4/GP1
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
HINT/
PFRAME
R4
R1
T4
R3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
§
HCNTL1/
PDEVSEL
Host control − selects between control, address, or data registers (I) [default] or PCI device
select (I/O/Z).
§
HCNTL0/
PSTOP
Host control − selects between control, address, or data registers (I) [default] or PCI stop
(I/O/Z)
§
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
§
HHWIL/PTRDY
§
HR/W/PCBE2
P1
T3
R2
T1
T2
P4
J2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
Host address strobe (I) [default] or PCI parity (I/O/Z)
§
HAS/PPAR
§
HCS/PPERR
Host chip select (I) [default] or PCI parity error (I/O/Z)
§
HDS1/PSERR
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
§
HDS2/PCBE1
§
HRDY/PIRDY
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
HD31/AD31
HD30/AD30
HD29/AD29
HD28/AD28
HD27/AD27
HD26/AD26
HD25/AD25
HD24/AD24
HD23/AD23
HD22/AD22
HD21/AD21
HD20/AD20
HD19/AD19
HD18/AD18
HD17/AD17
HD16/AD16
HD15/AD15
K3
J1
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z)
K4
K2
L3
As HPI data bus (PCI_EN pin = 0)
•
•
Used for transfer of data, address, and control
Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor
K1
L4
pullup/pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
L1
I/O/Z
M4
M2
N4
M1
N5
N1
P5
U4
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
As PCI data-address bus (PCI_EN pin = 1)
•
Used for transfer of data and address
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NAME
NO.
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) (CONTINUED)
§
§
§
HD14/AD14
HD13/AD13
HD12/AD12
U1
U3
Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z)
U2
§
As HPI data bus (PCI_EN pin = 0)
HD11/AD11
V4
V1
•
•
Used for transfer of data, address, and control
Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-kΩ resistor
§
HD10/AD10
§
§
§
§
§
§
§
§
§
§
HD9/AD9
HD8/AD8
HD7/AD7
HD6/AD6
HD5/AD5
HD4/AD4
HD3/AD3
HD2/AD2
HD1/AD1
HD0/AD0
V3
pullup/pulldown resistor on the HD5 pin:
V2
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
W2
W4
Y1
I/O/Z
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
Y3
Y2
As PCI data-address bus (PCI_EN pin = 1)
Y4
•
Used for transfer of data and address
AA1
AA3
W3
AD1
§
PCBE0
XSP_CS
I/O/Z
O
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
IPD
IPD
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface clock (O).
XSP_CLK
AC2
I/O/Z
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the
serial PROM.
XSP_DI
AB3
I
IPU
IPU
This pin has no function at default [default] or when PCI is enabled (PCI_EN = 1), this pin is the
PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the
serial PROM.
XSP_DO
AA2
O/Z
§
GP15/PRST
G3
F2
G4
J3
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
§
GP13/PINTA
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
§
GP12/PGNT
GP11/PREQ
I/O/Z
§
F1
L2
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
§
GP10/PCBE3
§
GP9/PIDSEL
M3
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
§
EMIF (32-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
PDT
L26
K23
K24
K25
M25
M26
L23
L24
M22
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIF memory space enables
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
EMIF byte-enable control
•
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF peripheral data transfer, allows direct transfer between external peripherals
§
EMIF (32-BIT) − BUS ARBITRATION
HOLDA
HOLD
N22
V23
P22
O
I
IPU
IPU
IPU
EMIF hold-request-acknowledge to the host
EMIF hold request from the host
EMIF bus request output
BUSREQ
O
§
EMIF (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIF external input clock. The EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) is
selected at reset via the pullup/pulldown resistors on the ECLKIN_SEL[1:0] pins.
AECLKIN is the default for the EMIF input clock.
ECLKIN
H25
I
IPD
EMIF output clock 2. Programmable to be EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6
clock) frequency divided-by-1, -2, or -4.
ECLKOUT2
ECLKOUT1
J23
J26
O/Z
O/Z
IPD
IPD
EMIF output clock 1 at EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock)
frequency.
EMIF asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
ARE/
SDCAS/
SADS/SRE
•
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between SADS and SRE:
J25
J24
O/Z
O/Z
IPU
IPU
If RENEN = 0, then the SADS/SRE signal functions as the SADS signal.
If RENEN = 1, then the SADS/SRE signal functions as the SRE signal.
AOE/
SDRAS/
SOE
EMIF asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
AWE/
SDWE/
SWE
EMIF asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
K26
L25
O/Z
O/Z
IPU
IPU
EMIF SDRAM clock-enable (used for self-refresh mode).
SDCKE
•
If SDRAM is not in system, SDCKE can be used as a general-purpose output.
SOE3
ARDY
R22
L22
O/Z
I
IPU
IPU
EMIF synchronous memory output-enable for CE3 (for glueless FIFO interface)
Asynchronous memory ready input
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
§
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NAME
NO.
§
EMIF (32-BIT) − ADDRESS
EA22
T22
V24
V25
V26
U23
U24
U25
U26
T25
T26
R23
R24
P23
P24
P26
N23
N24
N26
M23
M24
EA21
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
EMIF external address (word address)
Note: EMIF address numbering for the C6411 device starts with EA3 to maintain signal name
compatibility with other C64x devices (e.g., C6414, C6415, and C6416) [see the 64-bit EMIF
addressing scheme in the TMS320C6000 DSP External Memory Interface (EMIF) Reference
Guide (literature number SPRU266)].
O/Z
IPD
EA8
EA7
EA6
EA5
EA4
EA3
§
EMIF (32-bit) − DATA
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
C26
D26
D25
E25
E24
E26
F24
F25
F23
F26
G24
G25
G23
G26
H23
H24
C19
D19
I/O/Z
IPU
EMIF external data
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
§
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
§
EMIF (32-bit) − DATA (CONTINUED)
ED13
A20
D20
B20
C20
A21
D21
B21
C21
A22
C22
B22
B23
A23
A24
ED12
ED11
ED10
ED9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
I/O/Z
IPU
EMIF external data
TIMER 2
Timer 2 or general-purpose output
Timer 2 or general-purpose input
TIMER 1
TOUT2
TINP2
A4
C5
O/Z
I
IPD
IPD
TOUT1
TINP1
B5
A5
O/Z
I
IPD
IPD
Timer 1 or general-purpose output
Timer 1 or general-purpose input
TIMER 0
TOUT0
TINP0
D6
C6
O/Z
I
IPD
IPD
Timer 0 or general-purpose output
Timer 0 or general-purpose input
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
McBSP1 external clock source (as opposed to internal)
McBSP1 receive clock
CLKS1
CLKR1
CLKX1
DR1
AC8
AC10
AB12
AF11
AB11
AC9
I
I/O/Z
I/O/Z
I
McBSP1 transmit clock
McBSP1 receive data
DX1
O/Z
I/O/Z
I/O/Z
McBSP1 transmit data
FSR1
FSX1
McBSP1 receive frame sync
AB13
McBSP1 transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
CLKR0
CLKX0
DR0
F4
D1
E1
D2
E2
C1
E3
I
IPD
IPD
IPD
IPU
IPU
IPD
IPD
McBSP0 external clock source (as opposed to internal)
McBSP0 receive clock
I/O/Z
I/O/Z
I
McBSP0 transmit clock
McBSP0 receive data
DX0
O/Z
I/O/Z
I/O/Z
McBSP0 transmit data
FSR0
FSX0
McBSP0 receive frame sync
McBSP0 transmit frame sync
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
§
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NAME
NO.
RESERVED FOR TEST
AD11
AD12
A16
D15
G14
H7
For proper device operation, these RSV pins must be externally pulled
down to ground with a 10-kΩ resistor.
RSV
RSV
For proper device operation, these RSV pins must be externally pulled up to DV
with a 1-kΩ resistor.
DD
IPD
N20
P7
RSV
Reserved. These pins must be connected directly to CV
for proper device operation.
DD
Y13
R6
RSV
RSV
Reserved. This pin must be connected directly to DV
for proper device operation.
Reserved (leave unconnected, do not connect to power or ground)
DD
A3
A6
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
A7
A9
A10
A11
A12
A13
A14
A15
A17
B6
B7
B8
RSV
Reserved (leave unconnected, do not connect to power or ground)
B9
B10
B11
B12
B15
B16
B19
C7
C8
C9
C10
C11
C12
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
RESERVED FOR TEST (CONTINUED)
‡
NO.
C13
C14
C15
C16
C17
D7
IPU
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPD
IPD
IPU
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPD
D8
D9
D10
D11
D12
D13
D14
D16
D17
E11
E12
E13
E14
E15
G1
RSV
Reserved (leave unconnected, do not connect to power or ground)
G2
H3
J4
K6
N3
P3
R25
R26
T23
T24
W23
W24
W25
Y23
Y24
Y25
Y26
AA23
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NAME
NO.
RESERVED FOR TEST (CONTINUED)
AA24
AA25
AA26
AB1
IPU
IPU
IPU
IPD
IPD
AB2
AB14
AB24
AB25
AB26
AC1
IPU
IPU
IPU
IPD
AC11
AC12
AC13
AC14
AC19
AC20
AC21
AC25
AC26
AD7
IPU
IPU
IPU
IPU
IPU
RSV
Reserved (leave unconnected, do not connect to power or ground)
AD8
AD9
AD10
AD13
AD14
AD15
AD19
AD20
AD21
AD22
AD26
AE7
IPU
IPU
IPU
IPU
IPU
AE8
AE9
AE10
AE11
AE12
AE15
AE20
AE21
IPU
IPU
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
RESERVED FOR TEST (CONTINUED)
‡
NO.
AE22
AE23
AF3
IPU
IPU
IPD
AF7
AF9
AF10
AF12
AF13
AF14
AF20
AF21
AF22
AF23
AF24
RSV
Reserved (leave unconnected, do not connect to power or ground)
IPU
IPU
IPU
IPU
IPU
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used, unless otherwise noted.)
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢑ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢒ
ꢀ
ꢎ
ꢋ
ꢓꢋ
ꢀꢔ
ꢕ
ꢂ
ꢋ
ꢓꢒ
ꢔ
ꢕ
ꢐ
ꢖ
ꢑ
ꢆ
ꢍ
ꢂ
ꢂ
ꢑ
ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS
NAME
NO.
A2
A25
B1
B14
B26
E7
E8
E10
E17
E19
E20
F3
F9
F12
F15
F18
G5
G22
H5
H22
J21
K5
3.3-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
DV
S
DD
K22
L5
M5
M6
M21
N2
P25
R5
R21
T5
U5
U22
V6
V21
W5
W22
Y5
Y22
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NO.
AA9
AA12
AA15
AA18
AB7
AB8
AB10
AB17
AB19
AB20
AE1
AE13
AE26
AF2
AF25
A1
3.3-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
DV
DD
A26
B2
B25
C3
S
C24
D4
D23
E5
E22
F6
F7
1.2-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
CV
DD
F20
F21
G6
G7
G8
G10
G11
G13
G16
G17
G19
G20
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NAME
NO.
G21
H20
K7
K20
L7
L20
N7
P20
T7
T20
U7
U20
W7
W20
Y6
Y7
Y8
Y10
Y11
Y14
Y16
Y17
Y19
Y20
Y21
AA6
AA7
AA20
AA21
AB5
AB22
AC4
AC23
AD3
AD24
AE2
AE25
AF1
AF26
1.2-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
CV
S
DD
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
GROUND PINS
A8
A19
B3
B13
B24
C2
C4
C23
C25
D3
D5
D22
D24
E4
E6
E9
E18
E21
E23
F5
V
SS
GND
Ground pins
F8
F10
F11
F13
F14
F16
F17
F19
F22
G9
G12
G15
G18
H1
H6
H21
H26
J5
J7
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢑ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢋ
ꢒ
ꢀ
ꢎ
ꢋ
ꢓꢋ
ꢀꢔ
ꢕ
ꢂ
ꢋ
ꢓꢒ
ꢔ
ꢕ
ꢐ
ꢖ
ꢑ
ꢆ
ꢍ
ꢂ
ꢂ
ꢑ
ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NAME
NO.
J20
J22
K21
L6
L21
M7
M20
N6
N21
N25
P2
P6
P21
R7
R20
T6
T21
U6
U21
V5
V
SS
GND
Ground pins
V7
V20
V22
W1
W6
W21
W26
Y9
Y12
Y15
Y18
AA5
AA8
AA10
AA11
AA13
AA14
AA16
AA17
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NO.
AA19
AA22
AB4
AB6
AB9
AB18
AB21
AB23
AC3
AC5
AC22
AC24
AD2
V
SS
GND
Ground pins
AD4
AD23
AD25
AE3
AE14
AE24
AF8
AF19
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 DSP family member devices, including documentation. See
this document for further information on TMS320 DSP documentation or any TMS320 DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry.
To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
device support
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLZ) and the temperature range (for example, blank is the default commercial temperature
range). Figure 5 provides a legend for reading the complete device name for any TMS320C6000 DSP
platform member.
The ZLZ package, like the GLZ package, is a 532-pin plastic BGA only with lead-free balls. The ZLZ package
type is available upon request. For device part numbers and further ordering information for TMS320C6411 in
the GLZ and ZLZ package types, see the TI website (http://www.ti.com) or contact your TI sales representative.
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
device and development-support tool nomenclature (continued)
(
)
TMS 320
C 6411 GLZ
PREFIX
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
†
PACKAGE TYPE
GLZ = 532-pin plastic BGA
ZLZ = 532-pin plastic BGA, with lead free balls
DEVICE FAMILY
32 or 320 = TMS320t DSP family
‡
DEVICE
C64x DSP:
6411
6411A
TECHNOLOGY
C = CMOS
†
‡
BGA
=
Ball Grid Array
For the actual device part number (P/N) and ordering information, see the TI website (www.ti.com).
Figure 5. TMS320C6411 DSP Device Nomenclature
For additional information, see the TMS320C6411 Digital Signal Processor Silicon Errata (literature number
SPRZ194)
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s reference guides for all devices and tools;
technical briefs; development-support tools; on-line help; and hardware and software applications. The
following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital
signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW
architecture.
The TMS320C6414, TMS320C6415, and TMS320C6416 Fixed-Point Digital Signal Processors data sheet
(literature number SPRS146) describes the features of the TMS320C6414, TMS320C6415, and
TMS320C6416 DSP devices and provides pinouts, electrical specifications, and timings.
The TMS320C6414, TMS320C6415, and TMS320C6416 Digital Signal Processors Silicon Errata (literature
number SPRZ011) describes the known exceptions to the functional specifications for the TMS320C6414,
TMS320C6415, and TMS320C6416 DSP devices.
The TMS320C6411 Digital Signal Processor Silicon Errata (literature number SPRZ194) describes the known
exceptions to the functional specifications for particular silicon revisions of the TMS320C6411 device.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
For more detailed information on the device compatibility and similarities/differences among the C6211, C6411,
C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414,
TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718) and How To Begin
Development Today With the TMS320C6411 DSP application report (literature number SPRA374).
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 6
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of suppy voltage and operating case temperature table and the input and output clocks electricals
section). Table 23 lists some examples of compatible CLKIN external clock sources:
Table 23. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER
MANUFACTURER
JITO-2
STA series, ST4100 series
SG-636
Fox Electronix
SaRonix Corporation
Epson America
Oscillators
342
Corning Frequency Control
PLL
ICS525-02
Integrated Circuit Systems
Spread Spectrum Clock Generator
MK1714
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
clock PLL (continued)
3.3 V
CPU Clock
C1
C2
EMI
/2
Configuration Bus
filter
10 µF 0.1 µF
/8
/4
/6
Timer Internal Clock
PLLV
CLKOUT4,
McBSP Internal Clock
CLKMODE0
(See Table 24)
CLKOUT6
PLLMULT
PLL x6
00 01 10
ECLKIN_SEL[1:0]
CLKIN
PLLCLK
1
0
/4
/2
ECLKIN
EK2RATE
(GBLCTL.[19,18])
EMIF
00 01 10
Internal to C6411
(For the PLL Options, CLKMODE0 Pin Setup, and
PLL Clock Frequency Ranges, see Table 24.)
ECLKOUT1 ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
.
DD
Figure 6. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
†‡
Table 24. TMS320C6411 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ and ZLZ PACKAGE − 23 x 23 mm BGA
CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
TYPICAL
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
CLKMODE0
LOCK TIME
§
(µs)
0
1
Bypass (x1) [default]
x6
30−75.75
30−50.5
30−75.75
180−303
7.5−18.93
45−75.75
5−12.62
30−50.5
N/A
75
†
‡
These clock frequency range values are applicable to a C6411−300 speed device.
Use an external pullup resistor on the CLKMODE0 pin to set the C6411 device to the valid PLL multiply clock mode (x6). With an internal pulldown
resistor on the CLKMODE0 pin, the default clock mode is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
§
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
general-purpose input/output (GPIO)
To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
GPxDIR =
GPxDIR =
1
0
1
GP[x] pin is enabled
GP[x] pin is an input
GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 7 shows the GPIO enable bits in the GPEN register for the C6411 device. To use any of the GPx pins
as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default
values are device-specific, so refer to Figure 7 for the C6411 default configuration.
31
24 23
Reserved
R-0
16
15
GP15 GP14 GP13 GP12 GP11 GP10
EN EN EN EN EN EN
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP9
EN
GP8
EN
GP7
EN
GP6
EN
GP5
EN
GP4
EN
GP3
EN
GP2
EN
GP1
EN
GP0
EN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 7. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 8 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is
an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By
default, all the GPIO pins are configured as input pins.
31
24 23
Reserved
R-0
16
15
14
13
12
11
9
8
6
4
3
1
0
10
7
5
2
GP15 GP14 GP13 GP12 GP11 GP10
DIR DIR DIR DIR DIR DIR
GP9
DIR
GP8
DIR
GP7
DIR
GP6
DIR
GP5
DIR
GP4
DIR
GP3
DIR
GP2
DIR
GP1
DIR
GP0
DIR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 8. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
power-down mode logic
Figure 9 shows the power-down mode logic on the C6411.
CLKOUT4
CLKOUT6
Internal Clock Tree
Clock
Distribution
and Dividers
PD1
PD2
IFR
Power-
Clock
PLL
Internal
Peripherals
IER
Down
Logic
CSR
PWRD
CPU
PD3
TMS320C6411
CLKIN
RESET
†
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
†
Figure 9. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 25.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
31
16
8
15
14
13
Enabled
12
11
10
9
Enable or
Non-Enabled
Interrupt Wake
Reserved
R/W-0
PD3
PD2
PD1
Interrupt Wake
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 10. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account
for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect
upon PD1 mode termination by an enabled interrupt.
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PD2 and PD3 modes can only be aborted by device reset. Table 25 summarizes all the power-down modes.
Table 25. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
MODE
WAKE-UP METHOD
—
EFFECT ON CHIP’S OPERATION
000000
No power-down
PD1
—
CPU halted (except for the interrupt logic)
001001
Wake by an enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
Wake by an enabled or
non-enabled interrupt
010001
PD1
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
†
PD2
011010
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
†
PD3
011100
Wake by a device reset
All others
Reserved
—
—
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
C64x power-down mode with an emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP
reset will be required to get the DSP out of PD2/PD3.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 11).
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
I/O Supply
DV
CV
DD
DD
Schottky
Diode
C6000
DSP
Core Supply
V
SS
GND
Figure 11. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply
and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic
inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest
to the power pins. Medium bypass caps (220 pF or as large as can be obtained in a small package) should be
next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total) be placed
immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the “exterior”.
Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the
order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per supply
(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any
component, verification of capacitor availability over the product’s production lifetime should be considered.
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
IEEE 1149.1 JTAG compatibility statement
The TMS320C6411 DSP requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are
required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be released in
order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions
work correctly independent of current state of RESET.
For maximum reliability, the TMS320C6411 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly
initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of
JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST high before
attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode. For
more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320C6411 BSDL file contains information and constraints
regarding proper device operation while in Boundary Scan Mode.
EMIF device speed
The rated EMIF speed of this device only applies to the SDRAM interface when in a system that meets the
following requirements:
−
−
−
−
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
143-MHz SDRAM for 75-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above.
TI recommends utilizing the input/output buffer information specification (IBIS) models to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
bootmode
The C6411 device resets using the active-low signal RESET. While RESET is low, the device is held in reset
and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states
of device pins during reset. The release of RESET starts the processor running with the prescribed device
configuration and boot mode.
The C6411 has three types of boot modes:
D
Host boot
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as necessary
through the host interface, including internal configuration registers, such as those that control the EMIF or
other peripherals. For the C6411 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI
peripheral is used if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT
condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is
out of the “stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
D
D
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored
in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive
8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA
as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU
is released from the “stalled” state and starts running from address 0.
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage ranges: CV
DV
Input voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to DV
Output voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
DD
I
+ 0.5 V
IP
DD
O
(PCI), V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to DV
+ 0.5 V
OP
DD
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
MIN
1.14
3.14
0
NOM
1.2
3.3
0
MAX
1.26
3.46
0
UNIT
V
‡
CV
DV
Supply voltage, Core
Supply voltage, I/O
Supply ground
DD
DD
V
V
V
V
V
V
V
V
T
V
SS
High-level input voltage (except PCI)
Low-level input voltage (except PCI)
Input voltage (PCI)
2
V
IH
0.8
V
IL
−0.5
DV
DV
+ 0.5
V
IP
DD
DD
High-level input voltage (PCI)
Low-level input voltage (PCI)
0.5DV
DD
+ 0.5
V
IHP
ILP
OS
−0.5
0.3DV
DD
V
§
−1.0
§
4.3
Maximum voltage during overshoot/undershoot
Operating case temperature
V
0
90
_C
C
‡
Future variants of the C6411 DSP may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C641x devices.
§
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
High-level output voltage (except PCI)
High-level output voltage (PCI)
Low-level output voltage (except PCI)
Low-level output voltage (PCI)
DV
= MIN, = MAX
I
2.4
V
V
V
V
OH
DD
= −0.5 mA,
OH
DV
¶
I
= 3.3 V
0.9DV
DD
OHP
OL
OHP
DV
DD
= MAX
= MIN,
DD
= 1.5 mA,
I
0.4
OL
DV
¶
I
= 3.3 V
0.1DV
DD
OLP
OLP
DD
V = V
SS
to DV
no opposing internal
opposing internal
opposing internal
I
DD
DD
DD
10
uA
uA
uA
resistor
V = V
SS
to DV
I
50
100
150
I
I
Input current (except PCI)
‡
pullup resistor
V = V to DV
I
SS
−150
−100
−50
10
‡
pulldown resistor
§
I
I
Input leakage current (PCI)
0 < V < DV
,
DV
DD
= 3.3 V
uA
IP
IP DD
EMIF, CLKOUT4, CLKOUT6, EMUx
−16
mA
Timer, TDO, GPIO
(Excluding GP[15:9, 2, 1]), McBSP
−8
mA
High-level output current
OH
§¶
16
PCI/HPI
−0.5
mA
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, TDO, GPIO
(Excluding GP[15:9, 2, 1]), McBSP
8
mA
I
Low-level output current
Off-state output current
OL
¶
1.5
PCI/HPI
mA
uA
mA
mA
pF
I
I
I
V = DV
O DD
or 0 V
10
OZ
#
Core supply current
CV
DV
= 1.2 V, CPU clock = 300 MHz
= 3.3 V, CPU clock = 300 MHz
550
125
CDD
DDD
DD
DD
#
I/O supply current
Input capacitance
C
C
10
10
i
Output capacitance
pF
o
†
‡
§
¶
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
#
Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core
and I/O activity, refer to the TMS320C6411 Power Consumption Summary application report (literature number SPRA373).
recommended clock and control signal transition behavior
All clocks and control signals must transition between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 W
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 12. Test Load Circuit for AC Timing Measurements
The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate
the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX
IL
IH
OL
OHP
and V
PCI output clocks.
MIN for output clocks, V
MAX and V
MIN for PCI input clocks, and V
MAX and V
MIN for
OH
ILP
IHP
OLP
V
ref
= V MIN (or V
IH OH
MIN or
MIN)
V
MIN or V
IHP
OHP
V
ref
= V MAX (or V
IL OL
MAX or
MAX)
V
MAX or V
ILP
OLP
Figure 14. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 26 and Figure 15).
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 26. Board-Level Timings Example (see Figure 15)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
ECLKOUT
(Output from DSP)
1
ECLKOUT
(Input to External Device)
2
3
†
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
‡
Data Signals
(Output from External Device)
9
10
11
‡
Data Signals
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 15. Board-Level Input/Output Timings
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
INPUT AND OUTPUT CLOCKS
†‡§
timing requirements for CLKIN
(see Figure 16)
−300
PLL MODE x6
x1 (BYPASS)
NO.
UNIT
MIN
20
MAX
MIN
13.3
MAX
1
2
3
4
5
t
t
t
t
t
Cycle time, CLKIN
33.3
33.3
ns
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
Period jitter, CLKIN
0.4C
0.4C
0.45C
0.45C
5
1
0.02C
0.02C
J(CLKIN)
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
For more details on the PLL multiplier factor (x6), see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
1
5
4
2
CLKIN
3
4
Figure 16. CLKIN Timing
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡§
switching characteristics over recommended operating conditions for CLKOUT4
(see Figure 17)
−300
CLKMODE = x1, x6
MIN MAX
175
NO.
PARAMETER
UNIT
1
2
3
4
t
t
t
t
Period jitter, CLKOUT4
0
ps
ns
ns
ns
J(CKO4)
w(CKO4H)
w(CKO4L)
t(CKO4)
Pulse duration, CLKOUT4 high
Pulse duration, CLKOUT4 low
Transition time, CLKOUT4
2P − 0.7
2P − 0.7
2P + 0.7
2P + 0.7
1
†
‡
§
The reference points for the rise and fall transitions are measured at V
OL
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
MAX and V MIN.
OH
1
4
2
CLKOUT4
3
4
Figure 17. CLKOUT4 Timing
†‡§
switching characteristics over recommended operating conditions for CLKOUT6
(see Figure 18)
−300
CLKMODE = x1, x6
MIN MAX
175
NO.
PARAMETER
UNIT
1
2
3
4
t
t
t
t
Period jitter, CLKOUT6
0
ps
ns
ns
ns
J(CKO6)
w(CKO6H)
w(CKO6L)
t(CKO6)
Pulse duration, CLKOUT6 high
Pulse duration, CLKOUT6 low
Transition time, CLKOUT6
3P − 0.7
3P − 0.7
3P + 0.7
3P + 0.7
1
†
‡
§
The reference points for the rise and fall transitions are measured at V
OL
MAX and V MIN.
OH
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
1
4
2
CLKOUT6
3
4
Figure 18. CLKOUT6 Timing
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡§
timing requirements for ECLKIN
(see Figure 19)
−300
MIN
NO.
UNIT
MAX
¶
1
2
3
4
t
t
t
t
Cycle time, ECLKIN
7.5
16P
ns
ns
ns
ns
c(EKI)
Pulse duration, ECLKIN high
Pulse duration, ECLKIN low
Transition time, ECLKIN
3.38
3.38
w(EKIH)
w(EKIL)
t(EKI)
2
5
t
Period jitter, ECLKIN
0.02E
ns
J(EKI)
†
‡
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL IH
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
On the -300 device, 75-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. Minimum ECLKIN cycle times
must be met, even when ECLKIN is generated by an internal clock source.
1
5
4
2
ECLKIN
3
4
Figure 19. ECLKIN Timing
§#||
switching characteristics over recommended operating conditions for ECLKOUT1
(see Figure 20)
−300
MIN
NO.
PARAMETER
Period jitter, ECLKOUT1
UNIT
MAX
k
1
2
3
4
5
6
t
t
t
t
t
t
0
175
ps
ns
ns
ns
ns
ns
J(EKO1)
Pulse duration, ECLKOUT1 high
EH − 0.7 EH + 0.7
EL − 0.7 EL + 0.7
1
w(EKO1H)
w(EKO1L)
Pulse duration, ECLKOUT1 low
Transition time, ECLKOUT1
t(EKO1)
Delay time, ECLKIN high to ECLKOUT1 high
Delay time, ECLKIN low to ECLKOUT1 low
1
1
8
8
d(EKIH-EKO1H)
d(EKIL-EKO1L)
§
#
||
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
The reference points for the rise and fall transitions are measured at V MAX and V
MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns.
OL OH
kThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
ECLKIN
1
6
3
4
4
5
2
ECLKOUT1
Figure 20. ECLKOUT1 Timing
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡
switching characteristics over recommended operating conditions for ECLKOUT2
(see Figure 21)
−300
NO.
PARAMETER
Period jitter, ECLKOUT2
UNIT
MIN
MAX
§
1
2
3
4
5
6
t
t
t
t
t
t
0
175
ps
ns
ns
ns
ns
ns
J(EKO2)
Pulse duration, ECLKOUT2 high
0.5NE − 0.7
0.5NE − 0.7
0.5NE + 0.7
w(EKO2H)
w(EKO2L)
Pulse duration, ECLKOUT2 low
0.5NE + 0.7
Transition time, ECLKOUT2
1
8
8
t(EKO2)
Delay time, ECLKIN high to ECLKOUT2 high
Delay time, ECLKIN high to ECLKOUT2 low
1
1
d(EKIH-EKO2H)
d(EKIH-EKO2L)
†
‡
The reference points for the rise and fall transitions are measured at V
OL
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
N = the EMIF input clock divider; N = 1, 2, or 4.
MAX and V MIN.
OH
§
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
5
6
ECLKIN
1
3
4
4
2
ECLKOUT2
Figure 21. ECLKOUT2 Timing
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
ASYNCHRONOUS MEMORY TIMING
†‡
timing requirements for asynchronous memory cycles (see Figure 22 and Figure 23)
−300
NO.
UNIT
MIN
6.5
1
MAX
3
4
6
t
t
t
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
ns
ns
ns
ns
ns
su(EDV-AREH)
h(AREH-EDV)
Setup time, ARDY valid before ECLKOUTx high
3
su(ARDY-EKO1H)
Rev 1.1
Rev 2.0
1
7
t
Hold time, ARDY valid after ECLKOUTx high
h(EKO1H-ARDY)
1.3
†
‡
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
switching characteristics over recommended operating conditions for asynchronous memory
द
cycles
(see Figure 22 and Figure 23)
−300
MIN
NO.
PARAMETER
UNIT
MAX
7
1
2
t
t
t
t
t
t
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUTx high to ARE vaild
RS * E − 1.5
RS * E − 1.9
1
ns
ns
ns
ns
ns
ns
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
5
8
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUTx high to AWE vaild
WS * E − 1.7
WH * E − 1.8
1.3
9
10
7.1
‡
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
¶
E = ECLKOUT1 period in ns
Select signals for EMIF include: CEx, BE[3:0], EA[22:3], AOE; and for EMIF writes, include ED[31:0].
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
ECLKOUTx
CEx
2
2
1
1
1
BE[3:0]
BE
2
EA[22:3]
Address
3
4
2
ED[31:0]
1
5
Read Data
†
AOE/SDRAS/SOE
5
†
ARE/SDCAS/SADS/SRE
†
AWE/SDWE/SWE
7
7
6
6
ARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 22. Asynchronous Memory Read Timing
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Hold = 2
Strobe = 3
Not Ready
ECLKOUTx
CEx
9
9
8
8
8
8
BE[3:0]
BE
9
9
EA[22:3]
ED[31:0]
Address
Write Data
†
AOE/SDRAS/SOE
†
ARE/SDCAS/SADS/SRE
10
10
†
AWE/SDWE/SWE
7
7
6
6
ARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 23. Asynchronous Memory Write Timing
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING
timing requirements for programmable synchronous interface cycles (see Figure 24)
−300
NO.
UNIT
MIN
MAX
6
7
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
6.4
1.5
ns
ns
su(EDV-EKOxH)
h(EKOxH-EDV)
switching characteristics over recommended operating conditions for programmable
†
synchronous interface cycles (see Figure 24−Figure 26)
−300
NO.
PARAMETER
UNIT
MIN
MAX
9.7
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SADS/SRE valid
Delay time, ECLKOUTx high to, SOE valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SWE valid
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
9.7
3
1.3
4
9.7
5
1.3
1.3
1.3
8
9.7
9.7
9.7
9
10
11
12
1.3
1.3
9.7
†
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
−
−
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
READ latency = 2
ECLKOUTx
1
2
1
3
5
CEx
BE1
BE2
BE3
EA3
BE4
BE[3:0]
4
EA[22:3]
ED[31:0]
EA1
8
EA2
EA4
7
6
Q1
Q2
Q3
Q4
8
9
§
ARE/SDCAS/SADS/SRE
9
§
§
AOE/SDRAS/SOE
AWE/SDWE/SWE
†
‡
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
§
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
†‡
Figure 24. Programmable Synchronous Interface Read Timing (With Read Latency = 2)
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx
1
1
3
CEx
2
BE[3:0]
EA[22:3]
ED[31:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
EA1
10
Q1
10
11
8
8
§
ARE/SDCAS/SADS/SRE
AOE/SDRAS/SOE
§
12
12
§
AWE/SDWE/SWE
†
‡
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
§
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
†‡
Figure 25. Programmable Synchronous Interface Write Timing (With Write Latency = 0)
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
Write
Latency =
†
1
ECLKOUTx
1
1
3
CEx
2
BE[3:0]
BE1
BE2
EA2
BE3
EA3
Q2
BE4
EA4
Q3
5
4
EA[22:3]
ED[31:0]
EA1
10
10
11
8
Q1
Q4
8
§
§
ARE/SDCAS/SADS/SRE
AOE/SDRAS/SOE
12
12
§
AWE/SDWE/SWE
†
‡
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
§
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
†‡
Figure 26. Programmable Synchronous Interface Write Timing (With Write Latency = 1)
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 27)
−300
MIN MAX
5.4
NO.
UNIT
6
7
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
ns
ns
su(EDV-EKO1H)
2.5
h(EKO1H-EDV)
switching characteristics over recommended operating conditions for synchronous DRAM cycles
(see Figure 27−Figure 34)
−300
NO.
PARAMETER
UNIT
MIN
MAX
9.7
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SDCAS valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SDWE valid
Delay time, ECLKOUTx high to SDRAS valid
Delay time, ECLKOUTx high to SDCKE valid
Delay time, ECLKOUTx high to PDT valid
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-SDCKEV)
d(EKO1H-PDTV)
9.7
3
1.3
4
9.7
5
1.3
1.3
8
9.7
9.7
9
10
11
12
13
14
1.3
1.3
1.3
1.3
1.3
9.7
9.7
9.7
9.7
82
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
ECLKOUTx
CEx
1
1
2
3
BE[3:0]
BE1
BE2
BE3
BE4
4
5
5
5
Bank
EA[22:14]
EA[12:3]
4
Column
4
EA13
6
7
D2
ED[31:0]
D1
D3
D4
†
AOE/SDRAS/SOE
8
8
†
ARE/SDCAS/SADS/SRE
†
AWE/SDWE/SWE
PDTR/W
14
14
‡
PDT
†
‡
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
Figure 27. SDRAM Read Command (CAS Latency 3)
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE
ECLKOUTx
CEx
1
2
4
4
4
9
2
4
5
5
5
9
3
BE[3:0]
BE1
Bank
BE2
BE3
BE4
EA[22:14]
Column
EA[12:3]
EA13
10
ED[31:0]
D1
D2
D3
D4
†
AOE/SDRAS/SOE
8
8
†
ARE/SDCAS/SADS/SRE
11
11
†
AWE/SDWE/SWE
PDTR/W
14
14
‡
PDT
†
‡
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
Figure 28. SDRAM Write Command
84
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
ECLKOUTx
1
1
CEx
BE[3:0]
4
5
5
5
Bank Activate
EA[22:14]
EA[12:3]
4
Row Address
4
Row Address
EA13
ED[31:0]
12
12
†
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 29. SDRAM ACTV Command
DCAB
ECLKOUTx
1
1
CEx
BE[3:0]
EA[22:14, 12:3]
4
12
11
5
12
11
EA13
ED[31:0]
†
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 30. SDRAM DCAB Command
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC
ECLKOUTx
1
1
CEx
BE[3:0]
4
5
EA[22:14]
EA[12:3]
Bank
4
5
EA13
ED[31:0]
12
11
12
11
†
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 31. SDRAM DEAC Command
REFR
ECLKOUTx
1
1
CEx
BE[3:0]
EA[22:14, 12:3]
EA13
ED[31:0]
12
8
12
8
†
AOE/SDRAS/SSOE
†
†
ARE/SDCAS/SSADS
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 32. SDRAM REFR Command
86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS
ECLKOUTx
1
1
5
CEx
BE[3:0]
4
EA[22:3]
ED[31:0]
MRS value
12
8
12
8
†
AOE/SDRAS/SSOE
ARE/SDCAS/SSADS
†
11
11
†
AWE/SDWE/SSWE
†
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 33. SDRAM MRS Command
87
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
≥ TRAS cycles
End Self-Refresh
Self Refresh
ECLKOUTx
CEx
BE[3:0]
EA[22:14, 12:3]
EA13
ED[31:0]
†
AOE/SDRAS/SOE
†
ARE/SDCAS/SADS/SRE
†
AWE/SDWE/SWE
13
13
SDCKE
†
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 34. SDRAM Self-Refresh Timing
88
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOLD/HOLDA TIMING
†
timing requirements for the HOLD/HOLDA cycles (see Figure 35)
−300
NO.
UNIT
MIN MAX
3
t
Hold time, HOLD low after HOLDA low
E
ns
h(HOLDAL-HOLDL)
†
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA
†‡§
cycles
(see Figure 35)
−300
MIN
NO.
PARAMETER
UNIT
MAX
¶
1
2
4
5
6
7
t
t
t
t
t
t
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
Delay time, HOLD low to ECLKOUTx high impedance
Delay time, HOLD high to ECLKOUTx low impedance
2E
0
ns
ns
ns
ns
ns
ns
d(HOLDL-EMHZ)
2E
7E
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
d(HOLDL-EKOHZ)
d(HOLDH-EKOLZ)
2E
0
2E
¶
2E
2E
7E
†
‡
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE , SDCKE,
SOE3, and PDT.
§
¶
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
7
†
EMIF Bus
C6411
C6411
‡
ECLKOUTx
(EKxHZ = 0)
6
‡
ECLKOUTx
(EKxHZ = 1)
†
‡
EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[22:3], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE, SDCKE,
SOE3, and PDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
Figure 35. HOLD/HOLDA Timing
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 36)
−300
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Delay time, ECLKOUTx high to BUSREQ valid
0.6
7.1
ns
d(EKO1H-BUSRV)
ECLKOUTx
1
1
BUSREQ
Figure 36. BUSREQ Timing
90
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
RESET TIMING
†
timing requirements for reset (see Figure 37)
−300
UNIT
NO.
MIN
10P
250
MAX
‡
Width of the RESET pulse (PLL stable)
ns
µs
ns
ns
1
t
w(RST)
§
Width of the RESET pulse (PLL needs to sync up)
¶
#
4E or 4C
16
17
18
t
t
Setup time, boot configuration bits valid before RESET high
su(boot)
¶
Hold time, boot configuration bits valid after RESET high
||
4P
h(boot)
t
Setup time, PCLK active before RESET high
32N
ns
su(PCLK-RSTH)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6 when CLKIN and PLL are stable.
This parameter applies to CLKMODE x6 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL
circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 are the boot configuration pins during device reset.
E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select whichever value is larger for the MIN parameter.
N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met.
¶
#
||
†kh
switching characteristics over recommended operating conditions during reset
(see Figure 37)
−300
MIN
NO.
PARAMETER
UNIT
MAX
2
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RESET low to ECLKIN synchronized internally
Delay time, RESET high to ECLKIN synchronized internally
Delay time, RESET low to ECLKOUT1 high impedance
Delay time, RESET high to ECLKOUT1 valid
Delay time, RESET low to EMIF Z high impedance
Delay time, RESET high to EMIF Z valid
2E
2E
2E
3P + 20E
8P + 20E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(RSTL-ECKI)
d(RSTH-ECKI)
4
d(RSTL-ECKO1HZ)
d(RSTH-ECKO1V)
d(RSTL-EMIFZHZ)
d(RSTH-EMIFZV)
d(RSTL-EMIFHIV)
d(RSTH-EMIFHV)
d(RSTL-EMIFLIV)
d(RSTH-EMIFLV)
d(RSTL-LOWIV)
d(RSTH-LOWV)
d(RSTL-ZHZ)
5
8P + 20E
3P + 4E
6
2E
16E
2E
7
8P + 20E
8
Delay time, RESET low to EMIF high group invalid
Delay time, RESET high to EMIF high group valid
Delay time, RESET low to EMIF low group invalid
Delay time, RESET high to EMIF low group valid
Delay time, RESET low to low group invalid
9
8P + 20E
8P + 20E
11P
10
11
12
13
14
15
2E
0
Delay time, RESET high to low group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
0
2P
8P
d(RSTH-ZV)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
kE = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
hEMIF Z group consists of:
EA[22:3], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE,
SOE3, SDCKE, and PDT.
EMIF high group consists of: HOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: BUSREQ; HOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled
(with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details
on the PCI configuration pins, see the Device Configurations section of this data sheet.
HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1,
FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,
GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.
Z group consists of:
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
RESET TIMING (CONTINUED)
CLKOUT4
CLKOUT6
1
RESET
PCLK
18
2
4
3
5
ECLKIN
ECLKOUT1
ECLKOUT2
6
7
‡§
EMIF Z Group
EMIF High Group
EMIF Low Group
9
8
‡
‡
11
13
10
12
‡
Low Group
14
15
‡§
Z Group
Boot and Device
16
17
§¶
Configuration Inputs
†
EMIF Z group consists of:
EA[22:3], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE,
SOE3, SDCKE, and PDT.
EMIF high group consists of: HOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: BUSREQ; HOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled
(with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details
on the PCI configuration pins, see the Device Configurations section of this data sheet.
HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1,
FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,
GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.
Z group consists of:
‡
§
If LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention
between parameters 6, 7, 14, 15, 16, and 17.
Boot and Device Configurations Inputs (during reset) include: LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5.
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
†
Figure 37. Reset Timing
92
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
EXTERNAL INTERRUPT TIMING
†
timing requirements for external interrupts (see Figure 38)
−300
UNIT
NO.
MIN
4P
8P
4P
8P
MAX
Width of the NMI interrupt pulse low
ns
ns
ns
ns
1
2
t
t
w(ILOW)
Width of the EXT_INT interrupt pulse low
Width of the NMI interrupt pulse high
Width of the EXT_INT interrupt pulse high
w(IHIGH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
2
1
EXT_INTx/GPx, NMI
Figure 38. External/NMI Interrupt Timing
93
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOST-PORT INTERFACE (HPI) TIMING
†‡
timing requirements for host-port interface cycles (see Figure 39 through Figure 46)
−300
MAX
NO.
UNIT
MIN
5
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
ns
ns
ns
ns
ns
ns
ns
ns
su(SELV-HSTBL)
h(HSTBL-SELV)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2.4
¶
4P
3
Pulse duration, HSTROBE low
4
Pulse duration, HSTROBE high between consecutive accesses
4P
5
w(HSTBH)
§
Setup time, select signals valid before HAS low
10
11
12
13
su(SELV-HASL)
h(HASL-SELV)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
5
2.8
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
t
2
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
su(HASL-HSTBL)
2.1
h(HSTBL-HASL)
†
‡
§
¶
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
†‡
cycles (see Figure 39 through Figure 46)
−300
NO.
PARAMETER
UNIT
MIN
1.3
2
MAX
#
6
7
t
t
t
t
t
Delay time, HSTROBE low to HRDY high
4P+8
ns
ns
ns
ns
ns
d(HSTBL-HRDYH)
d(HSTBL-HDLZ)
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
Delay time, HSTROBE low to HD low impedance for an HPI read
Delay time, HD valid to HRDY low
8
−3
9
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
1.5
15
12
16
t
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P+8
ns
d(HSTBL-HDV)
†
‡
#
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL
4
3
3
†
HSTROBE
HCS
15
9
15
9
7
16
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 39. HPI16 Read Timing (HAS Not Used, Tied High)
†
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
‡
HSTROBE
18
18
HCS
15
15
7
9
16
9
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 40. HPI16 Read Timing (HAS Used)
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
2
2
2
2
3
1
1
1
1
HHWIL
3
4
†
HSTROBE
HCS
12
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 41. HPI16 Write Timing (HAS Not Used, Tied High)
19
11
19
†
HAS
11
11
11
10
10
10
10
10
10
HCNTL[1:0]
HR/W
11
11
HHWIL
3
4
‡
HSTROBE
18
12
18
HCS
12
13
13
HD[15:0] (input)
1st half-word
2nd half-word
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 42. HPI16 Write Timing (HAS Used)
96
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 43. HPI32 Read Timing (HAS Not Used, Tied High)
19
†
HAS
11
11
10
10
HCNTL[1:0]
HR/W
18
3
‡
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 44. HPI32 Read Timing (HAS Used)
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 45. HPI32 Write Timing (HAS Not Used, Tied High)
19
†
HAS
11
10
10
HCNTL[1:0]
HR/W
11
3
18
‡
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 46. HPI32 Write Timing (HAS Used)
98
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING
†‡
timing requirements for PCLK (see Figure 47)
−300
NO.
UNIT
MIN MAX
§
1
2
3
4
t
t
t
t
Cycle time, PCLK
30(or 8P )
ns
ns
c(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
11
11
1
w(PCLKH)
w(PCLKL)
sr(PCLK)
ns
4
V/ns
†
‡
§
For 3.3 V operation, the reference points for the rise and fall transitions are measured at V
ILP
P = 1/CPU clock frequency in ns. For example when running parts at 300 MHz, use P = 3.33 ns.
Select the parameter value of 30 ns or 8P, whichever is greater.
MAX and V MIN.
IHP
0.4 DV
Peak to Peak for
3.3V signaling
V MIN
DD
1
4
2
PCLK
3
4
Figure 47. PCLK Timing
timing requirements for PCI reset (see Figure 48)
−300
NO.
UNIT
MIN
1
MAX
1
2
t
t
Pulse duration, PRST
ms
w(PRST)
Setup time, PCLK active before PRST high
100
µs
su(PCLKA-PRSTH)
PCLK
PRST
1
2
Figure 48. PCI Reset (PRST) Timing
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING (CONTINUED)
timing requirements for PCI inputs (see Figure 49)
−300
NO.
UNIT
MIN
7
MAX
5
6
t
t
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
ns
ns
su(IV-PCLKH)
0
h(IV-PCLKH)
switching characteristics over recommended operating conditions for PCI outputs (see Figure 49)
−300
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Delay time, PCLK high to output valid
11
ns
ns
ns
ns
d(PCLKH-OV)
d(PCLKH-OIV)
d(PCLKH-OLZ)
d(PCLKH-OHZ)
Delay time, PCLK high to output invalid
2
2
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
28
PCLK
1
2
Valid
PCI Output
PCI Input
3
4
Valid
5
6
Figure 49. PCI Intput/Output Timing
100
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
timing requirements for serial EEPROM interface (see Figure 50)
−300
UNIT
NO.
MIN
50
0
MAX
8
9
t
t
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
ns
ns
su(DIV-CLKH)
h(CLKH-DIV)
†
switching characteristics over recommended operating conditions for serial EEPROM interface
(see Figure 50)
−300
NO.
PARAMETER
Pulse duration, XSP_CS low
UNIT
MIN
NOM
4092P
0
MAX
1
2
3
4
5
6
7
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
w(CSL)
Delay time, XSP_CLK low to XSP_CS low
Delay time, XSP_CS high to XSP_CLK high
Pulse duration, XSP_CLK high
d(CLKL-CSL)
d(CSH-CLKH)
w(CLKH)
2046P
2046P
2046P
2046P
2046P
Pulse duration, XSP_CLK low
w(CLKL)
Output setup time, XSP_DO valid before XSP_CLK high
Output hold time, XSP_DO valid after XSP_CLK high
osu(DOV-CLKH)
oh(CLKH-DOV)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
2
1
XSP_CS
3
4
5
XSP_CLK
7
6
XSP_DO
9
8
XSP_DI
Figure 50. PCI Serial EEPROM Interface Timing
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
†
timing requirements for McBSP (see Figure 51)
−300
NO.
UNIT
MIN
4P or 6.67
MAX
द
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
c(CKRX)
#
− 1
Pulse duration, CLKR/X high or CLKR/X low
0.5t
w(CKRX)
c(CKRX)
9
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
1.3
6
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
§
¶
#
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
Use whichever value is greater.
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.
102
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
switching characteristics over recommended operating conditions for McBSP (see Figure 51)
−300
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1
t
1.4
10
ns
d(CKSH-CKRXH)
§¶#
4P or 6.67
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
ns
c(CKRX)
||
C − 1
||
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C + 1
w(CKRX)
−2.1
−1.7
3
3
9
4
9
d(CKRH-FRV)
9
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
1.7
−3.9
Disable time, DX high impedance following last
data bit from CLKX high
12
13
2.0
−3.9 + D1k
4 + D2k
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
2.0 + D1k
9 + D2k
h
h
FSX int
FSX ext
−2.3 + D1
5.6 + D2
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
h
h
1.9 + D1
9 + D2
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
¶
#
||
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
Use whichever value is greater.
C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
DR
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
†
13
14
13
Bit(n-1)
†
12
DX
Bit 0
(n-2)
(n-3)
†
Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0
Figure 51. McBSP Timing
104
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 52)
−300
NO.
UNIT
MIN
4
MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
su(FRH-CKSH)
4
h(CKSH-FRH)
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 52. FSR Timing When GSYNC = 1
105
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 53)
−300
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 53)
−300
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T − 2 T + 3
L − 2 L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
−2
4
12P+2.8
20P+17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L − 2 L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
4P+3
12P+17
16P+17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
8P+1.8
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
106
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
107
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 54)
−300
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 54)
−300
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L − 2 L + 3
T − 2 T + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
−2
4
12P+4
12P+3
8P+2
20P+17
20P+17
16P+17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
−2
4
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H − 2 H + 4
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
108
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
−300
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
−300
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T − 2 T + 3
H − 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
−2
4
12P + 4 20P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
H − 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
4P + 3 12P + 17
8P + 2 16P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
109
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
110
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
−300
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
−300
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H − 2 H + 3
T − 2 T + 1
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
−2
4
12P + 4 20P + 17
12P + 3 20P + 17
8P + 2 16P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
−2
4
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L − 2 L + 4
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
111
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX
FSX
DX
1
2
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
112
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
TIMER TIMING
†
timing requirements for timer inputs (see Figure 57)
−300
UNIT
NO.
MIN
8P
MAX
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
ns
ns
w(TINPH)
8P
w(TINPL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
†
switching characteristics over recommended operating conditions for timer outputs
(see Figure 57)
−300
MIN MAX
NO.
PARAMETER
UNIT
3
4
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
8P−3
8P−3
ns
ns
w(TOUTH)
w(TOUTL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
2
1
TINPx
4
3
TOUTx
Figure 57. Timer Timing
113
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
†‡
timing requirements for GPIO inputs (see Figure 58)
−300
MIN MAX
NO.
UNIT
1
2
t
t
Pulse duration, GPIx high
Pulse duration, GPIx low
8P
8P
ns
ns
w(GPIH)
w(GPIL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
†
switching characteristics over recommended operating conditions for GPIO outputs
(see Figure 58)
−300
NO.
PARAMETER
UNIT
MIN
24P − 8
24P − 8
MAX
‡
‡
3
4
t
t
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
w(GPOH)
w(GPOL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO
is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 58. GPIO Port Timing
114
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉꢉ
ꢊ ꢋꢌ ꢍꢎꢏꢐꢑ ꢋ ꢒꢀ ꢎꢋ ꢓꢋ ꢀꢔꢕ ꢂꢋ ꢓ ꢒꢔꢕ ꢐꢖ ꢑ ꢆꢍ ꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 59)
−300
UNIT
NO.
MIN
35
10
9
MAX
1
3
4
t
t
t
Cycle time, TCK
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 59)
−300
NO.
PARAMETER
Delay time, TCK low to TDO valid
UNIT
MIN
MAX
2
t
0
18
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 59. JTAG Test-Port Timing
115
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉꢉ
ꢊ ꢋ ꢌꢍ ꢎꢏꢐ ꢑꢋ ꢒ ꢀ ꢎ ꢋ ꢓꢋ ꢀꢔꢕ ꢂ ꢋ ꢓꢒ ꢔꢕ ꢐ ꢖꢑ ꢆꢍꢂ ꢂꢑ ꢖ
SPRS196H − MARCH 2002 − REVISED JULY 2004
MECHANICAL DATA
The following table(s) show the thermal resistance characteristics for the PBGA — GLZ and ZLZ mechanical
packages.
thermal resistance characteristics (S-PBGA package) [GLZ]
†
NO.
1
°C/W
1.55
9.1
Air Flow (m/s )
RΘ
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
N/A
0.00
0.5
JC
JB
JA
JA
JA
JA
JT
JB
2
Junction-to-board
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-package top
Junction-to-board
3
17.9
15.02
13.4
11.89
0.5
4
5
1.0
6
2.00
N/A
N/A
7
Psi
Psi
8
7.4
†
m/s = meters per second
thermal resistance characteristics (S-PBGA package) [ZLZ]
†
NO.
°C/W
1.55
9.1
Air Flow (m/s )
1
2
3
4
5
6
7
8
RΘ
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
N/A
0.00
0.5
JC
JB
JA
JA
JA
JA
JT
JB
Junction-to-board
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-package top
Junction-to-board
17.9
15.02
13.4
11.89
0.5
1.0
2.00
N/A
N/A
Psi
Psi
7.4
†
m/s = meters per second
The following mechanical package diagram(s) reflect the most up-to-date mechanical data released for these
designated device(s).
116
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MPBG175B − OCTOBER 2000 − REVISED FEBRUARY 2002
GLZ (S-PBGA-N532)
PLASTIC BALL GRID ARRAY
23,10
22,90
SQ
20,00 TYP
0,80
0,40
AF
AD
AB
Y
AE
AC
AA
W
U
V
T
R
P
N
A1 Corner
M
K
L
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24 26
Heat Slug
Bottom View
3,30 MAX
1,00 NOM
Seating Plane
0,12
0,55
0,45
M
0,10
0,45
0,35
4201884/C 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL)
D. Flip chip application only
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明