TMX320C6455ZTZ7 [TI]
64-BIT, 66MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, PLASTIC, FCBGA-697;
| 型号： | TMX320C6455ZTZ7 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64-BIT, 66MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, PLASTIC, FCBGA-697 时钟 外围集成电路 |
| 文件： | 总238页 (文件大小：1965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
1 TMS320C6455 Fixed-Point Digital Signal Processor
1.1 Features
•
Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
•
High-Performance Fixed-Point DSP (C6455)
–
–
–
–
–
1-ns Instruction Cycle Time
1-GHz Clock Rate
Eight 32-Bit Instructions/Cycle
8000 MIPS/MMACS (16-Bits)
Commercial Temperature [0°C to 90°C]
–
–
1.25-, 2.5-, 3.125-Gbps Link Rates
Message Passing, DirectIO Support, Error
Management Extensions, and Congestion
Control
–
IEEE 1149.6 Compliant I/Os
•
•
TMS320C64x+™ DSP Core
•
32-Bit DDR2 Memory Controller (DDR2-500
SDRAM)
–
–
–
–
Dedicated SPLOOP Instruction
Compact Instructions (16-Bit)
Instruction Set Enhancements
Exception Handling
•
•
•
EDMA3 Controller (64 Independent Channels)
32-/16-Bit Host-Port Interface (HPI)
32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
One Inter-Integrated Circuit (I2C) Bus
TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
–
–
–
256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
•
•
•
Two McBSPs
10/100/1000 Mb/s Ethernet MAC (EMAC)
–
–
IEEE 802.3 Compliant
Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
–
–
256K-Bit (32K-Byte) L2 ROM
Time Stamp Counter
–
8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
•
•
Enhanced VCP2
–
–
Supports Over 694 7.95-Kbps AMR
Programmable Code Parameters
•
•
Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
Enhanced Turbo Decoder Coprocessor (TCP2)
UTOPIA
–
Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
Programmable Turbo Code and Decoding
Parameters
–
–
UTOPIA Level 2 Slave ATM Controller
8-Bit Transmit and Receive Operations up
to 50 MHz per Direction
–
–
User-Defined Cell Format up to 64 Bytes
•
•
Endianess: Little Endian, Big Endian
64-Bit/133-MHz EMIFA
•
•
•
16 General-Purpose I/O (GPIO) Pins
System PLL and PLL Controller
–
Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM and ZBT
SRAM)
Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
•
•
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
–
–
Supports Interface to Standard Sync
Devices and Custom Logic (FPGA, CPLD,
ASICs, etc.)
32M-Byte Total Addressable External
Memory Space
697-Pin Ball Grid Array (BGA) Package
(ZTZ Suffix), 0.8-mm Ball Pitch
•
•
0.09-µm/7-Level Cu Metal Process (CMOS)
3.3-, 1.8-, 1.5-, 1.2-V I/Os, 1.2-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2005–2006, Texas Instruments Incorporated
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
1.1.1 ZTZ BGA Package (Bottom View)
The TMS320C6455 devices are designed for a package temperature range of 0°C to +90°C (commercial
temperature range).
ZTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
2
4
6
8
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information,
see the Mechanical Data section of this document.
Figure 1-1. ZTZ BGA Package (Bottom View)
1.2 Description
The TMS320C64x+™ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The C6455 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making these DSPs an excellent choice for applications including video and
telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are
upward code-compatible from previous devices that are part of the C6000™ DSP platform.
Based on 90-nm process technology and with performance of up to 8000 million instructions per second
(MIPS) [or 8000 16-bit MMACs per cycle] at a clock rate of 1 GHz, the C6455 device offers cost-effective
solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational
flexibility of high-speed controllers and the numerical capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles
the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates
(MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+
core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, each
multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock
cycle.
The C6455 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves
system performance and reduces system cost for applications that include multiple DSPs on a board,
such as video and telecom infrastructures and medical/imaging.
2
TMS320C6455 Fixed-Point Digital Signal Processor
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
The C6455 DSP integrates a large amount of on-chip memory organized as a two-level memory system.
The level-1 (L1) program and data memories on the C6455 device are 32KB each. This memory can be
configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1
program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The
level 2 (L2) memory is shared between program and data space and is 2MB in size. L2 memory can also
be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodule also has
a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with
reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for
time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode
(ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit
timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event
generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient
interface between the C6455 DSP core processor and the network; a management data input/output
(MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is
capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM
interface.
The I2C ports on the C6455 allows the DSP to easily control peripheral devices and communicate with a
host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6455 device has two high-performance embedded coprocessors [enhanced Viterbi Decoder
Coprocessor (VCP2) and enhanced Turbo Decoder Coprocessor (TCP2)] that significantly speed up
channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over
694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint
lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5 and flexible polynomials, while
generating hard decisions or soft decisions. The TCP2 operating at CPU clock divided-by-3 can decode
up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2
implements the max*log-map algorithm and is designed to support all polynomials and rates required by
Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and
turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also
programmable. Communications between the VCP2/TCP2 and the CPU are carried out through the
EDMA3 controller.
The C6455 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into
source code execution.
TMS320C6455 Fixed-Point Digital Signal Processor
3
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
1.3 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6455 device.
32
C6455
DDR2 SDRAM
DDR2
Mem Ctlr
SBSRAM
PLL2 and
PLL2
Controller
ZBT SRAM
(D)
L2 ROM
32K
Bytes
L1P Cache Direct-Mapped
32K Bytes
64
EMIFA
(E)
SRAM
TCP2
VCP2
ROM/FLASH
I/O Devices
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
C64x+ DSP Core
(A)
McBSP0
Control Registers
SPLOOP Buffer
Instruction Fetch
(A)
McBSP1
16-/32-bit
Instruction Dispatch
L2
Cache
Memory
2048K
Bytes
Serial Rapid
I/O
Instruction
Decode
In-Circuit Emulation
Data Path B
M
e
g
a
m
o
d
u
l
Data Path A
(B)
HPI (32/16)
A Register File
A31−A16
B Register File
B31−B16
(B)
PCI66
A15−A0
B15−B0
e
(B)
UTOPIA
.M1
xx
xx
.M2
xx
xx
.L1 .S1
.D1
.D2
.S2 .L2
EMAC
10/100/1000
MII
RMII
GMII
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
(D)
RMGII
MDIO
L1D Cache
2-Way
Set-Associative
32K Bytes Total
16
(B)
GPIO16
I2C
(C)
Timer1
HI
LO
EDMA 3.0
Device
Configuration
Logic
PLL1 and
PLL1
Controller
(C)
Timer0
Secondary
Switched Central
Resource
HI
LO
Boot Configuration
A. McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins and the UTOPIA address pins. For more detailed information, see the Device
Configurationsection of this document.
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purpose timers or two 32-bit general-purpose
timers or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Figure 1-2. Functional Block Diagram
4
TMS320C6455 Fixed-Point Digital Signal Processor
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Contents
1
2
TMS320C6455 Fixed-Point Digital Signal
5.7
C64x+ Megamodule Register Description(s)........ 82
Processor.................................................. 1
1.1 Features .............................................. 1
1.1.1 ZTZ BGA Package (Bottom View)................... 2
1.2 Description............................................ 2
1.3 Functional Block Diagram ............................ 4
Device Overview ......................................... 6
2.1 Device Characteristics................................ 6
2.2 CPU (DSP Core) Description......................... 7
2.3 Memory Map Summary ............................. 10
2.4 Boot Sequence...................................... 11
2.5 Pin Assignments .................................... 14
2.6 Signal Groups Description .......................... 18
2.7 Terminal Functions.................................. 24
2.8 Development ........................................ 48
Device Configuration .................................. 50
3.1 Device Configuration at Device Reset .............. 50
6
Device Operating Conditions ........................ 90
6.1
Absolute Maximum Ratings Over Operating Case
Temperature Range (Unless Otherwise Noted)..... 90
6.2 Recommended Operating Conditions............... 90
6.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 92
7
C64x+ Peripheral Information and Electrical
Specifications ........................................... 95
7.1 Parameter Information .............................. 95
7.2
Recommended Clock and Control Signal Transition
Behavior ............................................. 97
7.3 Power Supplies...................................... 97
7.4
Enhanced Direct Memory Access (EDMA3)
Controller ............................................ 98
7.5 Interrupts........................................... 107
7.6 Reset Controller.................................... 110
7.7 PLL1 and PLL1 Controller ......................... 117
7.8 PLL2 and PLL2 Controller ......................... 132
7.9 DDR2 Memory Controller .......................... 141
7.10 External Memory Interface A (EMIFA)............. 143
7.11 I2C Peripheral ..................................... 154
7.12 Host-Port Interface (HPI) Peripheral............... 160
7.13 Multichannel Buffered Serial Port (McBSP) ....... 171
7.14 Ethernet MAC (EMAC) ............................ 180
7.15 Timers ............................................. 196
7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2).. 198
7.17 Enhanced Turbo Decoder Coprocessor (TCP2) .. 199
7.18 Peripheral Component Interconnect (PCI) ........ 201
7.19 UTOPIA............................................ 208
7.20 Serial Rapid I/O (SRIO) Port ...................... 212
7.21 General-Purpose Input/Output (GPIO) ............ 225
7.22 IEEE 1149.1 JTAG ................................ 227
3
3.2
Peripheral Configuration at Device Reset........... 52
Peripheral Selection After Device Reset ............ 54
3.3
3.4 Device State Control Registers ..................... 56
3.5 Device Status Register Description ................. 65
3.6
JTAG ID (JTAGID) Register Description ............ 67
3.7 Debugging Considerations .......................... 67
3.8 Configuration Examples............................. 68
System Interconnect................................... 70
4
5
4.1
Internal Buses, Bridges, and Switch Fabrics........ 70
4.2 Data Switch Fabric Connections .................... 71
4.3 Configuration Switch Fabric ......................... 73
4.4 Priority Allocation.................................... 75
C64x+ Megamodule.................................... 76
5.1 Memory Architecture ................................ 76
5.2 Memory Protection .................................. 79
5.3 Bandwidth Management ............................ 79
5.4 Power-Down Control ................................ 80
5.5 Megamodule Resets ................................ 80
5.6 Megamodule Revision............................... 81
Revision History............................................ 228
8
Mechanical Data....................................... 235
8.1 Thermal Data ...................................... 235
8.2 Packaging Information ............................. 235
Contents
5
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the C6455 DSP. The tables show significant features of the C6455
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.
Table 2-1. Characteristics of the C6455 Processor
HARDWARE FEATURES
C6455
EMIFA (64-bit bus width) [133 MHz]
(clock source = AECLKIN or SYSCLK4)
1
DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock source = CLKIN2)
1
EDMA3 (64 independent channels) [CPU/3 clock rate]
High-speed 1x/4x Serial Rapid IO Port
I2C
1
1
1
Peripherals
HPI (32- or 16-bit user selectable)
PCI (32-bit), [66-MHz or 33-MHz]
1 (HPI16 or HPI32)
1 (PCI66 or PCI33)
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configuration
section).
McBSPs (internal CPU/6 or external clock source up
to 100 Mbps)
2
UTOPIA (8-bit mode, 50-MHz, Slave-only)
10/100/1000 Ethernet MAC (EMAC)
Management Data Input/Output (MDIO)
1
1
1
64-Bit Timers (Configurable)
(internal clock source = CPU/6 clock frequency)
2 64-bit or 4 32-bit
General-Purpose Input/Output Port (GPIO)
VCP2 (clock source = CPU/3 clock frequency)
TCP2 (clock source = CPU/3 clock frequency)
Size (Bytes)
16
1
1
Decoder Coprocessors
On-Chip Memory
2128K
32K-Byte (32KB) L1 Program Memory Controller
[SRAM/Cache]
32KB Data Memory Controller [SRAM/Cache]
2048KB L2 Unified Memory/Cache
32KB L2 ROM
Organization
CPU Megamodule
Revision ID
Revision ID Register (MM_REVID.[15:0])
0x0181 2000
0x0
JTAG BSDL_ID
Frequency
JTAGID register (address location: 0x02A80008)
MHz
0x0008 A02F
720, 850, and 1000 (1-GHz)
1.39 ns (C6455-720), 1.17 ns (C6455-850),
1 ns (C6455-1000) [1 GHz CPU]
Cycle Time
ns
Core (V)
1.2 V (-720, -850, -1000)
1.2 [RapidIO],
1.5/1.8 [EMAC RGMII], and
1.8 and 3.3 V [I/O Supply Voltage]
Voltage
I/O (V)
PLL1 and PLL1
Controller Options
CLKIN1 frequency multiplier
Bypass (x1), x15, x20, x25, x30, x32
x20
CLKIN2 frequency multiplier
[DDR2 Memory Controller and EMAC support only]
PLL2
BGA Package
24 x 24 mm
µm
697-Pin Flip-Chip Plastic BGA (ZTZ)
0.09 µm
Process Technology
6
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-1. Characteristics of the C6455 Processor (continued)
HARDWARE FEATURES
C6455
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
Product Status(1)
PP
TMX320C6455ZTZ7,
TMX320C6455ZTZ8,
TMX320C6455ZTZ
(For more details on the C64x+™ DSP part
numbering, see Figure 2-13)
Device Part Numbers
(1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
2.2 CPU (DSP Core) Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two
16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add
operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There
is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms
such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes
for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex
multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and
16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for
audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Device Overview
7
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Other new features include:
•
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•
•
•
Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
•
•
•
C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
C64x+ DSP Cache User's Guide (literature number SPRUTBD)
C64x+ Megamodule Peripherals Reference Guide (literature number SPRU871)
C64x+ DSP Technical Overview (literature number SPRU965)
C64x to C64x+ CPU Migration Guide (literature number SPRAA84)
8
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Even
Odd
src1
src2
register
register
file A
file A
(A0, A2,
(A1, A3,
A4...A30)
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
Even
register
file B
(B0, B2,
B4...B30)
1x
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
Device Overview
9
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the C6455 device. The external memory
configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000
for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
Table 2-2. C6455 Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
1024K
32K
HEX ADDRESS RANGE
0000 0000 - 000F FFFF
0010 0000 - 0010 7FFF
0010 8000 - 007F FFFF
0080 0000 - 009F FFFF
00A0 0000 - 00DF FFFF
00E0 0000 - 00E0 7FFF
00E0 8000 - 00EF FFFF
00F0 0000 - 00F0 7FFF
00F0 8000 - 00FF FFFF
0100 0000 - 017F FFFF
0180 0000 - 01BF FFFF
01C0 0000 - 0287 FFFF
0288 0000 - 028B FFFF
028C 0000 - 028F FFFF
0290 0000 - 0293 FFFF
0294 0000 - 0297 FFFF
0298 0000 - 0299 FFFF
029A 0000 - 029A 01FF
029A 0200 - 029B FFFF
029C 0000 - 029C 01FF
029C 0200 - 029C FFFF
02A0 0000 - 02A0 7FFF
02A0 8000 - 02A1 FFFF
02A2 0000 - 02A2 7FFF
02A2 8000 - 02A2 FFFF
02A3 0000 - 02A3 7FFF
02A3 8000 - 02A3 FFFF
02A4 0000 - 02A7 FFFF
02A8 0000 - 02AB FFFF
02AC 0000 - 02AF FFFF
02B0 0000 - 02B0 3FFF
02B0 4000 - 02B3 FFFF
02B4 0000 - 02B4 01FF
02B4 0200 - 02B7 FFFF
02B8 0000 - 02B9 FFFF
02BA 0000 - 02BB FFFF
02BC 0000 - 02BF FFFF
02C0 0000 - 02C3 FFFF
02C4 0000 - 02C7 FFFF
02C8 0000 - 02C8 0FFF
02C8 1000 - 02C8 17FF
02C8 1800 - 02C8 1FFF
Reserved
Internal ROM
Reserved
7M - 32K
2M
Internal RAM (L2) [L2 SRAM]
Reserved
4M
L1P SRAM
32K
Reserved
1M - 32K
32K
L1D SRAM
Reserved
1M - 32K
8M
Reserved
C64x+ Megamodule Registers
Reserved
4M
12.5M
256K
256K
256K
256K
128K
512
HPI Control Registers
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
PLL1 Controller (including Reset Controller) Registers
Reserved
256K - 512
512
PLL2 Controller Registers
Reserved
64K
EDMA3.0 - CC Registers
Reserved
32K
96K
Reserved
32K
Reserved
32K
Reserved
32K
Reserved
32K
Reserved
256K
256K
256K
16K
Chip-Level Registers
Device State Control Registers
GPIO Registers
I2C Data and Control Registers
UTOPIA Control Registers
Reserved
256K
512
256K - 512
128K
128K
256K
256K
256K
4K
VCP2 Control Registers
TCP2 Control Registers
Reserved
PCI Control Registers
Reserved
EMAC Control
EMAC Control Module Registers
MDIO Control Registers
2K
2K
10
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-2. C6455 Memory Map Summary (continued)
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
8K
HEX ADDRESS RANGE
02C8 2000 - 02C8 3FFF
02C8 4000 - 02CF FFFF
02D0 0000 - 02D3 FFFF
02D4 0000 - 02DF FFFF
02E0 0000 - 02E0 3FFF
02E0 4000 - 02FF FFFF
0300 0000 - 03FF FFFF
0400 0000 - 0FFF FFFF
1000 0000 - 1FFF FFFF
2000 0000 - 2FFF FFFF
3000 0000 - 3000 00FF
3000 0100 - 33FF FFFF
3400 0000 - 3400 00FF
3400 0100 - 37FF FFFF
3C00 0000 - 3C00 03FF
3C00 0400 - 3C00 07FF
3C00 0800 - 3CFF FFFF
3D00 0000 - 3FFF FFFF
4000 0000 - 4FFF FFFF
5000 0000 - 57FF FFFF
5800 0000 - 5FFF FFFF
6000 0000 - 6FFF FFFF
7000 0000 - 77FF FFFF
7800 0000 - 7FFF FFFF
8000 0000 - 8FFF FFFF
9000 0000 - 9FFF FFFF
A000 0000 - A07F FFFF
A080 0000 - AFFF FFFF
B000 0000 - B07F FFFF
B080 0000 - BFFF FFFF
C000 0000 - C07F FFFF
C080 0000 - CFFF FFFF
D000 0000 - D07F FFFF
D080 0000 - DFFF FFFF
E000 0000 - EFFF FFFF
F000 0000 - FFFF FFFF
EMAC Descriptor Memory
Reserved
496K
RapidIO Control Registers
Reserved
256K
768K
RapidIO CPPI RAM
Reserved
16K
2M - 16K
16M
Reserved
Reserved
192M
Reserved
256M
Reserved
256M
McBSP 0 Data
256
Reserved
64M - 256
256
McBSP 1 Data
Reserved
64M - 256
1K
UTOPIA Receive (Rx) Data Queue
UTOPIA Transmit (Tx) Data Queue
Reserved
1K
16M - 2K
48M
Reserved
PCI External Memory Space
TCP2 Data Registers
VCP2 Data Registers
Reserved
256M
128M
128M
256M
EMIFA (EMIF64) Configuration Registers
DDR2 Memory Controller Configuration Registers
Reserved
128M
128M
256M
Reserved
256M
EMIFA CE2 - SBSRAM/Async(1)
8M
Reserved
256M - 8M
8M
EMIFA CE3 - SBSRAM/Async(1)
Reserved
EMIFA CE4 - SBSRAM/Async(1)
256M - 8M
8M
Reserved
256M - 8M
8M
EMIFA CE5 - SBSRAM/Async(1)
Reserved
256M - 8M
256M
DDR2 Memory Controller CE0 - DDR2 SDRAM
Reserved
256M
(1) The EMIFA CE0 and CE1 are not functionally supported on the C6455 device, and therefore, are not pinned out.
2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections and the DSP's internal registers are programmed with predetermined values. The boot sequence
is started automatically after each power-on, warm, max, and system reset. For more details on the
initiators of these resets, see Section 7.6, Reset, of this document.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset through the
BOOTMODE[3:0] pins.
Device Overview
11
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Each boot mode can be classified as a hardware boot mode or as a software boot mode. Software boot
modes require the use of the on-chip bootloader. The bootloader is DSP code that transfers application
code from an external source into internal or external program memory after the DSP is taken out of reset.
The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010
0000h. Hardware boot modes are carried out by the boot configuration logic. The boot configuration logic
is actual hardware that does not require the execution of DSP code. Section 2.4.1, Boot Modes
Supported, describes each boot mode in more detail.
When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not
exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU
frequency can be programmed to the frequency required by the application.
2.4.1 Boot Modes Supported
The C6455 has six boot modes:
•
•
No boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 SRAM located at address 0x80 0000.
Note: device operations is undefined if invalid code is located at address 0x80 0000. This boot mode is
a hardware boot mode.
Host boot (BOOTMODE[3:0] = 0001b and BOOTMODE[3:0] = 0111b)
If host boot is selected, after reset, the CPU is internally "stalled" while the remainder of the device is
released. During this period, an external host can initialize the CPU's memory space as necessary
through Host Port Interface (HPI) or the Peripheral Component Interconnect (PCI) interface. Internal
configuration registers, such as those that control the EMIF can also be initialized by the host with two
exceptions: Device State Control registers (Section 3.4), PLL1 and PLL2 Controller registers
(Section 7.7 and Section 7.8) cannot be accessed through any host interface, including HPI and PCI.
Once the host is finished with all necessary initialization, it must generate a DSP interrupt (DSPINT) to
complete the boot process. This transition causes boot configuration logic to bring the CPU out of the
"stalled" state. The CPU then begins execution from the internal L2 SRAM located at 0x80 0000. The
DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally
"stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host boot process is
selected.
All memory, with the exceptions previously described, may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled"
state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
As previously mentioned, for the C6455 device, the Host Port Interface (HPI) and the Peripheral
Component Interconnect (PCI) interface can be used for host boot. To use the HPI for host boot, the
PCI_EN pin (Y29) must be low [default] (enabling the HPI peripheral) and BOOTMODE[3:0] must be
set to 0001b at device reset. Conversely, to use the PCI interface for host boot, the PCI_EN pin (Y29)
must be high (enabling the PCI peripheral) and BOOTMODE[3:0] must be set to 0111b at device reset.
The DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control (HPIC)
register and the PCI TBD (TBD) register. The HPI host boot is a hardware boot mode while the PCI
host boot is a software boot mode.
If PCI boot is selected, the on-chip bootloader configures the PLL1 Controller such that CLKIN1 is
multiplied by 15. More specifically, PLLM is set to 0Eh (x15) and RATIO is set to 0 (÷1) in the PLL1
Multiplier Control Register (PLLM) and PLL1 Pre-Divider Register (PREDIV), respectively. The CLKIN1
frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM, 750
MHz, is not violated.
As mentioned previously, a DSP interrupt must be generated at the end of the host boot process to
begin execution of the loaded application. Since the DSP interrupt generated by the HPI and PCI is
mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA
Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
12
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
•
•
•
EMIFA 8-bit ROM boot (BOOTMODE[3:0] = 0100b)
After reset, the device will begin executing software out of an Asynchronous 8-bit ROM located in
EMIFA CE3 space using the default settings in the EMIFA registers. This boot mode is a hardware
boot mode.
Master I2C boot (BOOTMODE[3:0] = 0101b)
After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a
device acting as an I2C slave to the DSP using a predefined boot table format. The destination
address and length are contained within the boot table. This boot mode is a software boot mode.
Slave I2C boot (BOOTMODE[3:0] = 0110b)
A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a
Master to send data using a standard boot table format.
Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot
multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting
via an I2C EEPROM before acting as a Master and booting other DSPs.
The Slave I2C boot is a software boot mode.
•
Serial RapidIO boot (BOOTMODE[3:0] = 1000b through 1111b)
After reset, the following sequence of events occur:
–
–
–
–
–
–
–
–
–
The on-chip bootloader configures device registers, including SerDes, and EDMA3
The on-chip bootloader resets the peripheral's state machines and registers
RapidIO ports send idle control symbols to initialize SerDes ports
The host explores the system with RapidIO maintenance packets
The host identifies, enumerates, and initializes the RapidIO device
The host controller configures DSP peripherals through maintenance packets
The application software is sent from the host controller to DSP memory
The DSP CPU is awakened by interrupt such as a RapidIO DOORBELL packet
The application software is executed and normal operation follows
For Serial RapidIO boot, BOOTMODE2 (L26 pin) is used in conjunction with CFGGP[2:0] (T26, U26,
and U25 pins, respectively) to determine the device address within the RapidIO network.
BOOTMODE2 is the MSB of the address, while CFGGP[2:0] are used as the three LSBs–giving the
user the opportunity to have up to 16 unique device IDs.
BOOTMODE[1:0] (L25 and P26, respectively) denote the configuration of the RapidIO peripheral; i.e.,
"00b" refers to RapidIO Configuration 0. For exact device RapidIO Configurations, see the TBD
Application Report (literature number TBD).
The SRIO boot is a software boot mode.
2.4.2 2nd-Level Bootloaders
Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for
any level of customization to current boot methods as well as definition of a completely customized boot.
TI offers a few 2nd-level bootloaders, such as an EMAC bootloader and a UTOPIA bootloader, which can
be loaded using the Master I2C boot.
Device Overview
13
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2.5 Pin Assignments
2.5.1 Pin Map
Figure 2-2 through Figure 2-5 show the C6455 pin assigments in four quadrants (A, B, C, and D).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SYSCLK4/
GP[1]
AJ
AH
AG
FSX0
CLKS
DR0
TINPL1
DV
V
TMS
RSV26
RSV40
V
AJ
DV
GP[5]
TCK
DV
DD33
DD33
SS
SS
DD33
DR1/
AH
V
GP[4]
GP[7]
FSR0
GP[6]
NMI
TINPL0
TRST
TDO
EMU17
RSV38
EMU3
RSV27
RSV39
EMU8
EMU1
RSV36
EMU16
EMU9
DV
V
SS
TDI
SS
DD33
GP[8]
FSX1/
GP[11]
DX1/
AG
AF
AE
AD
AC
AB
AA
Y
CLKR0
EMU6
DV
V
RESET
POR
RIOCLK
CLKX0
DX0
TOUTL1
EMU0
EMU2
EMU4
DD33
SS
GP[9]
CLKR1/
GP[0]
HD11/
AD11
CLKX1/
GP[3]
AF
AE
DV
V
TOUTL0
EMU7
EMU5
EMU11
EMU14
EMU18
RIOCLK
DD33
SS
HD22/
AD22
HD0/
AD0
HD10/
AD10
FSR1/
GP[10]
V
DV
V
DV
EMU15
RSV37
EMU12
EMU10
RESETSTAT
DV
SS
DD33
SS
DD33
DD33
HD25/
AD25
HD5/
AD5
HD3/
AD3
HD21/
AD21
AD
AC
AB
AA
Y
DV
V
DV
EMU13
V
DV
V
DD33
SS
DD33
SS
DD33
SS
HD19/
AD19
HD13/
AD13
HD23/
AD23
HD29/
AD29
HD27/
AD27
DV
V
V
DV
V
DV
V
AV
DV
V
DD33
SS
SS
DD33
SS
DD33
SS
DDA
DD33
SS
HD17/
AD17
HD15/
AD15
HD9/
AD9
HD7/
AD7
HD1/
AD1
V
DV
DD33
SS
HD31/
AD31
HD28/
AD28
HD30/
AD30
DV
V
DV
V
SS
DD33
SS
DD33
HD26/
AD26
HD18/
AD18
HD16/
AD16
HD6/
AD6
HD4/
AD4
V
DV
DD33
SS
HD24/
AD24
HD20/
AD20
HD14/
AD14
HD8/
AD8
HD2/
AD2
W
W
RSV03
V
V
CV
V
CV
V
SS
SS
SS
DD
SS
DD
HHWIL/
PCLK
HD12/
AD12
V
V
DV
V
RSV02
V
DV
CV
V
CV
V
DV
DDRM
DD33
SS
SS
DD33
DD
SS
DD
SS
HDS2/
HDS1/
HINT/
HCNTL1/
HCNTL0/
PSTOP
HCS/
U
T
U
T
V
V
CV
V
CV
V
SS
SS
SS
DD
SS
DD
PCBE1
PSERR
PFRAME
PDEVSEL
PPERR
HAS/
PPAR
HRDY/
PIRDY
HR/W/
RSV15
RSV16
V
DV
CV
V
CV
V
CV
DD
SS
DD33
DD
SS
DD
SS
PCBE2
URADDR0/ URADDR1/
UXADDR1/
PIDSEL
R
R
DV
V
DV
V
V
CV
V
CV
V
SS
PGNT/
GP[12]
PRST/
GP[13]
DD33
SS
DD33
6
SS
SS
DD
SS
DD
1
2
3
4
5
7
8
9
10
11
12
13
14
15
Figure 2-2. C6455 Pin Map (Bottom View) [Quadrant A]
14
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AJ
V
AV
RIORX2
RIORX2
V
RIORX1
RIORX1
AV
V
DV
AED5
AED6
AED20
DV
DD33
AJ
SS
DDT
SS
DDT
SS
DD33
AH
V
DV
RIORX3
RIORX3
RIOTX2
RIOTX3
V
AV
V
V
RIORX0
RIOTX1
RIOTX0
RIORX0
DV
V
AED14
SCL
AED2
AED9
AED18
AED16
AED15
AED13
AED22
SS
AH
DD33
SS
DDT
SS
SS
DD33
SS
AG
AF
AE
AD
AC
AB
AA
Y
V
DV
RIOTX2
RIOTX1
DV
V
AED3
AED30
AED19
AED17
AED21
SS
AG
AF
DD33
DD33
SS
DV
RIOTX3
V
AV
V
AV
V
V
RIOTX0
DV
AED1
AED7
AED0
AED24
SDA
AED10
AED4
DD33
SS
DDT
SS
SS
DD33
AE
V
AV
V
V
RSV17
V
AV
V
V
AED12
AED11
AED26
AED23
ABE0
SS
DDT
SS
SS
DDT
SS
SS
DDT
SS
SS
AD
AC
AB
AA
Y
AV
DV
DV
V
V
DV
DV
DD33
AED8
DDA
SS
DD33
DDR
SS
SS
DD33
V
AV
DV
V
DV
V
AED28
AED25
AED31
V
DV
V
DV
DDA
DD33
SS
DD33
SS
SS
DD33
SS
DD33
AAWE/
ASWE
V
DV
AED29
ABE3
AED27
ABE2
SS
DD33
DV
V
ABE1
DD33
SS
AAOE/
ASOE
V
DV
PCI_EN
ABE7
RSV43
RSV42
RSV44
ACE2
ACE5
SS
DD33
W
W
V
DV
V
DV
V
DV
V
AR/W
ABA1/
ACE3
ABA0/
RSV41
ACE4
DD12
SS
DD12
SS
DD33
SS
V
V
DV
V
CV
V
DV
AECLKOUT
RSV20
SS
DDRM
SS
DD
SS
DD33
EMIFA_EN DDR2_EN
AEA5/
MCBSP1
_EN
AEA0/
AEA1/
AEA6/
PCI66
U
U
DV
V
CV
V
V
DV
V
DDRM
SS
DD
SS
DD33
SS
CFGGP0
CFGGP1
AEA4/
SYSCLKOUT
_EN
AEA2/
T
T
AEA3
V
CV
CV
V
DV
DD33
AEA11
PLLV1
SS
DD
SS
DD
SS
CFGGP2
AEA14/
HPI_
ASADS/
ASRE
AEA13/
AEA12/
R
R
CV
V
CV
V
DV
V
SS
AHOLD
29
DD
SS
DD
SS
DD33
LENDIAN UTOPIA_EN
WIDTH
16
17
18
19
20
21
22
23
24
25
26
27
28
Figure 2-3. C6455 Pin Map (Bottom View) [Quadrant B]
Device Overview
15
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
16
V
17
18
V
19
20
21
22
23
24
25
26
27
28
29
AEA16/
BOOT
AEA15/
AECLKIN
_SEL
AEA8/
P
N
M
L
P
N
M
L
CV
DV
V
SS
CV
RSV30
RSV31
SS
DD
DD33
DD
SS
PCI_EEAI
MODE0
AEA19/
BOOT
AEA7
V
V
CV
V
V
CV
V
DV
AHOLDA
CLKIN1
AECLKIN
SS
SS
DD
SS
DD
DD33
MODE3
AEA10/
AEA9/
CV
V
CV
DV
V
DV
V
SS
DD
SS
DD
SS
DD33
SS
DD33
SS
MACSEL1
MACSEL0
AEA17/
BOOT
AEA18/
BOOT
DV
CV
V
CV
V
V
ABUSREQ
AED32
AED44
AED43
AED50
AED56
AED59
AED57
AED61
AED49
ABE4
AED34
AED42
ABE5
AARDY
AED40
DD33
DD
SS
DD
SS
SS
MODE1
MODE2
K
J
K
J
V
ABE6
DV
AED33
AED38
AED47
AED55
AED63
SS
DD33
V
DV
AED46
AED45
AED54
AED36
SS
DD33
H
G
F
H
G
F
DV
V
DV
V
SS
DD33
SS
DD33
V
DV
V
DV
V
DV
DV
V
DV
DD18
AED48
AED52
AED35
AED37
SS
DD18
SS
DD18
SS
DD18
DD18
SS
DSDDQ
GATE3
V
V
V
SS
DV
RSV19
DV
DV
V
SS
SS
SS
DD18
DD18
DD18
DSDDQ
GATE2
E
D
C
B
A
E
D
C
B
A
DEODT0
DEA8
DEA4
AV
V
DSDDQS2
DSDDQS2
DSDDQM2
DV
DSDDQS3
DV
V
DV
DV
V
SS
DLL2
SS
DD18
DD18
SS
DD33
DD33
DEA5
DEA6
DEA7
DEA0
DEA1
DEA2
DED19
DED23
DED22
DED21
DED27
DED26
DED25
DSDDQS3
DSDDQM3
RSV11
RSV12
DED29
RSV32
RSV33
DED31
RSV09
RSV23
RSV22
AED58
AED60
AED51
AED39
AED41
DEA9
DED18
DED16
DV
V
DEA10
DV
DD18
SS
DD18
DEA11
16
DEODT1
DEA3
18
DED17
19
V
DED20
21
DED24
22
V
DED28
24
DED30
25
RSV10
26
AED62
27
AED53
28
DV
DD33
SS
SS
17
20
23
29
Figure 2-4. C6455 Pin Map (Bottom View) [Quadrant C]
16
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
1
2
3
4
5
6
7
8
9
10
11
12
SS
13
14
15
URADDR4/ URADDR3/ URADDR2/
UXADDR0/ UXADDR2/
P
N
M
L
P
N
M
L
PCBE0/
GP[2]
PREQ/
GP[15]
PINTA/
GP[14]
DV
V
RSV05
V
CV
V
CV
DD
DD33
SS
DD
SS
PTRDY
PCBE3
UXCLK/
MTCLK/
UXADDR3/
MDIO
UXDATA7/
MTXD7
RSV01
V
RSV29
RSV28
RSV04
CV
V
CV
V
SS
SS
DD
SS
DD
RMREFCLK
UXDATA0/
MTXD0/
URDATA7/ UXDATA6/
MRXD7 MTXD6
UXDATA2/ UXADDR4/
V
DV
CV
V
CV
V
CV
DD
SS
DD33
DD
SS
DD
SS
MTXD2
MDCLK
RMTXD0
UXDATA1/
MTXD1/
URDATA4/ URDATA5/ UXDATA4/
UXDATA5/
MTXD5
RSV06
V
V
CV
V
CV
V
SS
SS
DD
SS
DD
SS
MRXD4
MRXD5
MTXD4
RMTXD1
UXSOC/
MCOL
UXDATA3/
MTXD3
UXCLAV/
GMTCLK
K
J
K
J
DV
V
V
DV
DD33
DD33
SS
SS
URDATA0/
MRXD0/
URCLAV/
MCRS/
UXENB/
MTXEN/
RMTXEN
URDATA2/
MRXD2
URDATA3/
MRXD3
DV
V
SS
DD33
RMRXD0
RMCRSDV
URDATA1/
MRXD1/
URSOC/
MRXER/
RMRXER
URCLK/
MRCLK
URDATA6/
MRXD6
URENB/
MRXDV
H
G
F
H
G
F
V
DV
DD15
SS
RMRXD1
V
V
DV
CLKIN2
RSV08
RSV07
V
DV
V
DV
DV
V
DV
V
DV
V
SS
SS
DD33
SS
DD15
SS
DD18
DD18
SS
DD18
SS
DD18
SS
DV
DV
V
DV
V
DV
RSV14
RSV13
V
DV
V
V
DED11
DED10
DED9
V
SS
DD18
DD18
SS
DD18
SS
DD18
DBA2
DBA1
SS
DD15
SS
SS
E
D
C
B
A
E
D
C
B
A
RGRXD0
RGRXD1
RGRXC
RGTXCTL
RGRXD2
RGTXC
V
RSV34
V
DSDDQS1
DSDDQS1
DSDDQM1
DV
DSDDQS0
DSDDQS0
DV
RSV18
DCE0
SS
SS
DD18
DD18
V
DV
DV
RSV35
RSV25
RSV24
RSV21
6
DED14
DED7
DED6
DED5
DED4
10
DED3
DED2
DED1
DED0
12
DSDCAS
DSDCKE
SS
DD15
DD15
RGRXD3
RGRXCTL
RGTXD2 RGREFCLK
V
DED15
DED12
DED13
7
DED8
DSDDQM0
DSDRAS
DSDWE
V
DBA0
SS
REFSSTL
DDR2
DSDDQ
GATE1
V
V
RGTXD1
RGTXD0
3
RGMDCLK
RGMDIO
4
DV
DV
DV
DD18
DEA13
SS
REFHSTL
DD15
DD18
CLKOUT
DSDDQ
GATE0
DDR2
DV
RGTXD3
PLLV2
V
V
AV
DEA12
15
DD15
SS
SS
DLL1
CLKOUT
1
2
5
8
9
11
13
14
Figure 2-5. C6455 Pin Map (Bottom View) [Quadrant D]
Device Overview
17
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2.6 Signal Groups Description
RESETSTAT
RESET
NMI
CLKIN1
Clock/PLL1
and
PLL Controller
(A)
SYSCLK4/GP[1]
Reset and
Interrupts
PLLV1
POR
CLKIN2
PLLV2
Clock/PLL2
RSV00
RSV01
RSV02
RSV03
RSV04
RSV05
•
TMS
TDO
TDI
TCK
TRST
Reserved
•
•
IEEE Standard
1149.1
(JTAG)
Emulation
EMU0
EMU1
•
•
RSV42
RSV43
RSV44
•
EMU14
EMU15
EMU16
EMU17
EMU18
Peripheral
Enable/Disable
PCI_EN
Control/Status
A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
Figure 2-6. CPU and Peripheral Signals
18
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
TOUTL0
TINPL1
Timer 1
Timer 0
TINPL0
TOUTL1
Timers (64-Bit)
(C)
(C)
(C)
GP[7]
GP[6]
GP[5]
GP[4]
URADDR3/PREQ/GP[15]
URADDR2/PINTA/GP[14]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
(C)
GPIO
(B)
(B)
(B)
FSX1/GP[11]
FSR1/GP[10]
CLKX1/GP[3]
URADDR4/PCBE0/GP[2]
SYSCLK4/GP[1]
CLKR1/GP[0]
(C)
(B)
(A)
DX1/GP[9]
(B)
(B)
DR1/GP[8]
General-Purpose Input/Output 0 (GPIO) Port
4
4
RIOTX[3:0]
RIOCLK
RIOCLK
Transmit
Clock
RIOTX[3:0]
4
RIORX[3:0]
RIORX[3:0]
Receive
4
RAPID IO
A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For
more details, see the Device Configuration section of this document.
C. These UTOPIA and PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral
pins. For more details, see the Device Configuration section of this document.
Figure 2-7. Timers/GPIO/RapidIO Peripheral Signals
Device Overview
19
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
64
Data
AED[63:0]
AECLKIN
(A)
ACE5
AECLKOUT
(A)
ACE4
Memory Map
Space Select
(A)
ACE3
(A)
ACE2
External
Memory I/F
Control
20
Address
AEA[19:0]
ASWE/AAWE
AARDY
ABE7
ABE6
AR/W
AAOE/ASOE
ASADS/ASRE
ABE5
ABE4
ABE3
ABE2
Byte Enables
ABE1
ABE0
AHOLD
Bus
AHOLDA
ABUSREQ
Arbitration
Bank Address
ABA[1:0]
EMIFA (64-bit Data Bus)
32
DDR2CLKOUT
DDR2CLKOUT
DSDCKE
Data
DED[31:0]
DSDCAS
Memory Map
Space Select
DSDRAS
DCE0
DSDWE
External
Memory I/F
Control
DSDDQS[3:0]
DSDDQS[3:0]
14
Address
DEA[13:0]
DSDDQGATE[0]
DSDDQGATE[1]
DSDDQGATE[2]
DSDDQGATE[3]
DEODT[1:0]
DSDDQM3
DSDDQM2
DSDDQM1
DSDDQM0
Byte Enables
Bank Address
DBA[2:0]
DDR2 Memoty Controller (32-bit Data Bus)
A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6455 device.
Figure 2-8. EMIFA/DDR2 Memory Controller Peripheral Signals
20
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
(A)
HPI
(Host-Port Interface)
32
HD[15:0]/AD[15:0]
Data
HD[31:16]/AD[31:16]
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Register Select
Control
Half-Word
Select
HHWIL/PCLK
(HPI16 ONLY)
HINT/PFRAME
McBSP1
Transmit
McBSP0
Transmit
CLKX0
CLKX1/GP[3]
FSX0
DX0
FSX1/GP[11]
DX1/GP[9]
CLKR0
FSR0
CLKR1/GP[0]
FSR1/GP[10]
DR1/GP[8]
Receive
Clock
Receive
Clock
DR0
CLKS
(SHARED)
McBSPs
(Multichannel Buffered Serial Ports)
(B)
SCL
SDA
I2C
A. These HPI pins are muxed with the PCI peripheral. By default, these pins function as HPI. When the HPI is enabled, the number of HPI pins
used depends on the HPI configuration (HPI16 or HPI32). For more details on these muxed pins, see the Device Configuration section of this
document.
B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins. For
more details, see the Device Configuration section of this document.
Figure 2-9. HPI/McBSP/I2C Peripheral Signals
Device Overview
21
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Ethernet MAC
(EMAC)
Transmit
MII
UXDATA[7:2]/MTXD[7:2],
RMII
UXDATA[1:0]/MTXD[1:0]/RMTXD[1:0]
GMII
MDIO
(A)
RGTXD[3:0]
RGMII
Input/Output
MII
Receive
UXADDR3/MDIO
RMII
GMII
MII
URDATA[7:2]/MRXD[7:2],
URDATA[1:0]/MRXD[1:0]/RMRXD[1:0]
RMII
GMII
(A)
RGMII
RGMDIO
(A)
RGMII
RGRXD[3:0]
Clock
MII
Error Detect
and Control
UXADDR4/MDCLK
RGMDCLK
RMII
GMII
MII
URSOC/MRXER/RMRXER,
URENB/MRXDV,
URCLAV/MCRS/RMCRSDV,
UXSOC/MCOL,
RMII
GMII
(A)
RGMII
UXENB/MTXEN/RMTXEN
(A)
RGMII
RGTXCTL, RGRXCTL
Clocks
MII
UXCLK/MTCLK/RMREFCLK,
URCLK/MRCLK,
RMII
GMII
UXCLAV/GMTCLK
(A)
RGTXC,
RGRXC,
RGMII
RGREFCLK
(B)
Ethernet MAC (EMAC) and MDIO
A. RGMII signals are mutually exclusive to all other EMAC signals.
B. These EMAC pins are muxed with the UTOPIA peripheral. By default, these signals function as EMAC. For more details on these
muxed pins, see the Device Configuration section of this document.
Figure 2-10. EMAC/MDIO [MII/RMII/GMII/RGMII] Peripheral Signals
22
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
(A)
UTOPIA (SLAVE)
URDATA7/MRXD7
UXDATA7/MTXD7
URDATA6/MRXD6
URDATA5/MRXD5
UXDATA6/MTXD6
UXDATA5/MTXD5
URDATA4/MRXD4
URDATA3/MRXD3
UXDATA4/MTXD4
UXDATA3/MTXD3
Receive
Transmit
URDATA2/MRXD2
UXDATA2/MTXD2
URDATA1/MRXD1/RMRXD1
URDATA0/MRXD0/RMRXD0
UXDATA1/MTXD1/RMTXD1
UXDATA0/MTXD0/RMTXD0
UXENB/MTXEN/RMTXEN
UXADDR4/GMDCLK
UXADDR3/GMDIO
UXADDR2/PCBE3
UXADDR1/PIDSEL
UXADDR0/PTRDY
UXCLAV/GMTCLK
UXSOC/MCOL/TCLKRISE
URENB/MRXDV
URADDR4/PCLK/GP[2]
URADDR3/PREQ/GP[15]
URADDR2/PINTA/GP[14]
URADDR1/PRST/GP[13]
URADDR0/PGNT/GP[12]
URCLAV/MCRS/RMCRSDV
URSOC/MRXER/RMRXER
Control/Status
Control/Status
Clock
Clock
URCLK/MRCLK
UXCLK/MTCLK/REFCLK
A. These UTOPIA pins are muxed with the PCI or EMAC or GPIO peripherals. By default, these signals function as GPIO or EMAC peripheral
pins or have no function. For more details on these muxed pins, see the Device Configuration section of this data sheet.
Figure 2-11. UTOPIA Peripheral Signals
32
HD[15:0]/AD[15:0]
Data/Address
Clock
HHWIL/PCLK
HD[31:16]/AD[31:16]
UXADDR1/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
UXADDR2/PCBE3
HR/W/PCBE2
HDS2/PCBE1
UXADDR4/PCBE0/GP[2]
Command
Byte Enable
URADDR2/PINTA/GP[14]
HAS/PPAR
Control
URADDR1/PRST/GP[13]
HRDY/PIRDY
HCNTL0/PSTOP
UXADDR0/PTRDY
URADDR0/PGNT/GP[12]
URADDR3/PREQ/GP[15]
Arbitration
(A)
HDS1/PSERR
HCS/PPERR
Error
PCI Interface
A. These PCI pins are muxed with the HPI or UTOPIA or GPIO peripherals. By default, these signals function as HPI or GPIO or EMAC. For more
details on these muxed pins, see the Device Configuration section of this document.
Figure 2-12. PCI Peripheral Signals
Device Overview
23
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2.7 Terminal Functions
The terminal functions table (Table 2-3) identifies the external signal names, the associated pin (ball)
numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin
has any internal pullup/pulldown resistors and a functional pin description. For more detailed information
on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
the Device Configuration section of this document.
Table 2-3. Terminal Functions
SIGNAL
TYPE(1) IPD/IPU(2)
CLOCK/PLL CONFIGURATIONS
DESCRIPTION
NAME
NO.
CLKIN1
CLKIN2
PLLV1
PLLV2
N28
G3
I
I
IPD
IPD
Clock Input for PLL1.
Clock Input for PLL2.
T29
A5
A
A
1.8-V I/O supply voltage for PLL1
1.8-V I/O supply voltage for PLL2
SYSCLK4 is the clock output at 1/8 of the device speed (O/Z) or this pin can be
programmed as the GP1 pin (I/O/Z) [default].
SYSCLK4/GP[1](3)
AJ13
I/O/Z
IPD
JTAG EMULATION
TMS
TDO
TDI
AJ10
AH8
AH9
AJ9
I
IPU
IPU
IPU
IPU
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE
1149.1 JTAG compatibility statement portion of this document.
TRST
AH7
I
IPD
EMU0(4)
EMU1(4)
EMU2
AF7
AE11
AG9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 0
Emulation pin 1
Emulation pin 2
Emulation pin 3
Emulation pin 4
Emulation pin 5
Emulation pin 6
Emulation pin 7
Emulation pin 8
Emulation pin 9
Emulation pin 10
Emulation pin 11
Emulation pin 12
Emulation pin 13
Emulation pin 14
Emulation pin 15
Emulation pin 16
Emulation pin 17
Emulation pin 18
EMU3
AF10
AF9
EMU4
EMU5
AE12
AG8
EMU6
EMU7
AF12
AF11
AH13
AD10
AD12
AE10
AD8
EMU8
EMU9
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
AF13
AE9
AH12
AH10
AE13
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
Device reset
RESET
AG14
I
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-kΩ resistor should be used.)
(3) These pins are multiplexed pins. For more details, see the Device Configuration section of this document.
(4) The C6455 DSP does not require external pulldown resistors on the EMU0 and EMU1 pins for normal or boundary-scan operation.
24
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
Nonmaskable interrupt, edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin
is not used, it is recommended that the NMI pin be grounded versus relying on
the IPD.
NMI
AH4
I
IPD
RESETSTAT
POR
AE14
AF14
AG2
AG3
AJ2
O
Reset Status pin. The RESETSTAT pin indicates when the device is in reset
Power on reset.
I
GP[7]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
GP[6]
General-purpose input/output (GPIO) pins (I/O/Z).
GP[5]
GP[4]
AH2
URADDR3/PREQ/
GP[15]
P2
P3
R5
R4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
URADDR2/PINTA/
GP[14]
UTOPIA received address pins or PCI peripheral pins or General-purpose
input/output (GPIO) [15:12, 2] pins (I/O/Z) [default]
URADDR1/PRST/
GP[13]
PCI bus request (O/Z) or GP[15] (I/O/Z) [default]
PCI interrupt A (O/Z) or GP[14] (I/O/Z) [default]
PCI reset (I) or GP[13] (I/O/Z) [default]
PCI bus grant (I) or GP[12] (I/O/Z) [default]
PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z) [default]
URADDR0/PGNT/
GP[12]
FSX1/GP[11]
FSR1/GP[10]
DX1/GP[9]
AG4
AE5
AG5
AH5
AF5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]
DR1/GP[8]
GP[1] pin (I/O/Z). SYSCLK4 is the clock output at 1/8 of the device speed (O/Z)
or this pin can be programmed as a GP[1] pin (I/O/Z) [default].
CLKX1/GP[3]
URADDR4/PCBE0/
GP[2]
P1
I/O/Z
SYSCLK4/GP[1](3)
AJ13
AF4
O/Z
IPD
IPD
CLKR1/GP[0]
I/O/Z
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
GP[15:8], or PCI peripherals. This pin works in conjunction with the
MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details,
see the Device Configuration section of this document).
PCI_EN
Y29
I
IPD
HINT/PFRAME
U3
U4
I/O/Z
I/O/Z
Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z)
Host control - selects between control, address, or data registers (I) [default] or
PCI device select (I/O/Z)
HCNTL1/PDEVSEL
Host control - selects between control, address, or data registers (I) [default] or
PCI stop (I/O/Z)
HCNTL0/PSTOP
HHWIL/PCLK
U5
V3
I/O/Z
I/O/Z
Host half-word select - first or second half-word (not necessarily high or low
order)
[For HPI16 bus width selection only] (I) [default] or PCI clock (I)
HR/W/PCBE2
HAS/PPAR
T5
T3
U6
U2
U1
T4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
Host chip select (I) [default] or PCI parity error (I/O/Z)
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z)
URADDR3/PREQ/
GP[15]
UTOPIA received address pin 3 (URADDR3) (I) or PCI bus request (O/Z) or
GP[15] (I/O/Z) [default]
P2
P3
R5
I/O/Z
I/O/Z
I/O/Z
URADDR2/PINTA/
GP[14]
UTOPIA received address pin 2 (URADDR2) (I) or PCI interrupt A (O/Z) or
GP[14] (I/O/Z) default]
URADDR1/PRST/
GP[13]
UTOPIA received address pin 1 (URADDR1) (I) or PCI reset (I) or
GP[13] (I/O/Z) [default]
Device Overview
25
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
URADDR0/PGNT/
GP[12]
UTOPIA received address pin 0 (URADDR0) (I) or PCI bus grant (I) or
GP[12] (I/O/Z)[default]
R4
I/O/Z
UTOPIA received address pin 4 (URADDR4) (I) or PCI command/byte enable 0
(I/O/Z) or
GP[2] (I/O/Z)[default]
URADDR4/PCBE0/
GP[2]
P1
I/O/Z
UTOPIA transmit address pin 2 (UXADDR2) (I) or PCI command/byte enable 3
(I/O/Z). By default, this pin has no function.
UXADDR2/PCBE3
UXADDR1/PIDSEL
UXADDR0/PTRDY
P5
R3
P4
I/O/Z
I
UTOPIA transmit address pin 1 (UXADDR1) (I) or PCI initialization device
select (I). By default, this pin has no function.
UTOPIA transmit address pin 0 (UXADDR0) (I) or PCI target ready (PRTDY)
(I/O/Z). By default, this pin has no function.
I/O/Z
HD31/AD31
HD30/AD30
HD29/AD29
HD28/AD28
HD27/AD27
HD26/AD26
HD25/AD25
HD24/AD24
HD23/AD23
HD22/AD22
HD21/AD21
HD20/AD20
HD19/AD19
HD18/AD18
HD17/AD17
HD16/AD16
HD15/AD15
HD14/AD14
HD13/AD13
HD12/AD12
HD11/AD11
HD10/AD10
HD9/AD9
AA3
AA5
AC4
AA4
AC5
Y1
AD2
W1
Host-port data [31:16] pin (I/O/Z) [default] or PCI data-address bus [31:16]
(I/O/Z)
I/O/Z
AC3
AE1
AD1
W2
AC1
Y2
AB1
Y3
AB2
W4
AC2
V4
AF3
AE3
AB3
W5
HD8/AD8
I/O/Z
Host-port data [15:0] pin (I/O/Z) [default] or PCI data-address bus [15:0] (I/O/Z)
HD7/AD7
AB4
Y4
HD6/AD6
HD5/AD5
AD3
Y5
HD4/AD4
HD3/AD3
AD4
W6
HD2/AD2
HD1/AD1
AB5
AE2
HD0/AD0
26
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
NO.
EMIFA (64-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ABA1/EMIFA_EN
V25
O/Z
IPD
EMIFA bank address control (ABA[1:0])
•
Active-low bank selects for the 64-bit EMIFA.
When interfacing to 16-bit Asynchronous devices, ABA1 carries bit 1 of the
byte address.
For an 8-bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and
0 of the byte address
DDR2 Memory Controller enable (DDR2_EN) [ABA0]
0 - DDR2 Memory Controller peripheral pins are disabled (default)
1 - DDR2 Memory Controller peripheral pins are enabled
ABA0/DDR2_EN
V26
O/Z
IPD
EMIFA enable (EMIFA_EN) [ABA1]
0 - EMIFA peripheral pins are disabled (default)
1 - EMIFA peripheral pins are enabled
ACE5
ACE4
ACE3
ACE2
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
V27
V28
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
Enabled by bits 28 through 31 of the word address
W26
W27
W29
K26
•
Only one pin is asserted during any external data access
Note: The C6455 device does not have ACE0 and ACE1 pins
L29
EMIFA byte-enable control
L28
•
Decoded from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
AA29
AA28
AA25
AA26
•
Byte-write enables for most types of memory.
EMIFA (64-BIT) - BUS ARBITRATION
AHOLDA
AHOLD
N26
R29
L27
O
I
IPU
IPU
IPU
EMIFA hold-request-acknowledge to the host
EMIFA hold request from the host
EMIFA bus request output
ABUSREQ
O
EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK4
AECLKIN
N29
I
IPD
clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin.
Note: AECLKIN is the default for the EMIFA input clock.
AECLKOUT
V29
O/Z
O/Z
IPD
IPU
EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK4) frequency]
Asynchronous memory write-enable/Programmable synchronous interface
write-enable
AAWE/ASWE
AB25
AARDY
K29
W25
Y28
I
IPU
IPU
IPU
Asynchronous memory ready input
AR/W
O/Z
O/Z
Asynchronous/Programmable synchronous memory read/write
Asynchronous/Programmable synchronous memory output-enable
Programmable synchronous address strobe or read-enable
AAOE/ASOE
•
For programmable synchronous interface, the r_enable field in the Chip
Select x Configuration Register selects between ASADS and ASRE:
ASADS/ASRE
R26
O/Z
IPU
–
If r_enable = 0, then the ASADS/ASRE signal functions as the ASADS
signal.
–
If r_enable = 1, then the ASADS/ASRE signal functions as the ASRE
signal.
Device Overview
27
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
EMIFA (64-BIT) - ADDRESS
EMIFA external address (word address) (O/Z)
AEA19/BOOTMODE3
AEA18/BOOTMODE2
AEA17/BOOTMODE1
AEA16/BOOTMODE0
AEA15/AECLKIN_SEL
AEA14/HPI_WIDTH
AEA13/LENDIAN
N25
L26
L25
P26
P27
R25
R27
R28
Controls initialization of the DSP modes at reset (I) via pullup/pulldown resistors
[For more detailed information, see the Device Configurations section of this
datasheet.]
Note: If a configuration pin must be routed out from the device, the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends
the use of an external pullup/pulldown resistor.
O/Z
O/Z
IPD
IPU
•
Boot mode - device boot mode configurations (BOOTMODE[3:0]) [Note:
the peripheral must be enabled to use the particular boot mode.]
AEA[19:16]:
0000 - No boot (default mode)
0001 - Host boot (HPI)
AEA12/UTOPIA_EN
0010 -Reserved
0011 - Reserved
0100 - EMIFA 8-bit ROM boot
0101 - Master I2C boot
0110 - Slave I2C boot
0111 - Host boot (PCI)
1000 thru 1111 - Serial Rapid I/O boot configurations
For more detailed information on the boot modes, see Section 2.4, Boot
Sequence, of this document.
•
•
EMIFA input clock source select
Clock mode select for EMIFA (AECLKIN_SEL)
AEA15:
0 - AECLKIN (default mode)
1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software
selectable via the Software PLL1 Controller. By default, SYSCLK4 is
selected as CPU/8 clock rate.
HPI peripheral bus width (HPI_WIDTH) select
[Applies only when HPI is enabled; PCI_EN pin = 0]
AEA14:
O/Z
IPD
AEA11
T25
0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0]
pins are used and the remaining HD[31:16] pins are reserved pins in the
Hi-Z state.)
1 - HPI operates as an HPI32.
•
•
Device Endian mode (LENDIAN)
AEA13:
0 - System operates in Big Endian mode
1 - System operates in Little Endian mode(default)
UTOPIA Enable bit (UTOPIA_EN)
AEA12: UTOPIA peripheral enable(functional)
0 - UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enable(default).
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins
function as EMAC and MDIO. Which EMAC/MDIO configuration (interface)
[MII, RMII, GMII or the standalone RGMII] is controlled by the
MACSEL[1:0] bits.
1 - UTOPIA enabled; EMAC and MDIO disabled [except when the
MACSEL[1:0] bits = 11 then, the EMAC/MDIO RGMII interface is still
functional].
This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins now
function as UTOPIA. And if MACSEL[1:0] = 11, the RGMII standalone pin
functions can be used.
28
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
AEA10/MACSEL1
AEA9/MACSEL0
AEA8/PCI_EEAI
AEA7
NO.
M25
M27
P25
N27
U27
U28
•
EMAC/MDIO interface select bits (MACSEL[1:0])
If the EMAC and MDIO peripherals are enabled, AEA12 pin (UTOPIA_EN
= 0) , there are two additional configuration pins — MACSEL[1:0] — to
select the EMAC/MDIO interface.
AEA[10:9]: MACSEL[1:0] with AEA12 =0.
00 - 10/100 EMAC/MDIO MII Mode Interface (default)
01 - 10/100 EMAC/MDIO RMII Mode Interface
10 - 10/100/1000 EMAC/MDIO GMII Mode Interface
11 - 10/100/1000 with RGMII Mode Interface
AEA6/PCI66
AEA5/MCBSP1_EN
AEA4/
SYSCLKOUT_EN
T28
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
When UTOPIA is enabled (AEA12 = 1), if the MACSEL[1:0] bits = 11 then,
the EMAC/MDIO RGMII interface is still functional. For more detailed
information, see the Device Configuration section of this document.
AEA3
T27
T26
U26
AEA2/CFGGP2
AEA1/CFGGP1
•
•
PCI I2C EEPROM Auto-Initialization (PCI_EEAI)
AEA8: PCI auto-initialization via external I2C EEPROM
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be
pulled up.
0 - PCI auto-initialization through I2C EEPROM is disabled (default).
1 - PCI auto-initialization through I2C EEPROM is enabled.
PCI Frequency Selection (PCI66)
[The PCI peripheral needs be enabled (PCI_EN = 1) to use this function]
Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating
frequency is selected at reset via the pullup/pulldown resistor on the PCI66
pin:
O/Z
IPD
AEA6:
0 - PCI operates at 33 MHz (default).
1 - PCI operates at 66 MHz.
Note: If the PCI peripheral is disabled (PCI_EN = 0), this pin must not be
pulled up.
•
•
•
McBSP1 Enable bit (MCBSP1_EN)
Selects which function is enabled on the McBSP1/GPIO muxed pins
AEA0/CFGGP0
U25
AEA5:
0 - GPIO pin functions enabled (default).
1 - McBSP1 pin functions enabled.
SYSCLKOUT Enable bit (SYSCLKOUT_EN)
Selects which function is enabled on the SYSCLK4/GP[1] muxed pin
AEA4:
0 - GP[1] pin function of the SYSCLK4/GP[1] pin enabled (default).
1 - SYSCLK4 pin function of the SYSCLK4/GP[1] pin enabled.
Configuration GPI (CFGGP[2:0]) (AEA[2:0])
These pins are latched during reset and their values are shown in the
DEVSTAT register. These values can be used by software routines for boot
operations.
Note: For proper C6455 device operation, the AEA11 and AEA3 pins must be
externally pulled up with a 1-kΩ resistor at device reset.
Device Overview
29
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
EMIFA (64-BIT) - DATA
AED63
AED62
AED61
AED60
AED59
AED58
AED57
AED56
AED55
AED54
AED53
AED52
AED51
AED50
AED49
AED48
AED47
AED46
AED45
AED44
AED43
AED42
AED41
AED40
AED39
AED38
AED37
AED36
AED35
AED34
AED33
AED32
AED31
AED30
AED29
AED28
AED27
AED26
AED25
AED24
AED23
AED22
F25
A27
C27
C28
E27
D28
D27
F27
G25
G26
A28
F28
B28
G27
B27
G28
H25
J26
H26
J27
H27
J28
I/O/Z
IPU
EMIFA external data
C29
J29
D29
J25
F29
F26
G29
K28
K25
K27
AA27
AG29
AB29
AC27
AB28
AC26
AB27
AC25
AB26
AD28
30
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AED21
AED20
AED19
AED18
AED17
AED16
AED15
AED14
AED13
AED12
AED11
AED10
AED9
AD29
AJ28
AF29
AH28
AE29
AG28
AF28
AH26
AE28
AE26
AD26
AF27
AG27
AD27
AE25
AJ27
AJ26
AE27
AG25
AH27
AF25
AD25
I/O/Z
IPU
EMIFA external data
AED8
AED7
AED6
AED5
AED4
AED3
AED2
AED1
AED0
DDR2 MEMORY CONTROLLER (32-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
DDR2 Memory Controller memory space enable. When the DDR2 Memory
Controller is enabled, it always keeps this pin low.
DCE0
E14
O/Z
DBA2
DBA1
DBA0
E15
D15
C15
B14
A14
D13
C13
B13
D14
A17
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
DDR2 Memory Controller bank address control
DDR2CLKOUT
DDR2CLKOUT
DSDCAS
DDR2 Memory Controller output clock (CLKIN2 frequency × 10)
Negative DDR2 Memory Controller output clock (CLKIN2 frequency × 10)
DDR2 Memory Controller SDRAM column-address strobe
DDR2 Memory Controller SDRAM row-address strobe
DSDRAS
DSDWE
DDR2 Memory Controller SDRAM write-enable
DSDCKE
DDR2 Memory Controller SDRAM clock-enable (used for self-refresh mode).
DEODT1
On-die termination signals to external DDR2 SDRAM. These pins are reserved
for future use and should not be connected to the DDR2 SDRAM.
Note: There are no on-die termination resistors implemented on the C6455
DSP die.
DEODT0
E16
O/Z
DSDDQGATE3
DSDDQGATE2
DSDDQGATE1
DSDDQGATE0
DSDDQM3
F21
E21
B9
I
DDR2 Memory Controller data strobe gate [3:0]
O/Z
I
For hookup of these signals, please refer to the Implementing DDR2 PCB
Layout on a TMS320C6455 Hardware Design Application Report (literature
number SPRAAA9).
A9
O/Z
O/Z
O/Z
O/Z
C23
C20
C8
DDR2 Memory Controller byte-enable controls
•
Decoded from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
DSDDQM2
DSDDQM1
•
•
Byte-write enables for most types of memory.
DSDDQM0
C11
O/Z
Can be directly connected to SDRAM read and write mask signal (SDQM).
Device Overview
31
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
DSDDQS3
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
E23
E20
E8
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DSDDQS2
DSDDQS1
DSDDQS0
DSDDQS3
DSDDQS2
DSDDQS1
DSDDQS0
DDR2 Memory Controller data strobe [3:0] positive
DDR2 data strobe [3:0] negative
E11
D23
D20
D8
Note: These pins are used to meet AC timings. For more detailed information,
see the Implementing DDR2 PCB Layout on a TMS320C6455Hardware Design
Application Report (literature number SPRAAA9).
D11
DDR2 MEMORY CONTROLLER (32-BIT) - ADDRESS
DEA13
DEA12
DEA11
DEA10
DEA9
DEA8
DEA7
DEA6
DEA5
DEA4
DEA3
DEA2
DEA1
DEA0
B15
A15
A16
B16
C16
D16
B17
C17
D17
E17
A18
B18
C18
D18
O/Z
DDR2 Memory Controller external address
32
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
DDR2 MEMORY CONTROLLER (32-BIT) - DATA
DED31
DED30
DED29
DED28
DED27
DED26
DED25
DED24
DED23
DED22
DED21
DED20
DED19
DED18
DED17
DED16
DED15
DED14
DED13
DED12
DED11
DED10
DED9
B25
A25
B24
A24
D22
C22
B22
A22
D21
C21
B21
A21
D19
C19
A19
B19
C7
I/O/Z
DDR2 Memory Controller external data
D7
A7
B7
F9
E9
D9
DED8
C9
DED7
D10
C10
B10
A10
D12
C12
B12
A12
DED6
DED5
DED4
DED3
DED2
DED1
DED0
TIMER 1
TOUTL1
TINPL1
AG7
AJ6
O/Z
I
IPD
IPD
Timer 1 output pin for lower 32-bit counter
Timer 1 input pin for lower 32-bit counter
TIMER 0
TOUTL0
TINPL0
AF8
AH6
O/Z
I
IPD
IPD
Timer 0 output pin for lower 32-bit counter
Timer 0 input pin for lower 32-bit counter
INTER-INTEGRATED CIRCUIT (I2C)
SCL
SDA
AG26
AF26
I/O/Z
I/O/Z
I2C clock. When the I2C module is used, use an external pullup resistor.
I2C data. When I2C is used, ensure there is an external pullup resistor.
Device Overview
33
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0)
McBSP external clock source (as opposed to internal) (I)
[shared by McBSP1 and McBSP0]
CLKS
AJ4
I
IPD
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1/GP[0]
FSR1/GP[10]
DR1/GP[8]
AF4
AE5
AH5
AG5
AG4
AF5
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
McBSP1 receive frame sync (I/O/Z) or GP[10] (I/O/Z)[default]
McBSP1 receive data (I) or GP[8] (I/O/Z) [default]
DX1/GP[9]
McBSP1 transmit data (O/Z) or GP[9] (I/O/Z) [default]
McBSP1 transmit frame sync (I/O/Z) or GP[11] (I/O/Z) [default]
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
FSX1/GP[11]
CLKX1/GP[3]
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0
FSR0
DR0
AG1
AH3
AJ5
AF6
AJ3
AG6
I/O/Z
I/O/Z
I
IPU
IPD
IPD
IPD
IPD
IPU
McBSP0 receive clock (I/O/Z)
McBSP0 receive frame sync (I/O/Z)
McBSP0 receive data (I)
DX0
I/O/Z
I/O/Z
I/O/Z
McBSP0 transmit data (O/Z)
McBSP0 transmit frame sync (I/O/Z)
McBSP0 transmit clock (I/O/Z)
FSX0
CLKX0
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]
UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE
Source clock for UTOPIA transmit driven by Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
UXCLK/MTCLK/
RMREFCLK
pin is either EMAC MII transmit clock (MTCLK) or the EMAC RMII reference
clock. The EMAC function is controlled by the MACSEL[1:0] (AEA[10:9] pins).
For more detailed information, see the Device Configuration section of this
datasheet.
N4
K5
I/O/Z
I/O/Z
Transmit cell available status output signal from UTOPIA Slave.
0 indicates a complete cell is NOT available for transmit
1 indicates a complete cell is available for transmit
UXCLAV/GMTCLK
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC GMII transmit clock. MACSEL[1:0] dependent.
UTOPIA transmit interface enable input signal. Asserted by the Master ATM
Controller to indicate that the UTOPIA Slave should put out on the Transmit
Data Bus the first byte of valid data and the UXSOC signal in the next clock
cycle.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either the EMAC MII transmit enable [default] or EMAC RMII transmit
enable or EMAC GMII transmit enable. MACSEL[1:0] dependent.
UXENB/MTXEN/
RMTXEN
J5
I/O/Z
Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the
rising edge of the UXCLK, indicating that the first valid byte of the cell is
available on the 8-bit Transmit Data Bus (UXDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either the EMAC MII collision sense or EMAC GMII collision sense.
MACSEL[1:0] dependent.
UXSOC/MCOL
K3
I/O/Z
UXADDR4/MDCLK
UXADDR3/MDIO
UXADDR2/PCBE3
UXADDR1/PIDSEL
M5
N3
P5
R3
I
I
I
I
UTOPIA transmit address pins (UXADDR[4:0]) (I)
As UTOPIA transmit address pins, UTOPIA_EN (AEA12 pin) = 1:
•
5-bit Slave transmit address input pins driven by the Master ATM Controller
to identify and select one of the Slave devices (up to 31 possible) in the
ATM System.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0) and if
the PCI_EN pin = 1, these pins are PCI peripheral pins:
PCI command/byte enable 3(PCBE3) [I/O/Z],
UXADDR0/PTRDY
P4
I
PCI initialization device select (PIDSEL) [I], and
PCI target ready (PTRDY) [I/O/Z].
34
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
NO.
N5
M3
L5
UXDATA7/MTXD7
UXDATA6/MTXD6
UXDATA5/MTXD5
UXDATA4/MTXD4
UXDATA3/MTXD3
UXDATA2/MTXD2
UTOPIA 8-bit transmit data bus (I/O/Z) [default] or EMAC MII 4-bit transmit data
bus (I/O/Z) [default] or EMAC GMII 8-bit transmit data bus or EMAC RMII 2-bit
transmit data bus (I/O/Z)
L3
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
K4
M4
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
see the Device Configurations section of this datasheet).
UXDATA1/MTXD1/
RMTXD1
L4
UXDATA0/MTXD0/
RMTXD0
M1
UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE
Source clock for UTOPIA receive driven by Master ATM Controller.
URCLK/MRCLK
H1
J4
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive clock. MACSEL[1:0] dependent.
Receive cell available status output signal from UTOPIA Slave.
0 indicates NO space is available to receive a cell from Master ATM Controller
1 indicates space is available to receive a cell from Master ATM Controller
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII carrier sense [default] or RMII carrier sense/data valid or GMII
carrier sense. MACSEL[1:0] dependent. MACSEL[1:0] dependent.
URCLAV/MCRS/
RMCRSDV
I/O/Z
UTOPIA receive interface enable input signal. Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid. MACSEL[1:0] dependent.
URENB/MRXDV
H5
H4
I/O/Z
I/O/Z
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller
to indicate to the UTOPIA Slave that the first valid byte of the cell is available to
sample on the 8-bit Receive Data Bus (URDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or RMII or GMII receive error. MACSEL[1:0]
dependent.
URSOC/MRXER/
RMRXER
URADDR4/PCBE0/
GP[2]
UTOPIA receive address pins [URADDR[4:0] (I)]:
As UTOPIA receive address pins, UTOPIA_EN (AEA12 pin) = 1:
P1
P2
P3
R5
I
I
I
I
•
5-bit Slave receive address input pins driven by the Master ATM Controller
to identify and select one of the Slave devices (up to 31 possible) in the
ATM System.
URADDR3/PREQ/
GP[15]
URADDR2/PINTA/
GP[14]
•
When the UTOPIA peripheral is disabled [UTOPIA_EN (AEA12 pin) = 0],
these pins are PCI (if PCI_EN = 1) or GPIO (if PCI_EN = 0) pins
(GP[15:12, 2]).
URADDR1/PRST/
GP[13]
As PCI peripheral pins:
PCI command/byte enable 0 (PCBE0) [I/O/Z]
PCI bus request (PREQ) [O/Z],
PCI interrupt A (PINTA) [O/Z],
PCI reset (PRST) [I], and
URADDR0/PGNT/
GP[12]
R4
I
PCI bus grant (PGNT) [I/O/Z].
URDATA7/MRXD7
URDATA6/MRXD6
URDATA5/MRXD5
URDATA4/MRXD4
URDATA3/MRXD3
URDATA2/MRXD2
M2
H2
L2
L1
J3
UTOPIA 8-bit Receive Data Bus (I/O/Z) [default] or EMAC receive data bus
[MII] [default] (I/O/Z) or [GMII] (I/O/Z) or [RMII] (I/O/Z)
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details,
see the Device Configuration section of this document).
J1
URDATA1/MRXD1/
RMRXD1
H3
J2
URDATA0/MRXD0/
RMRXD0
Device Overview
35
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
RAPID I/O SERIAL PORT
RIOCLK
RIOCLK
RIOTX3
RIOTX2
RIOTX1
RIOTX0
RIOTX3
RIOTX2
RIOTX1
RIOTX0
RIORX3
RIORX2
RIORX1
RIORX0
RIORX3
RIORX2
RIORX1
RIORX0
AF15
AG15
AF17
AG18
AG22
AF23
AF18
AG19
AG21
AF22
AH18
AJ18
AJ22
AH22
AH17
AJ19
AJ21
AH23
I
I
Rapid I/O serial port source (reference) clock
Negative Rapid I/O serial port source (reference) clock
O/Z
Rapid IO transmit data bus bits [3:0] (differential)
Rapid IO negative transmit data bus bits [3:0] (differential)
Rapid IO receive data bus bits [3:0] (differential)
O/Z
I
I
Rapid IO negative receive data bus bits [3:0] (differential)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR MII/RMII/GMII
UTOPIA transmit address pin (UXADDR4) (I) 4 or MDIO serial clock (MDCLK)
(O)
UXADDR4/MDCLK
UXADDR3/MDIO
M5
N3
I/O/Z
I/O/Z
IPD
IPU
UTOPIA transmit address pin 3 (UXADDR3) (I) or MDIO serial data (MDIO)
(I/O)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR RGMII
RGMDCLK
RGMDIO
B4
A4
O/Z
I/O/Z
MDIO serial clock (RGMII mode) (RGMDCLK) (O)
MDIO serial data (RGMII mode) (RGMDIO) (I/O)
ETHERNET MAC (EMAC) [MII/RMII/GMII]
If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configuration pins —
the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC/MDIO interface.
For more detailed information on the EMAC configuration pins, see the Device Configuration section of this document.
UTOPIA receive clock (URCLK) driven by Master ATM Controller (I) or when
the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is
EMAC receive clock (MRCLK) for MII [default] or GMII. MACSEL[1:0]
dependent.
URCLK/MRCLK
H1
I
UTOPIA receive cell available status output signal from UTOPIA Slave (O) or
when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC carrier sense (MCRS) (I) for MII [default] or GMII, or EMAC carrier
sense/receive data valid (RMCRSDV) (I) for RMII. MACSEL[1:0] dependent.
URCLAV/MCRS/
RMCRSDV
J4
I/O/Z
I
UTOPIA receive Start-of-Cell signal (I) or when the UTOPIA peripheral is
disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is EMAC receive error
(MRXIR) (I) for MII [default], RMII, or GMII. MACSEL[1:0] dependent.
URSOC/MRXER/
RMRXER
H4
UTOPIA receive interface enable input signal (I). Asserted by the Master ATM
Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
URENB/MRXDV
H5
I
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC MII [default] or GMII receive data valid (MRXDV) (I). MACSEL[1:0]
dependent.
36
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
TYPE(1) IPD/IPU(2)
DESCRIPTION
NAME
NO.
M2
H2
L2
URDATA7/MRXD7
URDATA6/MRXD6
URDATA5/MRXD5
URDATA4/MRXD4
URDATA3/MRXD3
URDATA2/MRXD2
UTOPIA 8-bit Receive Data Bus (I) [default] or EMAC receive data bus for MII
[default], RMII, or GMII
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the
URCLK) can receive the 8-bit ATM cell data from the Master ATM Controller.
L1
J3
I
J1
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC receive data pins for MII [default], RMII, or GMII
(MRXD[x:0]) (I). MACSEL[1:0] dependent.
URDATA1/MRXD1/
RMTXD1
H3
J2
URDATA0/MRXD0/
RMTXD0
Transmit cell available status output signal from UTOPIA slave (O).
•
•
0 indicates a complete cell is NOT available for transmit
1 indicates a complete cell is available for transmit
UXCLAV/GMTCLK
K5
N4
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is EMAC GMII transmit clock (GMTCLK) (O). MACSEL[1:0] dependent.
UTOPIA transmit source clock (UXCLK) driven by Master ATM Controller (I) or
when the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is either EMAC MII [default] or GMII transmit clock (MTCLK) (I) or the
EMAC RMII reference clock (RMREFCLK) (I). The EMAC function is controlled
by the MACSEL[1:0] (AEA[10:9] pins). For more detailed information, see the
Device Configuration section of this datasheet.
UXCLK/MTCLK/
RMREFCLK
I
UTOPIA transmit Start-of-Cell signal (O). This signal is output by the UTOPIA
Slave on the rising edge of the UXCLK, indicating that the first valid byte of the
cell is available on the 8-bit Transmit Data Bus (UXDATA[7:0]).
UXSOC/MCOL
K3
J5
I/O/Z
I/O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
pin is the EMAC collision sense (MCDL) (I) for MII [default] or GMII.
MACSEL[1:0] dependent.
UTOPIA transmit interface enable input signal [default] (I) or when the UTOPIA
peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the
EMAC transmit enable (MTXEN) (O) for MII [default], RMII, or GMII.
MACSEL[1:0] dependent.
UXENB/MTXEN/
RMTXEN
UXDATA7/MTXD7
UXDATA6/MTXD6
UXDATA5/MTXD5
UXDATA4/MTXD4
UXDATA3/MTXD3
UXDATA2/MTXD2
N5
M3
L5
UTOPIA 8-bit transmit data bus (O) [default] or EMAC transmit data bus for MII
[default], RMII, or GMII.
L3
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
K4
M4
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
pins function as EMAC transmit data pins (MTXD[x:0]) (O) for MII, RMII, or
GMII. MACSEL[1:0] dependent.
UXDATA1/MTXD1/
RMTXD1
L4
UXDATA0/MTXD0/
RMTXD0
M1
Device Overview
37
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
ETHERNET MAC (EMAC) [RGMII]
If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configuration pins —
the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC/MDIO interface.
For more detailed information on the EMAC configuration pins, see the Device Configuration section of this document.
RGMII reference clock (O). This 125-MHz reference clock is provided as a
convenience. It can be used as a clock source to a PHY, so that the PHY may
RGREFCLK
C4
O/Z
O/Z
generate RXC clock to communicate with the EMAC. This clock is stopped
while the device is in reset. This pin is available only when RGMII mode is
selected ( MACSEL[1:0] =11).
RGMII transmit clock (O). This pin is available only when RGMII mode is
selected (MACSEL[1:0] =11).
RGTXC
D4
RGTXD3
RGTXD2
RGTXD1
RGTXD0
A2
C3
B3
A3
RGMII transmit data [3:0] (O). This pin is available only when RGMII mode is
selected (MACSEL[1:0] =11).
O/Z
RGMII transmit enable (O). This pin is available only when RGMII mode is
selected (MACSEL[1:0] =11).
RGTXCTL
RGRXC
D3
E3
O/Z
I
RGMII receive clock (I). This pin is available only when RGMII mode is selected
(MACSEL[1:0] =11).
RGRXD3
RGRXD2
RGRXD1
RGRXD0
C1
E4
E2
E1
I
I
I
I
RGMII receive data [3:0] (I). This pin is available only when RGMII mode is
selected (MACSEL[1:0] =11).
RGMII receive control (I). This pin is available only when RGMII mode is
selected (MACSEL[1:0] =11).
RGRXCTL
C2
I
RESERVED FOR TEST
RSV01
RSV02
RSV03
RSV04
RSV05
N1
V5
Reserved. These pins must be connected directly to Core Supply (CVDD) for
proper device operation
W3
N11
P11
Reserved. This pin must be connected directly to 3.3-V I/O Supply (DVDD33) for
proper device operation.
RSV06
RSV07
L6
G4
I
I
I
Reserved. This pin must be connected directly to 1.5-/1.8-V I/O Supply
(DVDD15) for proper device operation.
Note: If the EMAC RGMII is not used, these pins can be connected directly to
ground (VSS) .
RSV08
F3
RSV09
RSV10
D26
A26
Reserved. This pin must be connected directly to 1.8-V I/O Supply (DVDD18) for
proper device operation.
Reserved. This pin must be connected to ground (VSS) via a 200-Ω resistor for
proper device operation.
RSV11
RSV12
RSV13
D24
C24
F2
Reserved. This pin must be connected to the 1.8-V I/O supply (DVDD18) via a
200-Ω resistor for proper device operation.
Reserved.This pin must be connected to ground (VSS) via a 200-Ω resistor for
proper device operation.
Reserved. If EMAC RGMII is used, this pin must be connected to the 1.5/1.8-V
I/O supply (DVDD15) via a 200-Ω resistor directly for proper device operation. If
EMAC RGMII is not used, this pin can be connected to the 1.8-V I/O supply
(DVDD18) via a 200-Ω resistor for proper device operation.
RSV14
F1
Reserved. This pin must be connected via a 39-Ω resistor directly to ground
(VSS) for proper device operation.
RSV15
RSV16
T1
T2
Reserved. This pin must be connected via a 20-Ω resistor directly to 3.3-V I/O
Supply (DVDD33) for proper device operation.
38
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AE21
E13
F18
U29
A6
RSV17
RSV18
RSV19
RSV20
RSV21
RSV22
RSV23
RSV24
RSV25
RSV26
RSV27
RSV36
RSV37
RSV38
RSV39
RSV40
RSV41
RSV42
RSV43
RSV44
RSV28
RSV29
RSV30
RSV31
RSV32
RSV33
RSV34
RSV35
A
A
A
A
A
O
O
O
O
A
A
B26
C26
B6
C6
AJ11
AH11
AD11
AD9
AG10
AG11
AJ12
W28
Y26
Y25
Y27
N7
Reserved. (Leave unconnected, do not connect to power or ground.)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
O/Z
O/Z
O/Z
A
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
N6
A
P23
P24
D25
C25
E6
A
A
Reserved. These pins must be connected directly to VSS for proper device
operation.
I
IPD
IPD
IPD
IPD
I
I
D6
I
SUPPLY VOLTAGE PINS
(DVDD18/2)-V reference for SSTL buffer (DDR2 Memory Controller). This input
voltage can be generated directly from DVDD18 using two 1-KΩ resistors to form
a resistor divider circuit.
NOTE: This reference voltage must be supplied even if the DDR2 Memory
Controller peripheral is not used.
VREFSSTL
C14
A
A
(DVDD15/2)-V reference for HSTL buffer (EMAC RGMII). This input voltage can
be generated directly from DVDD15 using two 1-KΩ resistors to form a resistor
divider circuit.
NOTE: If the RGMII mode of the EMAC is not used, this pin must be connected
to a voltage of DVDD18/2. This input voltage can be generated directly from
DVDD18 using two 1-KΩ resistors to form a resistor divider circuit.
VREFHSTL
B2
1.8-V I/O supply voltage (SRIO regulator supply).
NOTE: If Rapid I/O is not used, this pin can be connected directly to VSS
DVDDR
AVDDA
AD20
S
A
.
AC15
AC17
AD16
A13
1.2-V I/O supply voltage (SRIO analog supply).
Do not use core supply.
NOTE: If Rapid I/O is not used, these pins can be connected directly to VSS
.
AVDLL1
AVDLL2
A
1.8-V I/O supply voltage.
E18
Device Overview
39
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
U16
V15
V17
W16
1.2-V I/O supply voltage (SRIO interface supply). The source for this supply
voltage must be the same as that of CVDD
DVDDRM
S
.
NOTE: If Rapid I/O is not used, these pins can be connected directly to VSS
.
.
1.2-V I/O supply voltage (Main SRIO supply)
Do not use core supply.
NOTE: If Rapid I/O is not used, these pins can be connected directly to VSS
DVDD12
S
A
W18
AE17
AE19
AE23
AF20
AH20
AJ17
AJ23
A1
1.2-V I/O supply voltage (SRIO termination supply)
Do not use core supply.
NOTE: If Rapid I/O is not used, these pins can be connected directly to VSS
AVDDT
.
B5
D2
1.8-V or 1.5-V I/O supply voltage (EMAC RGMII)
NOTE: If EMAC RGMII is not used, these pins must be connected to the
DVDD18 supply.
DVDD15
D5
S
F5
G6
H7
B8
B11
B20
B23
E10
E12
E22
E24
F7
F11
F13
F15
F17
F19
F23
G8
DVDD18
S
1.8-V I/O supply voltage (DDR2 Memory Controller)
G10
G12
G14
G16
G18
G20
G22
G24
40
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
A29
E26
E28
G2
H23
H28
J6
J24
K1
K7
K23
L24
M7
M23
M28
N24
P6
P28
R1
R6
R23
T7
DVDD33
S
3.3-V I/O supply voltage
T24
U23
V1
V7
V24
W23
Y7
Y24
AA1
AA6
AA23
AB7
AB24
AC6
AC9
AC11
AC13
AC19
AC21
AC23
AC29
Device Overview
41
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AD5
AD7
AD14
AD18
AD22
AD24
AE6
AE8
AE15
AF1
AF16
AF24
AG12
AG17
AG23
AH14
AH16
AH24
AJ1
DVDD33
S
3.3-V I/O supply voltage
AJ7
AJ15
AJ25
AJ29
L12
L14
L16
L18
M11
M13
M15
M17
M19
N12
CVDD
S
1.2-V core supply voltage
N14
N16
N18
P13
P15
P17
P19
R12
R14
R16
42
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
R18
T11
T13
T15
T17
T19
U12
U14
U18
V11
V13
V19
W12
W14
CVDD
S
1.2-V core supply voltage
GROUND PINS
A8
A11
A20
A23
B1
B29
C5
D1
E5
E7
VSS
GND
Ground pins
E19
E25
E29
F4
F6
F8
F10
F12
F14
F16
Device Overview
43
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
F20
F22
F24
G1
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
H6
H24
H29
J7
VSS
GND
Ground pins
J23
K2
K6
K24
L7
L11
L13
L15
L17
L19
L23
M6
M12
M14
44
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
M16
M18
M24
M26
M29
N2
N13
N15
N17
N19
N23
P7
P12
P14
P16
P18
P29
R2
VSS
GND
Ground pins
R7
R11
R13
R15
R17
R19
R24
T6
T12
T14
T16
T18
T23
U7
U11
U13
Device Overview
45
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
U15
U17
U19
U24
V2
V6
V12
V14
V16
V18
V23
W7
W11
W13
W15
W17
W19
W24
Y6
VSS
GND
Ground pins
Y23
AA2
AA7
AA24
AB6
AB23
AC7
AC8
AC10
AC12
AC14
AC16
AC18
46
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
DESCRIPTION
NO.
AC20
AC22
AC24
AC28
AD6
AD13
AD15
AD17
AD19
AD21
AD23
AE4
AE7
AE16
AE18
AE20
AE22
AE24
AF2
VSS
GND
Ground pins
AF19
AF21
AG13
AG16
AG20
AG24
AH1
AH15
AH19
AH21
AH25
AH29
AJ8
AJ14
AJ16
AJ20
AJ24
Device Overview
47
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
2.8 Development
2.8.1 Development Support
In case the customer would like to develop their own features and software on the C6455 device, TI offers
an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate
and debug software and hardware modules. The tool's support documentation is electronically available
within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of C6000™ DSP-based applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any DSP application.
Hardware Development Tools: Extended Development System (XDS™) Emulator (supports C6000™
DSP multiprocessor system debug) EVM (Evaluation Module)
2.8.2 Device Support
2.8.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMX320C6455ZTZ). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
48
Device Overview
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZTZ), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range in megahertz (for example, 1 is 1 GHz). Figure 2-13
provides a legend for reading the complete device name for any TMS320C64x+™ DSP generation
member.
For device part numbers and further ordering information for TMS320C6455 in the ZTZ package type, see
the TI website ( www.ti.com) or contact your TI sales representative.
TMX
320
C6455
ZTZ
7
DEVICE SPEED RANGE
7 = 720 MHz
PREFIX
TMX = Experimental device
TMS = Qualified device
8 = 850 MHz
Blank = 1 GHz
(A)
PACKAGE TYPE
ZTZ = 697-pin plastic BGA, with Pb-Free soldered balls
DEVICE FAMILY
320 = TMS320t DSP family
DEVICE
C64x+tDSP:
C6455
A. BGA = Ball Grid Array
Figure 2-13. TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6455 DSP)
2.8.2.2 Documentation Support
The following documents describe the TMS320C6455 Fixed-Point Digital Signal Processor. Copies of
these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the TMS320C6455, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871
SPRU965
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
C64x+ DSP Technical Overview. Covers the features of the C6455 DSP and describes
how, while utilizing the C64x+ core, it extends the performance by offering greater
multiplication bandwidth, higher I/O bandwidth,and larger and more flexible on-chip memory
while addressing code size and system issues.
SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRU889
High-Speed DSP Systems Design Reference Guide. Provides recommendations for
meeting the many challenges of high-speed DSP system design. These recommendations
include information about DSP audio, video, and communications systems for the C5000 and
C6000 DSP platforms.
Device Overview
49
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
3 Device Configuration
On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, are
selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset.
By default, the peripherals on the C6455 device are disabled and need to be enabled by software before
being used.
3.1 Device Configuration at Device Reset
Table 3-1 describes the C6455 device configuration pins. The logic level of the AEA[19:0], ABA[1:0], and
PCI_EN pins is latched at reset to determine the device configuration. The logic level on the device
configuration pins can be set by using external pullup/pulldown resistors or by using some control device
(e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to
ensure there is no contention on the lines when the device is out of reset. The device configuration pins
are sampled during reset and are driven after the reset is removed. At this time, the control device should
ensure it has stopped driving the device configuration pins of the DSP to again avoid contention.
NOTE
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN)
CONFIGURATION
PIN
IPD/
NO.
FUNCTIONAL DESCRIPTION
IPU(1)
Boot Mode Selections (BOOTMODE [3:0]).
These pins select the boot mode for the device.
0000
0001
0010
0011
0100
0101
0110
0111
No boot (default mode)
Host boot (HPI)
Reserved
Reserved
[N25,
L26,
L25,
P26]
EMIFA 8-bit ROM boot
Master I2C boot
Slave I2C boot
Host boot (PCI)
AEA[19:16]
IPD
1000 thru Serial Rapid I/O boot configurations
1111
If selected for boot, the corresponding peripheral is automatically enabled after device reset.
For more detailed information on boot modes, see Section 2.4, Boot Sequence, of this
document.
EMIFA input clock source select (AECLKIN_SEL).
0
1
AECLKIN (default mode)
AEA15
AEA14
P27
R25
IPD
IPD
SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable
via the Software PLL1 Controller. By default, SYSCLK4 is selected as CPU/8
clock rate.
HPI peripheral bus width select (HPI_WIDTH).
0
HPI operates in HPI16 mode (default).
HPI bus is 16 bits wide; HD[15:0] pins are used and the remaining HD[31:16]
pins are reserved pins in the Hi-Z state.
1
HPI operates in HPI32 mode.
HPI bus is 32 bits wide; HD[31:0] pins are used.
Applies only when HPI function of HPI/PCI multiplexed pins is selected (PCI_EN pin = 0).
(1) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-kΩ resistor should be used.)
50
Device Configuration
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU(1)
Device Endian mode (LENDIAN).
AEA13
R27
IPU
0
1
System operates in Big Endian mode.
System operates in Little Endian mode (default).
UTOPIA pin function enable bit (UTOPIA_EN).
This pin selects the function of the UTOPIA/EMAC and UTOPIA/MDIO multiplexed pins.
0
UTOPIA pin function disabled; EMAC and MDIO pin function enabled (default).
This means all multiplexed UTOPIA/EMAC and UTOPIA/MDIO pins function as
EMAC and MDIO pins. The interface used by EMAC/MDIO (MII, RMII, GMII or
the standalone RGMII) is controlled by the MACSEL[1:0] pins (AEA[10:9]).
AEA12
AEA11
R28
T25
IPD
IPD
1
UTOPIA pin function enabled; EMAC and MDIO pin function disabled.
This means all multiplexed UTOPIA/EMAC and UTOPIA/MDIO pins now function
as UTOPIA. The EMAC/MDIO peripheral can still be used with RGMII
(MACSEL[1:0] = 11).
For proper C6455 device operation, this pin must be externally pulled up with a 1-kΩ resistor
at device reset.
EMAC Interface Selects (MACSEL[1:0]).
These pins select the interface used by the EMAC/MDIO peripheral.
00
01
10
11
10/100 EMAC/MDIO with MII Interface [default]
10/100 EMAC/MDIO with RMII Interface
10/100/1000 EMAC/MDIO with GMII Interface
10/100/1000 EMAC/MDIO with RGMII Interface
[M25,
M27]
AEA[10:9]
IPD
If the UTOPIA pin function is selected [UTOPIA_EN (AEA12 pin) = 1] for multiplexed
UTOPIA/EMAC and UTOPIA/MDIO pins, the EMAC/MDIO peripheral can only be used with
RGMII.
For more detailed information on the UTOPIA_EN and MAC_SEL[1:0] control pin selections,
see Table 3-3.
PCI I2C EEPROM Auto-Initialization (PCI_EEAI).
PCI auto-initialization via external I2C EEPROM
0
PCI auto-initialization through external I2C EEPROM is disabled. The PCI
peripheral uses the specified PCI default values (default).
AEA8
P25
IPD
1
PCI auto-initialization through external I2C EEPROM is enabled. The PCI
peripheral is configured through external I2C EEPROM provided the PCI
peripheral pins are enabled (PCI_EN = 1).
Note: If the PCI pin function is disabled (PCI_EN pin = 0), this pin must not be pulled up.
AEA7
AEA6
N27
U27
IPD
IPD
For proper C6455 device operation, do not oppose the IPD on this pin.
PCI Frequency Selection (PCI66).
Selects the operating frequency of the PCI (either 33 MHz or 66 MHz).
0
1
PCI operates at 33 MHz (default)
PCI operates at 66 MHz
Note: If the PCI pin function is disabled (PCI_EN pin = 0), this pin must not be pulled up.
McBSP1 pin function enable bit (MCBSP1_EN).
Selects which function is enabled on the McBSP1/GPIO multiplexed pins.
0
GPIO pin function enabled (default).
This means all multiplexed McBSP1/GPIO pins function as GPIO pins.
AEA5
U28
IPD
1
McBSP1 pin function enabled.
This means all multiplexed McBSP1/GPIO pins function as McBSP1 pins.
SYSCLKOUT Enable bit (SYSCLKOUT_EN).
Selects which function is enabled on the SYSCLK4/GP[1] muxed pin.
AEA4
AEA3
T28
T27
IPD
IPD
0
1
GP[1] pin function is enabled (default)
SYSCLK4 pin function is enabled
For proper C6455 device operation, this pin must be externally pulled up with a 1-kΩ
resistor at device reset.
Device Configuration
51
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued)
CONFIGURATION
IPD/
NO.
FUNCTIONAL DESCRIPTION
PIN
IPU(1)
Configuration General-Purpose Inputs (CFGGP[2:0])
[T26,
U26,
U25]
The value of these pins is latched to the Device Status Register following device reset and is
used by the on-chip bootloader for some boot modes. For more information on the boot
modes, see Section 2.4, Boot Sequence, of this document.
AEA[2:0]
IPD
IPD
PCI pin function enable bit (PCI_EN).
Selects which function is enabled on the HPI/PCI and the PCI/UTOPIA multiplexed pins.
0
HPI and UTOPIA pin function enabled (default)
This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as HPI and
UTOPIA pins, respectively.
PCI_EN
Y29
1
PCI pin function enabled
This means all multiplexed HPI/PCI and PCI/UTOPIA pins function as PCI pins.
DDR2 Memory Controller enable (DDR2_EN).
ABA0
ABA1
V26
V25
IPD
IPD
0
1
DDR2 Memory Controller peripheral pins are disabled (default)
DDR2 Memory Controller peripheral pins are enabled
EMIFA enable (EMIFA_EN).
0
1
EMIFA peripheral pins are disabled (default)
EMIFA peripheral pins are enabled
3.2 Peripheral Configuration at Device Reset
Some C6455 peripherals share the same pins (internally multiplexed) and are mutually exclusive.
Therefore, not all peripherals may be used at the same time. The device configuration pins described in
the Device Configuration at Device Reset section determine which function is enabled for the multiplexed
pins.
Note that when the pin function of a peripheral is disabled at device reset, the peripheral is permanently
disabled and cannot be enabled until its pin function is enabled and another device reset is executed.
Also, note that enabling the pin function of a peripheral does not enable the corresponding peripheral. All
peripherals on the C6455 device are disabled by default, except when used for boot, and must be enabled
through software before being used.
Other peripheral options like PCI clock speed and EMAC/MDIO interface mode can also be selected at
device reset through the device configuration pins. The configuration selected is also fixed at device reset
and cannot be changed until another device reset is executed with a different configuration selected.
The multiply factor of the PLL1 Controller is not selected through the configuration pins. The PLL1 multiply
factor is set in software through the PLL1 controller registers after device reset. The PLL2 multiply factor is
fixed. Refer to the PLL1 and PLL1 Controller and PLL2 and PLL2 Controller sections of this document for
more information.
On the C6455 device, the PCI peripheral pins are multiplexed with the HPI pins and partially multiplexed
with the UTOPIA pins. The PCI_EN pin selects the function for the HPI/PCI multiplexed pins. The PCI66,
PCI_EEAI, and HPI_WIDTH control other functions of the PCI and HPI peripherals. Table 3-2 describes
the effect of the PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH configuration pins.
52
Device Configuration
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI)
CONFIGURATION PIN SETTING(1)
PERIPHERAL FUNCTION SELECTED
PCI66
AEA6 PIN
[U27]
PCI_EEAI
AEA8 PIN
[P25](1)
HPI_WIDTH
AEA14 PIN
[R25]
PCI_EN PIN
[Y29]
HPI DATA
LOWER
HPI DATA
UPPER
32-BIT PCI
(66-/33-MHz)
PCI
AUTO-INIT
0
0
0
0
0
0
0
1
Enabled
Enabled
Hi-Z
Disabled
Disabled
N/A
N/A
Enabled
Enabled
(via External I2C
EEPROM)
1
1
1
X
Disabled
Enabled
(66 MHz)
1
1
1
0
0
0
X
X
Disabled
Disabled
Disabled
Disabled
(default values)
Enabled
(33 MHz)
Enabled
(via External I2C
EEPROM)
1
0
1
X
Disabled
(1) PCI_EEAI is latched at reset as a configuration input. If PCI_EEAI is set as one, then default values are loaded from an external I2C
EEPROM.
The UTUPIA and EMAC/MDIO pins are also multiplexed on the C6455 device. The UTOPIA_EN function
(AEA12 pin) controls the function of these multiplexed pins. The MAC_SEL[1:0] configuration pins
(AEA[10:9) control which interface is used by the EMAC/MDIO. Note that since the PCI shares some pins
with the UTOPIA peripheral, its state also affects the operation of the UTOPIA. Table 3-3 describes the
effect of the UTOPIA_EN, PCI_EN, and MACSEL[1:0] configuration pins.
Table 3-3. UTOPIA_EN, and MAC_SEL[1:0] Peripheral Selection (UTOPIA and EMAC)
CONFIGURATION PIN SETTING
PERIPHERAL FUNCTION SELECTED
EMAC/MDIO UTOPIA
MAC_SEL[1:0]
UTOPIA_EN
PCI_EN PIN
[Y29]
AEA[10:9] PINS
[M25, M27]
AEA12 PIN [R28]
10/100 EMAC/MDIO with MII Interface
[default]
0
0
0
x
x
x
00b
01b
10b
11b
Disabled
Disabled
Disabled
Disabled
10/100 EMAC/MDIO with RMII
Interface
10/100/1000 EMAC/MDIO with GMII
Interface
10/100/1000 EMAC/MDIO with RGMII
Interface(1)
0
1
1
x
0
0
00b, 01b, or 10b Disabled
10/100/1000 EMAC/MDIO with RGMII
Interface(1)
UTOPIA Slave with Full Functionality
UTOPIA Slave with Full Functionality
11b
UTOPIA Slave with Single PHY Mode
Only
1
1
1
1
00b, 01b, or 10b Disabled
10/100/1000 EMAC/MDIO with RGMII UTOPIA Slave with Single PHY Mode
Interface(1)
Only
11b
(1) RGMII interface requires a 1.5-/1.8-V I/O supply.
Device Configuration
53
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
3.3 Peripheral Selection After Device Reset
On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4.
Table 3-4. Peripheral States
PERIPHERALS THAT CAN BE
STATE
DESCRIPTION
IN THIS STATE
HPI
PCI
Peripheral pin function has been completely
disabled through the device configuration
pins. Peripheral is held in reset and clock is
turned off.
McBSP1
UTOPIA
EMAC/MDIO
McBSP0
Static powerdown
EMIFA
DDR2 Memory Controller
TCP
VCP
I2C
Timer 1
Timer 2
GPIO
EMAC/MDIO
McBSP0
McBSP1
HPI
Peripheral is held in reset and clock is turned
off. Default state for all peripherals not in
static powerdown mode.
Disabled
PCI
UTOPIA
TCP
VCP
I2C
Timer 1
Timer 2
GPIO
Clock to the peripheral is turned on and the
peripheral is taken out of reset.
Enabled
MDIO
EMAC/MDIO
McBSP1
McBSP2
HPI
PCI
UTOPIA
Not a user-programmable state. This is an
intermediate state when transitioning from an
disabled state to an enabled state.
All peripherals that can be in an
enabled state.
Enable in progress
Following device reset, all peripherals that are not in the static powerdown state are in the disabled state
by default. Peripherals used for boot such as HPI and PCI are enabled automatically following a device
reset.
Peripherals are only allowed certain transitions between states (see Figure 3-1).
54
Device Configuration
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Fixed-Point Digital Signal Processor
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Static
Powerdown
Reset
Enable In
Progress
Disabled
Enabled
Figure 3-1. Peripheral Transitions Between States
Figure 3-2 shows the flow needed to change the state of a given peripheral on the C6455 device.
Unlock the PERCFG0 register by
using the PERLOCK register.
Write to the PERCFG0 register
within 16 SYSCLK3 clock cycles
to change the state of the
peripherals.
Poll the PERSTAT registers to
verify state change.
Figure 3-2. Peripheral State Change Flow
A 32-bit key (value = 0x0F0A 0B00) must be written to the Peripheral Lock register (PERLOCK) in order to
allow access to the PERCFG0 register. Writes to the PERCFG1 register can be done directly without
going through the PERLOCK register.
Device Configuration
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3.4 Device State Control Registers
The C6455 device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 3-5 and described in the next sections.
NOTE
The device state control registers can only be accessed using the CPU or the emulator.
Table 3-5. Device State Control Registers
HEX ADDRESS RANGE
02AC 0000
ACRONYM
REGISTER NAME
-
Reserved
02AC 0004
PERLOCK
Peripheral Lock Register
Peripheral Configuration Register 0
Reserved
02AC 0008
PERCFG0
02AC 000C
-
02AC 0010
-
Reserved
02AC 0014
PERSTAT0
Peripheral Status Register 0
Peripheral Status Register 1
Reserved
02AC 0018
PERSTAT1
02AC 001C - 02AC 001F
02AC 0020
-
EMACCFG
EMAC Configuration Register
Reserved
02AC 0024 - 02AC 002B
02AC 002C
-
PERCFG1
Peripheral Configuration Register 1
Reserved
02AC 0030 - 02AC 0053
02AC 0054
-
EMUBUFPD
-
Emulator Buffer Powerdown Register
Reserved
02AC 0058
3.4.1 Peripheral Lock Register Description
When written with correct 32-bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one
write to the PERCFG0 register within 16 SYSCLK3 cycles.
31
0
LOCKVAL
R/W-F0F0 F0F0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 3-3. Peripheral Lock Register (PERLOCK) - 0x02AC 0000
Table 3-6. Peripheral Lock Register (PERLOCK) Field Descriptions
Bit
Field
Value Description
31:0
LOCKVAL
When programmed with 0x0F0A 0B00 allows one write to the PERCFG0 register within 16
SYSCLK3 clock cycles.
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3.4.2 Peripheral Configuration Register 0 Description
The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. This is a
write-only register; reads are undefined. The state of the peripherals can be read from the Peripheral
Status Registers (PERSTAT0 and PERSTAT1).
31
30
29
24
SRIOCTL
W-0
Reserved
W-0
23
22
21
20
19
18
17
16
Reserved
W-0
UTOPIACTL
Reserved
PCICTL
Reserved
HPICTL
Reserved
McBSP1CTL
W-0
W-0
W-0
W-0
W-0
W-0
W-0
15
14
13
12
11
10
9
8
Reserved
McBSP0CTL
Reserved
I2CCTL
Reserved
GPIOCTL
Reserved
TIMER1CTL
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
7
6
5
4
3
2
1
0
Reserved
TIMER0CTL
Reserved
EMACCTL
Reserved
VCPCTL
Reserved
TCPCTL
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
LEGEND: W = Write only; -n = value after reset
Figure 3-4. Peripheral Configuration Register 0 (PERCFG0) - 0x02AC 0008
Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions
Bit
Field
Value Description
31-30 SRIOCTL
Mode control for SRIO. SRIO does not have a corresponding status bit in the Peripheral Status
Registers. Once SRIOCTL is set to 11b, the SRIO peripheral can be used within 16 SYSCLK3
cycles.
00b
11b
Set SRIO to disabled mode
Set SRIO to enabled mode
29:23 Reserved
Reserved.
22
UTOPIACTL
Mode control for UTOPIA
0
1
Set UTOPIA to disabled mode
Set UTOPIA to enabled mode
21
20
Reserved
PCICTL
Reserved.
Mode control for PCI. This bit defaults to 1 when Host boot is used (BOOTMODE[3:0] = 0111b).
0
1
Set PCI to disabled mode
Set PCI to enabled mode
19
18
Reserved
HPICTL
Reserved.
Mode control for HPI. This bit defaults to 1 when Host boot is used (BOOTMODE[3:0] = 0001b).
0
1
1
Set HPI to disabled mode
Set HPI to enabled mode
Reserved.
17
16
Reserved
McBSP1CTL
Mode control for McBSP1
Set McBSP1 to disabled mode
Set McBSP1 to enabled mode
Reserved.
0
1
15
14
Reserved
McBSP0CTL
Mode control for McBSP0
Set McBSP0 to disabled mode
Set McBSP0 to enabled mode
Reserved.
0
1
13
Reserved
Device Configuration
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Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued)
Bit
Field
Value Description
Mode control for I2C
12
I2CCTL
0
1
Set I2C to disabled mode
Set I2C to enabled mode
Reserved.
11
10
Reserved
GPIOCTL
Mode control for GPIO
Set GPIO to disabled mode
Set GPIO to enabled mode
Reserved.
0
1
9
8
Reserved
TIMER1CTL
Mode control for Timer1
Set Timer1 to disabled mode
Set Timer1 to enabled mode
Reserved.
0
1
7
6
Reserved
TIMER2CTL
Mode control for Timer2
Set Timer2 to disabled mode
Set Timer2 to enabled mode
Reserved.
0
1
5
4
Reserved
EMACCTL
Mode control for EMAC/MDIO
Set EMAC/MDIO to disabled mode
Set EMAC/MDIO to enabled mode
Reserved.
0
1
3
2
Reserved
VCPCTL
Mode control for VCP
Set VCP to disabled mode
Set VCP to enabled mode
Reserved.
0
1
1
0
Reserved
TCPCTL
Mode control for TCP
Set TCP to disabled mode
Set TCP to enabled mode
0
1
58
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Fixed-Point Digital Signal Processor
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3.4.3 Peripheral Configuration Register 1 Description
The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory
Controller. EMIFA and the DDR2 Memory Controller do not have corresponding status bits in the
Peripheral Status Registers. The EMIFA and DDR2 Memory Controller peripherals can be used within 16
SYSCLK3 cycles after EMIFACTL and DDR2CTL are set to 1. Once EMIFACTL and DDR2CTL are set to
1, they cannot be set to 0. Note that if the DDR2 Memory Controller and EMIFA are disabled at reset
through the device configuration pins (DDR2.EN[ABA0] and EMIFA[ABA1]), they cannot be enabled
through the PERCFG1 register.
31
8
Reserved
R-0x00
7
2
1
0
Reserved
R-0x00
DDR2CTL
EMIFACTL
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-5. Peripheral Configuration Register 1 (PERCFG1) - 0x02AC 002C
Table 3-8. Peripheral Configuration Register 1 (PERCFG1) Field Descriptions
Bit
31:2
1
Field
Value Description
Reserved
DDR2CTL
Reserved.
Mode Control for DDR2 Memory Controller. Once this bit is set to 1, it cannot be changed to 0.
0
1
Set DDR2 to disabled
Set DDR2 to enabled
0
EMIFACTL
Mode control for EMIFA. Once this bit is set to 1, it cannot be changed to 0. This bit defaults to 1 if
EMIFA 8-bit ROM boot is used (BOOTMODE[3:0] = 0100b).
0
1
Set EMIFA to disabled
Set EMIFA to enabled
Device Configuration
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3.4.4 Peripheral Status Registers Description
The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals.
31
30
29
27
26
24
Reserved
R-0
HPISTAT
R-0
McBSP1STAT
R-0
17
23
21
20
18
16
McBSP0STAT
I2CSTAT
R-0
GPIOSTAT
R-0
R-0
14
15
12
11
9
8
GPIOSTAT
TIMER1STAT
TIMER0STAT
EMACSTAT
R-0
7
R-0
5
R-0
2
R-0
0
6
3
EMACSTAT
R-0
LEGEND: R = Read only; -n = value after reset
VCPSTAT
R-0
TCPSTAT
R-0
Figure 3-6. Peripheral Status Register 0 (PERSTAT0) - 0x02AC 0014
Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions
Bit
Field
Value Description
Reserved.
31:30 Reserved
29:27 HPISTAT
HPI status
000
001
011
101
HPI is in the disabled state
HPI is in the enabled state
HPI is in the static powerdown state
HPI is in the enable in progress state
Others Reserved
McBSP1 status
26:24 McBSP1STAT
23:21 McBSP0STAT
20:18 I2CSTAT
000
001
011
101
McBSP1 is in the disabled state
McBSP1 is in the enabled state
McBSP1 is in the static powerdown state
McBSP1 is in the enable in progress state
Others Reserved
McBSP0 status
000
001
011
101
McBSP0 is in the disabled state
McBSP0 is in the enabled state
McBSP0 is in the static powerdown state
McBSP0 is in the enable in progress state
Others Reserved
I2C status
000
001
011
101
I2C is in the disabled state
I2C is in the enabled state
I2C is in the static powerdown state
I2C is in the enable in progress state
Others Reserved
60
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Fixed-Point Digital Signal Processor
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Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (continued)
Bit
Field
Value Description
17:15 GPIOSTAT
GPIO status
000
001
011
101
GPIO is in the disabled state
GPIO is in the enabled state
GPIO is in the static powerdown state
GPIO is in the enable in progress state
Others Reserved
Timer1 status
14:12 TIMER1STAT
000
001
011
101
Timer1 is in the disabled state
Timer1 is in the enabled state
Timer1 is in the static powerdown state
Timer1 is in the enable in progress state
Others Reserved
Timer0 status
11:9
8:6
5:3
2:0
TIMER0STAT
EMACSTAT
VCPSTAT
000
001
011
101
Timer0 is in the disabled state
Timer0 is in the enabled state
Timer0 is in the static powerdown state
Timer0 is in the enable in progress state
Others Reserved
EMAC/MDIO status
000
001
011
101
EMAC/MDIO is in the disabled state
EMAC/MDIO is in the enabled state
EMAC/MDIO is in the static powerdown state
EMAC/MDIO is in the enable in progress state
Others Reserved
VCP status
000
001
011
101
VCP is in the disabled state
VCP is in the enabled state
VCP is in the static powerdown state
VCP is in the enable in progress state
Others Reserved
TCP status
TCPSTAT
000
001
011
101
TCP is in the disabled state
TCP is in the enabled state
TCP is in the static powerdown state
TCP is in the enable in progress state
Others Reserved
Device Configuration
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31
16
Reserved
R-0
15
6
5
3
2
0
Reserved
UTOPIASTAT
R-0
PCISTAT
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018
Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions
Bit
31:6
5:3
Field
Value Description
Reserved
Reserved.
UTOPIASTAT
UTOPIA status
000
001
011
101
UTOPIA is in the disabled state
UTOPIA is in the enabled state
UTOPIA is in the static powerdown state
UTOPIA is in the enable in progress state
Others Reserved
PCI status
2:0
PCISTAT
000
001
011
101
PCI is in the disabled state
PCI is in the enabled state
PCI is in the static powerdown state
PCI is in the enable in progress state
Others Reserved
62
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Fixed-Point Digital Signal Processor
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3.4.5 EMAC Configuration Register (EMACCFG) Description
The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced
Media Independent Interface (RMII) logic of the EMAC. For more details on how to use this register, see
Section 7.14, Ethernet MAC (EMAC).
31
24
Reserved
R/W-0
23
20
19
18
16
Reserved
R/W-0
RMII_RST
Reserved
R/W-0
R/W-1
15
0
Reserved
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-8. EMAC Configuration Register (EMACCFG) - 0x02AC 0020
Table 3-11. EMAC Configuration Register (EMACCFG) Field Descriptions
Bit
Field
Value Description
31:20 Reserved
Reserved. Writes to this register must keep this bit as 0.
RMII reset bit. This bit is used to reset the RMII logic of the EMAC.
19
RMII_RST
Reserved
0
1
RMII logic reset is asserted.
RMII logic reset is released.
18:0
Reserved. Writes to this register must keep this bit as 0.
Device Configuration
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3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description
The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of
emulator pins EMU[18:2]. These buffers can be powered down if the device trace feature is not needed.
31
8
Reserved
R-0
7
1
0
Reserved
R-0
EMUCTL
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-9. Emulator Buffer Powerdown Register (EMUBUFPD) - 0x02AC 0054
Table 3-12. Emulator Buffer Powerdown Register (EMUBUFPD) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
EMUCTL
Reserved
Buffer powerdown for EMU[18:2] pins
Power-up buffers
0
1
Power-down buffers
64
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
3.5 Device Status Register Description
The device status register depicts the device configuration selected upon device reset. Once set, these
bits will remain set until a device reset. For the actual register bit names and their associated bit field
descriptions, see Figure 3-10 and Table 3-13.
Note that enabling or disabling peripherals through the Peripheral Configuration Registers (PERCFG0 and
PERCFG1) does not affect the DEVSTAT register. To determine the status of peripherals following writes
to the PERCFG0 and PERCFG1 registers, read the Peripherals Status Registers (PERSTAT0 and
PERSTAT1).
31
24
Reserved
R-0000 0000
23
22
21
20
19
18
17
16
Reserved
EMIFA_EN
DDR2_EN
PCI_EN
CFGGP2
CFGGP1
CFGGP0
Reserved
R-0
15
R-x
14
R-x
13
R-x
R-x
11
R-x
10
R-x
9
R-1
8
12
SYSCLKOUT_
EN
MCBSP1_EN
PCI66
Reserved
PCI_EEAI
MAC_SEL1
MAC_SEL0
Reserved
R-x
R-x
R-x
R-0
R-x
3
R-x
2
R-x
1
R-1
0
7
6
5
4
UTOPIA_EN
LENDIAN
HPI_WIDTH
AECLKINSEL
BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0
R-x
R-x
R-x
R-x
R-x R-x R-x R-x
LEGEND: R/W = Read/Write; R = Read only; -x = value after reset
Figure 3-10. Device Status Register (DEVSTAT) - 0x02A8 0000
Table 3-13. Device Status Register (DEVSTAT) Field Descriptions
Bit
Field
Value Description
31:23 Reserved
Reserved. Read-only, writes have no effect.
22
21
20
EMIFA_EN
DDR2_EN
PCI_EN
EMIFA Enable (EMIFA_EN) status bit
Shows the status of whether the EMIFA peripheral pins are enabled/disabled.
0
1
EMIFA peripheral pins are disabled (default)
EMIFA peripheral pins are enabled
DDR2 Memory Controller Enable (DDR2_EN) status bit
Shows the status of whether the DDR2 Memory Controller peripheral pins are enabled/disabled.
0
1
DDR2 Memory Controller peripheral pins are disabled (default)
DDR2 Memory Controller peripheral pins are enabled
PCI Enable (PCI_EN) status bit
Shows the status of which function is enabled on the HPI/PCI and PCI/UTOPIA multiplexed pins.
0
1
HPI and UTOPIA pin functions are enabled (default)
PCI pin functions are enabled
19:17 CFGGP[2:0]
Used as General-Purpose inputs for configuration purposes.
These pins are latched at reset. These values can be used by S/W routines for boot operations.
16
15
Reserved
Reserved. Read-only, writes have no effect.
SYSCLKOUT_EN
SYSCLKOUT Enable (SYSCLKOUT_EN) status bit
Shows the status of which function is enabled on the SYSCLK4/GP[1] muxed pin.
0
1
GP[1] pin function of the SYSCLK4/GP[1] pin enabled (default)
SYSCLK4 pin function of the SYSCLK4/GP[1] pin enabled
Device Configuration
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Fixed-Point Digital Signal Processor
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Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued)
Bit
Field
Value Description
14
MCBSP1_EN
McBSP1 Enable (MCBSP1_EN) status bit
Shows the status of which function is enabled on the McBSP1/GPIO muxed pins.
0
1
GPIO pin functions enabled (default)
McBSP1 pin functions enabled
13
PCI66
PCI Frequency Selection (PCI66) status bit
Shows the PCI operating frequency selected at reset.
0
1
PCI operates at 33 MHz (default)
PCI operates at 66 MHz
12
11
Reserved
PCI_EEAI
Reserved. Read-only, writes have no effect.
PCI I2C EEPROM Auto-Initialization (PCI_EEAI) status bit
Shows whether the PCI auto-initialization via external I2C EEPROM is enabled/disabled.
0
1
PCI auto-initialization through external I2C EEPROM is disabled; the PCI peripheral uses the
specified PCI default values (default).
PCI auto-initialization through external I2C EEPROM is enabled; the PCI peripheral is configured
through external I2C EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1).
10:9
MACSEL[1:0]
EMAC Interface Select (MACSEL[1:0]) status bits
Shows which EMAC interface mode has been selected.
00
01
10
11
10/100 EMAC/MDIO with MII Interface (default)
10/100 EMAC/MDIO with RMII Interface
10/100/1000 EMAC/MDIO with GMII Interface
10/100/1000 EMAC/MDIO with RGMII Mode Interface
[RGMII interface requires a 1.8 V or 1.5 V I/O supply]
8
7
Reserved
Reserved. Read-only, writes have no effect.
UTOPIA_EN
UTOPIA enable (UTOPIA_EN) status bit
Shows the status of which function is enabled on the UTOPIA/EMAC and UTOPIA/MDIO
multiplexed pins.
0
1
EMAC and MDIO pin functions are enabled (default)
UTOPIA pin functions are enabled
6
LENDIAN
Device Endian mode (LENDIAN)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode
(default).
0
1
System is operating in Big Endian mode
System is operating in Little Endian mode (default)
5
4
HPI_WIDTH
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
0
1
HPI operates in 16-bit mode. (default)
HPI operates in 32-bit mode
AECLKINSEL
EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for EMIFA.
0
1
AECLKIN (default mode)
SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the PLL1
Controller. By default, SYSCLK4 is selected as CPU/8 clock rate.
66
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Fixed-Point Digital Signal Processor
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Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued)
Bit
3:0
Field
Value Description
BOOTMODE[3:0]
Boot mode configuration bits
Shows the status of what device boot mode configuration is operational.
BOOTMODE[3:0]
[Note: if selected for boot, the corresponding peripheral is automatically enabled after device reset.]
0000 No boot (default mode)
0001 Host boot (HPI)
0010 Reserved
0011 Reserved
0100 EMIFA 8-bit ROM boot
0101 Master I2C boot
0110 Slave I2C boot
0111 Host boot (PCI)
1000 Serial Rapid I/O boot For more detailed information on the boot modes, see Section 2.4, Boot
thru
Sequence, of this document.
1111
3.6 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
C6455 device, the JTAG ID register resides at address location 0x02A8 0008. For the actual register bit
names and their associated bit field descriptions, see Figure 3-11 and Table 3-14.
31
28 27
12 11
1
0
VARIANT
(4-bit)
PART NUMBER
(16-bit)
MANUFACTURER
(11-bit)
LSB
R-n
R-0000 0000 1000 1010b
0000 0010 111b
R-1
LEGEND: R = Read only; -n = value after reset
Figure 3-11. JTAG ID (JTAGID) Register - 0x02A8 0008
Table 3-14. JTAG ID (JTAGID) Register Field Descriptions
Bit
Field
Value
Description
31:28 VARIANT
Variant (4-Bit) value. The value of this field depends on the silicon revision being
used. For more information, see the TMS320C6455 Digital Signal Processor
Silicon Errata (literature number SPRZ234).
Note: the VARIANT field may be invalid if no CLKIN1 signal is applied.
Part Number (16-Bit) value. C6455 value: 0000 0000 1000 1010b.
Manufacturer (11-Bit) value. C6455 value: 0000 0010 111b.
LSB. This bit is read as a "1" for C6455.
27:12 PART NUMBER
11:1 MANUFACTURER
0
LSB
3.7 Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including AEA[19:0],
ABA[1:0], and PCI_EN. Although internal pullup/pulldown resistors exist on these pins, providing external
connectivity adds convenience to the user in debugging and flexibility in switching operating modes.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
Device Configuration
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3.8 Configuration Examples
Figure 3-12 and Figure 3-13 illustrate examples of peripheral selections/options that are configurable on
the C6455 device.
32
HD[31:0]
HPI
HRDY, HINT
(32-Bit)
VCP2
HCNTL0, HCNTL1, HHWIL,
HAS, HR/W, HCS, HDS1, HDS2
TCP2
PCI
64
AED[63:0]
UTOPIA
GPIO
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT, ASDCKE,
AHOLDA, ABUSREQ,
ASADS/ASRE, AAOE/ASOE,
AAWE/ASWE
GP[15:12,2,1]
32
ED[31:0]
DDR2
EMIF
DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK,
DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS,
DSDWE
PLL2
and PLL2
Controller
PLL1
and PLL1
Controller
CLKIN1, PLLV1
SYSCLK4
CLKIN2, PLLV2
TINP1L
McBSP1
McBSP0
EMAC
TIMER1
TOUT1L
TINP0
CLKR0, FSR0, DR0, CLKS0,
DX0, FSX0, CLKX0
TIMER0
RapidIO
TOUT0
MRXD[7:0], MRXER, MRXDV, MCOL,
MCRS, MTCLK, MRCLK
RIOCLK, RIOCLK, RIOTX[3:0],
RIOTX[3:0], RIORX[3:0], RIORX[3:0]
SCL
SDA
MTXD[7:0], MTXEN,
MDIO, MDCLK
MDIO
I2C
Shading denotes a peripheral module not available for this configuration.
DEVSTAT Register: 0x0061 8161
PCI_EN = 0 (PCI disabled, default)
ABA1 (EMIFA_EN) = 1(EMIFA enabled)
ABA0 (DDR2_EN) = 1 (DDR2 Memory Controller enabled)
AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot)
AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default)
AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation)
AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default)
AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default)
AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode)
AEA[8] (PCI_EEAI) = 0, (PCI I2C EEPROM Auto-Init disabled, default)
AEA[7] = 0, (do not oppose IPD)
AEA[6] (PCI66) = 0, (PCI 33 MHz [default, don’t care])
AEA[5] (MCBSP1_EN) = 0, (McBSP1 disabled, default)
AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK3 pin function)
AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-12. Configuration Example A (McBSP + HPI32 + I2C + EMIFA + DDR2 Memory Controller +
TIMERS + RapidIO + EMAC (MII) + MDIO)
68
Device Configuration
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
32
HD[31:0]
HPI
(32-Bit)
VCP2
TCP2
HRDY, HINT
HCNTL0, HCNTL1, HHWIL,
HAS, HR/W, HCS, HDS1, HDS2
PCI
64
AED[63:0]
UTOPIA
GPIO
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT, ASDCKE,
AHOLDA, ABUSREQ,
ASADS/ASRE, AAOE/ASOE,
AAWE/ASWE
GP[15:12,2,1]
32
ED[31:0]
DDR2
EMIF
DEA[21:2], DCE[1:0], DBE[3:0], DDRCLK, DDRCLK,
DSDCKE, DDQS, DDQS, DSDCAS, DSDRAS,
DSDWE
PLL2
and PLL2
Controller
PLL1
and PLL1
Controller
CLKIN1, PLLV1
SYSCLK4
CLKIN2, PLLV2
TINP1L
CLKR1, FSR1, DR1, CLKS1,
DX1, FSX1, CLKX1
McBSP1
McBSP0
EMAC
TIMER1
TOUT1L
TINP0
CLKR0, FSR0, DR0, CLKS0,
DX0, FSX0, CLKX0
TIMER0
RapidIO
TOUT0
MRXD[7:0], MRXER, MRXDV, MCOL,
MCRS, MTCLK, MRCLK
RIOCLK, RIOCLK, RIOTX[3:0],
RIOTX[3:0], RIORX[3:0], RIORX[3:0]
SCL
SDA
MTXD[7:0], MTXEN,
MDIO, MDCLK
MDIO
I2C
Shading denotes a peripheral module not available for this configuration.
DEVSTAT Register: 0x0061 C161
PCI_EN = 0 (PCI disabled, default)
ABA1 (EMIFA_EN) = 1(EMIFA enabled)
ABA0 (DDR2_EN) = 1 (DDR2 Memory Controller enabled)
AEA[19:16] (BOOTMODE[3:0]) = 0001, (HPI Boot)
AEA[15] (AECLKIN_SEL) = 0, (AECLKIN, default)
AEA[14] (HPI_WIDTH) = 1, (HPI, 32-bit Operation)
AEA[13] (LENDIAN) = IPU, (Little Endian Mode, default)
AEA[12] (UTOPIA_EN) = 0, (UTOPIA disabled, default)
AEA[10:9] (MACSEL[1:0]) = 00, (10/100 MII Mode)
AEA[8] (PCI_EEAI) = 0, (PCI I2C EEPROM Auto-Init disabled, default)
AEA[7] = 0, (do not oppose IPD)
AEA[6] (PCI66) = 0, (PCI 33 MHz [default, don’t care])
AEA[5] (MCBSP1_EN) = 1, (McBSP1 enabled)
AEA[4] (SYSCLKOUT_EN) = 1, (SYSCLK3 pin function)
AEA[2:0] (CFGGP[2:0]) = 000 (default)
Figure 3-13. Configuration Example B (2 McBSPs + HPI32 + I2C + EMIFA + DDR2 Memory Controller +
TIMERS + RapidIO + EMAC (GMII) + MDIO
Device Configuration
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4 System Interconnect
On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system
peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency,
concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric the
CPU can send data to the Viterbi co-processor (VCP2) without affecting a data transfer between the PCI
and the DDR2 memory controller. The switch fabrics also allow for seamless arbitration between the
system masters when accessing system slaves.
4.1 Internal Buses, Bridges, and Switch Fabrics
Two types of buses exist in the C6455 device: data buses and configuration buses. Some C6455
peripherals have both a data bus and a configuration bus interface, while others only have one type of
interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.
Configuration buses are mainly used to access the register space of a peripheral and the data buses are
used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer
data. For example, data is transferred to the VCP2 and TCP2 via their configuration bus interface.
Similarly, the data bus can also be used to access the register space of a peripheral. For example, the
EMIFA and DDR2 memory controller registers are accessed through their data bus interface.
The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be
classified into two categories: masters and slaves. Masters are capable of initiating read and write
transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand
rely on the EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers,
SRIO, and PCI. Slaves include the McBSP, UTOPIA, and I2C.
The C6455 device contains two switch fabrics through which masters and slaves communicate. The data
switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect
mainly used to move data across the system ( for more information, see Section 4.2). The data SCR
connects masters to slaves via 128-bit data buses running at a SYSCLK2 frequency (SYSCLK2 is
generated from PLL1 controller). Peripherals that have a 128-bit data bus interface running at this speed
can connect directly to the data SCR; other peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly
used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3).
The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a
SYSCLK2 frequency (SYSCLK2 is generated from PLL1 controller). As with the data SCR, some
peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also
connects to the configuration SCR.
Bridges perform a variety of functions:
•
•
•
Conversion between configuration bus and data bus.
Width conversion between peripheral bus width and SCR bus width.
Frequency conversion between peripheral bus frequency and SCR bus frequency.
For example, the EMIFA and DDR2 memory controller require a bridge to convert their 64-bit data bus
interface into a 128-bit interface so that they can connect to the data SCR. In the case of the TCP2 and
VCP2, a bridge is required to connect the data SCR to the 64-bit configuration bus interface.
Note that some peripherals can be accessed through the data SCR and also through the configuration
SCR.
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4.2 Data Switch Fabric Connections
Figure 4-1 shows the connection between slaves and masters through the data switched central resource
(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves
via 128-bit data buses running at a SYSCLK2 frequency. SYSCLK2 is supplied by the PLL1 controller and
is fixed at a frequency equal to the CPU frequency divided by 3.
Some peripherals, like PCI and the C64x+ Megamodule, have both slave and master ports. Note that
each EDMA3 transfer controller has an independent connection to the data SCR.
The Serial RapioIO (SRIO) peripheral has two connections to the data SCR. The first connection is used
when descriptors are being fetched from system memory. The other connection is used for all other data
transfers.
Note that masters can access the configuration SCR through the data SCR. The configuration SCR is
described in Section 4.3.
Not all masters on the C6455 DSP may connect to all slaves. Allowed connections are summarized in
Table 4-1.
System Interconnect
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EDMA3 Channel
Controller
Events
SLAVE
MASTER
Data SCR
128
(SYSCLK2)
64 (SYSCLK2)
M
M
M
Bridge
Bridge
Bridge
S
S
S
TCP2
VCP2
128 (SYSCLK2)
128 (SYSCLK2)
M0
M1
M2
M3
S0
128
(SYSCLK2)
S1
S2
S3
EDMA3
Transfer
Controllers
64 (SYSCLK2)
32 (SYSCLK2)
128 (SYSCLK2)
128 (SYSCLK2)
128
(SYSCLK2)
CFG
SCR
128-bit
(SYSCLK2)
32 (SYSCLK3)
32
32 (SYSCLK3)
128
S
S
S
McBSPs
UTOPIA
PCI
EMAC
M
(SYSCLK3)
(SYSCLK3)
32
(SYSCLK3)
32
32
(SYSCLK3)
M
Bridge
(SYSCLK3)
HPI
PCI
M
M
Bridge
S
128 (SYSCLK2)
32 (SYSCLK3)
32 (SYSCLK3)
128
64
DDR2
Memory
Controller
(SYSCLK2)
(SYSCLK2)
M
M
M
Bridge
Bridge
S
S
S
32
32
(SYSCLK3)
(SYSCLK3)
128
(SYSCLK2)
64
Serial RapidIO
(Descriptor)
M
M
S
S
S
Bridge
(SYSCLK2)
EMIFA
Serial
RapidIO
(Data)
128 (SYSCLK2)
128 (SYSCLK2)
128 (SYSCLK2)
Megamodule
Megamodule
M
Configuration Bus
Data Bus
Figure 4-1. Switched Central Resource Block Diagram
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Table 4-1. SCR Connection Matrix
DDR2 MEMORY
CONTROLLER
TCP2
VCP2
McBSPs
UTOPIA2
CONFIGURATION SCR
PCI
EMIFA
MEGAMODULE
TC0
TC1
TC2
TC3
EMAC
HPI
Y
N
N
N
N
N
N
N
Y
Y
N
N
N
N
N
N
N
Y
N
Y
N
N
N
N
N
N
Y
N
Y
N
N
N
N
N
N
Y
N
Y
N
N
N
Y
Y
Y
Y
N
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
PCI
SRIO(1)
Megamodule
(1) Applies to both descriptor and data accesses by the SRIO peripheral.
4.3 Configuration Switch Fabric
Figure 4-2 shows the connection between the C64x+ Megamodule and the configuration switched central
resource (SCR). The configuration SCR is mainly used by the C64x+ Megamodule to access peripheral
registers. The data SCR also has a connection to the configuration SCR which allows masters to access
most peripheral registers. The only registers not accessible by the data SCR through the configuration
SCR are the device configuration registers and the PLL1 and PLL2 controller registers; these can only be
accessed by the C64x+ Megamodule.
The configuration SCR uses 32-bit configuration buses running at SYSCLK2 frequency. SYSCLK2 is
supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3.
System Interconnect
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CFG SCR
32 (SYSCLK2)
32 (SYSCLK2)
S
S
S
S
S
S
TCP2
VCP2
M
MUX
32
32
(SYSCLK3)
(SYSCLK2)
GPIO
32
(SYSCLK3)
McBSPs
32
(SYSCLK3)
UTOPIA
PCI
32
(SYSCLK3)
32
32-bit
(SYSCLK3)
(SYSCLK2)
32
(SYSCLK3)
S
I2C
Bridge
7
M
MUX
32
(SYSCLK3)
S
S
S
S
S
Timers
HPI
32
32 (SYSCLK2)
M
M
S
S
(SYSCLK3)
Megamodule
Data SCR
32
(SYSCLK2)
32
(SYSCLK3)
32 (SYSCLK2)
EMAC/MDIO
PLL
32
(SYSCLK3)
(A)
Controllers
32
(SYSCLK3)
Device
Configuration
(A)
Registers
32 (SYSCLK2)
M
S
S
Serial RapidIO
32
(SYSCLK2)
EDMA3 CC
EDMA3 TC0
32
(SYSCLK2)
S
S
S
S
32
(SYSCLK2)
32
(SYSCLK2)
MUX
M
EDMA3 TC1
EDMA3 TC2
32
(SYSCLK2)
32
(SYSCLK2)
EDMA3 TC3
Configuration Bus
Data Bus
A. Only accessible by the C64x+ Megamodule.
B. All clocks in this figure are generated by the PLL1 controller.
Figure 4-2. C64x+ Megamodule - SCR Connection
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4.4 Priority Allocation
On the C6455 device, each of the masters (excluding the C64x+ Megamodule) are assigned a priority via
the Priority Allocation Register (PRI_ALLOC), see Figure 4-3. The priority is enforced when several
masters in the system are vying for the same endpoint. A value of 000b has the highest priority, while
111b has the lowest priority.
Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will
be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the
configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the
C64x+ Megamodule.
Similarly, the HOST field applies to the priority of the HPI and PCI peripherals. The SRIO field is used to
specify the priority of the Serial RapidIO when accessing descriptors from system memory. The priority for
Serial RapidIO data accesses is set in the peripheral itself.
Other Master peripherals are not present in the PRI_ALLOC register as they have their own registers to
program their priorities. For more information on the default priority values in these peripheral registers,
see the device-compatible peripheral reference guides. TI recommends that these priority registers be
reprogrammed upon initial use.
31
15
16
Reserved
R-0000 0000 0000 0000
12
11
9
8
6
5
3
2
0
Reserved
R-000 0
SRIO
Reserved
R-0
HOST
EMAC
R/W-001
R/W-010
R/W-001
LEGEND: R/W = Read/Write; R = Read only; -n = value at reset
Figure 4-3. Priority Allocation Register (PRI_ALLOC)
System Interconnect
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5 C64x+ Megamodule
The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data
memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller,
power-down controller, and external memory controller. The C64x+ Megamodule also provides support for
memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to
the C64x+ Megamodule). Figure 5-1 shows a block diagram of the C64x+ Megamodule.
L1P cache/SRAM
256
L1 program memory controller
256
Cache control
L2 memory
controller
Advanced event
triggering
256
256
L2
cache/
SRAM
Bandwidth management
Memory protection
(AET)
Cache
control
256
256
C64x+ CPU
Bandwidth
management
Instruction fetch
SPLOOP buffer
Internal
ROM
(A)
256
Memory
protection
IDMA
16/32−bit instruction dispatch
Instruction decode
Data path 1
Data path 2
128
M1
xx
xx
M2
xx
xx
L1
S1
D1
D2
S2
L2
External memory
controller
A register file
B register file
32
Configuration
Registers
To Chip
registers
256
64
64
128
Interrupt
and exception
controller
Slave DMA
L1 data memory controller
Cache control
To primary
switch fabric
128
Bandwidth management
Memory protection
256
Power control
Master DMA
32
L1D cache/SRAM
A. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Figure 5-1. 64x+ Megamodule Block Diagram
For more detailed information on the TMS320C64x+ Megamodule on the C6455 device, see the C64x+
Megamodule Peripherals Reference Guide (Literature Number SPRU871).
5.1 Memory Architecture
The TMS320C6455 device contains a 2MB level-2 memory (L2), a 32KB level-1 program memory (L1P),
and a 32KB level-1 data memory (L1D).
The L1P memory configuration for the C6455 device is as follows:
•
•
Region 0 size is 0K bytes (disabled).
Region 1 size is 32K bytes with no wait states.
The L1D memory configuration for the C6455 device is as follows:
Region 0 size is 0K bytes (disabled).
•
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•
Region 1 size is 32K bytes with no wait states.
After device reset, L1P and L1D cache are configured as all cache by default. The L1P and L1D cache
can be reconfigured via software through the L1PMODE field of the L1P Configuration Register
(L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+
Megamodule. L1D is a two-way set-associative cache while L1P is a direct-mapped cache.
Figure 5-2 and Figure 5-3 show the available SRAM/cache configurations for L1P and L1D, respectively.
L1P mode bits
Block base
000
001
010
011
100
L1P memory
16K bytes
address
00E0 0000h
1/2
SRAM
3/4
SRAM
7/8
SRAM
direct
mapped
cache
All
SRAM
00E0 4000h
00E0 6000h
8K bytes
direct
mapped
cache
4K bytes
4K bytes
direct
mapped
cache
00E0 7000h
00E0 8000h
dm
cache
Figure 5-2. TMS320C6455 L1P Memory Configurations
L1D mode bits
Block base
address
00F0 0000h
000
001
010
011
100
L1D memory
16K bytes
1/2
SRAM
3/4
SRAM
7/8
SRAM
All
SRAM
2-way
cache
00F0 4000h
00F0 6000h
8K bytes
2-way
cache
4K bytes
4K bytes
2-way
cache
00F0 7000h
00F0 8000h
2-way
cache
Figure 5-3. TMS320C6455 L1D Memory Configurations
The L2 memory configuration for the C6455 device is as follows:
C64x+ Megamodule
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•
Port 0 configuration:
–
–
–
–
Memory size is 2Mbytes
Starting address is 0080 0000h
2-cycle latency
4 × 128-bit bank configuration
•
Port 1 configuration:
–
–
–
–
Memory size is 32KBytes (this corresponds to the internal ROM)
Starting address is 0010 0000h
1-cycle latency
1 × 256-bit bank configuration
L2 memory can be configured as all SRAM or as part 4-way set-associative cache. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration
Register (L2CFG) of the C64x+ Megamodule. Figure 5-4 shows the available SRAM/cache configurations
for L2. By default, L2 is configured as all SRAM after device reset.
L2 mode bits
Block base
address
000
001
010
011
111
L2 memory
0080 0000h
3/4
SRAM
1792K bytes
7/8
SRAM
15/16
SRAM
All
SRAM
31/32
SRAM
009C 0000h
128K bytes
64K bytes
4-way
cache
009E 0000h
009F 0000h
009F 8000h
00A0 0000h
4-way
cache
32K bytes
32K bytes
4-way
cache
4-way
Figure 5-4. TMS320C6455 L2 Memory Configurations
For more information on the operation L1 and L2 caches, see the TMS320C64x+ DSP Cache User's
Guide (literature number SPRUTBD).
All memory on the C6455 has a unique location in the memory map (see Table 2-2, C6455 Memory Map
Summary).
When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
Therefore, when using a software boot mode, care must be taken such that the CPU frequency does not
exceed 750 MHz at any point during the boot sequence. After the boot sequence has completed, the CPU
frequency can be programmed to the frequency required by the application. For more detailed information
ont he boot modes, see Section 2.4, Boot Sequence, of this document.
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5.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (64KB each). The L1D, L1P,
and L2 memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the
permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. Additionally, a page may be marked as either (or both) locally or globally accessible. A local
access is a direct CPU access to L1D, L1P, and L2, while a global access is initiated by a DMA (either
IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the
CPU count as global accesses.
The CPU and the system masters on the C6455 device are all assigned a privilege ID of 0. Therefore it is
only possible to specify whether memory pages are locally or globally accessible. The AID0 and LOCAL
bits of the memory protection page attribute registers specify the memory page protection scheme, see
Table 5-1.
Table 5-1. Available Memory Page Protection Schemes
AID0 Bit
LOCAL Bit
Description
0
0
1
0
1
0
No access to memory page is permitted.
Only direct access by CPU is permitted.
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA
accesses initiated by the CPU).
1
1
All accesses permitted
For more information on memory protection for L1D, L1P, and L2, see the TMS320C64x+ DSP
Megamodule Reference Guide (literature number SPRU871).
5.3 Bandwidth Management
When multiple requestors contend for a single C64x+ Megamodule resource, the conflict is solved by
granting access to the highest priority requestor. The following four resources are managed by the
Bandwidth Management control hardware:
•
•
•
•
Level 1 Program (L1P) SRAM/Cache
Level 1 Data (L1D) SRAM/Cache
Level 2 (L2) SRAM/Cache
Memory-mapped registers configuration bus
The priority level for operations initiated within the C64x+ Megamodule; e.g., CPU-initiated transfers,
user-programmed cache coherency operations, and IDMA-initiated transfers, are declared through
registers in the C64x+ Megamodule. The priority level for operations initiated outside the C64x+
Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see
Section 4.4. System peripherals with no fields in PRI_ALLOC have their own registers to program their
priorities.
More information on the bandwidth management features of the C64x+ Megamodule can be found in the
TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871).
C64x+ Megamodule
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5.4 Power-Down Control
The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The
power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache
control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used
to design systems for lower overall system power requirements.
NOTE
The C6455 does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C64x+ Megamodule can be found in the
TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871).
5.5 Megamodule Resets
Table 5-2 shows the reset types supported on the C6455 device and they affect the resetting of the
Megamodule, either both globally or just locally.
Table 5-2. Megamodule Reset (Global or Local)
GLOBAL
MEGAMODULE
RESET
LOCAL
MEGAMODULE
RESET
RESET TYPE
Power-On Reset
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Warm Reset
Max Reset
System Reset
CPU Reset
For more detailed information on the global and local Megamodule resets, see the TMS320C64x+ DSP
Megamodule Reference Guide (literature number SPRU871). And for more detailed information on device
resets, see Section 7.6, Reset of this document.
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5.6 Megamodule Revision
The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID
Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5
and described in Table 5-3. The C64x+ Megamodule revision is dependant on the silicon revision being
used. For more information, see the TMS320C6455 Digital Signal Processor Silicon Errata (literature
number SPRZ234).
31
16 15
0
VERSION
R-1h
REVISION(A)
R-n
LEGEND: R = Read only; -n = value after reset
A. The C64x+ Megamodule revision is dependant on the silicon revision being used. For more information, see
the TMS320C6455 Digital Signal Processor Silicon Errata (literature number SPRZ234).
Figure 5-5. Megamodule Revision ID Register (MM_REVID) [Hex Address: 0181 2000h]
Table 5-3. Megamodule Revision ID Register (MM_REVID) Field Descriptions
Bit
Field
Value Description
1h Version of the C64x+ Megamodule implemented on the device. This field is always read as 1h.
31:16 VERSION
15:0
REVISION
Revision of the C64x+ Megamodule version implemented on the device. The C64x+ Megamodule
revision is dependant on the silicon revision being used. For more information, see the
TMS320C6455 Digital Signal Processor Silicon Errata (literature number SPRZ234).
C64x+ Megamodule
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5.7 C64x+ Megamodule Register Description(s)
Table 5-4. Megamodule Interrupt Registers
HEX ADDRESS RANGE
0180 0000
ACRONYM
EVTFLAG0
REGISTER NAME
Event flag register 0 (Events [31:0])
0180 0004
EVTFLAG1
EVTFLAG2
EVTFLAG3
-
Event flag register 1
0180 0008
Event flag register 2
0180 000C
Event flag register 3
0180 0010 - 0180 001C
0180 0020
Reserved
EVTSET0
EVTSET1
EVTSET2
EVTSET3
-
Event set register 0 (Events [31:0])
Event set register 1
0180 0024
0180 0028
Event set register 2
0180 002C
Event set register 3
0180 0030 - 0180 003C
0180 0040
Reserved
EVTCLR0
EVTCLR1
EVTCLR2
EVTCLR3
-
Event clear register 0 (Events [31:0])
Event clear register 1
0180 0044
0180 0048
Event clear register 2
0180 004C
Event clear register 3
0180 0050 - 0180 007C
0180 0080
Reserved
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
-
Event mask register 0 (Events [31:0])
Event mask register 1
0180 0084
0180 0088
Event mask register 2
0180 008C
Event mask register 3
0180 0090 - 0180 009C
0180 00A0
Reserved
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
-
Masked event flag status register 0 (Events [31:0])
Masked event flag status register 1
Masked event flag status register 2
Masked event flag status register 3
Reserved
0180 00A4
0180 00A8
0180 00AC
0180 00B0 - 0180 00BC
0180 00C0
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
-
Exception mask register 0 (Events [31:0])
Exception mask register 1
Exception mask register 2
Exception mask register 3
Reserved
0180 00C4
0180 00C8
0180 00CC
0180 00D0 - 0180 00DC
0180 00E0
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
-
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Reserved
0180 00E4
0180 00E8
0180 00EC
0180 00F0 - 0180 00FC
0180 0100
-
Reserved
0180 0104
INTMUX1
INTMUX2
INTMUX3
-
Interrupt multiplexor register 1
Interrupt multiplexor register 2
Interrupt multiplexor register 3
Reserved
0180 0108
0180 010C
0180 0110 - 0180 013C
0180 0140
AEGMUX0
AEGMUX1
-
Advanced event generator mux regsiter 0
Advanced event generator mux regsiter 1
Reserved
0180 0144
0180 0148 - 0180 017C
0180 0180
INTXSTAT
Interrupt exception status register
82
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-4. Megamodule Interrupt Registers (continued)
HEX ADDRESS RANGE
0180 0184
ACRONYM
INTXCLR
INTDMASK
-
REGISTER NAME
Interrupt exception clear register
0180 0188
Dropped interrupt mask register
Reserved
0180 0188 - 0180 01BC
0180 01C0
EVTASRT
-
Event asserting register
Reserved
0180 01C4 - 0180 FFFF
Table 5-5. Megamodule Powerdown Control Registers
HEX ADDRESS RANGE
0181 0000
ACRONYM
PDCCMD
-
REGISTER NAME
Power-down controller command register
Reserved
0181 0004 - 0181 1FFF
Table 5-6. Megamodule Revision Register
HEX ADDRESS RANGE
0181 2000
ACRONYM
MM_REVID
-
REGISTER NAME
Megamodule Revision ID Register
Reserved
0181 2004 – 0181 2FFF
Table 5-7. Megamodule IDMA Registers
HEX ADDRESS RANGE
0182 0000
ACRONYM
IDMA0STAT
IDMA0MASK
IMDA0SRC
IDMA0DST
IDMA0CNT
-
REGISTER NAME
IDMA Channel 0 Status Register
IDMA Channel 0 Mask Register
IDMA Channel 0 Source Address Register
IDMA Channel 0 Destination Address Register
IDMA Channel 0 Count Register
Reserved
0182 0004
0182 0008
0182 000C
0182 0010
0182 0014 - 0182 00FC
0182 0100
IDMA1STAT
-
IDMA Channel 1 Status Register
Reserved
0182 0104
0182 0108
IMDA1SRC
IDMA1DST
IDMA1CNT
-
IDMA Channel 1 Source Address Register
IDMA Channel 1 Destination Address Register
IDMA Channel 1 Count Register
Reserved
0182 010C
0182 0110
0182 0114 - 0182 017C
0182 0180
-
Reserved
0182 0184 - 0182 01FF
-
Reserved
C64x+ Megamodule
83
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-8. Megamodule Cache Configuration Registers
HEX ADDRESS RANGE
0184 0000
ACRONYM
L2CFG
-
REGISTER NAME
L2 Cache Configuration Register
0184 0004 - 0184 001F
0184 0020
Reserved
L1PCFG
L1PCC
-
L1P Configuration Register
L1P Cache Control Register
Reserved
0184 0024
0184 0028 - 0184 003F
0184 0040
L1DCFG
L1DCC
-
L1D Configuration Register
L1D Cache Control Register
Reserved
0184 0044
0184 0048 - 0184 0FFF
0184 1000 - 0184 104F
0184 1050 - 0184 3FFF
0184 4000
-
See Table 5-10, CPU Megamodule Bandwidth Management Registers
Reserved
-
L2WBAR
L2WWC
-
L2 Writeback Base Address Register - for Block Writebacks
L2 Writeback Word Count Register
Reserved
0184 4004
0184 4008 - 0184 400C
0184 4010
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
L2 Writeback and Invalidate Base Address Register - for Block Writebacks
L2 Writeback and Invalidate word count register
L2 Invalidate Base Address Register
L2 Invalidate Word Count Register
L1P Invalidate Base Address Register
L1P Invalidate Word Count Register
L1D Writeback and Invalidate Base Address Register
L1D Writeback and Invalidate Word Count Register
Reserved
0184 4014
0184 4018
0184 401C
0184 4020
0184 4024
0184 4030
0184 4034
0184 4038
0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D Writeback Base Address Register - for Block Writebacks
L1D Writeback Word Count Register
L1D Invalidate Base Address Register
L1D Invalidate Word Count Register
Reserved
0184 4044
0184 4048
0184 404C
0184 4050 - 0184 4FFF
0184 5000
L2WB
L2WBINV
L2INV
-
L2 Global Writeback Register
0184 5004
L2 Global Writeback and Invalidate Register
L2 Global Invalidate Register
0184 5008
0184 500C - 0184 5024
0184 5028
Reserved
L1PINV
-
L1P Global Invalidate Register
0184 502C - 0184 503C
0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
L1D Global Writeback Register
0184 5044
L1D Global Writeback and Invalidate Register
L1D Global Invalidate Register
0184 5048
MAR0 to
MAR127
0184 8000 - 0184 81FC
0184 8200 - 0184 823C
0184 8240 - 0184 827C
Reserved
Reserved
Reserved
MAR128 to
MAR143
MAR144 to
MAR159
0184 8280
0184 8284
0184 8288
0184 828C
0184 8290
MAR160
MAR161
MAR162
MAR163
MAR164
Controls EMIFA CE2 Range A000 0000 - A0FF FFFF
Controls EMIFA CE2 Range A100 0000 - A1FF FFFF
Controls EMIFA CE2 Range A200 0000 - A2FF FFFF
Controls EMIFA CE2 Range A300 0000 - A3FF FFFF
Controls EMIFA CE2 Range A400 0000 - A4FF FFFF
84
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-8. Megamodule Cache Configuration Registers (continued)
HEX ADDRESS RANGE
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
0184 82D8
0184 82DC
0184 82E0
0184 82E4
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
0184 8300
0184 8304
0184 8308
0184 830C
0184 8310
0184 8314
0184 8318
0184 831C
0184 8320
0184 8324
0184 8328
0184 832C
0184 8330
0184 8334
0184 8338
0184 833C
0184 8340
0184 8344
0184 8348
0184 834C
ACRONYM
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
MAR182
MAR183
MAR184
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
MAR192
MAR193
MAR194
MAR195
MAR196
MAR197
MAR198
MAR199
MAR200
MAR201
MAR202
MAR203
MAR204
MAR205
MAR206
MAR207
MAR208
MAR209
MAR210
MAR211
REGISTER NAME
Controls EMIFA CE2 Range A500 0000 - A5FF FFFF
Controls EMIFA CE2 Range A600 0000 - A6FF FFFF
Controls EMIFA CE2 Range A700 0000 - A7FF FFFF
Controls EMIFA CE2 Range A800 0000 - A8FF FFFF
Controls EMIFA CE2 Range A900 0000 - A9FF FFFF
Controls EMIFA CE2 Range AA00 0000 - AAFF FFFF
Controls EMIFA CE2 Range AB00 0000 - ABFF FFFF
Controls EMIFA CE2 Range AC00 0000 - ACFF FFFF
Controls EMIFA CE2 Range AD00 0000 - ADFF FFFF
Controls EMIFA CE2 Range AE00 0000 - AEFF FFFF
Controls EMIFA CE2 Range AF00 0000 - AFFF FFFF
Controls EMIFA CE3 Range B000 0000 - B0FF FFFF
Controls EMIFA CE3 Range B100 0000 - B1FF FFFF
Controls EMIFA CE3 Range B200 0000 - B2FF FFFF
Controls EMIFA CE3 Range B300 0000 - B3FF FFFF
Controls EMIFA CE3 Range B400 0000 - B4FF FFFF
Controls EMIFA CE3 Range B500 0000 - B5FF FFFF
Controls EMIFA CE3 Range B600 0000 - B6FF FFFF
Controls EMIFA CE3 Range B700 0000 - B7FF FFFF
Controls EMIFA CE3 Range B800 0000 - B8FF FFFF
Controls EMIFA CE3 Range B900 0000 - B9FF FFFF
Controls EMIFA CE3 Range BA00 0000 - BAFF FFFF
Controls EMIFA CE3 Range BB00 0000 - BBFF FFFF
Controls EMIFA CE3 Range BC00 0000 - BCFF FFFF
Controls EMIFA CE3 Range BD00 0000 - BDFF FFFF
Controls EMIFA CE3 Range BE00 0000 - BEFF FFFF
Controls EMIFA CE3 Range BF00 0000 - BFFF FFFF
Controls EMIFA CE4 Range C000 0000 - C0FF FFFF
Controls EMIFA CE4 Range C100 0000 - C1FF FFFF
Controls EMIFA CE4 Range C200 0000 - C2FF FFFF
Controls EMIFA CE4 Range C300 0000 - C3FF FFFF
Controls EMIFA CE4 Range C400 0000 - C4FF FFFF
Controls EMIFA CE4 Range C500 0000 - C5FF FFFF
Controls EMIFA CE4 Range C600 0000 - C6FF FFFF
Controls EMIFA CE4 Range C700 0000 - C7FF FFFF
Controls EMIFA CE4 Range C800 0000 - C8FF FFFF
Controls EMIFA CE4 Range C900 0000 - C9FF FFFF
Controls EMIFA CE4 Range CA00 0000 - CAFF FFFF
Controls EMIFA CE4 Range CB00 0000 - CBFF FFFF
Controls EMIFA CE4 Range CC00 0000 - CCFF FFFF
Controls EMIFA CE4 Range CD00 0000 - CDFF FFFF
Controls EMIFA CE4 Range CE00 0000 - CEFF FFFF
Controls EMIFA CE4 Range CF00 0000 - CFFF FFFF
Controls EMIFA CE5 Range D000 0000 - D0FF FFFF
Controls EMIFA CE5 Range D100 0000 - D1FF FFFF
Controls EMIFA CE5 Range D200 0000 - D2FF FFFF
Controls EMIFA CE5 Range D300 0000 - D3FF FFFF
C64x+ Megamodule
85
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-8. Megamodule Cache Configuration Registers (continued)
HEX ADDRESS RANGE
0184 8350
0184 8354
0184 8358
0184 835C
0184 8360
0184 8364
0184 8368
0184 836C
0184 8370
0184 8374
0184 8378
0184 837C
0184 8380
0184 8384
0184 8388
0184 838C
0184 8390
0184 8394
0184 8398
0184 839C
0184 83A0
0184 83A4
0184 83A8
0184 83AC
0184 83B0
0184 83B4
0184 83B8
0184 83BC
ACRONYM
MAR212
MAR213
MAR214
MAR215
MAR216
MAR217
MAR218
MAR219
MAR220
MAR221
MAR222
MAR223
MAR224
MAR225
MAR226
MAR227
MAR228
MAR229
MAR230
MAR231
MAR232
MAR233
MAR234
MAR235
MAR236
MAR237
MAR238
MAR239
REGISTER NAME
Controls EMIFA CE5 Range D400 0000 - D4FF FFFF
Controls EMIFA CE5 Range D500 0000 - D5FF FFFF
Controls EMIFA CE5 Range D600 0000 - D6FF FFFF
Controls EMIFA CE5 Range D700 0000 - D7FF FFFF
Controls EMIFA CE5 Range D800 0000 - D8FF FFFF
Controls EMIFA CE5 Range D900 0000 - D9FF FFFF
Controls EMIFA CE5 Range DA00 0000 - DAFF FFFF
Controls EMIFA CE5 Range DB00 0000 - DBFF FFFF
Controls EMIFA CE5 Range DC00 0000 - DCFF FFFF
Controls EMIFA CE5 Range DD00 0000 - DDFF FFFF
Controls EMIFA CE5 Range DE00 0000 - DEFF FFFF
Controls EMIFA CE5 Range DF00 0000 - DFFF FFFF
Controls DDR2 CE0 Range E000 0000 - E0FF FFFF
Controls DDR2 CE0 Range E100 0000 - E1FF FFFF
Controls DDR2 CE0 Range E200 0000 - E2FF FFFF
Controls DDR2 CE0 Range E300 0000 - E3FF FFFF
Controls DDR2 CE0 Range E400 0000 - E4FF FFFF
Controls DDR2 CE0 Range E500 0000 - E5FF FFFF
Controls DDR2 CE0 Range E600 0000 - E6FF FFFF
Controls DDR2 CE0 Range E700 0000 - E7FF FFFF
Controls DDR2 CE0 Range E800 0000 - E8FF FFFF
Controls DDR2 CE0 Range E900 0000 - E9FF FFFF
Controls DDR2 CE0 Range EA00 0000 - EAFF FFFF
Controls DDR2 CE0 Range EB00 0000 - EBFF FFFF
Controls DDR2 CE0 Range EC00 0000 - ECFF FFFF
Controls DDR2 CE0 Range ED00 0000 - EDFF FFFF
Controls DDR2 CE0 Range EE00 0000 - EEFF FFFF
Controls DDR2 CE0 Range EF00 0000 - EFFF FFFF
MAR240 to
MAR255
0184 83C0 -0184 83FC
Reserved
Table 5-9. Megamodule L1/L2 Memory Protection Registers
HEX ADDRESS RANGE
0184 A000
ACRONYM
L2MPFAR
L2MPFSR
L2MPFCR
-
REGISTER NAME
L2 memory protection fault address register
0184 A004
L2 memory protection fault status register
L2 memory protection fault command register
Reserved
0184 A008
0184 A00C - 0184 A0FF
0184 A100
L2MPLK0
L2MPLK1
L2MPLK2
L2MPLK3
L2MPLKCMD
L2MPLKSTAT
-
L2 memory protection lock key bits [31:0]
L2 memory protection lock key bits [63:32]
L2 memory protection lock key bits [95:64]
L2 memory protection lock key bits [127:96]
L2 memory protection lock key command register
L2 memory protection lock key status register
Reserved
0184 A104
0184 A108
0184 A10C
0184 A110
0184 A114
0184 A118 - 0184 A1FF
0184 A200
L2MPPA0
L2MPPA1
L2MPPA2
L2 memory protection page attribute register 0
L2 memory protection page attribute register 1
L2 memory protection page attribute register 2
0184 A204
0184 A208
86
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
0184 A20C
0184 A210
0184 A214
0184 A218
0184 A21C
0184 A220
0184 A224
0184 A228
0184 A22C
0184 A230
0184 A234
0184 A238
0184 A23C
0184 A240
0184 A244
0184 A248
0184 A24C
0184 A250
0184 A254
0184 A258
0184 A25C
0184 A260
0184 A264
0184 A268
0184 A26C
0184 A270
0184 A274
0184 A278
0184 A27C
0184 A280
0184 A284
0184 A288
0184 A28C
0184 A290
0184 A294
0184 A298
0184 A29C
0184 A2A0
0184 A2A4
0184 A2A8
0184 A2AC
0184 A2B0
0184 A2B4
0184 A2B8
0184 A2BC
0184 A2C0
0184 A2C4
ACRONYM
L2MPPA3
REGISTER NAME
L2 memory protection page attribute register 3
L2 memory protection page attribute register 4
L2 memory protection page attribute register 5
L2 memory protection page attribute register 6
L2 memory protection page attribute register 7
L2 memory protection page attribute register 8
L2 memory protection page attribute register 9
L2 memory protection page attribute register 10
L2 memory protection page attribute register 11
L2 memory protection page attribute register 12
L2 memory protection page attribute register 13
L2 memory protection page attribute register 14
L2 memory protection page attribute register 15
L2 memory protection page attribute register 16
L2 memory protection page attribute register 17
L2 memory protection page attribute register 18
L2 memory protection page attribute register 19
L2 memory protection page attribute register 20
L2 memory protection page attribute register 21
L2 memory protection page attribute register 22
L2 memory protection page attribute register 23
L2 memory protection page attribute register 24
L2 memory protection page attribute register 25
L2 memory protection page attribute register 26
L2 memory protection page attribute register 27
L2 memory protection page attribute register 28
L2 memory protection page attribute register 29
L2 memory protection page attribute register 30
L2 memory protection page attribute register 31
L2 memory protection page attribute register 32
L2 memory protection page attribute register 33
L2 memory protection page attribute register 34
L2 memory protection page attribute register 35
L2 memory protection page attribute register 36
L2 memory protection page attribute register 37
L2 memory protection page attribute register 38
L2 memory protection page attribute register 39
L2 memory protection page attribute register 40
L2 memory protection page attribute register 41
L2 memory protection page attribute register 42
L2 memory protection page attribute register 43
L2 memory protection page attribute register 44
L2 memory protection page attribute register 45
L2 memory protection page attribute register 46
L2 memory protection page attribute register 47
L2 memory protection page attribute register 48
L2 memory protection page attribute register 49
L2MPPA4
L2MPPA5
L2MPPA6
L2MPPA7
L2MPPA8
L2MPPA9
L2MPPA10
L2MPPA11
L2MPPA12
L2MPPA13
L2MPPA14
L2MPPA15
L2MPPA16
L2MPPA17
L2MPPA18
L2MPPA19
L2MPPA20
L2MPPA21
L2MPPA22
L2MPPA23
L2MPPA24
L2MPPA25
L2MPPA26
L2MPPA27
L2MPPA28
L2MPPA29
L2MPPA30
L2MPPA31
L2MPPA32
L2MPPA33
L2MPPA34
L2MPPA35
L2MPPA36
L2MPPA37
L2MPPA38
L2MPPA39
L2MPPA40
L2MPPA41
L2MPPA42
L2MPPA43
L2MPPA44
L2MPPA45
L2MPPA46
L2MPPA47
L2MPPA48
L2MPPA49
C64x+ Megamodule
87
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
0184 A2C8
ACRONYM
L2MPPA50
L2MPPA51
L2MPPA52
L2MPPA53
L2MPPA54
L2MPPA55
L2MPPA56
L2MPPA57
L2MPPA58
L2MPPA59
L2MPPA60
L2MPPA61
L2MPPA62
L2MPPA63
-
REGISTER NAME
L2 memory protection page attribute register 50
L2 memory protection page attribute register 51
L2 memory protection page attribute register 52
L2 memory protection page attribute register 53
L2 memory protection page attribute register 54
L2 memory protection page attribute register 55
L2 memory protection page attribute register 56
L2 memory protection page attribute register 57
L2 memory protection page attribute register 58
L2 memory protection page attribute register 59
L2 memory protection page attribute register 60
L2 memory protection page attribute register 61
L2 memory protection page attribute register 62
L2 memory protection page attribute register 63
Reserved
0184 A2CC
0184 A2D0
0184 A2D4
0184 A2D8
0184 A2DC
0184 A2E0
0184 A2E4
0184 A2E8
0184 A2EC
0184 A2F0
0184 A2F4
0184 A2F8
0184 A2FC
0184 A300 - 0184 A3FF
0184 A400
L1PMPFAR
L1PMPFSR
L1PMPFCR
-
L1 program (L1P) memory protection fault address register
L1P memory protection fault status register
L1P memory protection fault command register
Reserved
0184 A404
0184 A408
0184 A40C - 0184 A4FF
0184 A500
L1PMPLK0
L1PMPLK1
L1PMPLK2
L1PMPLK3
L1P memory protection lock key bits [31:0]
L1P memory protection lock key bits [63:32]
L1P memory protection lock key bits [95:64]
L1P memory protection lock key bits [127:96]
0184 A504
0184 A508
0184 A50C
0184 A510
L1PMPLKCMD L1P memory protection lock key command register
L1PMPLKSTAT L1P memory protection lock key status register
0184 A514
0184 A518 - 0184 ABFF
0184 AC00
-
Reserved
L1DMPFAR
L1DMPFSR
L1DMPFCR
-
L1 data (L1D) memory protection fault address register
L1D memory protection fault status register
L1D memory protection fault command register
Reserved
0184 AC04
0184 AC08
0184 AC0C - 0184 ACFF
0184 AD00
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1D memory protection lock key bits [31:0]
L1D memory protection lock key bits [63:32]
L1D memory protection lock key bits [95:64]
L1D memory protection lock key bits [127:96]
0184 AD04
0184 AD08
0184 AD0C
0184 AD10
L1DMPLKCMD L1D memory protection lock key command register
L1DMPLKSTAT L1D memory protection lock key status register
0184 AD14
0184 AD18 - 0185 FFFF
-
Reserved
Table 5-10. CPU Megamodule Bandwidth Management Registers
HEX ADDRESS RANGE
0182 0200
ACRONYM
REGISTER NAME
EMCCPUARBE EMC CPU Arbitration Control Register
EMCIDMAARBE EMC IDMA Arbitration Control Register
EMCSDMAARBE EMC Slave DMA Arbitration Control Register
EMCMDMAARBE EMC Master DMA Arbitration Control Resgiter
0182 0204
0182 0208
0182 020C
0182 0210 - 0182 02FF
0184 1000
-
Reserved
L2DCPUARBU L2D CPU Arbitration Control Register
88
C64x+ Megamodule
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 5-10. CPU Megamodule Bandwidth Management Registers (continued)
HEX ADDRESS RANGE
0184 1004
ACRONYM
REGISTER NAME
L2DIDMAARBU L2D IDMA Arbitration Control Register
0184 1008
L2DSDMAARBU L2D Slave DMA Arbitration Control Register
0184 100C
L2DUCARBU
-
L2D User Coherence Arbitration Control Resgiter
Reserved
0184 1010 - 0184 103F
0184 1040
L1DCPUARBD L1D CPU Arbitration Control Register
L1DIDMAARBD L1D IDMA Arbitration Control Register
L1DSDMAARBD L1D Slave DMA Arbitration Control Register
0184 1044
0184 1048
0184 104C
L1DUCARBD
L1D User Coherence Arbitration Control Resgiter
Table 5-11. Device Configuration Registers (Chip-Level Registers)
HEX ADDRESS RANGE
02A8 0000
ACRONYM
DEVSTAT
PRI_ALLOC
JTAGID
REGISTER NAME
Device Status Register
COMMENTS
Read-only. Provides status of the
User's device configuration on reset.
02A8 0004
Priority Allocation Register
Sets priority for Master peripherals
JTAG and BSDL Identification
Register
Read-only. Provides 32-bit JTAG ID of
the device.
02A8 0008
02A8 000C - 02AB FFFF
02AC 0000
-
Reserved
-
Reserved
02AC 0004
PERLOCK
Peripheral Lock Register
Peripheral Configuration Register 0
Reserved
02AC 0008
PERCFG0
02AC 000C
-
02AC 0010
-
Reserved
02AC 0014
PERSTAT0
Peripheral Status Register 0
Peripheral Status Register 1
Reserved
02AC 0018
PERSTAT1
02AC 001C - 02AC 001F
02AC 0020
-
EMACCFG
EMAC Configuration Register
Reserved
02AC 0024 - 02AC 002B
02AC 002C
-
PERCFG1
Peripheral Configuration Register 1
Reserved
02AC 0030 - 02AC 0053
02AC 0054
-
EMUBUFPD
-
Emulator Buffer Powerdown Register
Reserved
02AC 0058
C64x+ Megamodule
89
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
6 Device Operating Conditions
6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)(1)
Supply voltage range:
(2)
CVDD
-0.5 V to 1.5 V
-0.5 V to 4.2 V
-0.5 to 2.5 V
(2)
DVDD33
(2)
DVDDR, DVDD18, AVDLL1, AVDLL2
1.5-V operation
1.8-V operation
-0.5 V to 1.98 V
-0.5 V to 2.5 V
-0.5 V to 1.5 V
-0.5 V to 1.5 V
-0.5 V to 4.2 V
-0.5 V to DVDD33 + 0.5 V
TBD
(2)
DVDD15
(2)
DVDD12, DVDDRM, AVDDT, AVDDA
PLLV1, PLLV2(2)
Input voltage (VI) range:
3.3-V pins (except PCI-capable pins)
PCI-capable pins
SRIO pins
RGMII pins
TBD
DDR2 memory controller pins
3.3-V pins (except PCI-capable pins)
PCI-capable pins
-0.5 V to 2.5 V
-0.5 V to 4.2 V
-0.5 V to DVDD33 + 0.5 V
TBD
Output voltage (VO) range:
SRIO pins
RGMII pins
TBD
DDR2 memory controller pins
-0.5 V to 2.5 V
0°C to 90°C
Operating case temperature range, TC: (default)
Storage temperature range, Tstg
–65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
6.2 Recommended Operating Conditions
MIN
1.17
NOM
MAX UNIT
CVDD
Supply voltage, Core
Supply voltage, I/O
Supply voltage, I/O
Supply voltage, I/O
Supply voltage, I/O
Reference voltage
1.2
1.24
3.46
V
V
V
V
V
V
V
V
V
V
DVDD33
DVDD18
AVDLL1
AVDLL2
VREFSSTL
3.14
3.3
1.71
1.8
1.89
1.71
1.8
1.89
1.71
1.8
0.50DVDD18
1.8
1.89
0.49DVDD18
1.71
0.51DVDD18
1.89
1.8-V operation
1.5-V operation
1.8-V operation
1.5-V operation
Supply voltage, I/O [required only
for EMAC RGMII]
DVDD15
1.43
1.5
1.57
0.855
0.713
0.9
0.945
0.787
VREFHSTL
Reference voltage
0.75
DVDD12
,
DVDDRM
,
Supply voltage, I/O [required only for RapidIO]
1.14
1.2
1.26
V
AVDDA
AVDDT
,
DVDDR
Supply voltage, I/O [required only for RapidIO]
Supply voltage, PLL
1.71
1.71
0
1.8
1.8
0
1.89
1.89
0
V
V
V
PLLV1,
PLLV2
VSS
Supply ground
90
Device Operating Conditions
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Recommended Operating Conditions (continued)
MIN
NOM
MAX UNIT
3.3 V pins (except
PCI-capable and
I2C pins)
2
V
PCI-capable pins
I2C pins
0.5DVDD33
0.7DVDD33
DVDD33 + 0.5
V
V
V
V
VIH
High-level input voltage
SRIO pins
RGMII pins
TBD
TBD
VREFHSTL + 0.10
DVDD15 + 0.30
DDR2 memory
controller pins
(DC)
VREFSSTL + 0.125
DVDD18 + 0.3
V
V
3.3 V pins (except
PCI-capable and
I2C pins)
0.8
PCI-capable pins
I2C pins
-0.5
0
0.3DVDD33
0.3DVDD33
TBD
V
V
V
V
VIL
Low-level input voltage
SRIO pins
TBD
-0.3
RGMII pins
VREFHSTL - 0.1
DDR2 memory
controller pins
(DC)
-0.3
0
VREFSSTL - 0.125
V
TC
Operating case temperature
90 °C
Device Operating Conditions
91
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6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS(1)
3.3-V pins (except
PCI-capable and I2C
pins)
DVDD33 = MIN,
IOH = MAX
2.4
V
IOH = -0.5 mA,
DVDD33 = 3.3 V
(2)
PCI-capable pins
0.9DVDD33
V
VOH
High-level output voltage
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
TBD
TBD
V
V
DDR2 memory
controller pins
TBD
TBD
TBD
3.3-V pins (except
PCI-capable and I2C
pins)
DVDD33 = MIN,
IOL = MAX
0.4
V
V
V
IOL = 1.5 mA,
DVDD33 = 3.3 V
(2)
PCI-capable pins
0.2DVDD33
Pulled up to 3.3
V, 3 mA sink
current
VOL
Low-level output voltage
I2C pins
0
0.4
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
TBD
TBD
V
V
DDR2 memory
controller pins
TBD
TBD
TBD
VI = VSS to
DVDD33, no
opposing
-1
1
uA
uA
internal resistor
VI = VSS to
DVDD33
,
3.3-V pins (except
PC-capableI and I2C
pins)
opposing
TBD
TBD
internal pullup
resistor(3)
VI = VSS to
DVDD33
,
II
Input current [DC]
opposing
internal
uA
pulldown
resistor(3)
0.1DVDD33≤ VI≤
0.9DVDD33
I2C pins
-10
1-
uA
uA
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
DDR2 memory
controller pins
TBD
TBD
0 < VIP
DVDD33 = 3.3 V
<
IIP
Input leakage current (PCI) [DC](4)
-1000
20
uA
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Table TBD
and Table TBD, respectively.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
92
Device Operating Conditions
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) (continued)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS(1)
AECLKOUT,
CLKR1/GP[0],
CLKX1/GP[3],
SYSCLK3/GP[1],
EMU[18:0], CLKR0,
CLKX0
-8
mA
EMIF pins (except
AECLKOUT), NMI,
TOUT0L, TINP0L,
TOUT1L, TINP1L,
PCI_EN,
UTOPIA-capable pins
(except URADDR[4:0]
and UXADDR[2:0]),
RESETSTAT,
McBSP-capable pins
(except CLKR1/GP[0],
CLKX1/GP[3], CLKR0,
CLKX0), GP[7:4], and
TDO
-4
mA
mA
High-level output current
[DC]
IOH
TRST, TCLK, TDI,
TMS
TBD
POR
TBD
-0.5(2)
mA
mA
mA
mA
PCI-capable pins
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
DDR2 memory
controller pins
TBD
TBD
mA
AECLKOUT,
CLKR1/GP[0],
CLKX1/GP[3],
SYSCLK3/GP[1],
EMU[18:0], CLKR0,
CLKX0
8
mA
EMIF pins (except
AECLKOUT), NMI,
TOUT0L, TINP0L,
TOUTP1L, TINP1L,
PCI_EN,
UTOPIA-capable pins
(except URADDR[4:0]
and UXADDR[2:1]),
RESETSTAT,
McBSP-capable pins
(except CLKR1/GP[0],
CLKX1/GP[3], CLKR0,
CLKX0), GP[7:4], and
TDO
4
mA
mA
Low-level output current
[DC]
IOL
TRST, TCLK, TDI,
TMS
0.5
POR
8
mA
mA
mA
mA
PCI-capable pins
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
TBD
DDR2 memory
controller pins
TBD
TBD
mA
Device Operating Conditions
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Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) (continued)
TEST
PARAMETER
MIN
TYP
MAX UNIT
CONDITIONS(1)
VO = DVDD33 or
0 V
3.3-V pins
-20
20
uA
SRIO pins
RGMII pins
TBD
TBD
TBD
TBD
uA
uA
Off-state output current
[DC]
IOZ
DDR2 memory
controller pins
TBD
TBD
uA
CVDD = 1.2 V,
CPU clock =
1000 MHz
ICDD
Core supply current(5)
TBD
TBD
mA
IDDD
Ci
I/O supply current(5)
Input capacitance
Output capacitance
TBD
mA
pF
pF
10
10
Co
(5) TBD
94
Device Operating Conditions
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
7 C64x+ Peripheral Information and Electrical Specifications
7.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission
line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
V
ref
= 1.5 V
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
C64x+ Peripheral Information and Electrical Specifications
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7.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external
device and from the external device to the DSP. This round-trip delay tends to negatively impact the input
setup time margin, but also tends to improve the input hold time margins (see Table 7-1 and Figure 7-4).
Figure 7-4 represents a general transfer between the DSP and an external device. The figure also
represents board route delays and how they are perceived by the DSP and the external device.
Table 7-1. Board-Level Timing Example
(see Figure 7-4)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
AECLKOUT
(Output from DSP)
1
AECLKOUT
(Input to External Device)
2
3
(A)
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
(B)
Data Signals
(Output from External Device)
9
10
11
(B)
Data Signals
(Input to DSP)
A. Control signals include data for Writes.
B. Data signals are generated during Reads from an external device.
Figure 7-4. Board-Level Input/Output Timings
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7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
7.3 Power Supplies
7.3.1 Power-Supply Sequencing
TI recommends the power-supply sequence options shown in Figure 7-5 and Figure 7-6. For Option 2,
after the DVDD33 supply is stable, the remaining power supplies can be powered up at the same time as
CVDD as long as their supply voltage never exceeds the CVDD voltage during powerup. Some TI
power-supply devices include an "auto-track" feature that can be used to ensure one supply voltage
always stays below another during powerup.
DV
DD33
CV
DD12
DV
DD18
1
2
V
(DDR2)
REFSSTL
3
DV
DD15
V
(RMII)
REFHSTL
4
DV
DD12
Figure 7-5. Power-Supply Sequence (Option 1)
DV
CV
DD33
1
DD12
2
All other
power supplies
Figure 7-6. Power-Supply Sequence (Option 2)
Table 7-2. Timing Requirements for Power-Supply Sequence (Option 1)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tsu(DVDD33-CVDD12) Setup time, DVDD33 supply stable before CVDD12 supply stable
0.5
200
ms
ms
Setup time, CVDD12 supply stable before DVDD18 supply and VREFSSTL
reference voltage stable
tsu(CVDD12-DVDD18)
0.5
200
200
200
Setup time, DVDD18 supply and VREFSSTL reference voltage stable before
tsu(DVDD18-DVDD15)
3
4
0.5
0.5
ms
ms
DVDD15 supply and VREFHSTL reference voltage stable
Setup time, DVDD15 supply and VREFHSTL reference voltage stable before
DVDD12 supply stable
tsu(DVDD15-DVDD12)
C64x+ Peripheral Information and Electrical Specifications
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Table 7-3. Timing Requirements for Power-Supply Sequence (Option 2)
-720
-850
-1000
NO.
UNIT
MIN
MAX
200
1
2
tsu(DVDD33-CVDD12) Setup time, DVDD33 supply stable before CVDD12 supply stable
tsu(CVDD12-ALLSUP) Setup time, CVDD12 supply stable before all other supplies stable
0.5
0
ms
ms
200
7.3.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors, therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. As with the selection of any component, verification of capacitor availability over the
product's production lifetime should be considered.
7.3.3 Power-Down Operation
One of the power goals for the C6455 is to reduce power dissipation due to unused peripherals. There are
different ways to power down peripherals on the C6455 device.
Some peripherals can be statically powered down at device reset through the device configuration pins
(see Section 3.1, Device Configuration at Device Reset). Once in a static power-down state, the peripheral
is held in reset and its clock is turned off. Peripherals cannot be enabled once they are in a static
power-down state. To take a peripheral out of the static power-down state, a device reset must be
executed with a different configuration pin setting.
After device reset, all peripherals on the C6455 device are in a disabled state and must be enabled by
software before being used. It is possible to enable only the peripherals needed by the application while
keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks
gated. For more information on how to enable peripherals, see Section 3.3, Peripheral Selection After
Device Reset.
Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not
possible to disable these peripherals after the boot process is complete.
The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+
megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or
the entire C64x+ megamodule through the power-down controller based on its own execution thread or in
response to an external stimulus from a host or global controller. More information on the power-down
features of the C64x+ Megamodule can be found in the TMS320C64x+ DSP Megamodule Reference
Guide (literature number SPRU871).
7.4 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two
memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers
(e.g., data movement between external memory and internal memory), performs sorting or subframe
extraction of various data structures, services event driven peripherals such as a McBSP or the UTOPIA
port, and offloads data transfers from the device CPU.
The EDMA3 includes the following features:
98
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
•
•
Fully orthogonal transfer description
–
–
–
3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames)
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
Flexible transfer definition:
–
–
Increment or FIFO transfer addressing modes
Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
–
Chaining allows multiple transfers to execute with one event
•
256 PaRAM entries
–
–
Used to define transfer context for channels
Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
•
•
64 DMA channels
–
Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
4 Quick DMA (QDMA) channels
–
–
Used for software-driven transfers
Triggered upon writing to a single PaRAM set entry
•
•
•
4 transfer controllers/event queues with programmable system-level priority
Interrupt generation for transfer completion and error conditions
Debug visibility
–
–
Queue watermarking/threshold allows detection of maximum usage of event queues
Error and status recording to facilitate debug
•
Memory protection support
–
–
Proxied memory protection for transfer request submission
Support for active memory protection for accesses to PaRAM and registers
Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 4-1
lists the peripherals that can be accessed by the transfer controllers.
7.4.1 EDMA Device-Specific Information
A DSP interrupt must be generated at the end of an HPI or PCI boot operation to begin execution of the
loaded application. Since the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event
DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must
be cleared by software before triggering transfers on DMA channel 0.
7.4.2 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move
data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals. Table 7-4 lists the source of the synchronization event associated with each of the
DMA channels. On the C6455, the association of each synchronization event and DMA channel is fixed
and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,
processed, prioritized, linked, chained, and cleared, etc., see the TMS320C645x DSP Enhanced DMA
(EDMA) Controller User's Guide (literature number SPRU966).
C64x+ Peripheral Information and Electrical Specifications
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Table 7-4. C6455 EDMA Channel Synchronization Events(1)
EDMA
CHANNEL
BINARY
EVENT NAME
EVENT DESCRIPTION
0(2)
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
-
DSP_EVT
HPI/PCI-to-DSP event
1
TEVTLO0
Timer 0 lower counter event
Timer 0 high counter event
None
2
TEVTHI0
3
-
4
-
-
None
5
None
6
-
None
7
-
None
8
-
None
9
-
None
10
11
12
13
14
15
16
17
18-19
20
21-27
28
29
30
31
32
33-39
40
41-43
44
45
46-47
48
49
50
51
52
53
54
55
56
57
-
None
-
None
XEVT0
REVT0
XEVT1
REVT1
TEVTLO1
TEVTHI1
-
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
Timer 1 lower counter event
Timer 1 high counter event
None
001 0100
-
RIOINT1
-
RapidIO Interrupt 1
None
001 1100
001 1101
001 1110
001 1111
010 0000
-
VCP2REVT
VCP2XEVT
TCP2REVT
TCP2XEVT
UREVT
-
VCP2 receive event
VCP2 transmit event
TCP2 receive event
TCP2 transmit event
UTOPIA receive event
None
010 1000
-
UXEVT
-
UTOPIA transmit event
None
010 1100
010 1101
-
ICREVT
ICXEVT
-
I2C receive event
I2C transmit event
None
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPINT8
GPINT9
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
GPIO event 4
GPIO event 5
GPIO event 6
GPIO event 7
GPIO event 8
GPIO event 9
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C645x DSP Enhanced
DMA (EDMA) Controller User's Guide (literature number SPRU966).
(2) HPI and PCI boots are terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event
Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.
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Table 7-4. C6455 EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
BINARY
EVENT NAME
EVENT DESCRIPTION
58
59
60
61
62
63
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
7.4.3 EDMA Peripheral Register Description(s)
Table 7-5. EDMA Registers
HEX ADDRESS RANGE
02A0 0000
02A0 0004
02A0 0008 - 02A0 00FC
02A0 0100
02A0 0104
02A0 0108
02A0 010C
02A0 0110
02A0 0114
02A0 0118
02A0 011C
02A0 0120
02A0 0124
02A0 0128
02A0 012C
02A0 0130
02A0 0134
02A0 0138
02A0 013C
02A0 0140
02A0 0144
02A0 0148
02A0 014C
02A0 0150
02A0 0154
02A0 0158
02A0 015C
02A0 0160
02A0 0164
02A0 0168
02A0 016C
02A0 0170
02A0 0174
02A0 0178
02A0 017C
ACRONYM
REGISTER NAME
PID
Peripheral ID Register
CCCFG
EDMA3CC Configuration Register
Reserved
-
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP12
DCHMAP13
DCHMAP14
DCHMAP15
DCHMAP16
DCHMAP17
DCHMAP18
DCHMAP19
DCHMAP20
DCHMAP21
DCHMAP22
DCHMAP23
DCHMAP24
DCHMAP25
DCHMAP26
DCHMAP27
DCHMAP28
DCHMAP29
DCHMAP30
DCHMAP31
DMA Channel 0 Mapping Register
DMA Channel 1 Mapping Register
DMA Channel 2 Mapping Register
DMA Channel 3 Mapping Register
DMA Channel 4 Mapping Register
DMA Channel 5 Mapping Register
DMA Channel 6 Mapping Register
DMA Channel 7 Mapping Register
DMA Channel 8 Mapping Register
DMA Channel 9 Mapping Register
DMA Channel 10 Mapping Register
DMA Channel 11 Mapping Register
DMA Channel 12 Mapping Register
DMA Channel 13 Mapping Register
DMA Channel 14 Mapping Register
DMA Channel 15 Mapping Register
DMA Channel 16 Mapping Register
DMA Channel 17 Mapping Register
DMA Channel 18 Mapping Register
DMA Channel 19 Mapping Register
DMA Channel 20 Mapping Register
DMA Channel 21 Mapping Register
DMA Channel 22 Mapping Register
DMA Channel 23 Mapping Register
DMA Channel 24 Mapping Register
DMA Channel 25 Mapping Register
DMA Channel 26 Mapping Register
DMA Channel 27 Mapping Register
DMA Channel 28 Mapping Register
DMA Channel 29 Mapping Register
DMA Channel 30 Mapping Register
DMA Channel 31 Mapping Register
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Table 7-5. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0180
ACRONYM
DCHMAP32
DCHMAP33
DCHMAP34
DCHMAP35
DCHMAP36
DCHMAP37
DCHMAP38
DCHMAP39
DCHMAP40
DCHMAP41
DCHMAP42
DCHMAP43
DCHMAP44
DCHMAP45
DCHMAP46
DCHMAP47
DCHMAP48
DCHMAP49
DCHMAP50
DCHMAP51
DCHMAP52
DCHMAP53
DCHMAP54
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DCHMAP59
DCHMAP60
DCHMAP61
DCHMAP62
DCHMAP63
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
-
REGISTER NAME
DMA Channel 32 Mapping Register
02A0 0184
DMA Channel 33 Mapping Register
DMA Channel 34 Mapping Register
DMA Channel 35 Mapping Register
DMA Channel 36 Mapping Register
DMA Channel 37 Mapping Register
DMA Channel 38 Mapping Register
DMA Channel 39 Mapping Register
DMA Channel 40 Mapping Register
DMA Channel 41 Mapping Register
DMA Channel 42 Mapping Register
DMA Channel 43 Mapping Register
DMA Channel 44 Mapping Register
DMA Channel 45 Mapping Register
DMA Channel 46 Mapping Register
DMA Channel 47 Mapping Register
DMA Channel 48 Mapping Register
DMA Channel 49 Mapping Register
DMA Channel 50 Mapping Register
DMA Channel 51 Mapping Register
DMA Channel 52 Mapping Register
DMA Channel 53 Mapping Register
DMA Channel 54 Mapping Register
DMA Channel 55 Mapping Register
DMA Channel 56 Mapping Register
DMA Channel 57 Mapping Register
DMA Channel 58 Mapping Register
DMA Channel 59 Mapping Register
DMA Channel 60 Mapping Register
DMA Channel 61 Mapping Register
DMA Channel 62 Mapping Register
DMA Channel 63 Mapping Register
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
Reserved
02A0 0188
02A0 018C
02A0 0190
02A0 0194
02A0 0198
02A0 019C
02A0 01A0
02A0 01A4
02A0 01A8
02A0 01AC
02A0 01B0
02A0 01B4
02A0 01B8
02A0 01BC
02A0 01C0
02A0 01C4
02A0 01C8
02A0 01CC
02A0 01D0
02A0 01D4
02A0 01D8
02A0 01DC
02A0 01E0
02A0 01E4
02A0 01E8
02A0 01EC
02A0 01F0
02A0 01F4
02A0 01F8
02A0 01FC
02A0 0200
02A0 0204
02A0 0208
02A0 020C
02A0 0210 - 02A0 021C
02A0 0220 - 02A0 023C
02A0 0240
-
Reserved
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
-
DMA Queue Number Register 0
DMA Queue Number Register 1
DMA Queue Number Register 2
DMA Queue Number Register 3
Reserved
02A0 0244
02A0 0248
02A0 024C
02A0 0250 - 02A0 025C
02A0 0260
QDMAQNUM
-
QDMA Queue Number Register
Reserved
02A0 0264 - 02A0 0280
02A0 0284
QUEPRI
Queue Priority Register
02A0 0288 - 02A0 02FC
-
Reserved
102
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Table 7-5. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0300
02A0 0304
02A0 0308
02A0 030C
02A0 0310
02A0 0314
02A0 0318
02A0 031C
02A0 0320
02A0 0324 - 02A0 033C
02A0 0340
02A0 0344
02A0 0348
02A0 034C
02A0 0350
02A0 0354
02A0 0358
02A0 035C
02A0 0360
02A0 0364
02A0 0368
02A0 036C
02A0 0370
02A0 0374
02A0 0378
02A0 0380
02A0 0384
02A0 0388
02A0 038C
02A0 0390
02A0 0394 - 02A0 039C
02A0 0400
02A0 0404
02A0 0408
02A0 040C
02A0 0410
02A0 0414
02A0 0418
02A0 041C
02A0 0420
02A0 0424
02A0 0428
02A0 042C
02A0 0430
02A0 0434
02A0 0438
02A0 043C
ACRONYM
EMR
REGISTER NAME
Event Missed Register
EMRH
EMCR
EMCRH
QEMR
QEMCR
CCERR
CCERRCLR
EEVAL
-
Event MissedRegister High
Event Missed Clear Register
Event Missed Clear Register High
QDMA Event Missed Register
QDMA Event Missed Clear Register
EDMA3CC Error Register
EDMA3CC Error Clear Register
Error Evaluate Register
Reserved
DRAE0
DRAEH0
DRAE1
DRAEH1
DRAE2
DRAEH2
DRAE3
DRAEH3
DRAE4
DRAEH4
DRAE5
DRAEH5
DRAE6
DRAEH6
DRAE7
DRAEH7
QRAE0
QRAE1
QRAE2
QRAE3
-
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register High for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register High for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register High for Region 2
DMA Region Access Enable Register for Region 3
DMA Region Access Enable Register High for Region 3
DMA Region Access Enable Register for Region 4
DMA Region Access Enable Register High for Region 4
DMA Region Access Enable Register for Region 5
DMA Region Access Enable Register High for Region 5
DMA Region Access Enable Register for Region 6
DMA Region Access Enable Register High for Region 6
DMA Region Access Enable Register for Region 7
DMA Region Access Enable Register High for Region 7
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Reserved
Q0E0
Event Queue 0 Entry Register 0
Q0E1
Event Queue 0 Entry Register 1
Q0E2
Event Queue 0 Entry Register 2
Q0E3
Event Queue 0 Entry Register 3
Q0E4
Event Queue 0 Entry Register 4
Q0E5
Event Queue 0 Entry Register 5
Q0E6
Event Queue 0 Entry Register 6
Q0E7
Event Queue 0 Entry Register 7
Q0E8
Event Queue 0 Entry Register 8
Q0E9
Event Queue 0 Entry Register 9
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Event Queue 0 Entry Register 10
Event Queue 0 Entry Register 11
Event Queue 0 Entry Register 12
Event Queue 0 Entry Register 13
Event Queue 0 Entry Register 14
Event Queue 0 Entry Register 15
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Table 7-5. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 0440
02A0 0444
02A0 0448
02A0 044C
02A0 0450
02A0 0454
02A0 0458
02A0 045C
02A0 0460
02A0 0464
02A0 0468
02A0 046C
02A0 0470
02A0 0474
02A0 0478
02A0 047C
02A0 0480
02A0 0484
02A0 0488
02A0 048C
02A0 0490
02A0 0494
02A0 0498
02A0 049C
02A0 04A0
02A0 04A4
02A0 04A8
02A0 04AC
02A0 04B0
02A0 04B4
02A0 04B8
02A0 04BC
02A0 04C0
02A0 04C4
02A0 04C8
02A0 04CC
02A0 04D0
02A0 04D4
02A0 04D8
02A0 04DC
02A0 04E0
02A0 04E4
02A0 04E8
02A0 04EC
02A0 04F0
02A0 04F4
02A0 04F8
ACRONYM
Q1E0
Q1E1
Q1E2
Q1E3
Q1E4
Q1E5
Q1E6
Q1E7
Q1E8
Q1E9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Q2E1
Q2E2
Q2E3
Q2E4
Q2E5
Q2E6
Q2E7
Q2E8
Q2E9
Q2E10
Q2E11
Q2E12
Q2E13
Q2E14
Q2E15
Q3E0
Q3E1
Q3E2
Q3E3
Q3E4
Q3E5
Q3E6
Q3E7
Q3E8
Q3E9
Q3E10
Q3E11
Q3E12
Q3E13
Q3E14
REGISTER NAME
Event Queue 1 Entry Register 0
Event Queue 1 Entry Register 1
Event Queue 1 Entry Register 2
Event Queue 1 Entry Register 3
Event Queue 1 Entry Register 4
Event Queue 1 Entry Register 5
Event Queue 1 Entry Register 6
Event Queue 1 Entry Register 7
Event Queue 1 Entry Register 8
Event Queue 1 Entry Register 9
Event Queue 1 Entry Register 10
Event Queue 1 Entry Register 11
Event Queue 1 Entry Register 12
Event Queue 1 Entry Register 13
Event Queue 1 Entry Register 14
Event Queue 1 Entry Register 15
Event Queue 2 Entry Register 0
Event Queue 2 Entry Register 1
Event Queue 2 Entry Register 2
Event Queue 2 Entry Register 3
Event Queue 2 Entry Register 4
Event Queue 2 Entry Register 5
Event Queue 2 Entry Register 6
Event Queue 2 Entry Register 7
Event Queue 2 Entry Register 8
Event Queue 2 Entry Register 9
Event Queue 2 Entry Register 10
Event Queue 2 Entry Register 11
Event Queue 2 Entry Register 12
Event Queue 2 Entry Register 13
Event Queue 2 Entry Register 14
Event Queue 2 Entry Register 15
Event Queue 3 Entry Register 0
Event Queue 3 Entry Register 1
Event Queue 3 Entry Register 2
Event Queue 3 Entry Register 3
Event Queue 3 Entry Register 4
Event Queue 3 Entry Register 5
Event Queue 3 Entry Register 6
Event Queue 3 Entry Register 7
Event Queue 3 Entry Register 8
Event Queue 3 Entry Register 9
Event Queue 3 Entry Register 10
Event Queue 3 Entry Register 11
Event Queue 3 Entry Register 12
Event Queue 3 Entry Register 13
Event Queue 3 Entry Register 14
104
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Table 7-5. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 04FC
ACRONYM
Q3E15
-
REGISTER NAME
Event Queue 3 Entry Register 15
02A0 0500 - 02A0 051C
02A0 0520 - 02A0 05FC
02A0 0600
Reserved
-
Reserved
QSTAT0
QSTAT1
QSTAT2
QSTAT3
-
Queue Status Register 0
02A0 0604
Queue Status Register 1
02A0 0608
Queue Status Register 2
02A0 060C
Queue Status Register 3
02A0 0610 - 02A0 061C
02A0 0620
Reserved
QWMTHRA
-
Queue Watermark Threshold A Register
Reserved
02A0 0624 - 02A0 063C
02A0 0640
CCSTAT
-
EDMA3CC Status Register
Reserved
02A0 0644 - 02A0 06FC
02A0 0700 - 02A0 07FC
02A0 0800
-
Reserved
MPFAR
MPFSR
MPFCR
MPPA0
MPPA1
MPPA2
MPPA3
MPPA4
MPPA5
MPPA6
MPPA7
-
Memory Protection Fault Address Register
Memory Protection Fault Status Register
Memory Protection Fault Command Register
Memory Protection Page Attribute Register 0
Memory Protection Page Attribute Register 1
Memory Protection Page Attribute Register 2
Memory Protection Page Attribute Register 3
Memory Protection Page Attribute Register 4
Memory Protection Page Attribute Register 5
Memory Protection Page Attribute Register 6
Memory Protection Page Attribute Register 7
Reserved
02A0 0804
02A0 0808
02A0 080C
02A0 0810
02A0 0814
02A0 0818
02A0 081C
02A0 0820
02A0 0824
02A0 0828
02A0 082C - 02A0 0FFC
02A0 1000
ER
Event Register
02A0 1004
ERH
Event Register High
02A0 1008
ECR
Event Clear Register
02A0 100C
ECRH
ESR
Event Clear Register High
Event Set Register
02A0 1010
02A0 1014
ESRH
CER
Event Set Register High
02A0 1018
Chained Event Register
02A0 101C
CERH
EER
Chained Event Register High
Event Enable Register
02A0 1020
02A0 1024
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
02A0 1028
02A0 102C
02A0 1030
02A0 1034
02A0 1038
02A0 103C
SERH
SECR
SECRH
-
02A0 1040
02A0 1044
02A0 1048 - 02A0 104C
02A0 1050
IER
Interrupt Enable Register
02A0 1054
IERH
Interrupt Enable High Register
Interrupt Enable Clear Register
02A0 1058
IECR
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Table 7-5. EDMA Registers (continued)
HEX ADDRESS RANGE
02A0 105C
ACRONYM
REGISTER NAME
Interrupt Enable Clear High Register
IECRH
02A0 1060
IESR
Interrupt Enable Set Register
Interrupt Enable Set High Register
Interrupt Pending Register
Interrupt Pending High Register
Interrupt Clear Register
Interrupt Clear High Register
Interrupt Evaluate Register
Reserved
02A0 1064
IESRH
02A0 1068
IPR
02A0 106C
IPRH
02A0 1070
ICR
02A0 1074
ICRH
02A0 1078
IEVAL
02A0 107C
-
02A0 1080
QER
QDMA Event Register
02A0 1084
QEER
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 1088
QEECR
02A0 108C
QEESR
02A0 1090
QSER
02A0 1094
QSECR
02A0 1098 - 02A0 1FFF
02A0 2000 - 02A0 2097
02A0 2098 - 02A0 21FF
02A0 2200 - 02A0 2297
02A0 2298 - 02A0 23FF
02A0 2400 - 02A0 2497
02A0 2498 - 02A0 25FF
02A0 2600 - 02A0 2697
02A0 2698 - 02A0 27FF
02A0 2800 - 02A0 2897
02A0 2898 - 02A0 29FF
02A0 2A00 - 02A0 2A97
02A0 2A98 - 02A0 2BFF
02A0 2C00 - 02A0 2C97
02A0 2C98 - 02A0 2DFF
02A0 2E00 - 02A0 2E97
02A0 2E98 - 02A0 2FFF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Shadow Region 0 Channel Registers
Reserved
Shadow Region 1 Channel Registers
Reserved
Shadow Region 2 Channel Registers
Reserved
Shadow Region 3 Channel Registers
Reserved
Shadow Region 4 Channel Registers
Reserved
Shadow Region 5 Channel Registers
Reserved
Shadow Region 6 Channel Registers
Reserved
Shadow Region 7 Channel Registers
Reserved
Table 7-6. EDMA Parameter RAM(1)
HEX ADDRESS RANGE
02A0 4000 - 02A0 401F
02A0 4020 - 02A0 403F
02A0 4040 - 02A0 405F
02A0 4060 - 02A0 407F
02A0 4080 - 02A0 409F
02A0 40A0 - 02A0 40BF
02A0 40C0 - 02A0 40DF
02A0 40F0 - 02A0 40FF
02A0 4100 - 02A0 411F
02A0 40D8 - 02A0 40EF
ACRONYM
REGISTER NAME
-
-
-
-
-
-
-
-
-
-
Parameter Set 0
Parameter Set 1
Parameter Set 2
Parameter Set 3
Parameter Set 4
Parameter Set 5
Parameter Set 6
Parameter Set 7
Parameter Set 8
Parameter Set 9
(1) The C6455 device has 256 EDMA parameter sets total. Each parameter set can be used as a DMA entry, a QDMA entry, or a link entry.
106 C64x+ Peripheral Information and Electrical Specifications
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Table 7-6. EDMA Parameter RAM (continued)
HEX ADDRESS RANGE
...
ACRONYM
REGISTER NAME
...
02A0 47E0 - 02A0 47FF
02A0 4800 - 02A0 481F
02A0 4820 - 02A0 483F
...
-
-
-
Parameter Set 63
Parameter Set 64
Parameter Set 65
...
02A0 5FC0 - 02A0 4FDF
02A0 5FE0 - 02A0 4FFF
-
-
Parameter Set 254
Parameter Set 255
7.5 Interrupts
7.5.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt
Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the
twelve CPU interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 8-4 shows
the mapping of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the
default interrupt mapping of the device. The remaining events must be mapped using software.
For more information on the Interrupt Controller, see the TMS320C64x+ DSP Megamodule Reference
Guide (literature number SPRU871).
Table 7-7. C6455 DSP Interrupts
EVENT NUMBER
INTERRUPT EVENT
EVT0
INTERRUPT SOURCE
0(1)
1(1)
2(1)
Interrupt Controller output of event combiner 0, for events 1 - 31.
Interrupt Controller output of event combiner 1, for events 32 - 63.
Interrupt Controller output of event combiner 2, for events 64 - 95.
Interrupt Controller output of event combiner 3, for events 96 - 127.
EVT1
EVT2
3(1)
EVT3
4 - 8(2)
Reserved
Reserved. Do not use.
EMU interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
9(2)
EMU_DTDMA
10(2)
11(2)
12(2)
13(2)
14(2)
15(2)
16
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMA0
Reserved. Do not use.
EMU real-time data exchange (RTDX) receive complete
EMU RTDX transmit complete
IDMA channel 0 interrupt
IDMA channel 1 interrupt
HPI/PCI-to-DSP interrupt
I2C interrupt
IDMA1
DSPINT
I2CINT
17
MACINT
Ethernet MAC interrupt
18
AEASYNCERR
Reserved
EMIFA error interrupt
19
Reserved. Do not use.
20
RIOINT0
RapidIO interrupt 0
21
RIOINT1
RapidIO interrupt 1
22
RIOINT4
RapidIO interrupt 4
23
Reserved
Reserved. Do not use.
24
EDMA3CC_GINT
EDMA3 channel global completion interrupt
(1) Interrupts 0 through 3 are non-maskable and fixed.
(2) Interrupts 4 through 15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
shows the default interrupt sources for Interrupts 4 through 15.
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Table 7-7. C6455 DSP Interrupts (continued)
EVENT NUMBER
INTERRUPT EVENT
Reserved
INTERRUPT SOURCE
25 - 31
32
Reserved. Do not use.
VCP2 error interrupt
TCP2 error interrupt
Reserved. Do not use.
UTOPIA interrupt
VCP2_INT
33
TCP2_INT
34 - 35
36
Reserved
UINT
37 - 39
40
Reserved
Reserved. Do not use.
RINT0
McBSP0 receive interrupt
McBSP0 transmit interrupt
McBSP1 receive interrupt
McBSP1 transmit interrupt
Reserved. Do not use.
41
XINT0
42
RINT1
43
XINT1
44 - 49
51
Reserved
GPINT0
GPIO interrupt
52
GPINT1
GPIO interrupt
53
GPINT2
GPIO interrupt
54
GPINT3
GPIO interrupt
55
GPINT4
GPIO interrupt
56
GPINT5
GPIO interrupt
57
GPINT6
GPIO interrupt
58
GPINT7
GPIO interrupt
59
GPINT8
GPIO interrupt
60
GPINT9
GPIO interrupt
61
GPINT10
GPIO interrupt
62
GPINT11
GPIO interrupt
63
GPINT12
GPIO interrupt
64
GPINT13
GPIO interrupt
65
GPINT14
GPIO interrupt
66
GPINT15
GPIO interrupt
67
TINTLO0
Timer 0 lower counter interrupt
Timer 0 higher counter interrupt
Timer 1 lower counter interrupt
Timer 1 higher counter interrupt
EDMA3CC completion interrupt - Mask0
EDMA3CC completion interrupt - Mask1
EDMA3CC completion interrupt - Mask2
EDMA3CC completion interrupt - Mask3
EDMA3CC completion interrupt - Mask4
EDMA3CC completion interrupt - Mask5
EDMA3CC completion interrupt - Mask6
EDMA3CC completion interrupt - Mask7
EDMA3CC error interrupt
EDMA3CC memory protection interrupt
EDMA3TC0 error interrupt
EDMA3TC1 error interrupt
EDMA3TC2 error interrupt
EDMA3TC3 error interrupt
Reserved. Do not use.
68
TINTHI0
69
TINTLO1
70
TINTHI1
71
EDMA3CC_INT0
EDMA3CC_INT1
EDMA3CC_INT2
EDMA3CC_INT3
EDMA3CC_INT4
EDMA3CC_INT5
EDMA3CC_INT6
EDMA3CC_INT7
EDMA3CC_ERRINT
EDMA3CC_MPINT
EDMA3TC0_ERRINT
EDMA3TC1_ERRINT
EDMA3TC2_ERRINT
EDMA3TC3_ERRINT
Reserved
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86 - 95
Reserved
Reserved. Do not use.
108
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Table 7-7. C6455 DSP Interrupts (continued)
EVENT NUMBER
INTERRUPT EVENT
INTERR
INTERRUPT SOURCE
Interrupt Controller dropped CPU interrupt event
EMC invalid IDMA parameters
Reserved. Do not use.
96
97
EMC_IDMAERR
Reserved
98
99
Reserved
Reserved. Do not use.
100
Reserved
Reserved. Do not use.
101
Reserved
Reserved. Do not use.
102 - 111
112
Reserved
Reserved. Do not use.
Reserved
Reserved. Do not use.
113
Reserved
Reserved. Do not use.
114 - 115
116
Reserved
Reserved. Do not use.
Reserved
Reserved. Do not use.
117
Reserved
Reserved. Do not use.
118
PDC_INT
Powerdown sleep interrupt
Reserved. Do not use.
119
Reserved
120
L1P_CMPA
L1P_DMPA
L1D_CMPA
L1D_DMPA
L2_CMPA
L2_DMPA
IDMA_CMPA
IDMA_BUSERR
L1P CPU memory protection fault
L1P DMA memory protection fault
L1D CPU memory protection fault
L1D DMA memory protection fault
L2 CPU memory protection fault
L2 DMA memory protection fault
IDMA CPU memory protection fault
IDMA bus error interrupt
121
122
123
124
125
126
127
7.5.2 External Interrupts Electrical Data/Timing
Table 7-8. Timing Requirements for External Interrupts(1) (see Figure 7-7)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(NMIL)
tw(NMIH)
Width of the NMI interrupt pulse low
Width of the NMI interrupt pulse high
6P
6P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
NMI
Figure 7-7. NMI Interrupt Timing
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7.6 Reset Controller
The reset controller detects the different type of resets supported on the C6455 device and manages the
distribution of those resets throughout the device.
The C6455 device has several types of resets - power-on reset, warm reset, max reset, system reset and
CPU reset. Table 7-9 explains further the types of reset, the reset initiator, and the effects of each reset on
the chip. See Section 7.6.8, Reset Electrical Data/Timing, for more information on the effects of each reset
on the PLL controllers and their clocks.
Table 7-9. Reset Types
TYPE
INITIATOR
EFFECT(s)
Power-on Reset
POR pin
Resets the entire chip including the test and emulation logic.
Resets everything except for the test and emulation logic and PLL2.
Emulator stays alive during Warm Reset.
Warm Reset
Max Reset
RESET pin
RapidIO [through RIOINT5(1)], Emulator
Same as a Warm Reset.
A system reset maintains memory contents and does not reset the
test and emulation circuitry. The device configuration pins are also
not re-latched and the state of the peripherals (enabled/disabled) is
also not affected.
System Reset
Emulator
HPI/PCI
CPU Local Reset
CPU local reset.
(1) RIOINT5 is used generate a MAX reset only. It is not connected to the device interrupt controller. For more detailed information on the
RIOINT5, see the Serial Rapid I/O (SRIO) Peripheral Reference Guide (literature number TBD).
7.6.1 Power-on Reset (POR Pin)
Power-on Reset is initiated by the POR pin and is used to reset the entire chip, including the test and
emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a
power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies
have reached their normal operating conditions. Note that a device power-up cycle is not required to
initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
While POR is asserted, all pins will be set to high-impedance. After the POR pin is deasserted (driven
high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain
at their reset state until the otherwise configured by their respective peripheral. All peripherals, except
those selected for boot purposes, are disabled after a Power-on Reset and must be enabled through
the Device State Control registers; for more details, see Section 3.3, Peripheral Selection After Device
Reset.
2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted
(low) for a minimum of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI input
clock, PCLK, must also be valid during this time. PCLK is only needed if the PCI module is being used.
If the DDR2 memory controller and the EMAC peripheral are not needed, CLKIN2 can be tied low and,
in this case, the POR pin must remain asserted (low) for a minimum of CLKIN1 cycles after all power
supplies have reached valid operating conditions.
Within the low period of the POR pin, the following happens:
–
The reset signals flow to the entire chip (including the test and emulation logic), resetting modules
that use reset asynchronously.
–
The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks
are propagated throughout the chip to reset modules that use reset synchronously. By default,
PLL1 is in reset and unlocked.
–
The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held
in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and
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all the system clocks are invalid at this point.
The RESETSTAT pin stays asserted (low), indicating the device is in reset.
–
3. The POR pin may now be deasserted (driven high).
When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers
change their system clocks to their default divide-down values. PLL2 is taken out of reset and
automatically starts its locking sequence. Other device initialization is also started.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause the system clocks are restarted at their default
divide-by settings.
5. The device is now out of reset, device execution begins as dictated by the selected boot mode (see
Section 2.4, Boot Sequence).
NOTE
To the device, reset is deasserted only when the POR and RESET pins are both
deasserted (driven high). Therefore, in the sequence described above, if the RESET pin
is held low past the low period of the POR pin, then the Power-on Reset will essentially
become a Warm Reset (described in Section 7.6.2). The only exception being that PLL2
is taken out of reset as soon as POR is deasserted (driven high), regardless of the state
of the RESET pin. The RESET pin should not be tied together with the POR pin.
7.6.2 Warm Reset (RESET Pin)
A Warm Reset has the same effects as a Power-on Reset, except that in this case, the test and emulation
logic and PLL2 are not reset.
The following sequence must be followed during a Warm Reset:
1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the minimum 24 CLKIN1 cycles.
Within the low period of the RESET pin, the following happens:
–
The Z group pins, low group pins, and the high group pins are set to their reset state with one
exception:
The PCI pins are not affected by warm reset if the PCI module was enabled before RESET went
low. In this case, PCI pins stay at whatever their value was before RESET went low.
The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules
that use reset asynchronously.
The PLL1 controller is reset thereby switching back to bypass mode and resetting all its registers to
their default values. PLL1 is placed in reset and loses lock. The PLL1 controller clocks start running
at the frequency of the system reference clock. The clocks are propagated throughout the chip to
reset modules that use reset synchronously.
–
–
–
–
The PLL2 controller is reset thereby resetting all its registers to their default values. The PLL2
controller clocks start running at the frequency of the system reference clock. PLL2 is not reset,
therefore it remains locked.
The RESETSTAT pin becomes active (low), indicating the device is in reset.
2. The RESET pin may now be released (driven inactive high).
When the RESET pin is released, the configuration pin values are latched and the PLL controllers
immediately change their system clocks to their default divide-down values. Other device initialization
is also started.
3. After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are
allowed to finish their current cycles and then paused for 10 cycles of their respective system reference
clocks. After the pause the system clocks are restarted at their default divide-by settings.
4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see
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Section 2.4, Boot Sequence).
NOTE
The POR pin should be held inactive (high) throughout the Warm Reset sequence.
Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met.
The RESET pin should not be tied together with the POR pin.
7.6.3 Max Reset
A Max Reset is initiated by the RapidIO peripheral or by the emulator and has the same affect as a Warm
Reset.
7.6.4 System Reset
A System Reset maintains memory contents and does not reset the clock logic or the test and emulation
circuitry. The device configuration pins are also not re-latched and the state of the peripherals
(enabled/disabled) is also not affected. A System Reset is initiated by the emulator.
During a System Reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to
propagate through the system. Internal system clocks are not affected.
2. After the internal reset signal has propagated, the PLL controllers pause and restart their system
clocks for about 10 cycles of their system reference clocks, but retain their configuration. The PLLs
also remain locked.
3. The boot sequence is started after the system clocks are restarted. Since the configuration pins
(including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as
shown in the DEVSTAT register, are used to select the boot mode.
NOTE
A System Reset should not be used if the peripheral used for boot loading was disabled
following boot. A Max Reset should be used instead such that the peripheral can be
properly re-enabled.
7.6.5 CPU Reset
A CPU Reset is initiated by the HPI or PCI peripheral. This reset only affects the CPU. During a
PCI-initiated CPU Reset, the PCI pins are set to their reset state. With the exception of the HRDY/PIRDY
pin, the PCI pins have a reset state of high-impedance; the HRDY/PIRDY pin goes high during reset.
7.6.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority
reset request. The rest request priorities are as follows (high to low):
•
•
•
•
•
Power-on Reset
Maximum Reset
Warm Reset
System Reset
CPU Reset
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7.6.7 Reset Controller Register
The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see
Table 7-15).
7.6.7.1 Reset Type Status Register Description
The rest type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The reset type status register is
shown in Figure 7-8 and described in Table 7-10.
31
15
16
Reserved
R-0
4
3
2
1
0
Reserved
R-0
SRST MRST WRST POR
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-8. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]
Table 7-10. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31:4
3
Field
Value Description
Reserved
SRST
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
System reset.
0
1
System Reset was not the last reset to occur.
System Reset was the last reset to occur.
Max reset.
2
1
0
MRST
WRST
POR
0
1
Max Reset was not the last reset to occur.
Max Reset was the last reset to occur.
Warm reset.
0
1
Warm Reset was not the last reset to occur.
Warm Reset was the last reset to occur.
Power-on reset.
0
1
Power-on Reset was not the last reset to occur.
Power-on Reset was the last reset to occur.
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7.6.8 Reset Electrical Data/Timing
NOTE
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
Table 7-11. Timing Requirements for Reset(1)(2) (see Figure 7-9 and Figure 7-10)
-720
-850
-1000
NO.
UNIT
MIN
MAX
5
6
tw(POR)
Pulse duration, POR low
256D(3)
ns
ns
tw(RESET)
Pulse duration, RESET low
24C
Setup time, boot mode and configuration pins valid before POR high or
RESET high(4)
7
8
tsu(boot)
th(boot)
6P
6P
ns
ns
Hold time, boot mode and configuration pins valid after POR high or
RESET high(4)
(1) C = 1/CLKIN1 clock frequency in ns.
(2) D = 1/CLKIN2 clock frequency in ns.
(3) If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use CLKIN2 cycles.
(4) AEA[19:0], ABA[1:0], and PCI_EN are the boot configuration pins during device reset.
Table 7-12. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 7-10)
–1000
NO.
PARAMETER
UNIT
MIN
MAX
9
td(PORH-RSTATH)
Delay time, POR high AND RESET high to RESETSTAT high
15000C
ns
(1) C = 1/CLKIN1 clock frequency in ns.
For Figure 7-9, note the following:
•
•
Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high
impedance as soon as their respective power supply has reached normal operating coditions. Pins
remain in high impedance until configured otherwise by their respective peripheral.
Low
group
consists
of:
UXDATA0/MTXD0/RMTXD0,
UXDATA3/MTXD3/RMTXD3
UXDATA1/MTXD1/RMTXD1,
,UXDATA4/MTXD4/RMTXD4,
UXDATA2/MTXD2/RMTXD2,
UXENB/MTXEN/RMTXEN, and ABUSREQ. Pins become low as soon as their respective power supply
has reached normal operating conditions. Pins remain low until configured otherwise by their
respective peripheral.
•
High group consists of: AHOLD and HRDY/PIRDY. Pins become high as soon as their respective
power supply has reached normal operating conditions. Pins remain high until configured otherwise by
their respective peripheral.
•
•
All peripherals must be enable through software following a Power-on Reset; for more details, see
Section 7.6.1, Power-on Reset, of this document.
For power-supply sequence requirements, see Section 7.3.1, Power-Supply Sequencing.
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Power Supplies Ramping
Power Supplies Stable
CLKIN1
PCLK
POR
5
RESET
9
RESETSTAT
SYSREFCLK (PLL1C)
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
AECLKOUT (Internal)
7
Boot and Device
Configuration Pins
8
High-Z
Z Group
Low Group
High Group
Undefined
Undefined
Undefined
Low
High
CLKIN2
Undefined
Internal Reset PLL2C
SYSREFCLK (PLL2C)
SYSCLK1 (PLL2C)
(A)
Undefined
Undefined
PLL2 Locked
PLL2 Unlocked
PLL2 Unlocked
(B)
Clock Valid
Clock Valid
A. SYSREFCLK of the PLL2 controller runs at CLKIN2 ×10.
B. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default).
C. Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of tw(POR)
.
Figure 7-9. Power-Up Timing
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CLKIN1
CLKIN2
POR
6
(A)(B)
RESET
9
RESETSTAT
7
8
Boot and
(C)
Device Configuration Pins
A. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see
Section 7.6, Reset Controller of this document.
B. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the
RESET pin during a Warm Reset.
C. Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], and PCI_EN.
Figure 7-10. Warm Reset and Max Reset Timing
CLKIN1
CLKIN2
POR
6
(A)
RESET
9
RESETSTAT
7
8
Boot and
(B)
Device Configuration Pins
A. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see
Section 7.6, Reset Controller of this document.
B. Boot and Device Configurations Inputs (during reset) include: AEA[19:0], ABA[1:0], and PCI_EN.
Figure 7-11. System Reset Timing
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7.7 PLL1 and PLL1 Controller
The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as
well as most of the system peripherals such as the multichannel buffered serial ports (McBSPs) and the
external memory interface (EMIF).
As shown in Figure 7-12, the PLL1 controller features a software-programmable PLL multiplier controller
(PLLM) and five dividers (PREDIV, D2, D3, D4, and D5). The PLL1 controller uses the device input clock
CLKIN1 to generate a system reference clock (SYSREFCLK) and four system clocks (SYSCLK2,
SYSCLK3, SYSCLK4, and SYSCLK5).
PLL1 power is supplied externally via the PLL1 power-supply pin (PLLV1). An external EMI filter circuit
must be added to PLLV1, as shown in Figure 7-12. The 1.8-V supply of the EMI filter must be from the
same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter manufacturer
Murata, part number NFM18CC222R1C3.
All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP
device as possible. For the best performance, TI recommends that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter).
The minimum CLKIN1 rise and fall times should also be observed. For the input clock timing
requirements, see the PLL1 Controller Input and Output Clock Electrical Data/Timing section.
CAUTION
The PLL controller module as described in the TMS320C645x DSP
Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature
number SPRUE56) includes a superset of features, some of which are not supported
on the C6455 DSP. The following sections describe the features that are supported; it
should be assumed that any feature not included in these sections is not supported
by the C6455 DSP.
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TMS320C6455 DSP
+1.8 V
PLLV1
C2
C1
EMI Filter
560 pF 0.1 mF
PLL1 Controller
PLL1
PLLEN (PLLCTL.[0])
SYSREFCLK
DIVIDER PREDIV
(B)
CLKIN1
(C64x+ MegaModule)
/1, /2,
..., /32
PLLM
(A)
DIVIDER D2
x1, x15,
x20, x25,
x30, x32
1
0
ENA
SYSCLK2
/3
PREDEN (PREDIV.[15])
(A)
DIVIDER D3
SYSCLK3
SYSCLK4
/6
DIVIDER D4
/1, /2,
..., /32
ENA
(Internal EMIF Clock Input)
D4EN (PLLDIV4.[15])
D5EN (PLLDIV4.[15])
DIVIDER D5
/1, /2,
..., /32
ENA
SYSCLK5
(Emulation and Trace)
AECLKIN (External EMIF Clock Input)
/1, /2,
..., /8
GP0
CLKDIV
(CTRL.[18:16])
1
0
1
0
AECLKINSEL
(AEA[15] pin)
SYSCLKOUT_EN
(TBD)
(EMIF Input Clock)
EMIFA
AECLKOUT
GP0/SYSCLK4
A. DIVIDER D2 and DIVIDER D3 are always enabled.
B. CLKIN1 is a 3.3-V signal.
Figure 7-12. PLL1 and PLL1 Controller
7.7.1 PLL1 Controller Device-Specific Information
7.7.1.1 Internal Clocks and Maximum Operating Frequencies
As shown in Figure 7-12, the PLL1 controller generates several internal clocks including the system
reference clock (SYSREFCLK), and the system clocks (SYSCLK2/3/4/5). The high-frequency clock signal
SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves as a
reference clock for the rest of the DSP system.
Dividers D2, D3, D4, and D5 divide the high-frequency clock SYSREFCLK to generate SYSCLK2,
SYSCLK3, SYSCLK4, and SYSCLK5, respectively. The system clocks are used to clock different portions
of the DSP:
•
SYSCLK2 is used to clock the switched central resources (SCRs), EDMA3, VCP2, TCP2, and
RapidIO, as well as the data bus interfaces of the EMIFA and DDR2 Memory Controller.
•
SYSCLK3 clocks the PCI, HPI, UTOPIA, McBSP, GPIO, TIMER, and I2C peripherals, as well as the
configuration bus of the PLL2 Controller.
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•
•
SYSCLK4 is used to generate the internal clock for the EMIFA.
SYSCLK5 clocks the emulation and trace logic of the DSP.
The divider ratio bits of dividers D2 and D3 are fixed at ÷3 and ÷6, respectively. The divider ratio bits of
dividers D4 and 54 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5,
respectively.
The PLL multiplier controller (PLLM) and the dividers (D4 and D5) must be programmed after reset. There
is no hardware CLKMODE selection on the C6455 device.
Since the divider ratio bits for D2 and D3 are fixed, the frequency of SYSCLK2 and SYSCLK3 is tied to
the frequency of SYSREFCLK. However, the D4 and D5 can be programmed to divide SYSREFCLK by
any value between 1 and 32. For example, with PLLM in the PLL1 multiply control register set to 10011b
(x20 mode) and a 50 MHz CLKIN1 input, the PLL output PLLOUT is set to 1000 MHz and SYSCLK2 and
SYSCLK3 run at 333 MHz and 166 MHz, respectively. The divider D4 can be programmed through the
PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4, and hence the EMIF, runs at
100 MHz.
All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, SYSCLK4, and
SYSCLK5. The clock generator must not be configured to exceed any of these constraints (certain
combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).
See Table 7-13 for the PLL clocks input and output frequency ranges.
Table 7-13. PLL1 Clock Frequency Ranges
CLOCK SIGNAL
MIN
MAX
66.6
66.6
1000
133
UNIT
MHz
MHz
MHz
MHz
MHz
CLKIN1
PLLREF (PLLEN = 1)(1)
PLLOUT(1)
33.3
400
SYSCLK4
SYSCLK5
333
(1) Only applies during PLL mode.
7.7.1.2 PLL1 Controller Operating Modes
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is
generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In
bypass mode, CLKIN1 is fed directly to SYSREFCLK.
All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
7.7.1.3 PLL1 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device powerup. The PLL should not be operated until this stabilization time has
expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
PLL1 reset time value, see Table 7-14.
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The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The
PLL1 lock time is given in Table 7-14.
Table 7-14. PLL1 Stabilization, Lock, and Reset Times
MIN
TYP
MAX
UNIT
µs
PLL stabilization time
PLL lock time
150
2000*C(1)
ns
PLL reset time
128*C(1)
ns
(1) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
7.7.2 PLL1 Controller Memory Map
The memory map of the PLL1 controller is shown in Table 7-15. Note that only registers documented here
are accessible on the TMS320C6455. Other addresses in the PLL1 controller memory map should not be
modified.
Table 7-15. PLL1 Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE
029A 0000 - 029A 00E3
029A 00E4
ACRONYM
REGISTER NAME
-
Reserved
RSTYPE
Reset Type Status Register (Reset Controller)
029A 00E8 - 029A 00FF
029A 0100
-
Reserved
PLLCTL
PLL Control Register
Reserved
029A 0104
-
029A 0108
-
Reserved
029A 010C
-
Reserved
029A 0110
PLLM
PLL Multiplier Control Register
PLL Pre-Divider Control Register
Reserved
029A 0114
PREDIV
029A 0118
-
029A 011C
-
Reserved
029A 0120
-
Reserved
029A 0124
-
Reserved
029A 0128
-
Reserved
029A 012C
-
Reserved
029A 0130
-
Reserved
029A 0134
-
Reserved
029A 0138
PLLCMD
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
029A 013C
PLLSTAT
029A 0140
ALNCTL
029A 0144
DCHANGE
029A 0148
-
029A 014C
-
Reserved
029A 0150
SYSTAT
SYSCLK Status Register
Reserved
029A 0154
-
029A 0158
-
Reserved
029A 015C
-
Reserved
029A 0160
PLLDIV4
PLLDIV5
-
PLL Controller Divider 4 Register
PLL Controller Divider 5 Register
Reserved
029A 0164
029A 0168 - 029B FFFF
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7.7.3 PLL1 Controller Register Descriptions
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUE56).
NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C645x DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUE56) are supported on the TMS320C6455.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
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7.7.3.1 PLL1 Control Register
The PLL control register (PLLCTL) is shown in Figure 7-13 and described in Table 7-16.
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
PLL
PWRDN
Reserved
R-0
Rsvd
R/W-0
Rsvd
R-1
Reserved
R/W-0
PLLRST
R/W-1
Rsvd
R-0
PLLEN
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-13. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]
Table 7-16. PLL1 Control Register (PLLCTL) Field Descriptions
Bit
31:8
7
Field
Value Description
Reserved
Reserved
Reserved
Reserved
PLLRST
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
6
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
5:4
3
Reserved. Writes to this register must keep this bit as 0.
PLL reset bit
0
1
PLL reset is released
PLL reset is asserted
2
1
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLLPWRDN
PLL power-down mode select bit
0
1
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
0
PLLEN
0
1
Bypass mode. Divider PREDIV and PLL are bypassed. All the system clocks (SYSCLKn) are
divided down directly from input reference clock.
PLL mode. Divider PREDIV and PLL are not bypassed. PLL output path is enabled. All the system
clocks (SYSCLKn) are divided down from PLL output.
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7.7.3.2 PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in Figure 7-14 and described in Table 7-17. The PLLM
register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits
(RATIO) in the PLL controller pre-divider register (PREDIV).
31
15
16
Reserved
R-0
5
4
0
Reserved
R-0
PLLM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-14. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Table 7-17. PLL Multiplier Control Register (PLLM) Field Descriptions
Bit
31:5
4:0
Field
Value Description
Reserved
PLLM
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL multiplier bits. Defines the frequency multiplier of the input reference clock in conjunction with
the PLL divider ratio bits (RATIO) in PREDIV.
0h
Eh
x1 multiplier rate
x15 multiplier rate
x20 multiplier rate
x25 multiplier rate
x30 multiplier rate
x32 multiplier rate
13h
18h
1Dh
1Fh
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7.7.3.3 PLL Pre-Divider Control Register
The PLL pre-divider register (PREDIV) is shown in Figure 7-15 and described in Table 7-18.
31
16
Reserved
R-0
15
14
5
4
0
PREDEN
R/W-1
Reserved
R-0
RATIO
R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-15. PLL Pre-Divider Register (PREDIV) [Hex Address: 029A 0114]
Table 7-18. PLL Pre-Divider Register (PREDIV) Field Descriptions
Bit
Field
Value Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Pre-divider enable bit.
15
PREDEN
0
1
0
Pre-divider is disabled. No clock output.
Pre-divider is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-1Fh Divider ratio bits.
0
÷1. Divide frequency by 1.
÷2. Divide frequency by 2.
1h
2h-1Fh Reserved, do not use.
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7.7.3.4 PLL Controller Divider Registers
The PLL controller divider register 4 and 5 (PLLDIV4 and PLLDIV5) are shown in Figure 7-16 and
Figure 7-17, respectively, and described in Table 7-19.
31
16
Reserved
R-0
15
14
5
4
0
D4EN
Reserved
R-0
RATIO
R/W-7
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-16. PLL Controller Divider Register 4 (PLLDIV4) [Hex Address: 029A 0160]
31
16
0
Reserved
R-0
15
14
5
4
D5EN
Reserved
R-0
RATIO
R/W-2
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-17. PLL Controller Divider Register 5 (PLLDIV5) [Hex Address: 029A 0164]
Table 7-19. PLL Controller Divider Registers (PLLDIV4 and PLLDIV5) Field Descriptions
Bit
Field
Value Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider Dn enable bit.
15
DnEN
0
1
0
Divider n is disabled. No clock output.
Divider n is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-1Fh Divider ratio bits.
0
÷1. Divide frequency by 1.
1h
2h
3h
÷2. Divide frequency by 2.
÷3. Divide frequency by 3.
÷4. Divide frequency by 4.
4h-1Fh ÷5 to ÷32. Divide frequency by 4 to divide frequency by 32.
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7.7.3.5 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in Figure 7-18 and described in Table 7-20.
31
15
16
Reserved
R-0
2
1
0
Reserved
R-0
Rsvd
R/W-0
GOSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-18. PLL Controller Command Register (PLLCMD) [Hex Address: 029A 0138]
Table 7-20. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31:2
1
Field
Value Description
Reserved
Reserved
GOSET
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0
1
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
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7.7.3.6 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-19 and described in Table 7-21.
31
15
16
Reserved
R-0
1
0
Reserved
R-0
GOSTAT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-19. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
Table 7-21. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
GOSTAT
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
0
1
GO operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
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7.7.3.7 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-20 and described in
Table 7-22.
31
15
16
Reserved
R-0
5
4
3
2
0
Reserved
R-0
ALN5 ALN4
Reserved
R-1
R-1 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-20. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]
Table 7-22. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31:5
4:3
Field
Value Description
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
ALNn
SYSCLKn alignment. Do not change the default values of these fields.
0
1
0
Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set to 1,
SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn.
2:0
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
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7.7.3.8 PLLDIV Ratio Change Status Register
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the
PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in
Figure 7-21 and described in Table 7-23.
31
15
16
Reserved
R-0
5
4
3
2
0
Reserved
R-0
SYS5 SYS4
Reserved
R-0
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-21. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]
Table 7-23. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31:5
4
Field
Value Description
Reserved
SYS5
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Identifies when the SYSCLK4 divide ratio has been modified.
0
1
SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected.
SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.
Identifies when the SYSCLK4 divide ratio has been modified.
3
SYS4
0
1
0
SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected.
SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
2:0
Reserved
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7.7.3.9 SYSCLK Status Register
The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is
shown in Figure 7-22 and described in Table 7-24.
31
16
Reserved
R-0
15
8
Reserved
R-0
7
5
4
3
2
1
0
Reserved
R-0
SYS5ON
SYS4ON
SYS3ON
SYS2ON
Reserved
R-1
R-1
R-1
R-1
R-1
LEGEND: R = Read only; -n = value after reset
Figure 7-22. SYSCLK Status Register (SYSTAT) [Hex Address: 029A 0150]
Table 7-24. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
31:4
4:1
Field
Value Description
Reserved
SYSnON
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLKn on status.
0
1
1
SYSCLKn is gated.
SYSCLKn is on.
0
Reserved
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
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7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing
Table 7-25. Timing Requirements for CLKIN1 Devices(1)(2)(3) (see Figure 7-23)
-720
-850
-1000
NO.
PLL MODES
UNIT
x1 (Bypass), x15,
x20, x25, x30, x32
MIN
15
MAX
1
2
3
4
5
tc(CLKIN1)
tw(CLKIN1H)
tw(CLKIN1L)
tt(CLKIN1)
Cycle time, CLKIN1(4)
30.3
ns
ns
ns
ns
ps
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
0.4C
0.4C
1.2
tJ(CLKIN1)
Period jitter (peak-to-peak), CLKIN1
100
(1) The reference points for the rise and fall transitions are measured at 3.3 V VIL MAX and VIH MIN.
(2) For more details on the PLL multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32), see Section 7.7.1.2, PLL1 Controller Operating
Modes.
(3) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
(4) The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for tc(CLKIN1). For more
detailed information on these limitations, see Section 7.7.1.1, Internal Clocks and Maximum Operating Frequencies.
1
5
4
2
CLKIN1
3
4
Figure 7-23. CLKIN1 Timing
Table 7-26. Switching Characteristics Over Recommended Operating Conditions for SYSCLK4
[CPU/8 - CPU/12](1)(2) (see Figure 7-24)
-720
-850
NO.
PARAMETER
-1000
UNIT
MIN
MAX
6P + 0.7
6P + 0.7
1
2
3
4
tw(CKO3H)
tw(CKO3L)
tt(CKO3)
Pulse duration, SYSCLK4 high
Pulse duration, SYSCLK4 low
Transition time, SYSCLK4
4P – 0.7
4P – 0.7
ns
ns
ns
(1) The reference points for the rise and fall transitions are measured at 3.3 V VOL MAX and VOH MIN.
(2) P = 1/CPU clock frequency in nanoseconds (ns)
3
SYSCLK4
2
3
Figure 7-24. SYSCLK4 Timing
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7.8 PLL2 and PLL2 Controller
The secondary PLL controller generates interface clocks for the Ethernet media access controller (EMAC)
and the DDR2 memory controller.
As shown in Figure 7-25, the PLL2 controller features a PLL multiplier controller and one divider (D1). The
PLL multiplier is fixed to a x20 multiplier rate and the divider D1 can be programmed to a ÷2 or ÷5 mode.
PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external PLL filter circuit must
be added to PLLV2 as shown in Figure 7-25. The 1.8-V supply for the EMI filter must be from the same
1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter manufacturer Murata,
part number NFM18CC222R1C3.
All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+
DSP device as possible. For the best performance, TI requires that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For
the input clock timing requirements, see the PLL2 Controller Input and Output Clock Electrical Data/Timing
section.
CAUTION
The PLL controller module as described in the TMS320C645x DSP
Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature
number SPRUE56) includes a superset of features, some of which are not supported
on the C6455 DSP. The following sections describe the features that are supported; it
should be assumed that any feature not included in these sections is not supported
by the C6455 DSP.
TMS320C6455 DSP
SYSCLK3 (From PLL1 Controller)
PLLV2
+1.8 V
SYSCLK2 (From PLL1 Controller)
0.1 pF
C162
560 pF
C161
DDR2
Memory
Controller
EMI Filter
PLLREF
PLLOUT
/2
PLL2
(B)(C)
CLKIN2
DIVIDER D1
SYSCLK1
PLLM
x20
EMAC
1
0
SYSREFCLK
(A)
/x
1
PLL2 Controller
A. /x must be programmed to /2 for GMII (default) and to /5 for RGMII or RMII
B. If EMAC is enabled, CLKIN2 frequency must be 25 MHz.
C. CLKIN2 is a 3.3-V signal.
Figure 7-25. PLL2 Block Diagram
7.8.1 PLL2 Controller Device-Specific Information
7.8.1.1 Internal Clocks and Maximum Operating Frequencies
As shown in Figure 7-25, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2
memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and
DDR2CLKOUT. Note that, internally, the data bus interface of the DDR2 memory controller is clocked by
SYSCLK2 of the PLL1 controller.
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The PLLOUT/2 clock is also fed back into the PLL2 controller where it becomes SYSREFCLK. Divider D1
of the PLL2 controller generates SYSCLK1 for the Ethernet media access controller (EMAC). The EMAC
uses SYSCLK1 to generate the necessary clock for each of its interfaces. Divider D1 should be
programmed to ÷2 mode [default] when using the Gigabit Media Independent Interface (GMII) mode and
to ÷5 mode when using the Reduce Gigabit Media Independent Interface (RGMII) or the Reduced Media
Independent Interface (RMII) mode. Divider D1 is software programmable and, if necessary, must be
programmed after device reset to ÷5 when the RGMII or RMII mode of the EMAC is used. Note that,
internally, the data bus interface of the EMAC is clocked by SYSCLK3 of the PLL2 controller.
Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, and SYSCLK1.
The clock generator must not be configured to exceed any of these constraints. See Table 7-27 for the
PLL clocks input and output frequency ranges. Also, when the EMAC is enabled, the frequency of CLKIN2
must be 25 MHz.
Table 7-27. PLL2 Clock Frequency Ranges
CLOCK SIGNAL
MIN
12.5
250
50
MAX
25
UNIT
MHz
MHz
MHz
PLLREF (PLLEN = 1)
PLLOUT
SYSCLK1(1)
500
125
(1) SYSCLK1 restriction applies only when the EMAC is enabled and the RGMII, RMII, or GMII modes are used. SYSCLK1 must be
programmed to 125 MHz when the GMII mode used and to 50 MHz when the RGMII or RMII mode is used.
7.8.1.2 PLL2 Controller Operating Modes
Unlike the PLL1 controller which can operate in bypass and a PLL mode, the PLL2 controller only
operates in PLL mode. In this mode, SYSREFCLK is generated outside the PLL2 controller by dividing the
output of PLL2 by two.
The PLL2 controller is affected by power-on reset, warm reset, and max reset. During these resets the
PLL2 controller registers get reset to their default values. The internal clocks of the PLL2 controller are
also affected as described in Section 7.6, Reset Controller, of this document.
PLL2 is only unlocked during the power-up sequence (see the Reset Controller section) and is locked by
the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
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7.8.2 PLL2 Controller Memory Map
The memory map of the PLL2 controller is shown in Table 7-28. Note that only registers documented here
are accessible on the TMS320C6455. Other addresses in the PLL2 controller memory map should not be
modified.
Table 7-28. PLL2 Controller Registers
HEX ADDRESS RANGE
029C 0000 - 029C 0114
029C 0118
ACRONYM
DESCRIPTION
-
Reserved
PLLDIV1
PLL Controller Divider 1 Register
Reserved
029C 011C - 029C 0134
029C 0138
-
PLLCMD
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
029C 013C
PLLSTAT
029C 0140
ALNCTL
029C 0144
DCHANGE
029C 0148
-
029C 014C
-
Reserved
029C 0150
SYSTAT
SYSCLK Status Register
Reserved
029C 0154 - 029C 0190
029C 0194 - 029C 01FF
029C 0200 - 029C FFFF
-
-
-
Reserved
Reserved
7.8.3 PLL2 Controller Register Descriptions
This section provides a description of the PLL2 controller registers. For details on the operation of the PLL
controller module, see the TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUE56).
NOTE: The PLL2 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C645x DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUE56) are supported on the TMS320C6455.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
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7.8.3.1 PLL Controller Divider 1 Register
The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-26 and described in Table 7-29.
31
16
0
Reserved
R-0
15
14
5
4
D1EN
Reserved
R-0
RATIO
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-26. PLL Controller Divider 1 Register (PLLDIV1) [Hex Address: 029C 0118]
Table 7-29. PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Bit
Field
Value Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider D1 enable bit.
15
D1EN
0
1
0
Divider D1 is disabled. No clock output.
Divider D1 is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0-1Fh Divider ratio bits.
1h
4h
÷2. Divide frequency by 2.
÷5. Divide frequency by 5.
Others Reserved
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7.8.3.2 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in Figure 7-27 and described in Table 7-30.
31
15
16
Reserved
R-0
2
1
0
Reserved
R-0
Rsvd
R/W-0
GOSET
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-27. PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138]
Table 7-30. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31:2
1
Field
Value Description
Reserved
Reserved
GOSET
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0
1
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
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7.8.3.3 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-28 and described in Table 7-31.
31
16
Reserved
R-0
15
1
0
Reserved
R-0
GOSTAT
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-28. PLL Controller Status Register (PLLSTAT) [Hex Address: 029C 013C]
Table 7-31. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
GOSTAT
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
0
1
Go operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
7.8.3.4 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-20 and described in
Table 7-22.
31
16
Reserved
R-0
15
1
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
ALN1
R/W-1
Figure 7-29. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029C 0140]
Table 7-32. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
ALN1
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK1 alignment. Do not change the default values of these fields.
0
1
Do not align SYSCLK1 during GO operation. If SYS1 in DCHANGE is set to 1, SYSCLK1 switches
to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK1 when the GOSET bit in PLLCMD is set. The SYSCLK1 ratio is set to the ratio
programmed in the RATIO bit in PLLDIV1.
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7.8.3.5 PLLDIV Ratio Change Status Register
Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the
DCHANGE status register. During the GO operation, the PLL controller will only change the divide ratio
SYSCLK1 if SYS1 in DCHANGE is 1. The PLLDIV divider ratio change status register is shown in
Figure 7-30 and described in Table 7-33.
31
15
16
Reserved
R-0
1
0
Reserved
R-0
SYS1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-30. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029C 0144]
Table 7-33. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
SYS1
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK1 divide ratio has been modified. SYSCLK1 ratio will be modified during GO operation.
SYSCLK1 ratio has not been modified. When GOSET is set, SYSCLK1 will not be affected.
SYSCLK1 ratio has been modified. When GOSET is set, SYSCLK1 will change to the new ratio.
0
1
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7.8.3.6 SYSCLK Status Register
The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is
shown in Figure 7-31 and described in Table 7-34.
31
15
16
Reserved
R-0
1
0
Reserved
R-0
SYS1ON
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-31. SYSCLK Status Register [Hex Address: 029C 0150]
Table 7-34. SYSCLK Status Register Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
SYS1ON
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK1 on status.
SYSCLK1 is gated.
SYSCLK1 is on.
0
1
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7.8.4 PLL2 Controller Input Clock Electrical Data/Timing
Table 7-35. Timing Requirements for CLKIN2(1)(2)(3) (see Figure 7-32)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
5
tc(CLKIN2)
tw(CLKIN2H)
tw(CLKIN2L)
tt(CLKIN2)
Cycle time, CLKIN2
37.5
0.4C
0.4C
80
ns
ns
ns
ns
ps
Pulse duration, CLKIN2 high
Pulse duration, CLKIN2 low
Transition time, CLKIN2
1.2
tJ(CLKIN2)
Period jitter (peak-to-peak), CLKIN2
100
(1) The reference points for the rise and fall transitions are measured at 3.3 V VIL MAX and VIH MIN.
(2) C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
(3) If EMAC is enabled, CLKIN2 cycle time must be 40 ns (25 MHz).
1
5
4
2
CLKIN2
3
4
Figure 7-32. CLKIN2 Timing
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7.9 DDR2 Memory Controller
The 32-bit DDR2 Memory Controller bus of the C6455 is used to interface to JESD79D-2A
standard-compliant DDR2 SDRAM devices. The DDR2 bus is designed to sustain a throughput of up to
2.0 GBps at a 500-MHz data rate (250-MHz clock rate) as long as data requests are pending in the DDR2
Memory Controller.
The DDR2 external bus only interfaces to DDR2 SDRAM devices; it does not share the bus with any other
types of peripherals. The decoupling of DDR2 memories from other devices both simplifies board design
and provides I/O concurrency from a second external memory interface, EMIFA.
7.9.1 DDR2 Memory Controller Device-Specific Information
The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces
such as EMIF, HPI, and McBSP. For these other interfaces the device timing was specified in terms of
data manual specifications and I/O buffer information specification (IBIS) models.
For the C6455 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the
printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has
performed the simulation and system characterization to ensure all DDR2 interface timings in this solution
are met. The complete DDR2 system solution is documented in the Implementing DDR2 PCB Layout on
the TMS320C6455 Application Report (literature number SPRAAA7).
TI only supports designs that follow the board design guidelines outlined in the SPRAAA7
Application Report.
The DDR2 Memory Controller pins must be enabled by setting the DDR2_EN configuration pin (ABA0)
high during device reset. See the Device Configuration at Device Reset section for more details.
The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2
memory device(s) must be connected to ground.
The DDR2 memory controller on the C6455 device supports the following memory topologies:
•
•
A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.
A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.
A race condition may exist when certain masters write data to the DDR2 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for indication
that the write completes, when master B attempts to read the software message, then the master B read
may bypass the master A write and, thus, master B may read stale data and, therefore, receive an
incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware guarantee of write-read ordering, it may be necessary to guarantee data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
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7.9.2 DDR2 Memory Controller Peripheral Register Description(s)
Table 7-36. DDR2 Memory Controller Registers
HEX ADDRESS RANGE
7800 0000
ACRONYM
REGISTER NAME
DDR2 Memory Controller Module and Revision Register
DDR2 Memory Controller Status Register
DDR2 Memory Controller SDRAM Configuration Register
DDR2 Memory Controller SDRAM Refresh Control Register
DDR2 Memory Controller SDRAM Timing 1 Register
DDR2 Memory Controller SDRAM Timing 2 Register
Reserved
MIDR
7800 0004
DMCSTAT
7800 0008
SDCFG
7800 000C
SDRFC
7800 0010
SDTIM1
7800 0014
SDTIM2
7800 0018
-
7800 0020
BPRIO
DDR2 Memory Controller Burst Priority Register
Reserved
7800 0024 - 7800 004C
7800 0050 - 7800 0078
7800 007C - 7800 00BC
7800 00C0 - 7800 00E0
7800 00E4
-
-
Reserved
-
Reserved
-
Reserved
DMCCTL
DDR2 Memory Controller Control Register
Reserved
7800 00E8 - 7800 00FC
7800 0100 - 7FFF FFFF
-
-
Reserved
7.9.3 DDR2 Memory Controller Electrical Data/Timing
The Implementing DDR2 PCB Layout on a TMS320C6455 Hardware Design Application Report (literature
number SPRAAA9) specifies a complete DDR2 interface solution for the C6455 as well as a list of
compatible DDR2 devices. TI has performed the simulation and system characterization to ensure all
DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is supplied
here for this interface.
TI only supports designs that follow the board design guidelines outlined in the SPRAAA9
Application Report.
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7.10 External Memory Interface A (EMIFA)
The EMIFA can interface to a variety of external devices or ASICs, including:
•
•
•
•
Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM)
ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM
Synchronous FIFOs
Asynchronous memory, including SRAM, ROM, and Flash
7.10.1 EMIFA Device-Specific Information
Timing analysis must be done to verify all AC timings are met. TI recommends utilizing I/O buffer
information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS
Models for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines
(see the Terminal Functions table for the EMIF output signals).
A race condition may exist when certain masters write data to the EMIFA. For example, if master A
passes a software message via a buffer in external memory and does not wait for indication that the write
completes, when master B attempts to read the software message, then the master B read may bypass
the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware guarantee of write-read ordering, it may be necessary to guarantee data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the EMIFA module ID and revision register.
3. Perform a dummy read to the EMIFA module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
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7.10.2 EMIFA Peripheral Register Description(s)
Table 7-37. EMIFA Registers
HEX ADDRESS RANGE
7000 0000
ACRONYM
REGISTER NAME
MIDR
Module ID and Revision Register
Status Register
7000 0004
STAT
7000 0008
-
Reserved
7000 000C - 7000 001C
7000 0020
-
Reserved
BPRIO
Bust Priority Register
7000 0024 - 7000 004C
7000 0050 - 7000 007C
7000 0080
-
Reserved
-
CE2CFG
CE3CFG
CE4CFG
CE5CFG
-
Reserved
EMIFA CE2 Configuration Register
EMIFA CE3 Configuration Register
EMIFA CE4 Configuration Register
EMIFA CE5 Configuration Register
Reserved
7000 0084
7000 0088
7000 008C
7000 0090 - 7000 009C
7000 00A0
AWCC
-
EMIFA Async Wait Cycle Configuration Register
Reserved
7000 00A4 - 7000 00BC
7000 00C0
INTRAW
INTMSK
INTMSKSET
INTMSKCLR
-
EMIFA Interrupt RAW Register
EMIFA Interrupt Masked Register
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
Reserved
7000 00C4
7000 00C8
7000 00CC
7000 00D0 - 7000 00DC
7000 00E0 - 77FF FFFF
-
Reserved
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7.10.3 EMIFA Electrical Data/Timing
Table 7-38. Timing Requirements for AECLKIN for EMIFA(1)(2)(3) (see Figure 7-33)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
5
tc(EKI)
tw(EKIH)
tw(EKIL)
tt(EKI)
Cycle time, AECLKIN
6(4)
2.7
2.7
16P
ns
ns
ns
ns
ns
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
Period Jitter, AECLKIN
2
tJ(EKI)
0.02E(5)
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(3) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(4) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the -1000
devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
(5) This timing only applies when AECLKIN is used for EMIFA.
1
5
4
2
AECLKIN
3
4
Figure 7-33. AECLKIN Timing for EMIFA
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Table 7-39. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module(1)(2)(3) (see Figure 7-34)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
6
tc(EKO)
Cycle time, AECLKOUT
E – 0.7
EH – 0.7
EL – 0.7
E + 0.7
ns
ns
ns
ns
ns
ns
tw(EKOH)
tw(EKOL)
Pulse duration, AECLKOUT high
EH + 0.7
Pulse duration, AECLKOUT low
EL + 0.7
tt(EKO)
Transition time, AECLKOUT
1
8
8
td(EKIH-EKOH)
td(EKIL-EKOL)
Delay time, AECLKIN high to AECLKOUT high
Delay time, AECLKIN low to AECLKOUT low
1
1
(1) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.
(2) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN
5
2
3
3
1
4
AECLKOUT1
Figure 7-34. AECLKOUT Timing for the EMIFA Module
7.10.3.1 Asynchronous Memory Timing
Table 7-40. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)(2)(3)
(see Figure 7-35 and Figure 7-36)
-720
-850
-1000
NO.
UNIT
MIN
MAX
3
4
5
6
7
tsu(EDV-AOEH)
th(AOEH-EDV)
tsu(ARDY-EKOH)
th(EKOH-ARDY)
tw(ARDY)
Setup time, AEDx valid before AAOE high
Hold time, AEDx valid after AAOE high
6.5
ns
ns
ns
ns
ns
3
Setup time, AARDY valid before AECLKOUT low
Hold time, AARDY valid after AECLKOUT low
Pulse width, AARDY assertion and deassertion
1
2
2E + 5
Delay time, from AARDY sampled deasserted on AECLKOUT falling to
beginning of programmed hold period
8
9
td(ARDY-HOLD)
tsu(ARDY-HOLD)
4E
ns
ns
Setup time, before end of programmed strobe period by which AARDY
should be asserted in order to insert extended strobe wait states.
2E
(1) E = AECLKOUT period in ns for EMIFA
(2) To ensure data setup time, simply program the strobe width wide enough.
(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to ensure setup and hold time is met.
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Table 7-41. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1)(2)(3) (see Figure 7-35 and Figure 7-36)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
7
1
tosu(SELV-AOEL)
toh(AOEH-SELIV)
td(EKOH-AOEV)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
td(EKOH-AWEV)
Output setup time, select signals valid to AAOE low
Output hold time, AAOE high to select signals invalid
Delay time, AECLKOUT high to AAOE valid
RS * E – 1.5
RS * E – 1.9
1
ns
ns
ns
ns
ns
ns
2
10
11
12
13
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUT high to AAWE valid
WS * E – 1.7
WH * E – 1.8
1.3
7.1
(1) E = AECLKOUT period in ns for EMIFA
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA chip select configuration registers.
(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].
Strobe = 4
Setup = 1
Hold = 1
2
AECLKOUT
ACEx
1
1
2
2
Byte Enables
Address
ABE[7:0]
1
AEA[19:0]/
ABA[1:0]
3
4
Read Data
AED[63:0]
10
10
(A)
AAOE/ASOE
(A)
AAWE/ASWE
AR/W
(B)
DEASSERTED
AARDY
A
B
AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous
memory accesses.
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 7-35. Asynchronous Memory Read Timing for EMIFA
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Strobe = 4
Hold = 1
Setup = 1
AECLKOUT
ACEx
12
12
12
11
11
Byte Enables
Address
ABE[7:0]
11
AEA[19:0]/
ABA[1:0]
11
12
Write Data
AED[63:0]
(A)
AAOE/ASOE
13
13
(A)
AAWE/ASWE
11
12
AR/W
(B)
AARDY
A
B
AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory
accesses.
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 7-36. Asynchronous Memory Write Timing for EMIFA
Strobe
Strobe
Hold = 2
Setup = 2
Extended Strobe
9
8
AECLKOUT
6
5
7
7
(A)
ASSERTED
DEASSERTED
AARDY
A
Polarity of the AARDY signal is programmable through the “wp” field of the EMIFA Async Wait Cycle Configuration Register
(ASYNCWAITCFG).
Figure 7-37. AARDY Timing
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7.10.3.2 Programmable Synchronous Interface Timing
Table 7-42. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7-38)
-720
-850
-1000
NO.
UNIT
MIN
MAX
6
7
tsu(EDV-EKOH)
th(EKOH-EDV)
Setup time, read AEDx valid before AECLKOUT high
Hold time, read AEDx valid after AECLKOUT high
2
ns
ns
1.5
Table 7-43. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module(1) (see Figure 7-38–Figure 7-40)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
4.9
1
2
td(EKOH-CEV)
td(EKOH-BEV)
td(EKOH-BEIV)
td(EKOH-EAV)
td(EKOH-EAIV)
td(EKOH-ADSV)
td(EKOH-OEV)
td(EKOH-EDV)
td(EKOH-EDIV)
td(EKOH-WEV)
Delay time, AECLKOUT high to ACEx valid
Delay time, AECLKOUT high to ABEx valid
Delay time, AECLKOUT high to ABEx invalid
Delay time, AECLKOUT high to AEAx valid
Delay time, AECLKOUT high to AEAx invalid
Delay time, AECLKOUT high to ASADS/ASRE valid
Delay time, AECLKOUT high to ASOE valid
Delay time, AECLKOUT high to AEDx valid
Delay time, AECLKOUT high to AEDx invalid
Delay time, AECLKOUT high to ASWE valid
1.3
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.9
3
4
4.9
5
1.3
1.3
1.3
8
4.9
4.9
4.9
9
10
11
12
1.3
1.3
4.9
(1) The following parameters are programmable via the EMIF CE Space Secondary Control register (CESECx):
•
•
•
Read latency (r_ltncy): 0-, 1-, 2-, or 3-cycle read latency
Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has
been issued (cs_ext = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (cs_ext = 1).
•
Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (r_enable = 1).
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READ latency = 2
AECLKOUT
1
1
3
5
ACEx
2
BE1
ABE[7:0]
AEA[19:0]/ABA[1:0]
AED[63:0]
BE2
BE3
BE4
4
EA1
EA2
EA3
EA4
7
6
Q1
Q2
Q3
Q4
8
9
8
(B)
ASADS/ASRE
9
(B)
AAOE/ASOE
(B)
AAWE/ASWE
A
B
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
−Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
−Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
−ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
−Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
−In this figure r_ltncy = 2, cs_ext = 0, and r_enable = 0.
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 7-38. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)(A)
AECLKOUT
1
2
1
3
ACEx
ABE[7:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
AEA[19:0]/ABA[1:0]
AED[63:0]
EA1
10
Q1
10
11
8
8
(B)
ASADS/ASRE
(B)
AAOE/ASOE
12
12
(B)
AAWE/ASWE
A
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
− Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
− ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
− Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
− In this figure r_ltncy = 2, cs_ext = 0, and r_enable = 0.
B
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 7-39. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)(A)
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Write
Latency =
(B)
1
AECLKOUTx
1
1
ACEx
3
2
ABE[7:0]
BE1
BE2
BE3
EA3
Q2
BE4
5
4
AEA[19:0]/ABA[1:0]
AED[63:0]
EA1
10
EA2
10
EA4
11
Q1
Q3
Q4
8
8
(B)
ASADS/ASRE
(B)
AAOE/ASOE
12
12
(B)
AAWE/ASWE
A
B
The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):
− Read latency (r_ltncy): 1-, 2-, or 3-cycle read latency
− Write latency (w_ltncy): 0-, 1-, 2-, or 3-cycle read latency
− ACEx assertion length (cs_ext): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been
issued (cs_ext = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (cs_ext = 1).
− Function of ASADS/ASRE (r_enable): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect
cycles (r_enable = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (r_enable = 1).
− In this figure r_ltncy = TBD, cs_ext = TBD, and r_enable = TBD.
AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 7-40. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) (A)
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7.10.4 HOLD/HOLDA Timing
Table 7-44. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module(1) (see Figure 7-41)
-720
-850
-1000
NO.
UNIT
MIN
MAX
3
th(HOLDAL-HOLDL)
Hold time, HOLD low after HOLDA low
E
ns
(1) E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
Table 7-45. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module(1)(2) (see Figure 7-41)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
(3)
1
2
4
5
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
2E
0
ns
ns
ns
ns
2E
7E
2E
2E
0
(1) E = the EMIF input clock (ECLKIN) period in ns for EMIFA.
(2) EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE, and AAWE/ASWE.
(3) All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the
minimum delay time can be achieved.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
(A)
1
4
EMIF Bus
DSP
DSP
AECLKOUT
A. EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE,
and AAWE/ASWE.
Figure 7-41. HOLD/HOLDA Timing for EMIFA
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7.10.5 BUSREQ Timing
Table 7-46. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 7-42)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
1
td(AEKOH-ABUSRV)
Delay time, AECLKOUT high to ABUSREQ valid
1
5.5
ns
AECLKOUTx
1
1
ABUSREQ
Figure 7-42. BUSREQ Timing for EMIFA
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7.11 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DSP through the I2C module.
7.11.1 I2C Device-Specific Information
The C6455 device includes an I2C peripheral module (I2C). NOTE: when using the I2C module, ensure
there are external pullup resistors on the SDA and SCL pins.
The I2C modules on the C6455 may be used by the DSP to control local peripherals ICs (DACs, ADCs,
etc.) or may be used to communicate with other controllers in a system or to implement a user interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to remove noise 50 ns or less
7- and 10-Bit Device Addressing Modes
Multi-Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
Figure 7-43 is a block diagram of the I2C module.
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I2C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
I2CPSC
Control
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
Bit Clock
Own
Generator
Address
SCL
Noise
Filter
I2C Clock
Slave
Address
I2CCLKH
I2CCLKL
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
Filter
I2C Data
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
Interrupt
Vector
Receive
Shift
I2CRSR
I2CIVR
Shading denotes control/status registers.
Figure 7-43. I2C Module Block Diagram
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7.11.2 I2C Peripheral Register Description(s)
Table 7-47. I2C Registers
HEX ADDRESS RANGE
02B0 4000
ACRONYM
REGISTER NAME
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
ICPID1
ICPID2
-
I2C own address register
02B0 4004
I2C interrupt mask/status register
I2C interrupt status register
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
02B0 4008
02B0 400C
02B0 4010
02B0 4014
02B0 4018
I2C data receive register
02B0 401C
I2C slave address register
I2C data transmit register
I2C mode register
02B0 4020
02B0 4024
02B0 4028
I2C interrupt vector register
I2C extended mode register
I2C prescaler register
02B0 402C
02B0 4030
02B0 4034
I2C peripheral identification register 1 [Value: 0x0000 0105]
I2C peripheral identification register 2 [Value: 0x0000 0005]
Reserved
02B0 4038
02B0 403C - 02B0 405C
02B0 4060 - 02B3 407F
02B0 4080 - 02B3 FFFF
-
Reserved
-
Reserved
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7.11.3 I2C Electrical Data/Timing
7.11.3.1 Inter-Integrated Circuits (I2C) Timing
Table 7-48. Timing Requirements for I2C Timings(1) (see Figure 7-44)
-720
-850
-1000
NO.
UNIT
STANDARD MODE
FAST MODE
MIN
MIN
MAX
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
3
th(SCLL-SDAL)
0.6
µs
4
5
6
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SDLH)
Setup time, SDA valid before SCL high
250
Hold time, SDA valid after SCL low (For I2C
bus™ devices)
7
th(SDA-SDLL)
0(3)
0(3)
0.9(4)
µs
Pulse duration, SDA high between STOP and
8
tw(SDAH)
START
4.7
1.3
µs
conditions
(5)
9
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
(5)
(5)
(5)
10
11
12
Setup time, SCL high before SDA high (for
STOP condition)
13
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
µs
14
15
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50
ns
(5)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 7-44. I2C Receive Timings
Table 7-49. Switching Characteristics for I2C Timings(1) (see Figure 7-45)
-720
-850
-1000
NO.
PARAMETER
UNIT
STANDARD MODE
FAST MODE
MIN
MIN
MAX
MAX
16
17
tc(SCL)
td(SCLH-SDAL)
td(SDAL-SCLL)
Cycle time, SCL
10
2.5
µs
µs
Delay time, SCL high to SDA low (for a
repeated START condition)
4.7
4
0.6
Delay time, SDA low to SCL low (for a START
and a repeated START condition)
18
0.6
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SDLH)
Delay time, SDA valid to SCL high
250
100
Valid time, SDA valid after SCL low (For I2C
bus™ devices)
22
23
tv(SDLL-SDAV)
tw(SDAH)
0
0
0.9
µs
µs
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
(1)
24
25
26
27
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
(1)
(1)
(1)
Delay time, SCL high to SDA high (for STOP
condition)
28
29
td(SCLH-SDAH)
Cp
4
0.6
µs
Capacitance for each I2C pin
10
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 7-45. I2C Transmit Timings
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7.12 Host-Port Interface (HPI) Peripheral
7.12.1 HPI Device-Specific Information
The C6455 device includes a user-configurable 16-bit or 32-bit Host-port interface (HPI16/HPI32). The
AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
C6455.
An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
7.12.2 HPI Peripheral Register Description(s)
Table 7-50. HPI Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0288 0000
-
Reserved
PWREMU_MGMT has both
Host/CPU read/write access
0288 0004
PWREMU_MGMT
HPI power and emulation management register
0288 0008 - 0288 0024
0288 0028
-
-
-
Reserved
Reserved
Reserved
0288 002C
HPIC has both Host/CPU
read/write access
0288 0030
0288 0034
0288 0008
HPIC
HPI control register
HPIA
HPI address register
(Write)
(HPIAW)(1)
HPIA has both Host/CPU
read/write access
HPIA
HPI address register
(Read)
(HPIAR)(1)
0288 000C - 028B 007F
0288 0080 - 028B FFFF
-
-
Reserved
Reserved
(1) Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR
independently.
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7.12.3 HPI Electrical Data/Timing
Table 7-51. Timing Requirements for Host-Port Interface Cycles(1)(2) (see Table 7-52 through Figure 7-53)
-720
-850
-1000
NO.
UNIT
MIN
MAX
9
tsu(HASL-HSTBL)
th(HSTBL-HASL)
tsu(SELV-HASL)
th(HASL-SELV)
tw(HSTBL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
Setup time, select signals(3) valid before HAS low
Hold time, select signals(3) valid after HAS low
Pulse duration, HSTROBE low
5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
37
5
5
15
2M
5
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals(3) valid before HSTROBE low
Hold time, select signals(3) valid after HSTROBE low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Setup time, HCS low before HSTROBE low
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
tsu(HCSL-HSTBL)
5
5
0
0
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
38
th(HRDYL-HSTBL)
0
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
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Table 7-52. Switching Characteristics for Host-Port Interface Cycles(1)(2)
(see Table 7-52 through Figure 7-53)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
Case 1. HPIC or HPIA read
5
15
Case 2. HPID read with no
auto-increment(3)
9 * M + 20
Delay time, HSTROBE low to
DSP data valid
Case 3. HPID read with auto-increment
and read FIFO initially empty(3)
1
td(HSTBL-HDV)
ns
9 * M + 20
15
Case 4. HPID read with auto-increment
and data previously prefetched into the
read FIFO
5
2
3
4
5
tdis(HSTBH-HDV)
ten(HSTBL-HD)
td(HSTBL-HRDYH)
td(HSTBH-HRDYH)
Disable time, HD high-impedance from HSTROBE high
Enable time, HD driven from HSTROBE low
Delay time, HSTROBE low to HRDY high
Delay time, HSTROBE high to HRDY high
Case 1. HPID read with no
1
3
4
15
12
12
ns
ns
ns
ns
10 * M + 20
10 * M + 20
auto-increment(3)
Delay time, HSTROBE low to
6
td(HSTBL-HRDYL)
ns
HRDY low
Case 2. HPID read with auto-increment
and read FIFO initially empty(3)
7
td(HDV-HRDYL)
td(DSH-HRDYL)
Delay time, HD valid to HRDY low
0
ns
ns
Case 1. HPIA write(3)
5 * M + 20
5 * M + 20
Delay time, HSTROBE high to
HRDY low
34
Case 2. HPID write with no
auto-increment(3)
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not
empty(3)
35
36
td(HSTBL-HRDYL)
td(HASL-HRDYH)
40 * M + 20
12
ns
ns
Delay time, HAS low to HRDY high
(1) M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
13
16
15
16
15
37
37
14
13
(A)
HSTROBE
3
3
1
1
2
2
HD[15:0]
38
4
7
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-46. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
11
12
11
HR/W
12
11
12
11
HHWIL
10
9
10
9
37
13
13
37
14
(A)
HSTROBE
1
3
1
3
2
2
HD[15:0]
7
38
36
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-47. HPI16 Read Timing (HAS Used)
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
16
13
16
15
37
15
37
13
14
(A)
HSTROBE
18
18
17
17
HD[15:0]
34
38
4
34
5
35
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-48. HPI16 Write Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
12
11
11
HR/W
12
11
12
11
14
HHWIL
9
10
10
9
37
37
13
(A)
HSTROBE
13
18
18
17
17
HD[15:0]
34
35
34
5
36
5
38
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing)and the state of the FIFO, transitions on HRDY may or may not occur.
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-49. HPI16 Write Timing (HAS Used)
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HAS (input)
16
15
HCNTL[1:0] (input)
HR/W (input)
13
(A)
HSTROBE (input)
37
HCS (input)
1
2
3
HD[31:0] (output)
38
7
6
4
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions on HRDY
may or may not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-50. HPI32 Read Timing (HAS Not Used, Tied High)
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10
HAS (input)
12
11
HCNTL[1:0] (input)
HR/W (input)
9
13
(A)
HSTROBE (input)
37
HCS (input)
1
2
3
HD[31:0] (output)
7
38
6
36
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR
HCS.
B. Depending on the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions on
HRDY may or may not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-51. HPI32 Read Timing (HAS Used)
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HAS (input)
16
15
HCNTL[1:0]
(input)
HR/W (input)
13
(A)
HSTROBE
(input)
37
HCS (input)
18
17
HD[31:0] (input)
38
34
35
5
4
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions on HRDY may or may
not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-52. HPI32 Write Timing (HAS Not Used, Tied High)
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10
HAS (input)
12
11
HCNTL[1:0]
(input)
HR/W (input)
9
13
(A)
HSTROBE
(input)
37
HCS (input)
18
17
HD[31:0] (input)
35
34
38
36
5
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write operation (HPID, HPIA, HPIC, HPID) and the state of the FIFO, transitions on HRDY
may or may not occur (see the TBD section for more details).
For more detailed information on the HPI peripheral, see the TBD Reference Guide (literature number TBD).
Figure 7-53. HPI32 Write Timing (HAS Used)
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7.13 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
External shift clock or an internal, programmable frequency shift clock for data transfer
For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel
Buffered Serial Port ( McBSP) Reference Guide (literature number SPRU580, rev. E or later).
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7.13.1 McBSP Device-Specific Information
The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the
Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.
7.13.1.1 McBSP Peripheral Register Description(s)
Table 7-53. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA3
controller can only read
this register; they cannot
write to it.
028C 0000
DRR0
McBSP0 Data Receive Register via Configuration Bus
3000 0000
028C 0004
3000 0010
028C 0008
028C 000C
028C 0010
028C 0014
028C 0018
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
McBSP0 Data Receive Register via EDMA3 Bus
McBSP0 Data Transmit Register via Configuration Bus
McBSP0 Data Transmit Register via EDMA Bus
McBSP0 Serial Port Control Register
McBSP0 Receive Control Register
McBSP0 Transmit Control Register
McBSP0 Sample Rate Generator register
McBSP0 Multichannel Control Register
McBSP0 Enhanced Receive Channel Enable Register
0 Partition A/B
028C 001C
RCERE00
McBSP0 Enhanced Transmit Channel Enable Register
0 Partition A/B
028C 0020
028C 0024
028C 0028
XCERE00
PCR0
McBSP0 Pin Control Register
McBSP0 Enhanced Receive Channel Enable Register
1 Partition C/D
RCERE10
McBSP0 Enhanced Transmit Channel Enable Register
1 Partition C/D
028C 002C
028C 0030
028C 0034
028C 0038
XCERE10
RCERE20
XCERE20
RCERE30
McBSP0 Enhanced Receive Channel Enable Register
2 Partition E/F
McBSP0 Enhanced Transmit Channel Enable Register
2 Partition E/F
McBSP0 Enhanced Receive Channel Enable Register
3 Partition G/H
McBSP0 Enhanced Transmit Channel Enable Register
3 Partition G/H
028C 003C
XCERE30
-
028C 0040 - 028F FFFF
Reserved
Table 7-54. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA
controller can only read
this register; they cannot
write to it.
0290 0000
DRR1
McBSP1 Data Receive Register via Configuration Bus
3400 0000
0290 0004
3400 0010
0290 0008
0290 000C
0290 0010
0290 0014
DRR1
DXR1
McBSP1 Data Receive Register via EDMA bus
McBSP1 Data Transmit Register via configuration bus
McBSP1 Data Transmit Register via EDMA bus
McBSP1 serial port control register
DXR1
SPCR1
RCR1
XCR1
McBSP1 Receive Control Register
McBSP1 Transmit Control Register
SRGR1
McBSP1 sample rate generator register
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Table 7-54. McBSP 1 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0290 0018
MCR1
McBSP1 multichannel control register
McBSP1 Enhanced Receive Channel Enable Register
0 Partition A/B
0290 001C
RCERE01
McBSP1 Enhanced Transmit Channel Enable Register
0 Partition A/B
0290 0020
0290 0024
0290 0028
XCERE01
PCR1
McBSP1 Pin Control Register
McBSP1 Enhanced Receive Channel Enable Register
1 Partition C/D
RCERE11
McBSP1 Enhanced Transmit Channel Enable Register
1 Partition C/D
0290 002C
0290 0030
0290 0034
0290 0038
XCERE11
RCERE21
XCERE21
RCERE31
McBSP1 Enhanced Receive Channel Enable Register
2 Partition E/F
McBSP1 Enhanced Transmit Channel Enable Register
2 Partition E/F
McBSP1 Enhanced Receive Channel Enable Register
3 Partition G/H
McBSP1 Enhanced Transmit Channel Enable Register
3 Partition G/H
0290 003C
XCERE31
-
0290 0040 - 0293 FFFF
Reserved
7.13.2 McBSP Electrical Data/Timing
7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing
Table 7-55. Timing Requirements for McBSP(1) (see Figure 7-54)
-720
-850
-1000
NO.
UNIT
MIN
MAX
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
6P or 10(2)(3)
0.5tc(CKRX)– 1(4)
ns
ns
Pulse duration, CLKR/X high or CLKR/X low
9
1.3
6
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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Table 7-56. Switching Characteristics Over Recommended Operating Conditions for McBSP(1)(2)
(see Figure 7-54)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input(3)
1
td(CKSH-CKRXH)
1.4
10
ns
2
3
4
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
6P or 10(4)(5)(6)
C – 1(7)
–2.1
ns
ns
ns
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C + 1(7)
td(CKRH-FRV)
3
–1.7
3
9
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
1.7
9
4
–3.9
Disable time, DX high impedance following
last data bit from CLKX high
12
13
2.1
9
–3.9 + D1(8)
2.1 + D1(8)
–2.3 + D1(9)
4 + D2(8)
9 + D2(8)
5.6 + D2(9)
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
14
td(FXH-DXV)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1(9)
9 + D2(9)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(5) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(6) Use whichever value is greater.
(7) C = H or L
S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
(A)
13
14
13
(A)
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
B. The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
Figure 7-54. McBSP Timing(B)
Table 7-57. Timing Requirements for FSR When GSYNC = 1 (see Figure 7-55)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4
4
ns
ns
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 7-55. FSR Timing When GSYNC = 1
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Table 7-58. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2)
(see Figure 7-56)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7-59. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2) (see Figure 7-56)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
T + 3
L + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXH-DXV)
Hold time, FSX low after CLKX low(4)
Delay time, FSX low to CLKX high(5)
Delay time, CLKX high to DX valid
T – 2
ns
ns
ns
L – 2
–2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
tdis(CKXL-DXHZ)
L – 2
L + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-4)
Figure 7-56. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 7-60. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1)(2)
(see Figure 7-57)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7-61. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0(1)(2) (see Figure 7-57)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
L + 3
T + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXL-DXV)
Hold time, FSX low after CLKX low(4)
Delay time, FSX low to CLKX high(5)
Delay time, CLKX low to DX valid
L – 2
ns
ns
ns
T – 2
–2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
7
tdis(CKXL-DXHZ)
td(FXL-DXV)
–2
4
ns
ns
Delay time, FSX low to DX valid
H – 2
H + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 7-57. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(1)(2)
(see Figure 7-58)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7-63. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1(1)(2) (see Figure 7-58)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
T + 3
H + 3
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXL-DXV)
Hold time, FSX low after CLKX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX low to DX valid
T – 2
ns
ns
ns
H – 2
–2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
tdis(CKXH-DXHZ)
H – 2
H + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 7-58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2)
(see Figure 7-59)
-720
-850
-1000
NO.
UNIT
MASTER
SLAVE
MIN
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7-65. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1(1)(2) (see Figure 7-59)
-720
-850
-1000
NO.
PARAMETER
UNIT
MASTER(3)
MIN
SLAVE
MIN
MAX
H + 3
T + 1
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX high to DX valid
H – 2
T – 2
ns
ns
ns
–2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
7
tdis(CKXH-DXHZ)
td(FXL-DXV)
–2
4
ns
ns
Delay time, FSX low to DX valid
L – 2
L + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 7-59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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7.14 Ethernet MAC (EMAC)
The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6455
DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second
[Mbps]), and 100BaseTX (100 Mbps), in either half- or full-duplex mode, and 1000BaseT (1000 Mbps) in
full-duplex mode, with hardware flow control and quality-of-service (QOS) support.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network.
The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 7-60. The
EMAC control module contains the necessary components to allow the EMAC to make efficient use of
device memory, plus it controls device interrupts. The EMAC control module incorporates 8K-bytes of
internal RAM to hold EMAC buffer descriptors. The relationship between these three components is
shown in Figure 7-60.
Interrupt
Controller
DMA Memory
Transfer Controller
Configuration Bus
Peripheral Bus
EMAC Control Module
MDIO Module
EMAC/MDIO
Interrupt
EMAC Module
MDIO Bus
Ethernet Bus
Figure 7-60. EMAC, MDIO, and EMAC Control Modules
For more detailed information on the EMAC/MDIO, see the TMS320C645x DSP EMAC/MDIO Module
Reference Guide (literature number SPRU975).
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7.14.1 EMAC Device-Specific Information
Interface Modes
The EMAC module on the TMS320C6455 supports four interface modes: Media Independent Interface
(MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and
Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are defined in
the IEEE 802.3-2002 standard.
The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface (RGMII)
Specification (version 2.0). The RGMII mode implements the same functionality as the GMII mode, but
with a reduced number of pins. Data and control information is transmitted and received using both edges
of the transmit and receive clocks (TXC and RXC).
Note: The EMAC internally delays the transmit clock (TXC) with respect to the transmit data and control
pins. Therefore, the EMAC conforms to the RGMII-ID operation of the RGMII specification. However, the
EMAC does not delay the receive clock (RXC); this signal must be delayed with respect to the receive
data and control pins outside of the DSP.
The RMII mode of the EMAC conforms to the RMII Specification (revision 1.2), as written by the RMII
Consortium. As the name implies, the Reduced Media Independent Interface (RMII) mode is a reduced
pin count version of the MII mode.
Interface Mode Select
The EMAC uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the
RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used
is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information,
see the Device Configurations section of this document). Table 7-66 shows which multiplexed pins are
used in the MII, GMII, and RMII modes on the EMAC. For a detailed description of these pin functions,
see the Terminal Functions Table.
Using the RMII Mode of the EMAC
The Ethernet Media Access Controller (EMAC) contains logic that allows it to communicate using the
Reduced Media Independent Interface (RMII) protocol. This logic must be taken out of reset before being
used. To use the RMII mode of the EMAC follow these steps:
1. Set SYSCLK2 of the PLL2 Controller to divide-by-5 mode.
–
Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO operation is currently in
progress.
–
–
–
Set RATIO = 4h in PLLDIV1.
Set the GOSET bit in PLLCMD to initiate the GO operation.
Read the GOSTAT bit to make sure the bit returns to 0 to indicate that the GO operation has
completed.
2. Enable the EMAC/MDIO through the Device State Control Registers.
–
–
–
Unlock the PERCFG0 register by writing 0x0F0A 0B00 to the PERLOCK register.
Set bit 4 in the PERCFG0 register within 16 SYSCLK3 clock cycles to enable the EMAC/MDIO.
Poll the PERSTAT0 register to verify state change.
3. Initialize the EMAC/MDIO as needed.
4. Release the RMII logic from reset by setting the RMII_RST bit of the EMAC Configuration Register
(see Section 3.4.5).
As described in the previous section, the RMII mode of the EMAC must be selected by setting
MACSEL[1:0] = 01b at device reset.
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Table 7-66. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
BALL NUMBER
DEVICE PIN NAME
MII
RMII
GMII
(MAC_SEL = (MAC_SEL = (MAC_SEL =
00b)
01b)
10b)
J2
H3
J1
URDATA0/MRXD0/RMRXD0
URDATA1/MRXD1/RMRXD1
URDATA2/MRXD2
MRXD0
MRXD1
MRXD2
MRXD3
RMRXD0
RMRXD1
MRXD0
MRXD1
MRXD2
MRXD3
MRXD4
MRXD5
MRXD6
MRXD7
J3
URDATA3/MRXD3
L1
L2
H2
M2
URDATA4/MRXD4
URDATA5/MRXD5
URDATA6/MRXD6
URDATA7/MRXD7
M1
L4
UXDATA0/MTXD0/RMTXD0
UXDATA1/MTXD1/RMTXD1
UXDATA2/MTXD2
MTXD0
MTXD1
MTXD2
MTXD3
RMTXD0
RMTXD1
MTXD0
MTXD1
MTXD2
MTXD3
MTXD4
MTXD5
MTXD6
MTXD7
M4
K4
L3
UXDATA3/MTXD3
UXDATA4/MTXD4
L5
UXDATA5/MTXD5
M3
N5
UXDATA6/MTXD6
UXDATA7/MTXD7
H4
H5
J5
URSOC/MRXER/RMRXER
URENB/MRXDV
MRXER
MRXDV
MTXEN
MCRS
RMRXER
MRXER
MRXDV
MTXEN
MCRS
UXENB/MTXEN/RMTXEN
URCLAV/MCRS/RMCRSDV
UXSOC/MCOL
RMTXEN
J4
RMCRSDV
K3
MCOL
MCOL
K5
H1
N4
UXCLAV/GMTCLK
URCLK/MRCLK
GMTCLK
MRCLK
MTCLK
MRCLK
MTCLK
UXCLK/MTCLK/REFCLK
RMREFCLK
N3
M5
UXADDR3_GMDIO
MDIO
MDIO
MDIO
UXADDR4_GMDCLK
MDCLK
MDCLK
MDCLK
The on-chip PLL2 and PLL2 Controller generate all the clocks to the EMAC module. When enabled, the
input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see the
PLL2 and PLL2 Controller section of this document.
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7.14.2 EMAC Peripheral Register Description(s)
Table 7-67. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
02C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
02C8 0004
TXCONTROL
02C8 0008
TXTEARDOWN
-
Transmit Teardown Register
02C8 000F
Reserved
02C8 0010
RXIDVER
Receive Identification and Version Register
Receive Control Register
02C8 0014
RXCONTROL
02C8 0018
RXTEARDOWN
-
Receive Teardown Register
02C8 001C
Reserved
02C8 0020 - 02C8 007C
02C8 0180
-
Reserved
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
-
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
02C8 0184
02C8 0188
02C8 018C
02C8 0190
02C8 0194 - 02C8 019C
02C8 01A0
Reserved
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
-
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
01C8 01A4
01C8 01A8
01C8 01AC
01C8 01B0
01C8 01B4
01C8 01B8
01C8 01BC
02C8 00C0 - 02C8 00FC
02C8 0100
MAC Interrupt Mask Clear Register
Reserved
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
02C8 0104
02C8 0108
02C8 010C
Receive Maximum Length Register
Receive Buffer Offset Register
02C8 0110
RXBUFFEROFFSET
RXFILTERLOWTHRESH
-
02C8 0114
Receive Filter Low Priority Frame Threshold Register
Reserved
02C8 0118 - 02C8 011C
02C8 0120
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
02C8 0124
02C8 0128
02C8 012C
02C8 0130
02C8 0134
02C8 0138
02C8 013C
02C8 0140
02C8 0144
02C8 0148
02C8 014C
02C8 0150
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Table 7-67. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
02C8 0154
ACRONYM
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFOCONTROL
MACCONFIG
SOFTRESET
-
REGISTER NAME
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
02C8 0158
02C8 015C
02C8 0160
02C8 0164
MAC Status Register
02C8 0168
Emulation Control Register
02C8 016C
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
Soft Reset Register
02C8 0170
02C8 0174
02C8 0178 - 02C8 01CC
02C8 01D0
Reserved
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
MAC Hash Address Register 2
Back Off Test Register
02C8 01D4
02C8 01D8
02C8 01DC
02C8 01E0
02C8 01E4
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
Transmit Pause Timer Register
Reserved
02C8 01E8
02C8 01EC
TXPAUSE
02C8 01F0 - 02C8 01FC
02C8 0200 - 02C8 02FC
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
-
(see Table 7-68)
-
EMAC Statistics Registers
Reserved
-
Reserved
MAC Address Low Bytes Register (used in receive address
matching)
02C8 0500
02C8 0504
MACADDRLO
MACADDRHI
MAC Address High Bytes Register (used in receive address
matching)
02C8 0508
02C8 050C - 02C8 05FC
02C8 0600
MACINDEX
-
MAC Index Register
Reserved
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
02C8 0604
02C8 0608
02C8 060C
02C8 0610
02C8 0614
02C8 0618
02C8 061C
02C8 0620
02C8 0624
02C8 0628
02C8 062C
02C8 0630
02C8 0634
02C8 0638
02C8 063C
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0640
02C8 0644
TX0CP
TX1CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
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Table 7-67. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0648
TX2CP
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
02C8 064C
02C8 0650
02C8 0654
02C8 0658
02C8 065C
02C8 0660
02C8 0664
02C8 0668
02C8 066C
02C8 0670
02C8 0674
02C8 0678
TX3CP
TX4CP
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
02C8 067C
RX7CP
-
02C8 0680 - 02C8 06FC
Reserved
Reserved
was State RAM Test Access Registers
Processor Read and Write Access to Head Descriptor Pointers and
Interrupt Acknowledge Registers
02C8 0700 - 02C8 077C
02C8 0780 - 02C8 0FFF
-
-
Reserved
Table 7-68. EMAC Statistics Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
02C8 0200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
02C8 0204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
02C8 0208
02C8 020C
02C8 0210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
02C8 0214
02C8 0218
02C8 021C
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
02C8 0220
02C8 0224
RXUNDERSIZED
RXFRAGMENTS
Receive Frame Fragments Register
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Table 7-68. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE
02C8 0228
ACRONYM
RXFILTERED
REGISTER NAME
Filtered Receive Frames Register
Received QOS Filtered Frames Register
02C8 022C
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
02C8 0230
02C8 0234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
02C8 0238
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
RXSOFOVERRUNS
RXMOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
02C8 028C
RXDMAOVERRUNS
-
02C8 0290 - 02C8 02FC
Reserved
Table 7-69. EMAC Control Module Registers
HEX ADDRESS RANGE
02C8 1000
ACRONYM
REGISTER NAME
-
EWCTL
EWINTTCNT
-
Reserved
02C8 1004
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Timer Count Register
Reserved
02C8 1008
02C8 100C - 02C8 17FF
Table 7-70. EMAC Descriptor Memory
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
02C8 2000 - 02C8 3FFF
-
EMAC Descriptor Memory
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7.14.3 EMAC Electrical Data/Timing (MII, GMII, RMII, and RGMII)
7.14.3.1 EMAC MII and GMII Electrical Data/Timing
Table 7-71. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-61)
-720
-850
-1000
NO.
UNIT
1000 Mbps
(GMII Only)
100 Mbps
10 Mbps
MIN
8
MAX
MIN
40
MAX
MIN
400
140
140
MAX
1
2
3
4
tc(MRCLK)
tw(MRCLKH)
tw(MRCLKL)
tt(MRCLK)
Cycle time, MRCLK
ns
ns
ns
ns
Pulse duration, MRCLK high
Pulse duration, MRCLK low
Transition time, MRCLK
2.8
2.8
14
14
1
3
3
4
1
4
2
3
MRCLK
Figure 7-61. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 7-72. Timing Requirements for MTCLK - MII and GMII Operation (see Figure 7-62)
-720
-850
-1000
NO.
UNIT
100 Mbps
10 Mbps
MIN
MIN
40
MAX
MAX
1
2
3
4
tc(MTCLK)
tw(MTCLKH)
tw(MTCLKL)
tt(MTCLK)
Cycle time, MTCLK
400
ns
ns
ns
ns
Pulse duration, MTCLK high
Pulse duration, MTCLK low
Transition time, MTCLK
14
140
14
140
3
3
4
1
4
2
3
MTCLK
Figure 7-62. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
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Table 7-73. Timing Requirements for GMTCLK - GMII Operation (see Figure 7-63)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN
8
MAX
1
2
3
4
tc(GMTCLK)
tw(GMTCLKH)
tw(GMTCLKL)
tt(GMTCLK)
Cycle time, GMTCLK
ns
ns
ns
ns
Pulse duration, GMTCLK high
Pulse duration, GMTCLK low
Transition time, GMTCLK
2.8
2.8
1
4
1
4
2
3
GMTCLK
Figure 7-63. GMTCLK Timing (EMAC – Transmit) [GMII Operation]
Table 7-74. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s(1) (see Figure 7-64)
-720
-850
-1000
NO.
UNIT
1000 Mbps
MIN
100/10 Mbps
MIN
MAX
MAX
Setup time, receive selected signals valid before
MRCLK high
1
2
tsu(MRXD-MRCLKH)
th(MRCLKH-MRXD)
2
0
8
8
ns
ns
Hold time, receive selected signals valid after
MRCLK high
(1) For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER. For GMII, Receive selected signals include: MRXD[7:0],
MRXDV, and MRXER.
1
2
MRCLK (Input)
MRXD7−MRXD4(GMII only),
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 7-64. EMAC Receive Interface Timing [MII and GMII Operation]
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Table 7-75. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII
Transmit 10/100 Mbit/s(1) (see Figure 7-65)
-720
-850
-1000
NO.
PARAMETER
UNIT
100/10 Mbps
MIN
MAX
1
td(MTCLKH-MTXD)
Delay time, MTCLK high to transmit selected signals valid
5
25
ns
(1) For MII, Transmit selected signals include: MTXD[3:0] and MTXEN. For GMII, Transmit selected signals include: GMTXD[7:0] and
MTXEN.
1
MTCLK (Input)
MTXD7−MTXD4(GMII only),
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 7-65. EMAC Transmit Interface Timing [MII and GMII Operation]
Table 7-76. Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit
1000 Mbit/s(1) (see Figure 7-66)
-720
-850
-1000
NO.
PARAMETER
UNIT
1000 Mbps
MIN
MAX
1
td(GMTCLKH-MTXD) Delay time, GMTCLK high to transmit selected signals valid
0.5
5
ns
(1) For GMII, Transmit selected signals include: GMTXD[7:0] and MTXEN.
1
GMTCLK (Input)
MTXD7−MTXD0,
MTXEN (Outputs)
Figure 7-66. EMAC Transmit Interface Timing [GMII Operation]
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7.14.3.2 EMAC RMII Electrical Data/Timing
The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The
RMREFCLK frequency should be 50 MHz ±50 PPM with a duty cycle between 35% and 65%, inclusive.
Table 7-77. Timing Requirements for RMREFCLK - RMII Operation (see Figure 7-67)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
13
1
2
3
tw(RMREFCLKH)
tw(RMREFCLKL)
tt(RMREFCLK)
Pulse duration, RMREFCLK high
Pulse duration, RMREFCLK low
Transition time, RMREFCLK
7
7
ns
ns
ns
13
2
3
1
RMREFCLK
(Input)
2
3
Figure 7-67. RMREFCLK Timing
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7.14.3.3 EMAC RGMII Electrical Data/Timing
An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note
that this reference clock is not a free-running clock. This should only be used by an external device if it
does not expect a valid clock during device reset.
Table 7-78. Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK -
RGMII Operation (see Figure 7-68)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
8+TBD
TBD
1
2
3
4
tc(RGFCLK)
tw(RGFCLKH)
tw(RGFCLKL)
tt(RGFCLK)
Cycle time, RGREFCLK
8-TBD
TBD
ns
ns
ns
ns
Pulse duration, RGREFCLK high
Pulse duration, RGREFCLK low
Transition time, RGREFCLK
TBD
TBD
TBD
1
4
2
RGREFCLK
3
4
Figure 7-68. RGREFCLK Timing
Table 7-79. Timing Requirements for RXC - RGMII Operation (see Figure 7-69)
-720
-850
-1000
NO.
UNIT
MIN
MAX
10 Mbps
360
36
440
44
1
2
3
4
tc(RXC)
Cycle time, RXC
100 Mbps
1000 Mbps
10 Mbps
ns
ns
ns
ns
7.2
8.8
0.40*tc(RXC) 0.60*tc(RXC)
0.40*tc(RXC) 0.60*tc(RXC)
0.45*tc(RXC) 0.55*tc(RXC)
0.40*tc(RXC) 0.60*tc(RXC)
0.40*tc(RXC) 0.60*tc(RXC)
0.45*tc(RXC) 0.55*tc(RXC)
0.75
tw(RXCH)
tw(RXCL)
tt(RXC)
Pulse duration, RXC high
Pulse duration, RXC low
Transition time, RXC
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
0.75
0.75
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Table 7-80. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps(1) (see Figure 7-69)
-720
-850
-1000
NO.
UNIT
MIN
MAX
5
6
tsu(RXD-RXCH)
th(RXCH-RXD)
Setup time, receive selected signals valid before RXC (at DSP) high/low
Hold time, receive selected signals valid after RXC (at DSP) high/low
1.0
1.0
ns
ns
(1) For RGMII, receive selected signals include: RXD[3:0] and RXCTL.
1
4
2
4
3
RXC
(B)
(at DSP)
5
1st Half-byte
6
2nd Half-byte
(A)
RXD[3:0]
RXD[3:0]
RXDV
RXD[7:4]
RXERR
(A)
RXCTL
A. Data and control information is received using both edges of the clocks. RXD[3:0] carries data bits 3-0 on the rising
edge of RXC and data bits 7-4 on the falling edge of RXC. Similarly, RXCTL carries RXDV on rising edge of RXC and
RXERR on falling edge
B. RXC must be externally delayed relative to the data and control pins.
Figure 7-69. EMAC Receive Interface Timing [RGMII Operation](A)(B)
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Table 7-81. Timing Requirements for TXC - RGMII Operation for 10/100/1000 Mbit/s (see Figure 7-70)
-720
-850
-1000
NO.
UNIT
MIN
MAX
10 Mbps
360
440
44
1
2
3
4
tc(TXC)
Cycle time, TXC
100 Mbps
1000 Mbps
10 Mbps
36
ns
ns
ns
ns
7.2
8.8
0.40*tc(TXC) 0.60*tc(TXC)
0.40*tc(TXC) 0.60*tc(TXC)
0.45*tc(TXC) 0.55*tc(TXC)
0.40*tc(TXC) 0.60*tc(TXC)
0.40*tc(TXC) 0.60*tc(TXC)
0.45*tc(TXC) 0.55*tc(TXC)
0.75
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, TXC high
Pulse duration, TXC low
Transition time, TXC
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
10 Mbps
100 Mbps
1000 Mbps
0.75
0.75
Table 7-82. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII
Transmit (1)(see Figure 7-70)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
5
6
tsu(TXD-TXCH)
th(TXCH-TXD)
Setup time, transmit selected signals valid before TXC (at DSP) high/low
Hold time, transmit selected signals valid after TXC (at DSP) high/low
1.2
1.2
ns
(1) For RGMII, transmit selected signals include: TXD[3:0] and TXCTL.
TXC at DSP pins
1
Internal TXC
4
4
2
3
(B)
TXC (at DSP)
1
5
(A)
1st Half-byte
2nd Half-byte
TXERR
TXD[3:0]
TXCTL
6
2
(A)
TXEN
A. Data and control information is transmitted using both edges of the clocks. TXD[3:0] carries data bits 3-0 on the rising
edge of TXC and data bits 7-4 on the falling edge of TXC. Similarly, TX_CTL carries TXEN on rising edge of TXC and
TXERR of falling edge.
B. TXC is delayed internally before being driven to the TXC pin.
Figure 7-70. EMAC Transmit Interface Timing [RGMII Operation](A)(B)
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7.14.4 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC
module for correct operation. The module is designed to allow almost transparent operation of the MDIO
interface, with very little maintenance from the core processor.
The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 7-60.
The MDIO uses the same pins for the MII, GMII, and RMII modes. Standalone pins are included for the
RGMII mode due to specific voltage requirements. Only one mode can be used at a time. The mode used
is selected at device reset based on the MACSEL[1:0] configuration pins (for more detailed information,
see the Device Configurations section of this document). Table 7-66 above shows which multiplexed pin
are used in the MII, GMII, and RMII modes on the MDIO.
For more detailed information on the EMAC/MDIO, see the TMS320C645x DSP EMAC/MDIO Module
Reference Guide (literature number SPRU975).
7.14.4.1 MDIO Device-Specific Information
Clocking Information
The on-chip PLL2 and PLL2 Controller generate all the clocks to the MDIO module. When enabled, the
input clock to the PLL2 Controller (CLKIN2) must have a 25 MHz frequency. For more information, see the
PLL2 and PLL2 Controller section of this document.
7.14.4.2 MDIO Peripheral Register Description(s)
Table 7-87. MDIO Registers
HEX ADDRESS RANGE
02C8 1800
ACRONYM
VERSION
REGISTER NAME
MDIO Version Register
MDIO Control Register
02C8 1804
CONTROL
02C8 1808
ALIVE
MDIO PHY Alive Status Register
02C8 180C
LINK
MDIO PHY Link Status Register
02C8 1810
LINKINTRAW
LINKINTMASKED
-
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
02C8 1814
02C8 1818 - 02C8 181C
02C8 1820
USERINTRAW
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
-
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
02C8 1824
02C8 1828
02C8 182C
02C8 1830 - 02C8 187C
02C8 1880
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
-
MDIO User Access Register 0
02C8 1884
MDIO User PHY Select Register 0
02C8 1888
MDIO User Access Register 1
02C8 188C
MDIO User PHY Select Register 1
02C8 1890 - 02C8 1FFF
Reserved
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7.14.4.3 MDIO Electrical Data/Timing
Table 7-88. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-73)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2a
2b
3
tc(MDCLK)
Cycle time, MDCLK
400
180
180
ns
ns
ns
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high
tw(MDCLK)
Pulse duration, MDCLK low
tt(MDCLK)
Transition time, MDCLK
5
4
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
10
10
5
1
MDCLK
3
4
MDIO
(input)
Figure 7-73. MDIO Input Timing
Table 7-89. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 7-74)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
100
ns
1
MDCLK
7
MDIO
(output)
Figure 7-74. MDIO Output Timing
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7.15 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send
synchronization events to the EDMA3 channel controller.
7.15.1 Timers Device-Specific Information
The C6455 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured
as a general-purpose timer or a watchdog timer. When configured as a general-purpose timer, each timer
can be programmed as a 64-bit timer or as two separate 32-bit timers.
Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx
and TOUTLx are connected to the low counter. The high counter does not have any external device pins.
7.15.2 Timers Peripheral Register Description(s)
Table 7-90. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0294 0000
-
Reserved
Timer 0 Emulation Management/Clock Speed
Register
0294 0004
EMUMGT_CLKSPD0
0294 0008
0294 000C
-
-
Reserved
Reserved
0294 0010
CNTLO0
CNTHI0
PRDLO0
PRDHI0
TCR0
TGCR0
WDTCR0
-
Timer 0 Counter Register Low
Timer 0 Counter Register High
Timer 0 Period Register Low
Timer 0 Period Register High
Timer 0 Control Register
Timer 0 Global Control Register
Timer 0 Watchdog Timer Control Register
Reserved
0294 0014
0294 0018
0294 001C
0294 0020
0294 0024
0294 0028
0294 002C
0294 0030
-
Reserved
0294 0034 - 0297 FFFF
-
Reserved
Table 7-91. Timer 1 Registers
HEX ADDRESS RANGE
0298 0000
ACRONYM
REGISTER NAME
Reserved
COMMENTS
-
0298 0004
EMUMGT_CLKSPD1
Timer 1 Emulation Management/Clock Speed Register
Reserved
0298 0008
-
-
0298 000C
Reserved
0298 0010
CNTLO1
CNTHI1
PRDLO1
PRDHI1
TCR1
TGCR1
WDTCR1
-
Timer 1 Counter Register Low
Timer 1 Counter Register High
Timer 1 Period Register Low
Timer 1 Period Register High
Timer 1 Control Register
Timer 1 Global Control Register
Timer 1 Watchdog Timer Control Register
Reserved
0298 0014
0298 0018
0298 001C
0298 0020
0298 0024
0298 0028
0298 002C
0298 0030
-
Reserved
0298 0034 - 0299 FFFF
-
Reserved
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7.15.3 Timers Electrical Data/Timing
Table 7-92. Timing Requirements for Timer Inputs(1) (see Figure 7-75)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(TINPH)
tw(TINPL)
Pulse duration, TINPLx high
Pulse duration, TINPLx low
12P
12P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-93. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs(1)
(see Figure 7-75)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, TOUTLx high
Pulse duration, TOUTLx low
12P – 3
12P – 3
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
TINPLx
4
3
TOUTLx
Figure 7-75. Timer Timing
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7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)
7.16.1 VCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2)
that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock
divided-by-4 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels.
The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, ½, 1/3, 1/4, and 1/5, and
flexible polynomials, while generating hard decisions or soft decisions. Communications between the
VCP2 and the CPU are carried out through the EDMA3 controller.
The VCP2 supports:
•
•
•
•
•
•
•
•
•
•
Unlimited frame sizes
Code rates 3/4, ½, 1/3, 1/4, and 1/5
Constraint lengths 5, 6, 7, 8, and 9
Programmable encoder polynomials
Programmable reliability and convergence lengths
Hard and soft decoded decisions
Tail and convergent modes
Yamamoto logic
Tail biting logic
Various input and output FIFO lengths
For more detailed information on the VCP2, see the TMS320C64x DSP Viterbi-Decoder Coprocessor 2
(VCP2) Reference Guide (literature number SPRUTBD). And TBD
7.16.2 VCP2 Peripheral Register Description(s)
Table 7-94. VCP2 Registers
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
5800 0000
5800 0004
5800 0008
5800 000C
5800 0010
5800 0014
5800 0018 - 5800 0044
5800 0048
5800 004C
5800 0050 - 5800 007C
5800 0080
5800 0084 - 5800 009C
5800 00C0
N/A
-
-
-
-
-
-
VCPIC0
VCPIC1
VCPIC2
VCPIC3
VCPIC4
VCPIC5
-
VCP2 Input Configuration Register 0
VCP2 Input Configuration Register 1
VCP2 Input Configuration Register 2
VCP2 Input Configuration Register 3
VCP2 Input Configuration Register 4
VCP2 Input Configuration Register 5
Reserved
-
-
VCPOUT0
VCPOUT1
-
VCP2 Output Register 0
VCP2 Output Register 1
Reserved
N/A
VCPWBM
-
VCP2 Branch Metrics Write FIFO Register
Reserved
N/A
VCPRDECS VCP2 Decisions Read FIFO Register
02B8 0018
02B8 0020
02B8 0040
02B8 0044
02B8 0050
VCPEXE
VCPEND
VCP2 Execution Register
N/A
VCP2 Endian Mode Register
N/A
VCPSTAT0 VCP2 Status Register 0
VCPSTAT1 VCP2 Status Register 1
N/A
N/A
VCPERR
-
VCP2 Error Register
Reserved
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Table 7-94. VCP2 Registers (continued)
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
N/A
02B8 0060
VCPEMU
-
VCP2 Emulation Control Register
N/A
02B8 0064 - 02B9 FFFF
Reserved
5800 1000
5800 2000
5800 3000
5800 6000
5800 F000
-
-
-
-
-
BM
Branch Metrics
SM
State Metric
TBHD
TBSD
IO
Traceback Hard Decision
Traceback Soft Decision
Decoded Bits
7.17 Enhanced Turbo Decoder Coprocessor (TCP2)
7.17.1 TCP2 Device-Specific Information
The C6455 device has a high-performance embedded coprocessor [Turbo-Decoder Coprocessor (TCP2)
that significantly speeds up channel-decoding operations on-chip. The TCP2 operating at CPU clock
divided-by-2 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6
iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials
and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable
frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping
criteria are also programmable. Communications between the TCP2 and the CPU are carried out through
the EDMA3 controller.
The TCP2 supports:
•
•
•
•
•
•
•
•
•
•
•
Parallel concatenated convolutional turbo decoding using the MAP algorithm
All turbo code rates greater than or equal to 1/5
3GPP and CDMA2000 turbo encoder trellis
3GPP and CDMA2000 block sizes in standalone mode
Larger block sizes in shared processing mode
Both max log MAP and log MAP decoding
Sliding windows algorithm with variable reliability and prolog lengths
The prolog reduction algorithm
Execution of a minimum and maximum number of iterations
The SNR stopping criteria algorithm
The CRC stopping criteria algorithm
For more detailed information on the TCP2, see the TMS320C64x DSP Turbo-Decoder Coprocessor
(TCP) Reference Guide (literature number SPRU534). And TBD
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7.17.2 TCP2 Peripheral Register Description(s)
Table 7-95. TCP2 Registers
EDMA BUS
HEX ADDRESS RANGE
CONFIGURATION BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
5000 0000
5000 0004
5000 0008
5000 000C
5000 0010
5000 0014
5000 0018
5000 001C
5000 0020
5000 0024
5000 0028
5000 002C
5000 0030
5000 0034
5000 0038
5000 003C
5000 0040
5000 0044
5000 0048
5001 0000
5003 0000
5004 0000
5005 0000
5006 0000
5007 0000
5008 0000
5009 0000
500A 0000
500B 0000
-
TCPIC0
TCPIC1
TCPIC2
TCPIC3
TCPIC4
TCPIC5
TCPIC6
TCPIC7
TCPIC8
TCPIC9
TCPIC10
TCPIC11
TCPIC12
TCPIC13
TCPIC14
TCPIC15
TCPOUT0
TCPOUT1
TCPOUTP2
X0
TCP2 Input Configuration Register 0
TCP2 Input Configuration Register 1
TCP2 Input Configuration Register 2
TCP2 Input Configuration Register 3
TCP2 Input Configuration Register 4
TCP2 Input Configuration Register 5
TCP2 Input Configuration Register 6
TCP2 Input Configuration Register 7
TCP2 Input Configuration Register 8
TCP2 Input Configuration Register 9
TCP2 Input Configuration Register 10
TCP2 Input Configuration Register 11
TCP2 Input Configuration Register 12
TCP2 Input Configuration Register 13
TCP2 Input Configuration Register 14
TCP2 Input Configuration Register 15
TCP2 Output Parameters Register 0
TCP2 Output Parameters Register 1
TCP2 Output Parameters Register 2
TCP2 Data/Sys and Parity Memory
TCP2 Extrinsic Mem 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
W0
W1
TCP2 Extrinsic Mem 1
I0
TCP2 Interleaver Memory
O0
TCP2 Output/Decision Memory
TCP2 Scratch Pad Memory
S0
T0
TCP2 Beta State Memory
C0
TCP2 CRC Memory
B0
TCP2 Beta Prolog Memory
A0
TCP2 Alpha Prolog Memory
TCP2 Peripheral Identification Register [Value:
0xTBD]
02BA 0000
TCPPID
N/A
N/A
N/A
N/A
N/A
N/A
02BA 004C
02BA 0050
TCPEXE
TCPEND
TCPERR
TCPSTAT
TCPEMU
-
TCP2 Execute Register
TCP2 Endianness Register
TCP2 Error Register
TCP2 Status Register
TCP2 Emulation Register
Reserved
02BA 0060
02BA 0068
02BA 0070
02BA 005C - 02BB FFFF
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7.18 Peripheral Component Interconnect (PCI)
The C6455 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus
interface. The PCI port interfaces to DSP internal resources via the data switched central resource. The
data switched central resource is described in more detail in Section 4.
For more detailed information on the PCI port peripheral module, see the TBD Reference Guide (literature
number SPRUTBD).
7.18.1 PCI Device-Specific Information
On the C6455 device, the PCI interface is multiplexed with the HPI, UTOPIA, or GPIO peripherals.
The PCI is controlled (enabled/disabled) by the PCI_EN pin (Y29) in conjunction with the MCSBP1_EN
(AEA5 pin [U28]). For more detailed information on the peripheral control, see the Device Configuration
section of this document.
By default, the PCI Vendor ID/Device ID register is initialized to 0xB000 after reset.
The PCI peripheral is a master peripheral in the C6455 DSP. It conforms to the PCI Specification, revision
2.3.
A PCI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
7.18.2 PCI Peripheral Register Description(s)
Table 7-96. PCI Configuration Registers
PCI HOST ACCESS
HEX ADDRESS OFFSET
ACRONYM
PCI HOST ACCESS REGISTER NAME
Vendor ID/Device ID
0x00
0x04
PCIVENDEV
PCICSR
PCICLREV
PCICLINE
PCIBAR0
PCIBAR1
PCIBAR2
PCIBAR3
PCIBAR4
PCIBAR5
-
Command/Status
0x08
Class Code/Revision ID
BIST/Header Type/Latency Timer/Cacheline Size
Base Address 0
0x0C
0x10
0x14
Base Address 1
0x18
Base Address 2
0x1C
Base Address 3
0x20
Base Address 4
0x24
Base Address 5
0x28 - 0x2B
0x2C
Reserved
PCISUBID
-
Subsystem Vendor ID/Subsystem ID
Reserved
0x30
0x34
PCICPBPTR
-
Capabilities Pointer
Reserved
0x38 - 0x3B
0x3C
PCILGINT
-
Max Latency/Min Grant/Interrupt Pin/Interrupt Line
Reserved
0x40 - 0x7F
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Table 7-97. PCI Back End Configuration Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
02C0 0000 - 02C0 000F
02C0 0010
-
Reserved
PCISTATSET
PCISTATCLR
-
PCI Status Set Register
02C0 0014
PCI Status Clear Register
02C0 0018 - 02C0 001F
02C0 0020
Reserved
PCIHINTSET
PCIHINTCLR
-
PCI Host Interrupt Enable Set Register
PCI Host Interrupt Enable Clear Register
Reserved
02C0 0024
02C0 0028 - 02C0 002F
02C0 0030
PCIBINTSET
PCIBINTCLR
PCIBCLKMGT
-
PCI Back End Application Interrupt Enable Set Register
PCI Back End Application Interrupt Enable Clear Register
PCI Back End Application Clock Management Register
Reserved
02C0 0034
02C0 0038
02C0 003C - 02C0 00FF
02C0 0100
PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register
PCICSRMIR PCI Command/Status Mirror Register
PCICLREVMIR PCI Class Code/Revision ID Mirror Register
02C0 0104
02C0 0108
02C0 010C
PCICLINEMIR
PCIBAR0MSK
PCIBAR1MSK
PCIBAR2MSK
PCIBAR3MSK
PCIBAR4MSK
PCIBAR5MSK
-
PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
02C0 0110
PCI Base Address Mask Register 0
PCI Base Address Mask Register 1
PCI Base Address Mask Register 2
PCI Base Address Mask Register 3
PCI Base Address Mask Register 4
PCI Base Address Mask Register 5
Reserved
02C0 0114
02C0 0118
02C0 011C
02C0 0120
02C0 0124
02C0 0128 - 02C0 012B
02C0 012C
PCISUBIDMIR
-
PCI Subsystem Vendor ID/Subsystem ID Mirror Register
Reserved
02C0 0130
02C0 0134
PCICPBPTRMIR PCI Capabilities Pointer Mirror Register
02C0 0138 - 02C0 013B
02C0 013C
-
Reserved
PCILGINTMIR
-
PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
Reserved
02C0 0140 - 02C0 017F
02C0 0180
PCISLVCNTL
-
PCI Slave Control Register
02C0 0184 - 02C0 01BF
02C0 01C0
Reserved
PCIBAR0TRL
PCIBAR1TRL
PCIBAR2TRL
PCIBAR3TRL
PCIBAR4TRL
PCIBAR5TRL
-
PCI Slave Base Address 0 Translation Register
PCI Slave Base Address 1 Translation Register
PCI Slave Base Address 2 Translation Register
PCI Slave Base Address 3 Translation Register
PCI Slave Base Address 4 Translation Register
PCI Slave Base Address 5 Translation Register
Reserved
02C0 01C4
02C0 01C8
02C0 01CC
02C0 01D0
02C0 01D4
02C0 01D8 - 02C0 01DF
02C0 01E0
PCIBAR0MIR
PCIBAR1MIR
PCIBAR2MIR
PCIBAR3MIR
PCIBAR4MIR
PCIBAR5MIR
-
PCI Base Address Register 0 Mirror Register
PCI Base Address Register 1 Mirror Register
PCI Base Address Register 2 Mirror Register
PCI Base Address Register 3 Mirror Register
PCI Base Address Register 4 Mirror Register
PCI Base Address Register 5 Mirror Register
Reserved
02C0 01E4
02C0 01E8
02C0 01EC
02C0 01F0
02C0 01F4
02C0 01F8 - 02C0 02FF
02C0 0300
PCIMCFGDAT PCI Master Configuration/IO Access Data Register
PCIMCFGADR PCI Master Configuration/IO Access Address Register
02C0 0304
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Table 7-97. PCI Back End Configuration Registers (continued)
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
02C0 0308
PCIMCFGCMD PCI Master Configuration/IO Access Command Register
02C0 030C - 02C0 030F
02C0 0310
-
Reserved
PCIMSTCFG
PCI Master Configuration Register
Table 7-98. DSP-to_PCI Address Translation Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
02C0 0314
02C0 0318
02C0 031C
02C0 0320
02C0 0324
02C0 0328
02C0 032C
02C0 0330
02C0 0334
02C0 0338
02C0 033C
02C0 0340
02C0 0344
02C0 0348
02C0 034C
02C0 0350
02C0 0354
02C0 0358
02C0 035C
02C0 0360
02C0 0364
02C0 0368
02C0 036C
02C0 0370
02C0 0374
02C0 0378
02C0 037C
02C0 0380
02C0 0384
02C0 0388
02C0 038C
02C0 0390
PCIADDSUB0
PCIADDSUB1
PCIADDSUB2
PCIADDSUB3
PCIADDSUB4
PCIADDSUB5
PCIADDSUB6
PCIADDSUB7
PCIADDSUB8
PCIADDSUB9
PCI Address Substitute 0 Register
PCI Address Substitute 1 Register
PCI Address Substitute 2 Register
PCI Address Substitute 3 Register
PCI Address Substitute 4 Register
PCI Address Substitute 5 Register
PCI Address Substitute 6 Register
PCI Address Substitute 7 Register
PCI Address Substitute 8 Register
PCI Address Substitute 9 Register
PCIADDSUB10 PCI Address Substitute 10 Register
PCIADDSUB11 PCI Address Substitute 11 Register
PCIADDSUB12 PCI Address Substitute 12 Register
PCIADDSUB13 PCI Address Substitute 13 Register
PCIADDSUB14 PCI Address Substitute 14 Register
PCIADDSUB15 PCI Address Substitute 15 Register
PCIADDSUB16 PCI Address Substitute 16 Register
PCIADDSUB17 PCI Address Substitute 17 Register
PCIADDSUB18 PCI Address Substitute 18 Register
PCIADDSUB19 PCI Address Substitute 19 Register
PCIADDSUB20 PCI Address Substitute 20 Register
PCIADDSUB21 PCI Address Substitute 21 Register
PCIADDSUB22 PCI Address Substitute 22 Register
PCIADDSUB23 PCI Address Substitute 23 Register
PCIADDSUB24 PCI Address Substitute 24 Register
PCIADDSUB25 PCI Address Substitute 25 Register
PCIADDSUB26 PCI Address Substitute 26 Register
PCIADDSUB27 PCI Address Substitute 27 Register
PCIADDSUB28 PCI Address Substitute 28 Register
PCIADDSUB29 PCI Address Substitute 29 Register
PCIADDSUB30 PCI Address Substitute 30 Register
PCIADDSUB31 PCI Address Substitute 31 Register
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Table 7-99. PCI Hook Configuration Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
02C0 0394
02C0 0398
02C0 039C
02C0 03A0
02C0 03A4
02C0 03A8
02C0 03AC
02C0 03B0
02C0 03B4
02C0 03B8
02C0 03BC
02C0 03C0
02C0 03C4
02C0 03C8
02C0 03CC
02C0 03D0
02C0 03D4
02C0 03D8
02C0 03DC
02C0 03E0
02C0 03E4
02C0 03E8
02C0 03EC
02C0 03F0
02C0 03F4
02C0 03F8
02C0 03FC - 02C0 03FF
PCIVENDEVPRG PCI Vendor ID and Device ID Program Register
PCICMDSTATPRG PCI Command and Status Program Register
PCICLREVPRG
PCISUBIDPRG
PCI Class Code and Revision ID Program Register
PCI Subsystem Vendor ID and Subsystem ID Program Register
PCIMAXLGPRG PCI Max Latency and Min Grant Program Register
PCILRSTREG
PCICFGDONE
PCI LRESET Register
PCI Configuration Done Register
PCIBAR0MPRG PCI Base Address Mask Register 0 Program Register
PCIBAR1MPRG PCI Base Address Mask Register 1 Program Register
PCIBAR2MPRG PCI Base Address Mask Register 2 Program Register
PCIBAR3MPRG PCI Base Address Mask Register 3 Program Register
PCIBAR4MPRG PCI Base Address Mask Register 4 Program Register
PCIBAR5MPRG PCI Base Address Mask Register 5 Program Register
PCIBAR0PRG
PCIBAR1PRG
PCIBAR2PRG
PCIBAR3PRG
PCIBAR4PRG
PCIBAR5PRG
PCI Base Address Register 0 Program Register
PCI Base Address Register 1 Program Register
PCI Base Address Register 2 Program Register
PCI Base Address Register 3 Program Register
PCI Base Address Register 4 Program Register
PCI Base Address Register 5 Program Register
PCIBAR0TRLPRG PCI Base Address Translation Register 0 Program Register
PCIBAR1TRLPRG PCI Base Address Translation Register 1 Program Register
PCIBAR2TRLPRG PCI Base Address Translation Register 2 Program Register
PCIBAR3TRLPRG PCI Base Address Translation Register 3 Program Register
PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register
PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register
PCIBASENPRG PCI Base En Prog Register
-
Reserved
Table 7-100. PCI External Memory Space
HEX ADDRESS OFFSET
4000 0000 - 407F FFFF
4080 0000 - 40FF FFFF
4100 0000 - 417F FFFF
4180 0000 - 41FF FFFF
4200 0000 - 427F FFFF
4280 0000 - 42FF FFFF
4300 0000 - 437F FFFF
4380 0000 - 43FF FFFF
4400 0000 - 447F FFFF
4480 0000 - 44FF FFFF
4500 0000 - 457F FFFF
4580 0000 - 45FF FFFF
4600 0000 - 467F FFFF
4680 0000 - 46FF FFFF
4700 0000 - 477F FFFF
ACRONYM
REGISTER NAME
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI Master Window 0
PCI Master Window 1
PCI Master Window 2
PCI Master Window 3
PCI Master Window 4
PCI Master Window 5
PCI Master Window 6
PCI Master Window 7
PCI Master Window 8
PCI Master Window 9
PCI Master Window 10
PCI Master Window 11
PCI Master Window 12
PCI Master Window 13
PCI Master Window 14
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Table 7-100. PCI External Memory Space (continued)
HEX ADDRESS OFFSET
4780 0000 - 47FF FFFF
4800 0000 - 487F FFFF
4880 0000 - 48FF FFFF
4900 0000 - 497F FFFF
4980 0000 - 49FF FFFF
4A00 0000 - 4A7F FFFF
4A80 0000 - 4AFF FFFF
4B00 0000 - 4B7F FFFF
4B80 0000 - 4BFF FFFF
4C00 0000 - 4C7F FFFF
4C80 0000 - 4CFF FFFF
4D00 0000 - 4D7F FFFF
4D80 0000 - 4DFF FFFF
4E00 0000 - 4E7F FFFF
4E80 0000 - 4EFF FFFF
4F00 0000 - 4F7F FFFF
4F80 0000 - 4FFF FFFF
ACRONYM
REGISTER NAME
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI Master Window 15
PCI Master Window 16
PCI Master Window 17
PCI Master Window 18
PCI Master Window 19
PCI Master Window 20
PCI Master Window 21
PCI Master Window 22
PCI Master Window 23
PCI Master Window 24
PCI Master Window 25
PCI Master Window 26
PCI Master Window 27
PCI Master Window 28
PCI Master Window 29
PCI Master Window 30
PCI Master Window 31
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7.18.3 PCI Electrical Data/Timing
7.18.3.1 Peripheral Component Interconnect (PCI) Timing
Table 7-101. Timing Requirements for PCLK(1) (see Figure 7-76)
-720
-850
-1000
NO.
UNIT
[33 MHz]
[66 MHz]
MIN
30
11
11
1
MAX
MIN
15
6
MAX
1
2
3
4
tc(PCLK)
Cycle time, PCLK
ns
ns
tw(PCLKH)
tw(PCLKL)
tsr(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
6
ns
4
1.5
4
V/ns
(1) For 3.3-V operation, the reference points for the rise and fall transitions are measured at PCI VIL MAX and VIH MIN.
0.4 DV V MIN
DD
Peak to Peak for
3.3V signaling
1
4
2
PCLK
3
4
Figure 7-76. PCLK Timing
Table 7-102. Timing Requirements for PCI Reset (see Figure 7-77)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(PRST)
tsu(PCLKA-PRSTH)
Pulse duration, PRST
1
ms
Setup time, PCLK active before PRST high
100
µs
PCLK
1
PRST
2
Figure 7-77. PCI Reset (PRST) Timing
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Table 7-103. Timing Requirements for PCI Inputs (see Figure 7-78)
-720
-850
-1000
NO.
UNIT
33 MHz
MIN
66 MHz
MIN
MAX
MAX
4
5
tsu(IV-PCLKH)
th(IV-PCLKH)
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
7
0
3
0
ns
ns
PCLK
4
5
PCI Input
Inputs Valid
Figure 7-78. PCI Input Timing (33-/66-MHz)
Table 7-104. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs
(see Figure 7-79)
-720
-850
-1000
NO.
PARAMETER
UNIT
33 MHz
MIN
66 MHz
MIN
MAX
MAX
1a
1b
2
td(PCLKH-OV)
td(PCLKH-OIV)
td(PCLKH-OLZ)
td(PCLKH-OHZ)
Delay time, PCLK high to output valid
11
6
ns
ns
ns
ns
Delay time, PCLK high to output invalid
2
2
2
2
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
3
28
14
PCLK
1
1
PCI Output
2
3
Figure 7-79. PCI Output Timing (33-/66-MHz)
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7.19 UTOPIA
7.19.1 UTOPIA Device-Specific Information
The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8-Bit
Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is
serviced directly by the EDMA3 controller. The UTOPIA peripheral contains two, two-cell FIFOs, one for
transmit and one for receive, with which to buffer up data sent/received across the pins. There is a
transmit and a receive event to the EDMA3 channel controller to enable servicing.
For more detailed information on the UTOPIA peripheral, see the TMS320C645x DSP Universal Test and
Operations PHY Interface for ATM 2 (UTOPIA2) User's Guide (literature number SPRUE48).
7.19.2 UTOPIA Peripheral Register Description(s)
Table 7-105. UTOPIA Registers
HEX ADDRESS RANGE
02B4 0000
ACRONYM
REGISTER NAME
UCR
UTOPIA Control Register
Reserved
02B4 0004
-
02B4 0008
-
Reserved
02B4 000C
-
Reserved
02B4 0010
-
Reserved
02B4 0014
CDR
EIER
EIPR
-
Clock Detect Register
Error Interrupt Enable Register
02B4 0018
02B4 001C
Error Interrupt Pending Register
Reserved
02B4 0020 - 02B4 01FF
02B4 0200 - 02B7 FFFF
-
Reserved
Table 7-106. UTOPIA Data Queues (Receive and Transmit) Registers
HEX ADDRESS RANGE
3C00 0000 - 3C00 03FF
3C00 0400 - 3C00 07FF
ACRONYM
URQ
REGISTER NAME
UTOPIA Receive (Rx) Data Queue
UTOPIA Transmit (Tx) Data Queue
UXQ
7.19.3 UTOPIA Electrical Data/Timing
Table 7-107. Timing Requirements for UXCLK(1) (see Figure 7-80)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
tc(UXCK)
tw(UXCKH)
tw(UXCKL)
tt(UXCK)
Cycle time, UXCLK
20
0.4tc(UXCK)
0.4tc(UXCK)
ns
ns
ns
ns
Pulse duration, UXCLK high
Pulse duration, UXCLK low
Transition time, UXCLK
0.6tc(UXCK)
0.6tc(UXCK)
2
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
208
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1
4
2
UXCLK
3
4
Figure 7-80. UXCLK Timing
Table 7-108. Timing Requirements for URCLK(1) (see Figure 7-81)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
3
4
tc(URCK)
tw(URCKH)
tw(URCKL)
tt(URCK)
Cycle time, URCLK
20
0.4tc(URCK)
0.4tc(URCK)
ns
ns
ns
ns
Pulse duration, URCLK high
Pulse duration, URCLK low
Transition time, URCLK
0.6tc(URCK)
0.6tc(URCK)
2
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1
4
2
URCLK
3
4
Figure 7-81. URCLK Timing
Table 7-109. Timing Requirements for UTOPIA Slave Transmit (see Figure 7-83)
-720
-850
-1000
NO.
UNIT
MIN
4
MAX
2
3
8
9
tsu(UXAV-UXCH)
th(UXCH-UXAV)
tsu(UXENBL-UXCH)
th(UXCH-UXENBL)
Setup time, UXADDR valid before UXCLK high
Hold time, UXADDR valid after UXCLK high
Setup time, UXENB low before UXCLK high
Hold time, UXENB low after UXCLK high
ns
ns
ns
ns
1
4
1
Table 7-110. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Transmit Cycles (see Figure 7-82)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
12
1
4
5
6
7
td(UXCH-UXDV)
Delay time, UXCLK high to UXDATA valid
3
3
3
9
3
ns
ns
ns
ns
ns
td(UXCH-UXCLAV)
td(UXCH-UXCLAVL)
td(UXCH-UXCLAVHZ)
tw(UXCLAVL-UXCLAVHZ)
Delay time, UXCLK high to UXCLAV driven active value
Delay time, UXCLK high to UXCLAV driven inactive low
Delay time, UXCLK high to UXCLAV going Hi-Z
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
12
12
18.5
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Table 7-110. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Transmit Cycles (see Figure 7-82) (continued)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
10
td(UXCH-UXSV)
UXCLK
Delay time, UXCLK high to UXSOC valid
3
12
ns
1
3
P45
P46
N
P47
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
0x1F
N
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals).
Figure 7-82. UTOPIA Slave Transmit Timing(A)
Table 7-111. Timing Requirements for UTOPIA Slave Receive (see Figure 7-82)
-720
-850
-1000
NO.
UNIT
MIN
4
MAX
1
2
tsu(URDV-URCH)
th(URCH-URDV)
tsu(URAV-URCH)
th(URCH-URAV)
tsu(URENBL-URCH)
th(URCH-URENBL)
tsu(URSH-URCH)
th(URCH-URSH)
Setup time, URDATA valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
ns
ns
ns
ns
ns
ns
ns
ns
1
3
4
4
1
9
4
10
11
12
1
4
1
210
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Table 7-112. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles (see Figure 7-83)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
12
5
6
7
8
td(URCH-URCLAV)
Delay time, URCLK high to URCLAV driven active value
Delay time, URCLK high to URCLAV driven inactive low
Delay time, URCLK high to URCLAV going Hi-Z
3
3
9
3
ns
ns
ns
ns
td(URCH-URCLAVL)
td(URCH-URCLAVHZ)
tw(URCLAVL-URCLAVHZ)
12
18.5
Pulse duration (low), URCLAV low to URCLAV Hi-Z
UXCLK
1
3
P45
P46
N
P47
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
0x1F
N
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
A. The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and UXSOC signals).
Figure 7-83. UTOPIA Slave Receive Timing(A)
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7.20 Serial Rapid I/O (SRIO) Port
The SRIO Port on the C6455 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the Rapid I/O interconnect in a baseband board design can create a
homogeneous interconnect environment, providing even more connectivity and control among the
components. Rapid I/O is based on the memory and device addressing concepts of processor buses
where the transaction processing is managed completely by hardware. This enables the Rapid I/O
interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. The Rapid I/O
interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per
second (Gbps) bidirectional links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate of 3 125 Gbps per differential pair.
This equals 12.5 raw GBaud/s for the 4x RapidIO port, or approximately 9 Gbps data throughput rate.
7.20.1 Serial RIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
EMIF, HPI, and McBSP. For these other interfaces the device timing was specified in terms of data
manual specifications and I/O buffer information specification (IBIS) models.
For the C6455 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing
two DSPs connected via a 4x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the Implementing Serial RapidIO (SRIO) PCB Layout on a TMS320C6455
Hardware Design Application Report (literature number SPRAAB0).
TI only supports designs that follow the board design guidelines outlined in the SPRAAB0
application report.
The Serial RapidIO peripheral is a master peripheral in the C6455 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
7.20.2 Serial RIO Peripheral Register Description(s)
Table 7-113. RapidIO Control Registers
HEX ADDRESS RANGE
02D0 0000
ACRONYM
REGISTER NAME
RapidIO Peripheral Identification Register
RapidIO Peripheral Control Register
RapidIO DFT Control 1 Register
RapidIO DFT Control 2 Register
Reserved
RIOPID
02D0 0004
RIO_PCR
02D0 0008
RIO_DFT1
02D0 000C
RIO_DFT2
02D0 0010
-
02D0 0014
-
Reserved
02D0 0018
-
Reserved
02D0 001C
-
Reserved
02D0 0020
RIO_PER_SET_CNTL
RIO_PER_SET_CNTL2
-
RapidIO Peripheral Settings Control Register
RapidIO SerDes Enable PLL Control Register
Reserved
02D0 0024
02D0 0028 - 02D0 002C
02D0 0030
RIO_GBL_EN
RIO_GBL_EN_STAT
RIO_BLK0_EN
RapidIO Peripheral Global Enable Register
RapidIO Peripheral Global Enable Status Register
RapidIO Block0 Enable Register
02D0 0034
02D0 0038
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Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 003C
02D0 0040
02D0 0044
02D0 0048
02D0 004C
02D0 0050
02D0 0054
02D0 0058
02D0 005C
02D0 0060
02D0 0064
02D0 0068
02D0 006C
02D0 0070
02D0 0074
02D0 0078
02D0 007C
02D0 0080
02D0 0084
02D0 0088
02D0 008C
02D0 0090
02D0 0094
02D0 0098
02D0 009C
02D0 00A0
02D0 00A4
02D0 00A8
02D0 00AC
02D0 00B0
02D0 00B4
02D0 00B8
02D0 00BC
02D0 00C0
02D0 00C4
02D0 00C8
02D0 00CC
02D0 00D0
02D0 00D4
02D0 00D8
02D0 00DC
02D0 00E0
02D0 00E4
02D0 00E8
02D0 00EC
02D0 00F0
02D0 00F4
ACRONYM
REGISTER NAME
RapidIO Block0 Enable Status Register
RapidIO Block1 Enable Register
RIO_BLK0_EN_STAT
RIO_BLK1_EN
RIO_BLK1_EN_STAT
RIO_BLK2_EN
RapidIO Block1 Enable Status Register
RapidIO Block2 Enable Register
RIO_BLK2_EN_STAT
RIO_BLK3_EN
RapidIO Block2 Enable Status Register
RapidIO Block3 Enable Register
RIO_BLK3_EN_STAT
RIO_BLK4_EN
RapidIO Block3 Enable Status Register
RapidIO Block4 Enable Register
RIO_BLK4_EN_STAT
RIO_BLK5_EN
RapidIO Block4 Enable Status Register
RapidIO Block5 Enable Register
RIO_BLK5_EN_STAT
RIO_BLK6_EN
RapidIO Block5 Enable Status Register
RapidIO Block6 Enable Register
RIO_BLK6_EN_STAT
RIO_BLK7_EN
RapidIO Block6 Enable Status Register
RapidIO Block7 Enable Register
RIO_BLK7_EN_STAT
RIO_BLK8_EN
RapidIO Block7 Enable Status Register
RapidIO Block8 Enable Register
RIO_BLK8_EN_STAT
RIO_GBL_PD_REQ
RIO_GBL_PD_ACK
RIO_GBL_PD_STAT
RIO_BLK0_PD_REQ
RIO_BLK0_PD_ACK
RIO_BLK0_PD_STAT
RIO_BLK1_PD_REQ
RIO_BLK1_PD_ACK
RIO_BLK1_PD_STAT
RIO_BLK2_PD_REQ
RIO_BLK2_PD_ACK
RIO_BLK2_PD_STAT
RIO_BLK3_PD_REQ
RIO_BLK3_PD_ACK
RIO_BLK3_PD_STAT
RIO_BLK4_PD_REQ
RIO_BLK4_PD_ACK
RIO_BLK4_PD_STAT
RIO_BLK5_PD_REQ
RIO_BLK5_PD_ACK
RIO_BLK5_PD_STAT
RIO_BLK6_PD_REQ
RIO_BLK6_PD_ACK
RIO_BLK6_PD_STAT
RIO_BLK7_PD_REQ
RIO_BLK7_PD_ACK
RIO_BLK7_PD_STAT
RIO_BLK8_PD_REQ
RIO_BLK8_PD_ACK
RIO_BLK8_PD_STAT
RapidIO Block8 Enable Status Register
RapidIO Peripheral Global Powerdown Request Register
RapidIO Peripheral Global Powerdown Acknowledge Register
RapidIO Peripheral Global Powerdown Status Register
RapidIO BLK0 Powerdown Request Register
RapidIO BLK0 Powerdown Acknowledge Register
RapidIO BLK0 Power Down Status Register
RapidIO BLK1 Powerdown Acknowledge Register
RapidIO BLK1 Powerdown Status Register
RapidIO BLK1 Powerdown Status Register
RapidIO BLK2 Powerdown Request Register
RapidIO BLK2 Powerdown Acknowledge Register
RapidIO BLK2 Powerdown Status Register
RapidIO BLK3 Powerdown Request Register
RapidIO BLK3 Powerdown Acknowledge Register
RapidIO BLK3 Powerdown Status Register
RapidIO BLK4 Powerdown Request Register
RapidIO BLK4 Powerdown Acknowledge Register
RapidIO BLK4 Powerdown Status Register
RapidIO BLK5 Powerdown Request Register
RapidIO BLK5 Powerdown Acknowledge Register
RapidIO BLK5 Powerdown Status Register
RapidIO BLK6 Powerdown Request Register
RapidIO BLK6 Powerdown Acknowledge Register
RapidIO BLK6 Powerdown Status Register
RapidIO BLK7 Powerdown Request Register
RapidIO BLK7 Powerdown Acknowledge Register
RapidIO BLK7 Powerdown Status Register
RapidIO BLK8 Powerdown Request Register
RapidIO BLK8 Powerdown Acknowledge Register
RapidIO BLK8 Powerdown Status Register
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Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 00F8 - 02D0 00FC
02D0 0100
ACRONYM
REGISTER NAME
-
Reserved
RIO_SERDES_CFGRX0_CNTL
RapidIO SerDes RX Channel 0 CFG Register
RapidIO SerDes RX Channel 1 CFG Register
RapidIO SerDes RX Channel 2 CFG Register
RapidIO SerDes RX Channel 3 CFG Register
RapidIO SerDes TX Channel 0 CFG Register
RapidIO SerDes TX Channel 1 CFG Register
RapidIO SerDes TX Channel 2 CFG Register
RapidIO SerDes TX Channel 3 CFG Register
RapidIO SerDes Macro 1 CFG Control Register
Reserved
02D0 0104
RIO_SERDES_CFGRX1_CNTL
02D0 0108
RIO_SERDES_CFGRX2_CNTL
02D0 010C
RIO_SERDES_CFGRX3_CNTL
02D0 0110
RIO_SERDES_CFGTX0_CNTL
02D0 0114
RIO_SERDES_CFGTX1_CNTL
02D0 0118
RIO_SERDES_CFGTX2_CNTL
02D0 011C
RIO_SERDES_CFGTX3_CNTL
02D0 0120
RIO_SERDES_CFG1_CNTL
02D0 0124
-
02D0 0128
RIO_SERDES_CFG2_CNTL
RapidIO SerDes Macro 2 CFG Control Register
Reserved
02D0 012C
-
02D0 0130
RIO_SERDES_CFG3_CNTL
RapidIO SerDes Macro 3 CFG Control Register
Reserved
02D0 0134
-
02D0 0138
RIO_SERDES_CFG4_CNTL
RapidIO SerDes Macro 4 CFG Control Register
Reserved
02D0 013C
-
02D0 0140
RIO_SERDES_TESTCFG1_CNTL
RapidIO SerDes Macro 1 TESTCFG Control Register
RapidIO SerDes Macro 2 TESTCFG Control Register
RapidIO SerDes Macro 3 TESTCFG Control Register
RapidIO SerDes Macro 4 TESTCFG Control Register
Reserved
02D0 0144
RIO_SERDES_TESTCFG2_CNTL
02D0 0148
RIO_SERDES_TESTCFG3_CNTL
02D0 014C
RIO_SERDES_TESTCFG4_CNTL
02D0 0150 - 02D0 01FC
02D0 0200
-
RIO_CPU0_ICSR
RapidIO CPU0 Interrupt Status Register
Reserved
02D0 0204
-
02D0 0208
RIO_CPU0_ICCR
RapidIO CPU0 Interrupt Clear Register
Reserved
02D0 020C
-
02D0 0210
RIO_CPU1_ICSR
RapidIO CPU1 Interrupt Status Register
Reserved
02D0 0214
-
02D0 0218
RIO_CPU1_ICCR
RapidIO CPU1 Interrupt Clear Register
Reserved
02D0 021C
-
02D0 0220
RIO_CPU2_ICSR
RapidIO CPU2 Interrupt Status Register
Reserved
02D0 0224
-
02D0 0228
RIO_CPU2_ICCR
RapidIO CPU2 Interrupt Clear Register
Reserved
02D0 022C
-
02D0 0230
RIO_CPU3_ICSR
RapidIO CPU3 Interrupt Status Register
Reserved
02D0 0234
-
02D0 0238
RIO_CPU3_ICCR
RapidIO CPU3 Interrupt Clear Register
Reserved
02D0 023C
-
02D0 0240
RIO_RX_CPPI_ICSR
RapidIO RX CPPI Interrupt Status Register
Reserved
02D0 0244 - 02D0 024C
02D0 0250
-
RIO_TX_CPPI_ICSR
RapidIO TX CPPI Interrupt Status Register
Reserved
02D0 0254 - 02D0 025C
02D0 0260
-
RIO_LSU_ICSR
RapidIO LSU Status Interrupt Register
Reserved
02D0 0264
-
02D0 0268
RIO_LSU _ICCR
-
RapidIO LSU Clear Interrupt Register
Reserved
02D0 026C
214
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Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
RapidIO Error, Reset, and Special Event Status Interrupt
Register
02D0 0270
RIO_ERR_RST_EVNT_ICSR
02D0 0274
02D0 0278
-
RIO_ERR_RST_EVNT_ICCR
-
Reserved
RapidIO Error, Reset, and Special Event Clear Interrupt Register
Reserved
02D0 027C
02D0 0280
RIO_CPU0_ICRR
RIO_CPU0_ICRR2
-
RapidIO CPU0 Interrupt Condition Routing Register
RapidIO CPU0 Interrupt Condition Routing Register 2
Reserved
02D0 0284
02D0 0288 - 02D0 028C
02D0 0290
RIO_CPU1_ICRR
RIO_CPU1_ICRR2
-
RapidIO CPU1 Interrupt Condition Routing Register
RapidIO CPU1 Interrupt Condition Routing Register 2
Reserved
02D0 0294
02D0 0298 - 02D0 029C
02D0 02A0
RIO_CPU2_ICRR
RIO_CPU2_ICRR2
-
RapidIO CPU2 Interrupt Condition Routing Register
RapidIO CPU2 Interrupt Condition Routing Register 2
Reserved
02D0 02A4
02D0 02A8 - 02D0 02AC
02D0 02B0
RIO_CPU3_ICRR
RIO_CPU3_ICRR2
-
RapidIO CPU3 Interrupt Condition Routing Register
RapidIO CPU3 Interrupt Condition Routing Register 2
Reserved
02D0 02B4
02D0 02B8 - 02D0 02BC
02D0 02C0
RIO_RX_CPPI _ICRR
RIO_RX_CPPI _ICRR2
RIO_RX_CPPI _ICRR3
-
RapidIO RX CPPI Interrupt Condition Routing Register
RapidIO RX CPPI Interrupt Condition Routing Register 2
RapidIO RX CPPI Interrupt Condition Routing Register 3
Reserved
02D0 02C4
02D0 02C8
02D0 02CC
02D0 02D0
RIO_TX_CPPI _ICRR
RIO_TX_CPPI _ICRR2
RIO_TX_CPPI _ICRR3
-
RapidIO TX CPPI Interrupt Condition Routing Register
RapidIO TX CPPI Interrupt Condition Routing Register 2
RapidIO TX CPPI Interrupt Condition Routing Register 3
Reserved
02D0 02D4
02D0 02D8
02D0 02DC
02D0 02E0
RIO_LSU_ICRR
RIO_LSU_ICRR2
RIO_LSU_ICRR3
RIO_LSU_ICRR4
RapidIO LSU Module Interrupt Condition Routing Register
RapidIO LSU Module Interrupt Condition Routing Register 2
RapidIO LSU Module Interrupt Condition Routing Register 3
RapidIO LSU Module Interrupt Condition Routing Register 4
02D0 02E4
02D0 02E8
02D0 02EC
RapidIO Error/Reset/special event Interrupt Condition
Routing Register
02D0 02F0
02D0 02F4
02D0 02F8
RIO_ERR_RST_EVNT_ICRR
RIO_ERR_RST_EVNT_ICRR2
RIO_ERR_RST_EVNT_ICRR3
RapidIO Error/Reset/special event Interrupt Condition
Routing Register 2
RapidIO Error/Reset/special event Interrupt Condition
Routing Register 3
02D0 02FC
02D0 0300
02D0 0304
02D0 0308
02D0 030C
02D0 0310
02D0 0314
02D0 0318
02D0 031C
02D0 0320
02D0 0324
02D0 0328
02D0 032C
-
Reserved
RIO_INTDST0_Decode
RIO_INTDST1_Decode
RIO_INTDST2_Decode
RIO_INTDST3_Decode
RIO_INTDST4_Decode
RIO_INTDST5_Decode
RIO_INTDST6_Decode
RIO_INTDST7_Decode
RIO_INTDST0_Rate_CNTL
RIO_INTDST1_Rate_CNTL
RIO_INTDST2_Rate_CNTL
RIO_INTDST3_Rate_CNTL
RapidIO INTDST0 Interrupt Status Decode Register
RapidIO INTDST1 Interrupt Status Decode Register
RapidIO INTDST2 Interrupt Status Decode Register
RapidIO INTDST3 Interrupt Status Decode Register
RapidIO INTDST4 Interrupt Status Decode Register
RapidIO INTDST5 Interrupt Status Decode Register
RapidIO INTDST6 Interrupt Status Decode Register
RapidIO INTDST7 Interrupt Status Decode Register
RapidIO INTDST0 Interrupt Rate Control Register
RapidIO INTDST1 Interrupt Rate Control Register
RapidIO INTDST2 Interrupt Rate Control Register
RapidIO INTDST3 Interrupt Rate Control Register
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Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0330
02D0 0334
02D0 0338
02D0 033C
02D0 0340 - 02D0 03FC
02D0 0400
02D0 0404
02D0 0408
02D0 040C
02D0 0410
02D0 0414
02D0 0418
02D0 041C
02D0 0420
02D0 0424
02D0 0428
02D0 042C
02D0 0430
02D0 0434
02D0 0438
02D0 043C
02D0 0440
02D0 0444
02D0 0448
02D0 044C
02D0 0450
02D0 0454
02D0 0458
02D0 045C
02D0 0460
02D0 0464
02D0 0468
02D0 046C
02D0 0470
02D0 0474
02D0 0478
02D0 047C
02D0 0480 - 02D0 04FC
02D0 0500
02D0 0504
02D0 0508
02D0 050C
02D0 0510
02D0 0514
02D0 0518
02D0 051C
02D0 0520
ACRONYM
RIO_INTDST4_Rate_CNTL
RIO_INTDST5_Rate_CNTL
RIO_INTDST6_Rate_CNTL
RIO_INTDST7_Rate_CNTL
-
REGISTER NAME
RapidIO INTDST4 Interrupt Rate Control Register
RapidIO INTDST5 Interrupt Rate Control Register
RapidIO INTDST6 Interrupt Rate Control Register
RapidIO INTDST7 Interrupt Rate Control Register
Reserved
RIO_LSU1_Reg0
RapidIO LSU1 Control Reg0 Register
RapidIO LSU1 Control Reg1 Register
RapidIO LSU1 Control Reg2 Register
RapidIO LSU1 Control Reg3 Register
RapidIO LSU1 Control Reg4 Register
RapidIO LSU1 Command Reg5 Register
RapidIO LSU1 Status Reg6 Register
RIO_LSU1_Reg1
RIO_LSU1_Reg2
RIO_LSU1_Reg3
RIO_LSU1_Reg4
RIO_LSU1_Reg5
RIO_LSU1_Reg6
RIO_LSU1_FLOW_MASKS
RIO_LSU2_Reg0
RapidIO Core0 LSU Congestion Control Flow Mask Register
RapidIO LSU2 Control Reg0 Register
RIO_LSU2_Reg1
RapidIO LSU2 Control Reg1 Register
RIO_LSU2_Reg2
RapidIO LSU2 Control Reg2 Register
RIO_LSU2_Reg3
RapidIO LSU2 Control Reg3 Register
RIO_LSU2_Reg4
RapidIO LSU2 Control Reg4 Register
RIO_LSU2_Reg5
RapidIO LSU2 Command Reg5 Register
RIO_LSU2_Reg6
RapidIO LSU2 Status Reg6 Register
RIO_LSU2_FLOW_MASKS
RIO_LSU3_Reg0
RapidIO Core1 LSU Congestion Control Flow Mask Register
RapidIO LSU3 Control Reg0 Register
RIO_LSU3_Reg1
RapidIO LSU3 Control Reg1 Register
RIO_LSU3_Reg2
RapidIO LSU3 Control Reg2 Register
RIO_LSU3_Reg3
RapidIO LSU3 Control Reg3 Register
RIO_LSU3_Reg4
RapidIO LSU3 Control Reg4 Register
RIO_LSU3_Reg5
RapidIO LSU3 Command Reg5 Register
RIO_LSU3_Reg6
RapidIO LSU3 Status Reg6 Register
RIO_LSU3_FLOW_MASKS
RIO_LSU4_Reg0
RapidIO Core2 LSU Congestion Control Flow Mask Register
RapidIO LSU4 Control Reg0 Register
RIO_LSU4_Reg1
RapidIO LSU4 Control Reg1 Register
RIO_LSU4_Reg2
RapidIO LSU4 Control Reg2 Register
RIO_LSU4_Reg3
RapidIO LSU4 Control Reg3 Register
RIO_LSU4_Reg4
RapidIO LSU4 Control Reg4 Register
RIO_LSU4_Reg5
RapidIO LSU4 Command Reg5 Register
RIO_LSU4_Reg6
RapidIO LSU4 Status Reg6 Register
RIO_LSU4_FLOW_MASKS
-
RapidIO Core3 LSU Congestion Control Flow Mask Register
Reserved
RIO_Queue0_TxDMA_HDP
RIO_Queue1_TxDMA_HDP
RIO_Queue2_TxDMA_HDP
RIO_Queue3_TxDMA_HDP
RIO_Queue4_TxDMA_HDP
RIO_Queue5_TxDMA_HDP
RIO_Queue6_TxDMA_HDP
RIO_Queue7_TxDMA_HDP
RIO_Queue8_TxDMA_HDP
RapidIO Queue0 TX DMA Head Descriptor Pointer Register
RapidIO Queue1 TX DMA Head Descriptor Pointer Register
RapidIO Queue2 TX DMA Head Descriptor Pointer Register
RapidIO Queue3 TX DMA Head Descriptor Pointer Register
RapidIO Queue4 TX DMA Head Descriptor Pointer Register
RapidIO Queue5 TX DMA Head Descriptor Pointer Register
RapidIO Queue6 TX DMA Head Descriptor Pointer Register
RapidIO Queue7 TX DMA Head Descriptor Pointer Register
RapidIO Queue8 TX DMA Head Descriptor Pointer Register
216
C64x+ Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0524
02D0 0528
02D0 052C
02D0 0530
02D0 0534
02D0 0538
02D0 053C
02D0 0540
02D0 0544
02D0 0548
02D0 054C
02D0 0550 - 02D0 057C
02D0 0580
02D0 0584
02D0 0588
02D0 058C
02D0 0590
02D0 0594
02D0 0598
02D0 059C
02D0 05A0
02D0 05A4
02D0 05A8
02D0 05AC
02D0 05B0
02D0 05B4
02D0 05B8
02D0 05BC
02D0 05C0
02D0 05C4
02D0 05C8
02D0 05CC
02D0 05D0 - 02D0 05FC
02D0 0600
02D0 0604
02D0 0608
02D0 060C
02D0 0610
02D0 0614
02D0 0618
02D0 061C
02D0 0620
02D0 0624
02D0 0628
02D0 062C
02D0 0630
02D0 0634
ACRONYM
REGISTER NAME
RIO_Queue9_TxDMA_HDP
RIO_Queue10_TxDMA_HDP
RIO_Queue11_TxDMA_HDP
RIO_Queue12_TxDMA_HDP
RIO_Queue13_TxDMA_HDP
RIO_Queue14_TxDMA_HDP
RIO_Queue15_TxDMA_HDP
RIO_Queue16_TxDMA_HDP
RIO_Queue17_TxDMA_HDP
RIO_Queue18_TxDMA_HDP
RIO_Queue19_TxDMA_HDP
-
RapidIO Queue9 TX DMA Head Descriptor Pointer Register
RapidIO Queue10 TX DMA Head Descriptor Pointer Register
RapidIO Queue11 TX DMA Head Descriptor Pointer Register
RapidIO Queue12 TX DMA Head Descriptor Pointer Register
RapidIO Queue13 TX DMA Head Descriptor Pointer Register
RapidIO Queue14 TX DMA Head Descriptor Pointer Register
RapidIO Queue15 TX DMA Head Descriptor Pointer Register
RapidIO Queue16 TX DMA Head Descriptor Pointer Register
RapidIO Queue17 TX DMA Head Descriptor Pointer Register
RapidIO Queue18 TX DMA Head Descriptor Pointer Register
RapidIO Queue19 TX DMA Head Descriptor Pointer Register
Reserved
RIO_Queue0_TxDMA_CP
RIO_Queue1_TxDMA_CP
RIO_Queue2_TxDMA_CP
RIO_Queue3_TxDMA_CP
RIO_Queue4_TxDMA_CP
RIO_Queue5_TxDMA_CP
RIO_Queue6_TxDMA_CP
RIO_Queue7_TxDMA_CP
RIO_Queue8_TxDMA_CP
RIO_Queue9_TxDMA_CP
RIO_Queue10_TxDMA_CP
RIO_Queue11_TxDMA_CP
RIO_Queue12_TxDMA_CP
RIO_Queue13_TxDMA_CP
RIO_Queue14_TxDMA_CP
RIO_Queue15_TxDMA_CP
RIO_Queue16_TxDMA_CP
RIO_Queue17_TxDMA_CP
RIO_Queue18_TxDMA_CP
RIO_Queue19_TxDMA_CP
-
RapidIO Queue0 TX DMA Completion Pointer Register
RapidIO Queue1 TX DMA Completion Pointer Register
RapidIO Queue2 TX DMA Completion Pointer Register
RapidIO Queue3 TX DMA Completion Pointer Register
RapidIO Queue4 TX DMA Completion Pointer Register
RapidIO Queue5 TX DMA Completion Pointer Register
RapidIO Queue6 TX DMA Completion Pointer Register
RapidIO Queue7 TX DMA Completion Pointer Register
RapidIO Queue8 TX DMA Completion Pointer Register
RapidIO Queue9 TX DMA Completion Pointer Register
RapidIO Queue10 TX DMA Completion Pointer Register
RapidIO Queue11 TX DMA Completion Pointer Register
RapidIO Queue12 TX DMA Completion Pointer Register
RapidIO Queue13 TX DMA Completion Pointer Register
RapidIO Queue14 TX DMA Completion Pointer Register
RapidIO Queue15 TX DMA Completion Pointer Register
RapidIO Queue16 TX DMA Completion Pointer Register
RapidIO Queue17 TX DMA Completion Pointer Register
RapidIO Queue18 TX DMA Completion Pointer Register
RapidIO Queue19 TX DMA Completion Pointer Register
Reserved
RIO_Queue0_RxDMA_HDP
RIO_Queue1_RxDMA_HDP
RIO_Queue2_RxDMA_HDP
RIO_Queue3_RxDMA_HDP
RIO_Queue4_RxDMA_HDP
RIO_Queue5_RxDMA_HDP
RIO_Queue6_RxDMA_HDP
RIO_Queue7_RxDMA_HDP
RIO_Queue8_RxDMA_HDP
RIO_Queue9_RxDMA_HDP
RIO_Queue10_RxDMA_HDP
RIO_Queue11_RxDMA_HDP
RIO_Queue12_RxDMA_HDP
RIO_Queue13_RxDMA_HDP
RapidIO Queue0 RX DMA Head Descriptor Pointer Register
RapidIO Queue1 RX DMA Head Descriptor Pointer Register
RapidIO Queue2 RX DMA Head Descriptor Pointer Register
RapidIO Queue3 RX DMA Head Descriptor Pointer Register
RapidIO Queue4 RX DMA Head Descriptor Pointer Register
RapidIO Queue5 RX DMA Head Descriptor Pointer Register
RapidIO Queue6 RX DMA Head Descriptor Pointer Register
RapidIO Queue7 RX DMA Head Descriptor Pointer Register
RapidIO Queue8 RX DMA Head Descriptor Pointer Register
RapidIO Queue9 RX DMA Head Descriptor Pointer Register
RapidIO Queue10 RX DMA Head Descriptor Pointer Register
RapidIO Queue11 RX DMA Head Descriptor Pointer Register
RapidIO Queue12 RX DMA Head Descriptor Pointer Register
RapidIO Queue13 RX DMA Head Descriptor Pointer Register
C64x+ Peripheral Information and Electrical Specifications
217
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0638
ACRONYM
REGISTER NAME
RIO_Queue14_RxDMA_HDP
RIO_Queue15_RxDMA_HDP
RIO_Queue16_RxDMA_HDP
RIO_Queue17_RxDMA_HDP
RIO_Queue18_RxDMA_HDP
RIO_Queue19_RxDMA_HDP
-
RapidIO Queue14 RX DMA Head Descriptor Pointer Register
RapidIO Queue15 RX DMA Head Descriptor Pointer Register
RapidIO Queue16 RX DMA Head Descriptor Pointer Register
RapidIO Queue17 RX DMA Head Descriptor Pointer Register
RapidIO Queue18 RX DMA Head Descriptor Pointer Register
RapidIO Queue19 RX DMA Head Descriptor Pointer Register
Reserved
02D0 063C
02D0 0640
02D0 0644
02D0 0648
02D0 064C
02D0 0650 - 02D0 067C
02D0 0680
RIO_Queue0_RxDMA_CP
RIO_Queue1_RxDMA_CP
RIO_Queue2_RxDMA_CP
RIO_Queue3_RxDMA_CP
RIO_Queue4_RxDMA_CP
RIO_Queue5_RxDMA_CP
RIO_Queue6_RxDMA_CP
RIO_Queue7_RxDMA_CP
RIO_Queue8_RxDMA_CP
RIO_Queue9_RxDMA_CP
RIO_Queue10_RxDMA_CP
RIO_Queue11_RxDMA_CP
RIO_Queue12_RxDMA_CP
RIO_Queue13_RxDMA_CP
RIO_Queue14_RxDMA_CP
RIO_Queue15_RxDMA_CP
RIO_Queue16_RxDMA_CP
RIO_Queue17_RxDMA_CP
RIO_Queue18_RxDMA_CP
RIO_Queue19_RxDMA_CP
-
RapidIO Queue0 RX DMA Completion Pointer Register
RapidIO Queue1 RX DMA Completion Pointer Register
RapidIO Queue2 RX DMA Completion Pointer Register
RapidIO Queue3 RX DMA Completion Pointer Register
RapidIO Queue4 RX DMA Completion Pointer Register
RapidIO Queue5 RX DMA Completion Pointer Register
RapidIO Queue6 RX DMA Completion Pointer Register
RapidIO Queue7 RX DMA Completion Pointer Register
RapidIO Queue8 RX DMA Completion Pointer Register
RapidIO Queue9 RX DMA Completion Pointer Register
RapidIO Queue10 RX DMA Completion Pointer Register
RapidIO Queue11 RX DMA Completion Pointer Register
RapidIO Queue12 RX DMA Completion Pointer Register
RapidIO Queue13 RX DMA Completion Pointer Register
RapidIO Queue14 RX DMA Completion Pointer Register
RapidIO Queue15 RX DMA Completion Pointer Register
RapidIO Queue16 RX DMA Completion Pointer Register
RapidIO Queue17 RX DMA Completion Pointer Register
RapidIO Queue18 RX DMA Completion Pointer Register
RapidIO Queue19 RX DMA Completion Pointer Register
Reserved
02D0 0684
02D0 0688
02D0 068C
02D0 0690
02D0 0694
02D0 0698
02D0 069C
02D0 06A0
02D0 06A4
02D0 06A8
02D0 06AC
02D0 06B0
02D0 06B4
02D0 06B8
02D0 06BC
02D0 06C0
02D0 06C4
02D0 06C8
02D0 06CC
02D0 06D0 - 02D0 06FC
02D0 0700
RIO_TX_QUEUE_TEAR_DOWN
RIO_TX_CPPI_FLOW_MASKS0
RIO_TX_CPPI_FLOW_MASKS1
RIO_TX_CPPI_FLOW_MASKS2
RIO_TX_CPPI_FLOW_MASKS3
RIO_TX_CPPI_FLOW_MASKS4
-
RapidIO TX Queue Teardown Register
02D0 0704
RapidIO TX CPPI Supported Flow Masks 0 Register
RapidIO TX CPPI Supported Flow Masks 1 Register
RapidIO TX CPPI Supported Flow Masks 2 Register
RapidIO TX CPPI Supported Flow Masks 3 Register
RapidIO TX CPPI Supported Flow Masks 4 Register
Reserved
02D0 0708
02D0 070C
02D0 0710
02D0 0714
02D0 0718 - 02D0 073C
02D0 0740
RIO_RX_QUEUE_TEAR_DOWN
RIO_RX_CPPI_CNTL
RapidIO RX Queue Teardown Register
02D0 0744
RapidIO RX CPPI Control Register
02D0 0748 - 02D0 077C
02D0 0780
-
Reserved
RIO_RXU _MMBX0_MAP1
RIO_RXU _MMBX0_MAP2
RIO_RXU _MMBX0_MAP3
RIO_RXU _MMBX0_MAP4
RIO_RXU _MMBX1_MAP1
RIO_RXU _MMBX1_MAP2
RIO_RXU _MMBX1_MAP3
RIO_RXU _MMBX1_MAP4
RIO_RXU _MMBX2_MAP1
RapidIO Multi-Segment 0 Message to Queue Map 1 Register
RapidIO Multi-Segment 0 Message to Queue Map 2 Register
RapidIO Multi-Segment 0 Message to Queue Map 3 Register
RapidIO Multi-Segment 0 Message to Queue Map 4 Register
RapidIO Multi-Segment 1 Message to Queue Map 1 Register
RapidIO Multi-Segment 1 Message to Queue Map 2 Register
RapidIO Multi-Segment 1 Message to Queue Map 3 Register
RapidIO Multi-Segment 1 Message to Queue Map 4 Register
RapidIO Multi-Segment 2 Message to Queue Map 1 Register
02D0 0784
02D0 0788
02D0 078C
02D0 0790
02D0 0794
02D0 0798
02D0 079C
02D0 07A0
218
C64x+ Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 07A4
02D0 07A8
02D0 07AC
02D0 07B0
02D0 07B4
02D0 07B8
02D0 07BC
02D0 07C0 - 02D0 07DC
02D0 07E0
02D0 07E4
02D0 07E8
02D0 07EC
02D0 07F0 - 02D0 07FC
02D0 0800
02D0 0804
02D0 0808
02D0 080C
02D0 0810
02D0 0814
02D0 0818
02D0 081C
02D0 0820
02D0 0824
02D0 0828
02D0 082C
02D0 0830
02D0 0834
02D0 0838
02D0 083C
02D0 0840
02D0 0844
02D0 0848
02D0 084C
02D0 0850
02D0 0854
02D0 0858
02D0 085C
02D0 0860
02D0 0864
02D0 0868
02D0 086C
02D0 0870
02D0 0874
02D0 0878
02D0 087C
02D0 0880
02D0 0884
ACRONYM
REGISTER NAME
RIO_RXU _MMBX2_MAP2
RIO_RXU _MMBX2_MAP3
RIO_RXU _MMBX2_MAP4
RIO_RXU _MMBX3_MAP1
RIO_RXU _MMBX3_MAP2
RIO_RXU _MMBX3_MAP3
RIO_RXU _MMBX3_MAP4
-
RapidIO Multi-Segment 2 Message to Queue Map 2 Register
RapidIO Multi-Segment 2 Message to Queue Map 3 Register
RapidIO Multi-Segment 2 Message to Queue Map 4 Register
RapidIO Multi-Segment 3 Message to Queue Map 1 Register
RapidIO Multi-Segment 3 Message to Queue Map 2 Register
RapidIO Multi-Segment 3 Message to Queue Map 3 Register
RapidIO Multi-Segment 3 Message to Queue Map 4 Register
Reserved
RIO_TX_QUEUE_CNTL0
RIO_TX_QUEUE_CNTL1
RIO_TX_QUEUE_CNTL2
RIO_TX_QUEUE_CNTL3
-
RapidIO TX Queue Control 0 Register TBD
RapidIO TX Queue Control 1 Register
RapidIO TX Queue Control 2 Register
RapidIO TX Queue Control 3 Register
Reserved
RIO_RXU_SMBX00_MAP
RIO_RXU_SMBX01_MAP
RIO_RXU_SMBX02_MAP
RIO_RXU_SMBX03_MAP
RIO_RXU_SMBX04_MAP
RIO_RXU_SMBX05_MAP
RIO_RXU_SMBX06_MAP
RIO_RXU_SMBX07_MAP
RIO_RXU_SMBX08_MAP
RIO_RXU_SMBX09_MAP
RIO_RXU_SMBX10_MAP
RIO_RXU_SMBX11_MAP
RIO_RXU_SMBX12_MAP
RIO_RXU_SMBX13_MAP
RIO_RXU_SMBX14_MAP
RIO_RXU_SMBX15_MAP
RIO_RXU_SMBX16_MAP
RIO_RXU_SMBX17_MAP
RIO_RXU_SMBX18_MAP
RIO_RXU_SMBX19_MAP
RIO_RXU_SMBX20_MAP
RIO_RXU_SMBX21_MAP
RIO_RXU_SMBX22_MAP
RIO_RXU_SMBX23_MAP
RIO_RXU_SMBX24_MAP
RIO_RXU_SMBX25_MAP
RIO_RXU_SMBX26_MAP
RIO_RXU_SMBX27_MAP
RIO_RXU_SMBX28_MAP
RIO_RXU_SMBX29_MAP
RIO_RXU_SMBX30_MAP
RIO_RXU_SMBX31_MAP
RIO_RXU_SMBX32_MAP
RIO_RXU_SMBX33_MAP
RapidIO Single-Segment 00 Message to Queue Map Register
RapidIO Single-Segment 01 Message to Queue Map Register
RapidIO Single-Segment 02 Message to Queue Map Register
RapidIO Single-Segment 03 Message to Queue Map Register
RapidIO Single-Segment 04 Message to Queue Map Register
RapidIO Single-Segment 05 Message to Queue Map Register
RapidIO Single-Segment 06 Message to Queue Map Register
RapidIO Single-Segment 07 Message to Queue Map Register
RapidIO Single-Segment 08 Message to Queue Map Register
RapidIO Single-Segment 09 Message to Queue Map Register
RapidIO Single-Segment 10 Message to Queue Map Register
RapidIO Single-Segment 11 Message to Queue Map Register
RapidIO Single-Segment 12 Message to Queue Map Register
RapidIO Single-Segment 13 Message to Queue Map Register
RapidIO Single-Segment 14 Message to Queue Map Register
RapidIO Single-Segment 15 Message to Queue Map Register
RapidIO Single-Segment 16 Message to Queue Map Register
RapidIO Single-Segment 17 Message to Queue Map Register
RapidIO Single-Segment 18 Message to Queue Map Register
RapidIO Single-Segment 19 Message to Queue Map Register
RapidIO Single-Segment 20 Message to Queue Map Register
RapidIO Single-Segment 21 Message to Queue Map Register
RapidIO Single-Segment 22 Message to Queue Map Register
RapidIO Single-Segment 23 Message to Queue Map Register
RapidIO Single-Segment 24 Message to Queue Map Register
RapidIO Single-Segment 25 Message to Queue Map Register
RapidIO Single-Segment 26 Message to Queue Map Register
RapidIO Single-Segment 27 Message to Queue Map Register
RapidIO Single-Segment 28 Message to Queue Map Register
RapidIO Single-Segment 29 Message to Queue Map Register
RapidIO Single-Segment 30 Message to Queue Map Register
RapidIO Single-Segment 31 Message to Queue Map Register
RapidIO Single-Segment 32 Message to Queue Map Register
RapidIO Single-Segment 33 Message to Queue Map Register
C64x+ Peripheral Information and Electrical Specifications
219
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 0888
02D0 088C
02D0 0890
02D0 0894
02D0 0898
02D0 089C
02D0 08A0
02D0 08A4
02D0 08A8
02D0 08AC
02D0 08B0
02D0 08B4
02D0 08B8
02D0 08BC
02D0 08C0
02D0 08C4
02D0 08C8
02D0 08CC
02D0 08D0
02D0 08D4
02D0 08D8
02D0 08DC
02D0 08E0
02D0 08E4
02D0 08E8
02D0 08EC
02D0 08F0
02D0 08F4
02D0 08F8
02D0 08FC
02D0 0900
02D0 0904
02D0 0908
02D0 090C
02D0 0910
02D0 0914
02D0 0918
02D0 091C
ACRONYM
REGISTER NAME
RIO_RXU_SMBX34_MAP
RIO_RXU_SMBX35_MAP
RIO_RXU_SMBX36_MAP
RIO_RXU_SMBX37_MAP
RIO_RXU_SMBX38_MAP
RIO_RXU_SMBX39_MAP
RIO_RXU_SMBX40_MAP
RIO_RXU_SMBX41_MAP
RIO_RXU_SMBX42_MAP
RIO_RXU_SMBX43_MAP
RIO_RXU_SMBX44_MAP
RIO_RXU_SMBX45_MAP
RIO_RXU_SMBX46_MAP
RIO_RXU_SMBX47_MAP
RIO_RXU_SMBX48_MAP
RIO_RXU_SMBX49_MAP
RIO_RXU_SMBX50_MAP
RIO_RXU_SMBX51_MAP
RIO_RXU_SMBX52_MAP
RIO_RXU_SMBX53_MAP
RIO_RXU_SMBX54_MAP
RIO_RXU_SMBX55_MAP
RIO_RXU_SMBX56_MAP
RIO_RXU_SMBX57_MAP
RIO_RXU_SMBX58_MAP
RIO_RXU_SMBX59_MAP
RIO_RXU_SMBX60_MAP
RIO_RXU_SMBX61_MAP
RIO_RXU_SMBX62_MAP
RIO_RXU_SMBX63_MAP
RIO_FLOW_CNTL0
RapidIO Single-Segment 34 Message to Queue Map Register
RapidIO Single-Segment 35 Message to Queue Map Register
RapidIO Single-Segment 36 Message to Queue Map Register
RapidIO Single-Segment 37 Message to Queue Map Register
RapidIO Single-Segment 38 Message to Queue Map Register
RapidIO Single-Segment 39 Message to Queue Map Register
RapidIO Single-Segment 40 Message to Queue Map Register
RapidIO Single-Segment 41 Message to Queue Map Register
RapidIO Single-Segment 42 Message to Queue Map Register
RapidIO Single-Segment 43 Message to Queue Map Register
RapidIO Single-Segment 44 Message to Queue Map Register
RapidIO Single-Segment 45 Message to Queue Map Register
RapidIO Single-Segment 46 Message to Queue Map Register
RapidIO Single-Segment 47 Message to Queue Map Register
RapidIO Single-Segment 48 Message to Queue Map Register
RapidIO Single-Segment 49 Message to Queue Map Register
RapidIO Single-Segment 50 Message to Queue Map Register
RapidIO Single-Segment 51 Message to Queue Map Register
RapidIO Single-Segment 52 Message to Queue Map Register
RapidIO Single-Segment 53 Message to Queue Map Register
RapidIO Single-Segment 54 Message to Queue Map Register
RapidIO Single-Segment 55 Message to Queue Map Register
RapidIO Single-Segment 56 Message to Queue Map Register
RapidIO Single-Segment 57 Message to Queue Map Register
RapidIO Single-Segment 58 Message to Queue Map Register
RapidIO Single-Segment 59 Message to Queue Map Register
RapidIO Single-Segment 60 Message to Queue Map Register
RapidIO Single-Segment 61 Message to Queue Map Register
RapidIO Single-Segment 62 Message to Queue Map Register
RapidIO Single-Segment 63 Message to Queue Map Register
RapidIO Flow Control Table Entry Register0
RIO_FLOW_CNTL1
RapidIO Flow Control Table Entry Register1
RIO_FLOW_CNTL2
RapidIO Flow Control Table Entry Register2
RIO_FLOW_CNTL3
RapidIO Flow Control Table Entry Register3
RIO_FLOW_CNTL4
RapidIO Flow Control Table Entry Register4
RIO_FLOW_CNTL5
RapidIO Flow Control Table Entry Register5
RIO_FLOW_CNTL6
RapidIO Flow Control Table Entry Register6
RIO_FLOW_CNTL7
RapidIO Flow Control Table Entry Register7
RapidIO Peripheral-Specific Registers
02D0 0920 - 02D0 0FFC
02D0 1000
-
Reserved
RIO_DEV_ID
RapidIO Device Identity CAR Register
RapidIO Device Information CAR Register
RapidIO Assembly Identity CAR Register
RapidIO Assembly Information CAR Register
RapidIO Processing Element Features CAR Register
RapidIO Switch Port Information CAR Register
RapidIO Source Operations CAR Register
02D0 1004
RIO_DEV_INFO
RIO_ASBLY_ID
RIO_ASBLY_INFO
RIO_PE_FEAT
RIO_SW_PORT
RIO_SRC_OP
02D0 1008
02D0 100C
02D0 1010
02D0 1014
02D0 1018
220
C64x+ Peripheral Information and Electrical Specifications
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 101C
ACRONYM
REGISTER NAME
RIO_DEST_OP
RapidIO Destination Operations CAR Register
02D0 1020 - 02D0 1038
02D0 1040
-
-
-
Reserved
Reserved
Reserved
02D0 1044 - 02D0 1048
RapidIO Processing Element Logical Layer Control CSR
Register
02D0 104C
02D0 1050
02D0 1058
RIO_PE_LL_CTL
-
Reserved
RapidIO Local Configuration Space Base Address 0 CSR
Register
RIO_LCL_CFG_HBAR
RapidIO Local Configuration Space Base Address 1 CSR
Register
02D0 105C
RIO_LCL_CFG_BAR
02D0 1060
02D0 1064
RIO_BASE_ID
RapidIO Base Device ID CSR Register
Reserved
-
02D0 1068
RIO_ HOST_BASE_ID_LOCK
RapidIO Host Base Device ID Lock CSR Register
RapidIO Component Tag CSR Register
Reserved
02D0 106C
RIO_ COMP_TAG
02D0 1070 - 02D0 10F8
02D0 10FC
-
-
Reserved
RapidIO Extended Features - LP Serial Registers
RapidIO 1x/4x LP-Serial Port Maintenance Block Header
Register
02D0 1100
RIO_ SP_MB_HEAD
02D0 1104 - 02D0 1118
02D0 111C
-
Reserved
-
Reserved
02D0 1120
RIO_SP_LT_CTL
RapidIO Port Link Time-Out Control CSR Register
RapidIO Port Response Time-Out Control CSR Register
Reserved
02D0 1124
RIO_SP_RT_CTL
02D0 1128
-
02D0 112C
-
Reserved
02D0 1130 -02D0 1138
02D0 113C
-
Reserved
RIO_SP_GEN_CTL
RIO_SP0_LM_REQ
RIO_SP0_LM_RESP
RIO_SP0_ACKID_STAT
-
RapidIO Port General Control CSR Register
RapidIO Port 0 Link Maintenance Request CSR Register
RapidIO Port 0 Link Maintenance Response CSR Register
RapidIO Port 0 Local AckID Status CSR Register
Reserved
02D0 1140
02D0 1144
02D0 1148
02D0 114C - 02D0 1150
02D0 1154
-
Reserved
02D0 1158
RIO_SP0_ERR_STAT
RIO_SP0_CTL
RIO_SP1_LM_REQ
RIO_SP1_LM_RESP
RIO_SP1_ACKID_STAT
-
RapidIO Port 0 Error and Status CSR Register
RapidIO Port 0 Control CSR Register
RapidIO Port 1 Link Maintenance Request CSR Register
RapidIO Port 1 Link Maintenance Response CSR Register
RapidIO Port 1 Local AckID Status CSR Register
Reserved
02D0 115C
02D0 1160
02D0 1164
02D0 1168
02D0 116C- 02D0 1170
02D0 1174
-
Reserved
02D0 1178
RIO_SP1_ERR_STAT
RIO_SP1_CTL
RIO_SP2_LM_REQ
RIO_SP2_LM_RESP
RIO_SP2_ACKID_STAT
-
RapidIO Port 1 Error and Status CSR Register
RapidIO Port 1 Control CSR Register
RapidIO Port 2 Link Maintenance Request CSR Register
RapidIO Port 2 Link Maintenance Response CSR Register
RapidIO Port 2 Local AckID Status CSR Register
Reserved
02D0 117C
02D0 1180
02D0 1184
02D0 1188
02D0 118C - 02D0 1190
02D0 1194
-
Reserved
02D0 1198
RIO_SP2_ERR_STAT
RapidIO Port 2 Error and Status CSR Register
C64x+ Peripheral Information and Electrical Specifications
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Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 119C
ACRONYM
REGISTER NAME
RIO_SP2_CTL
RapidIO Port 2 Control CSR Register
02D0 11A0
RIO_SP3_LM_REQ
RapidIO Port 3 Link Maintenance Request CSR Register
RapidIO Port 3 Link Maintenance Response CSR Register
RapidIO Port 3 Local AckID Status CSR Register
Reserved
02D0 11A4
RIO_SP3_LM_RESP
02D0 11A8
RIO_SP3_ACKID_STAT
02D0 11AC - 02D0 11B0
02D0 11B4
-
-
RIO_SP3_ERR_STAT
RIO_SP3_CTL
-
Reserved
02D0 11B8
RapidIO Port 3 Error and Status CSR Register
RapidIO Port 3 Control CSR Register
Reserved
02D0 11BC
02D0 11C0 - 02D0 1FFC
RapidIO Extended Feature - Error Management Registers
02D0 2000
02D0 2004
02D0 2008
02D0 200C
RIO_ERR_RPT_BH
-
RapidIO Error Reporting Block Header Register
Reserved
RIO_ERR_DET
RIO_ERR_EN
RapidIO Logical/Transport Layer Error Detect CSR Register
RapidIO Logical/Transport Layer Error Enable CSR Register
RapidIO Logical/Transport Layer High Address Capture CSR
Register
02D0 2010
02D0 2014
02D0 2018
RIO_H_ADDR_CAPT
RIO_ADDR_CAPT
RIO_ID_CAPT
RapidIO Logical/Transport Layer Address Capture CSR Register
RapidIO Logical/Transport Layer Device ID Capture CSR
Register
02D0 201C
02D0 2020 - 02D0 2024
02D0 2028
RIO_CTRL_CAPT
-
RapidIO Logical/Transport Layer Control Capture CSR Register
Reserved
RIO_PW_TGT_ID
RIO_PKT_TIME_LIVE
-
RapidIO Port-Write Target Device ID CSR Register
RapidIO Packet Time-to-Live CSR Register
Reserved
02D0 202C
02D0 2030 - 02D0 203C
02D0 2040
RIO_SP0_ERR_DET
RIO_SP0_RATE_EN
RapidIO Port 0 Error Detect CSR Register
RapidIO Port 0 Error Enable CSR Register
02D0 2044
02D0 2048
RIO_SP0_ERR_ATTR_CAPT_DBG0 RapidIO Port 0 Attributes Error Capture CSR Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR0
02D0 204C
02D0 2050
02D0 2054
02D0 2058
RIO_SP0_ERR_CAPT_0_DBG1
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR1
RIO_SP0_ERR_CAPT_1_DBG2
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR2
RIO_SP0_ERR_CAPT_2_DBG3
Register
RapidIO Port 0 Packet/Control Symbol Error Capture CSR3
RIO_SP0_ERR_CAPT_3_DBG4
Register
02D0 205C - 02D0 2064
02D0 2068
-
Reserved
RIO_SP0_ERR_RATE
RIO_SP0_ERR_THRESH
-
RapidIO Port 0 Error Rate CSR Register
RapidIO Port 0 Error Rate Threshold CSR Register
Reserved
02D0 206C
02D0 2070 - 02D0 207C
02D0 2080
RIO_SP1_ERR_DET
RIO_SP1_RATE_EN
RIO_SP1_ERR_ATTR_CAPT
RapidIO Port 1 Error Detect CSR Register
RapidIO Port 1 Error Enable CSR Register
RapidIO Port 1 Attributes Error Capture CSR Register
02D0 2084
02D0 2088
RapidIO Port 1 Packet/Control Symbol Error Capture CSR0
Register
02D0 208C
02D0 2090
02D0 2094
02D0 2098
RIO_SP1_ERR_CAPT_0
RIO_SP1_ERR_CAPT_1
RIO_SP1_ERR_CAPT_2
RIO_SP1_ERR_CAPT_3
RapidIO Port 1 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 1 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 1 Packet/Control Symbol Error Capture CSR3
Register
222
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 209C - 02D0 20A4
02D0 20A8
ACRONYM
-
REGISTER NAME
Reserved
RIO_SP1_ERR_RATE
RIO_SP1_ERR_THRESH
-
RapidIO Port 1 Error Rate CSR Register
RapidIO Port 1 Error Rate Threshold CSR Register
Reserved
02D0 20AC
02D0 20B0 - 02D0 20BC
02D0 20C0
RIO_SP2_ERR_DET
RIO_SP2_RATE_EN
RIO_SP2_ERR_ATTR_CAPT
RapidIO Port 2 Error Detect CSR Register
RapidIO Port 2 Error Enable CSR Register
RapidIO Port 2 Attributes Error Capture CSR Register
02D0 20C4
02D0 20C8
RapidIO Port 2 Packet/Control Symbol Error Capture CSR0
Register
02D0 20CC
02D0 20D0
02D0 20D4
02D0 20D8
RIO_SP2_ERR_CAPT_0
RIO_SP2_ERR_CAPT_1
RIO_SP2_ERR_CAPT_2
RIO_SP2_ERR_CAPT_3
RapidIO Port 2 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 2 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 2 Packet/Control Symbol Error Capture CSR3
Register
02D0 20DC - 02D0 20E4
02D0 20E8
-
Reserved
RIO_SP2_ERR_RATE
RIO_SP3_RATE_EN
-
RapidIO Port 2 Error Rate CSR Register
RapidIO Port 3 Error Enable CSR Register
Reserved
02D0 20EC
02D0 20F0 - 02D0 20FC
02D0 2100
RIO_SP3_ERR_DET
RIO_SP3_RATE_EN
RIO_SP3_ERR_ATTR_CAPT
RapidIO Port 3 Error Detect CSR Register
RapidIO Port 3 Error Enable CSR Register
RapidIO Port 3 Attributes Error Capture CSR Register
02D0 2104
02D0 2108
RapidIO Port 3 Packet/Control Symbol Error Capture CSR0
Register
02D0 210C
02D0 2110
02D0 2114
02D0 2118
RIO_SP3_ERR_CAPT_0
RIO_SP3_ERR_CAPT_1
RIO_SP3_ERR_CAPT_2
RIO_SP3_ERR_CAPT_3
RapidIO Port 3 Packet/Control Symbol Error Capture CSR1
Register
RapidIO Port 3 Packet/Control Symbol Error Capture CSR2
Register
RapidIO Port 3 Packet/Control Symbol Error Capture CSR3
Register
02D0 211C - 02D0 2124
02D0 2128
-
Reserved
RIO_SP3_ERR_RATE
RIO_SP3_ERR_THRESH
-
RapidIO Port 3 Error Rate CSR Register
RapidIO Port 3 Error Rate Threshold CSR Register
Reserved
02D0 212C
02D0 2130 - 02D1 0FFC
Implementation Registers
02D1 1000 - 02D1 1FFC
02D1 2000
-
Reserved
RIO_SP_IP_DISCOVERY_TIMER
RIO_SP_IP_MODE
RapidIO Port IP Discovery Timer in 4x Mode Register
RapidIO Port IP Mode CSR Register
Reserved
02D0 2004
02D1 2008 - 02D1 200C
02D1 2010
-
RIO_SP_IP_PW_IN_CAPT0
RIO_SP_IP_PW_IN_CAPT1
RIO_SP_IP_PW_IN_CAPT2
RIO_SP_IP_PW_IN_CAPT3
-
RapidIO Port-Write-In Capture 0 CSR Register
RapidIO Port-Write-In Capture 1 CSR Register
RapidIO Port-Write-In Capture 2 CSR Register
RapidIO Port-Write-In Capture 3 CSR Register
Reserved
02D1 2014
02D1 2018
02D1 201C
02D1 2020 - 02D1 3FFC
02D1 4000
RIO_SP0_RST_OPT
RIO_SP0_CTL_INDEP
RIO_SP0_SILENCE_TIMER
RapidIO Port 0 Reset Option CSR Register
RapidIO Port 0 Control Independent Register
RapidIO Port 0 Silence Timer Register
02D1 4004
02D1 4008
RapidIO Port 0 Multicast-Event Control Symbol Request
Register
02D1 400C
02D1 4010
RIO_SP0_MULT_EVNT_CS
-
Reserved
C64x+ Peripheral Information and Electrical Specifications
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Table 7-113. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D1 4014
ACRONYM
RIO_SP0_CS_TX
-
REGISTER NAME
RapidIO Port 0 Control Symbol Transmit Register
Reserved
02D1 4018 - 02D1 40FC
02D1 4100
RIO_SP1_RST_OPT
RIO_SP1_CTL_INDEP
RIO_SP1_SILENCE_TIMER
RapidIO Port 1 Reset Option CSR Register
RapidIO Port 1 Control Independent Register
RapidIO Port 1 Silence Timer Register
02D1 4104
02D1 4108
RapidIO Port 1 Multicast-Event Control Symbol Request
Register
02D1 410C
RIO_SP1_MULT_EVNT_CS
02D1 4110
02D1 4114
-
Reserved
RIO_SP1_CS_TX
-
RapidIO Port 1 Control Symbol Transmit Register
Reserved
02D1 4118 - 02D1 41FC
02D1 4200
RIO_SP2_RST_OPT
RIO_SP2_CTL_INDEP
RIO_SP2_SILENCE_TIMER
RapidIO Port 2 Reset Option CSR Register
RapidIO Port 2 Control Independent Register
RapidIO Port 2 Silence Timer Register
02D1 4204
02D1 4208
RapidIO Port 2 Multicast-Event Control Symbol Request
Register
02D1 420C
RIO_SP2_MULT_EVNT_CS
02D1 4210
02D1 4214
-
Reserved
RIO_SP2_CS_TX
-
RapidIO Port 2 Control Symbol Transmit Register
Reserved
02D1 4218 - 02D1 42FC
02D1 4300
RIO_SP3_RST_OPT
RIO_SP3_CTL_INDEP
RIO_SP3_SILENCE_TIMER
RapidIO Port 3 Reset Option CSR Register
RapidIO Port 3 Control Independent Register
RapidIO Port 3 Silence Timer Register
02D1 4304
02D1 4308
RapidIO Port 3 Multicast-Event Control Symbol Request
Register
02D1 430C
RIO_SP3_MULT_EVNT_CS
02D1 4310
02D1 4314
-
Reserved
RIO_SP3_CS_TX
RapidIO Port 3 Control Symbol Transmit Register
02D1 4318 - 02D2 0FFF
02D2 1000 - 02DF FFFF
-
-
Reserved
Reserved
7.20.3 Serial RIO Electrical Data/Timing
The TMS320C6455 Serial Rapid IO (SRIO) Hardware Designer's Resource Guide Application Report
(literature number SPRAAB0) specifies a complete printed circuit board (PCB) solution for the C6455 as
well as a list of compatible SRIO devices showing two DSPs connected via a 4x SRIO link. TI has
performed the simulation and system characterization to ensure all SRIO interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
TI only supports designs that follow the board design guidelines outlined in the Implementing
Serial RapidIO (SRIO) PCB Layout on a TMS320C6455 Hardware Design Application Report
(Literature number SPRAAB0).
224
C64x+ Peripheral Information and Electrical Specifications
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
7.21 General-Purpose Input/Output (GPIO)
7.21.1 GPIO Device-Specific Information
On the C6455 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the UTOPIA, PCI, and
McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral
configuration and the C6455 device pin muxing, see the Device Configuration section of this document.
7.21.2 GPIO Peripheral Register Description(s)
Table 7-114. GPIO Registers
HEX ADDRESS RANGE
02B0 0008
ACRONYM
REGISTER NAME
GPIO interrupt per bank enable register
Reserved
BINTEN
02B0 000C
-
02B0 0010
DIR
GPIO Direction Register
02B0 0014
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
SET_RIS_TRIG
CLR_RIS_TRIG
SET_FAL_TRIG
CLR_FAL_TRIG
-
GPIO Output Data register
GPIO Set Data register
02B0 0018
02B0 001C
GPIO Clear Data Register
GPIO Input Data Register
GPIO Set Rising Edge Interrupt Register
GPIO Clear Rising Edge Interrupt Register
GPIO Set Falling Edge Interrupt Register
GPIO Clear Falling Edge Interrupt Register
Reserved
02B0 0020
02B0 0024
02B0 0028
02B0 002C
02B0 0030
02B0 008C
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
-
Reserved
-
Reserved
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7.21.3 GPIO Electrical Data/Timing
Table 7-115. Timing Requirements for GPIO Inputs(1)(2) (see Figure 7-84)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
12P
12P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize
the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP
enough time to access the GPIO register through the CFGBUS.
Table 7-116. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs(1)
(see Figure 7-84)
-720
-850
-1000
NO.
PARAMETER
UNIT
MIN
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
36P – 8(2)
36P – 8(2)
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 7-84. GPIO Port Timing
226
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
7.22 IEEE 1149.1 JTAG
7.22.1 JTAG Device-Specific Information
7.22.1.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6455 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive
TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of
an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.
7.22.2 JTAG Peripheral Register Description(s)
7.22.3 JTAG Electrical Data/Timing
Table 7-117. Timing Requirements for JTAG Test Port (see Figure 7-85)
-720
-850
-1000
NO.
UNIT
MIN
MAX
1
3
4
tc(TCK)
Cycle time, TCK
35
10
9
ns
ns
ns
tsu(TDIV-TCKH)
th(TCKH-TDIV)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
Table 7-118. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7-85)
-720
-850
-1000
MIN
-3
NO.
PARAMETER
UNIT
MAX
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
18
ns
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 7-85. JTAG Test-Port Timing
C64x+ Peripheral Information and Electrical Specifications
227
TMS320C6455
Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
Revision History
This data sheet revision history highlights the technical changes made to the SPRS276A device-specific
data sheet to make it an SPRS276B revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6455 device,
have been incorporated. The C6455 device is at the product preview (PP) stage of development (see
ADDS/CHANGES/DELETES).
Continued incorporation of new format/outline structure. Updated/corrected device-specific information for
clarity.
SEE
ADDS/CHANGES/DELETES
Section 1.1
Features section:
Changed EDMA to EDMA3
Section 1.3
Section 2
Functional Block Diagram section:
Updated Functional Block Diagram and notes
Device Overview section:
Updated Table 2-1, Characteristics of the C6455 Processor:
Changed SYSCLK3 to SYSCLK4
Section 2.2
Section 2.3
CPU (DSP Core) Description section:
Updated C64x/C64x+ documentation references
Memory Map Summary section:
Updated Table 2-2, C6455 Memory Map Summary
Section 2.4
Changed section title from Bootmode Sequence to Boot Sequence
Section 2.4.1
Change section title from Bootmodes Supported to Boot Modes Supported
Updated paragraphs
Section 2.5
Section 2.6
Added Pin Assignments section:
Added Pin Map section:
Added four C6455 Pin Map (Bottom View) [Quadrants A, B, C, and D] drawings
Signal Groups Description section:
Updated Figure 2-6, CPU and Peripheral Signals
Updated Figure 2-7, Timers/GPIO/RapidIO Peripheral Signals
Updated Figure 2-8, EMIFA/DDR2 Memory Controller Peripheral Signals
Updated Figure 2-9, HPI/McBSP/I2C Peripheral Signals
Updated Figure 2-10, EMAC/MDIO [MII/RMII/GMII/RGMII] Peripheral Signals
Updated Figure 2-12, PCI Peripheral Signals
228
Revision History
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
SEE
ADDS/CHANGES/DELETES
Table 2-3
Terminal Functions table:
Added footnote (4)
Changed signal name for signal NO. AJ13 from SYSCLK3/GP[1] to SYSCLK4/GP[1]
Updated description for NMI signal
Updated descriptions for URADDR3/PREQ/GP[15], URADDR2/PINTA/GP[14], URADDR1/PRST/GP[13],
URADDR0/PGNT/GP[12], and URADDR4/PCBE0/GP[2] signals
Updated descriptions for UXADDR2/PCBE3, UXADDR1/PIDSEL, and UXADDR0/PTRDY signals
Updated description for EMIFA (64-BIT) - ADDRESS signals
Updated description for AEA[19:16] signals
Updated descriptions for DCE0, DDR2CLKOUT, DDR2CLKOUT, DSDCKE, DEODT[1:0], and
DSDDQGATE[3:0] signals
Updated description for DEA[13:0] signals
Updated type and description for CLKS signal
Updated types and/or descriptions for CLKR1/GP[0], FSR1/GP[10], DR1/GP[8], DX1/GP[9], and
FSX1/GP[11] signals
Updated types and/or descriptions for CLKR0, FSR0, DR0, DX0 FSX0, and CLKX0 signals
Updated descriptions for RIOTX[3:0] and RIORX[3:0] signals
Updated descriptions for UXADDR4/MDCLK, and UXADDR3/MDIO signals
Updated type for UXDATA[7:0]/MTXD[7:0]/RMTXD[1:0] signals
Updated descriptions for RGMDCLK and RGMDIO signals
Updated types and/or descriptions for URCLK/MRCLK, URCLAV/MCRS/RMCRSDV,
URSOC/MRXER/RMRXER, URENB/MRXDV, URDATA[7:0]/MRXD[7:0]/RMTXD[1:0], UXCLAV/GMTCLK,
UXCLK/MTCLK/RMREFCLK, UXSOC/MCOL, UXENB/MTXEN/RMTXEN,
UXDATA[7:0]/MTXD[7:0]/RMTXD[1:0], and UXDATA0/MTXD0/RMTXD0 signals
Updated descriptions for RGREFCLK, RGTXC, RGTXD[3:0], RGTXCTL, RGRXC, RGRXD[3:0], and
RGRXCTL signals
Updated description for RSV[07:08] signals
Updated descriptions for RSV[11:16] signals
Updated description for RSV[17:44] signals
Updated SUPPLY VOLTAGE PINS section:
Updated description for VREFSSTL signal
Updated description for VREFHSTL signal
Changed signal name for signal NOs. AC15, AC17, and AD16 from AVDD12to AVDDA
Updated description for DVDDR signal
Updated description for AVDDA signal
Changed signal name for signal NO. A13 from AVDD18to AVDLL1
Changed signal name for signal NO. E18 from AVDD18to AVDLL2 and updated description
Changed signal name for signal NOs. U16, V15, and V17 from DVDD12to DVDDRM
Added description for DVDDRM signal
Updated description for DVDD12 signal
Changed signal name for signal NOs. AE17, AE19, AE23, AF20, AH20, AJ17, and AJ23 from DVDD12to
AVDDT
Updated description for DVDD15 signal
Added description for AVDDT signal
Updated desctiption for CVDD signal
Section 2.8.2.1
Section 2.8.2.2
Section 3
Device and Development-Support Tool Nomenclature section:
Updated Figure 2-13, TMS320C64x+™ DSP Device Nomenclature (including the TMS320C6455 DSP).
Documentation Support section:
Added paragraph and documentation references
Updated Device Configuration section
Device Configuration at Device Reset section:
Added Note paragraph
Updated Table 3-1, C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN):
Changed SYSCLK3 to SYSCLK4 in the Functional Description for Configuration Pins AEA15 and AEA4
Deleted Priority Allocation section (moved to System Interconnect section)
Section 3.2
Section 3.3
Section 3.4
Updated Peripheral Configuration at Device Reset section:
Updated Table 3-2, and changed title to PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection
(HPI and PCI)
Updated Table 3-3, UTOPIA_EN, and MAC_SEL[1:0] Peripheral Selection (UTOPIA and EMAC)
Updated Peripheral Selection After Device Reset section:
Added Table 3-4, Peripheral States
Added Figure 3-1, Peripheral Transitions Between States
Added Figure 3-2, Peripheral State Change Flow
Added Device State Control Registers section:
Added Table 3-5, Device State Control Registers
Revision History
229
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Fixed-Point Digital Signal Processor
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SPRS276B–MAY 2005–REVISED FEBRUARY 2006
SEE
ADDS/CHANGES/DELETES
Added Peripheral Lock Register Description section:
Added Figure 3-3, Peripheral Lock Register (PERLOCK) - 0x02AC 0000, and Table 3-6, Peripheral Lock
Register (PERLOCK) Field Descriptions
Section 3.4.1
Section 3.4.2
Section 3.4.3
Section 3.4.4
Added Peripheral Configuration Register 0 Description section:
Added Figure 3-4, Peripheral Configuration Register 0 (PERCFG0) - 0x02AC 0008, and Table 3-7,
Peripheral Configuration Register 0 (PERCFG0) Field Descriptions
Added Peripheral Configuration Register 1 Description section:
Added Figure 3-5, Peripheral Configuration Register 1 (PERCFG1) - 0x02AC 002C, and Table 3-8,
Peripheral Configuration Register 1 (PERCFG1) Field Descriptions
Added Peripheral Status Registers Description section:
Added Figure 3-6, Peripheral Status Register 0 (PERSTAT0) - 0x02AC 0014, and Table 3-9, Peripheral
Status Register 0 (PERSTAT0) Field Descriptions
Added Figure 3-7, Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018, and Table 3-10, Peripheral
Status Register 1 (PERSTAT1) Field Descriptions
Section 3.4.5
Section 3.4.6
Section 3.5
Added EMAC Interface Reset Control Register (EIRCR) Description section:
Added Figure 3-8, EMAC Interface Reset Control Register (EIRCR) - 0x02AC 0020, and Table 3-11, EMAC
Interface Reset Control Register (EIRCR) Field Descriptions
Added Emulator Buffer Powerdown Register Description section:
Added Figure 3-9, Emulator Buffer Powerdown Register (EMUBUFPD) - 0x02AC 0054 and Table 3-12,
Emulator Buffer Powerdown Register (EMUBUFPD) Field Descriptions
Updated Device Status Register Description section:
Updated Figure 3-10, Device Status Register (DEVSTAT) - 0x02A8 0000, and Table 3-13, Device Status
Register (DEVSTAT) Field Descriptions:
Changed SYSCLK3 to SYSCLK4 in the Field Descriptions for SYSCLKOUT_EN and AECLKINSEL
Section 3.6
Section 3.8
Updated JTAG ID (JTAGID) Register Description section:
Updated Figure 3-11, JTAG ID (JTAGID) Register - 0x02A8 0008 and Table 3-14, JTAG ID (JTAGID)
Register Field Descriptions
Configuration Examples section:
Updated Figure 3-12, Configuration Example A, and Figure 3-13, Configuration Example B
Section 4
Added System Interconnect section
Section 4.4
Added Priority Allocation section and Figure 4-3, Priority Allocation Register (PRI_ALLOC) [moved from
Device Configuration section]
Changed bit name for bits 11:9 from SRIO_CPPI to SRIO
Changed bit name for bits 5:3 from HPI/PCI to HOST
Changed bit name for bits 2:0 from EMAC_CPPI to EMAC
Section 5
Updated C64x+ Megamodule section
Section 5.6
Added Megamodule Revision section:
Added Figure 5-5, Megamodule Revision ID Register (MM_REVID) [Hex Address: 0181 2000h], and
Table 5-3, Megamodule Revision ID Register (MM_REVID) Field Descriptions
Section 6
Section 7
Device Operating Conditions section:
Updated Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
Updated Recommended Operating Conditions
Updated Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted)
C64x+ Peripheral Information and Electrical Specifications section:
Updated 3.3-V signal Transition Levels section:
Updated Figure 7-3, Rise and Fall Transition Time Voltage Reference Levels
Deleted Power-Down Modes Logic section
Added Power Supplies section:
Updated Power-Supply Sequencing section:
Added Figure 7-5, Power-Supply Sequence (Option 1), Figure 7-6, Power-Supply Sequence (Option 2),
Table 7-2, Timing Requirements for Power-Supply Sequence (Option 1), and Table 7-3, Timing
Requirements for Power-Supply Sequence (Option 2)
Updated Power-Down Operation section
Deleted Powersaver section
Section 7.4
Updated Enhanced Direct Memory Access (EDMA3) Controller section:
Added Section 7.4.1, EDMA Device-Specific Information section
Updated Table 7-4, C6455 EDMA Channel Synchronization Events
Updated Table 7-5, EDMA3 Registers
Deleted EDMA Block Diagram
Section 7.5
Interrupts section:
Updated Interrupt Sources and Interrupt Controller section
Updated Table 7-7, C6455 DSP Interrupts
230
Revision History
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
SEE
ADDS/CHANGES/DELETES
Changed title of Reset section to Reset Controller
Section 7.6
Updated Reset Controller section
Updated Table 7-9, Reset Types
Updated Power-on Reset (POR Pin) section
Updated Warm Reset (RESET Pin) section
Updated System Reset section
Updated the CPU Reset section
Section 7.6.6
Section 7.6.7
Section 7.6.7.1
Added Reset Priority section
Added Reset Controller Register section:
Added Reset Type Status Register Description section:
Added Figure 7-8, Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4], and Table 7-10, Reset
Type Status Register (RSTYPE) Field Descriptions
Section 7.6.8
Reset Electrical Data/Timing section:
Added Note paragraph
Deleted Timing NOs. 1-4 and changed MIN value for Timing NO. 5 from 256*C to 256 on the Timing
Requirements for Reset table
Deleted Parameter NO. 9 and changed Parameter NO. 8 to NO. 9 on the Switching Characteristics Over
Recommended Operating Conditions During Reset table
Updated Figure 7-9, Power-Up Timing
Deleted Reset Timing diagram
Added Figure 7-10, Warm Reset and Max Reset Timing
Added Figure 7-11, System Reset Timing
Section 7.7
Updated PLL1 and PLL1 Controller section:
Updated Figure 7-12, PLL1 and PLL1 Controller
Section 7.7.1
Added PLL1 Controller Device-Specific Information section:
Added Internal Clocks and Maximum Operating Frequencies section:
Added Table 7-13, PLL1 Clock Frequency Ranges
Added PLL1 Controller Operating Modes section
Added PLL1 Stabilization, Lock, and Reset Times section:
Added Table 7-14, PLL1 Stabilization, Lock, and Reset Times
Section 7.7.2
Added PLL1 Controller Memory Map section:
Moved to this section and updated Table 7-15, PLL1 Controller Registers (Including Reset Controller)
Section 7.7.3
Added PLL1 Controller Register Description section:
Section 7.7.3.1
Added PLL Control Register section:
Added Figure 7-13, PLL Control Register (PLLCTL) [Hex Address: 029A 0100], and Table 7-16, PLL Control
Register (PLLCTL) Field Descriptions
Section 7.7.3.2
Added PLL Multiplier Control Register section:
Moved to this section and changed Figure 7-14, PLL Multiplier Control Register (PLLM) [Hex Address: 029A
0110] value after reset for bits 4:0 to R/W-0h
Updated Table 7-17, PLL Multiplier Control Register (PLLM) Field Descriptions for bits 4:0
Section 7.7.3.3
Section 7.7.3.4
Added PLL Pre-Divider Control Register section:
Added Figure 7-15, PLL Pre-Divider Register (PREDIV) [Hex Address: 029A 0114], and Table 7-18, PLL
Pre-Divider Register (PREDIV) Field Descriptions
Added PLL Controller Divider Registers section:
Added Figure 7-16, PLL Controller Divider Register 4 (PLLDIV4) [Hex Address: 029A 0167], Figure 7-17,
PLL Controller Divider Register 5 (PLLDIV5) [Hex Address: 029A 0140], and Table 7-19, PLL Controller
Divider Registers (PLLDIV4 and PLLDIV5) Field Descriptions
Section 7.7.3.5
Section 7.7.3.6
Section 7.7.3.7
Section 7.7.3.8
Section 7.7.3.9
Added PLL Controller Command Register section:
Added Figure 7-18, PLL Controller Command Register (PLLCMD) [Hex Address: 029A 0138], and
Table 7-20, PLL Controller Command Register (PLLCMD) Field Descriptions
Added PLL Controller Status Register section:
Added Figure 7-19, PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C], and Table 7-21,
PLL Controller Status Register (PLLSTAT) Field Descriptions
Added PLL Controller Clock Align Control Register section:
Added Figure 7-20, PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140], and
Table 7-22, PLL Controller Clock Align Control Register (ALNCTL) Filed Descriptions
Added PLLDIV Ratio Change Status Register section:
Added Figure 7-21, PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144],
and Table 7-23, PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Added SYSCLK Status Register section:
Added Figure 7-22, SYSCLK Status Register (SYSTAT) [Hex Address: 029A 0150], and Table 7-24,
SYSCLK Status Register (SYSTAT) Field Descriptions
Revision History
231
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
SEE
ADDS/CHANGES/DELETES
PLL1 Controller Input and Output Clock Electrical Data/Timing section:
Section 7.7.4
Changed table title to "Timing Requirements for CLKIN1" and changed Timing NO. 1 MAX value from 30 ns
to 30.3 ns, Timing NO. 4 MAX value from 5 ns to 1.2 ns, and Timing NO. 5 description to "Period jitter
(peak-to-peak)" and MAX value from 50 ps to 100 ps in the table
Changed table title to "Switching Characteristics Over Recommended Operating Conditions for SYSCLK4
[CPU/8 - CPU/12]" and changed SYSCLK3 to SYSCLK4 in the table
Changed figure title to "SYSCLK4 Timing" and changed SYSCLK3 to SYSCLK4 in the figure
Section 7.8
Updated PLL2 and PLL2 Controller section:
Updated Figure 7-25, PLL2 Block Diagram
Section 7.8.1
Added PLL2 Controller Device-Specific Information section:
Added Internal Clocks and Maximum Operating Frequencies section:
Added Table 7-27, PLL2 Clock Frequency Ranges
Added PLL2 Controller Operating Modes section
Section 7.8.2
Added PLL2 Controller Memory Map section:
Added Table 7-28, PLL2 Controller Registers
Section 7.8.3
Added PLL2 Controller Register Descriptions section:
Section 7.8.3.1
Added PLL Controller Divider 1 Register section:
Added Figure 7-26, PLL Controller Divider 1 Register (PLLDIV1) [Hex Address: 029C 0118], and Table 7-29,
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
Section 7.8.3.2
Section 7.8.3.3
Section 7.8.3.4
Section 7.8.3.5
Section 7.8.3.6
Section 7.8.4
Added PLL Controller Command Register section:
Added Figure 7-27, PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138], and
Table 7-30, PLL Controller Command Register (PLLCMD) Field Descriptions
Added PLL Controller Status Register section:
Added Figure 7-28, PLL Controller Status Register (PLLSTAT) [Hex Address: 029C 013C], and Table 7-31,
PLL Controller Status Register (PLLSTAT) Field Descriptions
Added PLL Controller Clock Align Control Register section:
Added Figure 7-29, PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029C 0140], and
Table 7-32, PLL Controller Clock Align Control Register (ALNCTL) Filed Descriptions
Added PLLDIV Ratio Change Status Register section:
Added Figure 7-30, PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029C 0144],
and Table 7-33, PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Added SYSCLK Status Register section:
Added Figure 7-31, SYSCLK Status Register [Hex Address: 029C 0150], and Table 7-34, SYSCLK Status
Register Field Descriptions
PLL2 Controller Input Clock Electrical Data/Timing section:
Changed Timing NO. 4 MAX value from 5 ns to 1.2 ns, and Timing NO. 5 description to "Period jitter
(peak-to-peak)" and MAX value from 50 ps to 100 ps in the Timing Requirements for CLKIN2 table
Changed Note (2) from "... when CLKIN2 frequency is 50 MHz, use C = 20 ns." to "... when CLKIN2
frequency is 25 MHz, use C = 40 ns." in the Timing Requirements for CLKIN2 table
Section 7.9
Updated DDR2 Memory Controller section
Section 7.9.1
DDR2 Memory Controller Device-Specific Information section:
Added paragraphs
Section 7.9.2
DDR2 Memory Controller Peripheral Register Description(s) section:
Updated Hex Address Ranges, Acronyms, and Register Name descriptions for Table 7-36, DDR2 Memory
Controller Registers
Section 7.10.2
Section 7.10.3
EMIFA Peripheral Register Description(s) section:
Updated Acronyms and Register Name descriptions for Table 7-37, EMIFA Registers
EMIFA Electrical Data/Timing section:
Changed SYSCLK3 to SLSCLK4 in footnote (3) of the Timing Requirements for AECLKIN for EMIFA table
Changed SYSCLK3 to SLSCLK4 in footnote (1) of the Switching Characteristics Over Recommended
Operating Conditions for AECLKOUT for the EMIFA Module table
Updated Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table
Section 7.11.2
I2C Peripheral Register Description(s) section:
Updated I2C Acronyms for Table 7-47, Registers
Section 7.12.1
Section 7.12.3
Updated HPI Device-Specific Information section
HPI Electrical Data/Timing section:
Changed MIN value for signal NO. 14 from 2 to 2M and updated footnote (2) of the Timing Requirements
for Host-Port Interface Cycles table
Changed MAX values from 2H to M, updated PARAMETER descriptions and footnote (1), and added
footnote (3) to the Switching Characteristics for Host-Port Interface Cycles table
Section 7.13.1
Updated McBSP Device-Specific Information section
232
Revision History
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
SEE
ADDS/CHANGES/DELETES
McBSP Peripheral Register Description(s) section:
Section 7.13.1.1
Updated Register Name descriptions for Table 7-53, McBSP 0 Registers, and Table 7-54, McBSP 1
Registers
Section 7.13.2
McBSP Electrical Data/Timing section:
Updated footnote (7) of the Switching Characteristics Over Recommended Operating Conditions for McBSP
table
Updated footnote (3) of the Switching Characteristics Over Recommended Operating Conditions for McBSP
as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 table
Updated footnote (3) of the Switching Characteristics Over Recommended Operating Conditions for McBSP
as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 table
Updated footnote (3) of the Switching Characteristics Over Recommended Operating Conditions for McBSP
as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 table
Updated footnote (3) of the Switching Characteristics Over Recommended Operating Conditions for McBSP
as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 table
Section 7.14.1
Section 7.14.2
EMAC Device-Specific Information section:
Added Using the RMII Mode of the EMAC section
Updated Table 7-66, EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes)
EMAC Peripheral Register Description(s) section:
Updated Register Name descriptions for Table 7-67, Ethernet MAC (EMAC) Control Registers
Changed title of Table 7-69from "EMAC Wrapper" to "EMAC Control Module Registers"
Updated EMAC Control Module Registers table
Changed title of Table 7-70from "EMAC CPPI RAM" to "EMAC Descriptor Memory"
Updated EMAC Descriptor Memory table
Section 7.14.3.2
Section 7.14.3.3
EMAC RMII Electrical Data/Timing section:
Updated paragraph
Changed table title to "Timing Requirements for RMREFCLK - RMII Operation," changed timing NOs., and
updated MIN and MAX values
Updated Figure 7-67, RMREFCLK Timing
EMAC RGMII Electrical Data/Timing section:
Updated formatting of Timing Requirements for RXC - RGMII Operation table
Updated formatting of Timing Requirements for TXC - RGMII Operation for 10/100/1000 Mbit/s table
Section 7.15
Updated Timers section:
Section 7.15.2
Timers Peripheral Register Description(s) section:
Updated Acronyms and Register Name descriptions for Table 7-90, Timer 0 Registers
Updated Acronyms and Register Name descriptions for Table 7-91, Timer 1 Registers
Section 7.16.1
Section 7.16.2
Updated VCP2 Device-Specific Information section
VCP2 Peripheral Register Description(s) section:
Updated EDMA Bus Hex Address Range and added descriptions for Registers BM, SM, HD, SD, and IO for
Table 7-94, VCP2 Registers
Section 7.17.1
Section 7.17.2
Updated TCP2 Device-Specific Information section
TCP2 Peripheral Register Description(s) section:
Updated Acroynms and Register Name descriptions for Table 7-95, TCP2 Registers
Section 7.18
Updated Peripheral Component Interconnect (PCI) section
Section 7.18.2
PCI Peripheral Register Description(s) section:
Separated PCI Peripheral Registers table into 5 tables:
Table 7-96, PCI Configuration Registers
Table 7-97, PCI Back End Configuration Registers
Table 7-98, DSP-to_PCI Address Translation Registers
Table 7-99, PCI Hook Configuration Registers
Table 7-100, PCI External Memory Space
Section 7.18.3
PCI Electrical Data/Timing section:
Updated footnote (1) of the Timing Requirements for PCLK table
Section 7.19.1
Section 7.19.2
Updated UTOPIA Device-Specific Information section
UTOPIA Peripheral Register Description(s) section:
Updated Acroynms and Register Name descriptions for Table 7-105, UTOPIA Registers
Updated Hex Address Range for Table 7-106, UTOPIA Data Queues (Receive and Transmit) Registers
Section 7.21.1
Section 7.21.2
Updated GPIO Device-Specific Information section
GPIO Peripheral Register Description(s) section:
Updated Acroynms and Register Name descriptions for Table 7-114, GPIO Registers
Section 7.22.1.1
Updated IEEE 1149.1 JTAG Compatibility Statement section
Revision History
233
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
234
Revision History
TMS320C6455
Fixed-Point Digital Signal Processor
www.ti.com
SPRS276B–MAY 2005–REVISED FEBRUARY 2006
8 Mechanical Data
8.1 Thermal Data
The following table(s) show the thermal resistance characteristics for the PBGA - ZTZ mechanical
package.
Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [ZTZ]
NO
1
°C/W
1.45
8.34
16.1
13.0
11.9
10.7
0.37
0.89
1.01
1.17
7.6
Air Flow (m/s(1)
)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
N/A
N/A
0.00
1.0
2
3
4
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
5
2.0
6
3.0
0.00
1.0
7
8
1.5
3.00
0.00
1.0
6.7
6.4
1.5
5.8
3.00
(1) m/s = meters per second
8.2 Packaging Information
The following packaging information and addendum reflect the most current released data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Mechanical Data
235
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMX320C6455ZTZ
TMX320C6455ZTZ7
TMX320C6455ZTZ8
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
ZTZ
697
697
697
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
ZTZ
ZTZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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相关型号：
TMX320C6455ZTZ720
IC 64-BIT, 66.67 MHz, OTHER DSP, PBGA697, 24 X 24 MM, 0.80 MM PITCH, PLASTIC, BGA-697, Digital Signal Processor
TI
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