TMX320F28027PTA [TI]
Piccolo Microcontrollers; Piccolo微处理器
| 型号： | TMX320F28027PTA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Piccolo Microcontrollers |
| 文件： | 总104页 (文件大小：1021K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
1 TMS320F2802x (Piccolo™) MCUs
1.1 Features
Multiplexed GPIO Pins With Input Filtering
•
High-Efficiency 32-Bit CPU (TMS320C28x™)
–
–
–
–
–
–
–
–
–
60 MHz (16.67-ns Cycle Time)
40 MHz (25-ns Cycle Time)
16 x 16 and 32 x 32 MAC Operations
16 x 16 Dual MAC
Harvard Bus Architecture
Atomic Operations
Fast Interrupt Response and Processing
Unified Memory Programming Model
Code-Efficient (in C/C++ and Assembly)
•
Peripheral Interrupt Expansion (PIE) Block
That Supports All Peripheral Interrupts
•
•
Three 32-Bit CPU Timers
On-Chip Memory
–
Flash, SARAM, OTP, Boot ROM Available
•
•
128-Bit Security Key/Lock
–
–
Protects Secure Memory Blocks
Prevents Firmware Reverse Engineering
Serial Port Peripherals
•
Low Device and System Cost:
–
–
–
One SCI (UART) Module
One SPI Module
One Inter-Integrated-Circuit (I2C) Bus
–
–
–
Single 3.3-V Supply
No Power Sequencing Requirement
Integrated Power-on Reset and Brown-out
Reset
Small Packaging, as low as 38-pin available
Low Power
•
•
Advanced Emulation Features
–
–
Analysis and Breakpoint Functions
Real-Time Debug via Hardware
–
–
–
Enhanced Control Peripherals
No Analog Support Pins
–
–
–
–
–
Enhanced Pulse Width Modulator (ePWM)
High-resolution PWM (HRPWM)
Enhanced Capture (eCAP)
Analog-to-Digital Converter (ADC)
Comparator
•
•
Clocking:
–
–
2 Internal Zero-pin Oscillators
On-chip Crystal Oscillator/External Clock
Input
Dynamic PLL Ratio Changes Supported
Watchdog Timer Module
Missing Clock Detection Circuitry
–
–
–
•
2802x Packages
–
38-Pin DA Plastic Small Outline Package
(PSOP)
Up to 22 Individually Programmable,
–
48-Pin PT Plastic Quad Flatpack (PQFP)
1.2 Description
The F2802x Piccolo™ family of microcontrollers provides the power of the C28x™ core coupled with
highly integrated control peripherals in low pin-count devices. This family is code compatible with previous
C28-based code, as well as providing a high level of analog integration.
An internal voltage regulator allows for single rail operation. Enhancements have been made to the
HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal
10-bit references have been added and can be routed directly to control the PWM outputs. The ADC
converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The
interface has been optimized for low overhead/latency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2008–2008, Texas Instruments Incorporated
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
1.3 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
•
•
•
Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0).
C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits)
2
TMS320F2802x (Piccolo™) MCUs
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Contents
TMS320F2802x (Piccolo™) MCUs .................... 1
1
4.5 High-Resolution PWM (HRPWM) ................... 54
4.6 Enhanced CAP Modules (eCAP1) .................. 55
4.7 JTAG Port ........................................... 56
4.8 GPIO MUX .......................................... 57
Device Support ......................................... 63
1.1 Features .............................................. 1
1.2 Description............................................ 1
1.3 Getting Started........................................ 2
Hardware Features ...................................... 4
2.1 Pin Assignments...................................... 5
2.2 Signal Descriptions ................................... 7
Functional Overview................................... 11
3.1 Block Diagram....................................... 11
3.2 Memory Maps ...................................... 12
3.3 Brief Descriptions.................................... 16
3.4 Register Map ........................................ 22
3.5 Device Emulation Registers......................... 23
3.6 Interrupts ............................................ 24
3.7 VREG/BOR/POR.................................... 28
3.8 System Control ...................................... 30
3.9 Low-power Modes Block ............................ 36
Peripherals............................................... 38
4.1 Analog Block ........................................ 38
2
3
5
6
5.1
Device and Development Support Tool
Nomenclature ....................................... 63
5.2 Related Documentation ............................. 64
Electrical Specifications .............................. 67
6.1 Absolute Maximum Ratings ......................... 67
6.2 Recommended Operating Conditions............... 67
6.3 Electrical Characteristics ........................... 68
6.4 Current Consumption................................ 68
6.5
Emulator Connection Without Signal Buffering for
the MCU............................................. 71
6.6 Timing Parameter Symbology....................... 73
6.7
Clock Requirements and Characteristics ........... 75
6.8 Power Sequencing .................................. 76
6.9 General-Purpose Input/Output (GPIO).............. 79
6.10 Enhanced Control Peripherals ...................... 84
6.11 Detailed Descriptions ............................... 97
Mechanicals ............................................. 99
4
4.1
Serial Peripheral Interface (SPI) Module ........... 42
Serial Communications Interface (SCI) Module .... 45
4.2
7
4.3 Inter-Integrated Circuit (I2C) ........................ 48
Enhanced PWM Modules (ePWM1/2/3/4) .......... 50
Revision History............................................ 100
4.4
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Contents
3
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
2 Hardware Features
Table 2-1. Hardware Features
28022
(40 MHz)
28023
(40 MHz)
28024
(40 MHz)
28025
(40 MHz)
28026
(60 MHz)
28027
(60 MHz)
FEATURE
TYPE(1)
Instruction cycle
–
–
–
25 ns
16K
6K
25 ns
32K
6K
25 ns
16K
6K
25 ns
32K
6K
16.67 ns
16K
16.67 ns
32K
On-chip flash (16-bit word)
On-chip SARAM (16-bit word)
6K
6K
Code security for on-chip flash/SARAM/OTP
blocks
–
–
–
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Boot ROM (8K X16)
One-time programmable (OTP) ROM (16-bit
word)
ePWM modules
eCAP modules
Watchdog timer
MSPS
1
0
–
ePWM1/2/3/4
ePWM1/2/3/4
ePWM1/2/3/4
ePWM1/2/3/4
ePWM1/2/3/4
ePWM1/2/3/4
eCAP1
eCAP1
eCAP1
Yes
3.07
325 ns
13
eCAP1
Yes
3.07
325 ns
13
eCAP1
eCAP1
Yes
Yes
Yes
Yes
3.07
3.07
4.6
4.6
12-Bit ADC
Conversion Time
Channels
3
325 ns
325 ns
216.67 ns
216.67 ns
7
3
7
3
13
3
13
3
32-Bit CPU timers
–
1
0
0
1
0
–
–
–
–
–
–
–
–
–
3
3
HiRES ePWM Channels
4
4
4
4
4
4
Comparators w/ Integrated DACs
Inter-integrated circuit (I2C)
1
1
2
2
2
2
1
1
1
1
1
1
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
1
1
1
1
1
1
1
1
1
1
1
1
Digital
I/O pins (shared)
Analog
20
6
20
6
22
22
22
6
22
6
6
6
External interrupts
3
3
3
3
3
3
Supply voltage (nominal)
3.3 V
–
3.3 V
–
3.3 V
Yes
–
3.3 V
Yes
–
3.3 V
Yes
–
3.3 V
Yes
–
48-Pin PT PQFP
Packaging
38-Pin DA PSOP
Yes
Yes
–
Yes
Yes
–
A: - 40°C to 85°C
Yes
Yes
TMX
Yes
Yes
TMX
Yes
–
Yes
–
Temperature
options
S: - 40°C to 125°C
Product status(2)
TMX
TMX
TMX
TMX
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) and in the peripheral reference guides.
(2) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages. TMX is an experimental device that
is not necessarily representative of the final device's electrical specifications. TMS is a fully qualified production device.
4
Hardware Features
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
2.1 Pin Assignments
Figure 2-1 shows the 48-pin PT plastic quad flatpack (PQFP) pin assignments. Figure 2-2 shows the
38-pin DA plastic small outline package (PSOP) pin assignments.
GPIO2/EPWM2A 37
GPIO3/EPWM2B/COMP2OUT 38
GPIO4/EPWM3A 39
24 GPIO18/SPICLKA/SCITXDA/XCLKOUT
23 GPIO38/XCLKIN (TCK)
22 GPIO37 (TDO)
GPIO5/EPWM3B/ECAP1 40
21 GPIO36 (TMS)
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41
GPIO7/EPWM4B/SCIRXDA 42
20 GPIO35 (TDI)
19 GPIO34/COMP2OUT
18 ADCINB7
VDD
VSS
43
44
17 ADCINB6/AIO14
16 ADCINB4/COMP2B/AIO12
15 ADCINB3
X1 45
X2 46
GPIO12/TZ1/SCITXDA 47
GPIO28/SCIRXDA/SDAA/TZ2 48
14 ADCINB2/COMP1B/AIO10
13 ADCINB1
Figure 2-1. 2802x 48-Pin PT PQFP (top view)
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Hardware Features
5
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
VDD
VSS
1
38 TEST
2
37 GPIO0/EPWM1A
VREGENZ
VDDIO
3
36 GPIO1/EPWM1B/COMP1OUT
35 GPIO16/SPISIMOA/TZ2
34 GPIO17/SPISOMIA/TZ3
4
GPIO2/EPWM2A
GPIO3/EPWM2B/COMP2OUT
GPIO4/EPWM3A
5
6
33 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1
32 GPIO18/SPICLKA/SCITXDA/XCLKOUT
31 GPIO38/XCLKIN (TCK)
30 GPIO37 (TDO)
7
GPIO5/EPWM3B/ECAP1
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA
VDD
8
9
10
11
12
13
14
15
16
17
18
19
29 GPIO36 (TMS)
28 GPIO35 (TDI)
VSS
27 GPIO34/COMP2OUT
GPIO12/TZ1/SCITXDA
26 ADCINB6/AIO14
GPIO28/SCIRXDA/SDAA/TZ2
GPIO29/SCITXDA/SCLA/TZ3
25 ADCINB4/COMP2B/AIO12
24 ADCINB2/COMP1B/AIO10
/VREFLO
23 VSSA
TRST
XRS
ADCINA6/AIO6
22 VDDA
21 ADCINA0/VREFHI
ADCINA4/COMP2A/AIO4
20 ADCINA2/COMP1A/AIO2
Figure 2-2. 2802x 38-Pin DA PSOP (top view)
6
Hardware Features
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
2.2 Signal Descriptions
Table 2-2. TERMINAL FUNCTIONS
TERMINAL
I/O/Z
DESCRIPTION
NAME
PT NO.
DA NO.
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or driven
low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
normal device operation. An external pulldown resistor is recommended on this pin.
The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since
this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application. (↓)
TRST
2
16
I
TCK
TMS
See GPIO38
I
I
See GPIO38. JTAG test clock with internal pullup (↑)
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control
input is clocked into the TAP controller on the rising edge of TCK. (↑)
See GPIO36
See GPIO35
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the
selected register (instruction or data) on a rising edge of TCK. (↑)
TDI
I
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA
drive)
TDO
See GPIO37
O/Z
FLASH
TEST
30
38
I/O
Test Pin. Reserved for TI. Must be left unconnected.
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This
is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to
3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
XCLKOUT
See GPIO18
O/Z
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1
pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN
path must be disabled by bit 13 in the CLKCTL register.
Note: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for
normal device operation may need to incorporate some hooks to disable this path
during debug using the JTAG connector. This is to prevent contention with the TCK
signal, which is active during JTAG debug sessions. The zero-pin internal oscillators
may be used during this time to clock the device.
See GPIO19 and
GPIO38
XCLKIN
I
On-chip crystal oscillator Input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path must
be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to
GND. (I)
X1
X2
45
46
–
–
I
On-chip crystal oscillator output. A quartz crystal or a ceramic resonator must be
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
O
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Hardware Features
7
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL
PT NO.
I/O/Z
DESCRIPTION
NAME
DA NO.
RESET
Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in
power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external
circuitry is needed to generate a reset pulse. During a power-on or brown-out
condition, this pin is driven low by the device. See the electrical section for thresholds
of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset
occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset
duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this
pin to assert a device reset. In this case, it is recommended that this pin be driven by
an open-drain device An R-C circuit must be connected to this pin for noise immunity
reasons. Regardless of the source, a device reset causes the device to terminate
execution. The program counter points to the address contained at the location
0x3FFFC0. When reset is deactivated, execution begins at the location designated by
the program counter. The output buffer of this pin is an open-drain with an internal
pullup. (I/OD)
XRS
3
17
I/O
ADC, COMPARATOR, ANALOG I/O
ADCINA7
6
4
I
ADC Group A, Channel 7 input
ADCINA6
AIO6
I
ADC Group A, Channel 6 input
Digital AIO 6
18
I/O
ADCINA4
COMP2A
AIO4
I
I
ADC Group A, Channel 4 input
Comparator Input 2A
Digital AIO 4
5
7
19
–
I/O
ADCINA3
I
ADC Group A, Channel 3 input
ADCINA2
COMP1A
AIO2
I
I
ADC Group A, Channel 2 input
Comparator Input 1A
Digital AIO 2
9
20
–
I/O
ADCINA1
8
I
ADC Group A, Channel 1 input
ADC Group A, Channel 0 input
ADC External Reference – only used when in ADC external reference mode. See
ADC Section.
ADCINA0
VREFHI
I
I
10
21
ADCINB7
18
17
–
I
ADC Group B, Channel 7 input
ADCINB6
AIO14
I
ADC Group B, Channel 6 input
Digital AIO 14
26
I/O
ADCINB4
COMP2B
AIO12
I
I
ADC Group B, Channel 4 input
Comparator Input 2B
Digital AIO12
16
15
14
13
25
–
I/O
ADCINB3
I
ADC Group B, Channel 3 input
ADCINB2
COMP1B
AIO10
I
I
ADC Group B, Channel 2 input
Comparator Input 1B
Digital AIO 10
24
–
I/O
ADCINB1
I
ADC Group B, Channel 1 input
CPU AND I/O POWER
Analog Power Pin
VDDA
11
12
22
23
VSSA
VREFLO
Analog Ground Pin
ADC Low Reference (always tied to ground)
I
VDD
VDD
VDDIO
VSS
32
43
35
33
44
1
11
4
CPU and Logic Digital Power Pins – no supply source needed when using internal
VREG. Tie with 1.2 µF ceramic capacitor to ground when using internal VREG.
Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled
Digital Ground Pins
2
VSS
12
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ
GPIO0
34
29
3
I
Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG
GPIO AND PERIPHERAL SIGNALS
37
I/O/Z
General purpose input/output 0
8
Hardware Features
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL
PT NO.
I/O/Z
DESCRIPTION
NAME
EPWM1A
–
DA NO.
O
–
Enhanced PWM1 Output A and HRPWM channel
–
–
–
–
GPIO1
EPWM1B
–
28
37
38
39
40
41
36
5
I/O/Z
O
General purpose input/output 1
Enhanced PWM1 Output B
–
COMP1OUT
GPIO2
EPWM2A
–
O
Direct output of Comparator 1
General purpose input/output 2
Enhanced PWM2 Output A and HRPWM channel
–
I/O/Z
O
–
–
GPIO3
EPWM2B
–
6
I/O/Z
O
General purpose input/output 3
Enhanced PWM2 Output B
–
COMP2OUT
GPIO4
EPWM3A
–
O
I/O/Z
O
Direct output of Comparator 2
General purpose input/output 4
Enhanced PWM3 output A and HRPWM channel
–
7
–
–
GPIO5
EPWM3B
–
8
I/O/Z
O
General purpose input/output 5
Enhanced PWM3 output B
–
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
I/O
Enhanced Capture input/output 1
General purpose input/output 6
Enhanced PWM4 output A and HRPWM channel
External ePWM sync pulse input
External ePWM sync pulse output
General purpose input/output 7
Enhanced PWM4 output B
SCI-A receive data
9
I/O/Z
O
I
O
EPWMSYNCO
GPIO7
EPWM4B
SCIRXDA
–
42
47
27
26
24
10
13
35
34
32
I/O/Z
O
I
–
GPIO12
TZ1
I/O/Z
General purpose input/output 12
Trip Zone input 1
I
SCITXDA
–
O
SCI-A transmit data
–
GPIO16
SPISIMOA
–
I/O/Z
I/O
General purpose input/output 16
SPI slave in, master out
–
TZ2
I
Trip Zone input 2
GPIO17
SPISOMIA
–
I/O/Z
I/O
General purpose input/output 17
SPI-A slave out, master in
–
TZ3
I
Trip zone input 3
GPIO18
SPICLKA
SCITXDA
I/O/Z
I/O
O
General purpose input/output 18
SPI-A clock input/output
SCI-A transmit
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Hardware Features
9
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL
PT NO.
I/O/Z
DESCRIPTION
NAME
DA NO.
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,
one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled
by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to
3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
XCLKOUT
O/Z
GPIO19
XCLKIN
25
33
I/O/Z
General purpose input/output 19
External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken not to enable this path for clocking if it is
being used for the other periperhal functions
SPISTEA
SCIRXDA
ECAP1
GPIO28
SCIRXDA
SDAA
I/O
I
SPI-A slave transmit enable input/output
SCI-A receive
I/O
I/O/Z
I
Enhanced Capture input/output 1
General purpose input/output 28
SCI receive data
48
1
14
15
-
I/OC
I
I2C data open-drain bidirectional port
Trip zone input 2
TZ2
GPIO29
SCITXDA
SCLA
I/O/Z
O
General purpose input/output 29.
SCI transmit data
I/OC
I
I2C clock open-drain bidirectional port
Trip zone input 3
TZ3
GPIO32
SDAA
31
36
I/O/Z
I/OC
I
General purpose input/output 32
I2C data open-drain bidirectional port
Enhanced PWM external sync pulse input
ADC start-of-conversion A
General-Purpose Input/Output 33
I2C clock open-drain bidirectional port
Enhanced PWM external synch pulse output
ADC start-of-conversion B
General-Purpose Input/Output 34
Direct output of Comparator 2
–
EPWMSYNCI
ADCSOCAO
GPIO33
SCLA
O
–
I/O/Z
I/OC
O
EPWMSYNCO
ADCSOCBO
GPIO34
COMP2OUT
–
O
19
27
I/O/Z
O
–
–
GPIO35
20
21
22
23
28
29
30
31
I/O/Z
I
General-Purpose Input/Output 35
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK
TDI
GPIO36
TMS
I/O/Z
I
General-Purpose Input/Output 36
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked
into the TAP controller on the rising edge of TCK.
GPIO37
TDO
I/O/Z
O/Z
General-Purpose Input/Output 37
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
GPIO38
TCK
I/O/Z
I
General-Purpose Input/Output 38
JTAG test clock with internal pullup
External Oscillator Input. The path from this pin to the clock block is not gated by the
mux function of this pin. Care must be taken to not enable this path for clocking if it is
being used for the other periperhal functions.
XCLKIN
I
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3 Functional Overview
3.1 Block Diagram
M0
SARAM 1K x 16
(0-wait)
OTP 1K x 16
Secure
SARAM
4K x 16
M1
SARAM 1K x 16
(0-wait)
(0-wait)
Secure
FLASH
Code
16K/32K x 16
Security
Secure
Module
Boot-ROM
8K x 16
(0-wait)
OTP/Flash
Wrapper
PSWD
Memory Bus
TRST
TCK
TDI
TMS
COMP1OUT
GPIO
C28x
COMP2OUT
32-bit CPU
TDO
MUX
GPIO
Mux
COMP1A
COMP1B
COMP2A
COMP2B
COMP
3 External Interrupts
XCLKIN
PIE
OSC1,
OSC2,
Ext,
CPU Timer 0
CPU Timer 1
CPU Timer 2
Memory Bus
X1
X2
AIO
MUX
PLL,
LPM,
WD
LPM Wakeup
XRS
ADC
A7:0
B7:0
POR/
BOR
VREG
32-bit Peripheral Bus
16-bit Peripheral Bus
32-Bit Peripheral Bus
EPWM
SCI
SPI
(4L FIFO)
I2C
ECAP
(4L FIFO)
(4L FIFO)
HRPWM
From
COMP1OUT,
COMP2OUT
GPIO MUX
Figure 3-1. Functional Block Diagram
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3.2 Memory Maps
In Figure 3-2, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data
memory only. A user program cannot access these memory maps in program space.
•
Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
•
•
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Locations 0x3D7C80 – 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 1000
0x00 6000
M0 Vector RAM (Enabled if VMAP=0)
M0 SARAM (1K x 16, 0-Wait)
M1 SARAM (1K x 16, 0-Wait)
Peripheral Frame 0
Reserved
Reserved
Peripheral Frame 1
(4K x 16, Protected)
0x00 7000
0x00 8000
Peripheral Frame 2
(4K x 16, Protected)
Reserved
L0 SARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0F00 9000
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K x 16, Secure Zone + ECSL)
Reserved
Calibration Data
0x3D 7CC0
0x3D 8000
Reserved
0x3F 0000
FLASH
(32K x 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP=1)
Figure 3-2. 28023/28025/28027 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector RAM (Enabled if VMAP=0)
M0 SARAM (1K x 16, 0-Wait)
0x00 0400
0x00 0800
M1 SARAM (1K x 16, 0-Wait)
Reserved
Peripheral Frame 0
0x00 1000
0x00 6000
Reserved
Peripheral Frame 1
(4K x 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K x 16, Protected)
L0 SARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0F00 9000
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K x 16, Secure Zone + ECSL)
Calibration Data
0x3D 7CC0
0x3D 8000
Reserved
0x3F 4000
FLASH
(16K x 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (4K x 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K x 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP=1)
Figure 3-3. 28022/28024/28026 Memory Map
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Table 3-1. Addresses of Flash Sectors in F28023/28025/28027
ADDRESS RANGE
0x3F 0000 - 0x3F 1FFF
0x3F 2000 - 0x3F 3FFF
0x3F 4000 - 0x3F 5FFF
0x3F 6000 - 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (8K x 16)
Sector C (8K x 16)
Sector B (8K x 16)
Sector A (8K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 - 0x3F 7FF5
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 3-2. Addresses of Flash Sectors in F28022/28024/28026
ADDRESS RANGE
0x3F 4000 - 0x3F 4FFF
0x3F 5000 - 0x3F 5FFF
0x3F 6000 - 0x3F 6FFF
0x3F 7000 - 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (4K x 16)
Sector C (4K x 16)
Sector B (4K x 16)
Sector A (4K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 - 0x3F 7FF5
0x3F 7FF6 - 0x3F 7FF7
0x3F 7FF8 - 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
NOTE
•
•
When the code-security passwords are programmed, all addresses between
0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF
may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for
data and should not contain program code.
Table 3-3 shows how to handle these memory locations.
Table 3-3. Impact of Using the Code Security Module
ADDRESS
FLASH
Code security enabled
Code security disabled
Application code and data
Reserved for data only
0x3F 7F80 - 0x3F 7FEF
0x3F 7FF0 - 0x3F 7FF5
Fill with 0x0000
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as
written. Because of the pipeline, a write immediately followed by a read to different memory locations, will
appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block
protection mode where a region of memory can be protected so that operations occur as written (the
penalty is extra cycles are added to align the operations). This mode is programmable and by default, it
protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-4.
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Table 3-4. Wait-states
AREA
WAIT-STATES (CPU)
0-wait
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Fixed
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait data and program
Programmable
1-wait minimum
Programmable
0-wait Paged min
Cycles can be extended by peripheral generated ready.
Fixed. Cycles cannot be extended by the peripheral.
Peripheral Frame 2
L0 SARAM
OTP
Assumes no CPU conflicts
Programmed via the Flash registers.
1-wait is minimum number of wait states allowed.
Programmed via the Flash registers.
FLASH
1-wait Random min
Random ≥ Paged
FLASH Password
Boot-ROM
16-wait fixed
0-wait
Wait states of password locations are fixed.
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3.3 Brief Descriptions
3.3.1 CPU
The 2802x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The
C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level
language, but also enabling development of math algorithms using C/C++. The device is as efficient at
MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit
processing capabilities enable the controller to handle higher numerical resolution problems efficiently.
Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at
high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
3.3.2 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory
bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory
bus.)
Data Reads
Program
Reads
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
3.3.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are
supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1).
3.3.4 Real-Time JTAG and Analysis
The devices implement the standard IEEE 1149.1 JTAG(1) interface for in-circuit based debug.
Additionally, the devices support real-time mode of operation allowing modification of the contents of
memory, peripheral, and register locations while the processor is running and executing code and
servicing interrupts. The user can also single step through non-time-critical code while enabling
time-critical interrupts to be serviced without interference. The device implements the real-time mode in
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software
monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or
data/address watch-points and generating various user-selectable break events when a match occurs.
These devices do not support boundary scan; however, IDCODE and BYPASS features are available if
the following considerations are taken into account. The IDCODE does not come by default. The user
needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For
BYPASS instruction, the first shifted DR value would be 1.
3.3.5 Flash
The F28027/25/23 devices contain 32K x 16 of embedded flash memory, segregated into four 8K x 16
sectors. The F28026/24/22 devices contain 16K x 16 of embedded flash memory, segregated into four 4K
x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 –
0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other
sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash
algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash
module to achieve higher performance. The flash/OTP is mapped to both program and data space;
therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5
are reserved for data variables and should not contain program code.
NOTE
The Flash and OTP wait-states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x2802x System Control and Interrupts Reference Guide (literature
number SPRUFN3).
3.3.6 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
3.3.7 L0 SARAM
The device contains 4K x 16 of single-access memory. This block is mapped to both program and data
space.
3.3.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math-related algorithms.
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Table 3-5. Boot Mode Selection
MODE
GPIO37/TDO
GPIO34/CMP2OUT
TRST
MODE
3
2
1
1
0
0
x
1
0
1
0
x
0
0
0
0
1
GetMode
Wait (see Section 3.3.9 for description)
1
SCI
0
Parallel IO
Emulation Boot
EMU
3.3.8.1 Emulation Boot
When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM
locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
3.3.8.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another
boot option by programming two locations in the OTP. One of the following loaders can be specified: SCI,
SPI, I2C, or OTP. If the content of either OTP location is invalid, then boot to flash is used
3.3.9 Security
The devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents via the JTAG port,
executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct
128-bit KEY value that matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0
memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in
the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the
password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (i.e., secured), the
CPU will start running and may execute an instruction that performs an access to a protected ECSL area.
If this happens, the ECSL will trip and cause the emulator connection to be cut.
The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an
emulator to be connected without tripping security. The user can then exit this mode once the emulator is
connected by using one of the emulation boot options as described in the TMS320x2802x Boot ROM
Reference Guide (SPRUFN6). Piccolo devices do not support a hardware wait-in-reset mode.
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NOTE
•
•
When the code-security passwords are programmed, all addresses between
0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations
must be programmed to 0x0000.
If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may
be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and
should not contain program code.
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS
INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND
CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE
WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER,
EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN
ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
3.3.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.3.11 External Interrupts (XINT1-XINT3)
The devices support three masked external interrupts (XINT1-XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0 – GPIO31 pins.
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3.3.12 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to
12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to
scale back on operating frequency if lower power operation is desired. Refer to the Electrical Specification
section for timing details. The PLL block can be set in bypass mode.
3.3.13 Watchdog
Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a
certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog
can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
3.3.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled
relative to the CPU clock.
3.3.15 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
This mode basically shuts down the device and places it in the lowest possible power
consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting
down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip
crystal oscillator is used as the clock source, it is shut down in this mode. A reset or
an external signal (through a GPIO pin) or the CPU-watchdog can wake the device
from this mode.
3.3.16 Peripheral Frames 0, 1, 2 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
Flash:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
Timers:
CSM:
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC Result Registers
ADC:
PF1: GPIO:
ePWM:
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
Enhanced Capture Module and Registers
Comparator Modules
eCAP:
Comparators:
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PF2: SYS:
System Control Registers
SCI:
SPI:
ADC:
I2C:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Configuration Registers
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
XINT
3.3.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.3.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
connected to INT14 of the CPU. It can be clocked by any one of the following:
•
•
•
•
SYSCLKOUT (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTSOC2)
External clock source
CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for
general use and is connected to the PIE block.
3.3.19 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the
HRPWM high resolution duty and period features. The type 1 module found on
2802x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP:
ADC:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned
out, depending on the device. It contains two sample-and-hold units for
simultaneous sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal
10-bit reference for supplying one input of the comparator.
3.3.20 Serial Port Peripherals
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The devices support the following serial communication peripherals:
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (one to sixteen bits) to be shifted into and out of the device
at a programmable bit-transfer rate. Normally, the SPI is used for communications
between the MCU and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multi-device communications are
supported by the master/slave operation of the SPI. The SPI contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 4-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a MCU
and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)
specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data
to/from the MCU through the I2C module. The I2C contains a 4-level receive and
transmit FIFO for reducing interrupt servicing overhead.
3.4 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See
Table 3-6.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-7.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-8.
Table 3-6. Peripheral Frame 0 Registers(1)
NAME
ADDRESS RANGE
0x00 0880 - 0x00 09FF
0x00 0A80 - 0x00 0ADF
0x00 0AE0 - 0x00 0AEF
0x00 0B00 - 0x00 0B0F
SIZE (×16)
EALLOW PROTECTED(2)
Device Emulation Registers
FLASH Registers(3)
Code Security Module Registers
384
96
Yes
Yes
Yes
No
16
ADC registers
16
0 wait read only
CPU–TIMER0/1/2 Registers
PIE Registers
0x00 0C00 - 0x00 0C3F
0x00 0CE0 - 0x00 0CFF
0x00 0D00 - 0x00 0DFF
64
32
No
No
No
PIE Vector Table
256
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
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Table 3-7. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6400 - 0x00 641F
0x00 6420 - 0x00 643F
0x00 6800 - 0x00 683F
0x00 6840 - 0x00 687F
0x00 6880 - 0x00 68BF
0x00 68C0 - 0x00 68FF
0x00 6A00 - 0x00 6A1F
0x00 6F80 - 0x00 6FFF
SIZE (×16)
EALLOW PROTECTED
(1)
Comparator 1 registers
Comparator 2 registers
EPWM1 + HRPWM1 registers
EPWM2 + HRPWM2 registers
EPWM3 + HRPWM3 registers
EPWM4 + HRPWM4 registers
ECAP1 registers
32
32
64
64
64
64
32
128
(1)
(1)
(1)
(1)
(1)
No
(1)
GPIO registers
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 3-8. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
0x00 7010 - 0x00 702F
0x00 7040 - 0x00 704F
0x00 7050 - 0x00 705F
0x00 7060 - 0x00 706F
0x00 7070 - 0x00 707F
0x00 7100 - 0x00 717F
0x00 7900 - 0x00 793F
SIZE (×16)
EALLOW PROTECTED
System Control Registers
SPI-A Registers
32
16
16
16
16
32
64
Yes
No
SCI-A Registers
No
NMI Watchdog Interrupt Registers
External Interrupt Registers
ADC Registers
Yes
Yes
(1)
(1)
I2C-A Registers
(1) Some registers are EALLOW protected. See the module reference guide for more information.
3.5 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-9.
Table 3-9. Device Emulation Registers
ADDRESS
RANGE
EALLOW
PROTECTED
NAME
SIZE (x16)
DESCRIPTION
Device Configuration Register
0x0880
0x0881
DEVICECNF
CLASSID
2
1
Yes
0x0882
Class ID Register
TMS320F28027
TMS320F28026
TMS320F28025
TMS320F28024
TMS320F28023
TMS320F28022
0x00CF
0x00C7
0x00CF
0x00C7
0x00CF
0x00C7
No
REVID
0x0883
1
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMX
No
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3.6 Interrupts
Figure 3-4 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, EPWM, I2C,
HRPWM, ECAP, ADC)
WDINT
Watchdog
Low Power Modes
WAKEINT
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Interrupt Control
XINT1CR(15:0)
XINT2CTR(15:0)
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
INT1
to
INT12
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT3CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
TINT0
XINT3
GPIO
MUX
Interrupt Control
XINT3CR(15:0)
XINT3CTR(15:0)
GPIO31.int
GPIOXINT3SEL(4:0)
CPU TIMER 0
CPU TIMER 1
CPU TIMER 2
TINT1
TINT2
INT13
INT14
CPUTMR2CLK
CLOCKFAIL
NMIRS
System Control
(See the system
control section)
NMI interrupt with watchdog function
(See the NMI watchdog section)
NMI
Figure 3-4. External and PIE Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. Table 3-10 shows the interrupts used by 2802x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
INTx
Peripherals or
External
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-5. Multiplexing of Interrupts Using the PIE Block
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Table 3-10. PIE MUXed Peripheral Interrupt Vector Table
INTx.8
WAKEINT
(LPM/WD)
0xD4E
Reserved
–
INTx.7
TINT0
(TIMER 0)
0xD4C
Reserved
–
INTx.6
ADCINT9
(ADC)
0xD4A
Reserved
–
INTx.5
XINT2
Ext. int. 2
0xD48
Reserved
–
INTx.4
XINT1
Ext. int. 1
0xD46
EPWM4_TZINT
(ePWM4)
0xD56
EPWM4_INT
(ePWM4)
0xD66
Reserved
–
INTx.3
Reserved
–
INTx.2
ADCINT2
(ADC)
INTx.1
ADCINT1
(ADC)
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
INT11.y
INT12.y
0xD44
EPWM3_TZINT
(ePWM3)
0xD54
EPWM3_INT
(ePWM3)
0xD64
Reserved
–
0xD42
0xD40
EPWM2_TZINT
(ePWM2)
0xD52
EPWM1_TZINT
(ePWM1)
0xD50
0xD5E
Reserved
–
0xD5C
Reserved
–
0xD5A
Reserved
–
0xD58
Reserved
–
EPWM2_INT
(ePWM2)
0xD62
EPWM1_INT
(ePWM1)
0xD60
0xD6E
Reserved
–
0xD6C
Reserved
–
0xD6A
Reserved
–
0xD68
Reserved
–
Reserved
–
ECAP1_INT
(eCAP1)
0xD70
0xD7E
Reserved
–
0xD7C
Reserved
–
0xD7A
Reserved
–
0xD78
Reserved
–
0xD76
Reserved
–
0xD74
Reserved
–
0xD72
Reserved
–
Reserved
–
0xD8E
Reserved
–
0xD8C
Reserved
–
0xD8A
Reserved
–
0xD88
Reserved
–
0xD86
Reserved
–
0xD84
Reserved
–
0xD82
0xD80
SPITXINTA
(SPI-A)
0xD92
SPIRXINTA
(SPI-A)
0xD90
0xD9E
Reserved
–
0xD9C
Reserved
–
0xD9A
Reserved
–
0xD98
Reserved
–
0xD96
Reserved
–
0xD94
Reserved
–
Reserved
–
Reserved
–
0xDAE
Reserved
–
0xDAC
Reserved
–
0xDAA
Reserved
–
0xDA8
Reserved
–
0xDA6
Reserved
–
0xDA4
Reserved
–
0xDA2
0xDA0
I2CINT2A
(I2C-A)
0xDB2
I2CINT1A
(I2C-A)
0xDBE
Reserved
–
0xDBC
Reserved
–
0xDBA
Reserved
–
0xDB8
Reserved
–
0xDB6
Reserved
–
0xDB4
Reserved
–
0xDB0
SCITXINTA
(SCI-A)
0xDC2
SCIRXINTA
(SCI-A)
0xDC0
0xDCE
ADCINT8
(ADC)
0xDDE
Reserved
–
0xDCC
ADCINT7
(ADC)
0xDDC
Reserved
–
0xDCA
ADCINT6
(ADC)
0xDDA
Reserved
–
0xDC8
ADCINT5
(ADC)
0xDD8
Reserved
–
0xDC6
ADCINT4
(ADC)
0xDC4
ADCINT3
(ADC)
0xDD4
Reserved
–
ADCINT2
(ADC)
ADCINT1
(ADC)
0xDD6
Reserved
–
0xDD2
0xDD0
Reserved
–
Reserved
–
0xDEE
Reserved
–
0xDEC
Reserved
–
0xDEA
Reserved
–
0xDE8
Reserved
–
0xDE6
Reserved
–
0xDE4
Reserved
–
0xDE2
0xDE0
Reserved
–
XINT3
Ext. Int. 3
0xDF0
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
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Table 3-11. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (x16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
3.6.1 External Interrupts
Table 3-12. External Interrupt Registers
NAME
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7078
0x00 7079
0x00 707A
SIZE (x16)
DESCRIPTION
XINT1CR
XINT2CR
XINT3CR
XINT1CTR
XINT2CTR
XINT3CTR
1
1
1
1
1
1
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT1 counter register
XINT2 counter register
XINT3 counter register
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2802x System and Interrupts Reference Guide
(literature number SPRUFN3).
3.7 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode,
eliminating a need for any external voltage supervisory circuits.
3.7.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
3.7.1.1 Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be pulled low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 µF capacitance
for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD
pins.
3.7.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be
pulled high.
3.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device
operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device
power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is
enabled (VREGENZ pin is pulled low). Both functions pull the XRS pin low when one of the voltages is
below their respective trip point. See the Section 6 for the various trip points as well as the delay time from
the voltage rising past the trip point and the release of the XRS pin. Figure 3-6 shows the VREG, POR,
and BOR.
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In
I/O Pin
Out
(Force HI-Z When High)
DIR (0 = Input, 1 = Output)
SYSRS
Internal
Weak PU
SYSCLKOUT
Deglitch
Filter
XRS
Sync
RS
C28
Core
MCLKRS
PLL
JTAG
TCK
Detect
Logic
XRS
Pin
+
Clocking
Logic
VREGHALT
WDRST(A)
PBRS(B)
POR/BOR
Generating
Module
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
A. WDRST is the reset signal from the CPU-watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 3-6. VREG + POR + BOR + Reset Signal Connectivity
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3.8 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low power
modes. Figure 3-7 shows the various clock domains that are discussed. Figure 3-8 shows the various
clock sources (both internal and external) that can provide a clock for device operation.
SYSCLKOUT
PCLKCR0/1/3
(System Ctrl Regs)
LOSPCP
(System Ctrl Regs)
C28x Core
CLKIN
Clock Enables
LSPCLK
Peripheral
Registers
SPI-A, SCI-A
I/O
I/O
I/O
I/O
PF2
Clock Enables
eCAP1
Peripheral
Registers
PF1
PF1
PF2
GPIO
Mux
Clock Enables
ePWM1/.../4
Clock Enables
I2C-A
Peripheral
Registers
Peripheral
Registers
Clock Enables
ADC
Registers
PF2
PF0
16 Ch
12-Bit ADC
Analog
GPIO
Mux
Clock Enables
COMP1/2
COMP
Registers
6
PF1
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-7. Clock and Reset Domains
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CLKCTL[WDCLKSRCSEL]
0
Internal
OSC 1
(10 MHz)
OSC1CLK
OSCCLKSRC1
INTOSC1TRIM Reg(A)
WDCLK
CPU-watchdog
(OSC1CLK on XRS reset)
1
OSCE
CLKCTL[INTOSC1OFF]
1 = Turn OSC Off
CLKCTL[OSCCLKSRCSEL]
CLKCTL[INTOSC1HALT]
1 = Ignore HALT
WAKEOSC
OSC2CLK
0
Internal
OSC 2
(10 MHz)
INTOSC2TRIM Reg(A)
OSCCLK
PLL/Missing
Clock-detect circuit(B)
(OSC1CLK on XRS reset)
1
OSCE
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
1 = Turn OSC Off
10
11
CLKCTL[INTOSC2OFF]
Prescale
/1, /2, /4,
/8, /16
SYNC
Edge
Detect
01, 10, 11
CPUTMR2CLK
1 = Ignore HALT
01
1
0
00
CLKCTL[INTOSC2HALT]
SYSCLKOUT
OSCCLKSRC2
CLKCTL[OSCCLKSRC2SEL]
0 = GPIO38
1 = GPIO19
XCLK[XCLKINSEL]
CLKCTL[XCLKINOFF]
0
1
0
GPIO19
or
XCLKIN
GPIO38
XCLKIN
X1
X2
EXTCLK
(Crystal)
OSC
WAKEOSC
(Oscillators enabled when this signal is high)
XTAL
0 = OSC on (default on reset)
1 = Turn OSC off
CLKCTL[XTALOSCOFF]
A. Register loaded from TI OTP-based calibration function.
B. See Section 3.8.4 for details on missing clock detection.
Figure 3-8. Clock Tree
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3.8.1 Internal Zero Pin Oscillators
The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are
turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,
unused oscillators may be powered down by the user. The center frequency of these oscillators is
determined by their respective oscillator trim registers, written to in the calibration routine as part of the
boot ROM execution. See the electrical section for more information on these oscillators.
3.8.2 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 10 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
0x00 7010
0x00 7011
0x00 7012
0x00 7013
0x00 7014
0x00 7016
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7025
0x00 7029
SIZE (x16)
DESCRIPTION(1)
XCLK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XCLKOUT Control
PLLSTS
PLL Status Register
CLKCTL
Clock Control Register
PLLLOCKPRD
INTOSC1TRIM
INTOSC2TRIM
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
PCLKCR3
PLLCR
PLL Lock Period
Internal Oscillator 1 Trim Register
Internal Oscillator 2 Trim Register
Low-Speed Peripheral Clock Prescaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Peripheral Clock Control Register 3
PLL Control Register
SCSR
System Control and Status Register
Watchdog Counter Register
Watchdog Reset Key Register
Watchdog Control Register
WDCNTR
WDKEY
WDCR
(1) All registers in this table are EALLOW protected.
XCLKIN/GPIO19/38
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
Figure 3-9. Using a 3.3-V External Oscillator
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XCLKIN/GPIO19/38
X1
X2
Turn off
C
C
L2
L1
XCLKIN path
in CLKCTL
register
Crystal
A. X1/X2 pins are available in 48-pin package only.
Figure 3-10. Using the On-chip Crystal Oscillator
3.8.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1
ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the
PLL (VCOCLK) is at least 50 MHz.
Table 3-14. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(1) (2)
PLLSTS[DIVSEL] = 0 or 1(3)
OSCCLK/4 (Default)(1)
(OSCCLK * 1)/4
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3
0000 (PLL bypass)
0001
OSCCLK
(OSCCLK * 1)/2
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
(OSCCLK * 11)/2
(OSCCLK * 12)/2
–
–
–
–
–
–
–
–
–
–
–
–
0010
(OSCCLK * 2)/4
0011
(OSCCLK * 3)/4
0100
(OSCCLK * 4)/4
0101
(OSCCLK * 5)/4
0110
(OSCCLK * 6)/4
0111
(OSCCLK * 7)/4
1000
(OSCCLK * 8)/4
1001
(OSCCLK * 9)/4
1010
(OSCCLK * 10)/4
(OSCCLK * 11)/4
(OSCCLK * 12)/4
1011
1100
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the TMS320x2802x System and Interrupts Reference Guide (literature number SPRUFN3 ) for
more information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 3-15. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1(1)
(1) This mode can be used only when the PLL is bypassed or off.
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The PLL-based clock module provides four modes of operation:
•
INTOSC1 (Internal zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide
the clock for the Watchdog block, core and CPU-Timer 2
•
INTOSC2 (Internal zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide
the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
•
•
Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-2 for details.
External clock source operation: If the on-chip (crystal) oscillator is not used, this mode allows it to
be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.
Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit
disables this clock input (forced low). If the clock source is not used or the respective pins are used as
GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 3-16. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
OSCCLK*n/4
OSCCLK*n/2
3.8.4 Loss of Input Clock (NMI watchdog function)
The 2802x devices may be clocked from either one of the internal zero-pin oscillators
(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the
clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will
issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at
a typical frequency of 1-5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the
Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect
the input clock failure and initiate necessary corrective action such as switching over to an alternative
clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 3-11 shows the interrupt mechanisms involved.
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NMIFLG[NMINT]
NMIFLGCLR[NMINT]
Clear
Latch
Set
Clear
XRS
Generate
Interrupt
Pulse
When
Input = 1
NMIFLG[CLOCKFAIL]
Clear
Latch
1
0
0
NMIFLGCLR[CLOCKFAIL]
CLOCKFAIL
NMINT
SYNC?
Set
Clear
SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
See System
Control Section
NMI Watchdog
NMIRS
Figure 3-11. NMI-watchdog
3.8.5 CPU-Watchdog Module
The CPU-watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets
the watchdog counter. Figure 3-12 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a
CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog
counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock).
NOTE
The CPU-watchdog counter is different from the NMI watchdog. It is the legacy watchdog
counter that is present in all 28x devices.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the MCU will be held in reset, should the input clocks
ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU,
should the capacitor ever get fully charged. An I/O pin may be used to discharge the
capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would
also help in detecting failure of the flash memory.
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WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
WDCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Watchdog
55 + AA
Key Detector
Output Pulse
(512 OSCCLKs)
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-12. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that it can wake the device from STANDBY (if enabled). See Section Section 3.9, Low-Power
Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
3.9 Low-power Modes Block
Table 3-17 summarizes the various modes.
Table 3-17. Low-power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, CPU-watchdog interrupt, any
enabled interrupt
IDLE
00
On
On
On
On
XRS, CPU-watchdog interrupt, GPIO
Port A signal, debugger(2)
STANDBY
HALT(3)
01
Off
Off
(CPU-watchdog still running)
Off
(on-chip crystal oscillator and
PLL turned off, zero-pin oscillator
and CPU-watchdog state
dependent on user code.)
XRS, GPIO Port A signal, debugger(2)
CPU-watchdog
,
1X
Off
Off
(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power
mode will not be exited and the device will go back into the indicated low power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
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The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt that is recognized by the
processor. The LPM block performs no tasks during this mode as long as
the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode:
CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake
the device from HALT mode. The user selects the signal in the
GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the TMS320x2802x System and Interrupts Reference Guide (literature
number SPRUFN3) for more details.
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4 Peripherals
4.1 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions.
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
38-Pin
VDDA
48-Pin
VDDA
VREFLO VREFLO
Tied To Tied To
Interface Reference
Diff
VSSA
VSSA
VREFHI VREFHI
Tied To Tied To
VREFHI
A0
B0
A0
A2
A4
A6
A0
A1
A2
A3
A4
A1
B1
COMP1OUT
A2
AIO2
AIO10
10-Bit
DAC
Comp1
Comp2
B2
A6
A7
A3
B3
ADC
COMP2OUT
A4
B4
B1
B2
B3
B4
AIO4
AIO12
10-Bit
DAC
B2
B4
B6
B5
B6
B7
A5
A6
Signal Pinout
AIO6
AIO14
B6
A7
B7
Figure 4-1. Analog Pin Configurations
Figure 4-2 shows the interaction of the analog module with the rest of the F2802x system.
4.1.1 ADC
Table 4-1. ADC Configuration and Control Registers
REGISTER NAME
ADDRESS
SIZE
(x16)
EALLOW
PROTECTED
DESCRIPTION
ADCCTL1
0x7100
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x7110
0x7112
0x7114
0x7115
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Yes
No
Control 1 Register
ADCINTFLG
Interrupt Flag Register
ADCINTFLGCLR
ADCINTOVF
No
Interrupt Flag Clear Register
No
Interrupt Overflow Register
ADCINTOVFCLR
ADCINTSEL1AND2
ADCINTSEL3AND4
ADCINTSEL5AND6
ADCINTSEL7AND8
ADCINTSEL9AND10
ADCSOCPRIORITYCTL
ADCSAMPLEMODE
ADCINTSOCSEL1
ADCINTSOCSEL2
No
Interrupt Overflow Clear Register
Interrupt 1 and 2 Selection Register
Interrupt 3 and 4 Selection Register
Interrupt 5 and 6 Selection Register
Interrupt 7 and 8 Selection Register
Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOC Priority Control Register
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Sampling Mode Register
Interrupt SOC Selection 1 Register (for 8 channels)
Interrupt SOC Selection 2 Register (for 8 channels)
38
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Table 4-1. ADC Configuration and Control Registers (continued)
REGISTER NAME
ADDRESS
SIZE
(x16)
EALLOW
PROTECTED
DESCRIPTION
ADCSOCFLG1
ADCSOCFRC1
ADCSOCOVF1
ADCSOCOVFCLR1
0x7118
0x711A
0x711C
0x711E
1
1
1
1
1
No
No
SOC Flag 1 Register (for 16 channels)
SOC Force 1 Register (for 16 channels)
No
SOC Overflow 1 Register (for 16 channels)
SOC Overflow Clear 1 Register (for 16 channels)
SOC0 Control Register to SOC15 Control Register
No
ADCSOC0CTL to
ADCSOC15CTL
0x7120 -
0x712F
Yes
ADCREFTRIM
ADCOFFTRIM
ADCREV
0x7140
0x7141
0x714F
1
1
1
Yes
Yes
No
Reference Trim Register
Offset Trim Register
Revision Register
Table 4-2. ADC Result Registers (mapped to PF0)
Name
Address
Size (x16)
EALLOW Description
Protected
ADCRESULT0 to
ADCRESULT15
0xB00 -
0xB0F
1
No
ADC Result 0 Register to ADC Result 15 Register
0-Wait
Result
Registers
PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
TINT 0
TINT 1
TINT 2
ADC
Core
12-Bit
CPUTIMER 0
CPUTIMER 1
CPUTIMER 2
AIO
MUX
ADC
Channels
ADCTRIG 1
ADCTRIG 2
ADCTRIG 3
XINT 2SOC
XINT 2
EPWM 1
EPWM 2
EPWM 3
EPWM 4
ADCTRIG 4
SOCA 1
SOCB 1
SOCA 2
SOCB 2
SOCA 3
SOCB 3
SOCA 4
SOCB 4
ADCTRIG 5
ADCTRIG 6
ADCTRIG 7
ADCTRIG 8
ADCTRIG 9
ADCTRIG 10
ADCTRIG 11
ADCTRIG 12
Figure 4-2. ADC Connections
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4.1.2 ADC MUX
To COMPy A or B input
To ADC Channel X
Logic implemented in GPIO MUX block
AIOx Pin
SYSCLK
AIOxIN
1
AIOxINE
AIODAT Reg
(Read)
SYNC
0
AIODAT Reg
(Latch)
AIOSET,
AIOCLEAR,
AIOTOGGLE
Regs
AIOMUX 1 Reg
AIODIR Reg
(Latch)
1
1
(0 = Input, 1 = Output)
0
0
IORS
Figure 4-3. ADC MUX
The ADC channel and Comparator functions are always available. The digital I/O function is available only
when the respective bit in the AIOMUX1 register is set to 1. In this mode, reading the AIODAT register
reflects the actual pin state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is cleared to 0. In this
mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital
I/O buffer is disabled to prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO
function disabled for that pin.
4.1.3 Comparator Block
Figure 4-4 shows the interaction of the Comparator modules with the rest of the system
40
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COMP x A
COMP x B
+
COMP
-
TZ1/2/3
GPIO
MUX
COMP x
+
DAC x
Wrapper
EPWM
AIO
MUX
COMPxOUT
DAC
Core
10-Bit
Figure 4-4. Comparator Block Diagram
Table 4-3. Comparator Control Registers
REGISTER
NAME
COMP1 ADDRESS COMP2 ADDRESS
SIZE (x16)
EALLOW PROTECTED
DESCRIPTION
COMPCTL
COMPSTS
DACVAL
0x6400
0x6402
0x6406
0x6420
0x6422
0x6426
1
1
1
Yes
No
Comparator Control Register
Comparator Status Register
DAC Value Register
Yes
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
4.1 Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals
or another processor. Typical applications include external I/O or peripheral expansion through devices
such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
(SPIBRR ) 1)
LSPCLK
Baud rate =
4
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
•
•
•
4-level transmit/receive FIFO
Delayed transmit control
Bi-directional 3 wire SPI mode support
The SPI port operation is configured and controlled by the registers listed in Table 4-4.
42
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TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Table 4-4. SPI-A Registers
NAME
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (x16) EALLOW PROTECTED
DESCRIPTION(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPICCR
SPICTL
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
SPISTS
SPIBRR
SPI-A Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Figure 4-5 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO Registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
-----
SPIINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _3
16
SPIRXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3
TX Interrupt
Logic
TX FIFO Interrupt
-----
TX FIFO _1
SPITX
TX FIFO _0
16
SPI INT
ENA
16
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
TRIWIRE
SPIPRI.0
16
M
S
M
SPIDAT
Data Register
TW
S
SW1
SW2
SPISIMO
M
S
TW
SPIDAT.15 - 0
M
TW
S
SPISOMI
SPISTE
Talk
SPICTL.1
State Control
Master/Slave
SPICTL.2
SPI Char
LSPCLK
SPICCR.3 - 0
S
SW3
3
2
1
0
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPIBRR.6 - 0
SPICCR.6
SPICTL.3
SPICLK
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 4-5. SPI Module Block Diagram (Slave Mode)
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
4.2 Serial Communications Interface (SCI) Module
The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates:
–
LSPCLK
(BRR ) 1) * 8
Baud rate =
when BRR ≠ 0
when BRR = 0
LSPCLK
16
Baud rate =
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
4-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-5.
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Table 4-5. SCI-A Registers(1)
EALLOW
PROTECTED
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
SCICTL1A
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-A Communications Control Register
SCI-A Control Register 1
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
46
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Figure 4-6 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
Register
TXENA
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
SCICTL2.0
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
8
TX FIFO _0
TX FIFO
Interrupts
TXINT
TX Interrupt
Logic
TX FIFO _1
-----
To CPU
TX FIFO _3
SCI TX Interrupt select logic
SCITXBUF.7-0
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
RX FIFO _3
BRKDT
SCIRXST.5
-----
RX FIFO
Interrupts
RX FIFO_1
RX FIFO _0
RXINT
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-6. Serial Communications Interface (SCI) Module Block Diagram
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
4.3 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 4-7 shows how the I2C peripheral module interfaces
within the device.
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
•
•
One 4-word receive FIFO and one 4-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
I2C module
I2CXSR
I2CDXR
TX FIFO
FIFO Interrupt
to CPU/PIE
SDA
RX FIFO
Peripheral bus
I2CRSR
I2CDRR
Control/status
registers
CPU
Clock
SCL
synchronizer
Prescaler
Noise filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-7. I2C Peripheral Module Interfaces
The registers in Table 4-6 configure and control the I2C port operation.
Table 4-6. I2C-A Registers
EALLOW
PROTECTED
NAME
ADDRESS
DESCRIPTION
I2COAR
I2CIER
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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www.ti.com
4.4 Enhanced PWM Modules (ePWM1/2/3/4)
The devices contain up to four enhanced PWM Modules (ePWM). Figure 4-8 shows a block diagram of
multiple ePWM modules. Figure 4-8 shows the signal interconnections with the ePWM. See the
TMS320x2802x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number
SPRUGE9) for more details.
Table 4-7 shows the complete ePWM register set per module.
EPWMSYNCI
EPWM1SYNCI
EPWM1B
EPWM1TZINT
EPWM1
Module
TZ1 to TZ3
EPWM1NT
EWPM2TZINT
PIE
CLOCKFAIL
EMUSTOP
EPWM2INT
EPWMxTZINT
EPWMxINT
TZ5
TZ6
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM1SYNCI
EMWM1SYNCO
TZ1 to TZ3
COMPOUT1
COMPOUT2
EPWM1B
EPWM2
Module
COMP
CLOCKFAIL
EMUSTOP
EPWM1A
EPWM2A
TZ5
TZ6
H
R
P
W
M
EPWM2ENCLK
TBCLKSYNC
EPWMxA
G
P
I
EPWM2SYNCO
O
M
U
X
SOCA1
SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
ADC
EPWMxSYNCI
EPWMxB
TZ1 to TZ3
EPWMx
Module
CLOCKFAIL
EMUSTOP
TZ5
TZ6
EPWM1ENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2
SPCAx
ADCSOCAO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active Low Output)
SOCB1
SOCB2
SPCBx
ADCSOCBO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active Low Output)
Figure 4-8. ePWM
50
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Table 4-7. ePWM Control and Status Registers
SIZE (x16) /
NAME
EPWM1
EPWM2
EPWM3
EPWM4
DESCRIPTION
#SHADOW
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
TBCTL
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6806
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6813
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6846
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6853
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6886
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6893
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C6
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x98D3
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
Time Base Control Register
TBSTS
Time Base Status Register
TBPHSHR
TBPHS
TBCTR
TBPRD
TBPRDHR
CMPCTL
CMPAHR
CMPA
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Time Base Period High Resolution Register(1)
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
CMPB
Counter Compare B Register Set
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
TZDCSEL
TZCTL
Trip Zone Digital Compare Register
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZEINT
TZFLG
(1)
Trip Zone Flag Register
TZCLR
Trip Zone Clear Register(1)
TZFRC
ETSEL
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
(1) Registers that are EALLOW protected.
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Piccolo Microcontrollers
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SIZE (x16) /
#SHADOW
NAME
EPWM1
EPWM2
EPWM3
EPWM4
DESCRIPTION
HRPWM Power Register
HRPWR
0x6821
0x6826
0x6828
0x682A
0x682B
0x682C
0x682D
0x6830
0x6831
0x6832
0x6833
0x6834
0x6835
0x6836
0x6837
0x6838
0x6839
-
-
-
1 / 0
1 / 0
HRMSTEP
HRPCTL
-
-
-
HRPWM MEP Step Register
0x6868
0x686A
0x686B
0x686C
0x686D
0x6870
0x6871
0x6872
0x6873
0x6874
0x6875
0x6876
0x6877
0x6878
0x6879
0x68A8
0x68AA
0x68AB
0x68AC
0x68AD
0x68B0
0x68B1
0x68B2
0x68B3
0x68B4
0x68B5
0x68B6
0x68B7
0x68B8
0x68B9
0x68E8
0x68EA
0x68EB
0x68EC
0x68ED
0x68F0
0x68F1
0x68F2
0x68F3
0x68F4
0x68F5
0x68F6
0x68F7
0x68F8
0x68F9
1 / 0
High resolution Period Control Register(1)
Time Base Period HRPWM Register Mirror
Time Base Period Register Mirror
Compare A HRPWM Register Mirror
Compare A Register Mirror
TBPRDHRM
TBPRDM
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
1 / 0
CMPAHRM
CMPAM
(1)
DCTRIPSEL
DCACTL
Digital Compare Trip Select Register
1 / 0
Digital Compare A Control Register(1)
Digital Compare B Control Register(1)
Digital Compare Filter Control Register(1)
Digital Compare Capture Control Register(1)
Digital Compare Filter Offset Register
DCBCTL
1 / 0
DCFCTL
1 / 0
DCCAPCT
DCFOFFSET
DCFOFFSETCNT
DCFWINDOW
DCFWINDOWCNT
DCCAP
1 / 0
1 / 1
1 / 0
Digital Compare Filter Offset Counter Register
Digital Compare Filter Window Register
Digital Compare Filter Window Counter Register
Digital Compare Counter Capture Register
1 / 0
1 / 0
1 / 1
(2) W = Write to shadow register
52
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TMS320F28025, TMS320F28026, TMS320F28027
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Time-Base (TB)
CTR=ZERO
Sync
In/Out
Select
Mux
TBPRD Shadow (24)
TBPRD Active (24)
EPWMxSYNCO
CTR=CMPB
Disabled
TBPRDHR (8)
8
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
CTR_Dir
TCBNT
Active (16)
CTR=PRD
CTR=ZERO
CTR=PRD or ZERO
CTR=CMPA
TBPHSHR (8)
EPWMxINT
16
8
EPWMxSOCA
Phase
Control
CTR=CMPB
CTR_Dir
(A)
DCAEVT1.soc
(A)
TBPHS Active (24)
Event
Trigger
and
Interrupt
(ET)
EPWMxSOCB
EPWMxSOCA
ADC
DCBEVT1.soc
EPWMxSOCB
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
16
8
HiRes PWM (HRPWM)
CMPA Active (24)
CMPA Shadow (24)
EPWMxA
EPWMA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
16
CMPB Active (16)
EPWMB
EPWMxB
EPWMxTZINT
TZ1 to TZ3
CMPB Shadow (16)
EMUSTOP
CTR=ZERO
CLOCKFAIL
DCAEVT1.inter
DCBEVT1.inter
(A)
(A)
(A)
(A)
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
DCAEVT2.inter
DCBEVT2.inter
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the
COMPxOUT and TZ signals.
Figure 4-9. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
4.5 High-Resolution PWM (HRPWM)
This module combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
•
•
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
NOTE
Between 40 to 50 MHz SYSCLKOUT under worst case process, voltage, and temperature
(maximum voltage and minimum temperature) conditions, the MEP step delay may
decrease to a point such that the maximum of 254 MEP steps may not cover 1 full
SYSCLKOUT cycle. In other words, high-resolution edge control will not be available for
the full range of a SYSCLKOUT cycle. If running SFO calibration software, the SFO
function will return an error code of “2” when this occurs. See the device-specific HRPWM
Reference Guide for more information on this error condition.
54
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
4.6 Enhanced CAP Modules (eCAP1)
The device contains an enhanced capture (eCAP) module. Figure 4-10 shows a functional block diagram
of a module.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Figure 4-10. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Table 4-8. eCAP Control and Status Registers
NAME
TSCTR
CTRPHS
CAP1
ECAP1
0x6A00
SIZE (x16) EALLOW PROTECTED
DESCRIPTION
Time-Stamp Counter
2
2
2
2
2
2
8
1
1
1
1
1
1
6
0x6A02
Counter Phase Offset Value Register
Capture 1 Register
0x6A04
CAP2
0x6A06
Capture 2 Register
CAP3
0x6A08
Capture 3 Register
CAP4
0x6A0A
Capture 4 Register
Reserved
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
Reserved
0x6A0C- 0x6A12
0x6A14
Reserved
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Reserved
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A1A- 0x6A1F
4.7 JTAG Port
On the 2802x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the
pins in Figure 4-11.
NOTE
In 2802x devices, the JTAG pins may also be used as GPIO pins. Care should be taken
in the board design to ensure that the circuitry connected to these pins do not affect the
emulation capabilities of the JTAG pin function. Any circuitry connected to these pins
should not prevent the emulator from driving (or being driven by) the JTAG pins for
successful debug.
56
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Piccolo Microcontrollers
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
TRST = 0: JTAG Disabled (GPIO Mode)
TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
TDO/GPIO37
GPIO38_out
GPIO37_in
C28x
Core
TDO
1
0
GPIO37_out
GPIO36_in
1
0
TMS
TDI
TMS/GPIO36
TDI/GPIO35
1
GPIO36_out
GPIO35_in
1
0
1
GPIO35_out
Figure 4-11. JTAG/GPIO Multiplexing
4.8 GPIO MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame
1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-9 shows the GPIO
register mapping.
Table 4-9. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F80
2
2
2
2
2
2
2
2
2
2
GPIO A Control Register (GPIO0 to 31)
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
0x6F90
0x6F92
0x6F96
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16-31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPIO B Control Register (GPIO32 to 38)
GPIO B Qualifier Select 1 Register (GPIO32 to 38)
GPIO B MUX 1 Register (GPIO32 to 38)
GPAPUD
GPBCTRL
GPBQSEL1
GPBMUX1
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TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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www.ti.com
Table 4-9. GPIO Registers (continued)
NAME
GPBDIR
GPBPUD
AIOMUX1
AIODIR
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO B Direction Register (GPIO32 to 38)
GPIO B Pull Up Disable Register (GPIO32 to 38)
Analog, I/O mux 1 register (AIO0 - AIO15)
Analog, I/O Direction Register (AIO0-AIO15)
0x6F9A
0x6F9C
0x6FB6
0x6FBA
2
2
2
2
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
0x6FD8
0x6FDA
0x6FDC
0x6FDE
2
2
2
2
2
2
2
2
2
2
2
2
GPIO A Data Register (GPIO0 to 31)
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 38)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO B Data Set Register (GPIO32 to 38)
GPIO B Data Clear Register (GPIO32 to 38)
GPIO B Data Toggle Register (GPIO32 to 38)
Analog I/O Data Register (AIO0 - AIO15)
Analog I/O Data Set Register (AIO0 - AIO15)
Analog I/O Data Clear Register (AIO0 - AIO15)
Analog I/O Data Toggle Register (AIO0 - AIO15)
GPBCLEAR
GPBTOGGLE
AIODAT
AIOSET
AIOCLEAR
AIOTOGGLE
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLPMSEL
0x6FE0
0x6FE1
0x6FE3
0x6FE8
1
1
1
2
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO0 to 31)
LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn
and GPxQSELn registers occurs to when the action is valid.
58
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
Table 4-10. GPIOA MUX
DEFAULT AT RESET
PRIMARY I/O
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
FUNCTION
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 bits = 11)
1-0
GPIO0
GPIO1
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
Reserved
Reserved(1)
Reserved
Reserved(1)
Reserved(1)
COMP1OUT (O)
Reserved(1)
COMP2OUT (O)
Reserved(1)
ECAP1 (I/O)
EPWMSYNCO (O)
Reserved
3-2
5-4
GPIO2
7-6
GPIO3
Reserved
9-8
GPIO4
Reserved(1)
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO5
GPIO6
EPWMSYNCI (I)
SCIRXDA (I)
Reserved
GPIO7
Reserved
Reserved
Reserved
Reserved
GPIO12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ1 (I)
SCITXDA (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01)
(GPAMUX2 BITS = 10)
(GPAMUX2 BITS = 11)
1-0
GPIO16
GPIO17
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
Reserved
Reserved
Reserved
TZ2 (I)
TZ3 (I)
3-2
5-4
GPIO18
SCITXDA (O)
SCIRXDA (I)
Reserved
XCLKOUT (O)
ECAP1 (I/O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ2 (O)
7-6
GPIO19/XCLKIN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO28
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCIRXDA (I)
SCITXDA (O)
Reserved
SDAA (I/OC)
SCLA (I/OC)
Reserved
GPIO29
TZ3 (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the
pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
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TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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www.ti.com
Table 4-11. GPIOB MUX
DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPBMUX1 REGISTER
BITS
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
1-0
GPIO32
GPIO33
SDAA (I/OC)
SCLA (I/OC)
COMP2OUT (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved
ADCSOCAO (O)
ADCSOCBO (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3-2
5-4
GPIO34
7-6
GPIO35 (TDI)
GPIO36 (TMS)
GPIO37 (TDO)
GPIO38/XCLKIN (TCK)
Reserved
Reserved
9-8
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 4-12. Analog MUX
DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS
AIOMUX1 BITS = 0,x
A0 (I)
AIOMUX1 BITS = 1,x
1-0
A0 (I)
A1 (I)
3-2
A1 (I)
5-4
AIO2 (I/O)
A3 (I)
A2 (I), COMPA1 (I)
A3 (I)
7-6
9-8
AIO4 (I/O)
A5 (I)
A4 (I), COMPA2 (I)
A5 (I)
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
AIO6 (I/O)
A7 (I)
A6 (I)
A7 (I)
B0 (I)
B0 (I)
B1 (I)
B1 (I)
AIO10 (I/O)
B3 (I)
B2 (I), COMPB1 (I)
B3 (I)
AIO12 (I/O)
B5 (I)
B4 (I), COMPB2 (I)
B5 (I)
AIO14 (I/O)
B7 (I)
B6 (I)
B7 (I)
60
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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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Piccolo Microcontrollers
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www.ti.com
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
External Interrupt
MUX
Low Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
Figure 4-12. GPIO Multiplexing
62
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SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
5 Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 2802x-based applications:
Software Development Tools
•
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
•
Development and evaluation boards
JTAG-based emulators - XDS510™ Class, XDS100
Flash programming tools
Power supply
Documentation and cables
5.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (e.g., TMS320F28025). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, DA) and temperature range (for example, A). Figure 5-1 provides a legend for
reading the complete device name for any family member.
TMS 320
F
28025
PT
A
PREFIX
TEMPERATURERANGE
A = −40°C to 85°C
S = −40°C to 125°C
experimental device
prototype device
qualified device
TMX =
TMP =
TMS =
PACKAGE TYPE
48-Pin PT Plastic Quad Flatpack
38-Pin DA Plastic Small-outline Package
DEVICE FAMILY
320 = TMS320 MCU Family
DEVICE
28027
28026
28025
28024
28023
28022
TECHNOLOGY
F = Flash
Figure 5-1. Device Nomenclature
5.2 Related Documentation
Extensive documentation supports all of the TMS320™ MCU family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.
See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for more information on types
of peripherals.
Table 5-1. TMS320F2802x Peripheral Selection Guide
Peripheral
Lit. No.
Type(1)
28027, 28026,
28025, 28024,
28023, 28022
TMS320x2802x Piccolo System Control and Interrupts
TMS320x2802x Piccolo Analog-to-Digital Converter and Comparator
TMS320x2802x Piccolo Serial Communications Interface (SCI)
TMS320x2802x Piccolo Serial Peripheral Interface (SPI)
TMS320x2802x Piccolo Boot ROM
SPRUFN3
SPRUGE5
SPRUGH1
SPRUG71
SPRUFN6
SPRUGE9
SPRUFZ8
SPRUFZ9
SPRUGE8
-
X
X
X
X
X
X
X
X
X
3/0(2)
0
1
-
TMS320x2802x Piccolo Enhanced Pulse Width Modulator Module (ePWM)
TMS320x2802x Piccolo Enhanced Capture Module (eCAP)
TMS320x2802x Piccolo Inter-Integrated Circuit (I2C)
1
0
0
1
TMS320x2802x Piccolo High-Resolution Pulse-Width Modulator (HRPWM)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
peripheral reference guides.
(2) The ADC module is Type 3 and the comparator module is Type 0.
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The following documents can be downloaded from the TI website (www.ti.com):
Data Manual
SPRS523
TMS320F28022, 28023, 28024, 28025, 28026, 28027 Microcontrollers (MCUs) contains the
pinout, signal descriptions, as well as electrical and timing specifications for the 2802x
devices.
SPRZ292
TMS320x28022, 28023, 28024, 28025, 28026, 28027 Piccolo DSP Silicon Errata describes
known advisories on silicon and provides workarounds.
CPU User's Guides
SPRU430 TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central
processing unit (CPU) and the assembly language instructions of the TMS320C28x
fixed-point digital signal processors (DSPs). It also describes emulation features available on
these DSPs.
Peripheral Guides
SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRUFN3 TMS320x2802x Piccolo System Control and Interrupts Reference Guide describes the
various interrupts and system control features of the C2802x microcontrollers (MCUs).
SPRUFN6 TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features of
the bootloader (factory-programmed boot-loading software) and provides examples of code.
It also describes other contents of the device on-chip boot ROM and identifies where all of
the information is located within that memory.
SPRUGE5 TMS320x2802x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference
Guide describes how to configure and use the on-chip ADC module, which is a 12-bit
pipelined ADC.
SPRUGE9 TMS320x2802x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor
control, switch mode power supply control, UPS (uninterruptible power supplies), and other
forms of power conversion.
SPRUGE8 TMS320x2802x Piccolo High-Resolution Pulse Width Modulator (HRPWM) describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM).
SPRUGH1 TMS320x2802x Piccolo Serial Communications Interface (SCI) Reference Guide describes
how to use the SCI.
SPRUFZ8 TMS320x2802x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the
enhanced capture module. It includes the module description and registers.
SPRUG71 TMS320x2802x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI
- a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit-transfer rate.
SPRUFZ9 TMS320x2802x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes the features
and operation of the inter-integrated circuit (I2C) module.
Tools Guides
SPRU513
TMS320C28x Assembly Language Tools User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514
TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++
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TMS320F28025, TMS320F28026, TMS320F28027
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compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320
DSP assembly language source code for the TMS320C28x device.
SPRU608
The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.
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6 Electrical Specifications
6.1 Absolute Maximum Ratings(1)(2)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO (I/O and Flash)
Supply voltage range, VDD
with respect to VSS
with respect to VSS
with respect to VSSA
– 0.3 V to 4.6 V
– 0.3 V to 2.5 V
– 0.3 V to 4.6 V
– 0.3 V to 4.6 V
– 0.3 V to 4.0 V
± 20 mA
Analog voltage range, VDDA
Input voltage range, VIN (3.3 V)
Output voltage range, VO
(3)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
Output clamp current, IOK (VO < 0 or VO > VDDIO
Operating ambient temperature ranges
)
± 20 mA
TA: A version
TA: S version
– 40°C to 85°C
– 40°C to 125°C
– 40°C to 150°C
– 65°C to 150°C
Junction temperature range, Tj
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.97
1.71
NOM
3.3
MAX
3.63
UNIT
Device supply voltage, I/O, VDDIO
V
Device supply voltage CPU, VDD (When internal
VREG is disabled and 1.8 V is supplied externally)
1.8
1.995
V
Supply ground, VSS
0
3.3
0
V
V
V
Analog supply voltage, VDDA
Analog ground, VSSA
2.97
3.63
Device clock frequency (system clock)
28022, 28023, 28024, 28025
28026, 28027
2
2
2
40
60
MHz
High-level input voltage, VIH(3.3 V)
Low-level input voltage, VIL (3.3 V)
VDDIO
0.8
V
V
High-level output source current, VOH = VOH(MIN) , IOH All GPIO pins
Group 2(1)
– 4
– 8
4
mA
mA
mA
mA
°C
Low-level output sink current, VOL = VOL(MAX), IOL
All GPIO pins
Group 2(1)
8
Ambient temperature, TA
TA: A version
TA: S version
– 40
– 40
85
125
125
°C
Junction temperature, TJ
°C
(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37
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6.3 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOHMAX
IOH = 50 µA
VOH High-level output voltage
VOL Low-level output voltage
V
VDDIO – 0.2
IOL = IOLMAX
0.4
V
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
All I/Os (including XRS)
– 100
Input current
(low level)
IIL
µA
Pin with pulldown
enabled
± 2
± 2
Pin with pullup
enabled
Input current
(high level)
IIH
µA
Pin with pulldown
enabled
100
2
Output current, pullup or
pulldown disabled
IOZ
CI
± 2
µA
Input capacitance
pF
6.4 Current Consumption
Table 6-1. TMS320F2802x Current Consumption at 40-MHz SYSCLKOUT
VREG ENABLED
IDDIO IDDA
TYP(3) MAX TYP(3)
VREG DISABLED
(1)
(2)
MODE
TEST CONDITIONS
IDD
IDDIO
IDDA
MAX
TYP(3)
MAX
TYP(3)
MAX
TYP
MAX
The following peripheral clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4
eCAP
SCI-A
SPI-A
ADC
Operation
al (Flash)
75 mA
13 mA
60 mA
15 mA
15 mA
I2C
COMP1/2
CPU Timer0/1/2
All PWM pins are toggled at 40 kHz.
All I/O pins are left unconnected.(4)
Code is running out of flash with 1
wait-state.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are off.
IDLE
14 mA
4 mA
100 µA
25 µA
25 µA
15 mA
4 mA
200 µA
200 µA
50 µA
100 µA
25 µA
25 µA
(5)
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
100 µA
50 µA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of SPI-A and SCI-A ports.
The hardware multiplier is exercised.
Watchdog is reset.
ADC is performing coninuous conversion.
COMP1/2 are continuously switching voltages.
GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
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Table 6-2. TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED
VREG DISABLED
(1)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP(3)
IDDA
IDD
IDDIO
TYP(3)
IDDA
MAX
TYP(3)
MAX
TYP(3)
MAX
MAX
TYP
MAX
The following peripheral clocks
are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
ADC
Operationa
l (Flash)
I2C
92 mA
13 mA
76 mA
15 mA
13 mA
COMP1/2
CPU-TIMER0/1/2
All PWM pins are toggled at 60
kHz.
All I/O pins are left
unconnected.(4)(5)
Code is running out of flash with
2 wait-states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are turned
off.
IDLE
20 mA
100 µA
20 mA
200 µA
100 µA
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
5 mA
25 µA
25 µA
4 mA
200 µA
50 µA
25 µA
25 µA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
100 µA
50 µA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by
writing to the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of SPI-A and SCI-A ports.
The hardware multiplier is exercised.
Watchdog is reset.
ADC is performing coninuous conversion.
COMP1/2 are continuously switching voltages.
GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.
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6.4.1 Reducing Current Consumption
The 2802x devices incorporate a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by
turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one
of the three low-power modes could be taken advantage of to reduce the current consumption even
further. Table 6-3 indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-3. Typical Current Consumption by Various
Peripherals (at 60 MHz)(1)
PERIPHERAL
MODULE(2)
IDD CURRENT
REDUCTION (mA)
ADC
2(3)
I2C
ePWM
3
2
eCAP
2
SCI
2
SPI
2
COMP/DAC
HRPWM
1
3
CPU-TIMER
Internal zero-pin oscillator
1
0.5
(1) All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral clocks
are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the
ADC (IDDA) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 45 mA, typical. To arrive at the IDD current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to the
baseline IDD current.
Following are other methods to reduce power consumption further:
•
The flash module may be powered down if code is run off SARAM. This results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
•
Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
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6.4.2 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
100
90
80
70
60
50
40
30
20
10
0
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
IDDIO (mA)
IDDA
Figure 6-1. Typical Operational Current Versus Frequency (F2802x)
Operational Power vs Frequency
450
400
350
300
250
200
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
Figure 6-2. Typical Operational Power Versus Frequency (F2802x)
6.5 Emulator Connection Without Signal Buffering for the MCU
Figure 6-3 shows the connection between the MCU and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-3 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
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6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
PD
4
TRST
TMS
TDI
GND
1
6
GND
GND
GND
GND
3
8
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCK_RET
MCU
JTAG Header
A. See Figure 4-11 for JTAG/GPIO multiplexing.
Figure 6-3. Emulator Connection Without Signal Buffering for the MCU
NOTE
The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header
on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7 kΩ
(typical) resistor.
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6.6 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
6.6.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.6.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
Α
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-4. 3.3-V Test Load Circuit
6.6.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2802x MCUs. Table 6-4 and Table 6-5 list the cycle times of various clocks.
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Table 6-4. 2802x Clock Table and Nomenclature (40-MHz Devices)
MIN
NOM
MAX UNIT
Internal zero-pin
oscillator 1
(INTOSC1)
tc(ZPOSC1), Cycle time
Frequency
100
ns
10
100
10
MHz
ns
Internal zero-pin
oscillator 2
(INTOSC2)
tc(ZPOSC2), Cycle time
Frequency
MHz
On-chip crystal
oscillator (X1/X2
pins)
tc(OSC), Cycle time
Frequency
28.6
20
50
35
ns
MHz
tc(CI), Cycle time
Frequency
25
4
250
40
ns
MHz
ns
XCLKIN
tc(SCO), Cycle time
Frequency
25
2
500
40
SYSCLKOUT
XCLKOUT
LSPCLK(1)
ADC clock
MHz
ns
tc(XCO), Cycle time
Frequency
50
0.5
25
2000
20
MHz
ns
tc(LCO), Cycle time
Frequency
100(2)
10(2)
40
40
MHz
ns
tc(ADCCLK), Cycle time
Frequency
25
MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 40 MHz.
Table 6-5. 2802x Clock Table and Nomenclature (60-MHz Devices)
MIN
NOM
MAX UNIT
ns
Internal zero-pin
oscillator 1
(INTOSC1)
tc(ZPOSC1), Cycle time
Frequency
100
10
MHz
ns
Internal zero-pin
oscillator 2
(INTOSC2)
tc(ZPOSC2), Cycle time
Frequency
100
10
MHz
On-chip crystal
oscillator (X1/X2
pins)
tc(OSC), Cycle time
Frequency
28.6
20
50
35
ns
MHz
tc(CI), Cycle time
Frequency
16.67
4
250
60
ns
MHz
ns
XCLKIN
tc(SCO), Cycle time
Frequency
16.67
2
500
60
SYSCLKOUT
XCLKOUT
LSPCLK(1)
ADC clock
MHz
ns
tc(XCO), Cycle time
Frequency
50
2000
20
0.5
MHz
ns
tc(LCO), Cycle time
Frequency
16.67
66.7(2)
15(2)
60
60
MHz
ns
tc(ADCCLK), Cycle time
Frequency
16.67
MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 60 MHz.
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6.7 Clock Requirements and Characteristics
Table 6-6. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
20
20
4
TYP MAX UNIT
35
Crystal (X1/X2)
35
fx
Input clock frequency
MHz
40
40-MHz device
60-MHz device
External oscillator/clock
source (XCLKIN pin)
4
60
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1-5
MHz
Table 6-7. XCLKIN Timing Requirements - PLL Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
33.3
200
6
ns
ns
ns
%
C9
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
%
Table 6-8. XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
25
MAX UNIT
C8
tc(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
40-MHz device
60-MHz device
Up to 20 MHz
250
250
6
ns
16.67
C9
tf(CI)
ns
ns
ns
ns
%
20 MHz to 60 MHz
Up to 20 MHz
2
C10 tr(CI)
6
20 MHz to 60 MHz
2
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
%
The possible configuration modes are shown in Table 3-16.
Table 6-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
PARAMETER
MIN
50
TYP
MAX
UNIT
40-MHz device
60-MHz device
C1
tc(XCO)
Cycle time, XCLKOUT
ns
50
C3
C4
C5
C6
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
ns
ns
ms
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H-2
H-2
H+2
H+2
(3)
1
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles.
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C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-5. Clock Timing
6.8 Power Sequencing
There is no power sequencing requirement. However, it is recommended that no voltage larger than a
diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages applied to pins
on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable
results.
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VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST
OSCCLK/8(A)
XCLKOUT
User-code dependent
t
w(RSL1)
XRS
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Boot-ROM execution starts
Peripheral/GPIO function
Based on boot code
(C)
GPIO pins as input (state depends on internal PU/PD)
User-code dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-6. Power-on Reset
Table 6-10. Reset (XRS) Timing Requirements
MIN
NOM
MAX UNIT
cycles
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
TBD
Pulse duration, XRS low on warm reset
8tc(OSCCLK)
cyclies
Table 6-11. Reset (XRS) Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(RSL1)
Pulse duration, XRS driven by device
600
µs
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
512tc(OSCCLK)
cycles
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
cycles
µs
td(EX)
Delay time, address/data valid after XRS high
Start up time, internal zero-pin oscillator
On-chip crystal, oscillator start-up time
32tc(OSCCLK)
tINTOSCST
3
(1)
tOSCST
1
10
ms
(1) Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
OSCCLK/8
XCLKOUT
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
(Don’t Care)
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete,SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
(Current CPU
Frequency)
(Changed CPU frequency)
Figure 6-8. Example of Effect of Writing Into PLLCR Register
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6.9 General-Purpose Input/Output (GPIO)
6.9.1 GPIO - Output Timing
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
8
ns
20
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-9. General-Purpose Output Timing
6.9.2 GPIO - Input Timing
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
(B)
w(SP)
by GPxCTRL[QUALPRD]
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-10. Sampling Mode
Table 6-13. General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
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Table 6-13. General-Purpose Input Timing Requirements (continued)
MIN
tw(SP) * (n(1) - 1)
MAX
UNIT
cycles
cycles
cycles
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SCO)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
6.9.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
t
w(GPI)
Figure 6-11. General-Purpose Input Timing
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6.9.4 Low-Power Mode Wakeup Timing
Table 6-14 shows the timing requirements, Table 6-15 shows the switching characteristics, and
Figure 6-12 shows the timing diagram for IDLE mode.
Table 6-14. IDLE Mode Timing Requirements(1)
MIN NOM
MAX
UNIT
Without input qualifier
With input qualifier
2tc(SCO)
5tc(SCO) + tw(IQSW)
tw(WAKE-INT) Pulse duration, external wake-up signal
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-15. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to
(2)
program execution resume
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
cycles
cycles
cycles
•
•
•
Wake-up from Flash
Flash module in active state
–
td(WAKE-IDLE)
Wake-up from Flash
Flash module in sleep state
–
1050tc(SCO) + tw(IQSW)
20tc(SCO)
Wake-up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT or XRS.
Figure 6-12. IDLE Entry and Exit Timing
Table 6-16. STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Without input qualification
With input qualification(1)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-17. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal
to program execution resume(1)
cycles
cycles
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
•
Wake up from flash
–
Flash module in active
state
td(WAKE-STBY)
•
Wake up from flash
cycles
cycles
–
Flash module in sleep
state
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
With input qualifier
100tc(SCO)
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-13. STANDBY Entry and Exit Timing Diagram
Table 6-18. HALT Mode Timing Requirements
MIN NOM
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
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Table 6-19. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
45tc(SCO)
1
UNIT
cycles
ms
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
32tc(SCO)
Delay time, PLL lock to program execution resume
1125tc(SCO)
35tc(SCO)
cycles
cycles
•
•
Wake up from flash
Flash module in sleep state
td(WAKE-HALT)
–
Wake up from SARAM
(G)
(A)
(C)
(E)
(B)
(D)
HALT
(F)
Device
Status
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G. Normal operation resumes.
Figure 6-14. HALT Wake-Up Using GPIOn
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6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-20 shows the PWM timing requirements and
Table 6-21, switching characteristics.
Table 6-20. ePWM Timing Requirements(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-21. ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
ns
6.10.2 Trip-Zone Input Timing
(A)
XCLKOUT
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-15. PWM Hi-Z Characteristics
Table 6-22. Trip-Zone input Timing Requirements(1)
MIN
1tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-23 shows the high-resolution PWM switching characteristics.
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Table 6-23. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1) (2)
150
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
(2) Between 40 to 50 MHz SYSCLKOUT under worst case process, voltage, and temperature (maximum voltage and minimum
temperature) conditions, the MEP step delay may decrease to a point such that the maximum of 254 MEP steps may not cover 1 full
SYSCLKOUT cycle. In other words, high-resolution edge control will not be available for the full range of a SYSCLKOUT cycle. If
running SFO calibration software, the SFO function will return an error code of “2” when this occurs. See the device-specific HRPWM
Reference Guide for more information on this error condition.
Table 6-24 shows the eCAP timing requirement and Table 6-25 shows the eCAP switching characteristics.
Table 6-24. Enhanced Capture (eCAP) Timing Requirement(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-25. eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
6.10.3 External Interrupt Timing
t
w(INT)
XINT1, XINT2, XINT3
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-16. External Interrupt Timing
Table 6-26. External Interrupt Timing Requirements(1)
TEST CONDITIONS
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
(2)
tw(INT)
Pulse duration, INT input low/high
Synchronous
With qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-27. External Interrupt Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
tw(IQSW) + 12tc(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
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6.10.4 I2C Electrical Specification and Timing
Table 6-28. I2C Timing
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
400
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
Vih
0.7 VDDIO
Vhys
Vol
0.05 VDDIO
V
Low level output voltage
Low period of SCL clock
3 mA sink current
0
0.4
V
tLOW
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
µs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
-10
µs
lI
Input current with an input voltage
10
µA
between 0.1 VDDIO and 0.9 VDDIO MAX
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-29 lists the master mode timing (clock phase = 0) and Table 6-30 lists the timing (clock
phase = 1). Figure 6-17 and Figure 6-18 show the timing waveforms.
86
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Table 6-29. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
UNIT
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
10
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
10
3
4
5
8
9
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO) -10
35
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
ns
ns
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MAX, slave mode receive 10-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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TMS320F28022, TMS320F28023, TMS320F28024
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master out data Is valid
10
SPISIMO
SPISOMI
Data Valid
11
Master in data
must be valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-17. SPI Master Mode External Timing (Clock Phase = 0)
88
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Table 6-30. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
UNIT
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M + 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCL))M
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
ns
ns
ns
ns
3
6
Pulse duration, SPICLK low (clock
polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
before SPICLK high (clock polarity
= 0)
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
before SPICLK low (clock polarity =
1)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
7
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M - 10
0.5tc(SPC)M -10
35
ns
ns
ns
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
10
11
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20 MHz MAX, master mode receive 10 MHz MAX
Slave mode transmit 10 MHz MAX, slave mode receive 10 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master out data Is valid
10
SPISIMO
SPISOMI
Data Valid
11
Master in data
must be valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-18. SPI Master Mode External Timing (Clock Phase = 1)
6.10.6 SPI Slave Mode Timing
Table 6-31 lists the slave mode external timing (clock phase = 0) and Table 6-32 (clock phase = 1).
Figure 6-19 and Figure 6-20 show the timing waveforms.
Table 6-31. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
MIN
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLK
4tc(LCO)
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
15 td(SPCH-SOMI)S
td(SPCL-SOMI)S
16 tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
19 tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20 tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
35
35
0.75tc(SPC)S
0.75tc(SPC)S
35
35
0.5tc(SPC)S-10
0.5tc(SPC)S-10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI data Is valid
19
SPISOMI
SPISIMO
20
SPISIMO data
must be valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-32. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)
NO.
MIN
8tc(LCO)
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
17 tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
18 tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low (clock polarity =
0)
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC)S
ns
21 tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
35
ns
ns
ns
22 tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S-10
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity =
1)
0.5tc(SPC)S-10
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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TMS320F28022, TMS320F28023, TMS320F28024
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Piccolo Microcontrollers
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI data is valid
21
SPISOMI
SPISIMO
Data Valid
22
SPISIMO data
must be valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 1)
6.10.6.1 On-chip Comparator/DAC
Table 6-33. Electrical Characteristics of the Comparator/DAC
CHARACTERISTIC
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
Comparator response time to PWM Trip Zone (Async)
Input Offset
VSSA – VDDA
V
30
±5
35
ns
mV
mV
Input Hysteresis
DAC
DAC Output Range
DAC resolution
DAC settling time
DAC Gain
VSSA – VDDA
V
bits
us
10
2
–1.5
10
%
DAC Offset
mV
No Missing Codes
INL
Yes
±3
LSB
92
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6.10.7 On-Chip Analog-to-Digital Converter
Table 6-34. ADC Electrical Characteristics (over recommended operating conditions)
PARAMETER
DC SPECIFICATIONS
Resolution
MIN
TYP
MAX
UNIT
12
Bits
MHz
MHz
ADC clock
40-MHz device
60-MHz device
0.001
60
ACCURACY
INL (Integral nonlinearity)
60-MHz clock (4.62
MSPS)
±2
LSB
DNL (Differential nonlinearity)
±1
±10
±10
±10
±4
LSB
LSB
LSB
LSB
LSB
LSB
(1)
Offset error
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ANALOG INPUT
±4
Analog input voltage (2) with internal reference
Analog input voltage (2) with external reference
VREFLO input voltage
0
3.3
V
VREFLO
VREFHI
V
V
(3)
VREFHI input voltage (with VREFLO = VSSA
Temperature coefficient
Input capacitance
)
1.98
VDDA
V
50
10
±5
PPM/°C
pF
Input leakage current
µA
(1) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(2) Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
(3) VREFLO is always connected to VSSA
.
6.10.7.1 ADC Power-Up Control Bit Timing
Table 6-35. ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
td(PWD)
Delay time for the ADC to be stable after power up
1
ms
(1) Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
td(PWD)
Request for ADC
Conversion
Figure 6-21. ADC Conversion Timing
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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6.10.7.1.1 ADC Sequential and Simultaneous Timings
0
2
9
15
22 24
37
ADCCLK
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
2 ADCCLKs
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
1 ADCCLK
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
Figure 6-22. Timing Example For Sequential Mode / Late Interrupt Pulse
94
Electrical Specifications
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TMS320F28022, TMS320F28023, TMS320F28024
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Piccolo Microcontrollers
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0
2
9
15
22 24
37
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
2 ADCCLKs
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
Figure 6-23. Timing Example For Sequential Mode / Early Interrupt Pulse
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
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www.ti.com
0
2
9
15
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
2 ADCCLKs
ADCRESULT 1
Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
1 ADCCLK
EOC1 Pulse
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
2 ADCCLKs
19
ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Figure 6-24. Timing Example For Simultaneous Mode / Late Interrupt Pulse
96
Electrical Specifications
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Piccolo Microcontrollers
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0
2
9
15
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
2 ADCCLKs
ADCRESULT 1
Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
2 ADCCLKs
19
ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Figure 6-25. Timing Example For Simultaneous Mode/Early Interrupt Pulse
6.11 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
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Electrical Specifications
97
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following
(
)
SINAD * 1.76
N +
formula,
6.02
it is possible to get a measure of performance expressed as N, the effective
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
98
Electrical Specifications
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TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
www.ti.com
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
7 Mechanicals
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
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Mechanicals
99
TMS320F28022, TMS320F28023, TMS320F28024
TMS320F28025, TMS320F28026, TMS320F28027
Piccolo Microcontrollers
SPRS523A–NOVEMBER 2008–REVISED DECEMBER 2008
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Additions, Deletions and Modifications
LOCATION
Section 1.1
Table 2-2
DESCRIPTION
Added enhanced control peripherals to features list
Modified the descriptions of the X1, X2, and XRS pins
Modified the memory maps
Section 3.2
Section 3.3.4
Section 3.3.19
Table 3-7
Modified the Real-time JTAG and Analysis section
Modified the Control Peripherals section
Modified the peripheral frame 2 registers table
Moved and modified the VREG + POR + BOR + Reset Signal Connectivity figure
Modified the clock and reset domains figure
Figure 3-6
Figure 3-7
Table 3-9
Modified the device emulation registers table
Figure 3-4
Figure 3-8
Table 3-14
Section 3.7.2
Section 3.8.4
Figure 3-11
Section 3.9
Table 4-1
Modified the external and PIE interrupt sources figure
Modified the clock tree figure
Modified the PLLCR bit descriptions table and changed the title to PLL Settings
Modified the section on POR and BOR circuit
Modified the Loss of Input Clock section and added to the title
Changed the title of the Clock Fail figure to NMI-watchdog
Modified the Low-power Modes Block section
Added a column to show EALLOW protection to register tables
Modified the peripheral frame 2 registers table
Modified the GPIO MUX section
Table 3-7
Section 4.8
Section 6.1
Section 6.4
Modified the Absolute Maximum Ratings table
Added the Current Consumption section and all the sections following it
100
Revision History
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TSSOP
LQFP
Drawing
TMX320F28023DAA
TMX320F28027PTA
ACTIVE
ACTIVE
DA
38
48
1
1
TBD
TBD
Call TI
Call TI
Call TI
Call TI
PT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
1
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