TMX320R2811PBKA [TI]
TMS320R2811, TMS320R2812 Digital Signal Processors; TMS320R2811 ， TMS320R2812数字信号处理器
| 型号： | TMX320R2811PBKA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320R2811, TMS320R2812 Digital Signal Processors |
| 文件： | 总147页 (文件大小：1991K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320R2811, TMS320R2812
Digital Signal Processors
Data Manual
Literature Number: SPRS257
June 2004
ADVANCE INFORMATION concerns new
products in the sampling or preproduction
phase of development. Characteristic data and
other specifications are subject to change
without notice.
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Contents
Page
Contents
Section
1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
2.3.2
2.3.3
Terminal Assignments for the GHH and ZHH Packages . . . . . . . . . . . . . . . . . . . 14
Pin Assignments for the PGF Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Assignments for the PBK Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1
3.2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Brief Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
C28x CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Memory Bus (Harvard Bus Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Real-Time JTAG and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
External Interface (XINTF) (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
M0, M1 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
L0, L1, L2, L3, H0 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Peripheral Interrupt Expansion (PIE) Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
External Interrupts (XINT1, 2, 13, XNMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Peripheral Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Peripheral Frames 0, 1, 2 (PFn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General-Purpose Input/Output (GPIO) Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . 34
32-Bit CPU-Timers (0, 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Control Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.2.18
3.2.19
3.2.20
3.3
3.4
3.5
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Interface, XINTF (2812 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5.1
3.5.2
Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
XREVISION Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.6
3.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.6.1 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Loss of Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
External Reference Oscillator Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Low-Power Modes Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1
32-Bit CPU-Timers 0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3
June 2004
SPRS257
Contents
4.2
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
General-Purpose (GP) Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Full-Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Programmable Deadband Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PWM Waveform Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Double Update PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PWM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Capture Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Quadrature-Encoder Pulse (QEP) Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
External ADC Start-of-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3
4.4
4.5
4.6
4.7
4.8
Enhanced Analog-to-Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Enhanced Controller Area Network (eCAN) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Multichannel Buffered Serial Port (McBSP) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Serial Communications Interface (SCI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
GPIO MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5
6
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.1
5.2
Device and Development Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.1
6.2
6.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x) . . . . . . . . . . . . . . . . . . 86
6.5
6.6
6.7
6.8
Current Consumption Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reducing Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power Sequencing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
General Notes on Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Device Clock Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Clock Requirements and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.9
6.10
6.11
6.12
6.13
6.13.1
6.13.2
Input Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Output Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.14
6.15
6.16
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Low-Power Mode Wakeup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.16.1
6.16.2
PWM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
General-Purpose Input/Output (GPIO) − Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
General-Purpose Input/Output (GPIO) − Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
External Interface (XINTF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
XINTF Signal Alignment to XCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
External Interface Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
External Interface Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4
SPRS257
June 2004
Contents
6.25
6.26
6.27
6.28
6.29
External Interface Ready-on-Read Timing With One External Wait State . . . . . . . . . . . . . . . . 118
External Interface Ready-on-Write Timing With One External Wait State . . . . . . . . . . . . . . . . 121
XHOLD and XHOLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
XHOLD/XHOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
On-Chip Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.29.1
6.29.2
ADC Absolute Maximum Ratings† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ADC Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.29.3
Current Consumption for Different ADC Configurations
(at 25-MHz ADCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.29.4
6.29.5
6.29.6
6.29.7
6.29.8
ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Sequential Sampling Mode (Single-Channel) (SMODE = 0) . . . . . . . . . . . . . . . 131
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) . . . . . . . . . . . . . . 133
Definitions of Specifications and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.30
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.30.1
6.30.2
McBSP Transmit and Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7
8
Migration From F281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
8.1
8.2
8.3
Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Low-Profile Quad Flatpacks (LQFPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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Figure
List of Figures
Page
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View) . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2−3. TMS320R2811 128-Pin PBK LQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3−1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3−2. R2812 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3−3. R2811 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 3−4. External Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 3−5. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3−6. Multiplexing of Interrupts Using the PIE Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3−7. Clock and Reset Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 3−8. OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 3−9. Recommended Crystal/Clock Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 3−10. Watchdog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4−1. CPU-Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4−3. Event Manager A Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4−4. Block Diagram of the R281x ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 4−5. ADC Pin Connections With Internal Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4−6. ADC Pin Connections With External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 4−7. eCAN Block Diagram and Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 4−8. eCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 4−9. McBSP Module With FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 4−12. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 5−1. TMS320x28x Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled) . . . . . . . . . . . . . . . . 87
Figure 6−2. Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 6−3. Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 6−4. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 6−5. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 6−8. Warm Reset in Microcomputer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 6−9. Effect of Writing Into PLLCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 6−10. IDLE Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 6−11. STANDBY Entry and Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 6−12. HALT Wakeup Using XNMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 6−13. PWM Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 6−14. TDIRx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6
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Figures
Figure 6−15. EVASOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 6−16. EVBSOC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 6−17. External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 6−18. General-Purpose Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 6−19. GPIO Input Qualifier − Example Diagram for QUALPRD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 6−20. General-Purpose Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 6−21. SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 6−22. SPI Master External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 6−25. Relationship Between XTIMCLK and SYSCLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 6−26. Example Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 6−27. Example Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 6−28. Example Read With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 6−29. Example Read With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 6−30. Write With Synchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 6−31. Write With Asynchronous XREADY Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 6−32. External Interface Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 6−33. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . 126
Figure 6−34. ADC Analog Input Impedance Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6−35. ADC Power-Up Control Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 6−36. Sequential Sampling Mode (Single-Channel) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 6−37. Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 6−38. McBSP Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 6−39. McBSP Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 138
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . 139
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 140
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . 141
Figure 7−1. TMS320R2812 179-Ball GHH MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 7−2. TMS320R2812 179-Ball ZHH MicroStar BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 7−3. TMS320R2812 176-Pin PGF LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 7−4. TMS320R2811 128-Pin PBK LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7
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Tables
Table
List of Tables
Page
Table 2−1. Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2−2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3−1. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3−2. Peripheral Frame 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−3. Peripheral Frame 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−4. Peripheral Frame 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 3−5. Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 3−6. XINTF Configuration and Control Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−7. XREVISION Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3−8. PIE Peripheral Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 3−9. PIE Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 3−10. External Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 3−12. PLLCR Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 3−13. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3−14. R281x Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 4−2. Module and Signal Names for EVA and EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 4−3. EVA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 4−4. ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 4−6. CAN Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 4−7. McBSP Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 4−8. SCI-A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4−9. SCI-B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 4−10. SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 4−11. GPIO Mux Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4−12. GPIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 6−2. TMS320R281x Clock Table and Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 6−3. Input Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−5. XCLKIN Timing Requirements − PLL Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−6. Possible PLL Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 6−8. Reset (XRS) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 6−9. IDLE Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 6−10. STANDBY Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 6−11. HALT Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 6−12. PWM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−13. Timer and Capture Unit Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 6−14. External ADC Start-of-Conversion − EVA − Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−15. External ADC Start-of-Conversion − EVB − Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 101
Table 6−16. Interrupt Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 6−17. Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 6−18. General-Purpose Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8
SPRS257
June 2004
Tables
Table 6−19. General-Purpose Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 6−20. SPI Master Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 6−21. SPI Master Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 6−24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse . . . . . . . . . . . . 112
Table 6−25. XINTF Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 6−26. External Memory Interface Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 6−27. External Memory Interface Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 6−28. External Memory Interface Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 6−29. External Memory Interface Read Switching Characteristics
(Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 6−30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . 118
Table 6−31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . . 118
Table 6−32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) . . . . . . . . . . . . . . 118
Table 6−33. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) . . . 121
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . . 121
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) . . . . . . . . . . . . . . 121
Table 6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) . . . . . . . . . . . . . . . . . . . . . . 126
Table 6−38. DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 6−39. AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 6−40. ADC Power-Up Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 6−41. Sequential Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 6−42. Simultaneous Sampling Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 6−43. McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 6−44. McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . 138
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . 138
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . 139
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . 139
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . 140
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . 140
Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . 141
Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . 141
Table 6−53. Feature Comparison Between F281x and R281x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 7−1. Thermal Resistance Characteristics for 179-GHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 7−2. Thermal Resistance Characteristics for 179-ZHH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 7−3. Thermal Resistance Characteristics for 176-PGF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 7−4. Thermal Resistance Characteristics for 128-PBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
9
June 2004
SPRS257
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10
SPRS257
June 2004
Features
1
Features
D
High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
D
D
Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
D
Three 32-Bit CPU-Timers
†
D
D
JTAG Boundary Scan Support
D
Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− Code and Pin Compatible to F2810,
F2811, and F2812 devices
D
D
Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP)
12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
− TMS320F24x/LF240x Processor Source
Code Compatible
D
D
On-Chip Memory
− 20K x 16 Total Single-Access RAM
(SARAM)
D
D
Up to 56 General Purpose I/O (GPIO) Pins
− L0 and L1: 2 Blocks of 4K x 16 Each
SARAM
− L2 and L3: 2 Blocks of 1K X 16 SARAM
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
D
Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
SPI, SCI, and GPIO Boot Loader Modes to
Support Loading Code From Off-chip
Sources to On-chip RAM. SPI Boot Mode
Supports Loading From an External Serial
EEPROM.
†
− JTAG Scan Controllers
D
D
Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
D
D
Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
Package Options
− 179-Ball MicroStar BGA With External
Memory Interface (GHH), (ZHH) (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Memory Interface
(PGF) (2812)
− 128-Pin LQFP Without External Memory
Interface (PBK) (2811)
External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
D
Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
D
Temperature Options:
− A: −40°C to 85°C (GHH, ZHH, PGF, PBK)
− S/Q: −40°C to 125°C (GHH, ZHH, PGF,
PBK)
− Watchdog Timer Module
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
11
June 2004
SPRS257
Introduction
2
Introduction
This section provides a summary of each device’s features, lists the pin assignments, and describes the
function of each pin. This document also provides detailed descriptions of peripherals, electrical
specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in Section 3, Functional Overview.
Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812,
respectively.
TMS320C28x is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12
SPRS257
June 2004
Introduction
2.2
Device Summary
Table 2−1 provides a summary of each device’s features.
†
Table 2−1. Hardware Features
FEATURE
R2811
R2812
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
Single-Access RAM (SARAM)
(16-bit word)
20K
20K
Boot ROM
Yes
—
Yes
Yes
External Memory Interface
Event Managers A and B
(EVA and EVB)
EVA, EVB
EVA, EVB
S
S
S
General-Purpose (GP) Timers
Compare (CMP)/PWM
4
4
16
16
Capture (CAP)/QEP Channels
6/2
6/2
Watchdog Timer
12-Bit ADC
Yes
Yes
Yes
Yes
S
Channels
16
16
32-Bit CPU Timers
SPI
3
3
Yes
Yes
SCIA, SCIB
CAN
SCIA, SCIB
SCIA, SCIB
Yes
Yes
56
Yes
Yes
56
McBSP
Digital I/O Pins (Shared)
External Interrupts
Supply Voltage
3
3
1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V I/O
179-ball GHH
Packaging
128-pin PBK
179-ball ZHH
176-pin PGF
A: −40°C to 85°C
Yes
Yes
Yes
Yes
†
Temperature Options
S/Q: −40°C to 125°C
‡
Product Status
TMX
TMX
†
‡
The S temperature option has been replaced by the Q temperature option (40°C to 125°C) from silicon revision E onwards. Q stands for
−40°C to 125°C Q100 automotive fault grading.
See Section 5.1, Device and Development Support Nomenclature for descriptions of TMS and TMX stages.
13
June 2004
SPRS257
Introduction
2.3
Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages.
Figure 2−2 shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 2−3
shows the pin assignments for the 128-pin PBK LQFP. Table 2−2 describes the function(s) of each pin.
2.3.1 Terminal Assignments for the GHH and ZHH Packages
See Table 2−2 for a description of each terminal’s function(s).
CAP6
T3CTRIP
T4CTRIP/
EVBSOC
PWM8
PWM7
V
V
V
V
V
DD
P
N
M
L
XZCS0AND1
SPISOMIA
PWM10
PWM9
XD[8]
XZCS2 SCITXDB
SS
DD
SS
DD
_QEPI2
_PDPINTB
T4PWM
_T4CMP
TEST2
V
V
DDIO
XR/W
C4TRIP
XD[11]
XA[2]
XWE
CANTXA CANRXA
DDIO
CAP4
_QEP3
CAP5
_QEP4
SCIRXDB
PWM1
V
SPISIMOA XA[1]
XRD
XD[6]
XD[4]
PWM12
PWM11
TEST1
XD[9]
X2
XA[3]
PWM2
XD[12]
PWM6
SS
V
V
V
V
XD[7]
C5TRIP
TDIRB
XD[10]
PWM3
PWM4
V
DD
DDIO
DDIO
SS
SS
T3PWM
_T3CMP
X1/
XCLKIN
PWM5
K
J
V
V
V
V
SPICLKA
SPISTEA
C6TRIP TCLKINB
XHOLDA
XD[13]
SS
SS
DD
SS
T1PWM
_T1CMP
T2PWM
_T2CMP
V
V
MCLKXA MFSRA
XD[3]
XD[5]
XA[4]
DDIO
SS
CAP1
CAP2
CAP3
T1CTRIP
H
G
F
V
DD
MCLKRA XD[1]
MFSXA
XD[2]
XA[0]
XA[5]
_QEP1
_QEP2
_QEPI1
_PDPINTA
T2CTRIP/
EVASOC
V
V
V
MDXA
MDRA
XD[0]
XA[6]
V
SS
DDIO
SS
DD
ADC-
RESEXT
V
XMP/MC
ADCINB7
C3TRIP XCLKOUT XA[7] TCLKINA TDIRA
V
SSA1
DDA1
AVDD-
AVSS-
ADC-
XNMI
V
E
D
C
B
A
ADCREFP
ADCREFM ADCINA5
XHOLD
XA[13]
C2TRIP
EMU0
XA[8]
TDO
C1TRIP
TMS
V
DDIO
SS
REFBG
REFBG
BGREFIN
_XINT13
XINT2
_ADCSOC _XBIO
XINT1
V
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
XRS
XA[18]
XA[9]
SS
V
ADCINB3 ADCINB0 ADCINB1 ADCINA2
SSA2
V
V
V
V
SCITXDA
EMU1
DD
XA[12]
XD[14]
XA[10]
TDI
SS1
SS
DD
V
V
ADCINB2
ADCLO ADCINA3 ADCINA7 XREADY XA[17]
XA[15]
TRST XZCS6AND7
V
V
DDAIO
SS
SS
DD
XF
_XPLLDIS
TCK
V
ADCINA0 ADCINA4
V
V
SCIRXDA XA[16]
XD[15]
XA[14]
TESTSEL XA[11]
SSAIO
DDA2
DD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 2−1. TMS320R2812 179-Ball GHH and ZHH MicroStar BGA (Bottom View)
14
SPRS257
June 2004
Introduction
2.3.2 Pin Assignments for the PGF Package
The TMS320R2812 176-pin PGF low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2.
See Table 2−2 for a description of each pin’s function(s).
132
89
133
88
XZCS2
XZCS6AND7
TESTSEL
TRST
87
CANTXA
SS
XA[3]
XWE
134
86
V
135
TCK
EMU0
85
84
136
137
T4CTRIP/EVBSOC
XHOLDA
XA[12]
XD[14]
83
82
138
139
81
80
V
XF_XPLLDIS
140
141
DDIO
XA[13]
XA[2]
T3CTRIP_PDPINTB
SS
V
DD
79
78
142
143
SS
V
V
XA[14]
DDIO
77
76
75
74
73
X1/XCLKIN
X2
DD
XD[11]
XD[10]
144
145
146
147
148
V
V
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
72
71
TCLKINB
TDIRB
149
150
XINT2_ADCSOC
XA[16]
70
69
V
V
151
152
SS
DDIO
V
DD
68
67
XD[9]
TEST1
153
154
SS
V
SCITXDA
XA[17]
SCIRXDA
XA[18]
XHOLD
XRS
66
65
64
63
62
61
TEST2
XD[8]
DDIO
C6TRIP
C5TRIP
C4TRIP
155
156
157
158
159
160
V
XREADY
60
59
58
57
56
55
CAP6_QEPI2
161
162
163
164
165
166
V
CAP5_QEP4
DD1
SS1
V
V
SS
ADCBGREFIN
CAP4_QEP3
V
DDA2
V
SSA2
DD
V
T4PWM_T4CMP
ADCINA7
ADCINA6
ADCINA5
54
53
52
XD[7]
167
168
169
T3PWM_T3CMP
V
SS
XR/W
PWM12
ADCINA4
ADCINA3
51
50
170
171
ADCINA2
ADCINA1
49
48
PWM11
PWM10
172
173
ADCINA0
ADCLO
47
46
PWM9
PWM8
174
175
V
PWM7
SSAIO
176
45
1
44
Figure 2−2. TMS320R2812 176-Pin PGF LQFP (Top View)
15
June 2004
SPRS257
Introduction
2.3.3 Pin Assignments for the PBK Package
The TMS320R2811 128-pin PBK low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−3.
See Table 2−2 for a description of each pin’s function(s).
96
65
97
64
TESTSEL
TRST
CANTXA
V
DD
98
63
V
SS
TCK
99
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
EMU0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
T4CTRIP/EVBSOC
XF_XPLLDIS
T3CTRIP_PDPINTB
V
V
SS
DD
SS
V
X1/XCLKIN
V
DDIO
X2
EMU1
V
DD
XINT1_XBIO
TCLKINB
TDIRB
XNMI_XINT13
XINT2_ADCSOC
V
V
SS
DDIO
TEST1
V
DD
SS
V
TEST2
SCITXDA
SCIRXDA
XRS
V
DDIO
C6TRIP
V
C5TRIP
DD1
SS1
V
C4TRIP
CAP6_QEPI2
CAP5_QEP4
CAP4_QEP3
ADCBGREFIN
V
DDA2
SSA2
V
V
DD
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
T4PWM_T4CMP
T3PWM_T3CMP
V
SS
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
V
SSAIO
128
33
1
32
Figure 2−3. TMS320R2811 128-Pin PBK LQFP
(Top View)
16
SPRS257
June 2004
Introduction
2.4
Signal Descriptions
Table 2−2 specifies the signals on the R281x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
†
Table 2−2. Signal Descriptions
PIN NO.
179-PIN
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
128-PIN
PBK
GHH
AND
ZHH
PGF
XINTF SIGNALS (2812 ONLY)
XA[18]
D7
B7
158
156
152
148
144
141
138
132
130
125
121
118
111
108
103
85
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
−
−
−
−
−
−
−
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
XA[9]
A8
B9
A10
E10
C11
A14
C12
D14
E12
F12
G14
H13
J12
M11
N10
M2
−
−
−
−
−
−
−
−
−
−
19-bit XINTF Address Bus
XA[8]
XA[7]
XA[6]
XA[5]
XA[4]
XA[3]
XA[2]
80
XA[1]
43
XA[0]
G5
18
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
17
June 2004
SPRS257
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
A9
B11
J10
L14
N9
L9
147
139
97
96
74
73
68
65
54
39
36
33
30
27
24
21
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
M8
P7
L5
16-bit XINTF Data Bus
L3
J5
K3
J3
H5
H3
G3
XD[0]
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
18
SPRS257
June 2004
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Microprocessor/Microcomputer Mode Select. Switches
between microprocessor and microcomputer mode. When
high, Zone 7 is enabled on the external interface. When low,
Zone 7 is disabled from the external interface, and on-chip
boot ROM may be accessed instead. This signal is latched
into the XINTCNF2 register on a reset and the user can modify
this bit in software. The state of the XMP/MC pin is ignored
after reset.
XMP/MC
F1
17
−
I
PD
External Hold Request. XHOLD, when active (low), requests
the XINTF to release the external bus and place all buses and
strobes into a high-impedance state. The XINTF will release
the bus when any current access is complete and there are no
pending accesses on the XINTF.
XHOLD
E7
159
82
−
−
I
PU
External Hold Acknowledge. XHOLDA is driven active (low)
when the XINTF has granted a XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when
XHOLDA is active (low).
XHOLDA
K10
O/Z
−
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active
(low) when an access to the XINTF Zone 0 or Zone 1 is
performed.
XZCS0AND1
XZCS2
P1
44
88
−
−
−
O/Z
O/Z
O/Z
−
−
−
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an
access to the XINTF Zone 2 is performed.
P13
B13
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active
(low) when an access to the XINTF Zone 6 or Zone 7 is
performed.
XZCS6AND7
133
Write Enable. Active-low write strobe. The write strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers.
XWE
XRD
N11
M3
N4
84
42
51
−
−
−
O/Z
O/Z
O/Z
−
−
−
Read Enable. Active-low read strobe. The read strobe
waveform is specified, per zone basis, by the Lead, Active,
and Trail periods in the XTIMINGx registers. NOTE: The XRD
and XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high. When low, XR/W
indicates write cycle is active; when high, XR/W indicates read
cycle is active.
XR/W
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
19
June 2004
SPRS257
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
XINTF SIGNALS (2812 ONLY) (CONTINUED)
Ready Signal. Indicates peripheral is ready to complete the
access when asserted to 1. XREADY can be configured to be
a synchronous or an asynchronous input. See the timing
diagrams for more details.
XREADY
B6
K9
161
−
I
PU
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input − input to the internal oscillator. This pin is also
used to feed an external clock. The 28x can be operated with
an external clock source, provided that the proper voltage
levels be driven on the X1/XCLKIN pin. It should be noted that
the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core
X1/XCLKIN
77
58
I
digital power supply (V ), rather than the 3.3-V I/O supply
DD
(V ). A clamping diode may be used to clamp a buffered
DDIO
clock signal to ensure that the logic-high level does not
exceed V (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
DD
X2
M9
F11
A13
76
57
87
97
O
O
I
Oscillator Output
Output clock derived from SYSCLKOUT to be used for
external wait-state generation and as a general-purpose clock
source. XCLKOUT is either the same frequency, 1/2 the
frequency, or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be
turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register
to 1.
XCLKOUT
TESTSEL
119
134
−
PD
Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution.
The PC will point to the address contained at the location
0x3FFFC0. When XRS is brought to a high level, execution
begins at the location pointed to by the PC. This pin is driven
low by the DSP when a watchdog reset occurs. During
watchdog reset, the XRS pin will be driven low for the
watchdog reset duration of 512 XCLKIN cycles.
XRS
D6
160
113
I/O
PU
The output buffer of this pin is an open-drain with an internal
pullup (100 µA, typical). It is recommended that this pin be
driven by an open-drain device.
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
TEST1
M7
N7
67
66
51
50
I/O
I/O
−
−
This pin is a “no connect (NC)” (i.e., this pin is not connected
to any circuitry internal to the device).
TEST2
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
20
SPRS257
June 2004
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
JTAG
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TRST
B12
135
98
I
PD
TCK
TMS
A12
D13
136
126
99
92
I
I
PU
PU
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDI
C13
D12
D11
C9
131
127
137
146
96
93
I
PU
−
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
TDO
O/Z
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
EMU0
EMU1
100
105
I/O/Z
I/O/Z
PU
PU
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
B5
D5
E5
A4
B4
C4
D4
A3
167
168
169
170
171
172
173
174
119
120
121
122
123
124
125
126
I
I
I
8-Channel analog inputs for Sample-and-Hold A. The ADC
I
I
I
I
I
pins should not be driven before V
pins have been fully powered up.
, V , and V
DDA2 DDAIO
DDA1
ADCINA0
†
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
21
June 2004
SPRS257
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
ADC ANALOG INPUT SIGNALS (CONTINUED)
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
F5
D1
D2
D3
C1
B1
C3
C2
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
I
I
I
I
I
I
I
I
8-Channel Analog Inputs for Sample-and-Hold B. The ADC
pins should not be driven before the V
, V
, and
DDA1
DDA2
V
DDAIO
pins have been fully powered up.
ADC Voltage Reference Output (2 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADCREFP
ADCREFM
E2
E4
11
10
11
10
I/O
I/O
ADC Voltage Reference Output (1 V). Requires a low ESR
(50 mΩ − 1.5 Ω) ceramic bypass capacitor of 10 µF to analog
ground. (Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1−10 µF low ESR
capacitor can be used in the external reference mode.)
ADCRESEXT
ADCBGREFIN
AVSSREFBG
AVDDREFBG
ADCLO
F2
E6
E3
E1
B3
F3
C5
16
164
12
16
116
12
O
I
ADC External Current Bias Resistor (24.9 kΩ ±±5)
Test Pin. Reserved for TI. Must be left unconnected.
ADC Analog GND
I
13
13
I
ADC Analog Power (3.3-V)
175
15
127
15
I
Common Low Side Analog Input. Connect to analog ground.
ADC Analog GND
V
SSA1
V
SSA2
I
165
117
I
ADC Analog GND
V
V
V
V
V
V
F4
A5
C6
A6
B2
A2
14
166
163
162
1
14
118
115
114
1
I
I
I
I
ADC Analog 3.3-V Supply
ADC Analog 3.3-V Supply
ADC Digital GND
DDA1
DDA2
SS1
ADC Digital 1.8-V (or 1.9-V) Supply
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
DD1
DDAIO
SSAIO
176
128
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
22
SPRS257
June 2004
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
NAME
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
POWER SIGNALS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
H1
L1
23
37
20
29
42
56
63
74
82
94
102
110
17
26
30
39
−
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
P5
56
P9
75
1.8-V or 1.9-V Core Digital Power Pins. See Section 6.2,
Recommended Operating Conditions, for voltage
requirements.
P12
K12
G12
C14
B10
C8
−
100
112
128
143
154
19
G4
K1
32
L2
38
P4
52
K6
58
P8
70
53
59
62
73
−
M10
L11
K13
J14
G13
E14
B14
D10
C10
B8
78
86
Core and Digital I/O Ground Pins
99
105
113
120
129
142
−
−
88
95
−
103
109
25
49
−
153
31
J4
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
L7
64
L10
N14
G11
E9
81
3.3-V I/O Digital Power Pins
−
−
114
145
69
83
104
52
N8
†
‡
§
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
23
June 2004
SPRS257
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
GPIO
PERIPHERAL SIGNAL
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
GPIOA12
GPIOA13
GPIOA14
GPIOA15
PWM1 (O)
M12
M14
L12
L13
K11
K14
J11
92
93
68
69
70
71
72
75
76
77
78
79
80
85
86
89
90
91
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #1
GPIO or PWM Output Pin #2
GPIO or PWM Output Pin #3
GPIO or PWM Output Pin #4
GPIO or PWM Output Pin #5
GPIO or PWM Output Pin #6
GPIO or Timer 1 Output
PWM2 (O)
PWM3 (O)
94
PWM4 (O)
95
PWM5 (O)
98
PWM6 (O)
101
102
104
106
107
109
116
117
122
123
124
T1PWM_T1CMP (I)
T2PWM_T2CMP (I)
CAP1_QEP1 (I)
CAP2_QEP2 (I)
CAP3_QEPI1 (I)
TDIRA (I)
J13
H10
H11
H12
F14
F13
E13
E11
F10
GPIO or Timer 2 Output
GPIO or Capture Input #1
GPIO or Capture Input #2
GPIO or Capture Input #3
GPIO or Timer Direction
TCLKINA (I)
C1TRIP (I)
GPIO or Timer Clock Input
GPIO or Compare 1 Output Trip
GPIO or Compare 2 Output Trip
GPIO or Compare 3 Output Trip
C2TRIP (I)
C3TRIP (I)
GPIOB OR EVB SIGNALS
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOB8
GPIOB9
GPIOB10
GPIOB11
GPIOB12
GPIOB13
GPIOB14
GPIOB15
PWM7 (O)
N2
P2
N3
P3
L4
45
46
47
48
49
50
53
55
57
59
60
71
72
61
62
63
33
34
35
36
37
38
40
41
43
44
45
54
55
46
47
48
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #7
GPIO or PWM Output Pin #8
GPIO or PWM Output Pin #9
GPIO or PWM Output Pin #10
GPIO or PWM Output Pin #11
GPIO or PWM Output Pin #12
GPIO or Timer 3 Output
PWM8 (O)
PWM9 (O)
PWM10 (O)
PWM11 (O)
PWM12 (O)
M4
K5
N5
M5
M6
P6
L8
T3PWM_T3CMP (I)
T4PWM_T4CMP (I)
CAP4_QEP3 (I)
CAP5_QEP4 (I)
CAP6_QEPI2 (I)
TDIRB (I)
GPIO or Timer 4 Output
GPIO or Capture Input #4
GPIO or Capture Input #5
GPIO or Capture Input #6
GPIO or Timer Direction
TCLKINB (I)
C4TRIP (I)
K8
N6
L6
GPIO or Timer Clock Input
GPIO or Compare 4 Output Trip
GPIO or Compare 5 Output Trip
GPIO or Compare 6 Output Trip
C5TRIP (I)
C6TRIP (I)
K7
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
24
SPRS257
June 2004
Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
GPIO
PERIPHERAL SIGNAL
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
GPIOD OR EVA SIGNALS
GPIOD0
GPIOD1
T1CTRIP_PDPINTA (I)
T2CTRIP/EVASOC (I)
H14
G10
110
81
I/O/Z
PU
PU
Timer 1 Compare Output Trip
Timer 2 Compare Output Trip or External
ADC Start-of-Conversion EV-A
115
84
I/O/Z
GPIOD OR EVB SIGNALS
GPIOD5
GPIOD6
T3CTRIP_PDPINTB (I)
T4CTRIP/EVBSOC (I)
P10
P11
79
60
I/O/Z
PU
PU
Timer 3 Compare Output Trip
Timer 4 Compare Output Trip or External
ADC Start-of-Conversion EV-B
83
61
I/O/Z
GPIOE OR INTERRUPT SIGNALS
GPIOE0
GPIOE1
GPIOE2
XINT1_XBIO (I)
D9
D8
E8
149
151
150
106
108
107
I/O/Z
I/O/Z
I/O/Z
−
−
GPIO or XINT1 or XBIO input
GPIO or XINT2 or ADC start of conversion
GPIO or XNMI or XINT13
XINT2_ADCSOC (I)
XNMI_XINT13 (I)
PU
GPIOF OR SPI SIGNALS
GPIOF0
GPIOF1
GPIOF2
GPIOF3
SPISIMOA (O)
SPISOMIA (I)
SPICLKA (I/O)
SPISTEA (I/O)
M1
N1
K2
K4
40
41
34
35
31
32
27
28
I/O/Z
I/O/Z
I/O/Z
I/O/Z
−
−
−
−
GPIO or SPI slave in, master out
GPIO or SPI slave out, master in
GPIO or SPI clock
GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIO or SCI asynchronous serial port TX
data
GPIOF4
GPIOF5
SCITXDA (O)
SCIRXDA (I)
C7
A7
155
157
111
112
I/O/Z
I/O/Z
PU
PU
GPIO or SCI asynchronous serial port RX
data
GPIOF OR CAN SIGNALS
GPIOF6
GPIOF7
CANTXA (O)
CANRXA (I)
N12
N13
87
89
64
65
I/O/Z
I/O/Z
PU
PU
GPIO or eCAN transmit data
GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS
GPIOF8
GPIOF9
GPIOF10
GPIOF11
GPIOF12
GPIOF13
MCLKXA (I/O)
MCLKRA (I/O)
MFSXA (I/O)
MFSRA (I/O)
MDXA (O)
J1
H2
H4
J2
28
25
26
29
22
20
23
21
22
24
19
18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
−
GPIO or transmit clock
GPIO or receive clock
GPIO or transmit frame synch
GPIO or receive frame synch
GPIO or transmitted serial data
GPIO or received serial data
G1
G2
MDRA (I)
PU
†
‡
§
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
25
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Introduction
†
Table 2−2. Signal Descriptions (Continued)
PIN NO.
179-PIN
GHH
AND
‡
§
GPIO
PERIPHERAL SIGNAL
I/O/Z
PU/PD
DESCRIPTION
176-PIN
PGF
128-PIN
PBK
ZHH
GPIOF OR XF CPU OUTPUT SIGNAL
This pin has three functions:
1. XF − General-purpose output pin.
2. XPLLDIS − This pin will be sampled
during reset to check if the PLL needs
to be disabled. The PLL will be
disabled if this pin is sensed low. HALT
and STANDBY modes cannot be used
when the PLL is disabled.
GPIOF14
GPIOG4
XF_XPLLDIS (O)
A11
140
101
I/O/Z
PU
3. GPIO − GPIO function
GPIOG OR SCI-B SIGNALS
GPIO or SCI asynchronous serial port
transmit data
SCITXDB (O)
SCIRXDB (I)
P14
M13
90
91
66
67
I/O/Z
I/O/Z
−
−
GPIO or SCI asynchronous serial port
receive data
GPIOG5
†
Typical drive strength of the output buffer for all pins [except TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins] is 4 mA typical.
I = Input, O = Output, Z = High impedance
PU = pin has internal pullup; PD = pin has internal pulldown
‡
§
NOTE:
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with
the 3.3-V supply.
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Functional Overview
3
Functional Overview
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
CPU-Timer 2
Real-Time JTAG
TINT2
INT14
Control
Address(19)
Data(16)
PIE
External
Interface
(XINTF)
†
(96 interrupts)
INT[12:1]
TINT1
‡
INT13
NMI
XINT13
External Interrupt
Control
(XINT1/2/13, XNMI)
M0 SARAM
1K x 16
M1 SARAM
1K x 16
XNMI
G
SCIA/SCIB
SPI
FIFO
FIFO
FIFO
P
I
O
GPIO Pins
L0 SARAM
4K x 16
McBSP
C28x CPU
M
U
X
L1 SARAM
4K x 16
eCAN
EVA/EVB
L2 SARAM
1K X 16
L3 SARAM
1K X 16
12-Bit ADC
16 Channels
System Control
XRS
X1/XCLKIN
X2
RS
(Oscillator and PLL
H0 SARAM
8K × 16
CLKIN
+
Peripheral Clocking
+
XF_XPLLDIS
Low-Power
Modes
+
Boot ROM
Memory Bus
4K × 16
WatchDog)
Peripheral Bus
†
45 of the possible 96 interrupts are used on the devices.
XINTF is available on the R2812 devices only.
‡
Figure 3−1. Functional Block Diagram
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Functional Overview
3.1
Memory Map
Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
Reserved
(2K × 16)
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
Reserved
= 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
0x00 2000
0x00 4000
XINTF Zone 0 (8K × 16, XZCS0AND1)
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(4K × 16, Protected)
Reserved
Peripheral Frame 2
(4K × 16, Protected)
Reserved
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K × 16)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
0x08 0000
0x10 0000
0x18 0000
XINTF Zone 2 (0.5M × 16, XZCS2)
0x00 A400
0x00 A800
L3 SARAM (1K × 16)
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
Reserved
Reserved
0x3F7FF8
0x3F 8000
0x3F A000
128-bit Password (see Note H)
H0 SARAM (8K × 16)
Reserved
0x3F C000
0x3F F000
0x3F FFC0
XINTF Zone 7 (16K × 16, XZCS6AND7)
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
(Enabled if MP/MC = 1)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
H. The passwords are set to all ones.
Figure 3−2. R2812 Memory Map (See Notes A through H)
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Functional Overview
Block
Start Address
On-Chip Memory
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
Reserved
(Enabled if VMAP
= 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(4K × 16, Protected)
Reserved
Peripheral Frame 2
(4K × 16, Protected)
0x00 8000
0x00 9000
0x00 A000
0x00 A400
L0 SARAM (4K × 16,)
L1 SARAM (4K × 16)
L2 SARAM (1K × 16)
L3 SARAM (1K × 16)
0x00 A800
Reserved
0x3F 7FF8
0x3F 8000
128-bit Password (see Note F)
H0 SARAM (8K × 16)
0x3F A000
Reserved
0x3F F000
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
0x3F FFC0
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. The passwords are set to all ones.
Figure 3−3. R2811 Memory Map (See Notes A through F)
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Functional Overview
The low 64K of the memory-address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the “High 64K” memory area. Hence, the top 32K of H0 SARAM block can be used to run
24x/240x-compatible code (if MP/MC mode is low) or, on the 2812, code can be executed from XINTF Zone 7
(if MP/MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample
or ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
NOTE:
The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged together into
a single chip select (XZCS6AND7). See Section 3.5, “External Interface, XINTF (2812 only)”,
for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the
user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset
is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and
hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by
XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 3−1.
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Functional Overview
Table 3−1. Wait States
AREA
WAIT-STATES
0-wait
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
Fixed
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Peripheral Frame 2
Fixed
Fixed
0-wait (writes)
2-wait (reads)
L0, L1, L2, and L3 SARAMs
H0 SARAM
0-wait
0-wait
1-wait
Fixed
Fixed
Boot-ROM
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Programmable,
1-wait minimum
XINTF
3.2
Brief Descriptions
3.2.1 C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant
software investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop
not only their system control software in a high-level language, but also enables math algorithms to be
developed using C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically
are handled by microcontroller devices. This efficiency removes the need for a second processor in many
systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x
to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive
floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical
registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.
The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables
the C28x to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The R28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single
cycle 32-bit operations. The multiple-bus architecture, commonly termed “Harvard Bus”, enables the R28x
to fetch an instruction, read a data value, and write a data value in a single cycle. All peripherals and memories
attached to the memory bus prioritize memory accesses.
C28x and TMS320C2000 are trademarks of Texas Instruments.
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Functional Overview
Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur
on the memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur
on the memory bus.)
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, R281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and
16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on R281x.
One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with
C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral
frame 1).
3.2.4 Real-Time JTAG and Analysis
R281x implements the standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. R281x
implements the real-time mode in hardware within the CPU. This is a unique feature to R281x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
3.2.5 External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
3.2.6 M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.7 L0, L1, L2, L3, H0 SARAMs
R281x contains an additional 18K x 16 of single-access RAM (SARAM), divided into 5 blocks (4K + 4K +1K
+1K+ 8K). Each block can be independently accessed, minimizing pipeline stalls. Each block is mapped to
both program and data space.
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Functional Overview
3.2.8 Boot ROM
The Boot ROM is factory programmed with boot-loading software that can be used to download software from
an external interface. Boot-mode signals are provided that tell the bootloader software which boot mode to
use on power up. The Boot ROM on R281x devices is identical to that on F281x devices, except that the jump
to flash and jump to OTP modes are not available. The Boot Rom also contains standard tables such as
SIN/COS waveforms, for use in math-related algorithms.
3.2.9 Security
R281x devices contain a non−utilizable code security module for compatibility with C281x and F281x devices.
The passwords for the security module are hard-wired in the device as all 0xFFFF. After a device reset, the
L0 and L1 SARAM blocks are in a locked condition until a dummy read of the passwords is performed. The
R281x Boot ROM performs a dummy read of the password locations. If execution after reset begins directly
in external memory on R2812 devices (i.e., MP/MC =1 ), the user should perform 8 dummy reads, one each
from address 0x3F7FF8 through 0x3F7FFF.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On R281x, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt
lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block
that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.
It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled/disabled within the PIE block.
3.2.11 External Interrupts (XINT1, 2, 13, XNMI)
R281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked
external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected
for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time stamp the interrupt.
3.2.12 Oscillator and PLL
R281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer
to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
R281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when
a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event
managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of
peripherals to be decoupled from increasing CPU clock speeds.
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Functional Overview
3.2.15 Low-Power Modes
R281x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
HALT:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event.
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. Only a reset or XNMI will wake the device from this
mode.
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
R281x segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
PIE:
External Interface Configuration Registers (2812 only)
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Timers: CPU-Timers 0, 1, 2 Registers
PF1:
PF2:
eCAN:
SYS:
GPIO:
EV:
eCAN Mailbox and Control Registers
System Control Registers
GPIO Mux Configuration and Control Registers
Event Manager (EVA/EVB) Control Registers
McBSP: McBSP Control and TX/RX Registers
SCI:
SPI:
ADC:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Peripheral Interface (SPI) Control and RX/TX Registers
12-Bit ADC Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured
as inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For
specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise
glitches.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero.
The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time
OS (RTOS)/BIOS applications. CPU-Timer 2 is reserved for the DSP/BIOS real-time operating system
(DSP/BIOS RTOS), and is connected to INT14 of the CPU. CPU-Timer 1 is for general use, and is connected
to INT13 of the CPU. CPU-Timer 0 is also for general use, and is connected to the PIE block.
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Functional Overview
3.2.19 Control Peripherals
R281x supports the following peripherals which are used for embedded control and communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four
two-phase motors. The event managers on R281x are compatible to the event managers
on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.20 Serial Port Peripherals
R281x supports the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
McBSP:
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of
the SPI. On R281x, the port supports a 16-level, receive and transmit FIFO for reducing
servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On R281x, the port supports a 16-level, receive and transmit FIFO for
reducing servicing overhead.
3.3
Register Map
R281x devices contain three peripheral register spaces. The spaces are categorized as follows:
•
•
•
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3−2.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3−3.
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3−4.
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†
Table 3−2. Peripheral Frame 0 Registers
‡
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 0880
0x00 09FF
Device Emulation Registers
reserved
384
EALLOW protected
0x00 0A00
0x00 0B1F
288
32
0x00 0B20
0x00 0B3F
XINTF Registers
reserved
Not EALLOW protected
Not EALLOW protected
0x00 0B40
0x00 0BFF
192
64
0x00 0C00
0x00 0C3F
CPU-TIMER0/1/2 Registers
reserved
0x00 0C40
0x00 0CDF
160
32
0x00 0CE0
0x00 0CFF
PIE Registers
Not EALLOW protected
EALLOW protected
0x00 0D00
0x00 0DFF
PIE Vector Table
256
512
0x00 0E00
0x00 0FFF
Reserved
†
‡
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
¶
Table 3−3. Peripheral Frame 1 Registers
NAME
eCAN Registers
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 6000
0x00 60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
0x00 6100
0x00 61FF
256
(128 x 32)
eCAN Mailbox RAM
reserved
Not EALLOW-protected
0x00 6200
0x00 6FFF
3584
¶
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
†
Table 3−4. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 7000
0x00 700F
reserved
16
0x00 7010
0x00 702F
System Control Registers
reserved
32
16
16
EALLOW Protected
0x00 7030
0x00 703F
0x00 7040
0x00 704F
SPI-A Registers
Not EALLOW Protected
†
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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†
Peripheral Frame 2 Registers (Continued)
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x00 7050
0x00 705F
SCI-A Registers
reserved
16
16
Not EALLOW Protected
0x00 7060
0x00 706F
0x00 7070
0x00 707F
External Interrupt Registers
reserved
16
Not EALLOW Protected
0x00 7080
0x00 70BF
64
0x00 70C0
0x00 70DF
GPIO Mux Registers
GPIO Data Registers
ADC Registers
reserved
32
EALLOW Protected
0x00 70E0
0x00 70FF
32
Not EALLOW Protected
Not EALLOW Protected
0x00 7100
0x00 711F
32
0x00 7120
0x00 73FF
736
64
0x00 7400
0x00 743F
EV-A Registers
reserved
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
0x00 7440
0x00 74FF
192
64
0x00 7500
0x00 753F
EV-B Registers
reserved
0x00 7540
0x00 774F
528
16
0x00 7750
0x00 775F
SCI-B Registers
reserved
0x00 7760
0x00 77FF
160
64
0x00 7800
0x00 783F
McBSP Registers
reserved
0x00 7840
0x00 7FFF
1984
†
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 3−5.
Table 3−5. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DESCRIPTION
0x00 0880
0x00 0881
DEVICECNF
2
Device Configuration Register
reserved
0x00 0882
0x00 0883
0x00 0884
0x00 0885
1
1
1
1
Not supported on Revision C and later silicon
Device ID Register (0x0001 − Silicon − Rev. A)
Block Protection Start Address Register
Block Protection Range Address Register
DEVICEID
PROTSTART
PROTRANGE
0x00 0886
0x00 09FF
reserved
378
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3.5
External Interface, XINTF (2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the 2812 devices.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the 2812 is mapped into five fixed zones shown in Figure 3−4.
Figure 3−4 shows the 2812 XINTF signals.
Data Space
Prog Space
0x00 0000
XD(15:0)
XA(18:0)
0x00 2000
0x00 4000
XINTF Zone 0
XZCS0
XZCS1
(8K × 16)
XZCS0AND1
XINTF Zone 1
(8K × 16)
0x00 6000
0x08 0000
XINTF Zone 2
(512K × 16)
XZCS2
0x10 0000
XINTF Zone 6
(512K × 16)
XZCS6
XZCS7
XZCS6AND7
0x18 0000
0x3F C000
XINTF Zone 7
(16K × 16)
(mapped here if MP/MC = 1)
0x40 0000
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note E)
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects
(XZCS0AND1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable
glueless connection to many external memories and peripherals.
C. The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select (XZCS0AND1). Any external memory
that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1.
D. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
E. XCLKOUT is also pinned out on the 2810 and 2811.
Figure 3−4. External Interface Block Diagram
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The operation and timing of the external interface, can be controlled by the registers listed in Table 3−6.
Table 3−6. XINTF Configuration and Control Register Mappings
NAME
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XINTCNF2
XBANK
ADDRESS
0x00 0B20
0x00 0B22
0x00 0B24
0x00 0B2C
0x00 0B2E
0x00 0B34
0x00 0B38
0x00 0B3A
SIZE (x16)
DESCRIPTION
2
2
2
2
2
2
1
1
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register
XINTF Bank Control Register
XREVISION
XINTF Revision Register
3.5.1 Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect
to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 6−25.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320F28x DSP
External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2 XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in Table 3−7.
Table 3−7. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
15−0
REVISION
R
0x0004
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3.6
Interrupts
Figure 3−5 shows how the various interrupt sources are multiplexed within R281x devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
Watchdog
WAKEINT
LPMINT
Low-Power Modes
XINT1
Interrupt Control
PIE
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to INT12
C28x CPU
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
GPIO
MUX
TINT0
TIMER 0
TIMER 2 (for RTOS)
TIMER 1
TINT2
TINT1
INT14
INT13
select
enable
NMI
XNMI_XINT13
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
†
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 3−5. Interrupt Sources
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Figure 3−6 shows how the interrupts are multiplexed using the PIE block. Eight PIE block interrupts are
grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96
possible interrupts. On R281x, 45 of these are used by peripherals as shown in Table 3−8.
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3−6. Multiplexing of Interrupts Using the PIE Block
†
Table 3−8. PIE Peripheral Interrupts
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT1
INT2
INT3
INT4
INT5
INT6
XINT2
XINT1
reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
reserved
reserved
reserved
reserved
reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
MXINT
(McBSP)
MRINT
(McBSP)
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
reserved
reserved
reserved
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ECAN1INT
(CAN)
ECAN0INT
(CAN)
SCITXINTB SCIRXINTB SCITXINTA
SCIRXINTA
(SCI-A)
INT9
reserved
reserved
(SCI-B)
reserved
reserved
reserved
(SCI-B)
reserved
reserved
reserved
(SCI-A)
reserved
reserved
reserved
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
†
Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
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Table 3−9. PIE Configuration and Control Registers
NAME
ADDRESS
DESCRIPTION
Size (x16)
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
0x0000−0CE0
0x0000−0CE1
0x0000−0CE2
0x0000−0CE3
0x0000−0CE4
0x0000−0CE5
0x0000−0CE6
0x0000−0CE7
0x0000−0CE8
0x0000−0CE9
0x0000−0CEA
0x0000−0CEB
0x0000−0CEC
0x0000−0CED
0x0000−0CEE
0x0000−0CEF
0x0000−0CF0
0x0000−0CF1
0x0000−0CF2
0x0000−0CF3
0x0000−0CF4
0x0000−0CF5
0x0000−0CF6
0x0000−0CF7
0x0000−0CF8
0x0000−0CF9
1
PIE, Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0000−0CFA
0x0000−0CFF
Note: The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
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3.6.1 External Interrupts
Table 3−10. External Interrupt Registers
NAME
XINT1CR
ADDRESS
0x00 7070
0x00 7071
SIZE (x16)
DESCRIPTION
1
1
XINT1 control register
XINT2 control register
XINT2CR
0x00 7072
0x00 7076
reserved
5
XNMICR
0x00 7077
0x00 7078
0x00 7079
1
1
1
XNMI control register
XINT1 counter register
XINT2 counter register
XINT1CTR
XINT2CTR
0x00 707A
0x00 707E
reserved
5
1
XNMICTR
0x00 707F
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more
information, see the TMS320F28x System Control and Interrupts Reference Guide (literature number
SPRU078).
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3.7
System Control
This section describes R281x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3−7 shows the various clock and reset domains in R281x devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
X1/XCLKIN
X2
C28x
CPU
PLL
OSC
Power
Modes
Control
XF_XPLLDIS
Clock Enables
System
Control
Registers
Peripheral
Registers
eCAN
I/O
I/O
I/O
LSPCLK
Low-Speed Prescaler
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
GPIOs
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
High-Speed Peripherals
EV-A/B
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
NOTE A: CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 3−7. Clock and Reset Domains
The PLL, clocking, watchdog and low-power modes are controlled by the registers listed in Table 3−11.
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Functional Overview
†
Table 3−11. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
reserved
ADDRESS
SIZE (x16)
DESCRIPTION
0x00 7010
0x00 7017
8
reserved
reserved
HISPCP
LOSPCP
PCLKCR
reserved
LPMCR0
LPMCR1
reserved
PLLCR
0x00 7018
0x00 7019
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
1
1
1
1
1
1
1
1
1
1
1
1
1
1
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
Peripheral Clock Control Register
Low Power Mode Control Register 0
Low Power Mode Control Register 1
‡
PLL Control Register
SCSR
System Control & Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
Watchdog Reset Key Register
Watchdog Control Register
0x00 7026
0x00 7028
reserved
WDCR
3
1
6
0x00 7029
0x00 702A
0x00 702F
reserved
†
‡
All of the above registers can only be accessed, by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) will not
reset PLLCR.
3.7.1 OSC and PLL Block
Figure 3−8 shows the OSC and PLL block on R281x.
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XPLLDIS
Latch
XRS
XF_XPLLDIS
OSCCLK (PLL Disabled)
X1/XCLKIN
XCLKIN
0
1
CLKIN
CPU
SYSCLKOUT
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 3−8. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to R281x devices using the X1/XCLKIN and X2
pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and
the X2 pin is left unconnected. The logic-high level in this case should not exceed V . The PLLCR bits [3:0]
DD
set the clocking ratio.
Table 3−12. PLLCR Register Bit Definitions
†
BIT(S)
NAME
TYPE
XRS RESET
DESCRIPTION
15:4
reserved
R = 0
0:0
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication factor.
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed
1
2
3
4
5
6
7
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
3:0
DIV
R/W
0,0,0,0
8
9
10
11
12
13
14
15
†
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
3.7.2 Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1−4 MHz. The PLLCR register should have been written to with a non-zero value for this feature
to work.
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Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset
or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing
(i.e., the watchdog counter does not change with the limp-mode clock). This condition could be used by the
application firmware to detect the input clock failure and initiate necessary shut-down procedure for the
system.
3.7.3 PLL-Based Clock Module
R281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for
the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different
CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be
re-enabled (if need be) after the PLL module has stabilized, which takes 131072 XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
•
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
•
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the X1/XCLKIN pin.
X1/XCLKIN
X2
X1/XCLKIN
X2
External Clock Signal
C
C
b2
b1
(Toggling 0−V
)
(see Note A)
Crystal
(a)
(see Note A)
NC
DD
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 3−9. Recommended Crystal/Clock Connection
Table 3−13. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Disabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
PLL Bypassed
PLL Enabled
XCLKIN/2
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
3.7.4 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
C (load capacitance) = 12 pF
L
C
L1
= C = 24 pF
L2
C
shunt
= 6 pF
ESR range = 25 to 40 Ω
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3.7.5 Watchdog Block
The watchdog block on R281x is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter
has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog
counter. Figure 3−10 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK(2:0))
1
0
1
WDRST
(See Note A)
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3−10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional
is the watchdog. The Watchdog module will run off the PLL clock or the oscillator clock. The WDINT signal
is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7.6,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is
the WATCHDOG.
3.7.6 Low-Power Modes Block
The low-power modes on R281x are similar to the 240x devices. Table 3−14 summarizes the various modes.
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Table 3−14. R281x Low-Power Modes
†
MODE
LPM(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT
Normal
X,X
on
on
on
−
XRS,
WDINT,
Any Enabled Interrupt,
‡
IDLE
0,0
on
on
on
XNMI
Debugger
§
XRS,
WDINT,
XINT1,
XNMI,
on
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
STANDBY
0,1
1,X
off
off
off
off
(watchdog still running)
SCIRXDB,
CANRX,
Debugger
§
off
XRS,
XNMI,
Debugger
HALT
(oscillator and PLL turned off,
watchdog not functional)
§
†
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will not
be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still functional
while on the 24x/240x the clock is turned off.
‡
§
On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is
recognized by the processor. The LPM block performs no tasks during
this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from
HALT mode. The XNMI input to the core has an enable/disable bit.
Hence, it is safe to use the XNMI signal for this function.
NOTE: The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them when the IDLE instruction was executed.
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4
Peripherals
The integrated peripherals of R281x are described in the following subsections:
•
•
•
•
•
•
•
•
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Enhanced controller area network (eCAN) module
Multichannel buffered serial port (McBSP) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
Digital I/O and shared pin functions
4.1
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on R281x devices (CPU-TIMER0/1/2).
CPU-Timer 2 is reserved for the real-time OS (such as DSP/BIOS). CPU-Timer 0/1 can be used in user
applications. These timers are different from the general-purpose (GP) timers that are present in the Event
Manager modules (EVA, EVB).
NOTE: If the application is not using DSP/BIOS, then CPU-Timers 1 and 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
32-Bit Counter
TIMH:TIM
(Timer Start Status)
Borrow
Borrow
TINT
Figure 4−1. CPU-Timers
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In R281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4−2.
INT1
to
TINT0
PIE
CPU-TIMER 0
INT12
C28x
TINT1
INT13
INT14
CPU-TIMER 1
XINT13
CPU-TIMER 2
Reserved RTOS
(DSP/BIOS)
TINT2
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4−2. CPU-Timer Interrupts Signals and Output Signal (See Notes A and B)
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 4−1 are used to configure the timers. For more information, see the TMS320F28x System Control
and Interrupts Reference Guide (literature number SPRU078).
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Table 4−1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x00 0C00
0x00 0C01
0x00 0C02
0x00 0C03
0x00 0C04
0x00 0C05
0x00 0C06
0x00 0C07
0x00 0C08
0x00 0C09
0x00 0C0A
0x00 0C0B
0x00 0C0C
0x00 0C0D
0x00 0C0E
0x00 0C0F
0x00 0C10
0x00 0C11
0x00 0C12
0x00 0C13
0x00 0C14
0x00 0C15
0x00 0C16
0x00 0C17
SIZE (x16)
DESCRIPTION
CPU-Timer 0, Counter Register
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
0x00 0C18
0x00 0C3F
reserved
40
4.2
Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units,
and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 4−2 shows the module and signal names
used. Table 4−2 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ. Table 4−3 lists the EVA registers. For more information, see the
TMS320F28x DSP Event Manager (EV) Reference Guide (literature number SPRU065).
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Table 4−2. Module and Signal Names for EVA and EVB
EVA
EVB
EVENT MANAGER MODULES
MODULE
SIGNAL
MODULE
SIGNAL
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
GP Timers
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Compare Units
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP1
QEP2
QEPI1
QEP3
QEP4
QEPI2
QEP1
QEP2
QEP3
QEP4
QEP Channels
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
External Clock Inputs
External Trip Inputs
External Trip Inputs
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
Compare
Compare
†
†
T1CTRIP_PDPINTA
T2CTRIP/EVASOC
T3CTRIP_PDPINTB
T4CTRIP/EVBSOC
†
In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.
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†
Table 4−3. EVA Registers
SIZE
(x16)
NAME
ADDRESS
DESCRIPTION
GPTCONA
T1CNT
T1CMPR
T1PR
0x00 7400
0x00 7401
0x00 7402
0x00 7403
0x00 7404
0x00 7405
0x00 7406
0x00 7407
0x00 7408
0x00 7409
0x00 7411
0x00 7413
0x00 7415
0x00 7417
0x00 7418
0x00 7419
0x00 7420
0x00 7422
0x00 7423
0x00 7424
0x00 7425
0x00 7427
0x00 7428
0x00 7429
0x00 742C
0x00 742D
0x00 742E
0x00 742F
0x00 7430
0x00 7431
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GP Timer Control Register A
GP Timer 1 Counter Register
GP Timer 1 Compare Register
GP Timer 1 Period Register
GP Timer 1 Control Register
GP Timer 2 Counter Register
GP Timer 2 Compare Register
GP Timer 2 Period Register
GP Timer 2 Control Register
GP Extension Control Register A
Compare Control Register A
Compare Action Control Register A
Dead-Band Timer Control Register A
Compare Register 1
T1CON
T2CNT
T2CMPR
T2PR
T2CON
‡
EXTCONA
COMCONA
ACTRA
DBTCONA
CMPR1
CMPR2
Compare Register 2
CMPR3
Compare Register 3
CAPCONA
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
CAP1FBOT
CAP2FBOT
CAP3FBOT
EVAIMRA
EVAIMRB
EVAIMRC
EVAIFRA
EVAIFRB
EVAIFRC
Capture Control Register A
Capture FIFO Status Register A
Two-Level Deep Capture FIFO Stack 1
Two-Level Deep Capture FIFO Stack 2
Two-Level Deep Capture FIFO Stack 3
Bottom Register Of Capture FIFO Stack 1
Bottom Register Of Capture FIFO Stack 2
Bottom Register Of Capture FIFO Stack 3
Interrupt Mask Register A
Interrupt Mask Register B
Interrupt Mask Register C
Interrupt Flag Register A
Interrupt Flag Register B
Interrupt Flag Register C
†
‡
The EV-B register set is identical except the address range is from 0x00−7500 to 0x00−753F. The above registers are mapped to Zone 2. This
space allows only 16-bit accesses. 32-bit accesses produce undefined results.
New register compared to 24x/240x
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Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
—
TX FIFO _15
MXINT
—
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR2 Transmit Buffer DXR1 Transmit Buffer
LSPCLK
FSX
McBSP Registers
and Control Logic
16
16
CLKX
Compand Logic
XSR2
XSR1
DX
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR2 Register
16
RBR1 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
—
RX FIFO _15
—
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 4−3. Event Manager A Functional Block Diagram (See Note A)
4.2.1 General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
•
•
•
•
•
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
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•
•
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
•
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the
time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP
timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period
and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse
width as needed.
4.2.2 Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
4.2.3 Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The
deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit
output signal. The output states of the deadband generator are configurable and changeable as needed by
way of the double-buffered ACTRx register.
4.2.4 PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
4.2.5 Double Update PWM Mode
The R281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM operation
mode in which the position of the leading edge and the position of the trailing edge of a PWM pulse are
independently modifiable in each PWM period. To support this mode, the compare register that determines
the position of the edges of a PWM pulse must allow (buffered) compare value update once at the beginning
of a PWM period and another time in the middle of a PWM period. The compare registers in R281x Event
Managers are all buffered and support three compare value reload/update (value in buffer becoming active)
modes. These modes have earlier been documented as compare value reload conditions. The reload
condition that supports double update PWM mode is reloaded on Underflow (beginning of PWM period) OR
Period (middle of PWM period). Double update PWM mode can be achieved by using this condition for
compare value reload.
4.2.6 PWM Characteristics
Characteristics of the PWMs are as follows:
•
•
•
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
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•
•
•
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
•
•
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after
PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx
register.
−
−
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
•
EXTCON register bits provide options to individually trip control for each PWM pair of signals
4.2.7 Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of
three capture circuits.
•
Capture units include the following features:
−
−
−
−
−
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet the input qualification circuitry requirements. The input pins
CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]
−
−
−
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the
capture function.
4.2.8 Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with
EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
4.2.9 External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
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4.3
Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4−4. The ADC module consists
of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
−
The digital value of the input analog voltage is derived by:
Input Analog Voltage * ADCLO
Digital Value + 4095
3
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
−
−
−
S/W − software immediate start
EVA − Event manager A (multiple event sources within EVA)
EVB − Event manager B (multiple event sources within EVB)
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
•
•
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in R281x has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC
clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service
event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel
module. Although there are multiple input channels and two sequencers, there is only one converter in the
ADC module. Figure 4−4 shows the block diagram of the R281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has
the choice of selecting any one of the respective eight channels available through an analog MUX. In the
cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once
the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
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SYSCLKOUT
System
Control Block
High-Speed
Prescaler
C28x
ADCENCLK
HSPCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCINA0
ADCINA7
ADCINB0
ADCINB7
S/H
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
EVB
SOC
SOC
Sequencer 1
Sequencer 2
Figure 4−4. Block Diagram of the R281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (V
/V
, AV
) from the digital
DDA1 DDA2
DDREFBG
supply. Figure 4−5 shows the ADC pin connections for R281x devices.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will
still function. This is necessary to make sure all registers and modes go into their default reset state. The
analog module will however be in a low-power inactive state. As soon as reset goes high, then the clock to
the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the
registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms
range) before the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the
CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
Figure 4−5 shows the ADC pin-biasing for internal reference and Figure 4−6 shows the ADC pin-biasing for
external reference.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Test Pin
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
†
ADCBGREFIN
§
24.9 kW
ADC External Current Bias Resistor ADCRESEXT
‡
10 mF
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
‡
ADCREFP and ADCREFM should not
be loaded by external circuitry
10 mF
V
V
V
V
Analog 3.3 V
Analog 3.3 V
DDA1
DDA2
SSA1
SSA2
ADC Analog Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
V
DDAIO
Analog 3.3 V
Analog Ground
V
SSAIO
V
1.8 V
Digital Ground
can use the same 1.8 V (or 1.9 V) supply as
the digital core but separate the two with a
ferrite bead or a filter
DD1
V
SS1
†
‡
§
Provide access to this pin in PCB layouts. Intended for test purposes only.
TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent
24.9-kΩ resistor is applicable for the full range of the ADC.
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4−5. ADC Pin Connections With Internal Reference (See Notes A and B)
NOTE:
The temperature rating of any recommended component must match the rating of the end
product.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Test Pin
Analog Input 0−3 V With Respect to ADCLO
Connect to Analog Ground
ADCBGREFIN
24.9 kW
ADC External Current Bias Resistor
ADC Reference Positive Input
ADC Reference Medium Input
ADCRESEXT
ADCREFP
(See
Note C)
2 V
1 V
ADCREFM
1 mF −10 mF
1 mF − 10 mF
V
V
V
V
Analog 3.3 V
Analog 3.3 V
DDA1
DDA2
ADC Analog Power
SSA1
SSA2
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
V
DDAIO
Analog 3.3 V
Analog Ground
V
SSAIO
V
DD1
1.8 V Can use the same 1.8-V (or 1.9-V)
V
SS1
Digital Ground
supply as the digital core but separate the
two with a ferrite bead or a filter
NOTES: A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP−ADCREFM)
= 1 V $ 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of
external reference is critical for overall gain. The voltage ADCREFP−ADCREFM will determine the overall accuracy.
Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the
TMS320F28x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more
information.
Figure 4−6. ADC Pin Connections With External Reference
61
June 2004
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Peripherals
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4−4.
†
Table 4−4. ADC Registers
SIZE
(x16)
NAME
ADDRESS
DESCRIPTION
ADCTRL1
ADCTRL2
0x00 7100
0x00 7101
0x00 7102
0x00 7103
0x00 7104
0x00 7105
0x00 7106
0x00 7107
0x00 7108
0x00 7109
0x00 710A
0x00 710B
0x00 710C
0x00 710D
0x00 710E
0x00 710F
0x00 7110
0x00 7111
0x00 7112
0x00 7113
0x00 7114
0x00 7115
0x00 7116
0x00 7117
0x00 7118
0x00 7119
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x00 711C
0x00 711F
reserved
4
†
The above registers are Peripheral Frame 2 Registers.
62
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Peripherals
4.4
Enhanced Controller Area Network (eCAN) Module
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
−
−
−
−
−
−
−
−
−
−
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
−
Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for further details.
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June 2004
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Peripherals
Address
Controls
Data
32
eCAN0INT
eCAN1INT
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4−7. eCAN Block Diagram and Interface Circuit
Table 4−5. 3.3-V eCAN Transceivers for the R281x DSPs
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
T
A
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
−−
−−
−−
−−
−−
−−
−40°C to 85°C
−40°C to 125°C
−40°C to 85°C
−40°C to 125°C
−40°C to 85°C
−40°C to 125°C
−40°C to 125°C
Yes
Sleep
Yes
None
None
None
None
None
Standby
Adjustable
None Diagnostic
Loopback
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Peripherals
Table 4−5. 3.3-V eCAN Transceivers for the TMS320R281x DSPs (Continued)
PART NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
T
A
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby & Sleep
Standby
Adjustable
Adjustable
None
None
−−
−40°C to 125°C
−40°C to 125°C
Autobaud
Loopback
eCAN Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN Memory (512 Bytes)
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6000h
603Fh
6040h
607Fh
Control and Status Registers
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
6080h
60BFh
60C0h
60FFh
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h−6107h
6108h−610Fh
6110h−6117h
6118h−611Fh
6120h−6127h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h−61E7h
61E8h−61EFh
61F0h−61F7h
61F8h−61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
61E8h−61E9h
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
Figure 4−8. eCAN Memory Map
65
June 2004
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The CAN registers listed in Table 4−6 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
†
Table 4−6. CAN Registers Map
SIZE
(x32)
REGISTER NAME
ADDRESS
DESCRIPTION
CANME
CANMD
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
1
Mailbox enable
1
Mailbox direction
Transmit request set
CANTRS
CANTRR
CANTA
1
1
Transmit request reset
Transmission acknowledge
Abort acknowledge
1
CANAA
1
CANRMP
CANRML
CANRFP
CANGAM
CANMC
1
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
1
1
1
1
CANBTC
CANES
1
Bit-timing configuration
Error and status
1
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
1
Transmit error counter
Receive error counter
1
1
Global interrupt flag 0
1
Global interrupt mask
1
Global interrupt flag 1
1
Mailbox interrupt mask
Mailbox interrupt level
1
1
Overwrite protection control
TX I/O control
1
1
RX I/O control
1
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
1
1
†
These registers are mapped to Peripheral Frame 1.
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Peripherals
4.5
Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
HIghly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
•
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
•
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
−
−
−
−
−
−
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
CLKSRG
(1 ) CLKGDIV)
•
McBSP clock rate = CLKG =
, where CLKSRG source could be LSPCLK, CLKX, or CLKR.
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.
Figure 4−9 shows the block diagram of the McBSP module with FIFO, interfaced to the R281x version of
Peripheral Frame 2.
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
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June 2004
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Peripherals
Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
—
TX FIFO _15
MXINT
—
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR2 Transmit Buffer DXR1 Transmit Buffer
LSPCLK
FSX
McBSP Registers
and Control Logic
16
16
CLKX
Compand Logic
XSR2
XSR1
DX
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR2 Register
16
RBR1 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
—
RX FIFO _15
—
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 4−9. McBSP Module With FIFO
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June 2004
Peripherals
Table 4−7 provides a summary of the McBSP registers.
Table 4−7. McBSP Register Summary
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
†
DATA REGISTERS, RECEIVE, TRANSMIT
−
−
−
−
−
−
−
−
−
0x0000
0x0000
0x0000
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
−
Read First if the word size is greater than 16 bits,
else ignore DRR2
McBSP Data Receive Register 1
−
Read Second if the word size is greater than 16 bits,
else read DRR1 only
McBSP Data Transmit Register 2
−
W
W
Write First if the word size is greater than 16 bits,
else ignore DXR2
McBSP Data Transmit Register 1
−
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
04
05
06
07
08
09
0A
0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
0C
0D
0E
0F
10
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR1
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
12
13
14
15
16
RCERC
RCERD
XCERC
XCERD
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
†
‡
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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Table 4−7. McBSP Register Summary (Continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
17
18
19
1A
1B
1C
1D
1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
‡
FIFO Data Registers
McBSP Data Receive Register 2 − Top of receive FIFO
Read First FIFO pointers will not advance
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
−
McBSP Data Receive Register 1 − Top of receive FIFO
Read Second for FIFO pointers to advance
−
McBSP Data Transmit Register 2 − Top of transmit FIFO
Write First FIFO pointers will not advance
W
W
−
McBSP Data Transmit Register 1 − Top of transmit FIFO
−
Write Second for FIFO pointers to advance
FIFO Control Registers
0xA000
MFFTX
MFFRX
MFFCT
MFFINT
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
0x201F
0x0000
0x0000
MFFST
0x0000
†
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
‡
4.6
Serial Communications Interface (SCI) Module
R281x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
−
−
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
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June 2004
Peripherals
•
•
Baud rate programmable to 64K different rates
LSPCLK
−
Baud rate =
=
,
when BRR ≠ 0
(BRR ) 1) * 8
LSPCLK
,
when BRR = 0
16
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Data-word format
−
−
−
−
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
−
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
−
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
150 MHz
Max bit rate +
+ 9.375 106 bńs
2 8
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is
accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
71
June 2004
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Peripherals
Figure 4−10 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
TXENA
Register
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
Transmitter−Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
SCICTL2.0
8
TX FIFO
Interrupts
TXINT
TX FIFO _0
TX FIFO _1
TX Interrupt
Logic
−−−−−
SCITXBUF.7−0
To CPU
TX FIFO _15
SCI TX Interrupt select logic
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 − 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 − 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7−0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
BRKDT
RX FIFO _15
SCIRXST.5
−−−−−
RX FIFO _0
RX FIFO
Interrupts
RX FIFO_1
RXINT
RX Interrupt
Logic
SCIRXBUF.7−0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 − 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 4−10. Serial Communications Interface (SCI) Module Block Diagram
72
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June 2004
Peripherals
The SCI port operation is configured and controlled by the registers listed in Table 4−8 and Table 4−9.
†
Table 4−8. SCI-A Registers
NAME
ADDRESS
0x00 7050
0x00 7051
0x00 7052
0x00 7053
0x00 7054
0x00 7055
0x00 7056
0x00 7057
0x00 7059
0x00 705A
0x00 705B
0x00 705C
0x00 705F
SIZE (x16)
DESCRIPTION
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI-A Communications Control Register
SCI-A Control Register 1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA
SCIFFRXA
SCIFFCTA
SCIPRIA
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
†
Shaded registers are new registers for the FIFO mode.
†‡
Table 4−9. SCI-B Registers
NAME
ADDRESS
0x00 7750
0x00 7751
0x00 7752
0x00 7753
0x00 7754
0x00 7755
0x00 7756
0x00 7757
0x00 7759
0x00 775A
0x00 775B
0x00 775C
0x00 775F
SIZE (x16)
DESCRIPTION
SCICCRB
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI-B Communications Control Register
SCI-B Control Register 1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB
SCIFFRXB
SCIFFCTB
SCIPRIB
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
†
‡
Shaded registers are new registers for the FIFO mode.
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
4.7
Serial Peripheral Interface (SPI) Module
R281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
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The SPI module features include:
Four external pins:
•
−
−
−
−
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates
LSPCLK
−
Baud rate =
, when BRR ≠ 0
(SPIBRR ) 1)
LSPCLK
=
,
when BRR = 0, 1, 2, 3
4
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted
such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
−
−
−
−
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register
is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing
to the upper byte has no effect.
Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 4−10.
Table 4−10. SPI Registers
NAME
SPICCR
SPICTL
ADDRESS
0x00 7040
0x00 7041
0x00 7042
0x00 7044
0x00 7046
0x00 7047
0x00 7048
0x00 7049
0x00 704A
0x00 704B
0x00 704C
0x00 704F
SIZE (x16)
DESCRIPTION
SPI Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI Operation Control Register
SPI Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI Baud Rate Register
SPI Receive Emulation Buffer Register
SPI Serial Input Buffer Register
SPI Serial Output Buffer Register
SPI Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI FIFO Transmit Register
SPI FIFO Receive Register
SPI FIFO Control Register
SPI Priority Control Register
NOTE: The registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4−11 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
SPI INT
ENA
16
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
†
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
†
SPISTE is driven low by the master for a slave device.
Figure 4−11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
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Peripherals
4.8
GPIO MUX
The GPIO Mux registers, are used to select the operation of shared pins on R281x devices. The pins can be
individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX
registers). If selected for “Digital I/O” mode, registers are provided to configure the pin direction (via the
GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
Table 4−11 lists the GPIO Mux Registers.
†‡§
Table 4−11. GPIO Mux Registers
NAME
GPAMUX
GPADIR
GPAQUAL
reserved
GPBMUX
GPBDIR
GPBQUAL
reserved
reserved
reserved
reserved
reserved
GPDMUX
GPDDIR
GPDQUAL
reserved
GPEMUX
GPEDIR
GPEQUAL
reserved
GPFMUX
GPFDIR
reserved
reserved
GPGMUX
GPGDIR
reserved
reserved
ADDRESS
0x00 70C0
0x00 70C1
0x00 70C2
0x00 70C3
0x00 70C4
0x00 70C5
0x00 70C6
0x00 70C7
0x00 70C8
0x00 70C9
0x00 70CA
0x00 70CB
0x00 70CC
0x00 70CD
0x00 70CE
0x00 70CF
0x00 70D0
0x00 70D1
0x00 70D2
0x00 70D3
0x00 70D4
0x00 70D5
0x00 70D6
0x00 70D7
0x00 70D8
0x00 70D9
0x00 70DA
0x00 70DB
SIZE (x16)
REGISTER DESCRIPTION
GPIO A Mux Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO A Direction Control Register
GPIO A Input Qualification Control Register
GPIO B Mux Control Register
GPIO B Direction Control Register
GPIO B Input Qualification Control Register
GPIO D Mux Control Register
GPIO D Direction Control Register
GPIO D Input Qualification Control Register
GPIO E Mux Control Register
GPIO E Direction Control Register
GPIO E Input Qualification Control Register
GPIO F Mux Control Register
GPIO F Direction Control Register
GPIO G Mux Control Register
GPIO G Direction Control Register
0x00 70DC
0x00 70DF
reserved
4
†
Reserved locations will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
‡
§
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Peripherals
If configured for digital I/O mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 4−12 lists the GPIO Data Registers. For more information, see the TMS320F28x System
Control and Interrupts Reference Guide (literature number SPRU078).
†‡
Table 4−12. GPIO Data Registers
NAME
GPADAT
ADDRESS
0x00 70E0
0x00 70E1
0x00 70E2
0x00 70E3
0x00 70E4
0x00 70E5
0x00 70E6
0x00 70E7
0x00 70E8
0x00 70E9
0x00 70EA
0x00 70EB
0x00 70EC
0x00 70ED
0x00 70EE
0x00 70EF
0x00 70F0
0x00 70F1
0x00 70F2
0x00 70F3
0x00 70F4
0x00 70F5
0x00 70F6
0x00 70F7
0x00 70F8
0x00 70F9
0x00 70FA
0x00 70FB
SIZE (x16)
REGISTER DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GPIO A Data Register
GPIO A Set Register
GPASET
GPACLEAR
GPATOGGLE
GPBDAT
GPIO A Clear Register
GPIO A Toggle Register
GPIO B Data Register
GPIO B Set Register
GPIO B Clear Register
GPIO B Toggle Register
GPBSET
GPBCLEAR
GPBTOGGLE
reserved
reserved
reserved
reserved
GPDDAT
GPIO D Data Register
GPIO D Set Register
GPIO D Clear Register
GPIO D Toggle Register
GPIO E Data Register
GPIO E Set Register
GPIO E Clear Register
GPIO E Toggle Register
GPIO F Data Register
GPIO F Set Register
GPIO F Clear Register
GPIO F Toggle Register
GPIO G Data Register
GPIO G Set Register
GPIO G Clear Register
GPIO G Toggle Register
GPDSET
GPDCLEAR
GPDTOGGLE
GPEDAT
GPESET
GPECLEAR
GPETOGGLE
GPFDAT
GPFSET
GPFCLEAR
GPFTOGGLE
GPGDAT
GPGSET
GPGCLEAR
GPGTOGGLE
0x00 70FC
0x00 70FF
reserved
4
†
‡
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
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Figure 4−12 shows how the various register bits select the various modes of operation.
GPxDAT/SET/CLEAR/TOGGLE
Digital I/O
Peripheral I/O
Register Bit(s)
High-
Impedance
Control
GPxQUAL
Register
GPxMUX
Register Bit Register Bit
GPxDIR
0
1
0
1
MUX
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
NOTES: A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value
written, not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the
corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0’s or all 1’s). This feature
removes unwanted spikes from the input signal.
Figure 4−12. Modes of Operation
NOTE:
The input function of the GPIO pin and the input path to the peripheral are always enabled.
It is the output function of the GPIO pin that is multiplexed with the output path of the primary
(peripheral) function. Since the output buffer of a pin connects back to the input buffer, any
GPIO signal present at the pin will be propagated to the peripheral module as well. Therefore,
when a pin is configured for GPIO operation, the corresponding peripheral functionality (and
interrupt-generating capability) must be disabled. Otherwise, interrupts may be inadvertently
triggered. This is especially critical when the PDPINTA and PDPINTB pins are used as GPIO
pins, since a value of zero for GPDDAT.0 or GPDDAT.5 (PDPINTx) will put PWM pins in a
high-impedance state. The CxTRIP and TxCTRIP pins will also put the corresponding PWM
pins in high impedance, if they are driven low (as GPIO pins) and bit EXTCONx.0 = 1.
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Development Support
5
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of R281x-based applications:
Software Development Tools
•
Code Composer Studio Integrated Development Environment (IDE)
−
−
−
−
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
R2812 eZdsp
JTAG-based emulators − SPI515, XDS510PP, XDS510PP Plus, XDS510 USB
Universal 5-V dc power supply
Documentation and cables
5.1
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each [TMS320] DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320R2812GHH). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development−support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.“
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
TMS320 is a trademark of Texas Instruments.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PBK) and temperature range (for example, A). Figure 5−1 provides a legend for reading
the complete device name for any TMS320x28x family member.
A
TMS 320
R
2812
PBK
PREFIX
TEMPERATURE RANGE
TMX = experimental device
TMP = prototype device
TMS = qualified device
A
S
Q
=
=
=
−40°C to 85°C
−40°C to 125°C
−40°C to 125°C − Q100
fault grading
†
PACKAGE TYPE
DEVICE FAMILY
320 = TMS320 DSP Family
GHH = 179-ball MicroStar BGA
ZHH = 179-ball MicroStar BGA (lead-free)
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2811
2812
TECHNOLOGY
F
=
=
=
Flash EEPROM (1.8-V/1.9-V Core/3.3-V I/O)
ROM (1.8-V/1.9-V Core/3.3-V I/O)
C
R
RAM only (1.8-V/1.9-V Core/3.3-V I/O)
†
BGA
=
Ball Grid Array
LQFP = Low-Profile Quad Flatpack
Figure 5−1. TMS320x28x Device Nomenclature
5.2
Documentation Support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets
and data manuals, with design specifications; and hardware and software applications. Useful reference
documentation includes:
TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the
central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital
signal processors (DSPs). It also describes emulation features available on these DSPs.
TMS320C28x Peripheral Reference Guide (literature number SPRU566) describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
TMS320F28x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060)
describes the ADC module. The module is a 12−bit pipelined ADC. The analog circuits of this converter,
referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample−and−hold
(S/H) circuits, the conversion core, voltage regulators, and other analog supporting circuits. Digital circuits,
referred to as the wrapper in this document, include programmable conversion sequencer, result registers,
interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules.
TMS320F28x Boot ROM Reference Guide (literature number SPRU095) describes the purpose and
features of the bootloader (factory-programmed boot-loading software). It also describes other contents of the
device on-chip boot ROM and identifies where all of the information is located within that memory.
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TMS320F28x Enhanced Controller Area Network (eCAN) Reference Guide (literature number SPRU074)
describes the eCAN that uses established protocol to communicate serially with other controllers in electrically
noisy environments. With 32 fully configurable mailboxes and time-stamping feature, the eCAN module
provides a versatile and robust serial communication interface. The eCAN module implemented in the C28x
DSP is compatible with the CAN 2.0B standard (active).
TMS320F28x Event Manager (EV) Reference Guide (literature number SPRU065) describes the EV
modules that provide a broad range of functions and features that are particularly useful in motion control and
motor control applications. The EV modules include general-purpose (GP) timers, full-compare/PWM units,
capture units, and quadrature-encoder pulse (QEP) circuits.
TMS320F28x External Interface (XINTF) Reference Guide (literature number SPRU067) describes the
external interface (XINTF) of the 28x digital signal processors (DSPs).
TMS320F28x Multichannel Buffered Serial Ports (McBSPs) Reference Guide (literature number
SPRU061) describes the McBSP) available on the C28x devices. The McBSPs allow direct interface between
a DSP and other devices in a system.
TMS320F28x Serial Communication Interface (SCI) Reference Guide (literature number SPRU051)
describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules
support digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format.
TMS320F28x Serial Peripheral Interface (SPI) Reference Guide (literature number SPRU059) describes
the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed
length (one to sixteen bits) to be shifted into and out of the device at a programmed bit−transfer rate. The SPI
is used for communications between the DSP controller and external peripherals or another controller.
TMS320F28x System Control and Interrupts Reference Guide (literature number SPRU078) describes
the various interrupts and system control features of the 28x digital signal processors (DSPs).
3.3 V DSP for Digital Motor Control Application Report (literature number SPRA550). New generations
of motor control digital signal processors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer higher
performance at lower cost. Replacing traditional 5-V digital control circuitry by 3.3-V designs introduce no
additional system cost and no significant complication in interfacing with TTL and CMOS compatible
components, as well as with mixed voltage ICs such as power transistor gate drivers. Just like 5-V based
designs, good engineering practice should be exercised to minimize noise and EMI effects by proper
component layout and PCB design when 3.3-V DSP, ADC, and digital circuitry are used in a mixed signal
environment, with high and low voltage analog and switching signals, such as a motor control system. In
addition, software techniques such as Random PWM method can be used by special features of the Texas
Instruments (TI) TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation.
This application report reviews designs of 3.3-V DSP versus 5-V DSP for low HP motor control applications.
The application report first describes a scenario of a 3.3-V-only motor controller indicating that for most
applications, no significant issue of interfacing between 3.3 V and 5 V exists. Cost-effective 3.3-V − 5-V
interfacing techniques are then discussed for the situations where such interfacing is needed. On-chip 3.3-V
ADC versus 5-V ADC is also discussed. Sensitivity and noise effects in 3.3-V and 5-V ADC conversions are
addressed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system’s
noise and EMI effects are summarized in the last section.
The TMS320C28x Instruction Set Simulator Technical Overview (literature number SPRU608) describes
the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x core.
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide (literature number
SPRU625) describes development using DSP/BIOS.
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TMS320C28x Assembly Language Tools User’s Guide (literature number SPRU513) describes the
assembly language tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x
device.
TMS320C28x Optimizing C Compiler User’s Guide (literature number SPRU514) describes the
TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces
TMS320 DSP assembly language source code for the TMS320C28x device.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual, use the comments@books.sc.ti.com email address, which is
a repository for feedback. For questions and support, contact the Product Information Center listed at the
http://www.ti.com/sc/docs/pic/home.htm site.
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Electrical Specifications
6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320R281x DSPs.
6.1
Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature
ranges. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Section 6.2 is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability. All voltage values are with respect to V
.
SS
Supply voltage range, V
, V
, V
, V
, and AV
. . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
DDIO
DDA1
DDA2
DDAIO
DDREFBG
Supply voltage range, V , V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 2.5 V
DD
DD1
Input voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
IN
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V
O
†
Input clamp current, I (V < 0 or V > V
DDIO
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
IN
IN
Output clamp current, I (V < 0 or V > V
OK
O
O
DDIO
Operating ambient temperature ranges, T : A version (GHH, PGF, PBK)‡ . . . . . . . . . . . . . . − 40°C to 85°C
A
T : S version (GHH, PGF, PBK)‡§ . . . . . . . . . . . . − 40°C to 125°C
A
T : Q version (GHH, PGF, PBK)‡ . . . . . . . . . . . . . − 40°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
A
†
Storage temperature range, T
stg
†
Continuous clamp current per pin is± 2 mA
‡
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963).
§
Replaced by Q temperature option from silicon revision E onwards
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Electrical Specifications
6.2
Recommended Operating Conditions†
MIN
3.14
NOM
3.3
1.8
1.9
0
MAX
3.47
UNIT
V
V
Device supply voltage, I/O
V
DDIO
1.8 V (135 MHz)
1.9 V (150 MHz)
1.71
1.81
1.89
2
, V
Device supply voltage, CPU
Supply ground
V
V
V
DD
DD1
V
V
SS
, V
DDA2
,
DDA1
ADC supply voltage
3.14
3.3
3.47
AV
, V
DDREFBG DDAIO
V
V
= 1.9 V ± 5%
= 1.8 V ± 5%
2
2
2
150
135
DD
Device clock frequency
(system clock)
f
MHz
V
SYSCLKOUT
DD
All inputs except XCLKIN
XCLKIN (@ 50 µA max)
All inputs except XCLKIN
XCLKIN (@ 50 µA max)
All I/Os except Group 2
V
DDIO
V
V
High-level input voltage
IH
0.7V
V
DD
DD
0.8
0.3V
Low-level input voltage
V
IL
DD
− 4
− 8
4
High-level output source current,
I
I
mA
mA
OH
‡
V
OH
= 2.4 V
Group 2
All I/Os except Group 2
Low-level output sink current,
= V MAX
OL
‡
V
OL
OL
Group 2
8
A version
S version
− 40
− 40
− 40
85
°C
°C
Ambient
temperature
§
125
125
T
A
Q version
†
‡
§
See Section 6.7 for power sequencing of V
Group 2 pins are as follows: XINTF pins, PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
Replaced by Q temperature option from silicon revision E onwards
, V
, V , V
V
AV
.
DDIO
DDAIO
DD
DDA1, DDA2, and
DDREFBG
6.3
Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
I
I
I
= I MAX
2.4
OH
OH
OL
OH
V
V
High-level output voltage
Low-level output voltage
OH
= 50 µA
V
− 0.2
DDIO
= I MAX
OL
0.4
V
OL
§
All I/Os (including XRS)
−80
−13
−140 −190
V
V
= 3.3 V,
= 0 V
DDIO
Input
current
except EVB
With pullup
I
IL
IN
µA
GPIOB/EVB
−25
−35
±2
(low level)
With pulldown
V
V
= 3.3 V, V = 0 V
IN
DDIO
DDIO
DDIO
With pullup
Input
current
(high level)
= 3.3 V, V = V
±2
IN
DD
I
I
µA
µA
IH
V
V
= 3.3 V,
¶
With pulldown
28
50
80
= V
IN
DD
Output current,
high-impedance state
(off-state)
V
O
= V
or 0 V
±2
OZ
DDIO
C
C
Input capacitance
Output capacitance
2
3
pF
pF
i
o
§
¶
The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and GPIOG5.
The following pins have an internal pulldown: XMP/MC, TESTSEL, and TRST.
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Electrical Specifications
6.4
Current Consumption by Power-Supply Pins Over Recommended Operating Conditions
During Low-Power Modes at 150-MHz SYSCLKOUT (TMS320R281x)
†
I
I
I
DDA
DD
DDIO
MODE
TEST CONDITIONS
‡
‡
‡
TYP
MAX
TYP
MAX
TYP
MAX
All peripheral clocks are enabled. All PWM pins
are toggled at 100 kHz.
Data is continuously transmitted out of the SCIA,
SCIB, and CAN ports. The hardware multiplier is
exercised.
Operational
214 mA
5 mA
40 mA
Code is running out of internal SARAM.
−
−
XCLKOUT is turned off
All peripheral clocks
are on, except ADC
IDLE
125 mA
3 mA
5 mA
1 µA
1 µA
−
−
Peripheral clocks are
turned off
Pins without an internal
PU/PD are tied
high/low
STANDBY
5 µA
−
−
Peripheral clocks are
turned off
Pins without an internal
PU/PD are tied
high/low
HALT
10 µA
5 µA
1 µA
−
Input clock is disabled
†
‡
I
includes current into V
, V
, AV
, and V
pins.
DDA
DDA1
DDA2
DDREFBG
DDAIO
MAX numbers are at 125°C, and max voltage (V = 2.0 V; V
, V
= 3.6 V).
DD
DDIO DDA
NOTE:
HALT and STANDBY modes cannot be used when the PLL is disabled.
86
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Electrical Specifications
6.5
Current Consumption Graphs
240
IDD
IDDIO
IDDA
Total
210
180
150
120
90
60
30
0
0
5
15
30
45
60
75
90
105
120
135
150
SYSCLOCKOUT (MHz)
Figure 6−1. R2812/R2811 Typical Current Consumption (With Peripheral Clocks Enabled)
6.6
Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 6−1 indicates the typical reduction in current consumption achieved by turning off the clocks
to various peripherals.
†
Table 6−1. Typical Current Consumption by Various Peripherals (at 150 MHz)
PERIPHERAL MODULE
I
CURRENT REDUCTION (mA)
DD
12
6
eCAN
EVA
6
EVB
‡
ADC
SCI
8
4
5
SPI
McBSP
13
†
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks
are turned on.
This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the
‡
elimination of the current drawn by the analog portion of the ADC (I
) as well.
CCA
6.7
Power Sequencing Requirements
Power sequencing is not required on the R281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp
together. R281x can also be used on boards that have F281x power sequencing implemented; however, if
the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least
1 V.
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6.8
Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions
table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.4 V.
Figure 6−2 shows output levels.
2.4 V (V
80%
)
OH
20%
0.4 V (V
)
OL
Figure 6−2. Output Levels
Output transition times are specified as follows:
•
For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
•
For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total
voltage range and higher and the level at which the output is said to be high is 80% of the total voltage
range and higher.
Figure 6−3 shows the input levels.
2.0 V (V
90%
)
IH
10%
0.8 V (V )
IL
Figure 6−3. Input Levels
Input transition times are specified as follows:
•
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the
total voltage range and lower.
•
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the
total voltage range and higher.
NOTE: See the individual timing diagrams for levels used for testing timing parameters.
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Electrical Specifications
6.9
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don’t care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
6.10 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this document.
6.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timing.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6−4. 3.3-V Test Load Circuit
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6.12 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on R281x DSPs. Table 6−2 lists the cycle times of various clocks.
Table 6−2. TMS320R281x Clock Table and Nomenclature
MIN
28.6
20
NOM
MAX
50
UNIT
ns
t
, Cycle time
c(OSC)
On-chip oscillator clock
XCLKIN
Frequency
, Cycle time
35
MHz
ns
t
6.67
4
250
150
500
150
2000
150
c(CI)
Frequency
, Cycle time
MHz
ns
t
6.67
2
c(SCO)
SYSCLKOUT
XCLKOUT
HSPCLK
Frequency
, Cycle time
MHz
ns
t
6.67
0.5
6.67
c(XCO)
Frequency
, Cycle time
MHz
ns
‡
t
13.3
c(HCO)
‡
Frequency
, Cycle time
75
150
75
MHz
ns
‡
t
13.3
40
26.6
c(LCO)
LSPCLK
‡
Frequency
, Cycle time
37.5
MHz
ns
†
t
c(ADCCLK)
ADC clock
SPI clock
Frequency
, Cycle time
25
MHz
ns
t
50
c(SPC)
Frequency
, Cycle time
20
MHz
ns
t
50
c(CKG)
McBSP
Frequency
, Cycle time
20
MHz
ns
t
6.67
c(XTIM)
XTIMCLK
Frequency
150
MHz
†
‡
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower.
ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
This is the default reset value if SYSCLKOUT = 150 MHz.
6.13 Clock Requirements and Characteristics
6.13.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6−3. Input Clock Frequency
PARAMETER
MIN
20
20
4
TYP
MAX
35
UNIT
MHz
MHz
Resonator
Crystal
35
f
f
Input clock frequency
x
XCLKIN
150
2
Limp mode clock frequency
l
90
SPRS257
June 2004
Electrical Specifications
Table 6−4. XCLKIN Timing Requirements − PLL Bypassed or Enabled
NO.
C8
MIN
MAX
250
6
UNIT
t
t
Cycle time, XCLKIN
6.67
ns
c(CI)
Up to 30 MHz
C9
Fall time, XCLKIN
ns
ns
f(CI)
30 MHz to 150 MHz
2
Up to 30 MHz
6
C10
t
Rise time, XCLKIN
30 MHz to 150 MHz
r(CI)
2
C11
C12
t
t
Pulse duration, X1/XCLKIN low as a percentage of t
40
40
60
60
%
%
w(CIL)
c(CI)
Pulse duration, X1/XCLKIN high as a percentage of t
w(CIH)
c(CI)
Table 6−5. XCLKIN Timing Requirements − PLL Disabled
NO.
MIN
MAX
250
6
UNIT
C8
t
t
Cycle time, XCLKIN
6.67
ns
c(CI)
Up to 30 MHz
C9
Fall time, XCLKIN
Rise time, XCLKIN
ns
ns
f(CI)
30 MHz to 150 MHz
Up to 30 MHz
2
6
C10
t
t
t
r(CI)
30 MHz to 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
2
40
45
40
45
60
55
C11
C12
Pulse duration, X1/XCLKIN low as a percentage of t
%
%
w(CIL)
c(CI)
XCLKIN ≤ 120 MHz
60
55
Pulse duration, X1/XCLKIN high as a percentage of t
w(CIH)
c(CI)
120 < XCLKIN ≤ 150 MHz
Table 6−6. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely
disabled. Clock input to the CPU (CLKIN) is directly derived from the clock
signal present at the X1/XCLKIN pin.
PLL Disabled
PLL Bypassed
PLL Enabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL
itself is bypassed. However, the /2 module in the PLL block divides the clock
input at the X1/XCLKIN pin by two before feeding it to the CPU.
XCLKIN/2
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module
in the PLL block now divides the output of the PLL by two before feeding it to
the CPU.
(XCLKIN * n) / 2
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June 2004
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Electrical Specifications
6.13.2 Output Clock Characteristics
†‡
Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
No.
C1
C3
C4
C5
C6
C7
PARAMETER
Cycle time, XCLKOUT
MIN
TYP
MAX
UNIT
ns
§
t
t
t
t
t
t
6.67
c(XCO)
Fall time, XCLKOUT
2
2
ns
f(XCO)
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
ns
r(XCO)
H−2
H−2
H+2
H+2
ns
w(XCOL)
w(XCOH)
ns
131072t
ns
p
c(CI)
†
‡
§
A load of 40 pF is assumed for these parameters.
H = 0.5t
The PLL must be used for maximum frequency operation.
c(XCO)
C10
C9
C8
XCLKIN
C6
(see Note A)
C1
C3
C4
C5
XCLKOUT
(see Note B)
NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6−5 is
intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6−5. Clock Timing
6.14 Reset Timing
†
Table 6−8. Reset (XRS) Timing Requirements
MIN
NOM
MAX
UNIT
t
t
8t
cycles
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
w(RSL1)
c(CI)
Warm reset
8t
c(CI)
cycles
w(RSL2)
WD-initiated reset
512t
c(CI)
c(CI)
c(CI)
10
t
t
Pulse duration, reset pulse generated by watchdog
Delay time, address/data valid after XRS high
Oscillator start-up time
512t
32t
cycles
cycles
w(WDRS)
d(EX)
‡
t
t
t
t
t
1
ms
OSCST
16t
16t
16t
cycles
cycles
cycles
cycles
Setup time for XPLLDIS pin
su(XPLLDIS)
h(XPLLDIS)
h(XMP/MC)
h(boot-mode)
c(CI)
c(CI)
Hold time for XPLLDIS pin
Hold time for XMP/MC pin
c(CI)
§
2520t
Hold time for boot-mode pins
c(CI)
†
‡
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after V reaches 1.5 V.
Dependent on crystal/resonator and board design.
DD
92
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June 2004
Electrical Specifications
†
V
V
, V
,
DDIO DDAn
2.5 V
0.3 V
(3.3 V)
(See Note A)
DDAIO
V
, V
DD1
(1.8 V (or 1.9 V))
DD
XCLKIN
X1
XCLKIN/8 (See Note B)
User-Code Dependent
XCLKOUT
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
User-Code Execution Phase
User-Code Dependent
t
d(EX)
t
su(XPLLDIS)
t
h(XPLLDIS)
XPLLDIS Sampling
(Don’t Care)
XF/XPLLDIS
XMP/MC
GPIOF14
t
h(XMP/MC)
(Don’t Care)
t
h(boot-mode)
see Note C)
(
User-Code Dependent
Boot-Mode Pins
See Note D
GPIO Pins as Input
Boot-ROM Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
Peripheral/GPIO Function
Based on Boot Code
I/O Pins
NOTES: A.
V
− V
/V
and AV
DDAn
DDA1 DDA2 DDREFBG
B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This
explains why XCLKOUT = XCLKIN/8 during this phase.
C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM
execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL
enabled.
D. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least
1 V and 3.3-V supply reaches 2.5 V.
Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0)
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June 2004
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Electrical Specifications
V
, V
(3.3 V)
,
DDIO DDAn
2.5 V
0.3 V
V
DDAIO
V
DD
, V
DD1
(1.8 V (or
1.9 V))
XCLKIN
X1
t
OSCST
XCLKOUT
XRS
User-Code Dependent
XCLKIN/8 (See Note A)
t
w(RSL)
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
t
d(EX)
Address/Data/
Control
(Don’t Care)
XPLLDIS Sampling
(Don’t Care)
t
h(XPLLDIS)
XF/XPLLDIS
XMP/MC
GPIOF14/XF (User-Code Dependent)
t
su(XPLLDIS)
(Don’t Care)
t
h(XMP/MC)
I/O Pins
User-Code Dependent
See Note B
Input Configuration (State Depends on Internal PU/PD)
NOTES: A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2
register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why
XCLKOUT = XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V
and 3.3-V supply reaches 2.5 V..
Figure 6−7. Power-on Reset in Microprocessor Mode (XMP/MC = 1)
94
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Electrical Specifications
XCLKIN
X1
XCLKIN/8
XCLKOUT
(XCLKIN * 5)
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
GPIOF14/XF
t
t
su(XPLLDIS)
h(XPLLDIS)
(Don’t Care)
XF/XPLLDIS
XMP/MC
GPIOF14
User-Code Dependent
(Don’t Care)
XPLLDIS Sampling
t
h(XMP/MC)
(Don’t Care)
†
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Peripheral/GPIO Function
User-Code Dependent
Boot-Mode Pins
I/O Pins
Peripheral/GPIO Function
User-Code Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
†
After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT
Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The
BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot
modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current
SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6−8. Warm Reset in Microcomputer Mode
95
June 2004
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Electrical Specifications
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN*2
XCLKIN/2
XCLKIN*4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
131072 XCLKIN Cycles Long.)
Figure 6−9. Effect of Writing Into PLLCR Register
96
SPRS257
June 2004
Electrical Specifications
6.15 Low-Power Mode Wakeup Timing
Table 6−9 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6−9. IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
MIN
TYP
MAX
UNIT
Cycles
Cycles
2 * t
c(SCO)
†
Pulse duration, external wake-up
signal
t
t
w(WAKE-INT)
1 * t
+ IQT
c(SCO)
Delay time, external wake signal to
program execution resume
‡
d(WAKE-IDLE)
− Wake-up from SARAM
− Wake-up from SARAM
Without input qualifier
With input qualifier
8 * t
Cycles
Cycles
c(SCO)
†
8 * t
+ IQT
c(SCO)
†
‡
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
c(SCO)
t
d(WAKE−IDLE)
A0−A15
†
XCLKOUT
t
w(WAKE−INT)
‡
WAKE INT
†
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
‡
Figure 6−10. IDLE Entry and Exit Timing
Table 6−10 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6−10. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT high
t
t
32 * t
12 * t
c(CI)
Cycles
d(IDLE-XCOH)
c(SCO)
Without input qualifier
With input qualifier
12 * t
Cycles
Cycles
c(CI)
Pulse duration, external
wake-up signal
w(WAKE-INT)
†
(2 + QUALSTDBY) * t
c(CI)
Delay time, external wake
signal to program execution
‡
resume
t
d(WAKE-STBY)
− Wake-up from SARAM
− Wake-up from SARAM
Without input qualifier
With input qualifier
12 * t
Cycles
Cycles
c(CI)
12 * t
+ t
w(WAKE-INT)
c(CI)
†
‡
QUALSTDBY is a 6-bit field in the LPMCR0 register.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
97
June 2004
SPRS257
Electrical Specifications
A
C
E
B
D
F
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/XCLKIN
t
d(IDLE−XCOH)
†
XCLKOUT
32 SYSCLKOUT Cycles
NOTES: A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being turned
off. This 32−cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. The device is now in STANDBY mode.
D. The external wake−up signal is driven active (negative edge triggered shown as an example).
E. After a latency period, the STANDBY mode is exited.
F. Normal operation resumes. The device will respond to the interrupt (if enabled).
Figure 6−11. STANDBY Entry and Exit Timing
Table 6−11. HALT Mode Switching Characteristics
PARAMETER
MIN
32 * t
TYP
45 * t
c(SCO)
MAX
UNIT
Cycles
Cycles
Cycles
Cycles
t
t
t
t
Delay time, IDLE instruction executed to XCLKOUT high
Pulse duration, XNMI wakeup signal
Pulse duration, XRS wakeup signal
PLL lock-up time
d(IDLE-XCOH)
w(WAKE-XNMI)
w(WAKE-XRS)
p
c(SCO)
2 * t
8 * t
c(CI)
c(CI)
131072 * t
c(CI)
Delay time, PLL lock to program execution resume
t
d(wake)
35*tc(SCO)
Cycles
− Wake-up from SARAM
98
SPRS257
June 2004
Electrical Specifications
A
C
E
G
B
D
HALT
F
Device
Status
HALT
Flushing Pipeline
PLL Lock−up Time
Normal
Execution
Wake−up Latency
XNMI
t
t
d(INT)
w(WAKE−XNMI)
t
p
X1/XCLKIN
Oscillator Start-up Time
t
d(IDLE−XCOH)
†
XCLKOUT
32 SYSCLKOUT Cycles
†
XCLKOUT = SYSCLKOUT
NOTES: A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the
CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the PLL is not
activated.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now
exited.
G. Normal operation resumes.
Figure 6−12. HALT Wakeup Using XNMI
99
June 2004
SPRS257
Electrical Specifications
6.16 Event Manager Interface
6.16.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
†‡
Table 6−12. PWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ns
§
t
t
25
Pulse duration, PWMx output high/low
Delay time, XCLKOUT high to PWMx output switching
w(PWM)
XCLKOUT = SYSCLKOUT/4
10
ns
d(PWM)XCO
†
‡
§
See the GPIO output timing for fall/rise times for PWM pins.
PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
PWM outputs may be 100%, 0%, or increments of t with respect to the PWM period.
c(HCO)
¶#
Table 6−13. Timer and Capture Unit Timing Requirements
MIN
2 * t
MAX
UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
c(SCO)
t
t
Pulse duration, TDIRx low/high
cycles
w(TDIR)
||
1 * t
+ IQT
c(SCO)
2 * t
c(SCO)
Pulse duration, CAPx input low/high
cycles
w(CAP)
||
1 * t
+ IQT
c(SCO)
t
t
t
40
60
60
%
%
ns
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
Cycle time, TCLKINx
w(TCLKINL)
w(TCLKINH)
c(TCLKIN)
40
4 * t
c(HCO)
¶
The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling period is
2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the qualification sampling
period is 1 x 2 = 2 SYSCLKOUT cycles (i.e., the input is sampled every 2 SYSCLKOUT cycles). Six such samples will be taken over five sampling
windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width that is needed is 5 x 2 = 10 SYSCLKOUT cycles.
However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide pulse ensures reliable recognition.
Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
#
||
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
†
XCLKOUT
t
d(PWM)XCO
t
w(PWM)
PWMx
†
XCLKOUT = SYSCLKOUT
Figure 6−13. PWM Output Timing
†
XCLKOUT
t
w(TDIR)
TDIRx
†
XCLKOUT = SYSCLKOUT
Figure 6−14. TDIRx Timing
100
SPRS257
June 2004
Electrical Specifications
†
Table 6−14. External ADC Start-of-Conversion − EVA − Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
t
1 * t
cycle
Delay time, XCLKOUT high to EVASOC low
Pulse duration, EVASOC low
d(XCOH-EVASOCL)
c(SCO)
32 * t
ns
w(EVASOCL)
c(HCO)
†
XCLKOUT = SYSCLKOUT
XCLKOUT
EVASOC
t
d(XCOH-EVASOCL)
t
w(EVASOCL)
Figure 6−15. EVASOC Timing
Table 6−15. External ADC Start-of-Conversion − EVB − Switching Characteristics
†
PARAMETER
MIN
MAX
UNIT
t
t
1 * t
cycle
Delay time, XCLKOUT high to EVBSOC low
Pulse duration, EVBSOC low
d(XCOH-EVBSOCL)
c(SCO)
32 * t
ns
w(EVBSOCL)
c(HCO)
†
XCLKOUT = SYSCLKOUT
XCLKOUT
EVBSOC
t
d(XCOH-EVBSOCL)
t
w(EVBSOCL)
Figure 6−16. EVBSOC Timing
101
June 2004
SPRS257
Electrical Specifications
6.16.2 Interrupt Timing
Table 6−16. Interrupt Switching Characteristics
PARAMETER
MIN
MAX
UNIT
Without input
qualifier
12
Delay time, PDPINTx low to PWM
high-impedance state
t
ns
d(PDP-PWM)HZ
†
With input qualifier
1 * t
+ IQT + 12
c(SCO)
Without input
qualifier
Delay time, CxTRIP/TxCTRIP
signals low to PWM
high-impedance state
3 * t
c(SCO)
t
t
ns
ns
d(TRIP-PWM)HZ
†
With input qualifier
[2 * t
] + IQT
c(SCO)
t
+ 12t
Delay time, INT low/high to interrupt-vector fetch
d(INT)
qual
c(XCO)
†
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
Table 6−17. Interrupt Timing Requirements
MIN
2 * t
MAX
UNIT
with no qualifier
c(SCO)
t
t
t
t
Pulse duration, INT input low/high
cycles
w(INT)
†
†
†
†
1 * t
+ IQT
with qualifier
c(SCO)
2 * t
with no qualifier
with qualifier
c(SCO)
Pulse duration, PDPINTx input low
Pulse duration, CxTRIP input low
Pulse duration, TxCTRIP input low
cycles
cycles
cycles
w(PDP)
1 * t
+ IQT
c(SCO)
2 * t
with no qualifier
with qualifier
c(SCO)
w(CxTRIP)
w(TxCTRIP)
1 * t
+ IQT
c(SCO)
2 * t
with no qualifier
with qualifier
c(SCO)
1 * t
+ IQT
c(SCO)
†
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
102
SPRS257
June 2004
Electrical Specifications
†
XCLKOUT
t
, t
, t
w(PDP) w(CxTRIP) w(TxCTRIP)
TxCTRIP, CxTRIP,
‡
PDPINTx
t
, t
d(PDP-PWM)HZ d(TRIP-PWM)HZ
§
PWM
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Interrupt Vector
A0−A15
†
XCLKOUT = SYSCLKOUT
‡
TxCTRIP − T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP
CxTRIP C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP
PDPINTx − PDPINTA or PDPINTB
−
§
PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin). The
state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
Figure 6−17. External Interrupt Timing
6.17 General-Purpose Input/Output (GPIO) − Output Timing
Table 6−18. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
t
t
Delay time, XCLKOUT high to GPIO low/high
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
All GPIOs
All GPIOs
All GPIOs
1 * t
cycle
ns
d(XCOH-GPO)
c(SCO)
10
r(GPO)
10
20
ns
f(GPO)
f
Toggling frequency, GPO pins
MHz
GPO
XCLKOUT
t
d(XCOH-GPO)
GPIO
t
r(GPO)
t
f(GPO)
Figure 6−18. General-Purpose Output Timing
103
June 2004
SPRS257
Electrical Specifications
6.18 General-Purpose Input/Output (GPIO) − Input Timing
See Note A
GPIO
Signal
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
QUALPRD
Sampling Window
QUALPRD = 1
SYSCLKOUT
(2 x SYSCLKOUT cycles) x 5
Output From
Qualifier
NOTES: A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary
from 00 to 0xFF. Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the qualification sampling
period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycle, the GPIO pin will be sampled). Six consecutive samples
must be of the same value for a given input to be recognized.
B. For the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs
should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure six sampling windows for detection to occur.
Since external signals are driven asynchronously, an 11-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 6−19. GPIO Input Qualifier − Example Diagram for QUALPRD = 1
Table 6−19. General-Purpose Input Timing Requirements
MIN
MAX
UNIT
With no qualifier
With qualifier
2 * t
c(SCO)
†
t
Pulse duration, GPIO low/high
All GPIOs
cycles
w(GPI)
1 * t
+ IQT
c(SCO)
†
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
XCLKOUT
GPIOxn
t
w(GPI)
Figure 6−20. General-Purpose Input Timing
NOTE:
The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC
pins as well.
104
SPRS257
June 2004
6.19 SPI Master Mode Timing
†‡
Table 6−20. SPI Master Mode External Timing (Clock Phase = 0)
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
NO.
UNIT
MIN
MAX
MIN
MAX
1
t
t
Cycle time, SPICLK
4t
128t
5t
127t
ns
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
c(LCO)
Pulse duration, SPICLK high
(clock polarity = 0)
0.5t
0.5t
0.5t
0.5t
−10
−10
−10
−10
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
−0.5t
−0.5t
+0.5t
+0.5t
−10
−10
−10
−10
0.5t
0.5t
−0.5t
w(SPCH)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
c(LCO)
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
§
ns
ns
ns
2
3
4
Pulse duration, SPICLK low
(clock polarity = 1)
t
t
t
t
t
−0.5t
w(SPCL)M
c(SPC)M
c(SPC)M
c(SPC)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
0.5t
+ 0.5t
+ 0.5t
w(SPCL)M
§
§
Pulse duration, SPICLK high
(clock polarity = 1)
w(SPCH)M
c(SPC)M
c(LCO)
Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0)
− 10
− 10
10
− 10
− 10
10
d(SPCH-SIMO)M
d(SPCL-SIMO)M
Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1)
10
10
Valid time, SPISIMO data valid
after SPICLK low
(clock polarity = 0)
t
t
0.5t
0.5t
−10
−10
0.5t
0.5t
+0.5t
+0.5t
−10
−10
v(SPCL-SIMO)M
v(SPCH-SIMO)M
c(SPC)M
c(SPC)M
c(LCO)
§
§
§
ns
ns
ns
5
8
9
Valid time, SPISIMO data valid
after SPICLK high
c(SPC)M
c(SPC)M
c(LCO)
(clock polarity = 1)
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
t
t
0
0
0
0
su(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
su(SOMI-SPCH)M
Valid time, SPISOMI data valid
after SPICLK low
(clock polarity = 0)
t
0.25t
0.25t
−10
−10
0.5t
0.5t
−0.5t
−0.5t
−10
v(SPCL-SOMI)M
v(SPCH-SOMI)M
c(SPC)M
c(SPC)M
c(LCO)
Valid time, SPISOMI data valid
after SPICLK high
t
−10
c(SPC)M
c(SPC)M
c(LCO)
(clock polarity = 1)
†
‡
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
4
LSPCLK
(SPIBRR ) 1)
t
= SPI clock cycle time =
or
c(SPC)
t
= LSPCLK cycle time
c(LCO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
ADVANCE INFORMATION
Electrical Specifications
1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
†
SPISTE
†
In the master mode, SPISTE goes active 0.5t
before valid SPI clock edge. On the trailing end of the word, the
c(SPC)
SPISTE will go inactive 0.5t
after the receiving edge (SPICLK) of the last data bit.
c(SPC)
Figure 6−21. SPI Master Mode External Timing (Clock Phase = 0)
106
SPRS257
June 2004
†‡
Table 6−21. SPI Master Mode External Timing (Clock Phase = 1)
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
NO.
UNIT
MIN
4t
MAX
MIN
MAX
127t
c(LCO)
1
t
t
Cycle time, SPICLK
128t
5t
ns
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
Pulse duration, SPICLK high
(clock polarity = 0)
0.5t
−10
−10
−10
−10
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
−0.5t
−10
−10
−10
−10
0.5t
0.5t
−0.5t
w(SPCH)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(LCO)
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
c(LCO)
§
ns
ns
2
Pulse duration, SPICLK low
(clock polarity = 1)
t
t
t
0.5t
0.5t
0.5t
−0.5t
+0.5t
+0.5t
−0.5t
w(SPCL)M
w(SPCL)M
w(SPCH)M
c(SPC)M
c(SPC)M
c(SPC)M
c(LCO)
c(LCO)
c(LCO)
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
0.5t
+ 0.5t
+ 0.5t
§
3
Pulse duration, SPICLK high
(clock polarity = 1)
Setup time, SPISIMO data
valid before SPICLK high
(clock polarity = 0)
t
t
t
t
t
t
t
t
0.5t
0.5t
0.5t
0.5t
−10
−10
−10
−10
0
0.5t
−10
−10
−10
−10
0
su(SIMO-SPCH)M
su(SIMO-SPCL)M
v(SPCH-SIMO)M
v(SPCL-SIMO)M
su(SOMI-SPCH)M
su(SOMI-SPCL)M
v(SPCH-SOMI)M
v(SPCL-SOMI)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
c(SPC)M
§
ns
ns
ns
ns
6
Setup time, SPISIMO data
valid before SPICLK low
(clock polarity = 1)
0.5t
0.5t
0.5t
Valid time, SPISIMO data
valid after SPICLK high
(clock polarity = 0)
§
7
Valid time, SPISIMO data
valid after SPICLK low
(clock polarity = 1)
Setup time, SPISOMI before
SPICLK high
(clock polarity = 0)
§
10
Setup time, SPISOMI before
SPICLK low
(clock polarity = 1)
0
0
Valid time, SPISOMI data
valid after SPICLK high
(clock polarity = 0)
0.25t
0.25t
−10
−10
0.5t
0.5t
−10
−10
c(SPC)M
c(SPC)M
§
11
Valid time, SPISOMI data
valid after SPICLK low
(clock polarity = 1)
c(SPC)M
c(SPC)M
†
‡
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
4
LSPCLK
(SPIBRR ) 1)
t
= SPI clock cycle time =
or
c(SPC)
t
= LSPCLK cycle time
c(LCO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
ADVANCE INFORMATION
Electrical Specifications
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data
Must Be Valid
†
SPISTE
†
In the master mode, SPISTE goes active 0.5t
before valid SPI clock edge. On the trailing end of the word, the
c(SPC)
SPISTE will go inactive 0.5t
after the receiving edge (SPICLK) of the last data bit.
c(SPC)
Figure 6−22. SPI Master External Timing (Clock Phase = 1)
108
SPRS257
June 2004
Electrical Specifications
6.20 SPI Slave Mode Timing
†‡
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0)
NO.
MIN
MAX
UNIT
‡
12
t
t
t
t
t
Cycle time, SPICLK
4t
ns
c(SPC)S
c(LCO)
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
0.5t
−10
−10
−10
−10
0.5t
w(SPCH)S
w(SPCL)S
w(SPCL)S
w(SPCH)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
§
ns
ns
13
0.5t
0.5t
0.5t
0.5t
0.5t
0.5t
§
14
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
t
t
t
0.375t
0.375t
−10
−10
d(SPCH-SOMI)S
d(SPCL-SOMI)S
v(SPCL-SOMI)S
c(SPC)S
c(SPC)S
§
ns
15
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75t
c(SPC)S
c(SPC)S
§
ns
ns
ns
16
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
t
0.75t
v(SPCH-SOMI)S
t
t
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
su(SIMO-SPCL)S
§
19
0
su(SIMO-SPCH)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
t
0.5t
v(SPCL-SIMO)S
v(SPCH-SIMO)S
c(SPC)S
§
20
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
t
0.5t
c(SPC)S
†
‡
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
LSPCLK
4
LSPCLK
(SPIBRR ) 1)
t
= SPI clock cycle time =
or
c(SPC)
t
= LSPCLK cycle time
c(LCO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Electrical Specifications
12
SPICLK
(clock polarity = 0)
13
15
14
SPICLK
(clock polarity = 1)
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
†
SPISTE
†
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
before the valid SPI clock edge and remain
c(SPC)
low for at least 0.5t
after the receiving edge (SPICLK) of the last data bit.
c(SPC)
Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0)
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SPRS257
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Electrical Specifications
†‡
Table 6−23. SPI Slave Mode External Timing (Clock Phase = 1)
NO.
MIN
MAX
UNIT
12
t
t
t
t
t
t
t
Cycle time, SPICLK
8t
0.5t
0.5t
0.5t
0.5t
ns
c(SPC)S
c(LCO)
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
−10
−10
−10
−10
0.5t
w(SPCH)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
c(SPC)S
§
ns
ns
ns
13
0.5t
0.5t
0.5t
w(SPCL)S
w(SPCL)S
§
14
w(SPCH)S
0.125t
su(SOMI-SPCH)S
su(SOMI-SPCL)S
c(SPC)S
c(SPC)S
§
17
0.125t
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
t
t
0.75t
v(SPCH-SOMI)S
c(SPC)S
c(SPC)S
§
ns
ns
ns
18
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75t
v(SPCL-SOMI)S
t
t
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
0
su(SIMO-SPCH)S
§
21
su(SIMO-SPCL)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
t
0.5t
0.5t
v(SPCH-SIMO)S
v(SPCL-SIMO)S
c(SPC)S
§
22
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
t
c(SPC)S
†
‡
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
LSPCLK
4
LSPCLK
(SPIBRR ) 1)
t
= SPI clock cycle time =
or
c(SPC)
t
= LSPCLK cycle time
c(LCO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
21
Data Valid
22
SPISIMO Data
Must Be Valid
†
SPISTE
†
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
before the valid SPI clock edge and
c(SPC)
remain low for at least 0.5t
after the receiving edge (SPICLK) of the last data bit.
c(SPC)
Figure 6−24. SPI Slave Mode External Timing (Clock Phase = 1)
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Electrical Specifications
6.21 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6−24 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
†‡
Table 6−24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)
DESCRIPTION
X2TIMING = 0
XRDLEAD x t
X2TIMING = 1
(XRDLEAD x 2) x t
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
− Cycle time, XTIMCLK
c(XTIM)
c(XTIM)
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) x t
(XRDACTIVE x 2 + WS + 1) x t
c(XTIM)
c(XTIM)
c(XTIM)
c(XTIM)
XRDTRAIL x t
XWRLEAD x t
(XRDTRAIL x 2) x t
(XWRLEAD x 2) x t
c(XTIM)
c(XTIM)
(XWRACTIVE + WS + 1) x t
XWRTRAIL x t
(XWRACTIVE x 2 + WS + 1) x t
c(XTIM)
c(XTIM)
(XWRTRAIL x 2) x t
c(XTIM)
c(XTIM)
†
‡
t
c(XTIM)
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
•
If the XREADY signal is ignored (USEREADY = 0), then:
1. Lead: LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
§
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 0
≥ 1
≥ 0
≥ 0
0, 1
§
No hardware to detect illegal XTIMING configurations
§
Examples of valid and invalid timing when not sampling XREADY :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Valid
0
1
0
0
0
0
0
1
0
0
0
0
0, 1
§
No hardware to detect illegal XTIMING configurations
112
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Electrical Specifications
•
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
1. Lead:
LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
2. Active:
AR ≥ 2 x t
c(XTIM)
AW ≥ 2 x t
c(XTIM)
NOTE: Restriction does not include external hardware wait states
†
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 1
≥ 0
≥ 1
≥ 1
≥ 0
0, 1
†
No hardware to detect illegal XTIMING configurations
†
Examples of valid and invalid timing when using Synchronous XREADY :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Invalid
Valid
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0, 1
0, 1
†
No hardware to detect illegal XTIMING configurations
•
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1. Lead:
LR ≥ t
c(XTIM)
LW ≥ t
c(XTIM)
2. Active:
AR ≥ 2 x t
c(XTIM)
AW ≥ 2 x t
c(XTIM)
NOTE: Restriction does not include external hardware wait states
3. Lead + Active: LR + AR ≥ 4 x t
c(XTIM)
LW + AW ≥ 4 x t
c(XTIM)
NOTE: Restriction does not include external hardware wait states
†
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
†
†
No hardware to detect illegal XTIMING configurations
†
or
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 1
0
≥ 2
≥ 1
0
0, 1
No hardware to detect illegal XTIMING configurations
†
Examples of valid and invalid timing when using Asynchronous XREADY :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
Invalid
Invalid
Valid
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
1
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
†
No hardware to detect illegal XTIMING configurations
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Electrical Specifications
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6−25.
Table 6−25. XINTF Clock Configurations
Mode
SYSCLKOUT
XTIMCLK
XCLKOUT
1
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
Example:
150 MHz
2
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
150 MHz
3
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
150 MHz
4
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6−25.
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
SYSCLKOUT
XCLKOUT
1
R28x
CPU
†
XTIMCLK
0
1
/2
†
1
/2
0
0
0
XINTCNF2
(CLKOFF)
XINTCNF2
(XTIMCLK)
XINTCNF2
(CLKMODE)
†
Default Value after reset
Figure 6−25. Relationship Between XTIMCLK and SYSCLKOUT
6.22 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE, and zone chip-select (XZCS) change state in relationship to the rising edge of
XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency
of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation
XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or
XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the
notation XCOH is used.
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Electrical Specifications
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XR/W active low
XRNWL
•
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the
total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd,
then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XWEL
XRD active low
XWE active low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead +
active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with
respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XR/W inactive high
XRNWH
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June 2004
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Electrical Specifications
6.23 External Interface Read Timing
Table 6−26. External Memory Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
t
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
d(XCOH-XZCSL)
t
−2
ns
d(XCOHL-XZCSH)
t
ns
d(XCOH-XA)
t
t
t
t
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
d(XCOHL-XRDL)
d(XCOHL-XRDH
h(XA)XZCSH
−2
†
ns
ns
†
ns
h(XA)XRD
†
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6−27. External Memory Interface Read Timing Requirements
MIN
MAX
UNIT
ns
‡
t
t
Access time, read data from address valid
(LR + AR) − 14
a(A)
‡
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR − 12
ns
a(XRD)
t
12
0
ns
su(XD)XRD
t
ns
h(XD)XRD
‡
LR = Lead period, read access. AR = Active period, read access. See Table 6−24.
Trail
Active
Lead
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
t
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
XA[0:18]
XRD
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
XWE
XR/W
t
a(A)
t
h(XD)XRD
t
a(XRD)
DIN
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−26. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
†
†
†
†
≥1
≥0
≥0
0
0
N/A
N/A
N/A
N/A
†
N/A = “Don’t care” for this example
116
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Electrical Specifications
6.24 External Interface Write Timing
Table 6−28. External Memory Interface Write Switching Characteristics
PARAMETER
MIN MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
d(XCOH-XZCSL)
t
−2
3
2
2
2
1
1
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
t
t
t
t
t
t
t
t
d(XCOHL-XWEL)
d(XCOHL-XWEH)
d(XCOH-XRNWL)
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
−2
d(XCOHL-XRNWH)
en(XD)XWEL
0
4
d(XWEL-XD)
†
‡
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
h(XA)XZCSH
h(XD)XWE
TW−2
4
dis(XD)XRNW
†
‡
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = Trail period, write access. See Table 6−24.
Active
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
DOUT
XD[0:15]
XREADY
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 6−27. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
†
†
†
†
N/A
N/A
N/A
0
0
≥1
≥0
≥0
N/A
†
N/A = “Don’t care” for this example
117
June 2004
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Electrical Specifications
6.25 External Interface Ready-on-Read Timing With One External Wait State
Table 6−29. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN MAX
UNIT
ns
t
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
1
d(XCOH-XZCSL)
t
−2
3
2
1
1
ns
d(XCOHL-XZCSH)
t
ns
d(XCOH-XA)
t
t
t
t
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
d(XCOHL-XRDL)
d(XCOHL-XRDH
h(XA)XZCSH
−2
ns
†
ns
†
ns
h(XA)XRD
†
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6−30. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ns
‡
t
t
Access time, read data from address valid
(LR + AR) − 14
a(A)
‡
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
AR − 12
ns
a(XRD)
t
12
0
ns
su(XD)XRD
t
ns
h(XD)XRD
‡
LR = Lead period, read access. AR = Active period, read access. See Table 6−24.
§
Table 6−31. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN MAX
UNIT
ns
t
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
15
12
3
su(XRDYsynchL)XCOHL
t
ns
h(XRDYsynchL)
t
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
ns
e(XRDYsynchH)
t
15
0
ns
su(XRDYsynchH)XCOHL
t
ns
h(XRDYsynchH)XZCSH
§
The first XREADY (Synch) sample occurs with respect to E in Figure 6−28:
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each t until it is found to be high.
c(XTIM)
For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t − t
c(XTIM)
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
¶
Table 6−32. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN MAX
UNIT
ns
t
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
11
8
su(XRDYAsynchL)XCOHL
t
ns
h(XRDYAsynchL)
t
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
3
ns
e(XRDYAsynchH)
t
11
0
ns
su(XRDYAsynchH)XCOHL
t
ns
h(XRDYasynchH)XZCSH
¶
The first XREADY (Asynch) sample occurs with respect to E in Figure 6−29:
E = (XRDLEAD + XRDACTIVE −2) t
c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each t until it is found to be high.
c(XTIM)
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) t − t
c(XTIM)
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
118
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Electrical Specifications
WS (Synch)
Trail
See Notes A and B
Active
See Note C
Lead
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
t
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
d(XCOH-XA)
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
t
su(XD)XRD
XWE
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
Legend:
See Note D
See Note E
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t
− t
c(XTIM)
su(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6−28. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
0 = XREADY
(Synch)
†
†
†
≥1
3
≥1
1
0
N/A
N/A
N/A
†
N/A = “Don’t care” for this example
119
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Electrical Specifications
WS (Asynch)
Active
See Notes
A and B
See Note C
Lead
Trail
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
t
t
t
d(XCOH-XZCSL)
d(XCOH-XA)
d(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE
XR/W
t
su(XD)XRD
t
a(XRD)
t
a(A)
t
h(XD)XRD
DIN
XD[0:15]
t
su(XRDYasynchL)XCOHL
t
e(XRDYasynchH)
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment
cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE −3 +n) t
− t
c(XTIM)
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
E. Reference for the first sample is with respect to this point:
E = (XRDLEAD + XRDACTIVE −2) t
c(XTIM)
Figure 6−29. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
1 = XREADY
(Asynch)
†
†
†
≥1
3
≥1
1
0
N/A
N/A
N/A
†
N/A = “Don’t care” for this example
120
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Electrical Specifications
6.26 External Interface Ready-on-Write Timing With One External Wait State
Table 6−33. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
d(XCOH-XA)
−2
3
2
2
2
1
1
d(XCOHL-XWEL)
d(XCOHL-XWEH)
d(XCOH-XRNWL)
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
Delay time, data valid after XWE active low
−2
d(XCOHL-XRNWH)
en(XD)XWEL
0
4
d(XWEL-XD)
†
‡
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
h(XA)XZCSH
h(XD)XWE
TW−2
4
dis(XD)XRNW
†
‡
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see Table 6−24)
§
Table 6−34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN MAX
UNIT
ns
t
t
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
15
12
su(XRDYsynchL)XCOHL
ns
h(XRDYsynchL)
t
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
3
ns
e(XRDYsynchH)
t
15
0
ns
su(XRDYsynchH)XCOHL
h(XRDYsynchH)XZCSH
t
ns
§
The first XREADY (Synch) sample occurs with respect to E in Figure 6−30:
E =(XWRLEAD + XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each t until it is found to be high.
c(XTIM)
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n − 1) t − t
c(XTIM)
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
¶
Table 6−35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN MAX
UNIT
ns
t
t
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
11
8
su(XRDYasynchL)XCOHL
ns
h(XRDYasynchL)
t
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
3
ns
e(XRDYasynchH)
t
11
0
ns
su(XRDYasynchH)XCOHL
h(XRDYasynchH)XZCSH
t
ns
¶
The first XREADY (Synch) sample occurs with respect to E in Figure 6−31:
E = (XWRLEAD + XWRACTIVE − 2) t
c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each t until it is found to be high.
c(XTIM)
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) t − t
c(XTIM)
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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Electrical Specifications
WS (Synch)
Active
See
Notes A
and B
See Note C
Trail
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES:
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an
access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as
D = (XWRLEAD + XWRACTIVE + n − 1) t
− t
c(XTIM)
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE) t
c(XTIM)
Figure 6−30. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
0 = XREADY
(Synch)
†
†
†
N/A
N/A
N/A
1
0
≥1
3
≥1
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Electrical Specifications
WS (Asynch)
Active
See Notes
A and B
See Note C
Trail
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE −3 + n) t
− t
c(XTIM)
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3 and so forth.
E. Reference for the first sample is with respect to this point
E = (XWRLEAD + XWRACTIVE −2) t
c(XTIM)
Figure 6−31. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
1 = XREADY
(Asynch)
†
†
†
N/A
N/A
N/A
1
0
≥1
3
≥1
†
N/A = “Don’t care” for this example
123
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Electrical Specifications
6.27 XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XD[15:0]
XWE, XRD
XR/W
XZCS0AND1
XZCS2
XZCS6AND7
All other signals not listed in this group remain in their default or functional operational modes during these
signal events. Detailed timing diagram will be released in a future revision of this data sheet.
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Electrical Specifications
6.28 XHOLD/XHOLDA Timing
†‡
Table 6−36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
ns
t
t
t
t
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
4t
c(XTIM)
5t
c(XTIM)
3t
c(XTIM)
4t
c(XTIM)
d(HL-HiZ)
d(HL-HAL)
d(HH-HAH)
d(HH-BV)
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
ns
ns
†
‡
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
High-Impedance
XZCS6AND7
Valid
XA[18:0]
XD[15:0]
Valid
High-Impedance
Valid
See Note A
See Note B
NOTES: A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6−32. External Interface Hold Waveform
125
June 2004
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Electrical Specifications
†‡§
Table 6−37. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
MIN
MAX
UNIT
ns
t
t
t
t
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
4t
t
d(HL-HiZ)
d(HL-HAL)
d(HH-HAH)
d(HH-BV)
c(XTIM)+ c(XCO)
4t
c(XTIM
+2t
ns
c(XCO)
c(XTIM)
c(XTIM)
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
4t
6t
ns
ns
†
‡
§
When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance state.
The state of XHOLD is latched on the rising edge of XTIMCLK.
After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of XCLKOUT. Thus,
for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
t
d(HL-HAL)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HiZ)
t
d(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
High-Impedance
XZCS6AND7
High-Impedance
High-Impedance
Valid
XA[18:0]
XD[15:0]
Valid
Valid
See Note B
See Note A
NOTES:
A All pending XINTF accesses are completed.
B Normal XINTF operation resumes.
Figure 6−33. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
126
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Electrical Specifications
6.29 On-Chip Analog-to-Digital Converter
6.29.1 ADC Absolute Maximum Ratings†
Supply voltage range,
V
/V
to V
/V
/AV . . . . . . . . . . . . . . . . . . −0.3 V to 4.6 V
DDREFBG
SSA1 SSA2
DDA1 DDA2
V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
SS1
DD1
‡
Analog Input (ADCIN) Clamp Current, total (max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
†
‡
Unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. Stresses beyond those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above V
or below V . The continuous clamp
DDA
SS
current per pin is ± 2 mA.
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June 2004
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Electrical Specifications
6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6−38. DC Specifications (See Note 1)
PARAMETER
MIN
12
TYP
MAX
UNIT
Bits
Resolution
1
kHz
ADC clock (See Note 2)
25
MHz
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)
Offset error (See Note 3)
±1.5
±1
LSB
LSB
LSB
±80
Overall gain error with internal reference
(See Note 4)
±50
±50
LSB
LSB
Overall gain error with external reference
(See Note 5)
If ADCREFP-ADCREFM = 1 V ±0.1%
Channel-to-channel offset variation
Channel-to-channel Gain variation
±8
±8
LSB
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(See Note 6)
0
3
5
V
ADCLO
−5
0
10
3
mV
pF
Input capacitance
Input leakage current
±5
µA
INTERNAL VOLTAGE REFERENCE (See Note 4)
Accuracy, ADCV
Accuracy, ADCV
2
1
V
REFP
V
V
REFM
Voltage difference, ADCREFP - ADCREFM
Temperature coefficient
1
50
100
PPM/°C
µV
Reference noise
EXTERNAL VOLTAGE REFERENCE (See Note 5)
Accuracy, ADCV
Accuracy, ADCV
1.9
2
1
2.1
V
V
REFP
0.95
1.05
REFM
Input voltage difference,
ADCREFP - ADCREFM
0.99
1
1.01
V
NOTES: 1. Tested at 12.5-MHz ADCCLK
2. If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2
3. 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
4. A single tirmmed internal band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination
of the gain error shown here and the voltage reference accuracy (ADCREFP - ADCREFM). A software-based calibration
procedure is recommended for better accuracy. See F2812 ADC Calibration Application Note (literature number SPRA989) and
Section 5.2, Documentation Support, for relevant documents.
5. In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP-ADCREFM) will
determine the overall accuracy.
6. Voltages above V
+ 0.3 V or below V - 0.3 V applied to an analog input pin may temporarily affect the conversion of another
DDA
SS
pin. To avoid this, the analog inputs should be kept within these limits.
128
SPRS257
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Electrical Specifications
Table 6−39. AC Specifications
PARAMETER
Signal-to-noise ratio + distortion
MIN
TYP
64
MAX
UNIT
dB
SINAD
SNR
Signal-to-noise ratio
66
dB
THD (100 kHz)
ENOB (SNR)
SFDR
Total harmonic distortion
Effective number of bits
Spurious free dynamic range
−68
10.7
70
dB
Bits
dB
6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)‡
§
I
(TYP)
I
(TYP)
I (TYP)
DD1
ADC OPERATING MODE/CONDITIONS
DDA
DDAIO
Mode A (Operational Mode):
40 mA
1 µA
0.5 mA
−
−
BG and REF enabled
PWD disabled
Mode B:
−
−
−
ADC clock enabled
BG and REF enabled
PWD enabled
7 mA
1 µA
1 µA
0
0
0
5 µA
5 µA
0
Mode C:
−
−
−
ADC clock enabled
BG and REF disabled
PWD enabled
Mode D:
−
−
−
ADC clock disabled
BG and REF disabled
PWD enabled
‡
§
Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
− includes current into V /V and AV
I
DDA
DDA1 DDA2
DDREFBG
129
June 2004
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Electrical Specifications
R
1 kΩ
on
Switch
R
ADCIN0
s
C
10 pF
C
h
1.25 pF
p
Source
Signal
ac
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
1 kΩ
on
Sampling Capacitor (C ):
1.25 pF
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
50 Ω
s
Figure 6−34. ADC Analog Input Impedance Model
6.29.4 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC
Conversion
Figure 6−35. ADC Power-Up Control Bit Timing
†
Table 6−40. ADC Power-Up Delays
MIN
7
TYP MAX
UNIT
Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register
(PWDNBG and PWDNREF) are to be set to 1 before the PWDNADC bit is enabled.
t
8
10
ms
d(BGR)
20
50
µs
Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register
(PWDNADC) is to be set to 1 before any ADC conversions are initiated.
t
d(PWD)
1
ms
†
These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions
are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at the same time.
130
SPRS257
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Electrical Specifications
6.29.5 Detailed Description
6.29.5.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP
is set to 2.0 V and ADCVREFM is set to 1.0 V.
6.29.5.2 Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a
time. These inputs are software-selectable.
6.29.5.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
6.29.5.4 Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected
channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
131
June 2004
SPRS257
Electrical Specifications
Sample n+2
Sample n+1
Sample n
Analog Input on
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger
from EV or Other
Sources
t
SH
Figure 6−36. Sequential Sampling Mode (Single-Channel) Timing
Table 6−41. Sequential Sampling Mode Timing
AT 25-MHz ADC
SAMPLE n
SAMPLE n + 1
CLOCK,
= 40 ns
REMARKS
t
c(ADCCLK)
Delay time from event
trigger to sampling
t
t
2.5t
c(ADCCLK)
d(SH)
Sample/Hold width/
Acquisition width
(1 + Acqps) *
Acqps value = 0-15
ADCTRL1[8:11]
40 ns with Acqps = 0
160 ns
SH
t
c(ADCCLK)
Delay time for first result
to appear in the Result
register
t
4t
c(ADCCLK)
d(schx_n)
Delay time for successive
results to appear in the
Result register
(2 + Acqps) *
t
80 ns
d(schx_n+1)
t
c(ADCCLK)
132
SPRS257
June 2004
Electrical Specifications
6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0
to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software
trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.
The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The
Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide
(maximum).
NOTE: In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ...,
A7/B7, and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger
from EV or Other
Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 6−37. Simultaneous Sampling Mode Timing
Table 6−42. Simultaneous Sampling Mode Timing
AT 25-MHz ADC
SAMPLE n
SAMPLE n + 1
CLOCK,
= 40 ns
REMARKS
t
c(ADCCLK)
Delay time from event
trigger to sampling
t
t
2.5t
c(ADCCLK)
d(SH)
Sample/Hold width/
Acquisition Width
(1 + Acqps) *
Acqps value = 0-15
ADCTRL1[8:11]
40 ns with Acqps = 0
160 ns
SH
t
c(ADCCLK)
Delay time for first result
to appear in Result
register
t
t
t
t
4t
d(schA0_n)
c(ADCCLK)
c(ADCCLK)
Delay time for first result
to appear in Result
register
5t
200 ns
120 ns
120 ns
d(schB0_n)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
d(schA0_n+1)
d(schB0_n+1)
t
c(ADCCLK)
Delay time for
successive results to
appear in Result register
(3 + Acqps) *
t
c(ADCCLK)
133
June 2004
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Electrical Specifications
6.29.8 Definitions of Specifications and Terminology
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined
as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code
transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
)
SINAD * 1.76
N +
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
134
SPRS257
June 2004
Electrical Specifications
6.30 Multichannel Buffered Serial Port (McBSP) Timing
6.30.1 McBSP Transmit and Receive Timing
†‡
Table 6−43. McBSP Timing Requirements
NO.
MIN MAX UNIT
1
kHz
MHz
ns
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
§
20
50
1
ms
ns
M11
M12
M13
M14
t
t
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
c(CKRX)
w(CKRX)
r(CKRX)
f(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P-7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15
M16
M17
M18
M19
M20
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
0
6
18
2
0
Hold time, DR valid after CLKR low
6
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
†
‡
§
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
CLKSRG
(1 ) CLKGDV)
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
.
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed
limit (20 MHz).
135
June 2004
SPRS257
Electrical Specifications
†‡
Table 6−44. McBSP Switching Characteristics
PARAMETER
NO.
MIN
MAX UNIT
M1
M2
M3
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
c(CKRX)
§
§
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D-5
D+5
C+5
ns
ns
ns
ns
w(CKRXH)
w(CKRXL)
§
§
C-5
0
3
0
3
4
27
4
M4
M5
M6
t
t
t
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
d(CKRH-FRV)
d(CKXH-FXV)
dis(CKXH-DXHZ)
ns
ns
27
8
Disable time, CLKX high to DX high impedance
following last data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
DXENA = 0
M7
t
ns
Delay time, CLKX high to DX valid
d(CKXH-DXV)
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
14
P + 8
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
P + 14
0
6
Enable time, CLKX high to DX driven
M8
M9
t
t
t
ns
ns
ns
en(CKXH-DX)
d(FXH-DXV)
en(FXH-DX)
P
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
P + 6
8
14
Delay time, FSX high to DX valid
FSX ext
FSX int
P + 8
P + 14
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
FSX ext
FSX int
0
6
Enable time, FSX high to DX driven
FSX ext
FSX int
M10
P
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode
FSX ext
P + 6
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
2P = 1/CLKG in ns.
C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
‡
§
136
SPRS257
June 2004
Electrical Specifications
M1, M11
M2, M12
M3, M12
M13
CLKR
FSR (int)
FSR (ext)
M4
M4
M14
M15
M17
M16
M18
DR
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(RDATDLY=00b)
M18
DR
Bit (n−1)
(n−3)
M18
(RDATDLY=01b)
M17
DR
Bit (n−1)
(n−2)
(RDATDLY=10b)
Figure 6−38. McBSP Receive Timing
M1, M11
M2, M12
M13
M14
M3, M12
CLKX
FSX (int)
FSX (ext)
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
DX
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
Bit (n−1)
(n−2)
Bit 0
M6
(XDATDLY=01b)
M7
M8
DX
Bit 0
Bit (n−1)
(XDATDLY=10b)
Figure 6−39. McBSP Transmit Timing
137
June 2004
SPRS257
Electrical Specifications
6.30.2 McBSP as SPI Master or Slave Timing
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M30
M31
M32
M33
t
t
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
P-10
P-10
8P-10
8P-10
8P+10
16P
ns
ns
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
su(BFXL-CKXH)
c(CKX)
2P
†
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN MAX
MIN MAX
M24
M25
t
t
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
2P
P
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
Disable time, DX high impedance following
last data bit from FSX high
M28
t
6
6
6P + 6
4P + 6
ns
ns
dis(FXH-DXHZ)
M29
t
Delay time, FSX low to DX valid
d(FXL-DXV)
†
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
138
SPRS257
June 2004
Electrical Specifications
†
Table 6−47. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M39
M40
M41
M42
t
t
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
P-10
P-10
8P-10
8P-10
16P+10
16P
ns
ns
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
su(FXL-CKXH)
c(CKX)
2P
†
Table 6−48. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN MAX
MIN
MAX
M34
M35
t
t
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
P
ns
ns
h(CKXL-FXL)
2P
d(FXL-CKXH)
Disable time, DX high impedance following last data bit
from CLKX low
M37
t
P + 6
6
7P+6
ns
ns
dis(CKXL-DXHZ)
M38
t
Delay time, FSX low to DX valid
4P + 6
d(FXL-DXV)
†
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M39
M40
(n-2)
DR
Bit 0
(n-3)
(n-4)
Figure 6−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
139
June 2004
SPRS257
Electrical Specifications
†
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
NO.
UNIT
MIN
P-10
P-10
MAX
MIN
8P-10
8P-10
8P+10
16P
MAX
M49
M50
M51
M52
t
t
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
ns
ns
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
su(FXL-CKXL)
c(CKX)
2P
†
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
2P
P
MAX
MIN MAX
M43
M44
t
t
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
Disable time, DX high impedance following last data bit
from FSX high
M47
M48
t
t
6
6
6P + 6
4P + 6
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M52
MSB
M51
M48
LSB
CLKX
FSX
M43
M44
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
M49
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
140
SPRS257
June 2004
Electrical Specifications
†
Table 6−51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
NO.
UNIT
MIN
P - 10
P - 10
MAX
MIN MAX
M58
M59
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
8P - 10
ns
ns
su(DRV-CKXL)
8P - 10
h(CKXL-DRV)
16P +
10
M60
M61
t
t
Setup time, FSX low before CLKX low
Cycle time, CLKX
ns
su(FXL-CKXL)
c(CKX)
2P
16P
ns
†
Table 6−52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
‡
MASTER
SLAVE
NO.
PARAMETER
UNIT
MIN
P
MAX
MIN MAX
M53
M54
t
t
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
h(CKXH-FXL)
2P
d(FXL-CKXL)
Disable time, DX high impedance following last data bit
from CLKX high
M56
t
P+6
6
7P + 6
4P + 6
ns
ns
dis(CKXH-DXHZ)
M57
t
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
C
D
=
=
CLKX low pulse width = P
CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
FSX
DX
M53
M55
M56
M57
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6−43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
141
June 2004
SPRS257
Electrical Specifications
7
Migration From F281x Devices
Table 6−53 shows the differences between F281x and R281x features. F281x stands for TMS320F2810,
TMS320F2811, and TMS320F2812 devices. R281x stands for TMS320R2811 and TMS320R2812 devices.
Table 6−53. Feature Comparison Between F281x and R281x Devices
FEATURES
R2811
F2811
R2812
F2812
R281X MIGRATION CONSIDERATIONS
Instruction Cycle (at 150 MHz)
6.67 ns
6.67 ns
6.67 ns
6.67 ns
R281x SARAM execution is single cycle,
zero−wait-state at 150 MHz.
Single−Access RAM (SARAM)
(16−bit word)
20K
18K
20K
18K
Additional 2K words of SARAM −L2/L3
blocks −See section 3.2.7.
Code Security feature
Disabled
Selectable
Disabled
Selectable
Code secuirty in R281x affects L0/L1
SARAM. However, CSM password
locations are preset as 0xFFFF to facilitate
easy unsecuring. See Section 3.2.9.
On−chip Non−Voltaile memory
No
Yes
No
Yes
F281x Flash/OTP space are reserved in
R281x devices.
Boot ROM
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Same Boot ROM code as F281x devices.
Not available on R281x
Flash/OTP Boot ROM
SPI−EEPROM Boot
H0 SARAM Boot
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SCI, Parallel I/O Boot
External Memory Interface
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Event Managers A and B
(EVA and EVB)
EVA, EVB
EVA, EVB
EVA, EVB
EVA, EVB
General−Purpose (GP) Timers
Compare (CMP)/PWM
Capture (CAP)/QEP Channels
Watchdog Timer
4
4
4
4
16
16
16
16
6/2
Yes
Yes
6/2
Yes
Yes
6/2
Yes
Yes
6/2
Yes
Yes
12−Bit ADC
Internal reference trimmed for gain
accuracy. Supports external reference
mode as in F281x devices. See Section 4.3.
Channels
16
16
16
16
32−Bit CPU Timers
SPI
3
Yes
3
Yes
3
Yes
3
Yes
SCIA, SCIB
CAN
SCIA, SCIB
Yes
SCIA, SCIB
Yes
SCIA, SCIB
Yes
SCIA, SCIB
Yes
McBSP
Yes
Yes
Yes
Yes
Digital I/O Pins (Shared)
External Interrupts
56
56
56
56
3
3
3
3
Supply Voltage − 1.9 V, 3.3 V,
150 MHz
150 MHz
150 MHz
150 MHz
(5%)
142
SPRS257
June 2004
Electrical Specifications
Table 6−53. Feature Comparison Between F281x and R281x Devices (Continued)
FEATURES
R2811
F2811
R2812
F2812
R281X MIGRATION CONSIDERATIONS
Supply Voltage − 1.8 V, 3.3 V,
135 MHz
135 MHz
135 MHz
135 MHz
(5%)
Power sequencing
Packaging
Optional
Required
Optional
Required
Power sequencing is optional in R281x
devices. See Section 6.7.
128−pin
128−pin
179−ball/
176−pin
179−ball/
176−pin
PBK
PBK
GHH, ZHH,
PGF
GHH, ZHH, Lead−free options in all packages
PGF
Temperature Options
A: −40°C to 85°C
S/Q: −40°C to 125°C
Product Status
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TMX
TMS
TMX
TMS
Reference Guides
F281x
version
F281x
version
F281x
version
F281x
version
See the F281x −CPU and peripheral
reference guides listed in Section 5.2 and in
the TMS320F28x Peripherals Reference
Guide (literature number SPRU566).
Code Development
CCS
2.2x or
above
2.2x or
above
2.2x or
above
2.2x or
above
eZdsp
USB version XDS510PP+
Emulators
All versions
Rev.1.0
All versions
Rev.1.0
All versions
All versions XDS510/XDS510PP+, XDS510USB or
other compatible emulators
C281x C/C++ Header Files
and Peripheral Examples
(literature number SPRC097)
Rev.1.0
Rev.1.0
Use DSP281x C/C++−header files rev 1.0
or later. Disable or remove sections that are
not applicable to R281x, such as Flash and
OTP.
143
June 2004
SPRS257
Mechanical Data
8
Mechanical Data
8.1
Ball Grid Array (BGA)
GHH (S-PBGA-N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
10,40 TYP
0,40
SQ
0,80
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4173504−3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
D. This package is not lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−1. TMS320R2812 179-Ball GHH MicroStar BGA
Table 7−1. Thermal Resistance Characteristics for 179-GHH
PARAMETER
Psi
179-GHH PACKAGE
UNIT
0.658
°C/W
JT
Θ
JA
Θ
JC
42.57
16.08
°C/W
°C/W
MicroStar BGA is a trademark of Texas Instruments.
144
SPRS257
June 2004
Mechanical Data
8.2
Plastic Ball Grid Array
ZHH (S−PBGA−N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
SQ
10,40 TYP
0,40
0,80
P
N
M
L
K
J
0,80
H
G
F
E
D
C
B
A
0,40
A1 Corner
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4204739/A 10/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGAt configuration.
D. This package is lead-free and needs a minimum reflow temperature of 250°C but not exceeding 260°C.
Figure 7−2. TMS320R2812 179-Ball ZHH MicroStar BGA
Table 7−2. Thermal Resistance Characteristics for 179-ZHH
PARAMETER
Psi
179-ZHH PACKAGE
UNIT
0.658
°C/W
JT
Θ
JA
Θ
JC
42.57
16.08
°C/W
°C/W
MicroStar BGA is a trademark of Texas Instruments.
145
June 2004
SPRS257
Mechanical Data
8.3
Low-Profile Quad Flatpacks (LQFPs)
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
0,17
M
0,08
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°−ꢀ7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This package is lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−3. TMS320R2812 176-Pin PGF LQFP
Table 7−3. Thermal Resistance Characteristics for 176-PGF
PARAMETER
Psi
176-PGF PACKAGE
UNIT
0.247
°C/W
JT
Θ
JA
Θ
JC
41.88
9.73
°C/W
°C/W
146
SPRS257
June 2004
Mechanical Data
PBK (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,13
0,40
96
M
0,07
64
65
97
128
33
0,13 NOM
1
32
Gage Plane
12,40 TYP
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°−ꢀ7°
15,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040279-3/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This package is lead-free and needs a minimum reflow temperature of 220°C but not exceeding 235°C.
Figure 7−4. TMS320R2811 128-Pin PBK LQFP
Table 7−4. Thermal Resistance Characteristics for 128-PBK
PARAMETER
Psi
128-PBK PACKAGE
UNIT
0.271
°C/W
JT
Θ
JA
Θ
JC
41.65
10.76
°C/W
°C/W
147
June 2004
SPRS257
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