TNETA1500APGE [TI]
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER;
| 型号： | TNETA1500APGE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER ATM 异步传输模式 |
| 文件： | 总29页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
Single-Chip Receiver/Transmitter for
Generates Alarms for:
Transporting 53-Byte Asynchronous
Transport Mode (ATM) Cells Via
STS-3c/STM-1 Frame (155.52 Mbit/s)
– Loss of Incoming Serial Signal (LOS)
– Out of Frame (OOF)
– Loss of Frame (LOF)
– B1-Byte Parity Error (B1ERR)
– Loss of ATM Cell Alignment (LOCA)
– Line Far-End Receive Failure (LFERF)
– Receive Loss of Pointer (LOP)
– Line Alarm Indication Signal (LAIS)
On-Chip Analog Phase-Locked Loop
(APLL) Provides:
– Recovery of Receive Clock From
Incoming Serial-Data Stream
– Transmit Clock Generation From
External 19.44-MHz Clock Source
Meets ATM Forum ATM User-Network
Interface Specification Requirement
Inserts and Extracts ATM Cells Into/From
SONET/SDH STS-3c/STM-1 SPE
Package Options Include 144-Pin Plastic
Quad Flat (PCM) and 144-Pin Thin Quad
Flat (PGE) Packages
Detects Multiple-Bit Errors and Corrects
Single-Bit Errors in the 5-Byte ATM
Headers of Incoming ATM Cells
description
The synchronous optical network (SONET)/synchronous digital hierarchy (SDH) asynchronous transport mode
(ATM) line-interface receiver/transmitter provides a single-chip implementation for transporting ATM cells over
the SONET/SDH network at the STS-3c/STM-1 rate of 155.52 Mbits/s. This device provides all the functionality
required to insert and extract 53-byte ATM cells into/from an STS-3c/STM-1 synchronous payload envelope
(SPE), including clock recovery and clock generation using analog phase-locked loops (APLL).
On the receive side, the TNETA1500A accepts 155.52-Mbit/s serial data, recovers the embedded clock signal,
performs SONET/SDH frame alignment and serial-to-parallel conversion, identifies the SONET/SDH payload,
and establishes the ATM-cell boundaries. The ATM cells are extracted from the payload, descrambled, and
passed to the receive output FIFO for output to the next device (i.e., a reassembly device). On the transmit side,
complete 53-byte ATM cells are placed in the transmit input FIFO, scrambled, and inserted into an
STS-3c/STM-1 SPE. The SONET/SDH frame is scrambled and converted to a serial-data stream for output.
An APLL is used to generate the 155.52-MHz output clock from a low-speed 19.44-MHz oscillator, eliminating
the need for a high-speed 155.52-MHz oscillator.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
PCM OR PGE PACKAGE
(TOP VIEW)
35
30
25
20
15
10
5
1
CRCAP
AGND
AGND
GND
V
CC
RESET
AV
CC
40
45
50
55
60
65
TEST4
TEST3
TEST2
FLB
140
RSDT
RSDC
AV
CC
AGND
AGND
TLB
CKGENBP
CKRECBP
CLKLOOP
LOF
135
130
125
120
115
110
CGCAP
AV
CC
TXREFCK
TXHCKT
GND
V
TXHCKC
TSDT
CC
8KHZREF
OOF
TSDC
TSCT
LOS
GND
TSCC
AV
V
CC
CC
AGND
SDHENABLE
OE
B1ERR
LOCA
LFERF
LAIS
LOP
RCKI
TEST0
TEST1
TXAF
RRE
GND
TXCELL
RXFE
RXCELL
LOSRD
GND
TWE
TCKI
GND
V
V
CC
CC
TD0
TD1
TD2
TD3
GND
NC
NC
NC
70
NC
GND
75
80
85
90
95
100
105
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
functional block diagram
CRCAP
Receive Operation
330-pF Capacitor
Connected Externally
LOP
LFERF
FLB
LOSRD
LAIS
LOCA
B1ERR
8KHZREF LOF LOS OOF
RSDT
8
RD0–RD7
RCKI
Descrambling,
B1-Parity,
Alarm
ATM-Cell
Extraction
and
RSDC
Framing and
Serial-to-Parallel
Conversion
Clock
Recovery
CKRECBP
Demux
RXCELL
RRE
RXFE
RSCT
RSCC
Generation
Descrambling
CLKLOOP
8
8
D0–D7
A0–A7
OE
READY
RD/WR
INTR
Controller
Interface
RESET
SEL
FLAGT
FLAGC
8
TSDT
TD0–TD7
Scrambling
ATM-Cell
Scrambling
and
TCKI
TXCELL
TWE
TSDC
TSCT
Parallel-to-Serial
Conversion
and
B1-Parity
Generation
Mux
Cell Insertion
TSCC
TXAF
TLB
Transmit Operation
SDHENABLE
CKGENBP
TXREFCK
TXHCKT
CGCAP
Clock
Generation
0.01-µF Capacitor
Connected Externally
TXHCKC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
detailed description
transmit operation
The transmit-cell interface consists of the byte-wide input data (TD0–TD7), input clock (TCKI), start of ATM-cell
input (TXCELL), transmit write-enable input (TWE), and transmit-input FIFO almost-full output (TXAF). Input
data is clocked into the TNETA1500A on low-to-high transitions of TCKI when TWE is low. The transmit-input
FIFO almost-full flag (TXAF) goes active when the transmit FIFO is within five bytes of filling up (the FIFO holds
three complete ATM cells).
The 48-byte information field of the ATM cell is scrambled using a self-synchronizing scrambler polynomial of
43
x
+ 1 to improve the efficiency of the cell-delineation procedure. At startup, the scrambler is initialized to an
all-1s state. The 5-byte ATM header is not scrambled at this step. TXCELL identifies the first byte of the ATM
cell and disables the scrambler. The input data is stored in the transmit-input FIFO and multiplexed into the
SONET/SDHpayload after all 53 bytes have been received. If the FIFO does not contain 53 bytes of information
at the start of a cell-insertion cycle, an idle or unassigned cell is sent, dependent on the status of the control
registers. An idle cell is defined as an ATM cell with the 5-byte header set to 00 00 00 01 52 (hex) and the 48-byte
payload set to 6A (hex). An unassigned cell is defined as an ATM cell with the 5-byte header set to
00 00 00 00 55 (hex) and the 48-byte payload set to 6A (hex). See controller-interface operation for more
information on the operation of the control registers.
The transmit section calculates the header-error-check (HEC) byte in the ATM header by default. This implies
that the fifth byte of the ATM cell that is input through the transmit-cell interface is ignored. The HEC byte is
calculated in accordance with the ANSI T1.624-1993 and CCITT recommendation I.432. This feature can be
disabled by setting a bit in the control register.
The transmit operation can be programmed to send either a SONET STS-3c frame or an SDH STM-1 frame.
WhenSDHENABLEislow, aSONETSTS-3cframeistransmitted. WhenSDHENABLEishigh, anSTM-1frame
is transmitted. For both the STS-3c and STM-1 frames, the location of the J1 byte in the path overhead is fixed;
the J1 byte always comes after the third C1 byte of the transport overhead (TOH). This is known as location 522.
The data-communication channels (D1 through D12 bytes) in the TOH are set to a hex value of FF 00 00. The
values for the transport- and path-overhead bytes for both an STS-3c frame and an STM-1 frame are given in
Table 1.
The parity bytes B1, B2 (three bytes), and B3 are calculated as follows:
B1 — B1 is a bit-interleaved parity-8 (BIP-8) code using even parity. B1 is calculated over all bits of the
previous STS-3c frame after scrambling. The calculated value of B1 is placed in the STS-3c frame before
the frame is scrambled.
B2 — For an STS-3c frame, the three B2 bytes combine to form a BIP-24 code; however, each B2 byte is
calculated as if the frame is composed of three individual STS-1s. Each B2 is calculated over all bits of the
line overhead and STS-1 envelope capacity of the previous STS-1 frame before scrambling, using even
parity. The computed value is placed in the appropriate B2 byte location before scrambling. The line
overhead consists of the six rows of TOH bytes, beginning with the first H1 byte and ending before the row
containing the first A1 byte (see Table 1).
B3 — For an STS-3c frame, the B3 byte is calculated over all bits of the previous STS-3c SPE before
scrambling. B3 is a BIP-8 code, using even parity. The computed value is placed in the B3 location
before scrambling.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
transmit operation (continued)
Table 1. Transmit Transport-Overhead and Path-Overhead Bytes
SONET FRAME
VALUE WHEN
SDH FRAME
VALUE WHEN
OVERHEAD BYTE
SDHENABLE = LOW
1111 0110 (F6h)
0010 1000 (28h)
01 02 03 (h)
SDHENABLE = HIGH
1111 0110 (F6h)
0010 1000 (28h)
01 00 00 (h)
A1
A2
C1 bytes
B1
B2
Calculated
Calculated
B3
First H1
0110 0010 (62h)
1001 0011 (93h)
0000 1010 (0Ah)
1111 1111 (FFh)
0000 0000 (00h)
0110 1010 (6Ah)
1001 1011 (9Bh)
0000 1010 (0Ah)
1111 1111 (FFh)
0000 0000 (00h)
Second H1 (H1*)
Third H1 (H1*)
First H2
Second H2 (H2*)
Third H2 (H2*)
Three H3 bytes
Normal operation: 0000 0000
Line FERF: 0000 0110
Normal operation: 0000 0000
Line FERF: 0000 0110
First K2
Third Z2
B2 error count:
0000 0000–0001 1000
B2 error count:
0000 0000–0001 1000
J1
0000 0000
0001 0011
0000 0000
0001 0011
C2
B3 error count:
0000–1000
Path FERF:
1001
B3 error count:
0000–1000
Path FERF:
1001
Bits 1–4
G1
Bit 5
Path RDI: 1
Path RDI: 1
Bits 6–8
H4
000
000
0000 0000
0000 0000
7
6
Before transmission, the STS-3c frame is scrambled using a generating polynomial of x + x + 1. The A1, A2,
and C1 overhead bytes are not scrambled, and the scrambler is reset to 1111111 on the most-significant bit of
the byte immediately following the third C1 byte. The scrambler runs continuously throughout the complete
STS-3c frame.
After the STS-3c frame has been scrambled, the bytes are converted to a serial-data stream using a
parallel-to-serial converter. An APLL is used to generate the 155.52-MHz output clock from a 19.44-MHz
oscillator connected to TXREFCK. Two other sources can be used for the 155.52-MHz clock. CKGENBP and
CLKLOOP are used to select either a 155.52-MHz external clock source or the clock recovered from the
incoming serial-data stream APLL (loop timing). The functions for selecting the transmit-clock source are shown
in Table 2. The clock-generation APLL requires that an external 0.01-µF capacitor be connected from CGCAP
to ground.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
transmit operation (continued)
Table 2. Functions for CKGENBP and CLKLOOP
CKGENBP
CLKLOOP
CLOCK SOURCE
TXREFCK (19.44 MHz)
L
L
L
H
Receive recovered clock (loop timing)
TXHCKT, TXHCKC (155.52 MHz)
H
H or L
Both true and complementary pseudo-emitter-coupled logic (PECL)-compatible serial data and clock outputs
are available. The serial data is output on the rising edge of the true clock signal (falling edge of the complement
clock). The outputs are designed to drive a 50-Ω line terminated through a 50-Ω resistor to 3 V (or its equivalent).
A terminal-loopback feature also is provided on the device. When the terminal-loopback input is high, the ATM
cells received on the transmit input are looped back to the receive output. The ATM cells received are blocked.
The transmit operation is not affected in this mode and operates as previously described.
receive operation
The receive serial inputs to the TNETA1500A consist of 155.52-Mbit/s true and complementary PECL data and
an optional 155.52-MHz true and complementary PECL clock. The 155.52-MHz clock inputs are needed only
if the clock-recovery-bypass input (CKRECBP) is high, which disables the clock-recovery circuit. This feature
is used typically for test purposes and normally is not used in a system application.
The clock-recovery circuit is used to recover the embedded clock signal from the serial nonreturn-to-zero (NRZ)
data inputs RSDT and RSDC. The clock-recovery circuit consists of a transition detector, an APLL, and a
retiming circuit. The transition detector is used to double the frequency of the incoming serial-data stream. This
is necessary because the NRZ-data stream does not contain a second harmonic, which is necessary to recover
the transmit clock. The APLL consists of a phase-frequency detector, a charge pump/loop filter, and an internal
voltage-controlled oscillator (VCO). The phase-frequency detector compares the output of the transition
detector to the output of the VCO and generates a signal to the charge-pump/loop filter that is used to change
the frequency of the VCO. The frequency of the VCO is adjusted until it matches the frequency of the transition
detector. When this occurs, the APLL is locked to the frequency of the embedded clock signal.
The clock-recovery circuit also contains a circuit that retimes the input serial data to the recovered output clock.
The only external component required for the clock-recovery circuit is a 330-pF capacitor that is connected from
CRCAP to ground. This capacitor is part of the charge-pump/loop-filter circuit.
The clock signal recovered from the incoming serial-data stream also can be used as the transmit clock for the
transmit section. This is known as clock looping. The advantage of using the recovered receive clock as the
transmit clock is that the transmit clock is frequency locked to the same clock source that is used to generate
theincomingdatastream. Ifthisclocksourceprovidesahighlyaccuratelow-parts-per-millionclock, thetransmit
clock also is a very accurate clock. The drawback to using clock looping is that if the receive signal is lost for
any reason, the transmit clock also is lost.
A facility-loopback (FLB) input loops the input data and recovered clock to the transmit output data and clock.
This provides a method of testing the function of the clock-recovery circuit and its jitter performance. It also can
be used for system-loopback testing.
The PECL inputs FLAGT and FLAGC are provided for interfacing to the loss-of-optical-signal outputs on optical
receivers. If the optical signal is lost, the loss-of-optical-carrier bit in the interrupt register is set and the interrupt
output (INTR) becomes active low.
The recovered clock signal and retimed input data are passed from the clock-recovery circuit to the framing
circuit. The framing circuit searches for the SONET framing bytes A1 and A2, where A1 has a set value of F6h
and A2 has a value of 28h. The exact framing pattern for an STS-3c frame is A1A1A1A2A2A2
(F6F6F6282828h). These bytes are not scrambled by the transmitter.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
receive operation (continued)
The TNETA1500A provides loss-of-signal (LOS), out-of-frame (OOF), and loss-of-frame (LOF) alarms in
accordance with BellCore specification TR-NWT-000253, Issue 2, December 1991. The LOS alarm goes active
when no transitions are detected on the receive serial data for 3.3 µs. The LOS alarm goes inactive when two
consecutive framing patterns have been detected, and during the intervening time (one frame time), no
transitionless 3.3-µs period is detected. The OOF alarm goes active when four consecutive-errored framing
patterns are received. The OOF alarm clears when two successive error-free framing patterns are received.
If the OOF condition fails to clear within 3 ms, the LOF alarm goes active. The LOF alarm goes inactive when
eight consecutive error-free SONET frames are identified. The LOS, OOF, and LOF alarms are indicated by
external signals and by setting a bit in the interrupt registers. This causes INTR of the controller interface to go
active low, signaling an interrupt.
After the SONET frame is established and the serial data converted to byte-wide data, the B1 BIP-8 parity is
calculated over the scrambled SONET frame. This value is compared with the value of B1 contained in the next
(n + 1) frame. The value of B1 calculated over the previous frame (n – 1) is compared to the value B1 in this
frame(framen). Ifthetwovaluesdonotmatch, B1ERRgoesactive, denotingthataB1parityerrorhasoccurred.
In addition, the B1 parity-error bit in the interrupt register is set and INTR goes active low.
Next, the SONET frame is unscrambled (except for the A1, A2, and C1 bytes, which were not scrambled by the
transmitter). The B2 BIP-24 value is calculated over all the bits of the line overhead and the STS-3c envelope
capacity and compared to the value contained in the next frame. If a B2 parity error occurs, the B2 parity-error
bit in the interrupt register is set and INTR goes active low to notify the controller that a parity error has occurred.
The TNETA1500A monitors the receive K2 byte for line alarm-indication signal (LAIS) and line far-end receive
failure (LFERF) alarms. A LAIS alarm occurs when bits 6–8 of the receive K2 byte are set to a value of 111 for
five consecutive frames. The LAIS alarm goes inactive when bits 6–8 of the receive K2 byte are set to any value
other than 111 for five consecutive frames. The LFERF alarm goes active when bits 6–8 of the receive K2 byte
aresettoavalueof110forfiveconsecutiveframes. TheLFERFalarmgoesinactivewhenbits6–8ofthereceive
K2 byte are set to any value other than 110 for five consecutive frames. Both the LAIS and LFERF alarms are
indicated on an external terminal and by setting a bit in interrupt register 2.
The location of the J1 byte in the SPE is determined from the H1 and H2 bytes in the TOH. The location of the
J1 byte does not change from the previous frame unless the first four bits of H1 are set to 1001 (the new-data
flag) or the pointer value contained in H1 and H2 is different for three consecutive frames. The location of J1
also can be incremented or decremented by a 1-byte position by inverting certain bits in the H1 and H2 byte
pointer. If bits 7, 9, 11, 13, and 15 are inverted, the location of J1 is incremented one time slot. If bits 8, 10, 12,
14, and 16 are inverted, the location of J1 is decremented one time slot. Subsequent pointers contain the
new offset.
The TNETA1500A provides a loss-of-pointer (LOP) alarm to indicate that either an invalid pointer was detected
in the incoming H1 and H2 bytes or a new-data flag (NDF) (set to a value of 1001 — the first four bits of H1)
was found in eight consecutive frames. The LOP alarm goes inactive when a valid pointer with the NDF set to
0110 is detected in three consecutive frames. The device also provides a path-AIS alarm to indicate that a
path-AIS condition has been detected in the H1 and H2 bytes. A path-AIS condition is detected as an all-1s
condition in bytes H1 and H2 for three consecutive frames. The path-AIS alarm goes inactive when a valid
pointer, withtheNDFsetto0110, isdetectedforthreeconsecutiveframes. TheLOPalarmisnotsetifapath-AIS
condition is detected. The LOP alarm is indicated by an external signal and by the interrupt register. The
path-AIS alarm is indicated only by the interrupt register.
The B3 BIP-8 byte is calculated over the contents of the STS-3c SPE, which begins with the J1 byte. The value
calculated for B3 is compared with the value found in the next frame. If a B3 parity error occurs, the B3
parity-error bit is set in the interrupt register and INTR goes active low to notify the controller.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
receive operation (continued)
The TNETA1500A monitors the receive G1 byte for a path far-end receive failure (FERF) and path
remote-defect indication (RDI) alarms. A path FERF occurs when bits 1–4 of the G1 byte are set to a value of
1001. The path FERF alarm goes inactive when bits 1–4 of the G1 byte are set to a non-1001 value. A path RDI
occurs when bit 5 of the G1 byte is set to a value of 1 for ten consecutive frames. The path RDI alarm goes
inactive when bit 5 of the G1 byte is set to a value of 0 for ten consecutive frames. Both the path FERF and path
RDI alarms are indicated through interrupt register 3.
Once the STS-3c SPE is located, the ATM cells are identified and extracted. Cell delineation is accomplished
by computing the HEC for the first four bytes after the J1 byte and comparing the calculated value with the fifth
byte. If the values do not match, the process advances one byte and then repeats. This process continues until
a match between the calculated value and the fifth byte occurs. Cell alignment is assumed to have occurred
when seven consecutive matches occur. Until cell alignment occurs, the loss-of-cell-alignment (LOCA) alarm
remains active. Once cell alignment is established, it is monitored constantly for a LOCA condition. A LOCA
condition is declared (LOCA goes active) when seven consecutive cells occur with header errors. At this point,
the hunting process starts over.
The receive side detects multiple-bit errors and corrects single-bit errors occurring in the 5-byte ATM header
of incoming ATM cells by using the HEC byte. This feature is deactivated by setting a bit in control register 1
(see Table 6). The ATM cells with multiple-bit header errors are dropped, unless a bit is set in control register 1
(see Table 6) to disable the dropping of cells with uncorrectable errors. An 8-bit saturating counter (accessible
through the controller interface) counts the number of ATM cells with multiple-bit ATM-header errors.
After the ATM cells are extracted, they are descrambled. The 48-byte payload in the ATM cell is scrambled at
43
the transmitter using an x + 1 polynomial to further distinguish the payload from the header bytes and improve
43
the efficiency of the cell-delineation algorithm. The x + 1 polynomial also is used to descramble the payload
so that it can be sent to the next device.
The TNETA1500A has the capability of dropping idle and unassigned cells from the receive-data stream. An
idle cell is defined as a cell with a 5-byte ATM header set to a value of 00 00 00 01 52 (hex) and an unassigned
cell is defined as a cell with a 5-byte header of 00 00 00 00 55 (hex). In both cases, the payload is ignored. The
dropping of idle and/or unassigned cells can be disabled through control register 1 (CR1) in the
controller interface.
After descrambling, the ATM cell is passed to the output buffer, which operates as a FIFO. The receive-cell
interface consists of the output data (RD0–RD7), receive-clock input (RCKI), receive-read-enable (RRE) input,
receive-FIFO-empty (RXFE) output, beginning-of-ATM-cell indicator (RXCELL), and loss-of-receive-data
(LOSRD)alarm. Data is sent out from the device on the rising edge of RCKI when RRE is low. The LOSRD alarm
goes active when the output FIFO overflows. In this case, the last cell placed into the FIFO is overwritten. The
output FIFO holds three complete ATM cells.
Cumulative counts of receive B1, B2, and B3 errors are provided by registers accessible through the controller
interface. These registers maintain running totals of B1, B2, and B3 block errors and coding violations. The
block-error counters maintain a count of the number of frames that are received with B1, B2, and B3 errors. The
coding-violation counters count the exact number of B1, B2, and B3 BIP errors that occur. It is possible for a
single frame to contain 8 B1, 24 B2, and 8 B3 BIP errors. When any of the block-error or coding-violation
counters reach maximum count, a bit is set in the interrupt registers and an interrupt is generated. These
countersarerollovercountersthatrollovertozeroafterthemaximumcountoccursandaninterruptisgenerated
(see the controller-interface operation section for additional information).
When the receive side enters a LOCA state, a path RDI may need to be sent out the transmit side through the
outgoing G1 byte. A path-RDI alarm is declared when a LOCA state is persistent for an amount of time (also
known as soak time) that has not yet been specified by any industry standards. To provide maximum flexibility
with regard to this unspecified soak time, an 8-bit counter is provided through the controller interface that allows
the user to program the amount of soak time for a path-RDI alarm in increments of 125 µs. This counter is preset
(when a device reset occurs) to a value of 4 ms, which is the anticipated soak time for a path-RDI alarm.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
controller-interface operation
The controller interface provides access to the internal memory locations that contain the control registers,
interrupt registers, interrupt-mask registers, and the ID register. Table 3 shows a memory map of the locations
of the various registers in the TNETA1500A.
Table 3. TNETA1500A Register-Memory Map
ADDRESS
(HEX VALUE)
ADDRESS
(HEX VALUE)
REGISTER
REGISTER
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
Interrupt register 1
Interrupt register 2
Interrupt register 3
ID register
0D
0E
0F
10
11
B1 block-error counter
Not implemented
B2 block-error counter
Not implemented
Not implemented
B3 block-error counter
Control register 1
12
13
14
15
16
17
18
>18
B1 coding-violation counter (LSB)
B1 coding-violation counter (MSB)
B2 coding-violation counter (LSB)
B2 coding-violation counter
B2 coding-violation counter (MSB)
B3 coding-violation counter (LSB)
B3 coding-violation counter (MSB)
Not implemented
Control register 2
Interrupt-mask register 1
Interrupt-mask register 2
Interrupt-mask register 3
Multierrored cell counter
Path-RDI soak counter
Not implemented
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
interrupt registers
The interrupt registers located at hex addresses 00, 01, and 02 contain information on the condition of the
receive-data stream that causes INTR to become active low. The coding for the interrupt registers is given in
Table 4.
Table 4. Interrupt-Register Coding
CAUSE OF
IR1 CODING
IR2 CODING
IR3 CODING
INTERRUPT
(ADDRESS 00)
(ADDRESS 01)
(ADDRESS 02)
B1 parity error
XXXX XXX1
—
—
B2 parity error
XXXX XX1X
—
—
B3 parity error
XXXX X1XX
—
—
Loss of cell alignment
Loss of incoming signal
Out of frame
XXXX 1XXX
—
—
XXX1 XXXX
—
—
XX1X XXXX
—
—
—
Loss of frame
X1XX XXXX
—
Loss of optical carrier
Line AIS
1XXX XXXX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XXXX XXX1
XXXX XX1X
XXXX X1XX
XXXX 1XXX
XXX1 XXXX
XX1X XXXX
X1XX XXXX
1XXX XXXX
—
—
Line FERF
—
Loss of receive data
Loss of pointer
Path AIS
—
—
—
B1 block-error overflow
B2 block-error overflow
B3 block-error overflow
B1 CV overflow
B2 CV overflow
B3 CV overflow
Path RDI
—
—
—
XXXX XXX1
XXXX XX1X
XXXX X1XX
XXXX 1XXX
XXX1 XXXX
—
—
—
Path FERF
—
The alarm conditions or errors set bits in the interrupt register that cause INTR to go active low. All of these
conditional actions are associated with the receive-data stream and are described in the following.
LOS, OOF, LOF, LAIS, LOP, LFERF, LOCA, and LOSRD
These alarm conditions cause an external signal to go active and set a bit in one of the interrupt registers (see
Terminal Functions tables for description of the individual alarms). The status of the bit in the interrupt register
for these alarms mirrors the status of the external signal. For example, as long as an LOF condition exists, both
LOF and the LOF bit in IR1 (the value for LOF is x1xx xxxx) are set. When the logic in the TNETA1500A detects
that the LOF condition has cleared, the external output and the status bit in the interrupt registers are cleared.
A change in the status bit in the interrupt registers for these alarms causes INTR to go active low. When the
status bit makes a low-to-high transition, INTR goes active low. INTR also goes active low when the status bit
makes a high-to-low transition. Reading the interrupt register does not clear the status bit for these particular
alarms. However, INTR goes inactive high on a read of any of the interrupt registers.
10
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SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
loss-of-optical carrier, path AIS, path RDI
These alarm conditions cause a status bit in one of the interrupt registers to go active. When the alarm condition
exists, the status bit remains set. When the logic in the TNETA1500A detects that the alarm condition has
cleared, the status bit is cleared. A change in the status bit in the interrupt registers for these alarms causes
INTR to go active low. When the status bit makes a low-to-high transition, INTR goes active low. INTR also goes
active low when the status bit makes a high-to-low transition. Reading the interrupt register does not clear the
statusbitfortheseparticularalarms. However, INTRgoesinactivehighonareadofanyoftheinterruptregisters.
B1/B2/B3 parity error, B1/B2/B3 block error overflow, B1/B2/B3 CV overflow
The status bits for these errors indicate that the specified error condition has occurred. The status bits in the
interrupt registers for these conditions are set when the error conditions occur and remain set until the interrupt
register is read. If a B1, B2, or B3 parity error is detected on an incoming frame, the corresponding status bit
is set in the interrupt register, INTR goes active low, and the status bit remains set until a read of any interrupt
register occurs. Once a read of any interrupt register occurs, the status bit for one of these error conditions is
cleared until the next time that this error condition is detected.
interrupt-mask registers
All of the interrupts in the three interrupt registers can be masked by setting bits in the corresponding
interrupt-mask registers. The coding for the interrupt-mask registers is the same as the coding for the interrupt
registers. To mask only the interrupt associated with a B2 parity error, a value of 0000 0010 is written to
interrupt-mask register 1 (IMR1). To mask all the interrupts in interrupt register 1, a value of 1111 1111 is written
to interrupt-mask register 1. After reset, all three interrupt-mask registers are cleared (set to 00 hex). Table 5
shows the coding for the interrupt-mask registers.
Table 5. Interrupt-Mask Register Coding
IMR1 CODING
(ADDRESS 07)
IMR2 CODING
(ADDRESS 08)
IMR3 CODING
(ADDRESS 09)
INTERRUPT TO BE MASKED
B1 parity error
XXXX XXX1
—
—
B2 parity error
XXXX XX1X
—
—
B3 parity error
XXXX X1XX
—
—
Loss of cell alignment (LOCA)
Loss of incoming signal (LOS)
Out of frame (OOF)
Loss of frame (LOF)
Loss of optical carrier
Line AIS
XXXX 1XXX
—
—
XXX1 XXXX
—
—
XX1X XXXX
—
—
—
X1XX XXXX
—
1XXX XXXX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XXXX XXX1
XXXX XX1X
XXXX X1XX
XXXX 1XXX
XXX1 XXXX
XX1X XXXX
X1XX XXXX
1XXX XXXX
—
—
Line FERF
—
Loss of receive data
Loss of pointer
—
—
—
Path AIS
B1 block-error overflow
B2 block-error overflow
B3 block-error overflow
B1 CV overflow
—
—
—
XXXX XXX1
XXXX XX1X
XXXX X1XX
XXXX 1XXX
XXX1 XXXX
B2 CV overflow
—
B3 CV overflow
—
Path RDI
—
Path FERF
—
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
control registers
The control registers are located at addresses 05 and 06 (hex). The control registers provide a means of
controllingtheoperationofthedevicethroughthecontrollerinterface. Aresetoperation, initiatedeitherbytaking
the RESET signal high or by performing a write operation to the ID register, clears both control registers. The
bit definition for the two control registers is shown in Table 6.
Table 6. Coding for Control Registers
CONTROL
REGISTER 1
(ADDRESS 05)
CONTROL
REGISTER 2
(ADDRESS 06)
ACTION
Disable error correction for receive ATM-cell headers
Disable transmit ATM-cell header HEC-byte generation
Enable terminal loopback (TLB)
XXXX XXX1
XXXX XX1X
XXXX X1XX
XXXX 1XXX
XXX1 XXXX
XX1X XXXX
X1XX XXXX
1XXX XXXX
—
—
—
—
Enable facility (serial) loopback (FLB)
—
Disable the dropping of ATM cells with multiple-bit header errors
Disable the dropping of ATM idle cells from the receive-data stream
Disable the dropping of ATM unassigned cells from the receive-data stream
Transmit STM-1 frame
—
—
—
—
Enable receive-clock looping
XXXX XXX1
XXXX XX1X
Transmit ATM unassigned cells as filler
—
Descriptions of the various control functions of the control registers follow:
disable error correction for receive ATM-cell headers
When set to a high level, this bit causes the error-detection and correction block to stop correcting single-bit
errors that are detected in the headers of incoming ATM cells. When a reset operation is performed, this bit is
cleared (set to 0). The normal operating state of the TNETA1500A provides single-bit error correction on the
headers of incoming ATM cells, and an action must be taken to disable this operation.
disable transmit ATM-cell header HEC-byte generation
Whensettoahighlevel, thisbitcausesthetransmitsectiontostopgeneratingtheHECbyteinthe5-byteheader
ofATMcellstransmitted. Whenaresetoperationoccurs, thisbitiscleared(setto0). Thenormaloperatingmode
of the TNETA1500A calculates the HEC byte from the first four bytes of the ATM cell transmitted and inserts
the calculated value in the HEC-byte location. This bit is used to disable the generation of the HEC byte.
enable terminal loopback (TLB)
When set to a high level, this bit causes the ATM-cells input (through the transmit-cell interface) to loop through
the device and be sent out through the receive-cell interface. The receive serial-data stream is blocked when
this mode of operation is chosen. However, the transmit section operates normally and the device continues
to transmit ATM cells that are inserted in an STS-3c/STM-1 frame. Internally, this bit is logically ORed with the
TLBinput, whichallowsaterminalloopbacktobeenabledthrougheithertheexternalinputorthroughthecontrol
register. When a reset operation occurs, the bit in the control register is cleared.
enable facility (serial) loopback (FLB)
When set to a high level, this bit causes the receive serial data and clock inputs to loop through the device and
be sent out through the transmit serial data and clock outputs. The transmit serial-data stream is blocked when
this mode of operation is chosen. However, the receive section operates normally, and the device continues
to extract ATM cells from the incoming STS-3c/STM-1 frame. Internally, this bit is logically ORed with the FLB
input, which allows a facility loopback to be enabled through either the external input terminal or through the
control register. When a reset operation occurs, the bit in the control register is cleared.
12
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155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
disable the dropping of ATM cells with multiple-bit header errors
When set to a high level, this bit causes the receive section to stop dropping ATM cells that contain multiple-bit
header errors. When a reset operation occurs, this bit is cleared. The normal operation of the TNETA1500A
drops ATM cells that contain multiple-bit header errors by not placing them in the receive output FIFO.
disable the dropping of ATM idle cells from the receive-data stream
When this bit is set, the receive section does not drop ATM idle cells from the receive-data stream. An idle cell
is defined as an ATM cell with the 5-byte header set to a value of 00 00 00 01 52 (hex). When a reset operation
occurs, this bit is cleared. The normal operation of the TNETA1500A is to drop idle cells from the
receive-data stream.
disable the dropping of ATM unassigned cells from the receive-data stream
When this bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An
unassigned cell is defined as an ATM cell with the 5-byte header set to a value of 00 00 00 00 55 (hex). When
a reset operation occurs, this bit is cleared. The normal operation of the TNETA1500A is to drop unassigned
cells from the receive-data stream.
transmit STM-1 frame
When this bit is set, the transmit section transmits an STM-1 frame instead of an STS-3c frame. Internally, this
bit is logically ORed with SDHENABLE, which allows this mode of operation to be enabled either through the
control register or the external input. When a reset operation occurs, this bit is cleared and causes the
TNETA1500A to transmit an STS-3c frame.
enable receive-clock looping
When this bit is set, the receive clock is used as the clock for the transmit side (clock looping). The receive clock
is either the receive serial clock or the clock recovered from the receive serial-data stream, depending on the
state of CLKRECBP. Internally, this bit is logically ORed with CLKLOOP, which allows the clock-loop function
to be enabled either through the control register or the external input. When a reset operation occurs, this bit
is cleared, which disables the clock loop.
transmit ATM unassigned cells as filler
When this bit is set, the transmit side sends ATM unassigned cells for cell rate decoupling when a user-data
cell is not available in the transmit FIFO. An unassigned cell is defined as a cell with the 5-byte header set to
a value of 00 00 00 00 55 (hex). The payload is set to 6A (hex). When this bit is not set, the device sends idle
cells as filler cells for cell-rate decoupling. An idle cell is defined as a cell with the 5-byte header set to a value
of 00 00 00 01 52 (hex) and the payload set to 6A (hex). When a reset operation occurs, this bit is cleared.
ID register
The ID register is located at address 03 (hex). This register identifies the device revision and also provides a
means of performing a software reset. The contents of this register are hardwired to a hexadecimal value of Ax
(x denotes the chip revision). A software reset on the TNETA1500A is initiated by writing to the ID register
through the controller interface. Since the contents of the ID register are firmware, the write does not change
the contents of the register. The software-reset function is logically ORed with RESET. A reset of the
TNETA1500A device is initiated through either the external input or the ID register.
multierrored cell-header counter
The multierrored cell-header counter is a saturating 8-bit counter that counts the number of ATM cells that are
received with multiple-bit errors in the 5-byte ATM header. This counter resets to zero when the register is read.
This counter does not cause INTR to go active low when the counter reaches maximum count. This counter
is set to zero when a reset operation occurs.
13
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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
path-RDI soak counter
This counter provides a count of the amount of time, in increments of 125 µs, that a LOCA condition must be
presentbeforeapath-RDIconditionissentviatheoutgoingG1byte. Theamountoftimerequiredisnotcurrently
specified by any industry standard. This counter is preset to a value of 4 ms when a reset operation occurs. The
counter value is modified by writing a new value to the counter through the controller interface. For instance,
to set the value in the counter to 1 ms, a value of eight (8 × 125 µs = 1 ms) is written in the counter. However,
the value in the counter is rewritten if a reset operation occurs because the counter is reset to 4 ms.
B1/B2/B3 block-error counters
These counters maintain the total number of frames received with B1, B2, and B3 errors. These counters track
the number of frames with errors, not the number of actual B1, B2, and B3 bits in error. All three counters are
8-bit counters. These 8-bit counters are read only and a reset operation clears all three counters. When these
counters reach their maximum count, INTR goes active low and a bit is set high in the interrupt register IR2. The
host system reads the IR registers to determine the cause of the interrupt. The host reads the counters to reset
them to zero, and finally, the host system reads IR2 again to clear the INTR line and the block-error-counter bit
on the IR2.
B1/B2/B3 coding-violation counters
These counters maintain the total number of receive B1, B2, and B3 BIP bits that are in error. The B1 and B3
counters are 16-bit counters, and the B2 counter is a 19-bit counter. When one of the counters reaches its
maximum count, INTR goes active low and a bit in the interrupt register is set. After the counters reach their
maximum count, they roll over and continue to count. To clear the interrupt condition, the host system reads any
of the three interrupt registers. After the host reads both counters in this sequence, both LSB and MSB counters
are reset to zero. The device clears both counters after the MSB counter is read. Software must read LSB first
to obtain its value before the LSB and MSB counters are cleared. A reset operation clears all three counters.
Since these counters are read only, a value cannot be written to any of the three counters.
14
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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
Terminal Functions
high-speed serial differential interface
TERMINAL
DESCRIPTION
I/O
NAME
NO.
Loss-of-optical-carrier alarm (true and complement). FLAGC and FLAGT are connected to a fiber-optic
receiver loss-of-optical-carrier output to provide an interrupt through the controller interface when the
incoming optical signal is lost.
FLAGC,
FLAGT
I
30, 31
(PECL)
RSCT,
RSCC
I
Receive serial clock (true and complement). RSCT and RSCC are used to clock in serial data on RSDT and
32, 33
41, 42
(PECL) RSDC when the clock-recovery phase-lock loop is bypassed by taking CKRECBP high.
RSDT,
RSDC
I
Receive serial data (true and complement). RSDT and RSDC are differential PECL inputs.
(PECL)
Transmit serial clock (true and complement). TSCT and TSCC provide the transmit serial output clock. This
clock is derived from either the receive serial clock, the output of the clock generation phase-lock loop, or
the transmit high-speed clock, depending on the state of CKGENBP and CLKLOOP.
TSCT,
TSCC
O
53, 54
(PECL)
TSDT,
TSDC
O
51, 52
49, 50
Transmit serial data (true and complement). TSDT and TSDC data is output on TSCT and TSCC.
(PECL)
TXHCKT,
TXHCKC
I
Transmit high-speed clock (true and complement). TXHCKT and TXHCKC (155.52 MHz) provide the
(PECL) transmit serial clock when CKGENBP is high.
alarm indicators
TERMINAL
DESCRIPTION
I/O
NAME
NO.
B1ERR
125
O
B1 error. A high on B1ERR indicates that a B1 parity-byte error is detected on the incoming frame.
Line alarm-indication signal. A high on LAIS indicates that bits 6–8 of the receive K2 byte are set to 111 for five
consecutive frames. The alarm clears when any non-111 pattern is detected in bits 6–8 of the receive K2 byte
for five consecutive frames.
LAIS
122
123
O
O
Line far-end receive failure. A high on LFERF indicates that bits 6–8 of the receive K2 bytes are set to 110 for
five consecutive frames. The alarm clears when any non-110 pattern is detected in bits 6–8 of the receive
K2 byte for five consecutive frames.
LFERF
Loss of cell alignment. A high on LOCA indicates that ATM cells cannot be found in the incoming data stream.
LOCA goes inactive when the cell-delineation algorithm finds seven consecutive ATM cells and goes active
when no valid ATM cells are found in seven consecutive cell slots.
LOCA
LOF
124
133
O
O
Loss of frame. LOF goes active when the framing circuit is unable to find two consecutive SONET frames for
3 ms. The alarm is cleared when eight consecutive error-free SONET frames are identified.
Loss of incoming pointer. LOP goes active to indicate that an invalid pointer was found in the H1, H2 pointer
bytes of the incoming frame. LOP also goes active when a new data flag (NDF) is detected for eight consecutive
frames. The LOP alarm deactivates when a valid pointer with a normal NDF is detected in three consecutive
frames.
LOP
121
O
Loss of signal. LOS goes active when no signal transitions are detected on the incoming serial signal for 3.3
µs.ThealarmisclearedwhentwoconsecutivevalidSONETframingpatternsaredetectedandnotransitionless
3.3-µs period is detected.
LOS
OOF
128
129
116
O
O
O
Out of frame. OOF goes active when four consecutive errored SONET frames are received. The alarm clears
when two consecutive error-free SONET frames are identified.
Loss of receive data. LOSRD goes active when the receive output FIFO overflows. The receive output FIFO
can store a maximum of three complete ATM cells. If a cell is not sent to the next device before a fourth cell
arrives, the newest cell is discarded to make room in the FIFO for the next arriving cell.
LOSRD
15
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155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
Terminal Functions (continued)
control signals
TERMINAL
DESCRIPTION
I/O
NAME
NO.
Clock-generation phase-locked loop bypass. When CKGENBP is high, the clock-generation PLL is
bypassed and the high-speed clock input (TXHCKT/TXHCKC) is used for the transmit clock. When
CKGENBP is low, the 19.44-MHz TXREFCK is used to generate the transmit clock.
I
CKGENBP
136
(TTL)
I
Clock-recovery phase-locked loop bypass. When CKRECBP is high, the clock-recovery PLL is bypassed.
RSCT/RSCC is used to clock RSDT/RSDC into the device.
CKRECBP
CLKLOOP
135
134
(TTL)
Receive clock loop. When CLKLOOP is high and CKGENBP is low, the receive-serial clock is looped to the
transmit side and used for the transmit-serial clock. The received clock is either the clock recovered from
the incoming data stream or RSCT/RSCC as determined by the state of CKRECBP.
I
(TTL)
Facility loopback. When FLB is high, the receive-serial data and clock is looped to the transmit-serial clock
and data output. The receive-serial clock is either the clock recovered from the incoming data stream or
RSCT/RSCC as determined by the state of CKRECBP.
I
FLB
OE
138
58
(TTL)
Output enable. When OE is low, all outputs on the TNETA1500A, except for the high-speed PECL outputs,
are placed in the high-impedance state. This feature facilitates board-level testing. OE contains an internal
pullup resistor so that it can be left open for normal operation.
I
(TTL)
Device reset. When RESET goes high, the device is reset. Reset causes the receive side to restart the
frame-search algorithm and forces OOF, LOF, and LOCA high. RESET also flushes any ATM cells stored
in the input and output FIFOs and causes the transmit side to begin building SONET frames from the A1
byte. The RESET pulse is high for a minimum of 51 ns to reset the TNETA1500A.
I
RESET
142
57
(TTL)
SDH enable. When SDHENABLE is high, the frame transmitted by the TNETA1500A has the 3 C1 bytes
set to the sequence 01 00 00 (hex). In addition, the 3 H1 bytes in the transmit frame set to the values 6A,
9B, 9B (hex). When SDHENABLE is low, the transmit C1 bytes are set to the sequence 01 02 03 (hex) and
the H1 bytes are set to the values 62, 93, 93 (hex). These conditions are necessary to comprehend the
differences between a SONET STS-3c frame and an SDH STM-1 frame. SDHENABLE has an internal
pulldown resistor so that it can be left open for SONET operation.
I
SDHENABLE
(TTL)
Terminalloopback. WhenTLBistakenhigh, thedatareceivedatthetransmit-cellinterfaceisloopedthrough
the device and out the receive-cell interface. Data appearing at the receive serial data input is blocked in
this mode.
I
TLB
137
48
(TTL)
Transmit-reference clock. TXREFCK is used to provide a 19.44-MHz reference clock to the
clock-generation PLL when CKGENBP and CLKLOOP are low. The clock-generation PLL multiplies this
clock by eight to generate the 155.52-MHz transmit-serial clock.
I
TXREFCK
(TTL)
16
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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
Terminal Functions (continued)
receive-cell interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I
Receiveclockinput. Outputsignalsareclockedoutofthereceive-cellinterfaceonpositivetransitionsofRCKI
RCKI
120
(TTL) when RRE is low.
92–95
98–101
Receive byte data. The ATM cells are clocked out of the TNETA1500A through RD0–RD7 one byte at a time
on positive transitions of RCKI, which begins with the first byte of the ATM-cell header.
RD0–RD7
O
I
119
117
118
Receive read enable. A low level on RRE enables the reading of data from the receive-cell interface.
RRE
(TTL)
Receive ATM-cell indicator. RXCELL goes high to identify the first byte (start) of an ATM cell. RXCELL is low
during the remainder of the output.
RXCELL
O
O
Receive FIFO empty. RXFE goes low to denote that the receive FIFO is empty and that the current output
byte is not a valid byte. RXFE goes high when a complete ATM cell is available for output.
RXFE
transmit-cell interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I
Transmit clock input. Input signals are clocked into the transmit-cell interface and output signals are clocked
TCKI
65
(TTL) out of the transmit-cell interface on positive transitions of TCKI when TWE is low.
68–71
74–77
I
Transmit byte data. The ATM cells are clocked into the transmit-cell interface one byte at a time on positive
TD0–TD7
(TTL) transitions of TCKI when TWE is low.
I
64
61
63
Transmit write enable. A low level on TWE enables the writing of ATM cells into the transmit-cell interface.
(TTL)
TWE
TXAF
TransmitFIFOalmostfull. TXAFgoeslowwhenthetransmitcellinputFIFOcanstoreonlyfiveadditionalinput
bytes. TXAF goes high when storage is available in the FIFO to store a complete 53-byte ATM cell.
O
I
Transmit start-of-cell indicator. A high level on TXCELL identifies the first byte of an incoming ATM cell.
(TTL) TXCELL should be low during the remainder of the cell input.
TXCELL
controller interface
TERMINAL
DESCRIPTION
I/O
NAME
NO.
I
A0–A7
19–26
Address lines. A0–A7 provide the address for accessing the internal registers. A7 is the most-significant bit.
(TTL)
1–4
7–10
Data I/O. D0–D7 provide access to the contents of the device’s internal registers. D7 is the most-significant
bit.
D0–D7
INTR
I/O
Interrupt (open drain). INTR goes low to indicate that a nonmasked interrupt has occurred. A read to any of
the interrupt registers makes the INTR signal inactive (high).
13
O
I
Read/write control. A high-level input on RD/WR indicates a read operation and a low-level input indicates
(TTL) a write operation.
16
14
15
RD/WR
READY
SEL
O
Ready. READY goes low to indicate that the device is ready to complete the requested transaction.
I
Device select. A low-level input on SEL enables the access of the device’s internal registers.
(TTL)
17
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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
Terminal Functions (continued)
miscellaneous signals
TERMINAL
DESCRIPTION
I/O
NAME
NO.
Clock-generation loop-filter external capacitor connection. A 0.01-µF capacitor is
connected from CGCAP to ground.
CGCAP
46
Clock-recovery loop-filter external capacitor connection. A 330-pF capacitor is connected
from CRCAP to ground.
CRCAP
AGND
37
35, 38, 39, 44, 45, 56
34, 36, 40, 43, 47, 55
Analog ground. AGND is the 0-V reference connection for APLLs.
AV
CC
Analog supply voltage. AV is the 5 V ±5% connection for APLLs.
CC
27–29, 80–83, 86–89,
104–107, 110–113
NC
No connection. These terminals are left open.
5, 11, 17, 62, 66, 72, 79,
85, 91, 97, 103, 109,
115, 127, 132, 144
GND
Ground. GND is the 0-V reference for digital logic.
6, 12, 18, 67, 73, 78, 84,
90, 96, 102, 108, 114,
126, 131, 143
V
CC
Supply voltage. V
is the 5-V ±5% supply for digital logic.
CC
TEST0–TEST3
TEST4
59, 60, 139, 140
141
I
I
Manufacturing test. TEST0–TEST3 are connected to V
for normal operation.
CC
Test. TEST4 is tied low for normal operation.
8KHZREF produces a pulse that is synchronized to the receive-side framing bytes.
8KHZREF serves as an indication that a frame is being received. When frames are
continuously received, 8KHZREF acts like an 8-kHz clock.
8KHZREF
130
O
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1): TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Analog supply voltage range, AV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
PECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to PV
CC
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
recommended operating conditions (see Note 2)
MIN
4.75
4.75
4.75
2
MAX
5.25
5.25
5.25
UNIT
TTL
V
Supply voltage
V
V
V
CC
PECL
AV
CC
Supply voltage, analog
High-level input voltage
TTL
V
IH
PECL (see Note 2)
TTL
V
V
–1.1
V
V
–0.8
CC
0.8
CC
V
IL
Low-level input voltage
V
PECL (see Note 2)
–1.9
0
–1.5
70
CC
CC
T
A
Operating free-air temperature
°C
NOTE 2: Thealgebraic convention, in which the least-positive (most-negative) value is designated minimum, is used for logic-level voltages only.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 4.75 V,
= 4.75 V,
I
I
I
I
I
= –18 mA
–1.2
V
IK
CC
IK
TTL
= –4 mA
= –22.4 mA
= 4 mA
4.25
4
CC
OH
OH
OL
OL
High-level output voltage
V
OH
PECL
TTL
PV
= 5 V,
= 4.75 V,
4.3
0.5
CC
V
CC
PV
V
OL
Low-level output voltage
Input current
V
PECL
TTL
= 5 V,
= 7.6 mA
3
3.4
CC
I
I
V
= 5.25 V,
V = V
I
or GND
±300
µA
CC
CC
CC
All other
PECL inputs
V
= 5.25 V,
V = 4.45 V
I
25
250
I
IH
High-level input current
Low-level input current
µA
µA
FLAGT, FLAGC,
PECL inputs
V
CC
V
CC
V
CC
= 5.25 V,
= 5.25 V,
= 5.25 V,
V = 4.45 V
I
All other
PECL inputs
V = 3.35 V
I
±25
I
IL
FLAGT, FLAGC,
PECL inputs
V = 3.35 V
I
–250
‡
§
I
I
Supply current
Supply current
V
V
= 5.25 V,
= 5.25 V,
I = 0,
f = 155.52 Mbits/s
f = 155.52 Mbits/s
150
230
4
180
255
mA
mA
pF
CC1
CC
O
CC2
CC
C
Input capacitance
TTL
i
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
CC
PECL outputs are unterminated.
PECL outputs are terminated with a 50-Ω resistor to 3 V.
A
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
timing requirements (see Figure 1)
NO.
MIN
35
3
MAX
UNIT
ns
1
2
3
4
t
t
t
t
Pulse duration, SEL low
w(SELL)
Setup time, RD/WR high before SEL↓
Setup time, A0–A7 valid before SEL↓
Hold time, A0–A7 valid after SEL↓
ns
su(RD/WR)
su(A0–A7)
h(A0–A7)
0
ns
4
ns
5
t
Hold time, RD/WR high after SEL↓
35
ns
h(RD/WR)
switching characteristics (see Figure 1)
NO.
MIN
7
MAX
25
UNIT
ns
6
7
8
t
t
t
Delay time, SEL↓ to D0–D7 valid
Delay time, SEL↑ to D0–D7 invalid
Delay time, SEL↓ to READY↓
d(SL–DV)
d(SH–DX)
d(SL–RL)
5
18
ns
7
26
ns
9
t
Delay time, SEL↑ to READY↑
3
15
ns
d(SH–RH)
RD/WR
(input)
2
3
5
1
SEL
(input)
4
A0–A7
(input)
8
9
READY
(output)
6
7
D0–D7
(output)
Invalid
Valid
Invalid
Figure 1. Controller-Interface Read Cycle
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
timing requirements (see Figure 2)
NO.
MIN
35
1
MAX
UNIT
ns
1
2
3
t
t
t
Pulse duration, SEL low
w(SELL)
Setup time, RD/WR low before SEL↓
Setup time, A0–A7 valid before SEL↓
ns
su(RD/WR)
su(A0–A7)
0
ns
4
5
6
t
t
t
Setup time, D0–D7 valid before SEL↑
Hold time, D0–D7 valid after SEL↑
Hold time, RD/WR low after SEL↓
5
0
ns
ns
ns
su(D0–D7)
h(D0–D7)
h(RD/WR)
35
RD/WR
(input)
2
3
6
1
SEL
(input)
A0–A7
(input)
4
5
D0–D7
(input)
Figure 2. Controller-Interface Write Cycle
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
timing requirements (see Note 3 and Figure 3)
NO.
MIN
10
MAX
UNIT
ns
1
2
3
4
5
6
t
t
t
t
t
t
Pulse duration, RCKI high
w(RCKIH)
w(RCKIL)
su(RRE)1
su(RRE)2
h(RRE)1
h(RRE)2
Pulse duration, RCKI low
10
ns
Setup time, RRE high before RCKI↑
Setup time, RRE low before RCKI↑
Hold time, RRE high after RCKI↑
Hold time, RRE low after RCKI↑
8
8
0
0
ns
ns
ns
ns
NOTE 3: All output signals are generated on the rising edge of RCKI. All input signals are sampled on the rising edge of RCKI.
switching characteristics (see Note 3 and Figure 3)
NO.
MIN
MAX
UNIT
f
t
t
t
t
t
Maximum clock frequency for RCKI
Delay time, RCKI↑ to RXCELL↑
Delay time, RCKI↑ to RD0–RD7 valid
Delay time, RCKI↑ to RXFE↑
50
MHz
max(RCKI)
7
8
9
5
5
4
5
5
18
16
12
11
18
ns
ns
ns
ns
ns
d(RCH–RXCH)
d(RCH–RDV)
d(RCH–RXFH)
d(RCH–RXFL)
d(RCKI–RXCH)
†
10
11
Delay time, RCKI↑ to RXFE↓
Delay time, RCKI↑ to RXCELL↓
†
RXFE goes active low when no complete cell is available in the receive cell FIFO. When a complete cell is available, RXFE is deactivated. The
pulse duration of this signal depends on the pulse duration of the RCKI clock and on the cell availability of the FIFO. The minimum pulse duration
is equal to the RCKI width. The maximum width is dependent on the RCKI clock pulse duration and cell availability.
NOTE 3: All output signals are generated on the rising edge of RCKI. All input signals are sampled on the rising edge of RCKI.
1
2
RCKI
(input)
3
5
4
6
RRE
(input)
7
8
11
RXCELL
(output)
RD0–RD7
(output)
Byte 53
10
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
9
RXFE
(output)
If necessary
Figure 3. Receive-Cell Interface
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
timing requirements (see Note 4 and Figure 4)
NO.
1
MIN
10
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, TCKI high
w(TCKIH)
2
Pulse duration, TCKI low
10
ns
w(TCKIL)
3
4
Setup time, TWE high before TCKI↑
Setup time, TXCELL high before TCKI↑
Setup time, TD0–TD7 valid before TCKI↑
Setup time, TWE low before TCKI↑
Setup time TXCELL low before TCKI↑
Hold time, TWE high after TCKI↑
Hold time, TXCELL high after TCKI↑
Hold time, TD0–TD7 valid after TCKI↑
Hold time, TWE low after TCKI↑
Hold time, TXCELL low after TCKI↑
12
12
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(TWE)1
su(TXCELL)1
su(TD0–TD7)
su(TWE)2
5
6
7
su(TXCELL)2
h(TWE)1
8
9
0
h(TXCELL)1
h(TD0–TD7)
h(TWE)2
10
11
12
0
0
0
h(TXCELL)2
NOTE 4: All output signals are generated on the rising edge of TCKI. All input signals are sampled on the rising edge of TCKI.
switching characteristics (see Note 4 and Figure 4)
NO.
MIN
MAX
UNIT
f
t
t
Maximum clock frequency for TCKI
Delay time, TCKI↑ to TXAF↓
Delay time, TCKI↑ to TXAF↑
50
MHz
max(TCKI)
13
14
4
4
12
12
ns
ns
d(TCH–TXAF)
d(TCKI–TXAF)
NOTE 4: All output signals are generated on the rising edge of TCKI. All input signals are sampled on the rising edge of TCKI.
1
2
TCKI
(input)
3
8
6
11
TWE
(input)
4
9
7
12
TXCELL
(input)
10
5
TD0–TD7
(input)
Input
Ignored
Byte 1
Byte 2
Byte 3
Byte 48
13
Byte 49
Byte 50
Byte 51
14
TXAF
(output)
Figure 4. Transmit-Cell Interface
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
switching characteristics (see Figure 5)
NO.
MIN
MAX
UNIT
1
t
Pulse duration, 8KHZREF low
22
27
ns
w(8KHZREFL)
1
8KHZREF
(output)
Figure 5. 8-kHz Reference Signal
APPLICATION INFORMATION
introduction
The TNETA1500A SONET/SDH ATM receiver/transmitter is designed to insert/extract ATM cells into/from a
155.52-Mbit/s STS-3c/STM-1 frame. The device contains two APLLs and the digital logic necessary to process
the incoming frame and build the output frame. The two APLLs are used to:
Recover a 155.52-MHz receive clock from the incoming serial-data stream
Generate a 155.52-MHz transmit clock from an external 19.44-MHz signal
The device is fabricated from a 0.8-µm BiCMOS process. The BiCMOS process provides the capability of
designing true differential PECL (ECL referenced to 5 V instead of ground) serial inputs and outputs. The
advantages of providing true PECL inputs and outputs are:
The device interfaces directly to fiber-optic receivers and transmitters and UTP-5 transceivers without
external buffering.
The device outputs can directly drive a 50-Ω line terminated with 50 Ω to 3 V or the Thevenin equivalent
(121 Ω to ground and 82 Ω to
improves performance.
V
). This eliminates transmission-line reflections and
CC
The differential PECL inputs provide a high common-mode noise-rejection ratio (CMRR), which improves
noise immunity of the device.
The reduced output voltage swing of the differential PECL outputs (approximately 800 mV) reduces the
internal noise generated when the high-speed serial outputs switch. This is especially important since the
outputs are switching at 155.52 Mbits/s.
Internally, the two APLLs are isolated from each other and the digital logic blocks (see Figure 6). Each APLL
has its own V
and ground connections that are not connected internally to the V
and ground connections
CC
CC
of the other blocks. From a power and ground connection viewpoint, this forms three blocks: the digital logic
block, the analog clock-recovery block, and the analog clock-generation block.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
APPLICATION INFORMATION
330 pF
AV
CC
AGND
CRCAP
RSDT
RSDC
Analog
Clock
Recovery
ATM
Cells
Out
PECL-to-CMOS
Converter
Serial-to-Parallel
Converter
Receive
Digital Logic
TSDT
TSDC
ATM
Cells
In
CMOS-to-PECL
Converter
Parallel-to-Serial
Converter
Transmit
Digital Logic
Analog
Clock
Generation
PECL-to-CMOS
Converter
0.01 µF
CGCAP
AV
CC
AGND
V
CC
GND
Figure 6. Analog and Digital Blocks in the TNETA1500A
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
APPLICATION INFORMATION
general layout considerations for the TNETA1500A
The major considerations in laying out a board for the TNETA1500A are:
Decouple the analog power supply (AV
an inductor or ferrite bead. For example:
terminals) from the digital power supply (V
terminals) using
CC
CC
–
Connect the AV terminals for the clock-recovery block together and use an inductor/ferrite bead to
CC
connect them through inductor LI to 5 V. Then, connect the AV
terminals for the clock-generation
CC
block together and use a second inductor/ferrite bead to connect these terminals through inductor LI
to 5 V.
Use low-inductance bypass capacitors, such as 0.1-µF surface-mount devices, to reduce V
noise due
CC
to output switching. The recommended bypassing is one bypass capacitor for each AV terminal and one
CC
bypass capacitor for each two V
capacitor is recommended between each analog section and ground.
terminals. For more filtering, an additional 10-µF surface-mount
CC
The TNETA1500A supply should be filtered from the main power supply. This can be accomplished with
apifilterconsistingoftwo470-µFcapacitorsanda220-µHinductor. Tomaintainasmallvoltagedropacross
theinductor, theinductorshouldhavealowdcresistance. Avoltageregulatorcanbeusedifahighervoltage
(> 5 V) is available.
There are many ways to physically lay out the planes that are described. One method is to cut each isolated
AV
plane out of the V
plane. These isolated planes are placed directly under the associated portions
CC
CC
of the device for easy connection to the pins. The ground plane can remain solid, with no cutouts under the
isolated V planes.
CC
The PECL inputs to the device are terminated using a split-resistor termination of 121 Ω to ground and 82 Ω
to V . Placing the termination resistors close to the input terminals reduces the possibility of signal reflections
CC
and maintains the integrity of the signal waveform. The PECL outputs also are terminated using a split-resistor
termination of 121 Ω to ground and 82 Ω to V . The termination resistors should be placed as close as possible
CC
to the input terminals of the device that the TNETA1500A is driving to prevent reflections and maintain
signal integrity.
External capacitors connected to terminals CGCAP and CRCAP must be connected to the APLLs to provide
theloop-filtercapacitance. OnecapacitorisrequiredforeachAPLL. Therecommendedvaluesofthecapacitors
connected to CRCAP and CGCAP terminals are 330 pF and 0.01 µF, respectively.
Figure 7 shows a typical connection between the TNETA1500A and fiber-optic or UTP-5 transceiver with PECL
inputs and outputs. In this diagram, the AV terminals are broken out between the analog clock-recovery block
CC
and the analog clock-generation block.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
APPLICATION INFORMATION
4.1 µH
To Other
AV
CC
Terminals for
Clock-Recovery
V
Terminals
CC
Power Plane
Terminals (34, 36, 40, 43)
0.1
0.1
10 µF
µF
0.1
µF
0.1
0.1
µF
µF
µF
4.1 µH
V
CC
34 36
40 43
18 12
121 Ω
82 Ω
41
RSDT
RSDC
42
LI
220 µH
Line
Receiver
(fiber optic
or UTP-5)
121 Ω
82 Ω
5 V
C1
470
37
CRCAP
CGCAP
V
CC
C2
470
µF
330
pF
µF
TNETA1500A
46
0.01
Filter
µF
Line
V
CC
Transmitter
(fiber optic
or UTP-5)
121 Ω
121 Ω
82 Ω
51
52
TSDT
TSDC
82 Ω
47 55
67 73
78 84
Power Plane
V
CC
To Other
Terminals
0.1 µF
10
µF
0.1 µF
0.1 µF
0.1 µF
V
CC
4.1 µH
Terminals for Clock-Generation Terminals (47, 55)
AV
CC
NOTES: A. If TXHCKT, TXHCKC, RSCT, and RSCC are not used, they should be terminated as follows:
TXHCKT (terminal 49) – 1-kΩ resistor to V
CC
TSHCKC (terminal 50) – 1-kΩ resistor to GND
RSCT (terminal 32) – 1-kΩ resistor to V
CC
RSCC (terminal 33) – 1-kΩ resistor to GND
B. FLAGT and FLAGC contain internal pullup/pulldown resistors and can be left open.
C. All AGND and GND terminals are connected to the same ground plane.
D. It is recommended that one 0.1-µF capacitor be used for each two V
CC
terminals (digital-power terminals).
E. Ferrite beads can be used in place of the 4.1-µH inductors. The following are part numbers of beads from Fair-Rite Corporation
that can be used. Other beads from other manufacturers may work as well:
Surface-mount ferrite beads:
Fair-Rite P/N 2743021447 (long bead)
Fair-Rite P/N 2743019447 (short bead)
Leaded ferrite bead:
Fair-Rite P/N 2743002111
F. Inductor LI – Toko 622LY–221K (Toko 822LY–221K)
G. Capacitors C1 and C2 – Panasonic ECE–A1AFS471 (radial) and Panasonic ECE–V1AA471 (surface mount)
Figure 7. Board Layout for the TNETA1500A
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TNETA1500APCM
TNETA1500APGE
OBSOLETE
OBSOLETE
QFP
PCM
144
144
TBD
TBD
Call TI
Call TI
Call TI
Call TI
LQFP
PGE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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