TO-PMOD-11 [TI]
8A SIMPLE SWITCHER® Power Module with 20V Maximum Input Voltage and Current Sharing; 8A SIMPLE SWITCHER®电源模块与20V最大输入电压和电流共享
| 型号： | TO-PMOD-11 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8A SIMPLE SWITCHER® Power Module with 20V Maximum Input Voltage and Current Sharing |
| 文件： | 总26页 (文件大小：1987K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMZ22008
LMZ22008 8A SIMPLE SWITCHER® Power Module with 20V Maximum Input Voltage
and Current Sharing
Literature Number: SNVS712D
June 13, 2011
LMZ22008
8A SIMPLE SWITCHER® Power Module with 20V Maximum
Input Voltage and Current Sharing
Easy to use 11 pin package
Performance Benefits
High efficiency reduces system heat generation
■
■
Low radiated emissions (EMI) complies with EN55022
(Note 2)
Only 7 external components
■
■
■
■
Low output voltage ripple
No external heat sink required
Simple current sharing for higher current applications
30153901
System Performance
TO-PMOD 11 Pin Package
15 x 17.79 x 5.9 mm (0.59 x 0.7 x 0.232 in)
Efficiency VIN = 12V, VOUT = 3.3V
θ
JA = 9.9 °C/W, θJC = 1.0 °C/W (Note 1)
RoHS Compliant
100
90
80
70
60
50
Electrical Specifications
40W maximum total output power
■
■
■
■
Up to 8A output current
Input voltage range 6V to 20V
Output voltage range 0.8V to 6V
12Vin
40
Efficiency up to 92%
0
1
2
3
4
5
6
7
8
■
OUTPUT CURRENT (A)
30153903
Key Features
Thermal derating curve
VIN = 12V, VOUT = 3.3V
Integrated shielded inductor
■
■
■
■
Simple PCB layout
10
Frequency synchronization input (350 kHz to 600 kHz)
8
Current sharing capability
6
Flexible startup sequencing using external soft-start,
■
tracking and precision enable
4
Protection against inrush currents and faults such as input
UVLO and output short circuit
■
2
θJA = 9.9 °C/W
0
– 40°C to 125°C junction temperature range
■
■
20 30 40 50 60 70 80 90 100110120
AMBIENT TEMPERATURE (°C)
Single exposed pad and standard pinout for easy
mounting and manufacturing
Fully enabled for Webench® Power Designer
30153909
■
■
Radiated EMI (EN 55022)
VIN = 12V, VOUT = 5V, IOUT = 8A
Pin compatible with LMZ22010/06, LMZ12010/08/06,
LMZ23610/08/06, and LMZ13610/08/06
50
45
40
35
30
25
20
15
Applications
Point of load conversions from 12V input rail
■
■
■
■
Time critical projects
Space constrained / high thermal requirement applications
Horizontal Peak
Vertical Peak
Class B Limit
Class A Limit
10
5
Negative output voltage applications See AN-2027
0
0
1002003004005006007008009001000
FREQUENCY (MHz)
30153914
Note 1: θJA measured on a 75mm x 90 mm four-layer PCB
Note 2: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B, tested on
Evaluation Board with EMI configuration
© 2011 National Semiconductor Corporation
301539
www.national.com
Simplified Application Schematic
30153924
Connection Diagram
30153933
Top View
11-Lead TO-PMOD
Ordering Information
Order Number
LMZ22008TZ
LMZ22008TZE
Package Type
TO-PMOD-11
TO-PMOD-11
NSC Package Drawing
TZA11A
Supplied As
32 Units in a Rail
TZA11A
250 Units on Tape and Reel
Pin Descriptions
Pin
Name Description
1, 2
VIN Input supply — Nominal operating range is 6V to 20V . A small amount of internal capacitance is contained within
the package assembly. Additional external input capacitance is required between this pin and the exposed pad
(PGND).
3
4
SYNC Synchronization — Apply a CMOS logic level square wave whose frequency is between 314 kHz and 600 kHz to
synchronize the PWM operating frequency to an external frequency source. When not using synchronization this pin
must be tied to ground. The module free running PWM frequency is 359 kHz (Typ).
EN
Enable — Input to the precision enable comparator. Rising threshold is 1.274V typical. Once the module is enabled,
a 13 uA source current is internally activated to facilitate programmable hysteresis.
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2
Pin
5, 6
7
Name Description
AGND Analog Ground — Reference point for all stated voltages. Must be externally connected to PGND(EP).
FB
Feedback — Internally connected to the regulation amplifier and over-voltage comparator. The regulation reference
point is 0.795V at this input pin. Connect the feedback resistor divider between VOUT and AGND to set the output
voltage.
8
9
SS
SH
Soft-Start/Track Input — To extend the 1.6 mSec internal soft-start connect an external soft start capacitor. For
tracking connect to an external resistive divider connected to a higher priority supply rail. See applications section.
Share — Connect this pin to the share pin of other LMZ22008 modules to share the load between the devices. One
device should be configured as the master by connecting FB normally. All other devices should be configured as
slaves by leaving their respective FB pins floating. Leave SH floating if current sharing is not used. Do Not Ground.
See applications section.
10, 11 VOUT Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad
(PGND).
EP
PGND Exposed Pad / Power Ground — Electrical path for the power circuits within the module. PGND is not internally
connected to AGND (pin 5,6). Must be electrically connected to pins 5 and 6 external to the package. The exposed
pad is also used to dissipate heat from the package during operation. Use one hundred 12 mil thermal vias from top
to bottom copper for best thermal performance.
3
www.national.com
ESD Susceptibility (Note 4)
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
± 2 kV
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to PGND
-0.3V to 24V
-0.3V to 5.5V
-0.3V to 2.5V
-0.3V to 0.3V
150°C
Operating Ratings (Note 3)
EN, SYNC to AGND
SS, FB, SH to AGND
AGND to PGND
Junction Temperature
Storage Temperature Range
VIN
6V to 20V
0V to 5.0V
−40°C to 125°C
EN, SYNC
Operation Junction Temperature
-65°C to 150°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Unless otherwise stated the following conditions apply: VIN = 12V, VOUT = 3.3V
Min
(Note 5)
Typ
Max
Symbol
Parameter
Conditions
Units
(Note 6) (Note 5)
SYSTEM PARAMETERS
Enable Control
VEN
IEN-HYS
Soft-Start
ISS
EN threshold
VEN rising
1.096
40
1.274
13
1.452
60
V
EN hysteresis source current
VEN > 1.274V
µA
SS source current
VSS = 0V
50
µA
tSS
Internal soft-start interval
1.6
msec
Current Limit
ICL
Current limit threshold
d.c. average
10.5
A
Internal Switching Oscillator
fosc
Free-running oscillator
frequency
Sync input connected to ground
314
314
359
404
kHz
fsync
Synchronization range
Vsync = 3.3Vp-p
600
kHz
V
VIL-sync
Synchronization logic zero
amplitude
Relative to AGND
0.4
VIH-sync
Sync d.c
Synchronization logic one
amplitude
Relative to AGND
1.8
V
.
Synchronization duty cycle
range
15
50
85
%
Regulation and Over-Voltage Comparator
VFB
In-regulation feedback voltage VSS >+ 0.8V
0.775
0.795
0.86
0.815
V
V
IO = 8A
VFB-OV
Feedback over-voltage
protection threshold
IFB
IQ
Feedback input bias current
5
3
nA
Non Switching Quiescent
Current
SYNC = 3.0V
mA
ISD
Shut Down Quiescent Current VEN = 0V
Maximum Duty Factor
32
85
μA
%
Dmax
Thermal Characteristics
TSD
TSD-HYST
θJA
Thermal Shutdown
Rising
165
15
°C
°C
Thermal shutdown hysteresis
Falling
Junction to Ambient (Note 7)
Natural Convection
225 LFPM
500 LFPM
9.9
6.8
5.2
1.0
°C/W
Junction to Case
°C/W
θJC
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4
Min
(Note 5)
Typ
Max
Symbol
Parameter
Conditions
Units
(Note 6) (Note 5)
PERFORMANCE PARAMETERS(Note 8)
Output voltage ripple
Line regulation
BW@ 20 MHz
24
±0.2
1
mV PP
%
ΔVO
VIN = 12V to 20V, IOUT= 8A
VIN = 12V, IOUT= 0.001A to 8A
VIN = 12V VOUT = 3.3V IOUT = 5A
VIN = 12V VOUT = 3.3V IOUT = 8A
ΔVO/ΔVIN
Load regulation
Peak efficiency
mV/A
%
ΔVO/ΔIOUT
89.5
88.5
η
η
Full load efficiency
%
Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 4: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
Note 5: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25°C and represent the most likely parametric norm.
Note 7: Theta JA measured on a 3.0” x 3.5” four layer board, with two ounce copper on outer layers and one ounce copper on inner layers, two hundred and ten
12 mil thermal vias, and 2W power dissipation. Refer to evaluation board application note layout diagrams.
Note 8: Refer to BOM in Typical Application Bill of Materials — Table 1.
5
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Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12V; CIN = three x 10μF + 47nF X7R Ceramic; COUT = two x
330μF Specialty Polymer + 47 uF Ceramic + 47nF Ceramic; CFF = 4.7nF; Tambient = 25° C for waveforms. All indicated temper-
atures are ambient.
Efficiency 5.0V output @ 25°C
100
Dissipation 5.0V output @ 25°C
8
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
7
6
5
4
3
2
1
0
90
80
70
60
50
40
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153934
30153935
Efficiency 3.3V output @ 25°C
100
Dissipation 3.3V output @ 25°C
8
6Vin
8Vin
10Vin
12Vin
16Vin
20Vin
90
80
70
60
50
40
6
4
2
0
6Vin
8Vin
10Vin
12Vin
16Vin
20Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153936
30153937
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6
Efficiency 2.5V output @ 25°C
100
Dissipation 2.5V output @ 25°C
8
6 Vin
8 Vin
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
90
80
70
60
50
40
30
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153938
30153939
Efficiency 1.8V output @ 25°C
90
Dissipation 1.8V output @ 25°C
7
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
80
70
60
50
40
30
20
6
5
4
3
2
1
0
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153940
30153941
Efficiency 1.5V output @ 25°C
90
Dissipation 1.5V output @ 25°C
7
6 Vin
8 Vin
80
70
60
50
40
30
20
10
10 Vin
12 Vin
16 Vin
20 Vin
6
5
4
3
2
1
0
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153942
30153943
7
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Efficiency 1.2V output @ 25°C
90
Dissipation 1.2V output @ 25°C
8
6 Vin
8 Vin
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
80
70
60
50
40
30
20
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153944
30153945
Efficiency 1.0V output @ 25°C
90
Dissipation 1.0V output @ 25°C
7
6 Vin
8 Vin
80
70
60
50
40
30
20
10
10 Vin
12 Vin
16 Vin
20 Vin
6
5
4
3
2
1
0
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153946
30153947
Efficiency 5.0V output @ 85°C
100
Dissipation 5.0V output @ 85°C
9
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
8
7
6
5
4
3
2
1
0
90
80
70
60
50
40
30
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153948
30153949
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8
Efficiency 3.3V output @ 85°C
100
Dissipation 3.3V output @ 85°C
8
6 Vin
8 Vin
90
80
70
60
50
40
30
20
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153950
30153951
Efficiency 2.5V output @ 85°C
100
Dissipation 2.5V output @ 85°C
8
6 Vin
8 Vin
90
80
70
60
50
40
30
20
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153952
30153953
Efficiency 1.8V output @ 85°C
90
Dissipation 1.8V output @ 85°C
8
6 Vin
8 Vin
80
70
60
50
40
30
20
10
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153954
30153955
9
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Efficiency 1.5V output @ 85°C
90
Dissipation 1.5V output @ 85°C
8
6 Vin
8 Vin
80
70
60
50
40
30
20
10
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153956
30153957
Efficiency 1.2V output @ 85°C
90
Dissipation 1.2V output @ 85°C
8
6 Vin
8 Vin
80
70
60
50
40
30
20
10
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153958
30153959
Efficiency 1.0V output @ 85°C
90
Dissipation 1.0V output @ 85°C
8
6 Vin
8 Vin
80
70
60
50
40
30
20
10
7
6
5
4
3
2
1
0
10 Vin
12 Vin
16 Vin
20 Vin
6 Vin
8 Vin
10 Vin
12 Vin
16 Vin
20 Vin
0
2
4
6
8
0
2
4
6
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
30153960
30153961
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10
Normalized line and load regulation VOUT = 3.3V
Thermal derating VIN = 12V, VOUT = 5.0V
1.002
10
6 Vin
8 Vin
10 Vin
12 Vin
8
6
4
16 Vin
20 Vin
1.001
1.000
0.999
0.998
2
θJA = 9.9 °C/W
θJA = 6.8 °C/W
θJA = 5.2 °C/W
0
0
2
4
6
8
20
40
60
80
100
120
OUTPUT CURRENT (A)
TEMPERATURE (C)
30153962
30153963
Thermal derating VIN = 12V, VOUT = 3.3V
θ
30
27
24
21
18
15
12
9
JA vs copper heat sinking area
10
2 Layer 0 LFPM
2 Layer 225 LFPM
4 Layer 0 LFPM
8
6
4
4 Layer 225 LFPM
2
θJA = 9.9 °C/W
θJA = 6.8 °C/W
6
θJA = 5.2 °C/W
0
3
20
40
60
80
100
120
0
2
4
6
8
10
12
2
TEMPERATURE (C)
COPPER AREA (in )
30153964
30153965
Output ripple
12VIN, 5.0VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, 5.0VOUT@ Full Load, BW = 250 MHz
30153966
30153969
11
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Output ripple
12VIN, 3.3VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, 3.3VOUT@ Full Load, BW = 250 MHz
30153970
30153967
Output ripple
12VIN, 1.2VOUT @ Full Load, BW = 20 MHz
Output ripple
12VIN, 1.2VOUT@ Full Load, BW = 250 MHz
30153971
30153968
Transient response
12VIN, 5.0VOUT 1 to 8A Step
Transient response
12VIN, 3.3VOUT 1 to 8A Step
30153972
30153973
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12
Transient response
12VIN, 1.2VOUT 1 to 8A Step
Short circuit current vs input voltage
16
14
12
10
8
6
4
Output Current
Input Current
2
0
30153974
5
10
15
20
INPUT VOLTAGE (V)
30153975
3.3VOUT Soft Start, no CSS
3.3VOUT Soft Start, CSS = 0.47uF
30153976
301539a4
Block Diagram
30153977
13
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precision under voltage lock out (UVLO), the Enable input
may be left open circuit and the internal resistor will always
enable the module. In such case, the internal UVLO occurs
typically at 4.3V (VIN rising).
General Description
The LMZ22008 SIMPLE SWITCHER© power module is an
easy-to-use step-down DC-DC solution capable of driving up
to 8A load. The LMZ22008 is available in an innovative pack-
age that enhances thermal performance and allows for hand
or machine soldering.
In applications with separate supervisory circuits Enable can
be directly interfaced to a logic source. In the case of se-
quencing supplies, the divider is connected to a rail that
becomes active earlier in the power-up cycle than the
LMZ22008 output rail.
The LMZ22008 can accept an input voltage rail between 6V
and 20V and deliver an adjustable and highly accurate output
voltage as low as 0.8V. The LMZ22008 only requires two ex-
ternal resistors and external capacitors to complete the power
solution. The LMZ22008 is a reliable and robust design with
the following protection features: thermal shutdown, pro-
grammable input under-voltage lockout, output over-voltage
protection, short-circuit protection, output current limit, and
allows startup into a pre-biased output.
Enable provides a precise 1.274V threshold to allow direct
logic drive or connection to a voltage divider from a higher
enable voltage such as VIN. Additionally there is 13 μA (typ)
of switched offset current allowing programmable hysteresis.
See Figure 1.
The function of the enable divider is to allow the designer to
choose an input voltage below which the circuit will be dis-
abled. This implements the feature of a programmable UVLO.
The two resistors should be chosen based on the following
ratio:
The sync input allows synchronization over the 314 to 600
kHz switching frequency range and up to 6 modules can be
connected in parallel for higher load currents.
RENT / RENB = (VIN UVLO / 1.274V) – 1
(1)
Design Steps for the LMZ22008
Application
The LMZ22008 is fully supported by Webench® which offers:
component selection, electrical and thermal simulations. Ad-
ditionally, there are both evaluation and demonstration
boards that may be used as a starting point for design. The
following list of steps can be used to manually design the
LMZ22008 application.
The LMZ22008 typical application shows 12.7kΩ for RENB and
42.2kΩ for RENT resulting in a rising UVLO of 5.51V. Note that
this divider presents 4.62V to the EN input when VIN is raised
to 20V. This upper voltage should always be checked, making
sure that it never exceeds the Abs Max 5.5V limit for Enable.
A 5.1V Zener clamp can be applied in cases where the upper
voltage would exceed the EN input's range of operation. The
zener clamp is not required if the target application prohibits
the maximum Enable input voltage from being exceeded.
All references to values refer to the typical applications
Additional enable voltage hysteresis can be added with the
inclusion of RENH. It is possible to select values for RENT and
RENB such that RENH is a value of zero allowing it to be omitted
from the design.
schematic Figure 5 .
• Select minimum operating VIN with enable divider resistors
• Program VOUT with FB resistor divider selection
• Select COUT
Rising threshold can be calculated as follows:
• Select CIN
VEN(rising) = 1.274 ( 1 + (RENT|| 2 meg)/ RENB
)
(2)
• Determine module power dissipation
• Layout PCB for required thermal performance
Whereas the falling threshold level can be calculated using:
VEN(falling) = VEN(rising) – 13 µA ( RENT|| 2 meg ||
ENABLE DIVIDER, RENT, RENB AND RENHSELECTION
RENTB + RENH
)
(3)
Internal to the module is a 2 mega ohm pull-up resistor con-
nected from VIN to Enable. For applications not requiring
30153979
FIGURE 1. Enable input detail
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14
OUTPUT VOLTAGE SELECTION
the SS/TRK rises past 0.795V the input is no longer enabled
and the 50 uA internal current source is switched off.
Output voltage is determined by a divider of two resistors
connected between VOUT and AGND. The midpoint of the di-
vider is connected to the FB input.
The regulated output voltage determined by the external di-
vider resistors RFBT and RFBB is:
VOUT = 0.795V * (1 + RFBT / RFBB
)
(4)
Rearranging terms; the ratio of the feedback resistors for a
desired output voltage is:
RFBT / RFBB = (VOUT / 0.795V) - 1
(5)
These resistors should generally be chosen from values in the
range of 1.0 kΩ to 10.0 kΩ.
For VOUT = 0.8V the FB pin can be connected to the output
directly and RFBB can be set to 8.06kΩ to provide minimum
output load.
A table of values for RFBT , and RFBB, is included in the sim-
plified applications schematic on page 2.
30153980
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp
to its steady state operating point after being enabled, thereby
reducing current inrush from the input supply and slowing the
output voltage rise-time.
FIGURE 2. Tracking option input detail
COUT SELECTION
None of the required COUT output capacitance is contained
within the module. A minimum value ranging from 330 μF for
6VOUT to 660 μF for 1.2VOUT applications is required based
on the values of internal compensation in the error amplifier.
These minimum values can be decreased if the effective ca-
pacitor ESR is higher than 15 mOhms.
Upon turn-on, after all UVLO conditions have been passed,
an internal 1.6msec circuit slowly ramps the SS input to im-
plement internal soft start. If 1.6 msec is an adequate turn–on
time then the Css capacitor can be left unpopulated. Longer
soft-start periods are achieved by adding an external capac-
itor to this input.
A Low ESR (15 mOhm) tantalum, organic semiconductor or
specialty polymer capacitor types in parallel with a 47nF X7R
ceramic capacitor for high frequency noise reduction is rec-
ommended for obtaining lowest ripple. The output capacitor
COUT may consist of several capacitors in parallel placed in
close proximity to the module. The output voltage ripple of the
module depends on the equivalent series resistance (ESR) of
the capacitor bank, and can be calculated by multiplying the
ripple current of the module by the effective impedance of
your chosen output capacitors (for ripple current calculation,
see equation 18). Electrolytic capacitors will have large ESR
and lead to larger output ripple than ceramic or polymer types.
For this reason a combination of ceramic and polymer ca-
pacitors is recommended for low output ripple performance.
Soft start duration is given by the formula:
tSS = VREF * CSS / Iss = 0.795V * CSS / 50uA
This equation can be rearranged as follows:
CSS = tSS * 50μA / 0.795V
(6)
(7)
Using a 0.22μF capacitor results in 3.5 msec typical soft-start
duration; and 0.47μF results in 7.5 msec typical. 0.47 μF is a
recommended initial value.
As the soft-start input exceeds 0.795V the output of the power
stage will be in regulation and the 50 μA current is deactivat-
ed. Note that the following conditions will reset the soft-start
capacitor by discharging the SS input to ground with an in-
ternal current sink.
The output capacitor assembly must also meet the worst case
ripple current rating of ΔiL, as calculated in equation (18) be-
low. Loop response verification is also valuable to confirm
closed loop behavior.
• The Enable input being pulled low
• A thermal shutdown condition
• VIN falling below 4.3V (TYP) and triggering the VCC UVLO
For applications with dynamic load steps; the following equa-
tion provides a good first pass approximation of COUT for load
transient requirements.
TRACKING SUPPLY DIVIDER OPTION
The tracking function allows the module to be connected as
a slave supply to a primary voltage rail (often the 3.3V system
rail) where the slave module output voltage is lower than that
of the master. Proper configuration allows the slave rail to
power up coincident with the master rail such that the voltage
difference between the rails during ramp-up is small (i.e.
<0.15V typ). The values for the tracking resistive divider
should be selected such that the effect of the internal 50uA
current source is minimized. In most cases the ratio of the
tracking divider resistors is the same as the ratio of the output
voltage setting divider. Proper operation in tracking mode dic-
tates the soft-start time of the slave rail be shorter than the
master rail; a condition that is easy to satisfy since the CSS
cap is replaced by RTKB. The tracking function is only sup-
ported for the power up interval of the master supply; once
(8)
For 12VIN, 3.3VOUT, a transient voltage of 5% of VOUT
=
0.165V (ΔVOUT), a 7A load step (ISTEP), an output capacitor
effective ESR of 3 mOhms, and a switching frequency of
350kHz (fSW):
(9)
15
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Note that the stability requirement for minimum output capac-
itance must always be met.
For the design case of VIN = 12V, VOUT = 3.3V, IOUT = 8A, and
TA-MAX = 50°C, the module must see a thermal resistance
from case to ambient (θCA) of less than:
One recommended output capacitor combination is two
330μF, 15 mOhm ESR tantalum polymer capacitors connect-
ed in parallel with a 47 uF 6.3V X5R ceramic. This combina-
tion provides excellent performance that may exceed the
requirements of certain applications. Additionally some small
47nF ceramic capacitors can be used for high frequency EMI
suppression.
(13)
Given the typical thermal resistance from junction to case
(θJC) to be 1.0 °C/W. Use the 85°C power dissipation curves
in the Typical Performance Characteristics section to esti-
mate the PIC-LOSS for the application being designed. In this
application it is 3.9W.
CIN SELECTION
The LMZ22008 module contains two internal ceramic input
capacitors. Additional input capacitance is required external
to the module to handle the input ripple current of the appli-
cation. The input capacitor can be several capacitors in par-
allel. This input capacitance should be located in very close
proximity to the module. Input capacitor selection is generally
directed to satisfy the input ripple current requirements rather
than by capacitance value. Input ripple current rating is dic-
tated by the equation:
(14)
To reach θCA = 18.23, the PCB is required to dissipate heat
effectively. With no airflow and no external heat-sink, a good
estimate of the required board area covered by 2 oz. copper
on both the top and bottom metal layers is:
(10)
(15)
where D ≊ VOUT / VIN
(As a point of reference, the worst case ripple current will oc-
cur when the module is presented with full load current and
when VIN = 2 * VOUT).
As a result, approximately 27.42 square cm of 2 oz copper on
top and bottom layers is the minimum required area for the
example PCB design. This is 5.23 x 5.23 cm (2.06 x 2.06 in)
square. The PCB copper heat sink must be connected to the
exposed pad. For best performance, use approximately 100,
12mil (305 μm) thermal vias spaced 59 mil (1.5 mm) apart
connect the top copper to the bottom copper.
Recommended minimum input capacitance is 30 uF X7R (or
X5R) ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. It is
also recommended that attention be paid to the voltage and
temperature derating of the capacitor selected. It should be
noted that ripple current rating of ceramic capacitors may be
missing from the capacitor data sheet and you may have to
contact the capacitor manufacturer for this parameter.
Another way to estimate the temperature rise of a design is
using θJA. An estimate of θJA for varying heat sinking copper
areas and airflows can be found in the typical applications
curves. If our design required the same operating conditions
as before but had 225 LFPM of airflow. We locate the required
θ
JA of
If the system design requires a certain minimum value of
peak-to-peak input ripple voltage (ΔVIN) to be maintained then
the following equation may be used.
(11)
(16)
If ΔVIN is 200 mV or 1.66% of VIN for a 12V input to 3.3V output
application and fSW = 350 kHz then:
On the Theta JA vs copper heatsinking curve, the copper area
required for this application is now only 1 square inches. The
airflow reduced the required heat sinking area by a factor of
four.
To reduce the heat sinking copper area further, this package
is compatable with D3-PAK surface mount heat sinks.
(12)
Additional bulk capacitance with higher ESR may be required
to damp any resonant effects of the input capacitance and
parasitic inductance of the incoming supply lines. The
LMZ22008 typical applications schematic and evaluation
board include a 150 μF 50V aluminum capacitor for this func-
tion. There are many situations where this capacitor is not
necessary.
For an example of a high thermal performance PCB layout for
SIMPLE SWITCHER© power modules, refer to AN-2093,
AN-2084, AN-2125, AN-2020 and AN-2026.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
POWER DISSIPATION AND BOARD THERMAL
REQUIREMENTS
When calculating module dissipation use the maximum input
voltage and the average output current for the application.
Many common operating conditions are provided in the char-
acteristic curves such that less common applications can be
derived through interpolation. In all designs, the junction tem-
perature must be kept below the rated maximum of 125°C.
www.national.com
16
mented by following a few simple design rules. A good layout
example is shown in Figure 6
Additional Features
SYNCHRONIZATION INPUT
The PWM switching frequency can be synchronized to an ex-
ternal frequency source. The PWM switching will be in phase
with the external frequency source. If this feature is not used,
connect this input either directly to ground, or connect to
ground through a resistor of 1.5 kΩ ohm or less. The allowed
synchronization frequency range is 314 kHz to 600 kHz. The
typical input threshold is 1.4V. Ideally, the input clock should
overdrive the threshold by a factor of 2, so direct drive from
3.3V logic via a 1.5kΩ or less Thevenin source resistance is
recommended. Note that applying a sustained “logic 1” cor-
responds to zero Hz PWM frequency and will cause the
module to stop switching.
CURRENT SHARING
When a load current higher than 8A is required by the appli-
cation, the LMZ22008 can be configured to share the load
between multiple devices. To share the load current between
the devices, connect the SH pin of all current sharing
LMZ22008 modules. One device should be configured as the
master by connecting FB normally. All other devices should
be configured as slaves by leaving their respective FB pins
floating. The modules should be synchronized by a clock sig-
nal to avoid beat frequencies in the output voltage caused by
small differences in the internal 359 kHz clock. If the modules
are not synchronized, the magnitude of the ripple voltage will
depend on the phase relationship of the internal clocks. The
external synchronizing clocks can be in phase for all modules,
or out of phase to reduce the current stress on the input and
output capacitors. As an example, two modules can be run
180 degrees out of phase, and three modules can be run 120
degrees out of phase. The VIN, VOUT, PGND, and AGND
pins should also be connected with low impedance paths. It
is particularly important to pay close attention to the layout of
AGND and SH, as offsets in grounding or noise picked up
from other devices will be seen as a mismatch in current
sharing and could cause noise issues.
30153981
FIGURE 3. High Current Loops
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout as shown in the
figure above. The high current loops that do not overlap have
high di/dt content that will cause observable high frequency
noise on the output pin if the input capacitor (CIN) is placed at
a distance away from the LMZ22008. Therefore place CIN as
close as possible to the LMZ22008 VIN and PGND exposed
pad. This will minimize the high di/dt area and reduce radiated
EMI. Additionally, grounding for both the input and output ca-
pacitor should consist of a localized top side plane that con-
nects to the PGND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the AGND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Additionally provide a
single point ground connection from pin 4 (AGND) to EP/
PGND.
Current sharing modules can be configured to share the same
set of bulk input and output capacitors, while each having their
own local input and output bypass capacitors. A CIN_BYP >=
30uF is still recommended for each module that is connected
in a current sharing configuration. A COUT_BYP consisting of
47nF X7R ceramic capacitor in parallel with a 22µF ceramic
capacitor is recommended to locally bypass the output volt-
age for each module. These capacitors will provide local
bypassing of high frequency switched currents.
3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB should be located
close to the FB pin. Since the FB node is high impedance,
maintain the copper area as small as possible. The traces
from RFBT, RFBB should be routed away from the body of the
LMZ22008 to minimize possible noise pickup.
In a current sharing system using two or more modules, the
slaves have their error amp circuitry disconnected. The mas-
ter over-rides the error amplifier outputs of the slaves. This
signal is then compared to each module’s individual current
sense circuitry. Due to this, the current sense gain of the entire
system increases according to the number of modules slaved
to the master. To compensate for this and ensure good sta-
bility, the total output capacitance has to be increased. For
example, two modules configured to provide 1.2VOUT and 16
amps have a required total bulk output capacitance of
COUT_BULK = 2 x 450µF (ESR 25mOhms). This is a thirty six
percent increase in the required output capacitance of a stand
alone module. Up to 6 modules can be connected in parallel
for loads up to 48A. For more information on current sharing
refer to AN-2093 (Current sharing evaluation board).
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
multiple copper layers, these thermal vias can also be con-
nected to inner layer heat-spreading ground planes. For best
results use a 10 x 10 via array or larger with a minimum via
diameter of 12mil (305 μm) thermal vias spaced 46.8mil (1.5
mm). Ensure enough copper area is used for heat-sinking to
keep the junction temperature below 125°C.
17
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30153982
FIGURE 4. Current Sharing Example Schematic
Output voltage ripple of two modules with
synchronization clocks in phase
OUTPUT OVER-VOLTAGE PROTECTION
If the voltage at FB is greater than a 0.86V internal reference,
the output of the error amplifier is pulled toward ground, caus-
ing VOUT to fall.
CURRENT LIMIT
The LMZ22008 is protected by both low side (LS) and high
side (HS) current limit circuitry. The LS current limit detection
is carried out during the off-time by monitoring the current
through the LS synchronous MOSFET. Referring to the Func-
tional Block Diagram, when the top MOSFET is turned off, the
inductor current flows through the load, the PGND pin and the
internal synchronous MOSFET. If this current exceeds 13A
(typical) the current limit comparator disables the start of the
next switching period. Switching cycles are prohibited until
current drops below the limit. It should also be noted that d.c.
current limit is dependent on duty cycle as illustrated in the
graph in the typical performance section. The HS current limit
monitors the current of top side MOSFET. Once HS current
limit is detected (16A typical) , the HS MOSFET is shutoff im-
mediately, until the next cycle. Exceeding HS current limit
causes VOUT to fall. Typical behavior of exceeding LS current
limit is that fSW drops to 1/2 of the operating frequency.
30153983
Output voltage ripple of two modules with
synchronization clocks 180 degrees out of phase
THERMAL PROTECTION
The junction temperature of the LMZ22008 should not be al-
lowed to exceed its maximum ratings. Thermal protection is
implemented by an internal Thermal Shutdown circuit which
activates at 165 °C (typ) causing the device to enter a low
power standby state. In this state the main MOSFET remains
off causing VOUT to fall, and additionally the CSS capacitor is
discharged to ground. Thermal protection helps prevent
catastrophic failures for accidental device overheating. When
the junction temperature falls back below 150 °C (typ Hyst =
30153984
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18
15°C) the SS pin is released, VOUT rises smoothly, and normal
operation resumes.
In CCM, current flows through the inductor through the entire
switching cycle and never falls to zero during the off-time.
Applications requiring maximum output current especially
those at high input voltage may require additional derating at
elevated temperatures.
Following is a comparison pair of waveforms showing both
the CCM (upper) and DCM operating modes.
CCM and DCM Operating Modes
VIN = 12V, VO = 3.3V, IO = 3A/0.3A
PRE-BIASED STARTUP
The LMZ22008 will properly start up into a pre-biased output.
This startup situation is common in multiple rail logic applica-
tions where current paths may exist between different power
rails during the startup sequence. The following scope cap-
ture shows proper behavior in this mode. Trace one is Enable
going high. Trace two is 1.8V pre-bias rising to 3.3V. Trace
three is the SS voltage with a CSS= 0.47uF. Risetime deter-
mined by CSS
.
Pre-Biased Startup
30153986
The approximate formula for determining the DCM/CCM
boundary is as follows:
(17)
The inductor internal to the module is 2.2 μH. This value was
chosen as a good balance between low and high input voltage
applications. The main parameter affected by the inductor is
the amplitude of the inductor ripple current (ΔiL). ΔiL can be
calculated with:
30153985
DISCONTINUOUS CONDUCTION AND CONTINUOUS
CONDUCTION MODES
At light load the regulator will operate in discontinuous con-
duction mode (DCM). With load currents above the critical
conduction point, it will operate in continuous conduction
mode (CCM). When operating in DCM, inductor current is
maintained to an average value equaling Iout . In DCM the
low-side switch will turn off when the inductor current falls to
zero, this causes the inductor current to resonate. Although it
is in DCM, the current is allowed to go slightly negative to
charge the bootstrap capacitor.
(18)
Where VIN is the maximum input voltage and fSW is typically
359 kHz.
If the output current IOUT is determined by assuming that
IOUT = IL, the higher and lower peak of ΔiL can be determined.
19
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Typical Application Schematic Diagram and BOM
30153987
FIGURE 5.
Typical Application Bill of Materials — Table 1
Ref Des
U1
Description
Case Size
TO-PMOD-11
1206
Manufacturer
National Semiconductor
Yageo America
Taiyo Yuden
Panasonic
Manufacturer P/N
SIMPLE SWITCHER ®
0.047 µF, 50V, X7R
10 µF, 50V, X7R
LMZ22008TZ
CC1206KRX7R9BB473
UMK325BJ106MM-T
EEE-FK1H151P
CIN1,6 (OPT)
CIN2,3,4
CIN5 (OPT)
CO1,5 (OPT)
CO2 (OPT)
CO3,4
1210
CAP, AL, 150µF, 50V
0.047 µF, 50V, X7R
47 µF, 10V, X7R
Radial G
1206
Yageo America
Murata
CC1206KRX7R9BB473
GRM32ER61A476KE20L
T520D337M006ATE015
ERJ-6ENF3321V
1210
CAPSMT_6_UE
0805
Kemet
330 μF, 6.3V, 0.015 ohm
3.32 kΩ
RFBT
Panasonic
RFBB
0805
Panasonic
ERJ-6ENF1071V
1.07 kΩ
RSYNC
0805
Vishay Dale
Panasonic
CRCW08051K50FKEA
ERJ-6ENF4222V
1.50 kΩ
RENT
0805
42.2 kΩ
RENB
0805
Panasonic
ERJ-6ENF1272V
12.7 kΩ
CSS
0805
AVX
0805YC474KAT2A
MMSZ5231BS-7-F
0.47 μF, ±10%, X7R, 16V
5.1V, 0.5W
D1 (OPT)
SOD-123
Diodes Inc.
www.national.com
20
30153988
30153989
FIGURE 6. Layout example
21
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22
Physical Dimensions inches (millimeters) unless otherwise noted
11-Lead TZA Package
NS Package Number TZA11A
23
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相关型号：
TO-PMOD-7
1A SIMPLE SWITCHER® Power Module with 20V Maximum Input Voltage for Military and Rugged Applications
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