TP13057ADW [TI]
MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER; 整体式串行接口联合PCM编解码器和过滤器
| 型号： | TP13057ADW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 文件： | 总17页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass
Filtering
µ-Law . . . TP3054A and TP13054A
A-Law . . . TP3057A and TP13057A
±5-V Operation
Low Operating Power . . . 50 mW Typ
Power-Down Standby Mode . . . 3 mW Typ
Automatic Power Down
– Receive Low-Pass Filter With (sin x)/x
Correction
– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and
Decoder
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density
– Internal Precision Voltage Reference
– Serial I/O Interface
Improved Versions of National
Semiconductor TP3054, TP3057, TP3054-X,
TP3057-X
– Internal Autozero Circuitry
description
DW OR N PACKAGE
(TOP VIEW)
The TP3054A, TP3057A, TP13054A, and
TP13057A are comprised of a single-chip PCM
codec (pulse code-modulated encoder and
decoder) and PCM line filter. These devices
provide all the functions required to interface a
full-duplex (2-wire) voice telephone circuit with a
TDM (time-division-multiplexed) system. These
devices are pin-for-pin compatible with the
National Semiconductor TP3054A and TP3057A,
respectively. Primary applications include:
VFXI+
VFXI–
GSX
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BB
ANLG GND
VFRO
TSX
V
CC
FSX
DX
FSR
DR
BCLKX
MCLKX
BCLKR/CLKSEL
MCLKR/PDN
•
Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems
•
•
•
•
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3054A, TP3057A, TP13054A, and TP13057A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3057A and
TP13057A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below –55 dBm0.
The TP3054A and TP3057A are characterized for operation from 0°C to 70°C. The TP13054A and TP13057A
are characterized for operation from –40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
functional block diagram
14
GSX
Autozero
Logic
R2
Analog
Input
R1
15
VFXI–
VFXI+
–
+
Switched-
Capacitor
Band-Pass Filter
RC
Active Filter
S/H
DAC
16
A/D
Control
Logic
Voltage
Reference
Transmit
Regulator
11
DX
OE
Comparator
Switched-
Capacitor
Low-Pass Filter
3
Receive
Regulator
RC Active
Filter
S/H
DAC
VFRO
6
DR
Power
Amplifier
CLK
13
Timing and Control
TSX
5 V
–5 V
9
8
10
7
5
12
4
1
2
MCLKX MCLKR/ BCLKX BCLKR/ FSR FSX
V
CC
V
BB
ANLG GND
PDN
CLKSEL
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
2
ANLG GND
Analog ground. All signals are referenced to ANLG GND.
BCLKR/CLKSEL
7
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in
the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1).
BCLKX
10 The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with
MCLKX.
DR
6
Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX
11 The 3-state PCM data output that is enabled by FSX.
FSR
5
Receive-frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
FSX
12 Transmit-frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
14 Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN
8
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should
be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected
for all internal timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX
TSX
9
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
13 Open-drain output that pulses low during the encoder time slot
V
V
1
4
3
Negative power supply. V
= –5 V ±5%
= 5 V ±5%
BB
BB
Positive power supply. V
CC
CC
VFRO
VFXI+
VFXI–
Analog output of the receive filter
16 Noninverting input of the transmit input amplifier
15 Inverting input of the transmit input amplifier
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
BB
Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
+0.3 V to V –0.3 V
CC
BB
Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . V
+0.3 V to ANLG GND –0.3 V
CC
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range: TP3054A, TP3057A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TP13054A, TP13057A . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
≤ 25°C
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DW
N
1025 mW
8.2 mW/°C
9.2 mW/°C
656 mW
736 mW
533 mW
598 mW
1150 mW
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
Supply voltage, V
Supply voltage, V
4.75
–4.75
2.2
5
5.25
CC
BB
–5 –5.25
V
High-level input voltage, V
V
IH
Low-level input voltage, V
IL
Common-mode input voltage range, V
0.6
V
‡
±2.5
V
ICR
Load resistance, GSX, R
10
kΩ
pF
L
Load capacitance, GSX, C
50
70
85
L
TP3054A, TP3057A
0
Operating free-air temperature, T
°C
A
TP13054A, TP13057A
–40
‡
Measured with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
electrical characteristics over recommended ranges of supply voltage operating free-air
temperature range (unless otherwise noted)
supply current
TP305xA
TP1305xA
PARAMETER
TEST CONDITIONS
No load
UNIT
mA
‡
‡
MIN TYP
MAX
MIN TYP
MAX
1.2
10
Power down
Active
0.5
6
1
9
1
9
0.5
6
I
I
Supply current from V
CC
CC
BB
Power down
Active
0.5
6
0.5
6
1.2
10
Supply current from V
No load
mA
BB
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
electrical characteristics at V
otherwise noted)
= 5 V ±5%, V
= –5 V ±5%, GND at 0 V, T = 25°C (unless
CC
BB A
digital interface
PARAMETER
High-level output voltage
TEST CONDITIONS
= -3.2 mA
MIN
MAX
UNIT
V
V
DX
I
H
I
L
I
L
2.4
V
OH
DX
= 3.2 mA
0.4
0.4
Low-level output voltage
V
OL
TSX
= 3.2 mA, Drain open
I
I
I
High-level input current
V = V to V
IH CC
±10
±10
±10
µA
µA
µA
IH
I
Low-level input current
All digital inputs
DX
V = GND to V
I
IL
IL
= GND to V
CC
Output current in high-impedance state
V
O
OZ
analog interface with transmit amplifier input
†
PARAMETER
TEST CONDITIONS
V = –2.5 V to 2.5 V
MIN TYP
MAX
UNIT
nA
MΩ
Ω
I
Input current
VFXI+ or VFXI –
VFXI+ or VFXI –
±200
I
I
r
Input resistance
V = –2.5 V to 2.5 V
I
10
i
r
Output resistance
Closed loop, Unity gain
1
2
3
o
Output dynamic range
Open-loop voltage amplification
Unity-gain bandwidth
Input offset voltage
GSX
R
≥ 10 kΩ
±2.8
V
L
A
VFXI+ to GSX
GSX
5000
1
V
B
MHz
mV
dB
I
V
VFXI+ or VFXI –
±20
IO
CMRR Common-mode rejection ratio
Supply-voltage rejection ratio
All typical values are at V = 5 V, V
60
60
K
dB
SVR
†
= –5 V, and T = 25°C.
CC
BB
A
analog interface with receive filter
PARAMETER
†
TEST CONDITIONS
MIN TYP
MAX
UNIT
Ω
Output resistance
VFRO
1
3
Load resistance
VFRO = ±2.5 V
600
Ω
Load capacitance
VFRO to GND
VFRO to GND
500
pF
Output dc offset voltage
†
±200
mV
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
timing requirements
†
PARAMETER
TEST CONDITIONS
MCLKX and Depends on the device used and
MIN TYP
MAX
UNIT
1.536
1.544
2.048
f
Frequency of master clock
MHz
clock(M)
MCLKR
BCLKX/CLKSEL
f
t
t
Frequency of bit clock, transmit
BCLKX
64
160
160
2048
kHz
ns
clock(B)
Pulse duration, MCLKX and MCLKR high
Pulse duration, MCLKX and MCLKR low
w1
ns
w2
MCLKX and
MCLKR
t
t
Rise time of master clock
Fall time of master clock
50
50
ns
ns
r1
f1
Measured from 20% to 80%
Measured from 20% to 80%
MCLKX and
MCLKR
t
t
Rise time of bit clock, transmit
Fall time of bit clock, transmit
BCLKX
BCLKX
50
50
ns
ns
r2
f2
Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKX↓
First bit clock after the leading
edge of FSX
t
100
ns
su1
t
t
Pulse duration, BCLKX and BCLKR high
Pulse duration, BCLKX and BCLKR low
V
= 2.2 V
= 0.6 V
160
160
ns
ns
w3
IH
IL
V
w4
Hold time, frame sync low after bit clock low
(long frame only)
t
t
t
0
0
ns
ns
ns
h1
Hold time, BCLKX high after frame sync↑
(short frame only)
h2
Setup time, frame sync high before bit clock↓
(long frame only)
80
0
su2
‡
‡
t
t
Delay time, BCLKX high to data valid
Delay time, BCLKX high to TSX low
140
140
ns
ns
Load = 150 pF plus 2 LSTTL loads
Load = 150 pF plus 2 LSTTL loads
d1
d2
Delay time, BCLKX (or 8 clock FSX in long frame only)
low to data output disabled
t
t
50
20
165
165
ns
ns
d3
Delay time, FSX or BCLKX high to data valid (long
frame only)
C
= 0 pF to 150 pF
d4
L
t
t
Setup time, DR valid before BCLKR↓
50
50
ns
ns
su3
Hold time, DR valid after BCLKR or BCLKX↓
h3
Setup time, FSR or FSX high before BCLKR or
BCLKR↓
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
t
t
t
t
50
100
100
160
ns
ns
ns
ns
su4
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
Hold time, FSX or FSR high after BCLKX or BCLKR↓
Hold time, frame sync high after bit clock↓
h4
Long-frame sync pulse
(from 3 to 8 bit clock periods long)
h5
Minimum pulse duration of the frame sync pulse
(low level)
64 kbps operating mode
w5
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
Nominal input value for an LSTTL load is 18 kΩ.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
operating characteristics, over operating free-air temperature range, V
= 5 V ±5%,
CC
V
= –5 V ±5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
BB
I
gain, noninverting (unless otherwise noted)
filter gains and tracking errors
‡
†
PARAMETER
TEST CONDITIONS
TP3054A, TP13054A 3.17 dBm0
MIN TYP
MAX
UNIT
V
2.501
2.492
Maximum peak transmit overload level
Transmit filter gain, absolute (at 0 dBm0)
TP3057A, TP13057A 3.14 dBm0
= 25°C
T
A
– 0.15
0.15
–40
–30
–26
–0.1
0.15
0.05
0
dB
f = 16 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
–1.8
–0.15
–0.35
–0.8
f = 300 Hz to 3000 Hz
f = 3300 Hz
f = 3400 Hz
f = 4000 Hz
Transmit filter gain, relative to absolute
dB
–14
f ≥ 4600 Hz (measure response from
0 Hz to 4000 Hz)
–32
0.1
Absolute transmit gain variation with temperature and supply
voltage
Relative to absolute transmit gain
–0.1
dB
dB
Sinusoidal test method,
Reference level = –10 dBm0
3 dBm0 ≥ input level ≥ –40 dBm0
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
Input is digital code sequence for
±0.2
±0.4
±0.8
Transmit gain tracking error with level
Receive filter gain, absolute (at 0 dBm0)
Receive filter gain, relative to absolute
–0.15
0.15
dB
dB
dB
0-dBm0 signal,
T
= 25°C
A
f = 0 H to 3000 Hz,
z
T
A
= 25°c
–0.15
–0.35
–0.8
0.15
0.05
0
f = 3300 Hz
f = 3400 Hz
f = 4000 Hz
–14
Absolute receive gain variation with temperature and supply
voltage
T
A
= full range,
See Note 4
–0.1
0.1
Sinusoidal test method; reference
input PCM code corresponds to an
ideally encoded –10 dBm0 signal
Receive gain tracking error with level
Receive output drive voltage
3 dBm0 ≥ input level ≥ –40 dBm0
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
±0.2
±0.4
±0.8
±2.5
R
= 10 kΩ
V
L
Pseudo-noise test method; reference
input PCM code corresponds to an
ideally encoded –10 dBm0 signal
Transmit and receive gain tracking error with level (A-law,
CCITT C 712)
dB
3 dBm0 ≥ input level ≥ –40 dBm0
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
±0.25
±0.3
±0.45
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
A
CC
BB
Absolute rms signal levels are defined as follows: V = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with R = 600 Ω.
I
L
NOTE 4: Full range for the TP3054A and TP3057A is 0°C to 70°C. Full range for the TP13054A and TP13057A is –40°C to 85°C.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
envelope delay distortion with frequency
PARAMETER
†
TEST CONDITIONS
f = 1600 Hz
MIN TYP
MAX
315
220
145
75
UNIT
Transmit delay, absolute (at 0 dBm0)
290
195
120
50
µs
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
Transmit delay, relative to absolute
20
40
µs
55
75
80
105
155
200
130
180
–25
–20
70
Receive delay, absolute (at 0 dBm0)
Receive delay, relative to absolute
µs
µs
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
–40
–30
90
125
175
100
140
noise
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
TP3054A,
Transmit noise, C-message weighted
TP13054A
VFXI = 0 V
VFXI = 0 V
9
14 dBrnC0
–75 dBm0p
Transmit noise, psophometric weighted
(see Note 5)
TP3057A,
TP13057A
–78
2
TP3054A, PCM code equals alternating positive
TP13054A and negative zero
Receive noise, C-message weighted
Receive noise, psophometric weighted
Noise, single frequency
4
dBrnC0
TP3057A,
PCM code equals positive zero
TP13057A
–86
–83 dBm0p
–53 dBm0
VFXI+ = 0 V,
Loop-around measurement
f = 0 kHz to 100 kHz,
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite signals on the transmit side are below –55 dBm0.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
power supply rejection
PARAMETER
TEST CONDITIONS
f = 0 Hz to 4 kHz
= 5 V + 100 mVrms,
MIN
38
38
40
35
35
40
40
40
40
38
38
40
MAX
UNIT
A-law
dB
V
CC
VFXI+ = –50 dBm0
†
†
†
†
Positive power-supply rejection, transmit
Negative power-supply rejection, transmit
Positive power-supply rejection, receive
Negative power-supply rejection, receive
µ-law
dBC
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
dB
A-law
dB
V
BB
= –5 V + 100 mVrms,
VFXI+ = –50 dBm0
µ-law
dBC
dB
A-law
dB
PCM code equals positive zero,
µ-law
dBC
dB
V
CC
= 5 V + 100 mVrms
A-law
dB
PCM code equals positive zero,
= –5 V + 100 mVrms
µ-law
dBC
dB
V
BB
0 dBm0, 300-Hz to 3400-Hz input applied to DR (measure individual
image signals at VFRO)
–30
dB
Spurious out-of-band signals at the
channel output (VFRO)
f = 4600 Hz to 7600 Hz
f = 7600 Hz to 8400 Hz
f = 8400 Hz to 100kHz
–33
–40
–40
dB
distortion
PARAMETER
TEST CONDITIONS
Level = 3 dBm0
MIN
33
36
29
30
14
15
MAX
UNIT
Level = 0 dBm0 to -30 dBm0
Transmit
†
dBC
‡
Level = –40 dBm0
Level = –55 dBm0
Signal-to-distortion ratio, transmit or receive half-channel
Receive
Transmit
Receive
Single-frequency distortion products, transmit
Single-frequency distortion products, receive
–46
–46
dB
dB
Loop-around measurement,
Intermodulation distortion
VFXI+ = –4 dBm0 to –21 dBm0,
–41
dB
Two frequencies in the range of 300 Hz to 3400 Hz
Level = –3 dBm0
33
36
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
Signal-to-distortion ratio, transmit half-channel (A-law)
(CCITT G.714)
33.5
28.5
13.5
33
dB
§
Level = –40 dBm0
Level = –55 dBm0
Level = –3 dBm0
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
36
Signal-to-distortion ratio, receive half-channel (A-law)
(CCITT G.714)
34.2
30
dB
§
Level = –40 dBm0
Level = –55 dBm0
15
†
‡
§
The unit dBC applies to C-message weighting.
Sinusoidal test method (see Note 6)
Pseudo-noise test method
NOTE 6: The TP3054A and TP13054A are measured using a C-message weighted filter. The TP3057A and TP13057A are measured using a
psophometric weighted filter.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
crosstalk
†
PARAMETER
TEST CONDITIONS
f = 300 Hz to 3000 Hz, DR at steady PCM code
VFXI = 0 V, f = 300 Hz to 3000 Hz
= –5 V, and T = 25°C.
MIN TYP
MAX
–75
–75
UNIT
dB
Crosstalk, transmit to receive
–90
–90
Crosstalk, receive to transmit (see Note 7)
dB
†
All typical values are at V
= 5 V, V
BB
CC
A
NOTE 7: Receive-to-transmit crosstalk is measured with a – 50 dBm0 activation signal applied at VFXI+.
PARAMETER MEASUREMENT INFORMATION
t
d2
t
d3
TSX
20%
20%
t
r1
t
w2
t
f1
f
clock(M)
MCLKX
MCLKR
80%
80%
80%
20%
20%
t
su1
t
w1
80%
80%
80%
BCLKX
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
80%
80%
FSX
20%
t
t
d3
d1
80%
1
2
3
4
5
6
7
8
DX
20%
80%
20%
80%
BCLKR
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
80%
FSR
20%
t
su3
t
h3
t
h3
1
2
3
4
5
6
7
8
DR
Figure 1. Short-Frame Sync Timing
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
t
w1
f
clock(M)
t
r1
t
t
w2
f1
MCLKX
MCLKR
80%
20%
80%
20%
80%
20%
t
r2
t
t
su1
su1
w3
t
f2
t
t
w4
80%
80%
80%
BCLKX
FSX
20%
1
2
20%
3
20%
4
5
6
7
8
9
t
f
h1
clock(B)
t
t
h5
su2
80%
80%
20%
t
d4
t
d1
t
d4
t
d3
80%
20%
DX
1
2
3
4
5
6
7
8
t
w3
t
d3
t
w4
80%
20%
80%
80%
20%
BCLKR
20%
20%
t
h1
t
su2
t
h5
80%
20%
80%
FSR
DR
t
su3
t
h3
t
h3
1
2
3
4
5
6
7
8
Figure 2. Long-Frame Sync Timing
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
PRINCIPLES OF OPERATION
system reliability and design considerations
TP305xA, TP1305xA system reliability and design considerations are described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP305xA and TP1305xA are heavily protected against latch-up, it is still possible to cause
latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up
can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage
rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied
but before the ground is connected. This can happen if the device is hot-inserted into a card with the power
applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a
system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP305xA- or TP1305xA-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.
device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure that no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply V (most negative voltage).
BB
4. Apply V
(most positive voltage).
CC
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power down condition.
8. Apply FS synchronization pulses.
9. Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
PRINCIPLES OF OPERATION
V
CC
DGND
V
BB
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3054A, TP3057A, TP13054A, and TP13057A devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies
MASTER-CLOCK FREQUENCY SELECTED
BCLKR/CLKSEL
TP13054A, TP3054A
TP13057A, TP3057A
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
The encoding cycle begins with each FSX pulse and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3057A and TP13057A, 1.536 MHz or 1.544 MHz for the TP3054A and TP13054A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, whichever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.
transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per µ-law (TP3054A and TP13054A) or A-law (TP3057A
and TP13057A) coding conventions, the ADC is a companding type. A precision voltage reference provides a
nominal input overload (t
) of nominally 2.5 V peak. The sampling of the filter output is controlled by the FSX
[max]
frame-sync pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a
buffer and shifted out through DX at the next FSX pulse. The total encoding delay is approximately 290 µs. Any
offset voltage due to the filters or comparator is cancelled by sign-bit integration.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
PRINCIPLES OF OPERATION
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is µ-law (TP3054A and TP13054A) or A-law (TP3057A and TP13057A) and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post-filter/power amplifier capable of driving a 600-Ω load to a level of 7.2 dBm. The
receive section is unity gain. At FSR, the data at DR is clocked in on the falling edge of the next eight BCLKR
(BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10 µs later, the decoder
DAC output is updated. The decoder delay is about 10 µs (decoder update) plus 110 µs (filter delay) plus
62.5 µs (1/2 frame), or a total of approximately 180 µs.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
APPLICATION INFORMATION
power supplies
While the pins of the TP1305xA and TP305xA families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. V
and V
CC
BB
supplies should be decoupled by connecting 0.1-µF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to V and V
.
BB
CC
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to V
CC
and V with 10-µF capacitors.
BB
16
15
1
–5 V
V
From SLIC
VFXI+
VFXI–
BB
0.1 µF
2
ANLG GND
R1
R2
14
GSX
0.1 µF
4
3
TP3054A
TP3057A
TP13054A
TP13057A
V
5 V
CC
Analog Interface
To SLIC
VFRO
FSR
5
12
11
FSX
DX
Data
Out
Digital
Interface
6
7
8
Data In
5 V or GND
PDN
DR
10
9
BCLKR/CLKSEL
MCLKR/PDN
BCLKX
MCLKX
BCLKX (2.048 MHz/1.544 MHz)
R1
R2
NOTE A: Transmit gain = 20 log
(
)
R2
,
R1
10 k
R2
Figure 4. Typical Synchronous Application
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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