TP23753 [TI]
IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER; IEEE 802.3-2005 PoE接口和隔离式转换器控制器
| 型号： | TP23753 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER |
| 文件： | 总27页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
IEEE 802.3-2005 PoE INTERFACE AND ISOLATED CONVERTER CONTROLLER
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
Optimized for Isolated Converters
Complete PoE Interface
The TPS23753 is a combined Power over Ethernet
(PoE) powered device (PD) interface and
current-mode dc/dc controller optimized specifically
Adapter ORing Support
12 V Adapter Support
for
isolated
converter
designs.
The
PoE
Programmable Frequency with Synch.
Robust 100 V, 0.7 Ω Hotswap MOSFET
Small TSSOP 14 Package
implementation supports the IEEE 802.3-2005
(previously 802.3af) standard, 12.95 W (13 W) PD.
The TPS23753 supports a number of input-voltage
ORing options including highest voltage, external
adapter preference, and PoE preference.
15 kV / 8 kV System Level ESD Capable
–40°C to 125°C Junction Temperature Range
Design Procedure Application Note - SLVA305
Adapter ORing Application Note - SLVA306
The PoE interface features an external detection
signature pin that can also be used to disable the
internal hotswap MOSFET. This allows the PoE
function to be turned off. Classification can be
programmed to any of the defined types with a single
resistor.
APPLICATIONS
•
•
•
•
IEEE 802.3-2005 Compliant Powered Devices
VoIP Telephones
Access Points
Security Cameras
The dc/dc controller features a bootstrap startup
mechanism with an internal, switched current source.
This provides the advantages of cycling overload fault
protection without the constant power loss of a pull up
resistor.
The programmable oscillator may be synchronized to
a higher-frequency external timing reference.
BR1
T1
CIN
DS
DEN
COUT
DVC
VOUT
VC
RVC
CLS
BR2
M1
VSS
VB
VB
GATE
CS
CTL
ROB
APD
FRS
*
RFBU
DA
RAPD1
RCTL
CCTL
CIZ
*
RFBL
Adapter
CIO
TLV431
are Optional
* Adapter interface and RBLNK
Figure 1. Basic TPS23753 Implementation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
PRODUCT INFORMATION(1)
DEVICE
DUTY CYCLE
POE UVLO ON / HYST.
PACKAGE
MARKING
TPS23753
0 – 80%
35/4.5
PW (TSSOP-14)
TP23753
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Voltags are with respect to VSS (unless otherwise noted)
VALUE
–0.3 to 100
–0.3 to 100
–0.3 to 6.5
–0.3 to 6.5
–0.3 to VB
–0.3 to 19
–0.3 to VC + 0.3
Internally limited
25
UNIT
VDD, VDD1, DEN, RTN(2)
V
V
VDD1 to RTN
CLS(3)
[APD, BLNK(3), CTL, FRS(3), VB(3)] to RTN
V
VI
Input voltage range
V
CS to RTN
VC to RTN
GATE to RTN
VB
V
V
V
Sourcing current
mA
mARMS
kV
V
Average sourcing or sinking current
GATE
HBM
2
ESD rating
CDM
500
ESD – system level (contact/air)(4)
Operating junction temperature range
8/15
kV
–40 to Internally
Limited
TJ
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) IRTN = 0 for VRTN > 80V.
(3) Do not apply voltage to these pins.
(4) Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the
TPS23753EVM-001 (HPA304-001) evaluation module (documentation available on the web). These were the test levels, not the failure
threshold.
DISSIPATION RATINGS
θJT
θJA
θJA
PACKAGE
(°C/W)(1)
(°C/W)(2)
(°C/W)(1)
PW (TSSOP-14)
0.97
173.6
99.3
(1) JEDEC method with high-k board (4 layers, 2 signal and 2 planes).
(2) JEDEC method with low-k board (2 signal layers).
2
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
RECOMMENDED OPERATING CONDITIONS
Voltage with respect to VSS (unless otherwise noted)
MIN
0
NOM
MAX
57
UNIT
V
Input voltage range, VDD, VDD1, RTN
Input voltage range, VDD, VDD1 to RTN
Input voltage range, VC to RTN
Input voltage range, APD, CTL to RTN
Input voltage range, CS to RTN
RTN current (TJ ≤ 125°C)
0
57
V
VI
0
18
V
0
VB
V
0
2
V
350
5
mA
mA
µF
kΩ
ns
°C
VB sourcing current
0
0.08
0
2.5
0.1
VB capacitance
2.2
350
150
125
RBLNK
Synchronization pulse width input (when used)
Operating junction temperature range
25
TJ
–40
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 µF, RDEN
24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C
Controller Section Only
=
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VC
UVLO1
UVLOH
VC rising
Hysteresis(1)
8.65
3.3
9
3.5
9.3
3.7
Undervoltage lockout
Operating current
V
VC = 12 V, CTL = VB
0.40
50
0.58
85
0.85
175
85
mA
ms
VDD1 = 10.2 V, VC(0) = 0 V
VDD1 = 35 V, VC(0) = 0 V
VDD1 = 10.2 V, VVC = 8.6 V
VDD1 = 48 V, VVC = 0 V
tST
Startup time, CVC = 22 µF
30
48
0.44
2.5
1.06
4.3
1.80
6.0
Startup current source - IVC
Voltage
mA
V
VB
6.5 V ≤ VC ≤ 18 V, 0 ≤ IVB ≤ 5 mA
4.75
223
5.10
5.25
273
FRS
CTL= VB, Measure GATE
RFRS = 60.4 kΩ
Switching frequency
248
kHz
DMAX
VSYNC
CTL
Duty cycle
CTL= VB, Measure GATE
Input threshold
76
78.5
2.2
81
%
V
Synchronization
2.0
2.4
VZDC
0% duty cycle threshold
Softstart period
V
CTL ↓ until GATE stops
1.3
400
70
1.5
800
100
1.7
V
Interval from switching start to VCSMAX
µs
kΩ
Input resistance
145
BLNK
In addition to t1
BLNK = RTN
Blanking delay
35
41
52
52
75
63
ns
RBLNK = 49.9 kΩ
CS
VCSMAX
t1
VSLOPE
ISL_EX
Maximum threshold voltage
Turn off delay
VCTL = VB, VCS ↑ until GATE duty cycle drops
VCS = 0.65 V
0.50
25
90
30
2
0.55
41
0.60
60
V
ns
Internal slope compensation voltage
Peak slope compensation current
Bias current (sourcing)
Peak voltage at maximum duty cycle, referred to CS
VCTL = VB, ICS at maximum duty cycle (ac component)
Gate high, dc component of CS current
118
42
142
54
mV
µA
µA
3
4.2
(1) The hysteresis tolerance tracks the rising threshold for a given device.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted: CS = APD = CTL = RTN, GATE open, RFRS = 60.4 kΩ, RBLNK = 249 kΩ, CVB = CVC = 0.1 µF, RDEN
24.9 kΩ, RCLS open, VVDD-VSS = 48 V, VVDD1-RTN = 48 V, 8.5 V ≤ VVC-RTN ≤ 18 V, –40°C ≤ TJ ≤ 125°C
Controller Section Only
=
[VSS = RTN and VDD = VDD1] or [VSS = RTN = VDD], all voltages referred to RTN. Typical specifications are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GATE
Source current
Sink current
VCTL = VB, VC = 12 V, GATE high, Pulsed measurement
VCTL = VB, VC = 12 V, GATE low, Pulsed measurement
0.30
0.50
0.46
0.79
0.60
1.1
A
A
APD
VAPDEN
VAPDH
VAPD
Hysteresis(2)
↑
1.42
0.28
1.5
0.3
1.58
0.32
Threshold voltage
V
THERMAL SHUTDOWN
Turn off temperature
Hysteresis(3)
135
145
20
155
°C
°C
(2) The hysteresis tolerance tracks the rising threshold for a given device.
(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
ELECTRICAL CHARACTERISTICS
PoE and Control
[VDD = VDD1] or [VDD1] = RTN, VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C.
PARAMETER
DEN (DETECTION)
TEST CONDITIONS
MIN TYP MAX UNIT
(VDD = VDD1 = RTN = VSUPPLY positive)
Measure ISUPPLY
VDD = 1.6 V
Detection current
62 64.3
399 406
5.2
66.5
413
12
5
µA
VDD = 10 V
Detection bias current
Hotswap disable threshold
DEN leakage current
VDD = 10 V, DEN open, Measure ISUPPLY
µA
V
VPD_DIS
Ilkg
3
4
VDEN = VDD = 57 V, Float VDD1 and RTN, Measure IDEN
(VDD = VDD1 = RTN = VSUPPLY positive)
13 V ≤ VDD ≤ 21 V, Measure ISUPPLY
RCLS = 1270 Ω
0.1
5
µA
CLS (CLASSIFICATION)
1.8 2.14
9.9 10.6
17.6 18.6
26.5 27.9
38 39.9
2.4
11.3
19.4
29.3
42
RCLS = 243 Ω
ICLS
Classification current
mA
RCLS = 137 Ω
RCLS = 90.9 Ω
RCLS = 63.4 Ω
VCL_ON
VCL_HYS
VCU_OFF
VCU_HYS
Ilkg
Regulator turns on, VDD rising
Hysteresis(1)
10 11.7
13
Classification regulator lower
threshold
V
1.9 2.05
2.2
23
Regulator turns off, VDD rising
Hysteresis(1)
21
22
Classification regulator upper
threshold
V
0.5 0.77
1
Leakage current
VDD = 57 V, VCLS = 0 V, DEN = VSS, Measure ICLS
(VDD1 = RTN)
1
µA
RTN (PASS DEVICE)
On resistance
0.7
405 450
100 140
11 12.3
1.2
Ω
Current limit
VRTN = 1.5 V, VDD = 48 V, Pulsed Measurement
VRTN = 2 V, VDD: 0 V → 48 V, Pulsed Measurement
VDD rising
505 mA
180 mA
Inrush limit
Foldback voltage threshold
Leakage current
13.6
40
V
Ilkg
VDD = VRTN = 100 V, DEN = VSS
µA
UVLO
UVLO_R
UVLO_H
VDD rising
33.9
35
36.1
4.70
Undervoltage lockout threshold
V
(1)
Hysteresis
4.40 4.55
(1) The hysteresis tolerance tracks the rising threshold for a given device.
4
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS (continued)
PoE and Control
[VDD = VDD1] or [VDD1] = RTN, VVC-RTN = 0 V, all voltages referred to VSS. Typical specifications are at 25°C.
PARAMETER
THERMAL SHUTDOWN
TEST CONDITIONS
MIN TYP MAX UNIT
Turn off temperature
Hysteresis(2)
135 145
20
155
°C
°C
(2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
DEVICE INFORMATION
TOP VIEW
CTL
14
13
12
11
10
9
FRS
BLNK
APD
CLS
1
2
3
4
5
6
7
V
B
CS
V
C
GATE
RTN
DEN
V
DD
V
8
SS
V
DD1
Table 1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NO.
NAME
1
CTL
I
The control loop input to the PWM (pulse width modulator). Use VB as a pull up for CTL.
5 V bias rail for dc/dc control circuits. Apply a 0.1 µF to RTN. VB may be used to bias an external
optocoupler for feedback.
2
VB
O
Dc/dc converter switching MOSFET current sense input. Connect CS to the high side of the
RTN-referenced current sense resistor.
3
4
CS
I
Dc/dc converter bias voltage. The internal startup current source and converter bias winding output
power this pin. Connect a 0.22 µF minimum ceramic capacitor to RTN, and a larger capacitor to
facilitate startup.
VC
I/O
O
5
6
7
8
9
GATE
RTN
VSS
Gate drive output for the dc/dc converter switching MOSFET.
RTN is the negative rail input to the dc/dc converter and output of the PoE hotswap.
Negative power rail derived from the PoE source.
VDD1
VDD
Source of dc/dc converter startup current. Connect to VDD for most applications.
Positive input power rail for PoE interface circuit. Derived from the PoE source.
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this pin
to VSS during powered operation causes the internal hotswap MOSFET to turn off.
10
11
12
DEN
CLS
APD
I/O
O
I
Connect a resistor from CLS to VSS to program the classification current per Table 2.
Pull APD above 1.5 V to disable the internal PD hotswap switch, forcing power to come from an
external adapter. Connect to the adapter through a resistor divider.
Connect to RTN to utilize the internally set blanking period or connect through a resistor to RTN to
program the blanking period.
13
14
BLNK
FRS
I/O
I/O
Connect a resistor from FRS to RTN to program the converter switching frequency.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
V
V
C
DD1
Oscillator
FRS
CTL
enb
CONV.
OFF
Control
800ms
Soft Start
50kW
50kW
enb
-
-
+
GATE
1
D
CK
Q
+
0.75V enb
CLRB
40mA
(pk)
RTN
Blank
Switch
Matrix
Converter
Thermal
Monitor
2.875kW
V
B
Regulator
Reference
CS
+
0.55V
-
RTN
1.5V
&1.2V
BLNK
APDb
2.53V
APD
CLS
V
DD
11.5V &
9.5V
Class
Regulator
AUXb
22V &
21.25V
VSS
DEN
12.5V
& 1V
400ms
Common
Circuits and
PoE Thermal
Monitor
S
R
Q
CONV.
OFF
1
0
ILIMb
H
L
+
-
35V &
30.5V
EN
V
RTN
SS
80mW
4.5V
AUXb
APDb
Figure 2. TPS23753 Functional Block Diagram
Pin Description
Refer to Figure 1 for component reference designators (RCS for example ), and the Electrical Characteristics table
for values denoted by reference (VCSMAX for example). Electrical Characteristic values take precedence over any
numerical values used in the following sections.
APD
APD forces power to come from an external adapter connected from VDD1 to RTN by opening the hotswap
switch. A resistor divider is recommended on APD when it is connected to an external adapter. The divider
provides ESD protection, leakage discharge for the adapter ORing diode, and input voltage qualification. Voltage
qualification assures the adapter can support the PD before the PoE current is cut off.
Select the APD divider resistors per the following equations where VADPTR-ON is the desired adapter voltage that
enables the APD function as adapter voltage rises.
6
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
R
= R
⋅ V
(
APD1 + R
−V
V
APDEN
)
APD1
APD2
ADPTR _ ON
APDEN
(1)
(2)
R
APD2
V
=
⋅ V
(
−V
)
ADPTR _ OFF
APDEN APDH
R
APD2
The CLS output is disabled when a voltage above VAPDEN is applied to the APD pin.
Place the APD pull-down resistor adjacent to the APD pin.
APD should be tied to RTN when not used.
BLNK
Blanking provides an interval between the gate drive going high and the current comparator on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparator is active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to RTN to obtain the internally set blanking period. Connect a resistor from BLNK to RTN for a
programmable blanking period. The relationship between the desired blanking period and the programming
resistor is defined by the following equation.
R
kΩ = t
( )
ns
BLNK
( )
BLNK
(3)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
Connect a resistor from CLS to VSS to program the classification current per IEEE 802.3-2005 and preliminary
802.3at specifications. The PD power ranges and corresponding resistor values are listed in Table 2. The power
assigned should correspond to the maximum average power drawn by the PD during operation. The TPS23753
supports class 0 – 3 power levels.
CS
The current sense input for the dc/dc converter should be connected to the high side of the switching MOSFET’s
current sense resistor. The current-limit threshold, VCSMAX, defines the voltage on CS above which the GATE ON
time will be terminated regardless of the voltage on CTL.
The TPS23753 provides internal slope compensation to stabilize the current mode control loop. If the provided
slope is not sufficient, the effective slope may be increased by addition of RS per Figure 22.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling VCTL below VZDC causes GATE
to stop switching. Increasing VCTL above VZDC raises the switching MOSFET programmed peak current. The
maximum (peak) current is requested at approximately VZDC + (2 × VCSMAX). The ac gain from CTL to the PWM
comparator is 0.5.
Use VB as a pull up source for CTL.
DEN
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. DEN goes to a high
impedance state when not in the detection voltage range. Pulling DEN to VSS during powered operation causes
the internal hotswap MOSFET and class regulator to turn off.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
FRS
Connect a resistor from FRS to RTN to program the converter switching frequency. Select the resistor per the
following relationship.
15000
R
(kΩ) =
FRS
f
(kHz)
SW
(4)
The converter may be synchronized to a frequency above its maximum free-running frequency by applying short
ac-coupled pulses into the FRS pin. More information is provided in the Applications section.
The FRS pin is high impedance. Keep the connections short and apart from potential noise sources.
GATE
Gate drive output for the dc/dc converter switching MOSFET.
RTN
RTN is internally connected to the drain of the PoE hotswap MOSFET, and the dc/dc controller return. RTN
should be treated as a local reference plane (ground plane) for the dc/dc controller and converter primary to
maintain signal integrity.
VB
VB is an internal 5V control rail that should be bypassed by a 0.1 µF capacitor to RTN. VB should be used to bias
the feedback optocoupler.
VC
VC is the bias supply for the dc/dc controller. The MOSFET gate driver runs directly from VC. VB is regulated
down from VC, and is the bias voltage for the rest of the converter control. A startup current source from VDD1 to
VC is controlled by a comparator with hysteresis to implement a bootstrap startup of the converter. VC must be
connected to a bias source, such as a converter auxiliary output, during normal operation.
A minimum 0.22 µF capacitor, located adjacent to the VC pin, should be connected from VC to RTN to bypass the
gate driver. A larger total capacitance is required for startup.
VDD
Positive input power rail for PoE control that is derived from the PoE. VDD should be bypassed to VSS with a 0.1
µF (X7R,10%) capacitor as required by the standard. A transient suppressor (Zener) diode, should be connected
from VDD to VSS to protect against overvoltage transients.
VDD1
Source of dc/dc converter startup current. Connect to VDD for most applications. VDD1 may be isolated by a diode
from VDD to support PoE priority operation.
VSS
VSS is the PoE input-power return side. It is the reference for the PoE interface circuits, and has a current-limited
hotswap switch that connects it to RTN. VSS is clamped to a diode drop above RTN by the hotswap switch. A
local VSS reference plane should be used to connect the input components and the VSS pin.
8
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
TYPICAL CHARACTERISTICS
DETECTION BIAS CURRENT
PoE CURRENT LIMIT
vs
TEMPERATURE
vs
VOLTAGE
458
456
8
7
6
5
4
3
2
TJ = 125°C
454
452
450
TJ = 25°C
448
446
1
0
TJ = -40°C
0
10
-40
20
40
120
-20
60
80
100
0
8
2
6
4
TJ - Junction Temperature - °C
VVDD-VSS - PoE Voltage - V
Figure 3.
Figure 4.
CONVERTER START TIME
CONVERTER STARTUP SOURCE CURRENT
vs
vs
TEMPERATURE
VVDD1
6
160
140
120
100
80
VVC = 8.6 V
TJ = -40°C
TJ = 25°C
CVC = 22 mF
5
4
VVDD1 = 10.2 V
TJ = 125°C
3
VVDD1 = 19.2 V
2
1
0
60
VVDD1 = 35 V
40
20
5
10
15
20
25
30
35
40
45
50
55
60
-40
-20
0
20
40
60
80
100
120
VVDD1-RTN - V
TJ - Junction Temperature - °C
Figure 5.
Figure 6.
CONTROLLER BIAS CURRENT
CONTROLLER BIAS CURRENT
vs
vs
TEMPERATURE
VOLTAGE
1200
1000
800
1000
900
800
700
600
Gate Open
TJ = 25°C
Gate Open
VVC = 12 V
500 kHz
250 kHz
500 kHz
250 kHz
100 kHz
100 kHz
500
400
300
600
50 kHz
400
200
0
50 kHz
200
VCTL = 0 V
VCTL = 0 V
100
0
-40
-20
0
20
40
60
80
100
120
7
15
17
9
11
13
TJ - Junction Temperature - °C
VC - Controller Bias Voltage - V
Figure 7.
Figure 8.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs
PROGRAMMED RESISTANCE
vs
TEMPERATURE
300
250
650
600
55
800
700
RFRS = 60.4 kW (250 kHz)
Ideal
600
500
Typical
200
150
RFRS = 30.1 kW (500 kHz)
500
450
400
350
400
300
RFRS = 148.5 kW (100 kHz)
RFRS = 301 kW (50 kHz)
100
50
0
200
100
0
60
-40
40
100
120
-20
20
80
0
0
10
20
30
40
50
6
-1
TJ - Junction Temperature - °C
Programmed Resistance (10 / RFRS ) - W
Figure 9.
Figure 10.
MAXIMUM DUTY CYCLE
vs
CURRENT SLOPE COMPENSATION VOLTAGE
vs
TEMPERATURE
TEMPERATURE
124
122
120
79
RFRS = 301 kW (50 kHz)
78.5
78
RFRS = 148.5 kW (100 kHz)
77.5
77
118
RFRS = 60.4 kW (250 kHz)
RFRS = 30.1 kW (500 kHz)
116
114
76.5
76
60
80
100
120
20
40
-40
-20
0
20
40
60
80
100
120
-40
0
-20
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 11.
Figure 12.
10
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
TYPICAL CHARACTERISTICS (continued)
CURRENT SLOPE COMPENSATION CURRENT
BLANKING PERIOD
vs
TEMPERATURE
vs
TEMPERATURE
270
50
45
40
35
30
115
105
265
260
RBLNK = 100 kW
95
85
75
255
RBLNK = 249 kW
250
245
65
55
45
RBLNK = 49.9 kW
RBLNK = RTN
240
235
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 13.
Figure 14.
BLANKING PERIOD
vs
RBLNK
18
14
450
400
350
10
6
300
250
200
2
-2
-6
-10
150
100
-14
50
-18
0
0
50
100
150
200
250
300
350
400
RBLNK - kW
Figure 15.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
APPLICATIONS
Classic PoE Overview
The following text is intended as an aid in understanding the operation of the TPS23753 but not as a substitute
for the actual IEEE 802.3-2005 or 802.3at standard. The pending IEEE 802.3at standard is an update to IEEE
802.3-2005 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a
device compliant to IEEE 802.3-2005 will be referred to as a Type 1 device, and devices with high power or
enhanced classification will be referred to as Type 2 devices. Standards change and should always be
referenced when making design decisions.
The IEEE 802.3-2005 (802.3at) standard defines a method of safely powering a PD (powered device) over a
cable, and then removing power if a PD is disconnected. The process proceeds through an idle state and three
operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state)
while it periodically looks to see if something has been plugged in; this is referred to as detection. The low power
levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is
present, the PSE may inquire how much power the PD requires; this is referred to as classification. Type 2 PSEs
are required to do hardware classification. The PD may return the default 12.95W (often refered to as 13W)
current-encoded class, or one of four other choices. The PSE may then power the PD if it has adequate capacity.
Once started, the PD must present the maintain power signature (MPS) to assure the PSE that it is still present.
The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns
the PSE to the idle state. Figure 16 shows the operational states as a function of PD input voltage.
Shut-
down
Classify
Normal Operation
Detect
0
2.7
10.1 14.5
20.5
30
PI Voltage (V)
36
57
42
Figure 16. IEEE 802.3-2005 (Type 1) Operational States
The PD input is typically an RJ-45 eight-lead connector which is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops in the cable and operating
margin. The IEEE 802.3-2005 standard uses a cable resistance of 20 Ω to derive the voltage limits at the PD
based on the PSE output voltage requirements. Although the standard specifies an output power of 15.4 W at
the PSE, only 12.95 W is available at the PI due to the worst-case power loss in the cable. The PSE can apply
voltage either between the RX and TX pairs (pins 1–2 and 3–6 for 10baseT or 100baseT), or between the two
spare pairs (4–5 and 7–8). The PSE may only apply voltage to one set of pairs at a time. The PD uses input
diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with
the input bridges create a difference between the standard limits at the PI and the TPS23753 specifications.
The PSE is permitted to disconnect a PD if it draws more than its maximum class power over a one second
interval. A PSE compliant to IEEE 802.3-2005 is required to limit current to between 400 mA and 450 mA during
powered operation, and it must disconnect the PD if it draws this current for more than 75 ms. Class 0 and 3 PDs
may draw up to 400 mA peak currents for up to 50 ms. The PSE may set lower output current limits based on
the PD’s declared power requirements.
Threshold Voltages
The TPS23753 has a number of internal comparators with hysteresis for stable switching between the various
states as shown in Figure 16. Figure 17 relates the parameters in the Electrical Characteristics section to the
PoE states. The mode labeled idle between classification and operation implies that the DEN, CLS, and RTN
pins are all high impedance.
12
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
PD Powered
Idle
Classification
VVDD-VSS
Detection
VUVLO_H
VCL_HYS
VCL_ON
VCU_HYS
VCU_OFF
1.4V
VUVLO_R
Note: Variable names refer to Electrical Characteristic
Table parameters
Figure 17. Threshold Voltages
PoE Startup Sequence
The waveforms of Figure 18 demonstrate detection, classification, and startup from a PSE. The key waveforms
shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE 802.3-2005 requires a minimum of two detection levels, however
four levels are shown in this example. Four levels guard against misdetection of a device when plugged in during
the detection sequence.
Figure 18. PoE Startup Sequence
Detection
The TPS23753 is in detection mode whenever VVDD-VSS is below the lower classification threshold. When the
input voltage rises above VCL_ON, the DEN pin goes to an open-drain condition to conserve power. While in
detection, RTN is high impedance, almost all the internal circuits are disabled, and the DEN pin is pulled to VSS
.
An RDEN of 24.9 kΩ (1%), presents the correct signature. It may be a small, low-power resistor since it only sees
a stress of about 5 mW. A valid PD detection signature is an incremental resistance between 23.75 kΩ and
26.25 kΩ at the PI.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and the TPS23753 bias loading. The input diode bridge’s incremental resistance
may be hundreds of Ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge
resistance is partially cancelled by the TPS23753's effective resistance during detection.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before starting and helps with
power management once power is applied. The maximum power entries in Table 2 determine the class the PD
must advertise. A Type 1 PD may not advertise Class 4. The PSE may disconnect a PD if it draws more than its
stated Class power. The standard permits the PD to draw limited current peaks, however the average power
requirement always applies.
Voltage between 14.5 V and 20.5 V is applied to the PD for up to 75 ms during hardware Classification. A fixed
output voltage is sourced by the CLS pin, causing a fixed current to be drawn from VDD through RCLS. The total
current drawn from the PSE during classification is the sum of bias and RCLS currents. PD current is measured
and decoded by the PSE to determine which of the five available classes is advertised (see Table 2). The
TPS23753 disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off
during PD thermal limit or when APD or DEN are active. The CLS output is inherently current limited, but should
not be shorted to VSS for long periods of time.
Table 2. Class Resistor Selection
POWER AT PD PI
Class Current Requirement
CLASS
RESISTOR (Ω)
NOTES
MINIMUM
MAXIMUM
MINIMUM (mA)
MAXIMUM (W)
(W)
0.44
0.44
3.84
6.49
(mA)
0
1
2
3
12.95
3.84
0
9
4
1270
243
12
20
30
6.49
17
26
137
12.95
90.9
802.3at only, not allowed for IEEE
802.3-2005 (type 1 devices)
4
12.95
25.5
36
44
63.4
Maintain Power Signature (MPS)
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (at a duty cycle of at least 75 ms on
every 225 ms) and an ac impedance lower than 26.25 kΩ in parallel with 0.05 µF. The ac impedance is usually
accomplished by the minimum CIN requirement of 5 µF. When APD or DEN are used to force the hotswap switch
off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power from the PD when this
occurs. A PSE that monitors only the ac MPS may remove power from the PD.
TPS23753 Operation
Startup and Converter Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and
classification. The converter circuits will discharge CIN, CVC, and CVB while the PD is unpowered. Thus VRTN-VDD
will be a small voltage just after full voltage is applied to the PD, as seen in Figure 18.
The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VDD rises
above the UVLO turn-on threshold (VUVLO-R, ~35 V) with RTN high, the TPS23753 enables the hotswap
MOSFET with a ~140 mA (inrush) current limit. Refer to the waveforms of Figure 19 for an example. Converter
switching is disabled while CIN charges and VRTN falls from VDD to nearly VSS, however the converter startup
circuit is allowed to charge CVC. Once the inrush current falls about 10% below the inrush current limit, the PD
control switches to the operational level (~450 mA) and converter switching is permitted.
14
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
Converter switching is allowed if the PD is not in inrush and the VC under-voltage lock out (UVLO) permits it.
Continuing the startup sequence shown in Figure 19, VVC rises as the startup current source charges CVC and
M1 switching is inhibited by the status of the VC UVLO. The VB regulator powers the internal converter circuits as
VVC rises. Startup current is turned off, converter switching is enabled, and a softstart cycle starts when VVC
exceeds UVLO1 (~9 V). VVC falls as it powers both the internal circuits and the switching MOSFET gate. If the
converter control-bias output rises to support VVC before it falls to UVLO1 – UVLO1H (~5.5 V), a successful
startup occurs. Figure 19 shows a small droop in VVC while the output voltage rises smoothly and a successful
startup occurs.
10
INRUSH
8
Exaggerated primary-
secondary softstart handoff
IPI
7
6
5
4
3
2
1
0
VC-RTN
VOUT
Turn ON
-0.
-0.
-0.
VDD-RTN
000.0E 10.0E-3 20.0E-3 30.0E-3 40.0E-3 50.0E-3 60.0E-3 70.0E-3 80.0E-3 90.0E-3 100.0E-
t - Time 10 - ms/DIV
Figure 19. Power Up and Start
If VVDD-VSS drops below the lower PoE UVLO (UVLOR – UVLOH, ~30.5 V), the hotswap MOSFET is turned off,
but the converter will still run. The converter will stop if VVC falls below the converter UVLO (UVLO1 – UVLOH,
~5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by VCTL (VCTL < VZDC, ~1.5 V), or
the converter is in thermal shutdown.
PD Interface Features
The PD section has the following functions, with the first four covered above.
•
•
•
•
•
•
•
Detection
Classification
VDD to VSS UVLO
Orderly sequencing of CIN charge and converter operation
Hotswap switch current limit
Hotswap switch foldback
Hotswap thermal protection
The internal hotswap MOSFET is protected against output faults with a current limit and deglitched foldback. The
PSE output cannot be relied on to protect the PD MOSFET against transient conditions, so the PD implements
its own protection. High stress conditions include converter output shorts, shorts from VDD to RTN, or transients
on the input line. An overload on the pass MOSFET engages the current limit, with VRTN-VSS rising as a result. If
VRTN rises above ~12 V for longer than ~400 µs, the current limit reverts to the inrush limit, and turns the
converter off. The 400 µs deglitch feature prevents momentary transients from causing a PD reset, provided that
recovery lies within the bounds of the hotswap and PSE protection. Figure 20 shows an example of recovery
from a 15 V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively
low current, recovers to 420 mA full current limit, and charges the input capacitor while the converter continues to
run. The MOSFET did not go into foldback because VRTN-VSS was below 12 V after the 400 µs deglitch.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
Figure 20. Response to PSE Step Voltage
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a VDD to RTN short cause high power dissipation in the MOSFET. An overtemperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The PD
state machine will always restart in inrush current limit when exiting from a PD overtemperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. This feature
allows a PD with secondary-side adapter ORing to achieve adapter priority. Care must be taken with
synchronous converter topologies that can deliver power in both directions.
The hotswap switch will be forced off under the following conditions:
•
•
•
•
VAPD above VAPDEN (~1.5 V)
DEN ≤ VPD_DIS when VVDD-VSS is in the operational range
PD over temperature
V
VVDD-VSS < PoE UVLO (~30.5 V).
Converter Controller Features
The TPS23753 dc/dc controller implements a typical current-mode control as shown in Figure 2. Features
include oscillator, overcurrent and PWM comparators, current-sense blanker, softstart, and gate driver. In
addition, an internal current-compensation ramp generator, frequency synchronization logic, thermal shutdown,
and startup current source with control are provided.
The TPS23753 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the
optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM and
converter. There is an offset of VZDC (~1.5 V) and 2:1 resistor divider between the CTL pin and the PWM. A VCTL
below VZDC will stop converter switching, while voltages above (VZDC + 2 × VCSMAX) will not increase the
requested peak current in the switching MOSFET. Optocoupler biasing design is eased by this limited control
range.
The internal startup current source and control logic implement a bootstrap-type startup. The startup current
source charges CVC from VDD1 when the converter is disabled (either by the PD control or the VC control), while
operational power must come from a converter (bias winding) output. Loading on VC and VB must be minimal
while CVC charges, otherwise the converter may never start. The optocoupler will not load VB when the converter
is off. The converter will shut off when VC falls below its lower UVLO. This can happen when power is removed
from the PD, or during a fault on a converter output rail. When one output is shorted, all the outputs fall in voltage
including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A
restart will initiate as described in "Startup and Converter Operation" if the converter turns off and there is
sufficient VDD1 voltage. This type of operation is sometimes referred to as “hiccup mode,” which provides robust
output short protection by providing time-average heating reduction of the output rectifier.
16
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection.
Leading-edge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected
tracking with output voltage. RVC (Figure 1) is often required slow the peak charging. Good transformer
bias-to-output-winding coupling results in reduced overshoot and better voltage tracking.
The startup current source transitions to a resistance as (VDD1 - VC) falls below 7 V, but will start the converter
from 12 V adapters within tST (VDD1 ≥ 10.2, V~85 ms). The bootstrap source provides reliable startup from widely
varying input voltages, and eliminates the continual power loss of external resistors. The startup current source
will not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD1 to
charge higher.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 22 to increase
slope compensation. This makes it easier to design the current limit to a fixed value.
The TPS23753 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
aviods current-sense waveform distortion, which tends to get worse at light output loads. While the internally set
blanking period is relatively precise, almost all converters will require their own blanking period. The TPS23753
provides the BLNK pin to allow this programming. There may be some situations or designers that prefer an R-C
approach. The TPS23753 provides a pull-down on CS during the GATE off time to improve sensing when an
R-C filter must be used. The CS input signal should be protected from nearby noisy signals like GATE drive and
the MOSFET drain.
Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 21
shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier
shown in Figure 1. This secondary-side error amplifier will not become active until there is sufficient voltage on
the secondary. The TPS23753 provides a primary-side softstart which persists long enough (~800 µs) for
secondary side voltage-loop softstart to take over. The primary-side current-loop softstart controls the switching
MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. Figure 19 shows
an exaggerated handoff between the primary and secondary-side softstart that is most easily seen in the IPI
waveform. The output voltage rises in a smooth monotonic fashion with no overshoot. This handoff can be
optimized by decreasing the secondary-side softstart period.
From Regulated
Output Voltage
ROB
CIZ
RSS
RFBU
DSS
CSS
RFBL
TLV431
Figure 21. Example of Softstart Circuit Added to Error Amplifier
The dc/dc controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, resets the
softstart generator, and forces the VC control into an under-voltage state.
Special Switching MOSFET Considerations
Special care must be used in selecting the converter switching MOSFET. The TPS23753 converter section has
minimum VC operating voltage of ~5.5 V, which is reflected in the applied gate voltage. This will occur during an
output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the
anticipated peak fault current at this gate voltage.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
Thermal Considerations
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS23753 is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS23753 device to experience an OTSD event if it is excessively heated by a nearby
device.
Blanking – RBLNK
The TPS23753 BLNK feature permits programming of the blanking period with specified tolerance. Selection of
the blanking period is often empirical because it is affected by parasitics and thermal effects of every device
between the gate-driver and output capacitors.
There is a critical range of blanking period that is bounded on the short side by erratic operation, and on the long
side by potentially harmful switching-MOSFET and output rectifier currents during a short circuit. The minimum
blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent
current “spike” that occurs when the switching MOSFET turns on. The maximum blanking period is bounded by
the output rectifier's ability to withstand the currents experienced during a converter output short. A short on the
flyback transformer secondary will cause very large peak MOSFET currents that are worsened by longer
blanking periods. A long blanking time also increases the minimum load required before cycle skipping occurs in
a non-synchronous converter.
The TPS23753 provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with a resistor from BLNK to RTN per the following equation.
R
kΩ = t
( )
ns
BLNK
( )
BLNK
(5)
For example, a 100 ns period is programmed by a 100 kΩ resistor. For a brand-new design, it is recommended
that an initial blanking period of 125 ns be designed in. This period should be be tuned once the converter is
operational.
Current Slope Compensation
Current-mode control requires addition of a compensation ramp to the sensed inductor (flyback transformer)
current for stability at duty cycles near and over 50%. The TPS23753 has a maximum duty cycle limit of 80%,
permitting the design of wide input-range flyback converters with a lower voltage stress on the output rectifiers.
While the maximum duty cycle is 80%, converters may be designed that run at duty cycles well below 80% for a
narrower, 36 V to 57 V range. The TPS23753 provides a fixed internal compensation ramp that suffices for most
applications. RS (see Figure 22) may be used if the internally provided slope compensation is not enough. It
works with ramp current (IPK = ISL-EX, ~40 µA) that flows out of the CS pin when the MOSFET is on. The IPK
specification does not include the ~3 µA fixed current that flows out of the CS pin.
Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp
voltage / switching period), however the electrical characteristics table specifies the slope peak (VSLOPE) based
on an 80% duty cycle. Assuming that the desired slope, VSLOPE-D (in mV/period), is based on the full period,
compute RS per the following equation where VSLOPE, DMAX, and ISL-EX are from the electrical characteristics table
with voltages in mV, current in µA, and the duty cycle is unitless (e.g. DMAX = 0.8).
18
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
V
(mV)
SLOPE
VSLOPE _D(mV) −
DMAX
RS(Ω) =
⋅1000
ISL _EX (µA)
(6)
GATE
CS
RS
RCS
CS
Figure 22. Additional Slope Compensation
CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to
appear at the CS pin. The TPS23753 has an internal pull-down on CS ( ~500 Ω ) while the MOSFET is OFF to
reduce cycle-to-cycle carry-over voltage on CS.
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23753 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 80% and
controls the current-compensation ramp circuit. RFRS should be selected per the following equation.
15000
R
(kΩ) =
FRS
f
(kHz)
SW
The TPS23753 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,
or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by
applying a short pulse ( > 25 ns) of magnitude VSYNC to FRS as shown in Figure 23. RFRS should be chosen so
that the maximum free-running frequency is just below the desired synchronization frequency. The
synchronization pulse terminates the potential on-time period, and the off-time period doesn’t begin until the
pulse terminates. A short pulse is preferred to avoid reducing the potential on-time.
Figure 23 shows examples of non-isolated and transformer-coupled synchronization circuits The pulse at the
FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and rise/fall times
less than 10 ns. The FRS node should be protected from noise because it is high-impedance.
Synchronization
Synchronization
Pulse
Pulse
FRS
RTN
FRS
RTN
47pF
47pF
1000pF
TSYNC
VSYNC
TSYNC
1:1
VSYNC
Example:
Pulse PA0184
Figure 23. Synchronization
Adapter ORing
Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power
solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
installation. While most applications only require that the PD operate when both sources are present, the
TPS23753 supports forced operation from either of the power sources. Figure 24 illustrates three options for
diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies
power to the TPS23753 PoE input, option 2 applies power between the TPS23753 PoE section and the power
circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and
disadvantages. A detailed discussion of the TPS23753 and ORing solutions is covered in application note
Advanced Adapter ORing Solutions using the TPS23753, literature number SLVA306.
Optional for PoE Priority
Low Voltage
Output
DEN
CLS
Power
Circuit
VSS
RTN
Adapter
Option 2
Adapter
Option 3
Adapter
Option 1
Figure 24. ORing Configurations
Preference of one power source presents a number of challenges. Combinations of adapter output voltage
(nominal and tolerance), power insertion point, and which source is prefered determine solution complexity.
Several factors which add to the complexity are the natural high-voltage selection of diode ORing (the simplest
method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits
(necessary for operation and reliability). Creating simple and seamless solutions is difficult if not impossible for
many of the combinations. However the TPS23753 offers several built-in features that simplify some
combinations.
Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with
PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to
assure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The
converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.
Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The
converter must be turned off while CIN capacitance charges, with a subsequent converter restart at the higher
voltage and lower input current. A third example is use of a 12 V adapter with ORing option 1. The PD hotswap
would have to handle four times the current, and have 1/16 the resistance (be 16 times larger) to dissipate equal
power. A fourth example is that MPS is lost when running from the adapter, causing the PSE to remove power
from the PD. If ac power is then lost, the PD will stop operating until the PSE detects and powers the PD.
The most popular preferential ORing scheme is option 2 with adapter priority. The hotswap MOSFET is disabled
when the adapter is used to pull APD high, blocking the PoE source from powering the output. This solution
works well with a wide range of adapter voltages, is simple, and requires few external parts. When the ac power
fails, or the adapter is removed, the hotswap switch is enabled. In the simplest implementation, the PD will
momentarily loose power until the PSE completes its startup cycle.
The DEN pin can be used to disable the PoE input when ORing with option 3. This is an adapter priority
implementation. Pulling DEN low, while creating an invalid detection signature, disables the hotswap MOSFET
and prevents the PD from redetecting. This would typically be accomplished with an optocoupler that is driven
from the secondary side of the converter.
20
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
TPS23753
www.ti.com.............................................................................................................................................................. SLVS853A–JUNE 2008–REVISED JUNE 2008
The least popular technique is PoE priority. It is implemented by placing a diode between the PD supply voltage,
VDD, and the dc/dc controller bias voltage, VDD1. The diode prevents reverse biasing of the PoE input diode
bridges when option 2 adapter ORing is used. The PSE may then detect, classify, and provide power to the PD
while a live adapter is connected. As long as the PoE voltage is greater than the adapter voltage, the PSE will
power the load. The APD function is not used in this technique.
The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The
adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections
for options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter.
Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the
adapter input pins, and damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in
option 3.
Protection
A TVS across the rectified PoE voltage per Figure 1 must be used. An SMAJ58A, or a part with equal to or better
performance, is recommended for general indoor applications. If an adapter is connected from VDD1 to RTN, as
in ORing option 2 above, voltage transients caused by the input cable inductance ringing with the internal PD
capacitance can occur. Adequate capacitive filtering or a TVS must limit this voltage to be within the absolute
maximum ratings
Outdoor applications require more extensive protection to lightning standards.
Frequency Dithering for Conducted Emissions Control
The international standard CISPR 22 (and adopted versions) is often used as a requirement for conducted
emissions. Ethernet cables are covered as a telecommunication port under section 5.2 for conducted emissions.
Meeting EMI requirements is often a challenge, with the lower limits of Class B being especially hard. Circuit
board layout, filtering, and snubbing various nodes in the power circuit are the first layer of control techniques. A
more detailed discussion of EMI control is presented in Practical Guidelines to Designing an EMI Compliant PoE
Powered Device With Isolated Flyback, TI literature number SLUA469. Additionally, IEEE802.3-2005 section 33.4
has requirements for noise injected onto the Ethernet cable based on compatibility with data transmission.
Occasionally, a technique referred to as frequency dithering is utilized to provide additional EMI measurement
reduction. The switching frequency is modulated to spread the narrowband individual harmonics across a wider
bandwidth, thus lowering peak measurements. The circuit of Figure 25 modulates the switching frequency by
feeding a small ac signal into the FRS pin. These values may be adapted to suit individual needs.
VB
6.04kΩ
+
-
TL331IDBV
10kΩ
To
301kΩ
FRS
1uF
RTN
Figure 25. Frequency Dithering
Design Procedure
A detailed design procedure for PDs using the TPS23753 is covered in Designing with the TPS23753 Powered
Device and Power Supply Controller , literature number SLVA305.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): TPS23753
TPS23753
SLVS853A–JUNE 2008–REVISED JUNE 2008.............................................................................................................................................................. www.ti.com
References
IEEE Standard for Information Technology … Part 3: Carrier sense multiple access with collision detection
(CSMA/CD) access method and physical layer specifications, IEEE Computer Society, IEEE 802.3™-2005
(Clause 33)
Information technology equipment – Radio disturbance characteristics – Limits and methods of measurement,
International Electrotechnical Commission, CISPR 22 Edition 5.2, 2006-03
Designing with the TPS23753 Powered Device and Power Supply Controller, Eric Wright, TI, SLVA305
Advanced Adapter ORing Solutions using the TPS23753, Eric Wright, TI, SLVA306
Practical Guidelines to Designing an EMI-Compliant PoE Powered Device With Isolated Flyback, Donald V.
Comiskey, TI, SLUA469
22
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS23753
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
TPS23753PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
14
14
14
14
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS23753PWG4
TPS23753PWR
TPS23753PWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS23753PWR
TSSOP
PW
14
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
TPS23753PWR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明