TP3054-X [TI]
Extended Temperature Serial Interface CODEC/Filter COMBO Family;
| 型号： | TP3054-X |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Extended Temperature Serial Interface CODEC/Filter COMBO Family |
| 文件： | 总22页 (文件大小：1065K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C –MARCH 2005–REVISED APRIL 2013
Extended Temperature Serial Interface CODEC/Filter COMBO Family
Check for Samples: TP3054-X, TP3057-X
1
FEATURES
DESCRIPTION
The TP3054, TP3057 family consists of μ-law and A-
law monolithic PCM CODEC/filters utilizing the A/D
and D/A conversion architecture shown in Figure 3,
2
•
•
−40°C to +85°C Operation
Complete CODEC and Filtering System
(COMBO) Including:
and
a serial PCM interface. The devices are
–
–
Transmit High-Pass and Low-Pass Filtering
fabricated using TI's advanced double-poly CMOS
process (microCMOS).
Receive Low-Pass Filter with Sin x/x
Correction
The encode portion of each device consists of an
input gain adjust amplifier, an active RC pre-filter
which eliminates very high frequency noise prior to
entering a switched-capacitor band-pass filter that
rejects signals below 200 Hz and above 3400 Hz.
–
–
Active RC Noise Filters
μ-Law or A-Law Compatible COder and
DECoder
–
–
–
Internal Precision Voltage Reference
Serial I/O Interface
Also included are auto-zero circuitry and
a
companding coder which samples the filtered signal
and encodes it in the companded μ-law or A-law
PCM format. The decode portion of each device
consists of an expanding decoder, which reconstructs
the analog signal from the companded μ-law or A-law
code, a low-pass filter which corrects for the sin x/x
response of the decoder output and rejects signals
above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The
devices require two 1.536 MHz, 1.544 MHz or
2.048 MHz transmit and receive master clocks, which
may be asynchronous; transmit and receive bit
clocks, which may vary from 64 kHz to 2.048 MHz;
and transmit and receive frame sync pulses. The
timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
Internal Auto-Zero Circuitry
•
•
•
•
•
•
•
•
•
•
•
μ-Law, 16-Pin - TP3054
A-Law, 16-Pin - TP3057
Designed for D3/D4 and CCITT Spplications
±5V Operation
Low Operating Power - Typically 50 mW
Power-Down Standby Mode - Typically 3 mW
Automatic Power-Down
TTL or CMOS Compatible Digital Interfaces
Maximizes Line Interface Card Circuit Density
Dual-In-Line or PCC Surface Mount Packages
See also AN-370, “Techniques for Designing
with CODEC/Filter COMBO Circuits”
(SNLA136)
Connection Diagram
Figure 1. Plastic Chip Carriers (Top View)
Figure 2. Dual-In-Line Package (Top View)
Package Number NFG001E & DW0016B
Package Number FN0020A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
TP3054-X, TP3057-X
SNOSBY2C –MARCH 2005–REVISED APRIL 2013
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Block Diagram
Figure 3.
PIN DESCRIPTIONS
Symbol
Function
VBB
Negative power supply pin.
VBB = −5V ±5%.
GNDA
VFRO
VCC
Analog ground. All signals are referenced to this pin.
Analog output of the receive power amplifier.
Positive power supply pin.
VCC = +5V ±5%.
Receive frame sync pulse which enables BCLKR to shift PCM data into DR. FSR is an 8 kHz
pulse train. See Figure 4 and Figure 5 for timing details.
FSR
DR
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The bit clock which shifts data into DR after the FSR leading edge. May vary from 64 kHz to
2.048 MHz. Alternatively, may be a logic input which selects either 1.536 MHz/1.544 MHz or
2.048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and
receive directions (see Table 1).
BCLKR/CLKSEL
MCLKR/PDN
Receive master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous with
MCLKX, but should be synchronous with MCLKX for best performance. When MCLKR is
connected continuously low, MCLKX is selected for all internal timing. When MCLKR is connected
continuously high, the device is powered down.
Transmit master clock. Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be asynchronous
with MCLKR. Best performance is realized from synchronous operation.
MCLKX
FSX
Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX. FSX is
an 8 kHz pulse train, see Figure 4 and Figure 5 for timing details.
The bit clock which shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
BCLKX
2
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PIN DESCRIPTIONS (continued)
Symbol
Function
DX
The TRI-STATE PCM data output which is enabled by FSX.
Open drain output which pulses low during the encoder time slot.
Analog output of the transmit input amplifier. Used to externally set gain.
Inverting input of the transmit input amplifier.
TSX
GSX
VFXI−
VFXI+
Non-inverting input of the transmit input amplifier.
Functional Description
POWER-UP
When power is first applied, power-on reset circuitry initializes the COMBO and places it into a power-down
state. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states.
To power-up the device, a logical low level or clock must be applied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down control modes are available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR inputs continuously low—the device will power-down
approximately 1 ms after the last FSX or FSR pulse. Power-up will occur on the first FSX or FSR pulse. The TRI-
STATE PCM data output, DX, will remain in the high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKX and the MCLKR/PDN pin can be used as a power-
down control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In
either case, MCLKX will be selected as the master clock for both the transmit and receive circuits. A bit clock
must also be applied to BCLKX and the BCLKR/CLKSEL can be used to select the proper internal divider for a
master clock of 1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz operation, the device automatically
compensates for the 193rd clock pulse each frame.
With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state
of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from 64 kHz to 2.048 MHz, but must
be synchronous with MCLKX.
Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the
enabled DX output on the positive edge of BCLKX. After 8 bit clock periods, the TRI-STATE DX output is returned
to a high impedance state. With an FSR pulse, PCM data is latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must be synchronous with MCLKX/R
.
Table 1. Selection of Master Clock Frequencies
Master Clock
Frequency Selected
TP3057
BCLKR/CLKSEL
TP3054
Clocked
2.048 MHz
1.536 MHz or 1.544 MHz
2.048 MHz
0
1
1.536 MHz or 1.544 MHz
2.048 MHz
1.536 MHz or 1.544 MHz
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ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive clocks may be applied. MCLKX and MCLKR must be
2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the TP3054, and need not be synchronous. For best
transmission performance, however, MCLKR should be synchronous with MCLKX, which is easily achieved by
applying only static logic levels to the MCLKR/PDN pin. This will automatically connect MCLKX to all internal
MCLKR functions (see Pin Description above). For 1.544 MHz operation, the device automatically compensates
for the 193rd clock pulse each frame. FSX starts each encoding cycle and must be synchronous with MCLKX and
BCLKX. FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the logic
levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate from 64 kHz to
2.048 MHz.
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the
device assumes a short frame mode. In this mode, both frame sync pulses, FSX and FSR, must be one bit clock
period long, with timing relationships specified in Figure 4. With FSX high during a falling edge of BCLKX, the next
rising edge of BCLKX enables the DX TRI-STATE output buffer, which will output the sign bit. The following seven
rising edges clock out the remaining seven bits, and the next falling edge disables the DX output. With FSR high
during a falling edge of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign
bit. The following seven falling edges latch in the seven remaining bits. All four devices may utilize the short
frame sync pulse in synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync pulses, FSX and FSR, must be three or more bit clock periods
long, with timing relationships specified in Figure 5. Based on the transmit frame sync, FSX, the COMBO will
sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must
be kept low for a minimum of 160 ns. The DX TRI-STATE output buffer is enabled with the rising edge of FSX or
the rising edge of BCLKX, whichever comes later, and the first bit clocked out is the sign bit. The following seven
BCLKX rising edges clock out the remaining seven bits. The DX output is disabled by the falling BCLKX edge
following the eighth rising edge, or by FSX going low, whichever comes later. A rising edge on the receive frame
sync pulse, FSR, will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX
in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous
mode.
In applications where the LSB bit is used for signalling, with FSR two bit clock periods long, the decoder will
interpret the lost LSB as “½” to minimize noise and distortion.
TRANSMIT SECTION
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors, see Figure 8. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio
passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an
eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the
encoder sample-and-hold circuit. The A/D is of companding type according to μ-law (TP3054) or A-law (TP3057)
coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX
)
of nominally 2.5V peak (see Transmission Characteristics). The FSX frame sync pulse controls the sampling of
the filter output, and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into
a buffer and shifted out through DX at the next FSX pulse. The total encoding delay will be approximately 165 μs
(due to the transmit filter) plus 125 μs (due to encoding delay), which totals 290 μs. Any offset voltage due to the
filters or comparator is cancelled by sign bit integration.
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RECEIVE SECTION
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or μ-law (TP3054) and the 5th order low pass filter corrects
for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-
filter/power amplifier capable of driving a 600Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon
the occurrence of FSR, the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX)
periods. At the end of the decoder time slot, the decoding cycle begins, and 10 μs later the decoder DAC output
is updated. The total decoder delay is ∼10 μs (decoder update) plus 110 μs (filter delay) plus 62.5 μs (½ frame),
which gives approximately 180 μs.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VCC to GNDA
7V
−7V
VBB to GNDA
Voltage at any Analog Input or Output
Voltage at any Digital Input or Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature
VCC+0.3V to VBB−0.3V
VCC+0.3V to GNDA−0.3V
−55°C to + 125°C
−65°C to +150°C
300°C
(Soldering, 10 sec.)
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC
=
+5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
2.2
Typ
Max
0.6
Units
DIGITAL INTERFACE
VIL
Input Low Voltage
Input High Voltage
V
V
VIH
VOL
DX, IL=3.2 mA
0.4
0.4
0.4
V
Output Low Voltage
SIGR, IL=1.0 mA
V
TSX, IL=3.2 mA, Open Drain
DX, IH=−3.2 mA
V
VOH
2.4
2.4
V
Output High Voltage
SIGR, IH=−1.0 mA
V
IIL
Input Low Current
Input High Current
GNDA≤VIN≤VIL, All Digital Inputs
−10
−10
10
10
μA
μA
IIH
IOZ
VIH≤VIN≤VCC
Output Current in High Impedance State
(TRI-STATE)
DX, GNDA≤VO≤VCC
−10
10
μA
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
IIXA
Input Leakage Current
Input Resistance
Output Resistance
Load Resistance
Load Capacitance
Output Dynamic Range
Voltage Gain
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
−2.5V≤V≤+2.5V, VFXI+ or VFXI−
Closed Loop, Unity Gain
GSX
−200
200
nA
MΩ
Ω
RIXA
ROXA
RLXA
CLXA
VOXA
AVXA
10
1
3
10
kΩ
pF
V
GSX
50
GSX, RL ≥ 10 kΩ
VFXI+ to GSX
−2.8
2.8
5000
V/V
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Electrical Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC
=
+5.0V, VBB = −5.0V, TA = 25°C.
Symbol
FUXA
Parameter
Unity Gain Bandwidth
Conditions
Min
1
Typ
Max
Units
MHz
mV
V
2
VOSXA
VCMXA
Offset Voltage
−20
−2.5
60
20
Common-Mode Voltage
CMRRXA > 60 dB
2.5
CMRRXA Common-Mode Rejection Ratio
PSRRXA Power Supply Rejection Ratio
DC Test
DC Test
dB
60
dB
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
RORF
RLRF
Output Resistance
Load Resistance
Pin VFRO
1
3
Ω
Ω
VFRO=±2.5V
600
CLRF
Load Capacitance
Output DC Offset Voltage
500
pF
mV
VOSRO
−200
200
POWER DISSIPATION (ALL DEVICES)
ICC
IBB
ICC
IBB
0
Power-Down Current
No Load(1)
No Load(1)
No Load
0.65
0.01
5.0
2.0
mA
mA
mA
mA
0
Power-Down Current
0.33
11.0
11.0
1
Power-Up (Active) Current
Power-Up (Active) Current
1
No Load
5.0
(1) ICC0 and IBB0 are measured after first achieving a power-up state.
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Timing Specifications
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC
=
+5.0V, VBB = –5.0V, TA = 25°C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing
Conventions section for test methods information.
Symbol
Parameter
Conditions
Depends on the Device Used and the
BCLKR/CLKSEL Pin.
Min
Typ
Max
Units
MHz
MHz
MHz
ns
1/tPM
1.536
1.544
2.048
Frequency of Master Clocks
MCLKX and MCLKR
tRM
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
MCLKX and MCLKR
50
50
tFM
MCLKX and MCLKR
ns
tPB
485
488
15725
50
ns
tRB
Rise Time of Bit Clock
Fall Time of Bit Clock
BCLKX and BCLKR
BCLKX and BCLKR
MCLKX and MCLKR
MCLKX and MCLKR
ns
tFB
50
ns
tWMH
tWML
tSBFM
Width of Master Clock High
Width of Master Clock Low
160
160
100
125
100
ns
ns
Short Frame
Long Frame
ns
Set-Up Time from BCLKX High First Bit Clock after the Leading Edge of
to MCLKX Falling Edge
FSX
tSFFM
Setup Time from FSX High to
MCLKX Falling Edge
ns
Long Frame Only
tWBH
tWBL
tHBFL
Width of Bit Clock High
Width of Bit Clock Low
VIH=2.2V
VIL=0.6V
160
160
ns
ns
Holding Time from Bit Clock
Low to Frame Sync
Long Frame Only
Short Frame Only
Long Frame Only
0
0
ns
ns
ns
tHBFS
tSFB
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
115
0
tDBD
Delay Time from BCLKX High
to Data Valid
Load=150 pF plus 2 LSTTL Loads
Load=150 pF plus 2 LSTTL Loads
CL=0 pF to 150 pF
140
140
165
ns
ns
ns
tDBTS
tDZC
Delay Time to TSX Low
Delay Time from BCLKX Low to
Data Output Disabled
50
20
tDZF
Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later
CL=0 pF to 150 pF
165
ns
tSDB
tHBD
tSF
Set-Up Time from DR Valid to
BCLKR/X Low
50
50
ns
ns
Hold Time from BCLKR/X Low to
DR Invalid
Set-Up Time from FSX/R to
BCLKX/R Low
Short Frame Sync Pulse (1 Bit Clock Period Long)
Short Frame Sync Pulse (1 Bit Clock Period Long)
50
ns
ns
tHF
Hold Time from BCLKX/R Low
to FSX/R Low
100
tHBFl
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSX or FSR)
Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods
Long)
100
160
ns
ns
tWFL
Minimum Width of the Frame
Sync Pulse (Low Level)
64k Bit/s Operating Mode
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Timing Diagrams
Figure 4. Short Frame Sync Timing
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Figure 5. Long Frame Sync Timing
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Transmission Characteristics
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AMPLITUDE RESPONSE
Absolute Levels
(Definition of nominal gain)
Nominal 0 dBm0 Level is 4 dBm
(600Ω) 0 dBm0
1.2276
Vrms
tMAX
Max Overload Level
TP3054 (3.17 dBm0)
TP3057 (3.14 dBm0)
2.501
2.492
VPK
VPK
GXA
GXR
TA=25°C, VCC=5V, VBB=−5V
Input at GSx=0 dBm0 at 1020 Hz
Transmit Gain, Absolute
−0.15
0.15
dB
f=16 Hz
−40
−30
−26
−0.1
0.15
0.20
0.1
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
f=50 Hz
f=60 Hz
f=200 Hz
−1.8
−0.15
−0.15
−0.35
−0.7
f=300 Hz–3000 Hz
f=3152 Hz
Transmit Gain, Relative to GXA
f=3300 Hz
f=3400 Hz
0
f=4000 Hz
−14
−32
f=4600 Hz and Up, Measure
Response from 0 Hz to 4000 Hz
GXAT
GXAV
GXRL
Absolute Transmit Gain Variation with
Temperature
Relative to GXA
Relative to GXA
−0.15
−0.05
0.15
dB
dB
Absolute Transmit Gain Variation with
Supply Voltage
0.05
Sinusoidal Test Method
Reference Level=−10 dBm0
VFXI+=−40 dBm0 to +3 dBm0
VFXI+=−50 dBm0 to −40 dBm0
VFXI+=−55 dBm0 to −50 dBm0
TA=25°C, VCC=5V, VBB=−5V
Input=Digital Code Sequence
for 0 dBm0 Signal at 1020 Hz
f=0 Hz to 3000 Hz
Transmit Gain Variations with Level
−0.2
−0.4
−1.2
0.2
0.4
1.2
dB
dB
dB
GRA
Receive Gain, Absolute
−0.20
0.20
dB
GRR
−0.15
−0.35
−0.7
0.15
0.1
0
dB
dB
dB
dB
f=3300 Hz
Receive Gain, Relative to GRA
f=3400 Hz
f=4000 Hz
−14
GRAT
GRAV
GRRL
Absolute Receive Gain Variation with
Temperature
Relative to GRA
Relative to GRA
−0.15
−0.05
0.15
dB
dB
Absolute Receive Gain Variation with
Supply Voltage
0.05
Sinusoidal Test Method; Reference
Input PCM Code Corresponds to an
Ideally Encoded
Receive Gain Variations with Level
PCM Level =−40 dBm0 to +3 dBm0
PCM Level =−50 dBm0 to −40 dBm0
PCM Level =−55 dBm0 to −50 dBm0
RL=600Ω
−0.2
−0.4
−1.2
−2.5
0.2
0.4
1.2
2.5
dB
dB
dB
V
VRO
Receive Output Drive Level
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Transmission Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ENVELOPE DELAY DISTORTION WITH FREQUENCY
DXA
DXR
Transmit Delay, Absolute
f=1600 Hz
290
195
120
50
315
220
145
75
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
f=500 Hz−600 Hz
f=600 Hz−800 Hz
f=800 Hz−1000 Hz
f=1000 Hz−1600 Hz
f=1600 Hz−2600 Hz
f=2600 Hz−2800 Hz
f=2800 Hz−3000 Hz
f=1600 Hz
Transmit Delay, Relative to DXA
20
40
55
75
80
105
155
200
130
180
−25
−20
70
DRA
DRR
Receive Delay, Absolute
f=500 Hz−1000 Hz
f=1000 Hz−1600 Hz
f=1600 Hz−2600 Hz
f=2600 Hz−2800 Hz
f=2800 Hz−3000 Hz
−40
−30
Receive Delay, Relative to DRA
90
100
145
125
175
NOISE
NXC
Transmit Noise, C Message Weighted TP3054(1)
Transmit Noise, P Message Weighted TP3057(1)
12
16
dBrnC0
dBm0p
NXP
−74
−67
NRC
PCM Code is Alternating Positive and
Negative Zero - TP3054
Receive Noise, C Message Weighted
Receive Noise, P Message Weighted
Noise, Single Frequency
8
11
dBrnC0
dBm0p
dBm0
NRP
NRS
TP3057 PCM Code Equals Positive Zero
−82
−79
−53
f=0 kHz to 100 kHz, Loop Around
Measurement, VFXI+=0 Vrms
PPSRX
NPSRX
PPSRR
VCC=5.0 VDC+100 mVrms
f=0 kHz−50 kHz(2)
Positive Power Supply Rejection,
Transmit
40
40
dBC
dBC
VBB=−5.0 VDC+ 100 mVrms
f=0 kHz−50 kHz(2)
Negative Power Supply Rejection,
Transmit
PCM Code Equals Positive Zero
VCC=5.0 VDC+100 mVrms
Measure VFR0
Positive Power Supply Rejection,
Receive
f=0 Hz−4000 Hz
38
38
35
dBC
dB
f=4 kHz−25 kHz
f=25 kHz−50 kHz
dB
NPSRR
PCM Code Equals Positive Zero
VBB=−5.0 VDC+100 mVrms
Measure VFR0
Negative Power Supply Rejection,
Receive
f=0 Hz−4000 Hz
38
38
35
dBC
dB
f=4 kHz−25 kHz
f=25 kHz−50 kHz
dB
(1) Measured by extrapolation from the distortion test result at −50 dBm0.
(2) PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+.
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Transmission Characteristics (continued)
Unless otherwise noted, limits printed in BOLD characters are ensured for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C
to +85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other
production tests and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier
connected for unity gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.
Symbol
Parameter
Conditions
Loop Around Measurement, 0 dBm0,
300 Hz to 3400 Hz Input PCM Code
Applied at DR.
Min
Typ
Max
Units
SOS
−30
dB
Spurious Out-of-Band Signals at the
Channel Output
4600 Hz–7600 Hz
−30
−40
−30
dB
dB
dB
7600 Hz–8400 Hz
8400 Hz–100,000 Hz
DISTORTION
STDX,
STDR
Sinusoidal Test Method(3)
Level=3.0 dBm0
33
36
28
29
13
14
dBC
dBC
dBC
dBC
dBC
dBC
dB
=0 dBm0 to −30 dBm0
Signal to Total Distortion Transmit or
Receive Half-Channel
=−40 dBm0
XMT
RCV
XMT
RCV
=−55 dBm0
SFDX
SFDR
IMD
Single Frequency Distortion, Transmit
Single Frequency Distortion, Receive
−43
−43
dB
Loop Around Measurement,
VFXI+=−4 dBm0 to −21 dBm0, Two
Frequencies in the Range
300 Hz−3400 Hz
Intermodulation Distortion
−41
dB
CROSSTALK
CTX-R
f=300 Hz−3400 Hz
DR=Quiet PCM Code(4)
Transmit to Receive Crosstalk, 0 dBm0
Transmit Level
−90
−90
−70
−70
dB
dB
CTR-X
Receive to Transmit Crosstalk, 0 dBm0
Receive Level
f=300 Hz−3400 Hz, VFXI=Multitone(5)
(3) TP3054/57 are measured using C message weighted filter for μ-law and psophometric weighted filter for A-law.
(4) CTX–R @ 1.544 MHz MCLKX freq. is −70 dB max. 50% ±5% BCLKX duty cycle.
(5) PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+.
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SNOSBY2C –MARCH 2005–REVISED APRIL 2013
Encoding Format at DX Output
TP3054 μ-Law
TP3057 A-Law (Includes Even Bit Inversion)
VIN (at GSX)=+Full-Scale
VIN (at GSX)=0V
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
VIN (at GSX)=−Full-Scale
APPLICATIONS INFORMATION
POWER SUPPLIES
While the pins of the TP3050 family are well protected against electrical misuse, it is recommended that the
standard CMOS practice be followed, ensuring that ground is connected to the device before any other
connections are made. In applications where the printed circuit board may be plugged into a “hot” socket with
power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the GNDA pin.
This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1 μF
supply decoupling capacitors should be connected from this common ground point to VCC and VBB, as close to
device pins as possible.
For best performance, the ground point of each CODEC/FILTER on a card should be connected to a common
card ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to VCC and VBB with 10 μF capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where a TP3050 family CODEC/filter receive output must drive a 600Ω load, but a peak swing
lower than ±2.5V is required, the receive gain can be easily adjusted by inserting a matched T-pad or π-pad at
the output. Table 2 lists the required resistor values for 600Ω terminations. As these are generally non-standard
values, the equations can be used to compute the attenuation of the closest practical set of resistors. It may be
necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation.
Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a
good return loss. For example a 30 dB return loss against 600Ω is obtained if the output impedance of the
attenuator is in the range 282Ω to 319Ω (assuming a perfect transformer).
Figure 6. T-Pad Attenuator
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Note: See Application Note 370 for further details.
Figure 7. π-Pad Attenuator
Table 2. Attentuator Tables for Z1=Z2=300Ω (All Values in Ω)
dB
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
R1
1.7
R2
26k
13k
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6l
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
R3
3.5
R4
52k
3.5
6.9
26k
5.2
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
17.4k
13k
6.9
8.5
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
413
386
366
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
3
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
4
5
84
6
100
115
379
143
156
168
180
190
200
210
218
233
246
7
8
9
10
11
12
13
14
15
16
18
20
77
61
14
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Product Folder Links: TP3054-X TP3057-X
TP3054-X, TP3057-X
www.ti.com
SNOSBY2C –MARCH 2005–REVISED APRIL 2013
Typical Synchronous Application
Figure 8.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
TP3054WM-X
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
NRND
SOIC
SOIC
SOIC
SOIC
DW
16
16
16
16
45
TBD
Call TI
Call TI
TP3054WM-X
COMBO$R
TP3054WM-X/63
TP3054WM-X/63SN
TP3054WM-X/NOPB
NRND
NRND
NRND
DW
DW
DW
1000
1000
45
TBD
Call TI
Call TI
TP3054WM-X
COMBO$R
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
Level-4-260C-72 HR
TP3054WM-X
COMBO$R
Green (RoHS
& no Sb/Br)
SN | CU SN
TP3054WM-X
COMBO$R
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TP3054WM-X/63
SOIC
SOIC
DW
DW
16
16
1000
1000
330.0
330.0
16.4
16.4
10.9
10.9
10.7
10.7
3.2
3.2
12.0
12.0
16.0
16.0
Q1
Q1
TP3054WM-X/63SN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TP3054WM-X/63
SOIC
SOIC
DW
DW
16
16
1000
1000
367.0
367.0
367.0
367.0
38.0
38.0
TP3054WM-X/63SN
Pack Materials-Page 2
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