TP3064A [TI]
MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER; 整体式串行接口联合PCM编解码器和过滤器
| 型号： | TP3064A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 文件： | 总20页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass
Filtering
µ-Law – TP3064B and TP13064B
A-Law – TP3067B and TP13067B
±5-V Operation
Low Operating Power . . . 70 mW Typ
Power-Down Standby Mode . . . 3 mW Typ
Automatic Power Down
– Receive Low-Pass Filter With (sin x)/x
Correction
– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and
Decoder
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density
– Internal Precision Voltage Reference
– Serial I/O Interface
Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
TP3067-X
– Internal Autozero Circuitry
description
DW OR N PACKAGE
(TOP VIEW)
The TP3064A, TP3067A, TP13064A, and
TP13067A are comprised of a single-chip PCM
codec (pulse-code-modulated encoder and de-
coder) and PCM line filter. These devices provide
all the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TDM
(time-division-multiplexed) system. These de-
vices are pin-for-pin compatible with the National
Semiconductor TP3064A and TP3067A, respec-
tively. Primary applications include:
VPO+
ANLG GND
VPO–
V
BB
VFXI+
VFXI–
GSX
ANLG LOOP
TSX
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
VPI
VFRO
V
CC
FSR
DR
14 FSX
13 DX
12 BCLKX
11 MCLKX
BCLKR/CLKSEL
•
Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems
MCLKR/PDN 10
•
•
•
•
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064A, TP3067A, TP13064A, and TP13067A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and
TP13067A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below –55 dBm0.
The TP3064A and TP3067A are characterized for operation from 0°C to 70°C. The TP13064A and TP13067A
are characterized for operation from –40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
functional block diagram
R2
17
16
GSX
Analog
Input
ANLG
LOOP
R1
18
Autozero
Logic
VFXI–
VFXI+
–
+
19
Switched-
Capacitor
Band-Pass Filter
RC
Active Filter
R
R
S/H
DAC
–
+
1
VPO+
VPO–
A/D
Control
Logic
Voltage
Reference
Transmit
Regulator
13
DX
DR
OE
Comparator
–
+
3
Switched-
Capacitor
Low-Pass Filter
Receive
Regulator
RC Active
Filter
S/H
DAC
R3
R4
8
4
VPI
CLK
5 VFRO
15
Timing and Control
TSX
5 V
–5 V
20
11
10
12
9
7
14
6
2
V
CC
V
BB
ANLG GND
MCLKX MCLKR/ BCLKX BCLKR/ FSR FSX
PDN CLKSEL
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
2
ANLG GND
Analog ground. All signals are referenced to ANLG GND.
ANLG LOOP
16
Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit
filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power
amplifier.
BCLKR/CLKSEL
BCLKX
9
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).
12
ThebitclockthatshiftsoutthePCMdataonDX. BCLKXcanvaryfrom64kHzto2.048MHz, butmustbesynchronous
with MCLKX.
DR
8
13
7
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that is enabled by FSX.
DX
FSR
Receive frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures
1 and 2 for timing details).
FSX
14
Transmit frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
GSX
17
10
Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should
besynchronousforbestperformance.WhenMCLKRisconnectedcontinuouslylow,MCLKXisselectedforallinternal
timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX
TSX
11
15
20
6
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
Open-drain output that pulses low during the encoder time slot
V
V
Negative power supply. V
= –5 V ± 5%
= 5 V ± 5%
BB
BB
Positive power supply. V
CC
CC
VFRO
VFXI+
VFXI–
VPI
5
Analog output of the receive filter
19
18
4
Noninverting input of the transmit input amplifier
Inverting input of the transmit input amplifier
Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to V
The noninverted output of the receive power amplifier
The inverted output of the receive power amplifier
BB
VPO+
VPO–
1
3
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
BB
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
+ 0.3 V to V – 0.3 V
+ 0.3 V to GND – 0.3 V
CC
BB
CC
Operating free-air temperature range, T : TP3064A, TP3067A . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TP13064A, TP13067A . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
T
A
≤ 25°C
T
A
= 70°C
T = 85°C
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DW
N
1025 mW
8.2 mW/°C
9.2 mW/°C
656 mW
736 mW
533 mW
598 mW
1150 mW
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
Supply voltage, V
Supply voltage, V
4.75
–4.75
2.2
5
5.25
CC
BB
–5 –5.25
V
High-level input voltage, V
V
IH
Low-level input voltage, V
IL
Common-mode input voltage range, V
0.6
V
‡
±2.5
V
ICR
Load resistance at GSX, R
10
kΩ
pF
L
Load capacitance at GSX, C
50
70
85
L
TP3064A, TP3067A
0
Operating free-air temperature, T
°C
A
TP13064A, TP13067A
–40
‡
Measure with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current
TP306xA
TP1306xA
PARAMETER
TEST CONDITIONS
No load
UNIT
mA
†
†
MIN TYP
MAX
1
MIN TYP
MAX
1.2
11
Power down
Active
0.5
6
0.5
6
I
I
Supply current from V
Supply current from V
CC
CC
10
1
Power down
Active
0.5
6
0.5
6
1.2
11
No load
mA
BB
BB
10
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
electrical characteristics at V =5V±5%, V =–5V±5%, GNDat0V, T =25°C (unless otherwise
CC
BB
A
noted)
digital interface
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
High-level output voltage
DX
I
H
I
L
I
L
= –3.2 mA
2.4
V
OH
DX
= 3.2 mA
0.4
0.4
Low-level output voltage
V
OL
TSX
= 3.2 mA, Drain open
I
I
I
High-level input current
V = V to V
IH CC
±10
±10
±10
µA
µA
µA
IH
I
Low-level input current
All digital inputs
DX
V = GND to V
I
IL
IL
= GND to V
CC
Output current in high-impedance state
V
O
OZ
analog interface with transmit amplifier input
†
PARAMETER
TEST CONDITIONS
V = –2.5 V to 2.5 V
MIN TYP
MAX
UNIT
nA
MΩ
Ω
I
I
Input current
VFXI+ or VFXI–
±200
I
r
i
Input resistance
VFXI+ or VFXI–
V = –2.5 V to 2.5 V
I
10
r
o
Output resistance
Closed loop, Unit gain
≥ 10 kΩ
1
2
3
Output dynamic range
Open-loop voltage amplification
Unity-gain bandwidth
Input offset voltage
GSX
R
±2.8
V
L
A
V
VFXI+ to GSX
GSX
5000
1
B
I
MHz
mV
dB
V
IO
VFXI+ or VFXI–
±20
CMRR
Common-mode rejection ratio
Supply-voltage rejection ratio
60
60
k
dB
SVR
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
analog interface with receive filter
PARAMETER
†
TEST CONDITIONS
MIN TYP
MAX
UNIT
Ω
Output resistance
VFRO
1
3
Load resistance
VFRO = ±2.5 V
600
Ω
Load capacitance
VFRO to GND
VFRO to GND
500
pF
Output dc offset voltage
±200
mV
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
analog interface with power amplifiers
†
PARAMETER
TEST CONDITIONS
VPI = –1 V to 1 V
MIN TYP
MAX
UNIT
nA
I
I
Input current
±100
r
Input resistance
VPI = –1 V to 1 V
VPO+ or VPO– Inverting unity gain
VPO– or VPO+ VPO– = 1.77 Vrms,
10
MΩ
Ω
i
r
o
Output resistance
Voltage amplification
Unity-gain bandwidth
Input offset voltage
1
A
R
= 600 Ω
L
–1
V
B
VPO–
Open loop
400
kHz
mV
I
V
±25
IO
0 kHz to 4 kHz
4 kHz to 50 kHz
60
36
k
Supply-voltage rejection ratio of V
or V
BB
VPO– connected to VPI
dB
SVR
CC
R
C
Load resistance
Connected from VPO+ to VPO–
600
Ω
L
L
Load capacitance
100
pF
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
operating characteristics, over operating free-air temperature range V
= 5 V ± 5%,
CC
= –5 V ± 5%, GND at 0 V, V = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
V
BB
I
gain, noninverting (unless otherwise noted)
timing requirements
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
MHz
MHz
ns
MCLX
and
MCLKR
1.536
1.544
2.048
Depends on the device used and
BCLKX/CLKSEL
f
f
t
Frequency of master clock
Frequency of bit clock, transmit
Rise time of master clock
clock(M)
clock(B)
r1
BCLKX
64
2.048
50
MCLKX
and
MCLKR
Measured from 20% to 80%
Measured from 20% to 80%
MCLKX
and
t
f1
Fall time of master clock
50
ns
MCLKR
t
t
t
t
Rise time of bit clock, transmit
BCLKX Measured from 20% to 80%
BCLKX Measured from 20% to 80%
50
50
ns
ns
ns
ns
r2
Fall time of bit clock, transmit
f2
Pulse duration, MCLKX and MCLKR high
Pulse duration, MCLKX and MCLKR low
160
160
w1
w2
Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKX↓
First bit clock after the leading edge
of FSX
t
100
ns
su1
t
t
Pulse duration, BCLKX and BCLKR high
Pulse duration, BCLKX and BCLKR low
V
V
= 2.2 V
= 0.6 V
160
160
ns
ns
w3
IH
w4
IL
Hold time, frame sync low after bit clock low (long
frame only)
t
t
t
0
0
ns
ns
ns
h1
Hold time, BCLKX high after frame sync↑ (short
frame only)
h2
Setup time, frame sync high before bit clock↓ (long
frame only)
80
0
su2
‡
‡
t
t
Delay time, BCLKX high to data valid
Delay time, BCLKX high to TSX low
Load = 150 pF plus 2 LSTTL loads
Load = 150 pF plus 2 LSTTL loads
140
140
ns
ns
d1
d2
Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled
t
t
50
20
165
165
ns
ns
d3
Delay time, FSX or BCLKX high to data valid (long
frame only)
C
= 0 pF to 150 pF
d4
L
t
t
Setup time, DR valid before BCLKR↓
50
50
ns
ns
su3
Hold time, DR valid after BCLKR or BCLKX↓
h3
Setup time, FSR or FSX high before BCLKR or
BCLKX↓
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
t
50
ns
ns
su4
h4
Hold time, FSX or FSR high after BCLKX or
BCLKR↓
Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)
t
100
Long-frame sync pulse (from 3- to
8-bit clock periods long)
t
t
Hold time, frame sync high after bit clock↓
100
160
ns
ns
h5
Pulse duration of the frame sync pulse (low level)
64 kbps operating mode
w5
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
Nominal input value for an LSTTL load is 18 kΩ.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
filter gains and tracking errors
‡
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
TP3064A, TP13064A 3.17 dBm0
TP3067A, TP13067A 3.14 dBm0
2.501
2.492
Maximum peak transmit
overload level
Transmit filter gain, absolute (at 0 dBm0)
T
= 25°C
–0.15
0.15
–40
–30
–26
–0.1
0.15
0.05
0
dB
A
f = 16 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
–1.8
–0.15
–0.35
–0.8
Transmit filter gain, relative to absolute
f = 300 Hz to 3000 Hz
f = 3300 Hz
dB
f = 3400 Hz
f = 4000 Hz
–14
–32
f ≥ 4600 Hz (measure response from 0 Hzto4000Hz)
Absolute transmit gain variation with
temperature and supply voltage
Relative to absolute transmit gain
–0.1
0.1
dB
dB
dB
dB
dB
Sinusoidal test method; Reference level = –10 dBm0
3 dBm0 ≥ input level ≥ –40 dBm0
±0.2
±0.4
±0.8
Transmit gain tracking error with level
Receive filter gain, absolute (at 0 dBm0)
Receive filter gain, relative to absolute
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
Input is digital code sequence for 0 dBm0 signal,
–0.15
0.15
T
A
= 25°C
f = 0 Hz to 3000 Hz,
f = 3300 Hz
T
A
= 25°C
–0.15
–0.35
–0.8
0.15
0.05
0
f = 3400 Hz
f = 4000 Hz
–14
Absolute receive gain variation with temperature
and supply voltage
T
A
= full range,
See Note 4
–0.1
0.1
Sinusoidal test method; reference input PCM code
corresponds to an ideally encoded –10 dBm0 signal
3 dBm0 ≥ input level ≥ –40 dBm0
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
±0.2
±0.4
±0.8
±2.5
Receive gain tracking error with level
Receive output drive voltage
dB
V
R
= 10 kΩ
L
Pseudo-noise-test method; reference input PCM
code corresponds to an ideally encoded –10 dBm0
signal
Transmit and receive gain tracking error with
level (A-law, CCITT C712)
dB
3 dBm0 ≥ input level ≥ –40 dBm0
–40 dBm0 > input level ≥ –50 dBm0
–50 dBm0 > input level ≥ –55 dBm0
±0.25
±0.3
±0.45
†
‡
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
A
CC
BB
Absolute rms signal levels are defined as follows: V = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with R = 600 Ω.
I
L
NOTE 4: Full range for the TP3064A and TP3067A is 0°C to 70°C. Full range for the TP13064A and TP13067A is –40°C to 85°C.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
envelope delay distortion with frequency
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
315
220
145
75
UNIT
Transmit delay, absolute (at 0 dBm0)
f = 1600 Hz
f = 500 Hz to 600 Hz
290
195
120
50
µs
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
Transmit filter gain, relative to absolute
20
40
µs
55
75
80
105
155
200
130
180
–25
–20
70
Receive delay, absolute (at 0 dBm0)
Receive delay, relative to absolute
µs
µs
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
–40
–30
90
125
175
100
140
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
CC
BB
A
noise
†
PARAMETER
TEST CONDITIONS
= 0 V
MIN TYP
MAX
UNIT
TP3064A,
TP13064A
Transmit noise, C-message weighted
V
V
9
14 dBrnC0
FXI
Transmit noise, psophometric weighted
(see Note 5)
TP3067A,
TP13067A
= 0 V
–78
2
–75 dBm0p
FXI
TP3064A,
TP13064A
PCM code equals alternating positive
and negative zero
Receive noise, C-message weighted
Receive noise, psophometric weighted
Noise, single frequency
4
dBrnC0
TP3067A,
TP13067A
PCM code equals positive zero
–86
–83 dBm0p
–53 dBm0
VFXI+ = 0 V,
f = 0 kHz to 100 kHz,
Loop-around measurement
†
All typical values are at V
= 5 V, V
= –5 V, and T = 25°C.
BB A
CC
NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite signals on the transmit side are below –55 dBm0.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
power supply rejection
PARAMETER
TEST CONDITIONS
f = 0 Hz to 4 kHz
= 5 V + 100 mVrms,
MIN
38
38
40
35
35
40
40
40
40
38
38
40
MAX
UNIT
A-law
dB
V
CC
VFXI+ = –50 dBm0
†
†
†
†
Positive power-supply rejection, transmit
Negative power-supply rejection, transmit
Positive power-supply rejection, receive
Negative power-supply rejection, receive
µ-law
dBC
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
f = 0 Hz to 4 kHz
f = 4 kHz to 50 kHz
dB
A-law
dB
V
BB
= –5 V + 100 mVrms,
VFXI+ = –50 dBm0
µ-law
dBC
dB
A-law
dB
PCM code equals positive zero,
µ-law
dBC
dB
V
CC
= 5 V + 100 mVrms
A-law
dB
PCM code equals positive zero,
= –5 V + 100 mVrms
µ-law
dBC
dB
V
BB
0 dBm0, 300-Hz to 3400-Hz input applied to DR
(measure individual image signals at VFRO)
–30
dB
dB
Spurious out-of-band signals at the
channel output (VFRO)
f = 4600 Hz to 7600 Hz
f = 7600 Hz to 100 kHz
–33
–40
†
The unit dBC applies to C-message weighting.
distortion
PARAMETER
TEST CONDITIONS
Level = 3 dBm0
MIN
33
36
29
30
14
15
MAX
UNIT
Level = 0 dBm0 to –30 dBm0
Transmit
Receive
Transmit
Receive
†
dBC
‡
Level = –40 dBm0
Signal-to-distortion ratio, transmit or receive half-channel
Level = –55 dBm0
Single-frequency distortion products, transmit
Single-frequency distortion products, receive
–46
–46
dB
dB
Loop-around measurement,
VFXI+ = –4 dBm0 to –21 dBm0,
Intermodulation distortion
–41
dB
Two frequencies in the range of 300 Hz to 3400 Hz
Pseudo noise test method
Level = –3 dBm0
33
36
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
Signal-to-distortion ratio, transmit half-channel (A-Law)
(CCITT G.714)§
33.5
28.5
13.5
33
dB
Level = –40 dBm0
Level = –55 dBm0
Level = –3 dBm0
Level = –6 dBm0 to –27 dBm0
Level = –34 dBm0
36
Signal-to-distortion ratio, receive half-channel (A-law)
(CCITT G.714)§
34.2
30
dB
Level = –40 dBm0
Level = –55 dBm0
15
†
‡
§
The unit dBC applies to C-message weighting.
Sinusoidal test method (see Note 6)
Pseudo-noise test method
NOTE 6: The TP13064A and TP3064A are measured using a C-message filter. The TP13067A and TP3067A are measured using a
psophometric weighted filter.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
crosstalk
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
–75
–72
UNIT
dB
Crosstalk, transmit to receive
f = 300 Hz to 3000 Hz, DR at steady PCM code
–90
–90
Crosstalk, receive to transmit (see Note 7)
VFXI = 0 V,
f = 300 Hz to 3000 Hz
dB
†
All typical values are at V
= 5 V, V
BB
= –5 V, and T = 25°C.
CC
A
NOTE 7: Receive-to-transmit crosstalk is measured with a –50 dBm0 activation signal applied to VFXI+.
power amplifiers
PARAMETER
TEST CONDITIONS
R connected between VPO+ and VPO –
L
MIN
MAX
UNIT
Balanced load,
R
R
R
R
= 600 Ω
= 1200 Ω
= 30 kΩ
= 600 Ω
3.3
3.5
4
Maximum 0 dBm0 rms level for better than ±0.1 dB
linearity over the range if –10 dBm0 to 3 dBm0
L
L
L
L
V
rms
Signal/distortion
50
dB
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
t
d2
t
d3
TSX
20%
20%
t
r1
t
w2
t
f1
f
clock(M)
80%
80%
80%
MCLKX
MCLKR
20%
20%
t
su1
t
w1
80%
80%
80%
BCLKX
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
FSX
20%
t
d3
t
d1
80%
1
2
3
4
5
6
7
8
DX
20%
80%
80%
20%
BCLKR
20%
20%
1
2
3
4
5
6
7
8
t
h2
t
su4
t
h4
80%
FSR
20%
t
su3
t
h3
t
h3
1
2
3
4
5
6
7
8
DR
Figure 1. Short-Frame Sync Timing
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
t
t
r1
w1
f
clock(M)
t
f1
t
w2
MCLKX
MCLKR
80%
20%
80%
20%
80%
20%
20%
t
f2
t
su1
t
w3
t
r2
t
su1
t
w4
80%
1
80%
80%
80%
20%
BCLKX
FSX
2
3
4
5
6
7
8
9
20%
20%
20%
t
h1
f
clock(B)
t
t
h5
su2
80%
20%
t
d4
t
d1
t
d4
t
d3
80%
20%
DX
1
2
3
4
5
6
7
8
t
w3
t
d3
t
w4
80%
80%
80%
20%
BCLKR
20%
20%
20%
20%
t
h1
t
su2
t
h5
80%
20%
80%
FSR
DR
t
su3
t
h3
t
h3
1
2
3
4
5
6
7
8
Figure 2. Long-Frame Sync Timing
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
system reliability and design considerations
TP306xA, TP1306xA system reliability and design considerations are described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP306xA and TP1306xA devices are heavily protected against latch-up, it is still possible to
cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals.
Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative
supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted
into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP306xA- or TP1306xA-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.
device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure that no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply V (most negative voltage).
BB
4. Apply V
(most positive voltage).
CC
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power down condition.
8. Apply FS synchronization pulses.
9. Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
V
CC
DGND
V
BB
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3064A, TP3067A, TP13064A, and TP13067A devices when power
is first applied, placing it into the power-down mode. DX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.
synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PDN is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies
MASTER-CLOCK FREQUENCY SELECTED
BCLKR/CLKSEL
TP3064A, TP13064A
TP3067A, TP13067A
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3064A and TP13064A, 1.536 MHz or 1.544 MHz for the TP3067A and TP13067A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PDN. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.
short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX
enables the 3-state output buffer, DX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables DX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the remaining bits. The short-frame sync pulse can be utilized in either the
synchronous or asynchronous mode.
long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships, as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a short-
or long-frame sync pulse is being used. For 64-kHz operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the DX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse may be used in either the synchronous or asynchronous mode.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
PRINCIPLES OF OPERATION
transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eight-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per µ-law (TP3064A and TP13064A) or A-law (TP3067A
and TP13067A) coding conventions, the ADC is a companding type. A precision voltage reference provides an
input overload of nominally 2.5-V peak. The sampling of the filter output is controlled by the FSX frame sync
pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and
shifted out through DX at the next FSX pulse. The total encoding delay is approximately 290 µs. Any offset
voltage due to the filters or comparator is cancelled by sign bit integration (see Table 2).
Table 2. Encoding Format at DX Output
TP3067A, TP13067A
TP3064A, TP13064A
A-Law
µ-Law
(INCLUDES EVEN-BIT INVERSION)
V = + Full scale
I
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V = 0
I
V = – Full scale
I
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is µ-law (TP3064A and TP13064A) or A-law (TP3067A and TP13067A), and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post filter with its output at VFRO. The receive section is unity gain, but gain can be
added by using the power amplifiers. At FSR, the data at DR is clocked in on the falling edge of the next eight
BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10-µs later the
decoder DAC output is updated. The decoder delay is about 10 µs (decoder update) plus 110 µs (filter delay)
plus 62.5 µs (1/2 frame), or a total of approximately180 µs.
receive power amplifiers
Two inverting-mode power amplifiers are provided for directly driving a match-line interface transformer. The
gain of the first power amplifier can be adjusted to boost the ±2.5-V peak output signal from the receive filter
uptothe±3.3-Vpeakintoanunbalanced300-Ω load, or±4Vintoanunbalanced15-kΩ load. Thesecondpower
amplifier is internally connected in the unity-gain inverting mode to give 6 dB of signal gain for balanced loads.
Maximum power transfer to a 600-Ω subscriber line termination is obtained by differentially driving a balanced
transformer with √2:1 turns ratio, as shown in Figure 3. A total peak power of 15.6 dBm can be delivered to the
load plus termination.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
APPLICATION INFORMATION
power supplies
While the pins of the TP1306xA and TP306xA families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. V
and V
CC
BB
supplies should be decoupled by connecting 0.1-µF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to V and V
.
BB
CC
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to V
CC
and V with 10-µF capacitors.
BB
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C – SEPTEMBER 1992 –REVISED JULY 1996
APPLICATION INFORMATION
600 Ω
2
Hybrid
1
1
300 Ω
2
Z
BAL
5 V
–5 V
300 Ω
R2
0.1 µF
0.1 µF
6
20
GND
V
BB
V
CC
1
3
4
5
19
18
VPO+
VPO–
VFXI+
VFXI–
R1
TP3064A
TP3067A
TP13064A
TP13067A
R3
R4
17
VPI
GSX
16
15
14
13
12
11
ANLG LOOP
VFRO
TSX
FSX
DX
7
8
FSR
DR
BCLKR
9
BCLKX
MCLKX
10
MCLKR/PDN
R1 + R2
R2
,
,
(R1 + R2) ≥ 10 kΩ
R4 ≥ 10 kΩ
NOTES: A. Transmit gain = 20 y log
B. Receive gain = 20 y log
2 × R3
R4
Figure 4. Typical Synchronous Application
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1998, Texas Instruments Incorporated
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