TPA032D02DCAR_技术文档

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

DCA PACKAGE

(TOP VIEW)

D

Extremely Efficient Class-D Stereo

Operation

D

Drives L and R Channels

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

SHUTDOWN

MUTE

COSC

AGND

RINN

2

10-W BTL Output Into 4 Ω From 12 V

32-W Peak Music Power

3

AGND

LINN

LINP

LCOMP

AGND

4

Fully Specified for 12-V Operation

Low Shutdown Current

5

RINP

6

RCOMP

FAULT0

FAULT1

7

Thermally-Enhanced PowerPAD Surface-

Mount Packaging

8

V

DD

9

LPV

RPV

DD

D

Thermal and Under-Voltage Protection

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

LOUTP

PGND

LOUTN

ROUTP

PGND

ROUTN

description

The TPA032D02 is a monolithic power IC stereo

audio amplifier that operates in extremely efficient

Class-D operation, using the high switching speed

of power DMOS transistors to replicate the analog

input signal through high-frequency switching of

the output stage. This allows the TPA032D02 to

be configured as a bridge-tied load (BTL) amplifier

capable of delivering up to 10 W of continuous

average power into a 4-Ω load at 0.5% THD+N

from a 12-V power supply in the high-fidelity audio

frequency range (20 Hz to 20 kHz). A BTL

configuration eliminates the need for external

coupling capacitors on the output. A chip-level

shutdown control is provided to limit total supply

current to 20 µA, making the device ideal for

battery-powered applications.

LPV

RPV

DD

V

REG

NC

V

CC

NC

CC

NC

AGND

PV

V2P5

PV

DD

VCP

NC

CP1

PGND

NC

CP2

NC − No internal connection

The output stage is compatible with a range of power supplies from 8 V to 14 V. Protection circuitry is included

to increase device reliability: thermal and under-voltage shutdown, with a status feedback terminal for use when

any error condition is encountered.

The high switching frequency of the TPA032D02 allows the output filter to consist of three small capacitors and

two small inductors per channel. The high switching frequency also allows for good THD+N performance.

The TPA032D02 is offered in the thermally enhanced 48-pin PowerPAD TSSOP surface-mount package

(designator DCA).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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Copyright  2000, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

schematic

FAULT1

FAULT0

CP1

CP2

VCP

PV

DD

LOUTN

LOUTP

ROUTN

ROUTP

2

•

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

Terminal Functions

TERMINAL

NAME

AGND

DESCRIPTION

NO.

3, 7, 20, Analog ground for Class-D analog circuitry

46, 47

COSC

CP1

48

24

Connect a capacitor from analog ground to this terminal to set the frequency of the ramp reference signal.

First diode node for charge pump

CP2

25

First inverter switching node for charge pump

FAULT0

FAULT1

LCOMP

LINN

42

Logic level fault0 output signal. Lower order bit of the two fault signals with open drain output.

Logic level fault1 output signal. Higher order bit of the two fault signals with open drain output.

Compensation capacitor terminal for left-channel Class-D amplifier

Class-D left-channel negative input

41

6

4

LINP

5

Class-D left-channel positive input

LOUTN

LOUTP

14, 15

10, 11

9, 16

2

Class-D amplifier left-channel negative output of H-bridge

Class-D amplifier left-channel positive output of H-bridge

Class-D amplifier left-channel power supply

LPV

DD

MUTE

Active-low TTL logic-level mute input signal. When MUTE is held low, the selected amplifier is muted. When MUTE

is held > high, the device operates normally. When the Class-D amplifier is muted, the low-side output transistors

are turned on, shorting the load to ground.

NC

18, 19, No connection

23, 26,

30, 31

PGND

12, 13

27

Power ground for left-channel H−bridge only

Power ground for charge pump only

36, 37

21, 28

43

Power ground for right-channel H-bridge only

PV

DD

V

DD

supply for charge-pump and gate drive circuitry

RCOMP

RINN

Compensation capacitor terminal for right-channel Class-D amplifier

Class-D right-channel negative input

45

RINP

44

Class-D right-channel positive input

RPV

DD

33, 40

34, 35

38, 39

1

Class-D amplifier right-channel power supply

ROUTN

Class-D amplifier right-channel negative output of H-bridge

Class-D amplifier right-channel positive output of H-bridge

ROUTP

SHUTDOWN

Active-low TTL logic-level shutdown input signal. When SHUTDOWN is held low, the device goes into shutdown

mode. When SHUTDOWN is held high, the device operates normally.

V

32

17

29

22

8

5V supply to logic. This terminal is typically connected to V REG.

CC

REG

5-V regulator output. This terminal requires a 1-µF capacitor to ground for stability reasons.

2.5V internal reference bypass. This terminal requires a capacitor to ground.

CC

V2P5

VCP

Connect a capacitor from this terminal to power ground to provide storage for the charge pump output voltage.

V

DD

V

bias supply for analog circuitry. This terminal needs to be well filtered to prevent degrading the device

DD

performance.

3

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

Class-D amplifier faults

Table 1. Class-D Amplifier Fault Table

FAULT 0

FAULT 1

DESCRIPTION

1

0

1

No fault. The device is operating normally.

Charge pump under-voltage lock-out (VCP-UV) fault. All low-side transistors are turned on, shorting the load to

ground. Once the charge pump voltage is restored, normal operation resumes, but FAULT1 is still active. This is not

a latched fault, however. FAULT1 is cleared by cycling MUTE, SHUTDOWN, or the power supply.

0

Thermal fault. All the low-side transistors are turned on, shorting the load to ground. Once the junction temperature

drops 20°C, normal operation resumes (not a latched fault). But the FAULTx terminals are still set and are cleared

by cycling MUTE, SHUTDOWN, or the power supply.

AVAILABLE OPTIONS

PACKAGED DEVICES

†

T

A

TSSOP

(DCA)

−40°C to 125°C

TPA032D02DCA

†

The DCA package is available in left-ended tape and reel. To order

a taped and reeled part, add the suffix R to the part number (e.g.,

TPA032D02DCAR).

4

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

absolute maximum ratings over operating free-air temperature range, T = 25°C (unless otherwise

C

†

noted)

Supply voltage, (V , PV , LPV , RPV

Logic supply voltage, (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V

DD

CC

DD

Input voltage, V (MUTE, MODE, SHUTDOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

I

Output current, I (FAULT0, FAULT1), open drain terminated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA

O

Supply/load voltage, (FAULT0, FAULT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Charge pump voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PV

+ 20 V

CP

DD

Continuous H-bridge output current (1 H-bridge conducting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 A

Pulsed H-Bridge output current, each output, I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A

max

Continuous V REG output current, I (V REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA

CC

O

CC

Continuous total power dissipation, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

C

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

J

Operating case temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 260°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle v 2%

DISSIPATION RATING TABLE

DERATING FACTOR

‡

T

≤ 25°C

T

A

= 70°C

T = 85°C

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

A

DCA

5.6 W

44.8 mW/°C

3.6 W 2.9 W

‡

Please see the Texas Instruments document, PowerPAD Thermally Enhanced Package Application

Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data

was measured on a PCB layout based on the information in the section entitled Texas Instruments

Recommended Board for PowerPAD on page 33 of the before mentioned document.

recommended operating conditions

MIN NOM

MAX

14

UNIT

Supply voltage, V , PV , LPV , RPV

DD

8

4.5

2

V

DD

Logic supply voltage, V

5.5

CC

High-level input voltage, V (MUTE, SHUTDOWN)

IH

V

DD

+ 0.3 V

0.8

Low-level input voltage, V (MUTE, SHUTDOWN)

IL

−0.3

Audio inputs, LINN, LINP, RINN, RINP, differential input voltage

PWM frequency

1

V

RMS

kHZ

100

250

500

5

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

electrical characteristics Class-D amplifier, V

= PV

= LPV

= RPV

= 12 V, R = 4 Ω to 8 Ω,

DD

DD L

T = 25°C, See Figure 1 (unless otherwise noted)

A

PARAMETER

TEST CONDITIONS

= PV = xPV = 11 V to 13 V

MIN

TYP

−40

25

MAX

UNIT

dB

Power supply rejection ratio

Supply current

V

DD

DD DD

I

No output filter connected

MUTE = 0 V

35

18

30

mA

µA

DD

Supply current, mute mode

Supply current, shutdown mode

10

DD(Mute)

DD(S/D)

SHUTDOWN = 0 V

20

High-level input current (MUTE, MODE,

SHUTDOWN)

|I

|

V

= 5.25 V

= −0.3 V

= 0.5 A

10

µA

IH

Low-level input current (MUTE, MODE,

SHUTDOWN)

|

IL

Static drain-to-source on-state resistance

(high-side + low-side FETs)

r

I

720

800

mΩ

DS(on)

DD

Matching, high-side to high-side, low-side to

low-side, same channel

95%

98%

operating characteristics, Class-D amplifier, V

= PV

= LPV

= RPV

= 12 V, R = 4 Ω,

DD L

DD

T = 25°C, See Figure 1 (unless otherwise noted)

A

PARAMETER

TEST CONDITIONS

f = 1 kHz,

MIN

TYP

MAX

UNIT

THD = 0.5%, per channel,

Device soldered on PCB,

See Note 2

P

O

Output power

10

W

Efficiency

P

O

= 10 W, f = 1 kHz

77%

25

A

V

Gain

dB

Left/right channel gain matching

Noise floor

92%

20

95%

−60

80

dB

Dynamic range

Crosstalk

f = 1 kHz

−50

dB

Frequency response bandwidth, post output filter, −3 dB

Maximum output power bandwidth

20000

20

Hz

B

OM

kHz

kΩ

Z

I

Input impedance

10

NOTE 2: Output power is thermally limited, T = 23°C

A

6

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

operating characteristics, Class-D amplifier, V

= PV

= LPV

= RPV

= 12 V, R = 8 Ω,

DD L

DD

T = 25°C, See Figure 2 (unless otherwise noted)

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THD = 0.5%, per channel,

Device soldered on PCB,

See Note 2

P

O

Output power

7.5

W

Efficiency

P

O

= 7.5 W,

f = 1 kHz

85%

25

A

V

Gain

dB

Left/right channel gain matching

Noise floor

92%

20

95%

−60

80

dB

Dynamic range

Crosstalk

f = 1 kHz

−50

dB

Frequency response bandwidth, post output filter, −3 dB

Maximum output power bandwidth

20000

20

Hz

B

OM

kHz

kΩ

Z

I

Input impedance

10

NOTE 2: Output power is thermally limited, T = 85°C

A

operating characteristics, V

5-V regulator, T = 25°C (unless otherwise noted)

A

CC

PARAMETER

TEST CONDITIONS

MIN

4.5

90

TYP

MAX

UNIT

V

= PV

DD

= LPV

= RPV

= 8 V to 14 V,

DD

= 0 to 90 mA

DD

V

O

Output voltage

5.5

I

O

†

I

Short-circuit output current

V

= PV

= LPV

= RPV

= 8 V to 14 V

mA

OS

DD DD

DD

†

Pulse width must be limited to prevent exceeding the maximum operating virtual junction temperature of 150°C.

thermal shutdown

PARAMETER

TEST CONDITIONS

MIN

TYP

165

30

MAX

UNIT

°C

Thermal shutdown temperature

Thermal shutdown hysteresis

°C

7

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

PARAMETER MEASUREMENT INFORMATION

42

FAULT0

41

FAULT1

1

SHUTDOWN

MUTE

V

CC

V

CC

REG

15 µH

14,15

2

LOUTN

0.22 µF

1 µF

4 Ω

9,16

LPV

DD

12 V

10,11

29

LOUTP

V2P5

1 µF

15 µH

5

4

LINP

LINN

Balanced

Differential

Input Signal

1 µF

6

LCOMP

RCOMP

1 µF

43

1000 pF

8

12 V

V

DD

48

COSC

17

1000 pF

To V

CC

V

CC

REG

0.1 µF

1 µF

44

RINP

RINN

Balanced

Differential

Input Signal

24

CP1

45

47 nF

1 µF

25

22

CP2

VCP

33,40

RPV

DD

12 V

3, 7,20,46,47

AGND

PGND

12,13,27,36,37

21, 28

0.1 µF

PV

DD

12 V

15 µH

34,35

38,39

ROUTN

ROUTP

500 kΩ

0.22 µF

1 µF

4 Ω

32

To V REG

CC

V

CC

100 kΩ

15 µH

Figure 1. 12-V, 4-Ω Test Circuit

8

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

PARAMETER MEASUREMENT INFORMATION

42

FAULT0

41

FAULT1

1

SHUTDOWN

MUTE

V

REG

30 µH

CC

14,15

2

LOUTN

CC

0.1 µF

1 µF

8 Ω

9,16

LPV

DD

12 V

10,11

29

LOUTP

V2P5

1 µF

30 µH

5

4

LINP

LINN

Balanced

Differential

Input Signal

1 µF

6

LCOMP

RCOMP

1 µF

43

1000 pF

8

12 V

V

DD

48

COSC

17

1000 pF

To V

CC

V

CC

REG

0.1 µF

1 µF

44

RINP

RINN

Balanced

Differential

Input Signal

24

CP1

45

47 nF

1 µF

25

22

CP2

VCP

33,40

RPV

DD

12 V

3, 7,20,46,47

AGND

PGND

12,13,27,36,37

21, 28

0.1 µF

PV

DD

12 V

30 µH

34,35

38,39

ROUTN

ROUTP

500 kΩ

0.1 µF

1 µF

8 Ω

32

To

REG

V

CC

V

CC

100 kΩ

30 µH

Figure 2. 12-V, 8-Ω Test Circuit

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

1

2

To System

Control

SHUTDOWN

MUTE

V

CC

REG

9,16

LPV

DD

12 V

1 µF

100 kΩ

10 µF

100 kΩ

42

FAULT0

FAULT1

1 µF

To System

Control

41

5

4

LINP

LINN

Left Class-D Balanced

Differential Input

Signal

15 µH

14,15

LOUTN

1 µF

0.22 µF

6

LCOMP

RCOMP

1 µF

4 Ω

43

1000 pF

10,11

LOUTP

V2P5

15 µH

48

29

COSC

8

1000 pF

1 µF

V

DD

12 V

1 µF

44

17

RINP

RINN

Right Class-D Balanced

Differential Input

Signal

V

CC

REG

CC

45

1 µF

33,40

RPV

DD

12 V

1 µF

10 µF

3, 7,20,46,47

AGND

PGND

12,13,27,36,37

24

21, 28

CP1

PV

DD

12 V

47 nF

1 µF

25

22

CP2

VCP

0.1 µF

15 µH

34,35

ROUTN

0.22 µF

1 µF

4 Ω

0.1 µF

32

V

CC

V

DD

38,39

ROUTP

500 kΩ

15 µH

To

V

CC

REG

0.1 µF

100 kΩ

NOTE A:

= power ground and

= analog ground

Figure 3. TPA032D02 Typical Configuration Application Circuit

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

input capacitor, C

I

In the typical application an input capacitor, C , is required to allow the amplifier to bias the input signal to the

I

proper dc level for optimum operation. In this case, C and Z , the TPA032D02’s input resistance forms a

I

high-pass filter with the corner frequency determined in equation 8.

−3 dB

1

f

+

(8)

c(highpass)

2pZ C

I I

Z is nominally 10 kΩ

I

f

c

The value of C is important to consider as it directly affects the bass (low frequency) performance of the circuit.

I

Consider the example where the specification calls for a flat bass response down to 40 Hz. Equation 8 is

reconfigured as equation 9.

1

C +

I

(9)

2pZ f

c

I

In this example, C is 0.40 µF so one would likely choose a value in the range of 0.47 µF to 1 µF. A low-leakage

I

tantalum or ceramic capacitor is the best choice for the input capacitors. When polarized capacitors are used,

the positive side of the capacitor should face the amplifier input, as the dc level there is held at 1.5 V, which is

likely higher than the source dc level. Please note that it is important to confirm the capacitor polarity in the

application.

differential input

The TPA032D02 has differential inputs to minimize distortion at the input to the IC. Since these inputs nominally

sit at 1.5 V, dc-blocking capacitors are required on each of the four input terminals. If the signal source is

single-ended, optimal performance is achieved by treating the signal ground as a signal. In other words,

reference the signal ground at the signal source, and run a trace to the dc-blocking capacitor, which should be

located physically close to the TPA032D02. If this is not feasible, it is still necessary to locally ground the unused

input terminal through a dc-blocking capacitor.

power supply decoupling, C

S

The TPA032D02 is a high-performance Class-D CMOS audio amplifier that requires adequate power supply

decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling

also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling

is achieved by using two capacitors of different types that target different types of noise on the power supply

leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-

resistance (ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device’s various V

DD

leads, works best. For filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF

or greater placed near the audio power amplifier is recommended.

The TPA032D02 has several different power supply terminals. This was done to isolate the noise resulting from

high-current switching from the sensitive analog circuitry inside the IC.

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

mute and shutdown modes

The TPA032D02 employs both a mute and a shutdown mode of operation designed to reduce supply current,

, to the absolute minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN

I

DD

input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN

low causes the outputs to mute and the amplifier to enter a low-current state, I = 20 µA. Mute mode alone

DD

reduces I

to 10 mA.

DD

using low-ESR capacitors

Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)

capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this

resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this

resistance the more the real capacitor behaves like an ideal capacitor.

output filter components

The output inductors are key elements in the performance of the class-D audio amplifier system. It is important

that these inductors have a high enough current rating and a relatively constant inductance over frequency and

temperature. The current rating should be higher than the expected maximum current to avoid magnetically

saturating the inductor. When saturation occurs, the inductor loses its functionality and looks like a short circuit

to the PWM signal, which increases the harmonic distortion considerably.

A shielded inductor may be required if the class-D amplifier is placed in an EMI sensitive system; however, the

switching frequency is low for EMI considerations and should not be an issue in most systems. The dc series

resistance of the inductor should be low to minimize losses due to power dissipation in the inductor, which

reduces the efficiency of the circuit.

Capacitors are important in attenuating the switching frequency and high frequency noise, and in supplying

some of the current to the load. It is best to use capacitors with low equivalent-series-resistance (ESR). A low

ESR means that less power is dissipated in the capacitor as it shunts the high-frequency signals. Placing these

capacitors in parallel also parallels their ESR, effectively reducing the overall ESR value. The voltage rating is

also important, and, as a rule of thumb, should be 2 to 3 times the maximum rms voltage expected to allow for

high peak voltages and transient spikes. These output filter capacitors should be stable over temperature since

large currents flow through them.

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

efficiency of class-D vs linear operation

Amplifier efficiency is defined as the ratio of output power delivered to the load to power drawn from the supply.

In the efficiency equation below, P is power across the load and P

is the supply power.

L

SUP

P

L

Efficiency + h +

P

SUP

A high-efficiency amplifier has a number of advantages over one with lower efficiency. One of these advantages

is a lower power requirement for a given output, which translates into less waste heat that must be removed

from the device, smaller power supply required, and increased battery life.

Audio power amplifier systems have traditionally used linear amplifiers, which are well known for being

inefficient. Class-D amplifiers were developed as a means to increase the efficiency of audio power amplifier

systems.

A linear amplifier is designed to act as a variable resistor network between the power supply and the load. The

transistors operate in their linear region and voltage that is dropped across the transistors (in their role as

variable resistors) is lost as heat, particularly in the output transistors.

The output transistors of a class-D amplifier switch from full OFF to full ON (saturated) and then back again,

spending very little time in the linear region in between. As a result, very little power is lost to heat because the

transistors are not operated in their linear region. If the transistors have a low on-resistance, little voltage is

dropped across them, further reducing losses. The ideal class-D amplifier is 100% efficient, which assumes that

both the on-resistance (r

) and the switching times of the output transistors are zero.

DS(on)

the ideal class-D amplifier

To illustrate how the output transistors of a class-D amplifier operate, a half-bridge application is examined first

(see Figure 4).

V

DD

M1

I

L

I

OUT

V

A

+

L

V

OUT

R

C

L

M2

C

L

−

Figure 4. Half-Bridge Class-D Output Stage

Figures 5 and 6 show the currents and voltages of the half-bridge circuit. When transistor M1 is on and M2 is

off, the inductor current is approximately equal to the supply current. When M2 switches on and M1 switches

off, the supply current drops to zero, but the inductor keeps the inductor current from dropping. The additional

inductor current is flowing through M2 from ground. This means that V (the voltage at the drain of M2, as shown

A

in Figure 4) transitions between the supply voltage and slightly below ground. The inductor and capacitor form

a low-pass filter, which makes the output current equal to the average of the inductor current. The low-pass filter

averages V , which makes V

equal to the supply voltage multiplied by the duty cycle.

A

OUT

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

the ideal class-D amplifier (continued)

Control logic is used to adjust the output power, and both transistors are never on at the same time. If the output

voltage is rising, M1 is on for a longer period of time than M2.

Inductor Current

Output Current

Supply Current

0

M1 on M1 off M1 on

M2 off M2 on M2 off

Time

Figure 5. Class-D Currents

V

DD

V

A

V

OUT

0

M1 on M1 off M1 on

M2 off M2 on M2 off

Time

Figure 6. Class-D Voltages

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

the ideal class-D amplifier (continued)

Given these plots, the efficiency of the class-D device can be calculated and compared to an ideal linear

amplifier device. In the derivation below, a sine wave of peak voltage (V ) is the output from an ideal class-D

P

and linear amplifier and the efficiency is calculated.

CLASS-D

LINEAR

V

P

V

+

V

+

L(rms)

V

Ǹ

2

V

I

V

DD

L(rms)

P

_Averageǒ_IǓ ₊

P +

+

DD

L

V

R

L

2 R

L

V

2

p

P

_Averageǒ_IǓ ₊

P + V I

L

DD

R

L

V

DD

R

P

2

p

_Averageǒ_IǓ

_Averageǒ_IǓ ₊

P

+ V

P

+ V

SUP

DD

SUP

DD

L

V

I

V

P

DD L(rms)

L(rms)

L

P

+

Efficiency + h +

SUP

V

P

DD

SUP

V 2

P

2R

P

L

Efficiency + h +

Efficiency + h + V

DD

P

V

SUP

2

P

p

R

L

V

p

P

Efficiency + h + 1

Efficiency + h +

4

V

DD

In the ideal efficiency equations, assume that V = V , which is the maximum sine wave magnitude without

P

DD

clipping. Then, the highest efficiency that a linear amplifier can have without clipping is 78.5%. A class-D

amplifier, however, can ideally have an efficiency of 100% at all power levels.

The derivation above applies to an H-bridge as well as a half-bridge. An H-bridge requires approximately twice

the supply current but only requires half the supply voltage to achieve the same output power—factors that

cancel in the efficiency calculation. The H-bridge circuit is shown in Figure 7.

V

DD

V

DD

M1

M4

I

L

I

OUT

V

OUT

+

−

V

A

L

R

L

C

L

M3

M2

Figure 7. H-Bridge Class-D Output Stage

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

losses in a real-world class-D amplifier

Losses make class-D amplifiers nonideal, and reduce the efficiency below 100%. These losses are due to the

output transistors having a nonzero r

, and rise and fall times that are greater than zero.

DS(on)

The loss due to a nonzero r

nonswitching times, when the transistor is on (saturated). Any r

is called conduction loss, and is the power lost in the output transistors at

DS(on)

above 0 Ω causes conduction loss.

DS(on)

Figure 8 shows an H-bridge output circuit simplified for conduction loss analysis and can be used to determine

new efficiencies with conduction losses included.

V

DD

= 12 V

r

0.36 Ω

5 MΩ

r

DS(off)

DS(on)

R

L

4 Ω

r

0.36 Ω

r

DS(on)

DS(off)

Figure 8. Output Transistor Simplification for Conduction Loss Calculation

The power supplied, P , is determined to be the power output to the load plus the power lost in the transistors,

SUP

assuming that there are always two transistors on.

P

L

Efficiency + h +

P

SUP

2

I R

L

Efficiency + h +

2

I 2r

) I R

DS(on)

L

R

L

Efficiency + h +

2r

) R

DS(on)

L

_{Efficiency + h + 95%}ǒ_{at all output levels r}

_{+ 0.1 Ω, R + 4 Ω}Ǔ

DS(on)

L

_{Efficiency + h + 85%}ǒ_{at all output levels r}

_{+ 0.36 Ω, R + 4 Ω}Ǔ

L

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

losses in a real-world class-D amplifier (continued)

Losses due to rise and fall times are called switching losses. A diagram of the output, showing switching losses,

is shown in Figure 9.

1

f

SW

t

=

+

t

SW

SWon

SWoff

Figure 9. Output Switching Losses

Rise and fall times are greater than zero for several reasons. One is that the output transistors cannot switch

instantaneously because (assuming a MOSFET) the channel from drain to source requires a specific period

of time to form. Another is that transistor gate-source capacitance and parasitic resistance in traces form RC

time constants that also increase rise and fall times.

Switching losses are constant at all output power levels, which means that switching losses can be ignored at

high power levels in most cases. At low power levels, however, switching losses must be taken into account

when calculating efficiency. Switching losses are dominated by conduction losses at the high output powers,

but should be considered at low powers. The switching losses are automatically taken into account if you

consider the quiescent current with the output filter and load.

class-D effect on power supply

Efficiency calculations are an important factor for proper power supply design in amplifier systems. Table 2

shows Class-D efficiency at a range of output power levels (per channel) with a 1-kHz sine wave input. The

maximum power supply draw from a stereo 10-W per channel audio system with 4-Ω loads and a 12-V supply

is almost 26 W. A similar linear amplifier such as the TPA032D02 has a maximum draw of greater than 50 W

under the same circumstances.

Table 2. Efficiency vs Output Power in 12-V 4-Ω H-Bridge Systems

Output Power (W)

Efficiency (%)

Peak Voltage (V)

Internal Dissipation (W)

0.5

2

41.7

66.7

75.1

78

2

4

0.7

1.0

5

6.32

8

1.66

2.26

2.84

8

†

8.94

10

77.9

†

High peak voltages cause the THD to increase

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

class-D effect on power supply (continued)

There is a minor power supply savings with a class-D amplifier versus a linear amplifier when amplifying sine

waves. The difference is much larger when the amplifier is used strictly for music. This is because music has

much lower RMS output power levels, given the same peak output power (see Figure 10); and although linear

devices are relatively efficient at high RMS output levels, they are very inefficient at mid-to-low RMS power

levels. The standard method of comparing the peak power to RMS power for a given signal is crest factor, whose

equation is shown below. The lower RMS power for a set peak power results in a higher crest factor

P_PK

Crest Factor + 10 log

P_rms

P

PK

P

RMS

Time

Figure 10. Audio Signal Showing Peak and RMS Power

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

class-D EVM power supply decoupling data

The decoupling capacitance required will depend upon the application. Pads and through-holes have been

provided on the EVM for the addition of bulk capacitance (see the schematic). A plot showing the impact of

various levels of bulk capacitance on the voltage ripple on the power supply line is shown in Figure 11. This ripple

is maximum at higher frequency. The figure shows worst-case voltage ripple for a 20-kHz, 10-W output into a

4-Ω load. In all cases, two 10-µF and one 1-µF ceramic chip capacitors were decoupling the power supply signal

from the EVM. The 1-µF unit was placed immediately adjacent to the IC power pins, and the 10-µF units were

placed adjacent to each other a little farther out.

The upper trace shows the ripple when only these capacitors are used. The middle trace shows the impact of

an additional 330-µF aluminum electrolytic capacitor rated at 25 V, 90 mΩ, and for 755 mA at 100 kHz. In the

bottom trace, the 330-µF capacitor was replaced by a 390-µF aluminum electrolytic capacitor rated at 35 V, 65

mΩ, and for 1.2 A of 100 kHz ripple current.

The results indicate that for sensitive circuits where minimum voltage ripple is required, a larger bulk

capacitance with low ESR should be used. For systems that are contained and EMI is controlled, less

capacitance may be used. The difference in the level of distortion in the output signal was very small between

each level of decoupling, with the 20-µF bulk capacitance providing the least distortion. This is attributed to the

low ESR of the capacitor, which is only a few milliohms at the switching frequency of 250 kHz. The distortion

is made lower still by the parallel combination. Distortion of the output signal when only one 10-µF capacitor

is used is the same as for 20 µF. The difference is more noticeable on the power supply line, though the distortion

is increased only slightly more than with the 20-µF capacitor.

RIPPLE VOLTAGE

Time (10 µsec per division)

Figure 11. Power Supply Decoupling

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

crest factor and thermal considerations

A typical music CD requires 12 dB to 15 dB of dynamic headroom to pass the loudest portions without distortion

as compared with the average power output. From the TPA032D02 data sheet, one can see that when the

TPA032D02 is operating from a 12-V supply into a 4-Ω speaker that 20-W peaks are available. Converting watts

to dB:

P

20

1

W

_+ 10Logǒ Ǔ _{+ 6 dB}

P

+ 10Log ǒ Ǔ

(17)

dB

P

ref

Subtracting the crest factor restriction to obtain the average listening level without distortion yields:

(

)

6.0 dB * 18 dB + * 12 dB 15 dB crest factor

(

)

6.0 dB * 15 dB + * 9 dB 15 dB crest factor

(

6.0 dB * 12 dB + * 6 dB 12 dB crest factor

(

)

6.0 dB * 9 dB + * 3 dB 9 dB crest factor

(

6.0 dB * 6 dB + * 0 dB 6 dB crest factor

(

)

6.0 dB * 3 dB + 3 dB 3 dB crest factor

Converting dB back into watts:

PdBń10

P

+ 10

P

W

ref

(18)

+ 315 mW (18 dB crest factor)

+ 630 mW (15 dB crest factor)

+ 1.25 W (12 dB crest factor)

+ 2.5 W (9 dB crest factor)

+ 5 W (6 dB crest factor)

+ 10 W (3 dB crest factor)

This is valuable information to consider when attempting to estimate the heat dissipation requirements for the

amplifier system. Comparing the absolute worst case, which is 10 W of continuous power output with a 3 dB

crest factor, against 12 dB and 15 dB applications drastically affects maximum ambient temperature ratings for

the system. Using the power dissipation curves for a 12-V, 4-Ω system, the internal dissipation in the

TPA032D02 and maximum ambient temperatures are shown in Table 3.

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SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

APPLICATION INFORMATION

crest factor and thermal considerations (continued)

Table 3. TPA032D02 Power Rating, 12-V, 4-Ω, Stereo

PEAK OUTPUT POWER

(W)

POWER DISSIPATION

AVERAGE OUTPUT POWER

MAXIMUM AMBIENT

TEMPERATURE

(W/Channel)

20

10 W (3 dB)

5 W (6 dB)

2.84

1.66

1.12

0.87

0.7

23°C

75°C

2.5 W (9 dB)

100°C

111°C

118°C

123°C

1.25 W (12 dB)

630 mW (15 dB)

315 mW (18 dB)

0.6

The maximum ambient temperature depends on the heatsinking ability of the PCB system. Using the 0 CFM

2

data from the dissipation rating table, the derating factor for the DCA package with 6.9 in of copper area on

a multilayer PCB is 44.8 mW/°C. Converting this to Θ

:

JA

1

Θ

+

JA

Derating

(19)

1

0.0448

+ 22.3°CńW

To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are

per channel so the dissipated heat needs to be doubled for two channel operation. Given Θ , the maximum

JA

allowable junction temperature, and the total internal dissipation, the maximum ambient temperature can be

calculated with the following equation. The maximum recommended junction temperature for the TPA032D02

is 150 °C. The internal dissipation figures are taken from the Efficiency vs Output Power graphs.

T Max + T Max * Θ

P

(20)

A

J

JA

D

(

)

(

)

+ 150 * 22.3 0.7 2 + 118°C 15 dB crest factor

(

)

(

)

+ 150 * 22.3 2.84 2 + 23°C 3dB crest factor

NOTE:

Internal dissipation of 1.4 W is estimated for a 10-W system with a 15 dB crest factor per channel.

The TPA032D02 is designed with thermal protection that turns the device off when the junction temperature

surpasses 150°C to prevent damage to the IC. Table 3 was calculated for maximum listening volume without

distortion. When the output level is reduced the numbers in the table change significantly. Also, using 8-Ω

speakers dramatically increases the thermal performance by increasing amplifier efficiency.

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢃꢅ

ꢇꢃ ꢈꢉ ꢊꢀ ꢋ ꢌ ꢋꢍ ꢎ ꢏꢂ ꢊꢊ ꢈꢆ ꢂꢐ ꢆꢑ ꢍ ꢁ ꢍꢉ ꢋꢌ ꢂꢒ ꢁꢏ ꢑꢓ ꢑꢋ ꢌ

SLOS243B − DECEMBER 1999 − REVISED JUNE 2000

THERMAL INFORMATION

The thermally enhanced DCA package is based on the 56-pin TSSOP, but includes a thermal pad (see Figure 12)

to provide an effective thermal contact between the IC and the PWB.

Traditionally, surface-mount and power have been mutually exclusive terms. A variety of scaled-down TO-220-type

packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages,

however, have only two shortcomings: they do not address the very low profile requirements (<2 mm) of many of

today’s advanced systems, and they do not offer a terminal-count high enough to accommodate increasing

integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that

severely limits the usable range of many high-performance analog circuits.

The PowerPAD package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal

performance comparable to much larger power packages.

The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the very small size and

limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that

remove heat from the component. The thermal pad is formed using a patented lead-frame design and manufacturing

technique to provide a direct connection to the heat-generating IC. When this pad is soldered or otherwise thermally

coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can

be reliably achieved.

Thermal

Pad

DIE

Side View (a)

DIE

End View (b)

Bottom View (c)

Figure 12. Views of Thermally Enhanced DCA Package

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jul-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TPA032D02DCA

TPA032D02DCAG4

TPA032D02DCAR

TPA032D02DCARG4

ACTIVE

HTSSOP

DCA

48

40

TBD

CU NIPDAU Level-3-220C-168 HR

Call TI Call TI

CU NIPDAU Level-3-220C-168 HR

Call TI Call TI

DCA

2000

DCA

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to

discontinue any product or service without notice. Customers should obtain the latest relevant information

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subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent

TI deems necessary to support this warranty. Except where mandated by government requirements, testing

of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Amplifiers

Data Converters

DSP

Interface

Applications

Audio

Automotive

Broadband

Digital Control

Military

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Logic

Power Mgmt

Microcontrollers

Low Power Wireless

power.ti.com

microcontroller.ti.com

www.ti.com/lpw

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TPA032D02DCAR
厂家：	TEXAS INSTRUMENTS
描述：	10-W STEREO CLASS-D AUDIO POWER AMPLIFIER 10 -W立体声D类音频功率放大器放大器功率放大器
文件：	总26页 (文件大小：561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPA032D02DCAR [TI]

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