TPA2011D1_15 [TI]
Mono Filter-Free Class-D Audio Power Amplifier;
| 型号： | TPA2011D1_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Mono Filter-Free Class-D Audio Power Amplifier |
| 文件： | 总24页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA2011D1
www.ti.com
SLOS626A –DECEMBER 2009–REVISED MAY 2010
3.2W Mono Filter-Free Class-D Audio Power Amplifier
With Auto-Recovering Short-Circuit Protection
Check for Samples: TPA2011D1
1
FEATURES
APPLICATIONS
•
•
•
Wireless or Cellular Handsets and PDAs
Portable Navigation Devices
General Portable Audio Devices
•
Powerful Mono Class-D Amplifier
–
–
–
–
3.24 W (4 Ω, 5 V, 10% THDN)
2.57 W (4 Ω, 5 V, 1% THDN)
1.80 W (8 Ω, 5 V, 10% THDN)
1.46 W (8 Ω, 5 V, 1% THDN)
DESCRIPTION
The TPA2011D1 is a 3.2-W high efficiency filter-free
class-D audio power amplifier (class-D amp) in a
1,21 mm
(WCSP) that requires only three external
components.
•
•
Integrated Feedback Resistor of 300 kΩ
Integrated Image Reject Filter for DAC Noise
Reduction
× 1,16 mm wafer chip scale package
•
•
•
•
•
Low Output Noise of 20 mV
Low Quiescent Current of 1.5 mA
Auto Recovering Short-Circuit Protection
Thermal Overload Protection
Features like 95% efficiency, 86-dB PSRR, 1.5 mA
quiescent current and improved RF immunity make
the TPA2011D1 class-D amp ideal for cellular
handsets. A fast start-up time of 4 ms with no audible
turn-on pop makes the TPA2011D1 ideal for PDA
and smart-phone applications. The TPA2011D1
allows independent gain while summing signals from
separate sources, and has a low 20 mV noise floor.
9-Ball, 1,21mm x 1,16 mm 0,4 mm Pitch WCSP
APPLICATION CIRCUIT
TPA2011D1
9-BALL 0.4mm PITCH
WAFER CHIP SCALE PACKAGE(YFF)
(TOP VIEW OF PCB)
IN+
A1
GND
A2
VO-
A3
VDD
B1
PVDD
B2
PGND
B3
EN
TPA2011D1
IN-
C1
EN
C2
VO+
C3
1.214 mm
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA2011D1
SLOS626A –DECEMBER 2009–REVISED MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGED DEVICES(1)
PART NUMBER(2)
TPA2011D1YFFR
TPA2011D1YFFT
SYMBOL
OEW
—40°C to 85°C
9-ball WSCP
OEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com
(2) The YFF package is only available taped and reeled. The suffix "R" indicates a reel of 3000, the suffix "T" indicates a reel of 250.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, TA = 25°C (unless otherwise noted)(1)
VALUE
–0.3 to 6
UNIT
V
In active mode
In shutdown mode
EN, IN+, IN–
VDD, PVDD
Supply voltage
Input voltage
–0.3 to 6
V
VI
–0.3 to VDD + 0.3
3.2
V
RL
Minimum load resistance
Ω
Output continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range
Storage temperature range
See Dissipation Rating Table
–40 to 85
TA
°C
°C
°C
°C
TJ
–40 to 150
Tstg
–65 to 85
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
DERATING FACTOR(1)
TA < 25°C
TA = 70°C
TA = 85°C
YFF (WCSP)
4.2 mW/°C
525 mW
336 mW
273 mW
(1) Derating factor measure with high K board.
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
MAX UNIT
VDD
VIH
VIL
RI
Class-D supply voltage
High-level input voltage
Low-level input voltage
Input resistor
5.5
V
V
EN
1.3
EN
0.35
V
Gain ≤ 20 V/V (26 dB)
15
kΩ
V
VIC
TA
Common mode input voltage range VDD = 2.5V, 5.5V, CMRR ≥ 49 dB
0.75 VDD-1.1
–40 85
Operating free-air temperature
°C
2
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TPA2011D1
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Output offset voltage (measured
differentially)
|VOS
|
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
1
5
mV
|IIH
|
High-level input current
Low-level input current
VDD = 5.5 V, VEN = 5.5 V
VDD = 5.5 V, VEN = 0 V
VDD = 5.5 V, no load
50
1
mA
mA
|IIL|
1.8
1.5
1.3
0.1
2
2.5
2.3
2.1
2
I(Q)
Quiescent current
VDD = 3.6 V, no load
mA
VDD = 2.5 V, no load
I(SD)
Shutdown current
VEN = 0.35 V, VDD = 2.5 V to 5.5 V
VEN = 0.35 V
mA
kΩ
RO, SD
f(SW)
AV
Output impedance in shutdown mode
Switching frequency
Gain
VDD = 2.5 V to 5.5 V
250
300
350
kHz
V/V
kΩ
VDD = 2.5 V to 5.5 V, RI in kΩ
285/RI 300/RI
300
315/RI
REN
Resistance from EN to GND
OPERATING CHARACTERISTICS
VDD = 3.6 V, TA = 25°C, AV = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
3.24
MAX
UNIT
VDD = 5 V
THD + N = 10%, f = 1 kHz, RL = 4 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
1.62
W
0.70
2.57
THD + N = 1%, f = 1 kHz, RL = 4 Ω
THD + N = 10%, f = 1 kHz, RL = 8 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
1.32
W
W
0.57
PO
Output power
1.80
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
0.91
0.42
1.46
VDD = 3.6 V
VDD = 2.5 V
A-weighting
No weighting
0.74
W
0.33
VDD = 3.6 V, Inputs AC grounded
with CI = 2mF, f = 20 Hz to 20 kHz
20
Vn
Noise output voltage
mVRMS
25
VDD = 5.0 V, PO = 1.0 W, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz, RL = 8 Ω
VDD = 2.5 V, PO = 0.2 W, f = 1 kHz, RL = 8 Ω
VDD = 5.0 V, PO = 2.0 W, f = 1 kHz, RL = 4 Ω
VDD = 3.6 V, PO = 1.0 W, f = 1 kHz, RL = 4 Ω
VDD = 2.5 V, PO = 0.4 W, f = 1 kHz, RL = 4 Ω
0.11%
0.05%
0.05%
0.23%
0.07%
0.06%
Total harmonic distortion plus
noise
THD+N
PSRR
VDD = 3.6 V, Inputs AC grounded with CI = 2 mF,
200 mVpp ripple, f = 217 Hz
AC power supply rejection ratio
86
dB
CMRR
TSU
Common mode rejection ratio
Startup time from shutdown
VDD = 3.6 V, VIC = 1 VPP, f = 217 Hz
VDD = 3.6 V
79
4
dB
ms
VDD = 3.6 V, VO+ shorted to VDD
VDD = 3.6 V, VO– shorted to VDD
VDD = 3.6 V, VO+ shorted to GND
VDD = 3.6 V, VO– shorted to GND
VDD = 3.6 V, VO+ shorted to VO–
2
2
Overcurrent protection
threshold
IOC
2
A
2
2
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
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OPERATING CHARACTERISTICS (continued)
VDD = 3.6 V, TA = 25°C, AV = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Time for which output is
disabled after a short-circuit
event, after which
TSD
VDD = 2.5 V to 5.5 V
100
ms
auto-recovery trials are
continuously made
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
WCSP BALL
IN–
IN+
VO-
VO+
C1
A1
A3
C3
I
Negative differential audio input
I
Positive differential audio input
Negative BTL audio output
Positive BTL audio output
O
O
Analog ground terminal. Must be connected to same potential as PGND using a direct connection
to a single point ground.
GND
PGND
VDD
A2
B3
B1
I
I
I
High-current Analog ground terminal. Must be connected to same potential as GND using a direct
connection to a single point ground.
Power supply terminal. Must be connected to same power supply as PVDD using a direct
connection. Voltage must be within values listed in Recommended Operating Conditions table.
High-current Power supply terminal. Must be connected to same power supply as VDD using a
direct connection. Voltage must be within values listed in Recommended Operating Conditions
table.
PVDD
EN
B2
C2
I
I
Shutdown terminal. When terminal is low the device is put into Shutdown mode.
FUNCTIONAL BLOCK DIAGRAM
Input
Buffer
EN
SC
300 KΩ
4
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
TEST SETUP FOR GRAPHS
CI
CI
RI
RI
+
-
IN+
IN-
OUT+
+
30 kHz
Low Pass
Filter
Measurement
Output
Measurement
Input
Load
TPA2011D1
-
OUT-
VDD
GND
CS1
CS2
+
-
VDD
1. Input resistor RI = 150kΩ gives a gain of 6 dB which is used for all the graphs
2. CI was shorted for any common-mode input voltage measurement. All other measurements were taken with CI = 0.1-mF
(unless otherwise noted).
3. CS1 = 0.1mF is placed very close to the device. The optional CS2 = 10mF is used for datasheet graphs.
4. The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low-pass filter (1kΩ,
4700pF) is used on each output for the data sheet graphs.
TYPICAL CHARACTERISTICS
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
EFFICIENCY vs
EFFICIENCY vs
OUTPUT POWER
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
RL = 8 Ω + 33 µH
Gain = 6 dB
RL = 4 Ω + 33 µH
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
PO − Output Power − W
PO − Output Power − W
Figure 1.
Figure 2.
POWER DISSIPATION vs
OUTPUT POWER
POWER DISSIPATION vs
OUTPUT POWER
0.4
0.3
0.2
0.1
0.0
0.6
0.5
0.4
0.3
0.2
0.1
0.0
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
VDD = 3.6 V
Gain = 6 dB
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
VDD = 5.0 V
Gain = 6 dB
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
PO − Output Power − W
PO − Output Power − W
Figure 3.
Figure 4.
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
SUPPLY CURRENT vs
OUTPUT POWER
SUPPLY CURRENT vs
OUTPUT POWER
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.5
0.4
0.3
0.2
0.1
0.0
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
RL = 4 Ω + 33 µH
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
RL = 8 Ω + 33 µH
Gain = 6 dB
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
PO − Output Power − W
PO − Output Power − W
Figure 5.
Figure 6.
SUPPLY CURRENT vs
SUPPLY VOLTAGE
SUPPLY CURRENT vs
EN VOLTAGE
2.00
1.75
1.50
1.25
1.00
200
150
100
50
RL = No Load
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Gain = 6 dB
Gain = 6 dB
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0
0.1
0.2
0.3
0.4
0.5
VDD − Supply Voltage − V
VEN − EN Voltage − V
Figure 7.
Figure 8.
OUTPUT POWER vs
LOAD RESISTANCE
OUTPUT POWER vs
LOAD RESISTANCE
5
4
3
2
1
0
4
3
2
1
0
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 10 %
Frequency = 1 kHz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 1 %
Frequency = 1 kHz
Gain = 6 dB
4
8
12
16
20
24
28
32
4
8
12
16
20
24
28
32
RL − Load Resistance − Ω
RL − Load Resistance − Ω
Figure 9.
Figure 10.
6
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
OUTPUT POWER vs
SUPPLY VOLTAGE
THD + NOISE vs
OUTPUT POWER
4
3
2
1
0
RL = 4 Ω, THD+N = 1 %
RL = 4 Ω, THD+N = 10 %
RL = 8 Ω, THD+N = 1 %
RL = 8 Ω, THD+N = 10 %
Frequency = 1 kHz
Gain = 6 dB
2.5
3.0
3.5
4.0
4.5
5.0
VDD − Supply Voltage − V
Figure 11.
Figure 12.
THD + NOISE vs
OUTPUT POWER
THD + NOISE vs
FREQUENCY
10
1
VDD = 5.0 V
RL = 8 Ω + 33 µH
Gain = 6 dB
PO = 50 mW
PO = 250 mW
PO = 1 W
0.1
0.01
0.001
20
100
1k
10k 20k
f − Frequency − Hz
Figure 13.
Figure 14.
THD + NOISE vs
FREQUENCY
THD + NOISE vs
FREQUENCY
10
10
1
VDD = 3.6 V
RL = 8 Ω + 33 µH
Gain = 6 dB
PO = 25 mW
PO = 125 mW
PO = 500 mW
VDD = 2.5 V
RL = 8 Ω + 33 µH
Gain = 6 dB
PO = 15 mW
PO = 75 mW
PO = 200 mW
1
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
THD + NOISE vs
FREQUENCY
THD + NOISE vs
FREQUENCY
10
1
10
1
VDD = 5.0 V
RL = 4 Ω + 33 µH
Gain = 6 dB
PO = 100 mW
PO = 500 mW
PO = 2 W
VDD = 3.6 V
RL = 4 Ω + 33 µH
Gain = 6 dB
PO = 50 mW
PO = 250 mW
PO = 1 W
0.1
0.1
0.01
0.001
0.01
0.001
20
20
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 17.
Figure 18.
THD + NOISE vs
FREQUENCY
THD + NOISE vs
COMMON MODE INPUT VOLTAGE
10
1
10
1
VDD = 2.5 V
PO = 30 mW
PO = 150 mW
PO = 400 mW
RL = 8 Ω + 33 µH
Frequency = 1 kHz
PO = 200 mW
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
RL = 4 Ω + 33 µH
Gain = 6 dB
Gain = 6 dB
0.1
0.1
0.01
0.001
0.01
100
1k
10k 20k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
f − Frequency − Hz
VIC − Common Mode Input Voltage − V
Figure 19.
Figure 20.
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
0
−10
0
−10
Inputs AC−Grounded
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
Inputs AC−Grounded
CI = 2 µF
RL = 4 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
CI = 2 µF
RL = 8 Ω + 33 µH
−20
−20
Gain = 6 dB
Gain = 6 dB
−30
−30
−40
−40
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−100
−110
−120
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 21.
Figure 22.
8
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
POWER SUPPLY REJECTION RATIO vs
COMMON MODE INPUT VOLTAGE
COMMON MODE REJECTION RATIO
vs FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−30
−40
−50
−60
−70
−80
−90
−100
RL = 8 Ω + 33 µH
Frequency = 217 Hz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
VIC = 1 VPP
RL = 8 Ω + 33 µH
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
100
1k
10k 20k
VIC − Common Mode Input Voltage − V
f − Frequency − Hz
Figure 23.
Figure 24.
COMMON MODE REJECTION RATIO vs
COMMON MODE INPUT VOLTAGE
0
RL = 8 Ω + 33 µH
Frequency = 217 Hz
Gain = 6 dB
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−10
−20
−30
−40
−50
−60
−70
−80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIC − Common Mode Input Voltage − V
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 mF, CS1 = 0.1 mF, CS2 = 10 mF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
GSM POWER SUPPLY REJECTION
vs TIME
Figure 26.
GSM POWER SUPPLY REJECTION
vs FREQUENCY
Figure 27.
10
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
APPLICATION INFORMATION
SHORT CIRCUIT AUTO-RECOVERY
When a short-circuit event occurs, the TPA2011D1 goes to shutdown mode and activates the integrated
auto-recovery process whose aim is to return the device to normal operation once the short-circuit is removed.
This process repeatedly examines (once every 100ms) whether the short-circuit condition persists, and returns
the device to normal operation immediately after the short-circuit condition is removed. This feature helps protect
the device from large currents and maintain a good long-term reliability.
INTEGRATED IMAGE REJECT FILTER FOR DAC NOISE REJECTION
In applications which use a DAC to drive Class-D amplifiers, out-of-band noise energy present at the DAC's
image frequencies fold back into the audio-band at the output of the Class-D amplifier. An external low-pass filter
is often placed between the DAC and the Class-D amplifier in order to attenuate this noise.
The TPA2011D1 has an integrated Image Reject Filter with a low-pass cutoff frequency of 130 kHz, which
significantly attenuates this noise. Depending on the system noise specification, the integrated Image Reject
Filter may help eliminate external filtering, thereby saving board space and component cost.
COMPONENT SELECTION
Figure 28 shows the TPA2011D1 typical schematic with differential inputs and Figure 29 shows the TPA2011D1
with differential inputs and input capacitors, and Figure 30 shows the TPA2011D1 with single-ended inputs.
Differential inputs should be used whenever possible because the single-ended inputs are much more
susceptible to noise.
Table 1. Typical Component Values
REF DES
VALUE
EIA SIZE
0402
MANUFACTURER
Panasonic
Murata
PART NUMBER
ERJ2RHD154V
RI
150 kΩ (±0.5%)
1 mF (+22%, –80%)
3.3 nF (±10%)
CS
0402
GRP155F50J105Z
GRP033B10J332K
(1)
CI
0201
Murata
(1) CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF
(with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz.
Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to Equation 1.
2 x 150 kW
V
V
ǒ Ǔ
Gain +
R
(1)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or
better to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with
1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2011D1 to limit noise injection on the high-impedance nodes.
For optimal performance the gain should be set to 2 V/V or lower. Lower gain allows the TPA2011D1 to operate
at its best, and keeps a high voltage at the input making the inputs less susceptible to noise.
Decoupling Capacitors (CS1, CS2)
The TPA2011D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor CS1 = 0.1mF ,
placed as close as possible to the device VDD lead works best. Placing CS1 close to the TPA2011D1 is important
for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device
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and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10 mF or greater
capacitor (CS2) placed near the audio power amplifier would also help, but it is not required in most applications
because of the high PSRR of this device. Typically, the smaller the capacitor's case size, the lower the
inductance and the closer it can be placed to the TPA2011D1. X5R and X7R dielectric capacitors are
recommended for both CS1 and CS2.
Input Capacitors (CI)
The TPA2011D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD –0.8 V (shown in Figure 28). If the input signal is not biased within the recommended
common-mode input range, if needing to use the input as a high pass filter (shown in Figure 29), or if using a
single-ended source (shown in Figure 30), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 2.
1
f +
c
ǒ
Ǔ
2p R C
I I
(2)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation 3 is reconfigured to solve for the input coupling capacitance.
1
C +
I
ǒ
cǓ
2p R f
I
(3)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 mF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
To Battery
Internal
V
DD
Oscillator
C
S
RI
RI
+
−
IN−
IN+
V
O+
PWM
H−
_
+
Differential
Input
Bridge
V
O−
GND
Bias
Circuitry
EN
TPA2011D1
Filter-Free Class D
Figure 28. Typical TPA2011D1 Application Schematic With Differential Input for a Wireless Phone
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
To Battery
Internal
V
DD
C
S
Oscillator
C
I
R
I
IN−
IN+
V
O
+
PWM
H−
_
+
Differential
Input
Bridge
V
O
−
C
I
R
I
GND
Bias
Circuitry
EN
TPA2011D1
Filter-Free Class D
Figure 29. TPA2011D1 Application Schematic With Differential Input and Input Capacitors
To Battery
Internal
V
DD
Oscillator
C
S
C
I
R
I
I
Single-ended
Input
IN−
IN+
V
O+
PWM
H−
_
+
Bridge
V
O−
R
C
I
GND
Bias
Circuitry
EN
TPA2011D1
Filter-Free Class D
Figure 30. TPA2011D1 Application Schematic With Single-Ended Input
SUMMING INPUT SIGNALS WITH THE TPA2011D1
Most wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources
that need separate gain. The TPA2011D1 makes it easy to sum signals or use separate signal sources with
different gains. Many phones now use the same speaker for the earpiece and ringer, where the wireless phone
would require a much lower gain for the phone earpiece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
Summing Two Differential Input Signals
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see Equation 4 and Equation 5, and Figure 31).
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
Gain 2 +
+
V
R
I1
(4)
(5)
V
V
O
I2
2 x 150 kW
V
ǒ Ǔ
+
R
V
I2
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
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If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain 1
= 0.1 V/V. The resistor values would be. . .
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
R
R
I1
+
-
Differential
Input 1
To Battery
I1
Internal
V
DD
Oscillator
C
S
R
I2
+
IN-
V
O+
PWM
H-
_
+
Differential
Input 2
Bridge
V
O-
R
I2
-
IN+
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 31. Application Schematic With TPA2011D1 Summing Two Differential Inputs
Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 32 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 8. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
Gain 2 +
+
V
R
I1
(6)
(7)
(8)
V
V
O
I2
2 x 150 kW
V
ǒ Ǔ
+
R
V
I2
1
C
+ ǒ2p R c2Ǔ
I2
f
I2
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at gain 1 = 0.1 V/V, and the ring-tone gain is set
to gain 2 = 2 V/V, the resistor values would be…
RI1 = 3 MΩ, and = RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by CI2. If the desired corner frequency is less
than 20 Hz...
1
C
u
I2
ǒ
Ǔ
2p 150kW 20Hz
(9)
C
u 53 nF
I2
(10)
14
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TPA2011D1
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
R
R
I1
Differential
Input 1
To Battery
I1
Internal
V
DD
Oscillator
C
S
C
I2
R
I2
Single-Ended
Input 2
IN-
V
O+
PWM
H-
Bridge
_
+
V
O-
R
I2
IN+
C
I2
GND
Bias
SHUTDOWN
Circuitry
Filter-Free Class D
Figure 32. Application Schematic With TPA2011D1 Summing Differential Input and Single-Ended Input
Signals
Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 11 through Equation 14,
and Figure 33). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an ac signal.
V
O
I1
2 x 150 kW
V
V
ǒ Ǔ
Gain 1 +
Gain 2 +
+
V
R
I1
(11)
(12)
(13)
V
V
O
I2
2 x 150 kW
V
ǒ Ǔ
+
R
V
I2
1
C
+ ǒ2p R c1Ǔ
I1
f
I1
1
C
+ ǒ2p R c2Ǔ
I2
f
I2
(14)
(15)
C
+ C ) C
P
I1
I2
R
+ ǒR
R
I1
I1
I2
I2
R
P
Ǔ
) R
(16)
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C
I1
R
I1
I2
Single-Ended
Input 1
To Battery
Internal
V
DD
Oscillator
C
S
C
I2
R
Single-Ended
Input 2
IN-
V
O+
PWM
H-
Bridge
_
+
V
O-
R
P
IN+
C
P
GND
Bias
Circuitry
SHUTDOWN
Filter-Free Class D
Figure 33. Application Schematic With TPA2011D1 Summing Two Single-Ended Inputs
WHEN TO USE AN OUTPUT FILTER
Design the TPA2011D1 without an Inductor / Capacitor (LC) output filter if the traces from the amplifier to the
speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used
without an output filter.
The TPA2011D1 does not require an LC output filter for short speaker connections (approximately 100 mm long
or less). A ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter;
and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into
account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower
than rated current values. See the TPA2011D1 EVM User's Guide for components used successfully by TI.
Figure 34 shows a typical ferrite-bead output filter.
Ferrite
Chip Bead
V
O−
1 nF
1 nF
Ferrite
Chip Bead
V +
O
Figure 34. Typical Ferrite Chip Bead Filter
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TPA2011D1
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
EFFICIENCY AND THERMAL INFORMATION
The maximum ambient operating temperature of the TPA2011D1 depends on the load resistance, power supply
voltage and heat-sinking ability of the PCB system. The derating factor for the YFF package is shown in the
dissipation rating table. Converting this to qJA:
1
q
+
JA
Derating Factor
(17)
Given qJA (from the Package Dissipation ratings table), the maximum allowable junction temperature (from the
Absolute Maximum ratings table), and the maximum internal dissipation (from Power Dissipation vs Output
Power figures) the maximum ambient temperature can be calculated with the following equation. Note that the
units on these figures are Watts RMS. Because of crest factor (ratio of peak power to RMS power) from 9–15
dB, thermal limitations are not usually encountered.
T Max + T Max * q
P
A
J
JA Dmax
(18)
The TPA2011D1 is designed with thermal protection that turns the device off when the junction temperature
surpasses 150°C to prevent damage to the IC. Note that the use of speakers less resistive than 4-Ω (typ) is not
advisable. Below 4-Ω (typ) the thermal performance of the device dramatically reduces because of increased
output current and reduced amplifier efficiency. The Absolute Maximum rating of 3.2-Ω covers the manufacturing
tolerance of a 4-Ω speaker and speaker impedance decrease due to frequency. qJA is a gross approximation of
the complex thermal transfer mechanisms between the device and its ambient environment. If the qJA calculation
reveals a potential problem, a more accurate estimate should be made.
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PRINTED CIRCUIT BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 35 shows the appropriate diameters for a WCSP layout.
Figure 35. Land Pattern Image and Dimensions
SOLDER PAD
DEFINITIONS
SOLDER MASK
OPENING(5)
COPPER
THICKNESS
STENCIL
THICKNESS
COPPER PAD
STENCIL OPENING(6)(7)
Nonsolder mask
defined (NSMD)
1 oz max
(0.032 mm)
0.275 mm x 0.275 mm Sq.
(rounded corners)
0.23 mm
0.310 mm
0.1 mm thick
1. Circuit traces from NSMD defined PWB lands should be 75 mm to 100 mm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Best reliability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
3. Recommend solder paste is Type 3 or Type 4.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 mm on top of the copper circuit pattern
6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils give inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
Figure 36. Layout Snapshot
An on-pad via is not required to route the middle ball B2 (PVDD) of the TPA2011D1. Just short ball B2 (PVDD) to
ball B1 (VDD) and connect both to the supply trace as shown in Figure 36. This simplifies board routing and
saves manufacturing cost.
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SLOS626A –DECEMBER 2009–REVISED MAY 2010
Package Dimensions
D
E
Max = 1190µm
Min = 1130µm
Max = 1244µm
Min = 1184µm
Spacer
REVISION HISTORY
Changes from Original (December 2009) to Revision A
Page
•
Changed the Package Dimensions table. D was Max = 1244µm, Min = 1184µm. E was Max = 1190µm, Min =
1130µm ............................................................................................................................................................................... 19
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PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPA2011D1YFFR
TPA2011D1YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
Green (RoHS
& no Sb/Br)
SNAGCU Level-1-260C-UNLIM
Request Free Samples
Green (RoHS
& no Sb/Br)
SNAGCU Level-1-260C-UNLIM
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA2011D1YFFR
TPA2011D1YFFT
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
180.0
180.0
8.4
8.4
1.34
1.34
1.34
1.34
0.81
0.81
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA2011D1YFFR
TPA2011D1YFFT
DSBGA
DSBGA
YFF
YFF
9
9
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
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相关型号：
TPA2011D1_17
3.2-W Mono Filter-Free Class-D Audio Power Amplifier With Auto-Recovering Short-Circuit Protection
TI
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