TPA3003D2PFB_技术文档

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

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FEATURES

DESCRIPTION

D

3-W/Ch Into an 8-Ω Load From 12-V Supply

Efficient, Class-D Operation Eliminates

Heatsinks and Reduces Power Supply

Requirements

32-Step DC Volume Control From −40 dB

to 36 dB

Third Generation Modulation Techniques

− Replaces Large LC Filter With Small

Low-Cost Ferrite Bead Filter

The TPA3003D2 is a 3-W (per channel) efficient,

Class-D audio amplifier for driving bridged-tied stereo

speakers. The TPA3003D2 can drive stereo speakers

as low as 8 Ω. The high efficiency of the TPA3003D2

eliminates the need for external heatsinks when playing

music.

D

Stereo speaker volume is controlled with a dc voltage

applied to the volume control terminal offering a range

of gain from –40 dB to 36 dB.

D

Thermal and Short-Circuit Protection

APPLICATIONS

D

LCD Monitors and TVs

Powered Speakers

D

PVCC

10 nF

PVCC

10 nF

10 µF

Cs

0.1 µF

Cbs

Cs

Ccpr

SYSTEM CONTROL

Crinn

SD

VCLAMPR

1 µF

NC

RINN

Crinp

1 µF

MUTE

AVCC

MUTE CONTROL

RINP

AVCC

C2p5

1 µF

V2P5

Cvcc

10 µF

Cs

0.1 µF

Clinp

1 µF

Clinn

LINP

NC

1 µF

LINN

TPA3003D2

1 µF

AVDDREF

VREF

AGND

VOLUME

REFGND

FADE

SYSTEM CONTROL

AVDD

Cosc

Cvdd

AVDD

100 nF

Rosc

COSC

ROSC

AGND

VCLAMPL

220 pF

120 kΩ

VOLUME

Ccpl

1 µF

Cs

Cbs

0.1 µF

Cs

10 nF

10 µF

PVCC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ

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1

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

†

48-PIN TQFP (PFB)

−40°C to 85°C

TPA3003D2PFB

†

The PFB package is available taped and reeled. To order a taped and

reeled part, add the suffix R to the part number (e.g., TPA3003D2PFBR).

PHP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

SD

RINN

RINP

V2P5

LINP

LINN

1

2

3

4

5

6

7

8

9

10

36 VCLAMPR

35 NC

34 MUTE

33

32 NC

NC

30 FADE

AV

CC

31

TPA3003D2

AV REF

DD

VREF

AGND

29

DD

28 COSC

27 ROSC

26 AGND

VOLUME 11

12

REFGND

VCLAMPL

25

13 14 15 16 17 18 19 20 21 22 23 24

2

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

functional block diagram

V2P5

PVCC

V2P5

VClamp

Gen

VCLAMPR

BSRN

PVCCR(2)

Gate

Drive

ROUTN(2)

RINN

Gain

PGNDR

BSRP

Deglitch &

Modulation

Logic

Adj.

RINP

PVCCR(2)

V2P5

Gate

Drive

ROUTP(2)

PGNDR

VREF

VOLUME

To Gain Adj.

Blocks

Gain

Control

FADE

REFGND

ROSC

Short Circuit

Detect

V2P5

Ramp

Thermal

VDDok

VCCok

Biases

Startup

Generator

VDD

&

Protection

Logic

COSC

References

AVCC

AVDDREF

AVDD

AVCC

5V LDO

PVCC

AGND

TTL Input

Buffer

SD

VClamp

Gen

VCLAMPL

MUTE

BSLN

PVCCL(2)

Cint2

Gate

LOUTN(2)

Drive

V2P5

LINN

LINP

PGNDL

BSLP

Deglitch &

Modulation

Logic

Gain

Adj.

Rfdbk2

PVCCL(2)

Rfdbk2

Gate

Drive

LOUTP(2)

PGNDL

Cint2

3

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NO.

AGND

NAME

9, 10, 26

33

−

Analog ground for digital/analog cells in core

AV

High-voltage analog power supply (8.5 V to 14 V)

CC

DD

AV

29

O

5-V Regulated output

AV REF

DD

7

O

5-V Reference output—provided for connection to adjacent VREF terminal.

Bootstrap I/O for left channel, negative high-side FET

Bootstrap I/O for left channel, positive high-side FET

Bootstrap I/O for right channel, negative high-side FET

Bootstrap I/O for right channel, positive high-side FET

I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5

BSLN

BSLP

BSRN

BSRP

COSC

FADE

13

I/O

I

24

48

37

28

30

Input for controlling volume ramp rate when cycling SD or during power-up. A logic low on this pin places

the amplifier in fade mode. A logic high on this pin allows a quick transition to the desired volume setting.

LINN

6

5

I

Negative differential audio input for left channel

Positive differential audio input for left channel

LINP

LOUTN

LOUTP

MUTE

NC

16, 17

20, 21

34

O

I

Class-D 1/2-H-bridge negative output for left channel

Class-D 1/2-H-bridge positive output for left channel

A logic high on this pin disables the outputs. A low on this pin enables the outputs.

Not internally connected

31, 32,

35

−

PGNDL

PGNDR

PVCCL

18, 19

42, 43

14, 15

−

Power ground for left channel H-bridge

Power ground for right channel H-bridge

Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or

AV

.

CC

PVCCL

PVCCR

REFGND

22, 23

38,39

46, 47

12

−

Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or

AV

.

CC

Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or

AV

.

CC

Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or

AV

.

CC

Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC

ground to this terminal.

RINP

3

2

I

Positive differential audio input for right channel

Negative differential audio input for right channel

RINN

ROSC

27

I/O

O

I

Current setting resistor for ramp generator. Nominally equal to 1/8*V

Class-D 1/2-H-bridge negative output for right channel

Class-D 1/2-H-bridge positive output for right channel

CC

ROUTN

ROUTP

SD

44, 45

40, 41

1

Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to V

Internally generated voltage supply for left channel bootstrap capacitors.

Internally generated voltage supply for right channel bootstrap capacitors.

DC voltage that sets the gain of the amplifier.

.

CC

VCLAMPL

VCLAMPR

VOLUME

VREF

25

−

I

36

11

8

I

Analog reference for gain control section.

V2P5

4

O

2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended

inputs.

4

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range: AV

PV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V

CC,

CC

Input voltage range, V : MUTE, VREF, VOLUME, FADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V

I

SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+ 0.3 V

CC

RINN, RINP, LINN, LINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

AV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Supply current,

DD

AVDDREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

A

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

PACKAGE

T

A

≤ 25°C

DERATING FACTOR

T

A

= 70°C

T = 85°C

A

PFB

2.8 W

22.2 mW/°C

1.8 W

1.4 W

recommended operating conditions

MIN

8.5

MAX

14

UNIT

Supply voltage, V

CC

PV , AV

CC

V

CC

Volume reference voltage

VREF

VOLUME

SD

3.0

5.5

Volume control pins, input voltage

2

3.5

4

MUTE

FADE

SD

High-level input voltage, V

IH

V

0.8

2

MUTE

FADE

Low-level input voltage, V

IL

2

MUTE, V = 5 V, V

I

= 14 V

1

CC

SD, V = 14 V, V

= 14 V

50

150

High-level input current, I

µA

I

CC

IH

FADE, V = 5 V, V

= 14 V

I

CC

Low-level input current, I

IL

Oscillator frequency, f

OSC

Operating free-air temperature, T

MUTE, SD, FADE, V = 0 V, V

I

= 14 V

1

275

85

µA

kHz

°C

CC

225

−40

A

5

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

dc characteristics, T = 25°C, V

= 12 V, R = 8 Ω (unless otherwise noted)

L

A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

10

MAX

65

UNIT

Output offset voltage (measured

differentially)

INN and INP connected together,

Gain = 36 dB

| V

OS

|

mV

0.45x

AV

DD

0.5x 0.55x

AV AV

V2P5 (terminal 4)

PSRR

2.5-V Bias voltage

No load

V

DD DD

Power supply rejection ratio

Supply quiescent current

V

CC

= 11.5 V to 12.5 V

−80

16

dB

mA

A

I

MUTE = 2 V, SD = 2 V

MUTE = 3.5 V, SD = 2 V

28.5

9

CC

MUTE mode quiescent current

Supply current at max power

Supply current in shutdown mode

7

CC(MUTE)

CC(max power)

CC(SD)

R

= 8 Ω, P = 3 W

0.6

1

L

O

SD = 0.8 V

10

700

µA

High side

Low side

Total

600

1200

V

I

= 12 V,

CC

= 1 A,

r

Drain-source on-state resistance

700

mΩ

O

ds(on)

T = 25°C

J

1400

ac characteristics, T = 25°C, V

= 12 V, R = 8 Ω (unless otherwise noted)

L

A

CC

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

V

= 11.5 V to 12.5 V from 10 Hz

CC

k

Supply ripple rejection ratio

−67

dB

SVR

to 1 kHz, Gain = 36 dB

THD+N = 1%, f = 1 kHz, R = 8 Ω

3

W

L

P

Maximum continuous output power

O(max)

n

THD+N = 10%, f = 1 kHz, R = 8 Ω

3.75

L

20 Hz to 22 kHz, No weighting filter,

Gain = 0.5 dB

V

Output integrated noise floor

Crosstalk, Left → Right

Signal-to-noise ratio

−82

−77

102

dBV

dB

Gain = 13.2 dB, P = 1 W, R = 8 Ω

O

L

Maximum output at THD+N < 0.5%,

f= 1 kHz, Gain = 0.5 dB

SNR

dB

Thermal trip point

Thermal hystersis

150

20

°C

6

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

Table 1. DC Volume Control

VOLTAGE ON THE

VOLUME PIN AS A

PERCENTAGE OF

VREF (DECREASING

VOLUME)

GAIN OF AMPLIFIER

VOLUME PIN AS A

PERCENTAGE OF

VREF (INCREASING

VOLUME OR FIXED

GAIN)

dB

%

†

−75

0 − 4.5

0 − 2.9

4.5 − 6.7

2.9 − 5.1

−40.0

−37.5

−35.0

−32.4

−29.9

−27.4

−24.8

−22.3

−19.8

−17.2

−14.7

−12.2

−9.6

6.7 − 8.91

8.9 − 11.1

11.1 − 13.3

13.3 − 15.5

15.5 − 17.7

17.7 − 19.9

19.9 − 22.1

22.1 − 24.3

24.3 − 26.5

26.5 − 28.7

28.7 − 30.9

30.9 − 33.1

33.1 − 35.3

35.3 − 37.5

37.5 − 39.7

39.7 − 41.9

41.9 − 44.1

44.1 − 46.4

46.4 − 48.6

48.6 − 50.8

50.8 − 53.0

53.0 − 55.2

55.2 − 57.4

57.4 − 59.6

59.6 − 61.8

61.8 − 64.0

64.0 − 66.2

66.2 − 68.4

68.4 − 70.6

> 70.6

5.1 − 7.2

7.2 − 9.4

9.4 − 11.6

11.6 − 13.8

13.8 − 16.0

16.0 − 18.2

18.2 − 20.4

20.4 − 22.6

22.6 − 24.8

24.8 − 27.0

27.0 − 29.1

29.1 − 31.3

31.3 − 33.5

33.5 − 35.7

35.7 − 37.9

37.9 − 40.1

40.1 − 42.3

42.3 − 44.5

44.5 − 46.7

46.7 − 48.9

48.9 − 51.0

51.0 − 53.2

53.2 − 55.4

55.4 − 57.6

57.6 − 59.8

59.8 − 62.0

62.0 − 64.2

64.2 − 66.4

66.4 − 68.6

>68.6

−7.1

−4.6

−2.0

†

0.5

3.1

5.6

8.1

10.7

13.2

15.7

18.3

20.8

23.3

25.9

28.4

30.9

33.5

†

36.0

†

Tested in production. Remaining steps are specified by design.

7

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Efficiency

vs Output power

1

2

P

O

Output power

vs Load resistance

vs Supply voltage

vs Output Power

vs Supply voltage

vs Gain

3

I

Quiescent supply current

Supply current

4

Q

5

CC

Quiescent shutdown supply current

Input impedance

6

Q(sd)

7

vs Frequency

8, 9

10, 11

12

13, 14

15

16

17

18

19

20

THD+N

Total harmonic distortion + noise

vs Output power

vs Frequency

k

Supply ripple rejection ratio

Closed loop response

Intermodulation performance

Input offset voltage

SVR

vs Common-mode input voltage

vs Frequency

Crosstalk

Mute attenuation

vs Frequency

Shutdown attenuation

Common-mode rejection ratio

8

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

TYPICAL CHARACTERISTICS

EFFICIENCY

vs

OUTPUT POWER

vs

OUTPUT POWER

LOAD RESISTANCE

80

70

60

50

40

30

20

10

0

8

7

6

5

4

3

2

1

0

V

= 12 V, R = 8 Ω

L

CC

V

= 12 V,

CC

V

CC

= 8.5 V, R = 8 Ω

V

= 12 V,

L

CC

THD = 1%

THD = 10%

Thermally Limited

LC Filter

Resistive Load

V

= 8.5 V,

V

= 8.5 V,

CC

THD = 1%

CC

THD = 10%

0

0.5

1

1.5

2

2.5

3

8

9

10

11

12

13

14

15

16

P

O

− Output Power − W

R

L

− Load Resistance − Ω

Figure 1

Figure 2

OUTPUT POWER

vs

SUPPLY VOLTAGE

QUIESCENT SUPPLY CURRENT

vs

SUPPLY VOLTAGE

6

18

17

T

A

= 25°C

5

4

16

15

14

13

12

Thermally Limited

8 Ω, THD = 10%

8 Ω, THD = 1%

3

2

1

11

10

8.5

9

10

11

12

13

14

8.5

9

10

11

12

13

14

V

DD

− Supply Voltage − V

V

CC

− Supply Voltage − V

Figure 3

Figure 4

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

QUIESCENT SHUTDOWN SUPPLY CURRENT

vs

OUTPUT POWER (TOTAL)

SUPPLY VOLTAGE

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

V

R

= 12 V,

CC

= 8 Ω

L

1

0.8

0.6

0.4

V

= 0.8 V

SD

0.2

0

V

SD

= 0 V

0

1

2

3

4

5

6

8.5

9

10

11

12

13

14

P

O

− Output Power (Total) − W

V

CC

− Supply Voltage − V

Figure 5

Figure 6

INPUT IMPEDANCE

TOTAL HARMONIC DISTORTION + NOISE

vs

GAIN

FREQUENCY

120

100

80

10

5

V

= 12 V,

CC

= 8 Ω,

R

T

L

= 25°C

A

2

1

0.5

P

O

= 1 W

60

40

P

O

= 0.5 W

0.2

P

O

= 3 W

0.1

0.05

20

0

0.02

0.01

−50

−30

−10

10

30

50

20

50 100 200 500 1 k 2 k

f − Frequency − Hz

5 k 10 k 20 k

Gain − dB

Figure 7

Figure 8

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TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

FREQUENCY

10

5

10

5

V

R

T

A

= 8.5 V,

CC

= 8 Ω,

V

R

T

A

= 12 V,

CC

= 8 Ω,

L

= 25°C

2

1

2

1

P

O

= 1 W

0.5

f = 1 kHz

f = 20 Hz

P

O

= 0.5 W

0.2

0.1

0.05

P

O

= 3.5 W

f = 20 KHz

0.02

0.01

0.02

0.01

20m 50m 100m 200m 500m

1

2

5

10

20

50 100 200 500 1 k 2 k

f − Frequency − Hz

5 k 10 k 20 k

P

O

− Output Power − W

Figure 10

Figure 9

TOTAL HARMONIC DISTORTION + NOISE

SUPPLY RIPPLE REJECTION RATIO

vs

OUTPUT POWER

FREQUENCY

10

5

−40

−45

−50

−55

−60

−65

−70

−75

V

R

T

A

= 12 V,

V

R

= 12 V,

CC

= 8 Ω,

CC

= 8 Ω

L

= 25°C

2

1

f = 1 kHz

0.5

f = 20 Hz

0.2

0.1

0.05

f = 20 kHz

−80

−85

−90

0.02

0.01

20m 50m 100m 200m 500m

1

2

5

10

20

100

1 k

10 k

100 k

P

O

− Output Power − W

f − Frequency − Hz

Figure 11

Figure 12

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TYPICAL CHARACTERISTICS

CLOSED LOOP RESPONSE

Gain

50

100

50

100

50

Gain

0

−50

0

Phase

0

−50

−100

−150

Phase

−50

−100

−150

−200

−250

−50

−100

−150

−200

−250

−100

−150

V

= 12 V,

V

= 12 V,

CC

Gain = +36 dB,

Gain = +5.6 dB,

−200

−250

−200

−250

R

= 8 Ω

R

= 8 Ω

L

10

100

1 k

10 k

100 k

1 M

10

100

1 k

10 k

100 k

1 M

f − Frequency − Hz

Figure 13

Figure 14

INPUT OFFSET VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

INTERMODULATION PERFORMANCE

6

5

4

3

0

V

CC

= 12 V

V

= 12 V, 19 kHz, 20 kHz,

CC

−20

1:1, P = 1 W, R = 8 Ω

Gain= +13.2 dB,

BW =20 Hz to 22 kHz,

Class-D

No Filter

O

L

−40

−60

−80

2

1

−100

−120

−140

0

−1

1

1.5

2

2.5

3

3.5

4

4.5

5

50 100

1 k

10 k

V

ICM

− Common-Mode Input Voltage − V

f − Frequency − Hz

Figure 15

Figure 16

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TYPICAL CHARACTERISTICS

CROSSTALK

vs

MUTE ATTENUATION

vs

FREQUENCY

−30

−40

−60

−65

−70

−75

V

R

= 12 V,

CC

= 8 Ω,

V

= 12 V,

CC

Gain = +13.2 dB,

L

V = 1 V

I

Class-D,

VOLUME = 0 V

rms

R

= 8 Ω,

= 1 W

L

−50

−60

P

O

−70

−80

−85

−90

−100

−110

−90

−95

−120

−130

10

100

1 k

10 k

10

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 17

Figure 18

COMMON-MODE REJECTION RATIO

SHUTDOWN ATTENUATION

vs

FREQUENCY

−60

−70

−80

−85

V

R

= 12 V,

V

CC

= 12 V

CC

= 8 Ω,

L

V = 1 V

I

rms

−90 Gain = +13.2 dB,

Class-D

−95

−100

−105

−110

−115

−120

−80

−90

−125

−130

−100

1 k

20

100

10 k 20 k

10

100

1 k

10 k

f − Frequency − Hz

Figure 19

Figure 20

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APPLICATION INFORMATION

C22

1 nF

C23

1 nF

L1

(Bead)

L2

(Bead)

10 µF

PGND

0.1uF

C10

10 nF

C19

10 nF

C18

C15

0.1uF

C9

C7

SD

VCLAMPR

GND

VCC

SHUTDOWN

C1

PGND

1 µF

RINN

RIN−

NC

C2

1 µF

MUTE

CONTROL

MUTE

RINP

C5

1 µF

C13

0.1 µF

C16

10 µF

AVCC

AGND

V2P5

C3

1 µF

LINP

NC

C4

1 µF

LINN

LIN−

TPA3003D2

1 µF

AVDDREF

VREF

FADE

AVDD

C14

AVDD

COSC

C6

100 nF

R1

AGND

VOLUME

REFGND

220pF

ROSC

AGND

120 kΩ

P1

50 kΩ

AGND

GND

C8

GND

VCLAMPL

1 µF

PGND

AGND

C11

C12

C20

C21

0.1 µF

C17

10 nF

10 µF

PGND

L3

(Bead)

L4

(Bead)

C24

1nF

C25

1nF

Figure 21. Stereo Configuration With Single-Ended Inputs

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APPLICATION INFORMATION

class-D operation

This section focuses on the class-D operation of the TPA3003D2.

traditional class-D modulation scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output

where each output is 180 degrees out of phase and changes from ground to the supply voltage, V . Therefore,

CC

the differential prefiltered output varies between positive and negative V , where filtered 50% duty cycle yields

CC

0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown

in Figure 22. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is

high, causing high loss, thus causing a high supply current.

OUTP

OUTN

+12 V

Differential Voltage

0 V

Across Load

−12 V

Current

Figure 22. Traditional Class-D Modulation Scheme’s Output Voltage and

Current Waveforms Into an Inductive Load With No Input

TPA3003D2 modulation scheme

The TPA3003D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.

However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater

than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%

and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout

2

most of the switching period, greatly reducing the switching current, which reduces any I R losses in the load.

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APPLICATION INFORMATION

TPA3003D2 modulation scheme (continued)

OUTP

OUTN

Output = 0 V

Differential

+12 V

Voltage

0 V

Across

−12 V

Load

Current

OUTP

OUTN

Output > 0 V

Differential

Voltage

Across

Load

+12 V

0 V

−12 V

Current

Figure 23. The TPA3003D2 Output Voltage and Current Waveforms Into an Inductive Load

efficiency: LC filter required with the traditional class-D modulation scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform

results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple

current is large for the traditional modulation scheme, because the ripple current is proportional to voltage

multiplied by the time at that voltage. The differential voltage swing is 2 × V , and the time at each voltage is

CC

half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from

each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both

resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3003D2 modulation scheme has very little loss in the load without a filter because the pulses are very

short and the change in voltage is V

instead of 2 × V . As the output power increases, the pulses widen,

CC

making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for

most applications the filter is not needed.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow

through the filter instead of the load. The filter has less resistance than the speaker, which results in less power

dissipation, therefore increasing efficiency.

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APPLICATION INFORMATION

effects of applying a square wave into a speaker

Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the

waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the

square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching

2

frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f for

frequencies beyond the audio band.

Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency

switching current. The amount of power dissipated in the speaker may be estimated by first considering the

overall efficiency of the system. If the on-resistance (r

) of the output transistors is considered to cause the

ds(on)

dominant loss in the system, then the maximum theoretical efficiency for the TPA3003D2 with an 8-Ω load is

as follows:

_{Efficiency (theoretical, %) + R ń}ǒ_RL_) r

Ǔ

100% + 8ń(8 ) 1.4) 100% + 85.11%

L

ds(on)

(1)

The maximum measured output power is approximately 3 W with an 12-V power supply. The total theoretical

power supplied (P ) for this worst-case condition would therefore be as follows:

(total)

P

+ P ńEfficiency + 3 W ń 0.8511 + 3.52 W

(total)

O

(2)

The efficiency measured in the lab using an 8-Ω speaker was 75%. The power not accounted for as dissipated

across the r may be calculated by simply subtracting the theoretical power from the measured power:

ds(on)

Other losses + P

(measured) * P

(theoretical) + 4 * 3.52 + 0.48 W

(total)

(3)

The quiescent supply current at 12 V is measured to be 28.5 mA. It can be assumed that the quiescent current

encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any

remaining power is dissipated in the speaker and is calculated as follows:

P

+ 0.48 W * (12 V 28.5 mA) + 0.14 W

(dis)

(4)

Note that these calculations are for the worst-case condition of 3 W delivered to the speaker. Since the 0.14 W

is only 5% of the power delivered to the speaker, it may be concluded that the amount of power actually

dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the

specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the

power generated from a clipping waveform.

when to use an output filter

Design the TPA3003D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered

speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without

a filter.

Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and

CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high

impedance at high frequencies, but very low impedance at low frequencies.

Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from

the amplifier to the speaker.

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when to use an output filter (continued)

33 µH

OUTP

C

2

L

1

C

1

0.1 µF

0.47 µF

33 µH

OUTN

C

3

L

2

0.1 µF

Figure 24. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8 Ω

Ferrite

Chip Bead

OUTP

1 nF

Ferrite

Chip Bead

OUTN

1 nF

Figure 25. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)

volume control operation

The VOLUME terminal controls the internal amplifier gain. This pin is controlled with a dc voltage, which should

not exceed VREF. Table 1 lists the gain as determined by the voltage on the VOLUME pin in reference to the

voltage on VREF.

If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to

AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 21 in the

Application Information Section). For fixed gain, calculate the resistor divider values necessary to center the

voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7

dB is desired, the resistors in the divider network can both be 10 kΩ. With these resistor values, a voltage of

50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB.

If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage

for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left

unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the

VREF input and any fluctuations in the DAC output voltage will not affect the TPA3003D2 gain. The percentages

in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME

terminal is increased. The percentages in the second column should be used for the DAC voltages when

decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the

gain based on an increase or decrease in the desired system volume. This is explained further in a section

below.

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volume control operation (continued)

If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND.

VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column

in Table 1 should be used to determine the point at which the gain changes depending on the direction that the

potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in

Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the

second column should be referenced.

The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME

terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that

the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation

of the volume control can be found in Figure 26. The graph focuses on three gain steps with the trip points

defined in the first and second columns of Table 1. The dotted lines represent the hysteresis about each gain

step.

The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the

rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates

every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is

reached. For example, if the TPA3003D2 is currently in the +0.53 dB gain step and the VOLUME pin is adjusted

for maximum gain at +36 dB, the time required for the gain to reach +36 dB is 14 steps x 67ms/step = 0.938

seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step

of +36 dB.

Decreasing Voltage on

VOLUME Terminal

5.6

3.1

Increasing Voltage on

VOLUME Terminal

0.5

2.00

2.21

(40.1%*VREF)

2.10 2.11

(44.1%*VREF)

(41.9%*VREF)

(42.3%*VREF)

Voltage on VOLUME Pin − V

Figure 26. DC Volume Control Operation, VREF = 5 V

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FADE operation

The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions

to and from the shutdown state and during power-up.

A logic low on this terminal places the amplifier in the fade mode. During power-up or recovery from the

shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute

state, −75 dB, to the desired volume setting determined by the voltage on the volume control terminal.

Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is

applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock.

This clock determines the rate at which the gain changes when adjusting the voltage on the external volume

control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step

until the final desired gain is reached. For example, if the TPA3003D2 is currently in the +0.53 dB class-D gain

step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36

dB is 14 steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB

gain step and the maximum gain step of +36 dB.

Figure 27 shows a scope capture of the differential output (measured across OUT+ and OUT−) with the amplifier

in the fade mode. A 1 V dc voltage was applied across the differential inputs and a logic low was applied to

pp

the SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step

to the next lower step at approximately 67 ms/step.

A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and

during power-up. During power-up or recovery from the shutdown state (a logic high is applied to the SD

terminal), the transition from the mute state, −75 dB, to the desired volume setting is less than 1 ms. Conversely,

the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD

terminal.

Figure 28 shows a scope capture of the differential output with the fade effect disabled. The outputs transition

to the lowest gain state within 1ms of applying a logic low to the SD terminal.

SD = 0V

GND

Figure 27. Differential Output With FADE (Terminal 30) Held Low

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APPLICATION INFORMATION

SD = 0 V

GND

Figure 28. Differential Output With FADE Terminal Held High

MUTE operation

The MUTE pin is an input for controlling the output state of the TPA3003D2. A logic high on this pin disables

the outputs. A logic low on this pin enables the outputs. This pin may be used as a quick disable or enable of

the outputs without a volume fade. Quiescent current is listed in the dc characteristics specification table. The

MUTE pin should never be left floating.

For power conservation, the SD pin should be used to reduce the quiescent current to the absolute minimum

level. The volume will fade, slowly increase or decrease, when leaving or entering the shutdown state if the

FADE terminal is held low. If the FADE terminal is held high, the outputs will transition very quickly. Refer to the

FADE operation section.

SD operation

The TPA3003D2 employs a shutdown mode of operation designed to reduce supply current (I ) to the absolute

CC

minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see

specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low causes the

outputs to mute and the amplifier to enter a low-current state. SD should never be left unconnected, because

amplifier operation would be unpredictable.

For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing

the power supply voltage.

selection of COSC and ROSC

The switching frequency is determined using the values of the components connected to ROSC (pin 20) and

COSC (pin 21) and may be calculated with the following equation:

f

= 6.6 / (R

* C

)

OSC

The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for R

and C

.

OSC

The recommended values are C

= 220 pF, R

=120 kΩ for a switching frequency of 250 kHz.

OSC

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APPLICATION INFORMATION

internal 2.5-V bias generator capacitor selection

The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stage. The external input

capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of

the input preamplifiers.

The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance.

During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the

amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75 x V2P5, or 75% of its final value, the

device turns on and the class-D outputs start switching. The startup time is not critical for the best depop

performance since any pop sound that is heard is the result of the class-D outputs switching on and not the

startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor.

A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.

input resistance

Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest

value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB

or cutoff frequency also changes by over six times.

Z

f

C

i

Z

i

IN

Input

Signal

The −3-dB frequency can be calculated using equation 5.

1

f

+

*3dB

2p Z C

(5)

i i

input capacitor, C

i

In the typical application an input capacitor (C ) is required to allow the amplifier to bias the input signal to the

i

proper dc level (V2P5) for optimum operation. In this case, C and the input impedance of the amplifier (Z ) form

i

a high-pass filter with the corner frequency determined in equation 6.

−3 dB

(6)

1

f

+

c

2pZ C

i

f

c

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The value of C is important, as it directly affects the bass (low frequency) performance of the circuit. Consider

i

the example where Z is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6

i

is reconfigured as equation 7.

1

C +

i

2pZ f

c

(7)

i

In this example, C is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is

i

known and will be constant, use Z to calculate C . Calculations for C should be based off the impedance at the

i

lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path

from the input source through the input network (C ) and the feedback network to the load. This leakage current

i

creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain

applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized

capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as

the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm

the capacitor polarity in the application.

power supply decoupling, C

S

The TPA3003D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling

to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also

prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is

achieved by using two capacitors of different types that target different types of noise on the power supply leads.

For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance

(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device V

lead works best. For

CC

filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near

the audio power amplifier is recommended. The 10-µF capacitor also serves as a local storage capacitor for

supplying current during large signal transients on the amplifier outputs.

BSN and BSP capacitors

The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the

high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected

from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from

xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit

diagram in Figure 21.)

VCLAMP capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two

internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25)

and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals

vary with V

and may not be used for powering any other circuitry.

CC

internal regulated 5-V supply (AV

)

DD

The AV

terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator,

DD

preamplifier, and volume control circuitry. It requires a 0.1-µF to 1-µF capacitor, placed very close to the pin,

to ground to keep the regulator stable. The regulator may not be used to power any external circuitry.

23

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APPLICATION INFORMATION

differential input

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.

To use the TPA3003D2 with a differential source, connect the positive lead of the audio source to the INP input

and the negative lead from the audio source to the INN input. To use the TPA3003D2 with a single-ended source,

ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the audio

source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the audio

source instead of at the device input for best noise performance.

using low-ESR capacitors

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)

capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this

resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this

resistance the more the real capacitor behaves like an ideal capacitor.

short-circuit protection

The TPA3003D2 has short circuit protection circuitry on the outputs that prevents damage to the device during

output-to-output shorts, output-to-GND shorts, and output-to-V

shorts. When a short-circuit is detected on

CC

the outputs, the output drive is immediately disabled. This is a latched fault and must be reset by cycling the

voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the

short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the

protection circuitry will again activate.

thermal protection

Thermal protection on the TPA3003D2 prevents damage to the device when the internal die temperature

exceeds 150°C. There is a 15 degree tolerance on this trip point from device to device. Once the die

temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are

disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by

20°C. The device begins normal operation at this point with no external system interaction.

thermal considerations: output power and maximum ambient temperature

To calculate the maximum ambient temperature, the following equation may be used:

T

= T – Θ P

JA Dissipated

Amax

J

where: T = 150°C

J

Θ

= 45°C/W

JA

(8)

(9)

(The derating factor for the 48-pin PFB package is given in the dissipation rating table.)

To estimate the power dissipation, the following equation may be used:

P

= P

x ((1 / Efficiency) – 1)

Dissipated

O(average)

Efficiency = ~75% for an 8-Ω load

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APPLICATION INFORMATION

thermal considerations: output power and maximum ambient temperature (continued)

Example. What is the maximum ambient temperature for an application that requires the TPA3003D2 to drive

3 W into an 8-Ω speaker (stereo)?

P

= 6 W x ((1 / 0.75) – 1) = 2 W

(P = 3 W * 2)

O

Dissipated

T

= 150°C – (45°C/W x 2 W) = 60°C

Amax

This calculation shows that the TPA3003D2 can drive 3 W of continuous RMS power per channel into an 8-Ω

speaker up to an ambient temperature of 60°C.

printed circuit board (PCB) layout

Because the TPA3003D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit

board (PCB) should be optimized according to the following guidelines for the best possible performance.

D

Decoupling capacitors — As described on page 23, the high-frequency 0.1-uF decoupling capacitors

should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AV (pin 33) terminals as

CC

possible. The V2P5 (pin 4) capacitor, AV

(pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should

DD

also be placed as close to the device as possible. Large (10 uF or greater) bulk power supply decoupling

capacitors should be placed near the TPA3003D2 on the PVCCL, PVCCR, and AV terminals.

CC

D

Grounding — The AV

(pin 33) decoupling capacitor, AV

(pin 29) capacitor, V2P5 (pin 4) capacitor,

CC

DD

COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND,

pin 26. The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground

(PGND, pins 18, 19, 42, 43). Basically, an AGND island should be created with a single connection to PGND.

Output filter — The ferrite EMI filter (Figure 25, page 18) should be placed as close to the output terminals

as possible for the best EMI performance. The LC filter (Figure 24, page 18 should be placed close to the

outputs. The capacitors used in both the ferrite and LC filters should be grounded to PGND.

For an example layout, please refer to the TPA3003D2 Evaluation Module (TPA3003D2EVM) User Manual, TI

literature number SLOU159. The EVM user manual is available on the TI web site at http://www.ti.com.

basic measurement system

This section focuses on methods that use the basic equipment listed below:

D

Audio analyzer or spectrum analyzer

Digital multimeter (DMM)

Oscilloscope

Twisted pair wires

Signal generator

Power resistor(s)

Linear regulated power supply

Filter components

EVM or other complete audio circuit

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APPLICATION INFORMATION

Figure 29 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine

wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics

are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must

be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise

and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II)

(Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling

capacitors, (C ), so no additional coupling is required. The generator output impedance should be low to avoid

IN

attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 kΩ).

Conversely the analyzer-input impedance should be high. The output impedance, R

in the hundreds of milliohms and can be ignored for all but the power-related calculations.

, of the APA is normally

OUT

Figure 29(a) shows a class-AB amplifier system, which is relatively simple because these amplifiers are linear

their output signal is a linear representation of the input signal. They take analog signal input and produce analog

signal output. These amplifier circuits can be directly connected to the AP-II or other analyzer input.

This is not true of the class-D amplifier system shown in Figure 29(b), which requires low pass filters in most

cases in order to measure the audio output waveforms. This is because it takes an analog input signal and

converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some

analyzers.

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APPLICATION INFORMATION

Power Supply

Analyzer

20 Hz − 20 kHz

Signal

Generator

APA

R_L

(a) Basic Class−AB

Power Supply

Class−D APA

Low−Pass RC

Filter

Analyzer

20 Hz − 20 kHz

Signal

Generator

R_L

Low−Pass RC

Filter

(b) Filter−Free and Traditional Class−D

Figure 29. Audio Measurement Systems

The TPA3003D2 uses a modulation scheme that does not require an output filter for operation, but they do

sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs

cannot accurately process the rapidly changing square-wave output and therefore record an extremely high

level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the

analyzer can measure the output sine wave.

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APPLICATION INFORMATION

differential input and BTL output

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.

Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.

Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly

used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180

degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling

the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in Figure 30. The differential input is a balanced input,

meaning the positive (+) and negative (−) pins will have the same impedance to ground. Similarly, the BTL output

equates to a balanced output.

Evaluation Module

Audio Power

Generator

Analyzer

Amplifier

Low−Pass

RC Filter

C_IN

R_GEN

R_IN

R_OUT

R_ANA

C_ANA

R_L

V_GEN

Low−Pass

RC Filter

R_GEN

R_ANA

C_ANA

Twisted−Pair Wire

Figure 30. Differential Input—BTL Output Measurement Circuit

The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced

output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer

must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode

noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL

outputs:

D

Use a balanced source to supply the input signal.

Use an analyzer with balanced inputs.

Use twisted-pair wire for all connections.

Use shielding when the system environment is noisy.

Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large

currents (see Table 2).

Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real

concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations

are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.

28

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

APPLICATION INFORMATION

Table 2. Recommended Minimum Wire Size for Power Cables

P

(W)

R

(Ω)

AWG SIZE DC POWER LOSS

(mW)

AC POWER LOSS

(mW)

OUT

L

1

8

22 to 28

2.0

1.5

8.0

6.1

2.1

1.6

8.1

6.2

< 0.75

8

Class-D RC low-pass filter

A RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width

modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff

frequency is set above the audio band. The high frequency of the square wave has negligible impact on

measurement accuracy because it is well above the audible frequency range and the speaker cone cannot

respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the

class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).

The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 31.

R is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should

L

be available and substituted for R

and C

. The filter components, R

and C

, can then be derived

ANA

FILT

for the system. The filter should be grounded to the APA near the output ground pins or at the power supply

ground pin to minimize ground loops.

Load

RC Low−Pass Filters

R_FILT

AP Analyzer Input

C_ANA

R_ANA

C_FILT

V_L= V

IN

R_L

V_OUT

R_FILT

C_ANA

R_ANA

C_FILT

To APA

GND

Figure 31. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

APPLICATION INFORMATION

The transfer function for this circuit is shown in equation (10) where ω = R

C

, R = R

R

and C

O

EQ EQ EQ

FILT

ANA EQ

= (C

+ C

). The filter frequency should be set above f

, the highest frequency of the measurement

FILT

ANA

MAX

bandwidth, to avoid attenuating the audio signal. Equation (11) provides this cutoff frequency, f . The value of

C

R

must be chosen large enough to minimize current that is shunted from the load, yet small enough to

FILT

minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R

and R

.

FILT

ANA

A rule of thumb is that R

error to less than 1% for R

should be small (~100 Ω) for most measurements. This reduces the measurement

ANA

FILT

≥ 10 kΩ.

R

ANA

ǒ Ǔ

R

)R

V

ANA

FILT

OUT

ǒ Ǔ

+

V

IN

w

_{1 ) j}ǒ Ǔ

w

O

(10)

Ǹ

f

+ 2 f

C

MAX

(11)

An exception occurs with the efficiency measurements, where R

must be increased by a factor of ten to

FILT

reduce the current shunted through the filter. C

must be decreased by a factor of ten to maintain the same

FILT

cutoff frequency. See Table 3 for the recommended filter component values.

Once f is determined and R is selected, the filter capacitance is calculated using equation (12). When the

C

FILT

calculated value is not available, it is better to choose a smaller capacitance value to keep f above the minimum

C

desired value calculated in equation (11).

1

C

+

FILT

2p f R

C

FILT

(12)

based on common component values. The value of f

C

Table 3 shows recommended values of R

was originally calculated to be 28 kHz for an f

and C

FILT

of 20 kHz. C

, however, was calculated to be 57000 pF,

MAX

FILT

but the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead,

and f is 34 kHz, which is above the desired value of 28 kHz.

C

Table 3. Typical RC Measurement Filter Values

MEASUREMENT

Efficiency

All other measurements

R

C

FILT

1 000 Ω

100 Ω

5 600 pF

56 000 pF

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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003

MECHANICAL DATA

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,50

M

0,08

0,17

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°−ā7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

31

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MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	TPA3003D2PFB
厂家：	TEXAS INSTRUMENTS
描述：	3-W STEREO CLASS-D AUDIO POWER AMPLIFIER WITH DC VOLUME CONTROL 3 -W立体声D类音频功率放大器采用直流音量控制放大器放大器功率放大器
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