TPA3007D1_17 [TI]
6.5-W MONO CLASS-D AUDIO POWER AMPLIFIER;
| 型号： | TPA3007D1_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 6.5-W MONO CLASS-D AUDIO POWER AMPLIFIER 放大器 功率放大器 |
| 文件： | 总20页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3007D1
www.ti.com
SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
6.5-W MONO CLASS-D AUDIO POWER AMPLIFIER
FEATURES
DESCRIPTION
•
•
•
6.5 W Into 8-Ω Load From 12-V Supply
(10% THD+N)
The TPA3007D1 is a 6.5-W mono bridge-tied load
(BTL) class-D audio power amplifier with high ef-
ficiency, eliminating the need for heat sinks. The
TPA3007D1 can drive 8-Ω speakers with only a
ferrite bead filter required to reduce EMI.
Short Circuit Protection (Short to VCC, Short
to GND, Short Between Outputs)
Third-Generation Modulation Technique:
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the ampli-
fier to be configured for a gain of 12, 18, 23.6, and 36
dB. The differential input stage provides high com-
mon mode rejection and improved power supply
rejection.
– Replaces Large LC Filter With Small,
Low-Cost Ferrite Bead Filter in Most
Applications
– Improved Efficiency
– Improved SNR
•
•
Low Supply Current . . . 8 mA Typ at 12 V
Shutdown Control . . . <1 µA Typ
The amplifier also includes depop circuitry to reduce
the amount of pop at power-up and when cycling
SHUTDOWN.
APPLICATIONS
The TPA3007D1 is available in the 24-pin TSSOP
package (PW) and does not require an external heat
sink.
•
•
•
•
LCD Monitors/TVs
Desktop Replacement Notebook PCs
Hands-Free Car Kits
Powered Speakers
Functional Schematic Diagram
U1
TPA3007D1
V
CC
1
2
0.47 µF
C1
24
23
C4
V
INN
CC
IN−
IN+
1 µF
C3
VREF
INP
1 µF
0.47 µF
C2
C11
3
4
5
22
21
BYPASS
COSC
GAIN0
GAIN1
GAIN SELECT
GAIN SELECT
1 µF
C12
220 pF
R1
ROSC
20
19
SHUTDOWN
CONTROL
SHUTDOWN
120 kΩ
6
7
AGND
AGND
BSP
PGND
VCLAMP
BSN
18
R3
51 Ω
R2
C10
1 µF
8
17
16
15
C9
0.22 µF
C8
0.22 µF
51 Ω
9
10
11
12
PV
CC
V
V
CC
PV
CC
CC
OUTP
OUTP
PGND
C6
1 µF
C5
1 µF
OUTN
OUTN
PGND
C7
10 µF
14
13
D1
D2
L1
L2
(Ferrite
Bead)
(Ferrite
Bead)
C15
1 nF
C14
1 nF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
AVAILABLE OPTIONS
PACKAGED DEVICES
TSSOP (PW)(1)
TA
-40°C to 85°C
TPA3007D1PW
(1) The PW package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g.,
TPA3007D1PWR).
PW PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
INN
INP
GAIN0
V
CC
2
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
3
4
GAIN1
5
SHUTDOWN
PGND
6
7
VCLAMP
BSN
8
9
PV
PV
CC
CC
10
11
12
OUTN
OUTN
PGND
OUTP
OUTP
PGND
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
18, 19
Analog ground terminal
Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22-µF
capacitor with a 51-Ω resistor in series from OUTN to BSN)
BSN
BSP
8
I
I
Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22-µF
capacitor with a 51-Ω resistor in series from OUTP to BSP)
17
BYPASS
COSC
GAIN0
GAIN1
INN
22
21
3
I
I
I
I
I
I
Connect 1-µF capacitor to ground for BYPASS voltage filtering
Connect a 220-pF capacitor to ground to set oscillation frequency
Bit 0 of gain control (see Table 2 for gain settings)
Bit 1 of gain control (see Table 2 for gain settings)
Negative differential input
4
1
INP
2
Positive differential input
Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit
protection
OUTN
10, 11
O
O
OUTP
14, 15
Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection
Power ground
PGND
PVCC
6, 12, 13
9, 16
20
5
I
I
High-voltage power supply (for output stages)
ROSC
SHUTDOWN
VCC
Connect 120 kΩ resistor to ground to set oscillation frequency
Shutdown terminal (active low), TTL compatible, 21-V compliant
Analog high-voltage power supply
I
24
7
I
VCLAMP
VREF
O
O
Connect 1-µF capacitor to ground to provide reference voltage for H-bridge gates
5-V internal regulator for control circuitry (connect a 0.1-µF to 1-µF capacitor to ground)
23
2
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
Functional Block Diagram
VREF
VREF
AGND
V
VCLAMP
CC
V
CC
Clamp
Reference
BSN
PV
CC
+
_
Deglitch
Logic
Gate
Drive
OUTN
Gain
Adjust
_
+
INN
INP
PGND
BSP
_
+
_
+
PV
CC
+
_
_
+
Gain
Adjust
Deglitch
Logic
Gate
Drive
OUTP
PGND
SD
Short-Circuit
Detect
SHUTDOWN
GAIN1
Start-Up
Protection
Logic
Biases
and
References
Ramp
Generator
2
GAIN0
Gain
COSC
ROSC
Thermal
V
CC
OK
BYPASS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
Supply voltage: VCC, PVCC
Load impedance, RL
-0.3 V to 21 V
≥7 Ω
Input voltage
SHUTDOWN
GAIN0, GAIN1
INN, INP
-0.3 V to VCC + 0.3 V
-0.3 V to 5.5 V
-0.3 V to 7 V
Continuous total power dissipation
See Dissipation Rating Table
-40°C to 85°C
-40°C to 150°C
-65°C to 85°C
260°C
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PW
1.43 W
11.45 mW/°C(1)
0.915 W
0.744 W
(1) Based on High-K board
3
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
RECOMMENDED OPERATING CONDITIONS
MIN
8
MAX
UNIT
V
Supply voltage, VCC, PVCC
Load impedance, RL
RL≥ 7.0Ω(1)
18
7.0
2
Ω
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA
Operating junction temperature, TJ
GAIN0, GAIN1, SHUTDOWN
GAIN0, GAIN1, SHUTDOWN
V
0.8
85
V
40
°C
°C
(2)
125
(1) The TPA3007D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 7.0Ω over the
audio frequency band.
(2) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. The
junction temperature is controlled by the thermal design of the application and should be carefully considered in high power dissipation
applications. See the thermal considerations section on page 14 for recommendations on improving the thermal performance of your
application.
ELECTRICAL CHARACTERISTICS
TA= 25°C, PVCC = VCC = 12 V (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
VI = 0 V, AV = 12 dB, 18, 23.6 dB
VI = 0 V, AV = 36 dB
MIN TYP MAX UNIT
50
mV
100
Output offset voltage (measured differen-
tially)
|VOS
|
PSRR
|IIH
Power supply rejection ratio
High-level input current
Low-level input current
PVCC = 11.5 V to 12.5 V
73
dB
µA
µA
|
PVCC = 12 V, VI = PVCC
1
1
|IIL|
PVCC = 12 V, VI = 0 V
SHUTDOWN = 2.0 V, No load
8
15 mA
ICC
Supply current
SHUTDOWN = VCC, VCC = 18 V,PO = 6.5 W, RL
8Ω
=
0.42
A
ICC(SD)
fs
Supply current, shutdown mode
Switching frequency
SHUTDOWN = 0.8 V
1
2
µA
kHz
Ω
ROSC = 120 kΩ, COSC = 220 pF
IO = 1 A, TJ = 25°C
250
rds(on)
Output transistor on resistance (total)
1.4
GAIN1 = 0.8 V, GAIN0 = 0.8 V
GAIN1 = 0.8 V, GAIN0 = 2 V
GAIN1 = 2 V, GAIN0 = 0.8 V
GAIN1 = 2 V, GAIN0 = 2 V
10.9
17.1
12 12.8 dB
18 18.5 dB
G
Gain
23 23.6 24.3 dB
33.9 36 36.5 dB
4
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
OPERATING CHARACTERISTICS
PVCC = VCC = 12 V, Gain = 12 dB, TA= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Continuous output power at 10%
THD+N
f = 1 kHz, RL = 8Ω
f = 1 kHz, RL = 8Ω
6.5
PO
W
Continuous output power at 1%
THD+N
5.0
THD + N Total harmonic distortion plus noise
PO = 3.25 W, RL = 8 Ω , f = 1 kHz
THD = 1%
0.19%
20
BOM
kSVR
SNR
Maximum output power bandwidth
Supply ripple rejection ratio
Signal-to-noise ratio
kHz
dB
f = 1 kHz, C(BYPASS) = 1 µF
PO = 3.25 W, RL = 8 Ω
70
97
dB
86
µV(rms)
dBV
C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, No weighting
filter used
81
Vn
Zi
Noise output voltage
Input impedance
66
µV(rms)
dBV
C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, A-weighted
filter
84
See Table 2, page 14
>23
kΩ
OPERATING CHARACTERISTICS
PVCC = VCC = 18 V, Gain = 12 dB, TA= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.16%
20
MAX UNIT
THD + N Total harmonic distortion plus noise
PO = 3.25 W, RL = 8 Ω, f = 1 kHz
THD = 1%
BOM
kSVR
SNR
Maximum output power bandwidth
Supply ripple rejection ratio
Signal-to-noise ratio
kHz
dB
f = 1 kHz, CBYPASS = 1 µF
PO = 3.25 W, RL = 8Ω
70
97
dB
86
µV(rms)
dBV
C(BYPASS) = 1 µF, f = 20 Hz to 20 kHz, No weighting
filter used
81
Vn
Zi
Noise output voltage
Input impedance
66
µV(rms)
dBV
C(BYPASS) = 1 µF, f = 20 Hz to 22 kHz, A-weighted
filter
84
See Table 2, page 14
>23
kΩ
5
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE
Efficiency
vs Output power
vs Supply Voltage
1
2
PO
Output power
Supply current
Shutdown current
ICC
3
vs Supply voltage
ICC(SD)
4
vs Output power
vs Frequency
5, 6
7, 8
9
THD+N
kSVR
Total harmonic distortion + noise
Supply voltage rejection ratio
Gain and phase
vs Frequency
10
11
12
CMRR
VIO
Common-mode rejection ratio
Input offset voltage
vs Common-mode input voltage
EFFICIENCY
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
SUPPLY VOLTAGE
90
80
70
60
50
40
30
20
10
0
10
9
8 Ω
8
10% THD+N
7
Thermally Limited
6
5
1% THD+N
4
V
CC
= 12 V
3
2
1
0
0
4
8
12
16
20
8
9
10 11 12 13 14 15 16 17 18
V
CC
− Supply Voltage − V
P
O
− Output Power − W
Figure 1.
Figure 2.
6
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs
SUPPLY VOLTAGE
11
10
9
5
4
3
2
1
0
SHUTDOWN = 0.8 V
8
7
6
8
10
12
14
16
18
8
10
12
14
16
18
V
CC
- Supply Voltage - V
V
CC
- Supply Voltage - V
Figure 3.
Figure 4.
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
R
= 12 V
= 8 Ω
CC
V
R
= 12 V
= 8 Ω
CC
L
L
Gain = +36 dB
Gain = +12 dB
f = 1 kHz
f = 20 Hz
f = 20 Hz
1
f = 20 kHz
1
f = 1 kHz
0.1
0.01
f = 20 kHz
0.1
0.1
1
10
0.1
1
10
P
O
− Output Power − W
P
O
− Output Power − W
Figure 5.
Figure 6.
7
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
vs
FREQUENCY
FREQUENCY
1
1
P
O
= 0.5 W
V
CC
= 12 V
P
O
= 0.5 W
R
L
= 8 Ω
P
O
= 4 W
P
O
= 5 W
0.1
0.1
P
O
= 2 W
P
O
= 2 W
V
CC
= 18 V
R
L
= 8 Ω
0.01
0.01
20
100
1 k
10 k 20 k
20
100
1 k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 7.
Figure 8.
SUPPLY VOLTAGE REJECTION RATIO
GAIN and PHASE
vs
FREQUENCY
vs
FREQUENCY
14
12
10
8
-50
30
20
C
R
= 1 µF
(Bypass)
Gain
= 8 Ω
L
10
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
V
CC
= 8 V
Phase
6
V
= 15 V
DD
4
2
0
V
R
= 8 V
= 8 Ω
CC
L
-70
-80
Gain = 12 dB
20
100
1k
10k
100k
20
100
1k
10k
f - Frequency - Hz
f - Frequency - Hz
Figure 9.
Figure 10.
8
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
COMMON-MODE REJECTION RATIO
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
vs
FREQUENCY
-40
6
5
V
R
= 8 V to 18 V
= 8 Ω
CC
V
CC
= 8 V to 18 V
L
-41
-42
-43
4
3
2
1
0
-44
-45
-46
-1
-2
-3
-4
20
100
1 k
10 k
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
f - Frequency - Hz
V
IC
- Common-Mode Input Voltage - V
Figure 11.
Figure 12.
9
TPA3007D1
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION
APPLICATION CIRCUIT
U1
TPA3007D1
V
CC
1
2
3
4
24
23
22
21
20
19
18
0.47 µF
C1
C4
INN
INP
IN−
V
CC
1 µF
C3
1 µF
VREF
IN+
C2 0.47 µF
C11
1 µF
GAIN SELECT
GAIN0
BYPASS
COSC
C12
220 pF
GAIN1
GAIN SELECT
R1
5
6
SHUTDOWN
CONTROL
SHUTDOWN
PGND
ROSC
AGND
AGND
BSP
120 kΩ
7
8
VCLAMP
BSN
R2
R3
C10
17
16
15
14
13
1 µF
C8
0.22 µF
C9
0.22 µF
51 Ω
51 Ω
9
V
CC
PV
CC
PV
CC
V
CC
10
11
12
C6
1 µF
OUTN
OUTN
PGND
OUTP
OUTP
C7
10 µF
C5
1 µF
PGND
D1
D2
L2
L1
(Ferrite (Ferrite
Bead)
Bead)
C15
1 nF
C14
1 nF
L1, L2: Fair-Rite, Part Number 2512067007Y3
D1, D2: Diodes, Inc., Part Number B130
Figure 13. Typical Application Circuit
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3007D1.
TRADITIONAL CLASS-D MODULATION SCHEME
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 14. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
10
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION (continued)
OUTP
OUTN
+12 V
Differential Voltage
0 V
Across Load
–12 V
Current
Figure 14. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3007D1 MODULATION SCHEME
The TPA3007D1 uses a modulation scheme that still has each output switching from ground to VCC. However,
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is
greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See
Figure 15).
11
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION (continued)
OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
–12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
Voltage
Across
Load
+12 V
0 V
–12 V
Current
Figure 15. The TPA3007D1 Output Voltage and Current Waveforms Into an Inductive Load
DRIVING THE OUTPUT INTO CLIPPING
The output of the TPA3007D1 may be driven into clipping to attain a higher output power than is possible with no
distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power into
the load may be calculated with Equation 1.
P
P
1.25
O(10% THD)
O(1% THD)
(1)
OUTPUT FILTER CONSIDERATIONS
A ferrite bead filter (shown in Figure 16) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long
wires (greater than 11 inches) from the amplifier to the speaker, as shown in Figure 17.
12
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
APPLICATION INFORMATION (continued)
Ferrite
Chip Bead
OUTP
1 nF
1 nF
7 Ω or Greater
Ferrite
Chip Bead
OUTN
Figure 16. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
Ferrite
Chip Bead
33 µH
OUTP
OUTN
0.47 µF
0.47 µF
1 nF
33 µH
8 Ω
Ferrite
Chip Bead
1 nF
Figure 17. Typical LC Output Filter for 8-Ω Speaker, Cutoff Frequency of 41 kHz
SHORT-CIRCUIT PROTECTION
The TPA3007D1 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on the
outputs, the part immediately disables the output drive and enters into shutdown mode. This is a latched fault
and must be reset by cycling the voltage on the SHUTDOWN pin to a logic low and back to the logic high state
for normal operation. This clears the short-circuit flag and allow for normal operation if the short was removed. If
the short was not removed, the protection circuitry again activates.
Two Schottky diodes are required to provide short-circuit protection. The diodes should be placed as close to the
TPA3007D1 as possible, with the anodes connected to PGND and the cathodes connected to OUTP and OUTN
as shown in the application circuit schematic. The diodes should have a forward voltage rating of 0.5V at a
minimum of 1A output current and a dc blocking voltage rating of at least 30 V. The diodes must also be rated to
operate at a junction temperature of 150°C.
If short-circuit protection is not required, the Schottky diodes may be omitted.
THERMAL PROTECTION
Thermal protection on the TPA3007D1 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
13
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SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
THERMAL CONSIDERATION: OUTPUT POWER AND RECOMMENDED
AMBIENT TEMPERATURE
To calculate the maximum ambient temperature, the following equation may be used:
T
+ T * θ
P
A(max)
J
JA Dissipated
where : T + 125°C
J
1
1
θ
+
+
+ 87.3°CńW
JA
0.01145
derating factor
(2)
(3)
(The derating factor for the 24-pin PW package is given in the dissipation rating table.)
To estimate the power dissipation, the following equation may be used:
1
ǒ Ǔ
ǒ Ǔ
P
+ P
–1
Dissipated
O(average)
Efficiency
Efficiency +X 85% for an 8-W load
Example. What is the maximum ambient temperature for an application that requires the TPA3007D1 to drive 3
W into an 8-Ω speaker?
PDissipated = 3 W x ((1 / 0.85) - 1) = 0.529 W
TAmax = 125°C - (87.3°C/W x 0.529 W) = 78.8°C
This calculation shows that the TPA3007D1 can drive 3 W into an 8-Ω speaker up to the absolute maximum
ambient temperature rating of 78.8°C, which must never be exceeded.
GAIN SETTING VIA GAIN0 AND GAIN1 INPUTS
The gain of the TPA3007D1 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance may shift by
30% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 23 kΩ, which is the absolute minimum input impedance of the TPA3007D1. At the lower gain
settings, the input impedance could increase as high as 313 kΩ.
Table 2. Gain Settings
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE
(kΩ)
GAIN1
GAIN0
TYP
12
TYP
241
168
104
33
0
0
1
1
0
1
0
1
18
23.6
36
INPUT RESISTANCE
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB
or cutoff frequency also changes by over six times.
14
TPA3007D1
www.ti.com
SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
Z
f
C
i
Z
i
IN
Input
Signal
The -3-dB frequency can be calculated using Equation 4. Use Table 2 for Zi values.
1
f +
2p Z C
i
i
(4)
INPUT CAPACITOR, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in Equation 5.
-3 dB
1
f
+
c
2pZ C
i
i
f
c
(5)
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Zi is 241 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 5 is
reconfigured as Equation 6.
1
C +
i
2pZ f
c
i
(6)
In this example, Ci is 33 nF, so one would likely choose a value of 0.1 µF, as this value is commonly used. If the
gain is known and will be constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor
is the leakage path from the input source through the input network (Ci) and the feedback network to the load.
This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom,
especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the application.
POWER SUPPLY DECOUPLING
The TPA3007D1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 1 µF placed as close as possible to the device VCC lead works best. For filtering
lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audio
power amplifier is recommended.
15
TPA3007D1
www.ti.com
SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
BSN AND BSP CAPACITORS
The full H-bridge output stage uses only NMOS transistors. It therefore requires bootstrap capacitors for the high
side of each output to turn on correctly. A 0.22-µF ceramic capacitor, rated for at least 25 V, must be connected
from each output to its corresponding bootstrap input. Specifically, one 0.22-µF capacitor must be connected
from OUTP to BSP, and one 0.22-µF capacitor must be connected from OUTN to BSN. (See Figure 13.)
BSN AND BSP RESISTORS
To limit the current when charging the bootstrap capacitors, a resistor with a value of 51 Ω (+/-10% maximum)
must be placed in series with each bootstrap capacitor. The current is limited to less than 500 µA.
VCLAMP CAPACITOR
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, an internal
regulator clamps the gate voltage. A 1-µF capacitor must be connected from VCLAMP (pin 7) to ground and
must be rated for at least 25 V. The voltage at VCLAMP (pin 7) varies with VCC and may not be used for
powering any other circuitry.
MIDRAIL BYPASS CAPACITOR
The midrail bypass capacitor (C11 of Figure 13) is the most critical capacitor and serves several important
functions. During start-up or recovery from shutdown mode, CBYPASS determines the rate at which the amplifier
starts up. The second function is to reduce noise produced by the power supply caused by coupling into the
output drive signal. This noise is from the midrail generation circuit internal to the amplifier, which appears as
degraded PSRR and THD+N.
Bypass capacitor (C11) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommended for
the best THD noise, and depop performance. The bypass capacitor must be a value greater than the input
capacitors for optimum depop performance.
VREF DECOUPLING CAPACITOR
The VREF terminal (pin 23) is the output of an internally-generated 5-V supply, used for the oscillator and gain
setting logic. It requires a 0.1-µF to 1-µF capacitor to ground to keep the regulator stable. The regulator may not
be used to power any additional circuitry.
DIFFERENTIAL INPUT
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3007D1 EVM with a differential source, connect the positive lead of the audio source to the INP
input and the negative lead from the audio source to the INN input. To use the TPA3007D1 with a single-ended
source, ac ground the INN input through a capacitor and apply the audio signal to the INP input. In a
single-ended input application, the INN input should be ac-grounded at the audio source instead of at the device
input for best noise performance.
SWITCHING FREQUENCY
The switching frequency is determined using the values of the components connected to ROSC (pin 20) and COSC
(pin 21) and may be calculated with the following equation:
6.6
f
+
s
R
C
OSC OSC
(7)
The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC
.
SHUTDOWN OPERATION
The TPA3007D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal should
be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to
mute and the amplifier to enter a low-current state, ICC(SD) = 1 µA. SHUTDOWN should never be left
unconnected, because amplifier operation would be unpredictable.
16
TPA3007D1
www.ti.com
SLOS418A–SEPTEMBER 2003–REVISED DECEMBER 2004
Ideally, the device should be held in shutdown when the system powers up and brought out of shutdown once
any digital circuitry has settled. However, if SHUTDOWN is to be left unused, the terminal may be connected
directly to VCC
.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance
the more the real capacitor behaves like an ideal capacitor.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3007D1 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
•
•
•
Decoupling capacitors — As described in the Power Supply Decoupling section, the high-frequency 0.1-uF
decoupling capacitors should be placed as close to the PVCC (pin 9 and pin 16) and VCC (pin 24) terminals
as possible. The BYPASS (pin 22) capacitor, VREF (pin 23) capacitor, and VCLAMP (pin 7) capacitor should
also be placed as close to the device as possible. The large (10 uF or greater) bulk power supply decoupling
capacitor should be placed near the TPA3007D1.
Grounding — The VCC (pin 24) decoupling capacitor, VREF (pin 23) capacitor, BYPASS (pin 22) capacitor,
COSC (pin 21) capacitor, and ROSC (pin 20) resistor should each be grounded to analog ground (AGND,
pin 18 and pin 19). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power
ground (PGND, pin 12 and pin 13). Analog ground and power ground should be connected as a central
ground connection or star ground for the TPA3007D1.
Output filter — The ferrite filter (Figure 16) should be placed as close to the output terminals (pins 10, 11, 14,
and 15) as possible for the best EMI performance. The LC filter (Figure 17) should be placed close to the
ferrite filter. The capacitors used in both the ferrite and LC filters should be grounded to power ground.
For an example layout, refer to the TPA3007D1 Evaluation Module (TPA3007D1EVM) User Manual, TI literature
number SLOU164, available on the TI web site at http://www.ti.com.
For further layout information, refer to Layout Guidelines for TPA300x Series Parts, TI literature number
SLOA103, also available on the TI website.
17
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
TPA3007D1PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPA3007D1PWG4
TPA3007D1PWR
TPA3007D1PWRG4
TSSOP
TSSOP
TSSOP
PW
PW
PW
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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