TPA3100D2RGZR [TI]
20-W STEREO CLASS-D AUDIO POWER AMPLIFIER; 20 -W立体声D类音频功率放大器器
| 型号： | TPA3100D2RGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-W STEREO CLASS-D AUDIO POWER AMPLIFIER |
| 文件： | 总31页 (文件大小：2796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3100D2
TQFP
QFN
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
20-W STEREO CLASS-D AUDIO POWER AMPLIFIER
FEATURES
APPLICATIONS
•
Televisions
•
•
•
•
•
20-W/ch into an 8-Ω Load From a 18-V Supply
10-W/ch into an 8-Ω Load From a 12-V Supply
15-W/ch into an 4-Ω Load From a 12-V Supply
Operates from 10 V to 26 V
DESCRIPTION
The TPA3100D2 is a 20-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. The TPA3100D2 can drive stereo
speakers as low as 4 Ω. The high efficiency of the
TPA3100D2, 92%, eliminates the need for an
external heat sink when playing music.
92% Efficient Class-D Operation Eliminates
Need for Heat Sinks
•
•
•
Four Selectable, Fixed Gain Settings
Differential Inputs
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32, 36
dB.
Thermal and Short-Circuit Protection With
Auto Recovery Feature
•
•
•
Clock Output for Synchronization With
Multiple Class-D Devices
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an auto
recovery feature and monitor output.
Surface Mount 7 mm × 7 mm, 48-pin QFN
Package
Surface Mount 7 mm × 7 mm, 48-pin TQFP
Package
Shutdown
and Mute
Shutdown
and Mute
33 mH
Control
Control
Fault
Fault
33 mH
Output
Output
0.1 mF
8 W
0.47 mF
33 mH
0.1 mF
8
W
0.47 mF
33 mH
0.1 mF
0.1 mF
10
V - 26 V
220nF
220nF
10
V
-
26
V
220nF
220nF
10 mF
1
mF
10 mF
1
mF
10
V - 26 V
NC
NC
10
V - 26 V
1
mF
GND
GND
RINN
PVCCR
1
mF
1
mF
RINN
PVCCR
220 mF
1
mF
PVCCR
RINP
220 mF
PVCCR
Differential
Analog
1 mF
RINP
PGNDR
AGND
Differential
Analog
1 mF
AGND
PGNDR
Inputs
1
mF
Inputs
LINP
PGNDR
1
mF
LINP
PGNDR
1
mF
VCLAMPR
1
mF
TPA3100D2
LINN
NC
TPA3100D2
VCLAMPR
1
mF
LINN
1
mF
(QFN Version)
1
mF
(TQFP Version)
VCLAMPL
1
mF
VCLAMPL
GAIN0
GAIN0
PGNDL
4-Step
GAIN0
PGNDL
4-Step
Gain Control
GAIN1
PGNDL
Gain Control
GAIN1
PGNDL
220 mF
MSTR/SLV
PVCCL
220 mF
Synchronize Multiple
MSTR/SLV
PVCCL
Synchronize Multiple
Class-D Devices
SYNC
PVCCL
Class-D Devices
1
mF
SYNC
PVCCL
1
mF
NC
NC
10
V
-
26
V
GND
GND
10
V - 26 V
100 kW
100 kW
220nF
220nF
220nF
220nF
10 nF
10 nF
1
mF
33 mH
1
mF
0.1 mF
33 mH
0.1 mF
8
W
8 W
0.47 mF
33 mH
0.47 mF
33 mH
0.1 mF
0.1 mF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
VI
Supply voltage
Input voltage
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
SYNC
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
Operating free-air temperature range
Operating junction temperature range(2)
Storage temperature range
See Dissipation Rating Table
–40°C to 85°C
–40°C to 150°C
–65°C to 150°C
260°C
TA
TJ
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Load Resistance
RLoad
3.2 Ω Minimum
±2 kV
Human body model (3) (all pins)
Electrostatic discharge
Machine model (4) (all pins)
±200 V
Charged-device model (5) (all pins)
±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the TQFP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method A115-A
(5) In accordance with JEDEC Standard 22, Test Method C101-A
TYPICAL DISSIPATION RATINGS
PACKAGE
48-pin QFN
48-pin TQFP
T
A ≤ 25°C
DERATING FACTOR
37.7 mW/°C(1)
TA = 70°C
3.02 W
TA = 85°C
2.45 W
4.7 W
4.65 W
37.2 mW/°C(2)
2.98 W
2.42 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about
using the QFN thermal pad.
(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the TQFP
thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
MAX
UNIT
VCC
VIH
PVCC, AVCC
10
26
V
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
High-level input voltage
Low-level input voltage
2
V
V
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
SYNC
VIL
0.8
SHUTDOWN, VI = VCC, VCC = 24 V
MUTE, VI = VCC, VCC = 24 V
125
75
IIH
High-level input current
µA
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
VCC = 24 V
2
2
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SHUTDOWN, VI = 0, VCC = 24 V
2
1
IIL
Low-level input current
µA
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0
V, VCC = 24 V
VOH
VOL
fOSC
TA
High-level output voltage
Low-level output voltage
Oscillator frequency
FAULT, IOH = 1 mA
FAULT, IOL = -1 mA
Rosc Resistor = 100 kΩ
VREG - 0.6
V
V
AGND + 0.4
200
–40
300
85
kHz
°C
Operating free-air temperature
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
5
50
mV
Midrail reference for input amplifier
4-V internal supply voltage
VBYP, no load
1.1
1.3 1.45
V
V
VREG, no load, VCC = 10 V to 26 V
3.85
4
4.35
VCC = 12 V to 24 V, inputs ac coupled to AGND,
Gain = 36 dB
PSRR
DC Power supply rejection ratio
-70
dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
22 26.5
mA
µA
ICC(SD)
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load
180 250
ICC(MUTE) Quiescent supply current in mute mode
MUTE = 2 V, no load
8
200
200
10
mA
High Side
VCC = 12 V, IO = 500 mA,
TJ = 25°C
rDS(on)
Drain-source on-state resistance
Low side
mΩ
Total
400 500
GAIN0 = 0.8 V
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
19
25
31
35
20
26
21
27
33
37
GAIN1 = 0.8 V
dB
dB
G
Gain
32
GAIN1 = 2 V
36
Gain matching
Turn-on time
Turn-off time
Between channels
2%
25
tON
C(VBYP) = 1 µF, SHUTDOWN = 2 V
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
ms
ms
tOFF
0.1
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI = 0 V, Gain = 36 dB
MIN
TYP MAX UNIT
Class-D output offset voltage (measured
differentially)
| VOS
|
5
50
mV
Midrail reference for input amplifier
4-V internal supply voltage
VBYP, no load
VREG, no load
1.1
1.4 1.45
V
V
3.85
4
4.35
VCC = 12 V to 24 V, Inputs ac coupled to AGND,
Gain = 36 dB
PSRR
DC Power supply rejection ratio
Quiescent supply current
-70
dB
ICC
SHUTDOWN = 2 V, MUTE = 0 V, no load
18 22.5
80 200
mA
µA
ICC(SD)
Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load
ICC(MUTE) Quiescent supply current in mute mode
MUTE = 2 V, no load
7
200
200
8.1
mA
High Side
Low side
Total
VCC = 12 V, IO = 500 mA,
TJ = 25°C
rDS(on)
Drain-source on-state resistance
mΩ
400 500
3
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
DC CHARACTERISTICS (continued)
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
GAIN0 = 0.8 V
MIN
19
TYP MAX UNIT
20
26
32
36
25
0.1
21
27
33
37
GAIN1 = 0.8 V
dB
dB
GAIN0 = 2 V
GAIN0 = 0.8 V
GAIN0 = 2 V
25
G
Gain
31
GAIN1 = 2 V
35
tON
Turn-on time
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
ms
ms
tOFF
AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
KSVR
PO
Supply ripple rejection
–70
dB
THD+N = 7%, f = 1 kHz, VCC = 18 V
20.6
21.8
0.11%
100
W
W
Continuous output power
THD+N = 10%, f = 1 kHz, VCC = 18 V
VCC = 18 V, f = 1 kHz, PO = 10 W (half-power)
THD+N Total harmonic distortion + noise
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–92
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
Signal-to-noise ratio
102
dB
Thermal trip point
Thermal hysteresis
150
20
°C
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
KSVR
Supply ripple rejection
–70
dB
THD+N = 7%, f = 1 kHz
9.4
10
THD+N = 10%, f = 1 kHz
PO
Continuous output power
W
THD+N = 7%, f = 1 kHz, RL = 4 Ω
THD+N = 10%, f = 1 kHz, RL = 4 Ω
RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power)
RL = 4 Ω, f = 1 kHz, PO = 8 W (half-power)
15.6
16.4
0.11%
0.15%
100
THD+N Total harmonic distortion + noise
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
Po = 1 W, Gain = 20 dB, f = 1 kHz
–80
Crosstalk
–94
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
SNR
Signal-to-noise ratio
98
dB
Thermal trip point
Thermal hysteresis
150
30
°C
°C
4
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
48 PIN, QFN PACKAGE
(TOP VIEW)
48 PIN, TQFP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
48 47 46 45 44 43 42 41 40 39 38 37
36
1
NC
NC
1
36
35
34
33
32
GND
GND
RINN
2
35
RINN
RINP
PVCCR
PVCCR
2
PVCCR
PVCCR
PGNDR
PGNDR
VCLAMPR
VCLAMPL
PGNDL
PGNDL
PVCCL
PVCCL
GND
3
34
33
32
31
30
3
RINP
4
AGND
PGNDR
4
AGND
LINP
5
LINP
LINN
PGNDR
5
Exposed
6
VCLAMPR
Exposed
6
31
30
29
28
27
26
LINN
Thermal Pad
7
VCLAMPL
NC
Thermal Pad
7
GAIN0
GAIN0
GAIN1
8
29 PGNDL
28 PGNDL
27 PVCCL
GAIN0
GAIN1
MSTR/SLV
SYNC
NC
8
9
9
10
11
12
10
11
12
MSTR/SLV
SYNC
26
PVCCL
25
NC
GND
25
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
QFN
NO.
TQFP
NO.
NAME
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
levels with compliance to AVCC.
SHUTDOWN
44
44
I
RINN
RINP
LINN
2
3
6
5
8
9
2
3
I
I
I
I
I
I
Negative audio input for right channel. Biased at VBYP.
Positive audio input for right channel. Biased at VBYP.
6
Negative audio input for left channel. Biased at VBYP.
LINP
5
Positive audio input for left channel. Biased at VBYP.
GAIN0
GAIN1
7, 8
9
Gain select least significant bit. TTL logic levels with compliance to VREG.
Gain select most significant bit. TTL logic levels with compliance to VREG.
1, 12, 13,
24, 25, 36,
37
GND
Connect to the thermal pad.
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
MUTE
45
45
I
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only
reports short-circuit faults. Thermal faults are not reported on this terminal.
FAULT
BSLP
46
18
46
18
O
I/O
Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge, not internally connected to PVCCR
or AVCC.
PVCCL
26, 27
26, 27
LOUTP
PGNDL
LOUTN
BSLN
19, 20
28, 29
21, 22
23
19, 20
28, 29
21, 22
23
O
Class-D 1/2-H-bridge positive output for left channel.
Power ground for left channel H-bridge.
O
Class-D 1/2-H-bridge negative output for left channel.
Bootstrap I/O for left channel, negative high-side FET.
Internally generated voltage supply for left channel bootstrap capacitor.
Internally generated voltage supply for right channel bootstrap capacitor.
Bootstrap I/O for right channel, negative high-side FET.
Class-D 1/2-H-bridge negative output for right channel.
Power ground for right channel H-bridge.
I/O
VCLAMPL
VCLAMPR
BSRN
30
30
31
31
38
38
I/O
O
ROUTN
PGNDR
39, 40
32, 33
39, 40
32, 33
5
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
QFN
I/O
DESCRIPTION
TQFP
NO.
NAME
NO.
41, 42
34, 35
43
ROUTP
PVCCR
BSRP
41, 42
34, 35
43
O
Class-D 1/2-H-bridge positive output for right channel.
Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
Bootstrap I/O for right channel, positive high-side FET.
Analog ground for digital/analog cells in core.
I/O
I/O
I
AGND
ROSC
4, 17
14
4, 17
14
I/O for current setting resistor of ramp generator.
Master/Slave select for determining direction of SYNC terminal.
HIGH=Master mode, SYNC terminal is an output; LOW = slave mode,
SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
MSTR/SLV
10
10
Clock input/output for synchronizing multiple class-D devices. Direction
determined by MSTR/SLV terminal. Input signal not to exceed VREG.
SYNC
VBYP
VREG
AVCC
11
16
15
48
11
16
I/O
O
Reference for preamplifier inputs. Nominally equal to 1.4 V. Also controls
start-up time via external capacitor sizing.
4-V regulated output for use by internal cells, GAINx, MUTE, and
MSTR/SLV pins only. Not specified for driving other external circuitry.
15
O
High-voltage analog power supply. Not internally connected to PVCCR or
PVCCL.
47, 48
1, 7, 12,
13, 24, 25,
36, 37, 47
NC
Not internally connected.
Connect to AGND and PGND – should be star point for both grounds.
Internal resistive connection to AGND and PGND. Thermal vias on the PCB
should connect this pad to a large copper area on an internal or bottom
layer for the best thermal performance. The Thermal Pad must be soldered
to the PCB for mechanical reliability.
Thermal Pad
-
-
-
6
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
FUNCTIONAL BLOCK DIAGRAM
PVCCR
PVCCR
VCLAMPR
PVCCR
VBYP
BSRN
VBYP
AVCC
AVCC
Gain
Gate
ROUTN
Drive
VClamp
RINN
Gain
PWM
Gen
PVCCR
Control
Logic
RINP
VBYP
BSRP
Gate
To Gain Adj.
Blocks and
Startup Logic
Drive
GAIN0
Gain
ROUTP
Control
GAIN1
8
Gain
FAULT
SC
PGNDR
Detect
AVCC
VBYP
Thermal
VREGok
VCCok
ROSC
SYNC
VREG
Ramp
Startup
Protection
Logic
Biases
and
References
Generator
PVCCL
AVCC
MSTR/SLV
PVCCL
VREG
4V Reg
VREG
VCLAMPL
PVCCL
TLL Input
Buffer
BSLN
SHUTDOWN
(VCC Compliant)
TLL Input
Buffer
Gate
MUTE
LOUTN
Drive
(VCC Compliant)
Gain
VClamp
VBYP
Gen
PVCCL
LINN
Gain
PWM
BSLP
Control
Logic
LINP
Gate
LOUTP
Drive
Gain
PGNDL
AGND
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS(1)
FIGURE
THD+N
Total harmonic distortion + noise
Total harmonic distortion + noise
Closed-loop response
Output power
vs Frequency
1, 2, 3, 4
5, 6, 7, 8
9, 10
THD+N
vs Output power
vs Frequency
vs Supply voltage
vs Output power
vs Total output power
vs Frequency
11. 12
13, 14
15, 16
17, 18
19, 20
Efficiency
VCC
Supply current
Crosstalk
kSVR
Supply ripple rejection ratio
vs Frequency
(1) All graphs were measured using the TPA3100D2 EVM.
7
TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
10
V
CC
= 12 V
V
CC
= 18 V
R
L
= 8 Ω
R = 8 Ω
L
Gain = 20 dB
Gain = 20 dB
1
1
P
O
= 2.5 W
P
O
= 0.5 W
P
O
= 0.5 W
0.1
0.1
P
O
= 2.5 W
P = 5 W
O
P
O
= 5 W
0.01
0.01
0.005
0.005
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
FREQUENCY
FREQUENCY
10
10
V
CC
= 24 V
V
CC
= 12 V
R
L
= 8 Ω
R = 4 Ω
L
Gain = 20 dB
Gain = 20 dB
1
1
P
O
= 5 W
P
O
= 1 W
P
O
= 1 W
P
O
= 10 W
0.1
0.1
P
O
= 10 W
P
O
= 5 W
0.01
0.01
0.005
0.005
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 3.
Figure 4.
8
TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
CC
= 12 V
V
CC
= 18 V
R
L
= 8 Ω
R
L
= 8 Ω
Gain = 32 dB
Gain = 32 dB
1
1
10 kHz
10 kHz
1 kHz
1 kHz
0.1
0.1
20 Hz
20 Hz
0.01
0.01
10 m
100 m
1
10 20 40
10 m
100 m
1
10 20 40
P
O
− Output Power − W
P
O
− Output Power − W
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
V
CC
= 12 V
V
CC
= 24 V
R
L
= 4 Ω
R
L
= 8 Ω
Gain = 32 dB
Gain = 32 dB
Power Beyond 20 W
May Require
1
1
More Heatsinking.
10 kHz
10 kHz
1 kHz
1 kHz
0.1
0.1
20 Hz
20 Hz
0.01
0.01
10 m
100 m
1
10 20 40
10 m
100 m
1
10 20 40
P
O
− Output Power − W
P
O
− Output Power − W
Figure 7.
Figure 8.
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
CLOSED LOOP RESPONSE
CLOSED LOOP RESPONSE
vs
vs
FREQUENCY
FREQUENCY
200
150
100
50
200
150
100
50
40
40
35
30
25
20
15
10
5
Gain
35
Gain
30
25
Phase
Phase
20
0
0
15
−50
−50
−100
−150
V
CC
= 12 V
V
CC
= 24 V
10
−100
R
= 8 W
R = 8 W
L
L
Gain = 32 dB
= 0.1 V
Gain = 32 dB
V = 0.1 V
V
5
I
rms
−150
I
rms
RC Filter = 100 W, 0.47 nF
RC Filter = 100 W, 0.47 nF
−200
100k
−200
0
0
10
100
1k
10k
10
100
1k
10k
100k
f − Frequency − Hz
f − Frequency − Hz
Figure 9.
Figure 10.
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
50
35
R
= 8 W
R
= 4 W
L
L
45
Gain = 20 dB
Gain = 20 dB
30
25
20
15
10
5
40
35
30
THD+N = 10%
25
THD+N = 10%
20
THD+N = 1%
THD+N = 1%
15
10
5
Power Represented by
Dash Lines May Require
More Heatsinking.
Power Represented by
Dash Lines May Require
More Heatsinking.
0
0
10 12
14 16
18
20
22
24
26 28
10
11
12
13
14
15
16
V
- Supply Voltage - V
V
CC
− Supply Voltage − V
CC
Figure 11.
Figure 12.
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
EFFICIENCY
vs
OUTPUT POWER
EFFICIENCY
vs
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
V
CC
= 12 V
V
= 12 V
CC
V
= 18 V
CC
V
= 24 V
CC
R
= 8 W
L
R
L
= 4 Ω
Gain = 32 dB
Gain = 32 dB
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10
12
14 15
P
O
− Output Power (Per Channel) − W
P
O
− Output Power (Per Channel) − W
Figure 13.
Figure 14.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
2.5
3.5
R
L
= 8 Ω
R
L
= 4 Ω
Gain = 20 dB
V
CC
= 18 V
Gain = 20 dB
3
2
2.5
V
CC
= 12 V
V
CC
= 12 V
1.5
2
V
CC
= 24 V
1.5
1
1
0.5
Power Represented by
Dash Lines May Require
More Heatsinking.
Power Represented by
Dash Lines May Require
More Heatsinking.
0.5
0
0
0
10
20
30
40
0
10
20
30
40
P
O
− Total Output Power − W
P
O
− Total Output Power − W
Figure 15.
Figure 16.
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
-40
-40
V
CC
= 24 V
V
CC
= 12 V
R
L
= 8 Ω
R
L
= 8 Ω
Gain = 20 dB
Gain = 20 dB
−60
−60
V
= 1 Vrms
V
= 1 Vrms
O
O
L to R
L to R
−80
−80
R to L
R to L
−100
−100
−120
−120
−140
20
−140
20
100
1k
10k 20k
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 17.
Figure 18.
SUPPLY RIPPLE REJECTION RATIO
SUPPLY RIPPLE REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
= 12 V
V
= 18 V
CC
CC
R
= 8 Ω
R = 8 Ω
L
L
Gain = 20 dB
Gain = 20 dB
V = 200 mV
(RIPPLE)
V
= 200 mV
(RIPPLE)
PP
PP
20
100
1k
10k 20k
20
100
1k
10k 20k
f − Frequency − Hz
f − Frequency − Hz
Figure 19.
Figure 20.
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION
33 mH
0.47 mF
33 mH
0.1 mF
8 W
0.1 mF
10 V - 26 V
220nF
220nF
10 mF
1 mF
10 V - 26 V
NC
NC
1 mF
RINN
PVCCR
1 mF
220 mF
PVCCR
RINP
1 mF
Differential
PGNDR
AGND
Analog
Inputs
1 mF
LINP
PGNDR
1 mF
VCLAMPR
LINN
NC
TPA3100D2
1 mF
1 mF
VCLAMPL
GAIN0
PGNDL
4-Step
Gain Control
GAIN1
PGNDL
220 mF
MSTR/SLV
PVCCL
Synchronize Multiple
Class-D Devices
SYNC
PVCCL
1 mF
NC
NC
10 V - 26 V
100 kW
220nF
220nF
10 nF
1 mF
33 mH
0.1 mF
8 W
0.47 mF
33 mH
0.1 mF
Figure 21. Stereo Class-D With Differential Inputs (QFN)
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
33 mH
0.47 mF
33 mH
0.1 mF
8 W
0.1 mF
10 V - 26 V
220nF
220nF
10 mF
1 mF
10 V - 26 V
GND
GND
1 mF
RINN
PVCCR
1 mF
220 mF
PVCCR
RINP
1 mF
Differential
Analog
AGND
PGNDR
Inputs
1 mF
LINP
PGNDR
1 mF
TPA3100D2
VCLAMPR
LINN
(TQFP Version)
1 mF
1 mF
VCLAMPL
GAIN0
GAIN0
PGNDL
4-Step
Gain Control
GAIN1
PGNDL
220 mF
MSTR/SLV
PVCCL
Synchronize Multiple
Class-D Devices
SYNC
PVCCL
1 mF
GND
GND
10 V - 26 V
100 kW
220nF
220nF
10 nF
1 mF
33 mH
0.1 mF
8 W
0.47 mF
33 mH
0.1 mF
Figure 22. Stereo Class-D With Differential Inputs (TQFP)
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3100D2.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 23. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
0 V
Across Load
-12 V
Current
Figure 23. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3100D2 Modulation Scheme
The TPA3100D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
OUTP
OUTN
Output = 0 V
Differential
+12 V
Voltage
0 V
Across
-12 V
Load
Current
OUTP
OUTN
Output > 0 V
Differential
+12 V
Voltage
0 V
Across
-12 V
Load
Current
Figure 24. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3100D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
Design the TPA3100D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use a LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from
the amplifier to the speaker.
When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to
the IC followed by the ferrite bead filter.
33 mH
OUTP
C2
L1
C1
0.1 mF
0.47 mF
33 mH
OUTN
C3
L2
0.1 mF
Figure 25. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
C2
L1
C1
0.22 mF
1 mF
15 mH
OUTN
C3
L2
0.22 mF
Figure 26. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 27. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3)
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TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
Using the LC filter in Figure 25, the TPA3100D2 EMI EVM passed the FCC Part 15 Class B radiated emissions
with 21 inch speaker wires. Quasi-peak measurements were taken for 4 configurations, and the TPA3100D2 EMI
EVM passed with at least a 5.6-dB margin. A plot of the peak measurement for the horizontal rear configuration
is shown in Figure 28.
Figure 28. Radiated Emissions Prescan 30 MHz - 1000 MHz
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
APPLICATION INFORMATION (continued)
Adaptive Dynamic Range Control
TPA3100D2
TPA3100D2
Closest Competitor
Closest Competitor
t - Time = 100 ms/div
t - Time = 20 ms/div
Figure 29. 1-kHz Sine Output at 10% THD+N
Figure 30. 8-kHz Sine Output at 10% THD+N
The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch
inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher
frequencies as shown in Figure 30.
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3100D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 12.8 kΩ, which is the absolute minimum input impedance of the TPA3100D2. At the lower gain
settings, the input impedance could increase as high as 38.4 kΩ
Table 1. Gain Setting
INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
(kΩ)
TYP
32
GAIN1
GAIN0
TYP
20
0
0
1
1
0
1
0
1
26
16
32
16
36
16
INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ± 20%, to
the largest value, 32 kΩ± 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
Z
f
C
i
Z
i
IN
Input
Signal
The -3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1.
1
f =
2p Z C
i
i
(1)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 2.
-3 dB
1
f
=
c
2p Z C
i
i
f
c
(2)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
C =
i
2p Z f
i
c
(3)
In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
Power Supply Decoupling, CS
The TPA3100D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 µF to 1 µF placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near
the audio power amplifier is recommended. The 220 µF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF
capacitor on the AVCC terminal is adequate.
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the
application circuit diagram in Figure 21.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
VCLAMP Capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 30) and
VCLAMPR (pin 31) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminals may
vary with VCC and may not be used for powering any other circuitry.
Internal Regulated 4-V Supply (VREG)
The VREG terminal (pin 15) is the output of an internally generated 4-V supply, used for the oscillator,
preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator
stable.
This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not
be used to drive external circuitry.
VBYP Capacitor Selection
The internal bias generator (VBYP) nominally provides a 1.4-V internal bias for the preamplifier stages. The
external input capacitors and this internal reference allow the inputs to be biased within the optimal
common-mode range of the input preamplifiers.
The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance.
During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the
amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer.
When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the
standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV
is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5.6 ms to reach the value of VBYP and
begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor
on the VBYP terminal.
A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.4-V bias generator.
A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop
performance, the VBYP capacitor should be greater than or equal to the input capacitors.
ROSC Resistor Selection
The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation 4:
1
F
=
OSC
2 x ROSC x COSC
(4)
COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can
result in a ±15% change in this capacitor value.
For example, if ROSC is fixed at 100 kΩ, the frequency from device to device with this fixed resistance could
vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC
resistor should also be considered to determine the range of expected switching frequencies from device to
device. It is recommended that 1% tolerance resistors be used.
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
Differential Input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3100D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3100D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance.
SHUTDOWN OPERATION
The TPA3100D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the
power supply voltage.
MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3100D2. A logic high on this terminal
disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick
disable/enable of outputs when changing channels on a television or transitioning between different audio
sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.
The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event.
When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been
detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault
flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is
removed from the output. If a short remains at the output, the cycle continues until the short is removed.
If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate
can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 31.
TPA3100D2
External GPIO
Control
MUTE
FAULT
Figure 31. External MUTE Control
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TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
MSTR/SLV and SYNC operation
The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching.
When the MSTR/SLV terminal is high, the output switching frequency is determined by the selection of the
resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output
in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL
compatible, push-pull output can be connected to another TPA3100D2, configured in the slave mode. The output
switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D
amplifiers in the same system are switching at slightly different frequencies.
When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave
on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square
wave from another TPA3100D2 configured in the master mode or from an external GPIO. If connecting to an
external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the
maximum amplitude is 4 V.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
23
TPA3100D2
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SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
The TPA3100D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the
outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the
voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if
the short was removed. If the short was not removed, the protection circuitry again activates.
The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status
with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to
the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a
short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and
clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes
if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short
is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired,
an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see
Figure 31.
THERMAL PROTECTION
Thermal protection on the TPA3100D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3100D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
•
Decoupling capacitors—The high-frequency 1µF decoupling capacitors should be placed as close to the
PVCC (pins 26, 27, 34, and 35) and AVCC (pin 48) terminals as possible. The VBYP (pin 16) capacitor,
VREG (pin 15) capacitor, and VCLAMP (pins 30 and 31) capacitor should also be placed as close to the
device as possible. Large (22 µF or greater) bulk power supply decoupling capacitors should be placed near
the TPA3100D2 on the PVCCL, PVCCR, and AVCC terminals.
•
Grounding—The AVCC (pin 48) decoupling capacitor, VREG (pin 15) capacitor, VBYP (pin 16) capacitor,
and ROSC (pin 14) resistor should each be grounded to analog ground (AGND, pin 17). The PVCC
decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 28,
29, 32, and 33). Analog ground and power ground should be connected at the thermal pad, which should be
used as a central ground connection or star ground for the TPA3100D2.
•
•
Output filter—The ferrite EMI filter (Figure 27) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 25 and Figure 26) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are
used, the LC filter should be placed first, following the outputs.
Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 5,1 mm by 5,1 mm. Five rows of
solid vias (five vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Technical Briefs
SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs
SLMA002 for more information about using the TQFP thermal pad. For recommended PCB footprints, see
figures at the end of this data sheet.
For an example layout, see the TPA3100D2 Evaluation Module (TPA3100D2EVM) User Manual, (SLOU179).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
http://www.ti.com.
24
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
BASIC MEASUREMENT SYSTEM
This application note focuses on methods that use the basic equipment listed below:
•
•
•
•
•
•
•
•
•
Audio analyzer or spectrum analyzer
Digital multimeter (DMM)
Oscilloscope
Twisted-pair wires
Signal generator
Power resistor(s)
Linear regulated power supply
Filter components
EVM or other complete audio circuit
Figure 32 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer-input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 32(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 32(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
25
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
Power Supply
Analyzer
20 Hz - 20 kHz
Signal
APA
R
L
Generator
(a) Basic Class-AB
Power Supply
Low-Pass RC
Filter
Analyzer
20 Hz - 20 kHz
Signal
Generator
R
L
Class-D APA
(See note A)
Low-Pass RC
Filter
(b) Filter-Free and Traditional Class-D
A. For efficiency measurements with filter-free Class-D, RL should be an inductive load like a speaker.
Figure 32. Audio Measurement Systems
The TPA3100D2 uses a modulation scheme that does not require an output filter for operation, but they do
sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs
cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level
of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer
can measure the output sine wave.
DIFFERENTIAL INPUT AND BTL OUTPUT
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 33. The differential input is a balanced input,
meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
26
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
Evaluation Module
Audio Power
Generator
Analyzer
Amplifier
Low-Pass
C
IN
RC Filter
R
GEN
R
IN
R
R
C
OUT
ANA
ANA
R
L
V
GEN
C
IN
Low-Pass
R
OUT
RC Filter
R
R
R
ANA
C
GEN
IN
ANA
Twisted-Pair Wire
Twisted-Pair Wire
Figure 33. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
•
•
•
•
•
Use a balanced source to supply the input signal.
Use an analyzer with balanced inputs.
Use twisted-pair wire for all connections.
Use shielding when the system environment is noisy.
Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 2).
Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 2. Recommended Minimum Wire Size for Power Cables
DC POWER LOSS
(MW)
AC POWER LOSS
(MW)
POUT (W)
RL(Ω)
AWG Size
10
4
4
8
8
18
18
22
22
22
22
28
28
16
3.2
2
40
8
18
3.7
2.1
1.6
42
8.5
8.1
6.2
2
1
8
< 0.75
1.5
6.1
CLASS-D RC LOW-PASS FILTER
An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 34. RL
is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be
available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the
system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin
to minimize ground loops.
27
TPA3100D2
www.ti.com
SLOS469B–OCTOBER 2005–REVISED OCTOBER 2005
Load
RC Low-Pass Filters
AP Analyzer Input
R
FILT
R
C
C
FILT
ANA
ANA
V = V
L
IN
R
V
L
OUT
R
FILT
R
ANA
C
ANA
C
FILT
To APA
GND
Figure 34. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs
The transfer function for this circuit is shown in Equation 5 where ωO = REQCEQ, REQ = RFILT || RANA and
CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation 6 provides this cutoff frequency, fC. The value of RFILT
must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the
attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A general rule is
that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than
1% for RANA ≥ 10 kΩ.
R
ANA
(
)
R
+ R
V
ANA
FILT
OUT
=
(
)
V
w
IN
1 + j
w
O
(
)
(5)
(6)
f =
c
Ö2 x f
max
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 3 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated using . When the calculated value
is not available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value
calculated in Equation 7.
1
C
=
FILT
2p x f x R
c
FILT
(7)
Table 3 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but
the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and
fC is 34 kHz, which is above the desired value of 28 kHz.
Table 3. Typical RC Measurement Filter Values
MEASUREMENT
Efficiency
RFILT
1000 Ω
100 Ω
CFILT
5,600 pF
56,000 pF
All other measurements
28
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
Drawing
TPA3100D2RGZR
TPA3100D2RGZT
PREVIEW
PREVIEW
RGZ
48
48
TBD
TBD
Call TI
Call TI
Call TI
Call TI
RGZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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