TPA3118D2DAP [TI]
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance; 15W ， 30W ， 50W无滤波器D类立体声放大器系列与AM避免
| 型号： | TPA3118D2DAP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance |
| 文件： | 总34页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPA3116D2
TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance
Check for Samples: TPA3116D2 , TPA3118D2, TPA3130D2
1
FEATURES
DESCRIPTION
The TPA31xxD2 series are stereo efficient, digital
amplifier power stage for driving speakers up to
100W/2Ω in mono. The high efficiency of the
TPA3130D2 allows it to do 2x15W without external
heat sink on a single layer PCB. The TPA3118D2 can
even run 2x30W/8Ω without heat sink on a dual layer
PCB. If even higher power is needed the TPA3116D2
does 2x50W/4Ω with a small heat-sink attached to its
top side PowerPad. All three devices share the same
footprint enabling a single PCB to be used across
different power levels.
•
Supports Multiple Output Configurations
–
–
–
2×50-W into a 4-Ω BTL Load at 21 V
(TPA3116D2)
2×30-W into a 8-Ω BTL Load at 24 V
(TPA3118D2)
2×15-W into a 8-Ω BTL Load at 15 V
(TPA3130D2)
•
•
Wide Voltage Range: 4.5 V – 26 V
Efficient Class-D Operation
–
>90% Power Efficiency Combined with Low
Idle Loss Greatly Reduces Heat Sink Size
The TPA31xxD2 advanced oscillator/PLL circuit
employs a multiple switching frequency option to
avoid AM interferences; this is achieved together with
an option of Master/Slave option, making it possible
to synchronize multiple devices.
–
Advanced Modulation Schemes
•
Multiple Switching Frequencies
–
–
–
AM Avoidance
The TPA31xxD2 devices are fully protected against
faults with short-circuit protection and thermal
protection as well as over-voltage, under-voltage and
DC protection. Faults are reported back to the
processor to prevent devices from being damaged
during overload conditions.
Master/Slave Synchronization
Up to 1.2 MHz Switching Frequency
•
Feedback Power Stage Architecture with High
PSRR Reduces PSU Requirements
•
•
•
Programmable Power Limit
Differential/Single-Ended Inputs
Simplified Application Circuit
Stereo and Mono Mode with Single Filter Mono
Configuration
4.5 V-26 V
PSU
Audio Processor
TPA3116D2
And control
Tuner AM/FM
Right
•
•
Single Power Supply Reduces Component
Count
PBTL
Detect
Left
Right
Left
LC Filter
LC Filter
CD/ MP3
Aux in
SDZ
MUTE
Integrated Self-Protection Circuits Including
Over-Voltage, Under-Voltage, Over-
Temperature, DC-Detect, and Short Circuit
with Error Reporting
FAULTZ
AM/FM Avoidance
Control
AM2,1,0
GAIN control and Master /Slave setting
Power Limit
GAIN/SLV
PLIMIT
Sync
Capable of synchronizing to other devices
•
•
Thermally Enhanced Packages
–
–
DAD (32-pin HTSSOP Pad-up)
DAP (32-pin HTSSOP Pad-down)
DEVICE
POWER
HTSSOP 32-PIN
Pad down (DAP)
Pad down (DAP)
Pad up (DAD)
TPA3130D2
TPA3118D2
TPA3116D2
2 x 15W/8Ω
2 x 30W/8Ω
2 x 50W/4Ω
–40°C to 85°C Ambient Temperature Range
APPLICATIONS
•
•
•
•
Mini-Micro Component, Speaker Bar, Docks
After-Market Automotive
CRT TV
Consumer Audio Applications
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL ASSIGNMENT
TPA3116D2
TPA3130D2 and TPA3118D2
32-PIN HTSSOP PACKAGE (DAD)
32-PIN HTSSOP PACKAGE (DAP)
PACKAGE
(TOP VIEW)
PACKAGE
(TOP VIEW)
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PVCC
PVCC
BSPR
OUTPR
GND
MODSEL
SDZ
MODSEL
SDZ
2
3
FAULTZ
RINP
3
FAULTZ
RINP
4
4
RINN
5
RINN
5
PLIMIT
GVDD
GAIN/SLV
GND
6
OUTNR
BSNR
GND
PLIMIT
GVDD
GAIN/SLV
GND
6
OUTNR
BSNR
GND
7
7
8
8
Thermal
PAD
Thermal
PAD
9
BSPL
OUTPL
GND
9
BSPL
OUTPL
GND
LINP
10
11
12
13
14
15
16
LINP
10
11
12
13
14
15
16
Top
Bottom
LINN
LINN
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
AM1
AM1
AM0
AM0
SYNC
SYNC
Terminal Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1
2
3
MODSEL
I
Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to
AVCC.
SDZ
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with
compliance to AVCC.
FAULTZ
DO
General fault reporting including Over-temp, DC Detect. Open drain.
FAULTZ = High, normal operation
FAULTZ = Low, fault condition
4
5
6
RINP
I
I
I
Positive audio input for right channel. Biased at 3 V.
Negative audio input for right channel. Biased at 3 V.
RINN
PLIMIT
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly
to GVDD for no power limit.
7
GVDD
PO
Internally generated gate voltage supply. Not to be used as a supply or connected to any component other
than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
8
9
GAIN/SLV
GND
I
G
I
Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
Ground
10 LINP
11 LINN
12 MUTE
Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
I
I
Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic
levels with compliance to AVCC.
13 AM2
14 AM1
I
I
AM Avoidance Frequency Selection
AM Avoidance Frequency Selection
(1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.
2
Copyright © 2012, Texas Instruments Incorporated
TPA3116D2
TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
Terminal Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
15 AM0
I
DIO
P
AM Avoidance Frequency Selection
16 SYNC
17 AVCC
18 PVCC
19 PVCC
20 BSNL
21 OUTNL
22 GND
Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
Analog Supply
P
Power supply
P
Power supply
BST
PO
G
Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
Negative left channel output
Ground
23 OUTPL
24 BSPL
25 GND
PO
BST
G
Positive left channel output
Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL
Ground
26 BSNR
27 OUTNR
28 GND
BST
PO
G
Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR
Negative right channel output
Ground
29 OUTPR
30 BSPR
31 PVCC
32 PVCC
PO
BST
P
Positive right channel output
Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR
Power supply
P
Power supply
33 Thermal Pad
or
G
Connect to GND for best system performance. If not connected to GND, leave floating.
PowerPAD
Copyright © 2012, Texas Instruments Incorporated
3
TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
SYSTEM BLOCK DIAGRAM
GVDD
PVCC
BSPR
SDZ
PVCC
TTL
Buffer
Modulation and
PBTL Select
MUTE
Gain
Control
OUTPR_FB
Gate
Drive
OUTPR
GAIN
+
OUTPR FB
–
–
–
–
GND
RINP
+
+
PWM
Logic
Gain
Control
PLIMIT
GVDD
–
PVCC
–
RINN
+
BSNR
+
PVCC
OUTPNR FB
FAULTZ
OUTNR_
FB
+
Gate
Drive
OUTNR
GND
SC Detect
DC Detect
SYNC
GAIN/SLV
Ramp
Generator
Startup Protection
Logic
Biases and
References
Thermal
Detect
AM<2:0>
PLIMIT
Reference
PLIMIT
UVLO/OVLO
GVDD
PVCC
BSNL
AVDD
PVCC
LDO
Regulator
AVCC
GVDD
Gate
Drive
OUTNL
GVDD
+
OUTNL_FB
OUTNL_
FB
–
–
–
LINN
GND
+
Gain
Control
PWM
Logic
PLIMIT
GVDD
–
LINP
PVCC
+
+
+
BSPL
PVCC
OUTPL_FB
–
Gate
Drive
OUTPL
GND
Input
PBTL
Modulation and
PBTL Select
Sense
Select
OUTPL_FB
GND
Thermal
Pad
4
Copyright © 2012, Texas Instruments Incorporated
TPA3116D2
TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
–0.3 to 30
–0.3 to 6.3
–0.3 to GVDD+0.3
–0.3 to PVCC+0.3
10
UNIT
Supply voltage, VCC
Input voltage, VI
PVCC, AVCC
V
V
INPL, INNL, INPR, INNR
PLIMIT, GAIN / SLV, SYNC
AM0, AM1, AM2, MUTE, SDZ, MODSEL
AM0, AM1, AM2, MUTE, SDZ, MODSEL
V
V
Slew rate, maximum(2)
V/msec
°C
Operating free-air temperature, TA
–40 to 85
–40 to 150
–40 to 125
±2
Operating junction temperature range, TJ
Storage temperature range, Tstg
°C
°C
Electrostatic discharge: Human body model, ESD
Electrostatic discharge: Charged device model, ESD
kV
V
±500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 100 kΩ series resistor is needed if maximum slew rate is exceeded.
THERMAL INFORMATION
TPA3130D2
TPA3118D2
TPA3116D2
DAP
DAP
DAD
THERMAL METRIC(1)
UNITS
1 Layer PCB(2)
2 Layer PCB(3)
Heatsink(4)
32 PINS
36
32 PINS
22
32 PINS
14
θJA
ψJT
ψJB
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.4
0.3
1.2
°C/W
5.9
4.8
5.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For the PCB layout please see the TPA3130D2EVM user guide. A 1 layer 90x85mm 1oc PCB was used
(3) For the PCB layout please see the TPA3130D2EVM user guide. A 2 layer 90x85mm 1oc PCB was used
(4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
VCC
VIH
Supply voltage
PVCC, AVCC
4.5
26
V
High-level input
voltage
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
2
V
Low-level input
voltage
VIL
VOL
IIH
AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL
FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V
0.8
0.8
50
V
V
Low-level output
voltage
High-level input
current
AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V)
µA
TPA3116D2, TPA3118D2
3.2
5.6
1.6
3.2
4
8
RL(BTL)
Output filter: L = 10 µH, C = 680 nF
Output filter: L = 10 µH, C = 1 µF
TPA3130D2
Minimum load
Impedance
Ω
TPA3116D2, TPA3118D2
TPA3130D2
RL(PBTL)
Lo
4
Output-filter
Inductance
Minimum output filter inductance under short-circuit condition
1
µH
Copyright © 2012, Texas Instruments Incorporated
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TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
MAX UNIT
DC ELECTRICAL CHARACTERISTICS
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Class-D output offset voltage (measured
differentially)
| VOS
ICC
|
VI = 0 V, Gain = 36 dB
1.5
15
mV
mA
SDZ = 2 V, No load or filter, PVCC = 12 V
SDZ = 2 V, No load or filter, PVCC = 24 V
SDZ = 0.8 V, No load or filter, PVCC = 12 V
SDZ = 0.8 V, No load or filter, PVCC = 24 V
20
32
35
50
Quiescent supply current
<50
50
Quiescent supply current in shutdown
mode
ICC(SD)
rDS(on)
µA
mΩ
dB
400
Drain-source on-state resistance,
measured pin to pin
PVCC = 21 V, Iout = 500 mA, TJ = 25°C
120
R1 = open, R2 = 20 kΩ
R1 = 100 kΩ, R2 = 20 kΩ
R1 = 100 kΩ, R2 = 39 kΩ
R1 = 75 kΩ, R2 = 47 kΩ
R1 = 51 kΩ, R2 = 51 kΩ
R1 = 47 kΩ, R2 = 75 kΩ
R1 = 39 kΩ, R2 = 100 kΩ
R1 = 16 kΩ, R2 = 100 kΩ
SDZ = 2 V
19
25
31
35
19
25
31
35
20
26
32
36
20
26
32
36
10
2
21
27
33
37
21
27
33
37
G
G
Gain (BTL)
Gain (SLV)
dB
dB
dB
ton
Turn-on time
ms
µs
V
tOFF
GVDD
Turn-off time
SDZ = 0.8 V
Gate drive supply
IGVDD < 200 µA
6.4
6.9
7.4
Output voltage maximum under PLIMIT
control
VO
V(PLIMIT) = 2 V; VI = 1 Vrms
6.75
7.90
8.75
V
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs AC-
coupled to GND
KSVR
PO
Power supply ripple rejection
–70
dB
THD+N = 10%, f = 1 kHz, PVCC = 14.4 V
THD+N = 10%, f = 1 kHz, PVCC = 21 V
VCC = 21 V, f = 1 kHz, PO = 25 W (half-power)
25
50
Continuous output power
W
THD+N Total harmonic distortion + noise
0.1%
65
µV
dBV
dB
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
VO = 1 Vrms, Gain = 20 dB, f = 1 kHz
–80
–100
Crosstalk
Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB,
A-weighted
SNR
Signal-to-noise ratio
102
dB
AM2=0, AM1=0, AM0=0
AM2=0, AM1=0, AM0=1
AM2=0, AM1=1, AM0=0
AM2=0, AM1=1, AM0=1
AM2=1, AM1=0, AM0=0
AM2=1, AM1=0, AM0=1
AM2=1, AM1=1, AM0=0
AM2=1, AM1=1, AM0=1
376 400
470 500
564 600
940 1000
1128 1200
424
530
636
1060
kHz
fOSC
Oscillator frequency
1278
Reserved
Thermal trip point
Thermal hysteresis
150+
15
°C
°C
TPA3130D2
4.5
Over current trip point
A
TPA3118D2, TPA3116D2
7.5
6
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Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2
TPA3116D2
TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
TYPICAL CHARACTERISTICS
fs = 400 kHz, BD Mode (unless otherwise noted)
TOTAL HARMONIC DISTORTION +NOISE (BTL)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
vs
FREQUENCY
FREQUENCY
10
1
10
1
PO = 0.5W
PO = 1W
PO = 2.5W
PO = 1W
PO = 2.5W
PO = 5W
Gain = 26dB
PVCC = 6V
TA = 25°C
RL = 4Ω
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G002
G003
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE (BTL)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
vs
FREQUENCY
FREQUENCY
10
1
10
1
PO = 1W
PO = 5W
PO = 10W
PO = 1W
PO = 2.5W
PO = 5W
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 4Ω
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 8Ω
0.1
0.1
0.01
0.001
0.01
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G004
G005
Figure 3.
Figure 4.
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TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
vs
FREQUENCY
OUTPUT POWER
10
10
1
PO = 1W
PO = 5W
PO = 10W
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 8Ω
Gain = 26dB
PVCC = 6V
TA = 25°C
RL = 4Ω
1
0.1
0.1
0.01
0.001
0.01
f = 20Hz
f = 1kHz
f = 6kHz
0.001
20
100
1k
10k 20k
0.01
0.1
1
10
Frequency (Hz)
Output Power (W)
G006
G008
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE (BTL)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
vs
OUTPUT POWER
OUTPUT POWER
10
1
10
1
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 4Ω
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
1
10
40
0.01
0.1
1
10
100
Output Power (W)
Output Power (W)
G009
G010
Figure 7.
Figure 8.
8
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Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2
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TPA3118D2
TPA3130D2
www.ti.com
SLOS708B –APRIL 2012–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs
vs
OUTPUT POWER
OUTPUT POWER
10
10
1
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 8Ω
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 8Ω
1
0.1
0.1
0.01
0.01
f = 20Hz
f = 1kHz
f = 6kHz
f = 20Hz
f = 1kHz
f = 6kHz
0.001
0.001
0.01
0.1
1
10
50
0.01
0.1
1
10
50
Output Power (W)
Output Power (W)
G011
G012
Figure 9.
Figure 10.
OUTPUT POWER (BTL)
vs
GAIN/PHASE (BTL)
vs
PLIMIT VOLTAGE
FREQUENCY
30
20
300
200
100
0
50
Gain = 26dB
TA = 25°C
PVCC = 24V
RL = 4Ω
40
30
20
10
0
10
0
−10
−20
−30
−40
−50
−100
−200
−300
−400
−500
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
Gain
Phase
20
100
1k
10k
100k
Frequency (Hz)
0
1
2
3
4
G014
PLIMIT Voltage (V)
G013
Figure 11.
Figure 12.
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TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
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TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
MAXIMUM OUTPUT POWER (BTL)
MAXIMUM OUTPUT POWER (BTL)
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
50
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Gain = 26dB
TA = 25°C
RL = 8Ω
Gain = 26dB
TA = 25°C
RL = 4Ω
45
40
35
30
25
20
15
10
5
THD+N = 1%
THD+N = 10%
THD+N = 1%
THD+N = 10%
0
0
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
G015
G016
Figure 13.
Figure 14.
POWER EFFICIENCY (BTL)
POWER EFFICIENCY (BTL)
vs
vs
OUTPUT POWER
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVCC = 6V
PVCC =12V
PVCC = 24V
PVCC = 6V
PVCC = 12V
PVCC = 24V
Gain = 26dB
TA = 25°C
RL = 8Ω
Gain = 26dB
TA = 25°C
RL = 4Ω
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
Output Power (W)
Output Power (W)
G017
G018
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
CROSSTALK
vs
CROSSTALK
vs
FREQUENCY
FREQUENCY
0
0
−10
Gain = 26dB
PVCC = 24V
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
−10
TA = 25°C
RL = 8Ω
−20
−20
−30
−30
−40
−50
−40
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−130
−140
−100
−110
−120
−130
−140
Right to Left
Left to Right
Right to Left
Left to Right
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G021
G022
Figure 17.
Figure 18.
SUPPLY RIPPLE REJECTION RATIO (BTL)
TOTAL HARMONIC DISTORTION + NOISE (PBTL)
vs
vs
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
10
Gain = 26dB
PVCC = 12VDC + 200mVP-P
TA = 25°C
RL = 8Ω
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 2Ω
1
0.1
0.01
0.001
PO = 1W
PO = 5W
PO = 10W
Left Channel
Right Channel
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
G023
G024
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE (PBTL)
MAXIMUM OUTPUT POWER (PBTL)
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
180
160
140
120
100
80
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 2Ω
Gain = 26dB
TA = 25°C
RL = 2Ω
1
0.1
60
0.01
40
f = 20Hz
f = 1kHz
20
THD+N = 1%
f = 6kHz
THD+N = 10%
0.001
0
0.01
0.1
1
10
40
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Output Power (W)
G025
G027
Figure 21.
Figure 22.
POWER EFFICIENCY (PBTL)
SUPPLY RIPPLE REJECTION RATIO (PBTL)
vs
vs
OUTPUT POWER
FREQUENCY
100
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Gain = 26dB
PVCC = 12VDC + 200mVP-P
TA = 25°C
RL = 2Ω
90
80
70
60
50
40
30
20
10
0
PVCC = 6V
PVCC = 12V
PVCC =24V
Gain = 26dB
TA = 25°C
RL = 2Ω
0
10
20
30
40
50
60
70
80
90 100
20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)
G028
G030
Figure 23.
Figure 24.
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SLOS708B –APRIL 2012–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
fs = 400 kHz, BD Mode (unless otherwise noted)
TOTAL HARMONIC DISTORTION + NOISE (PBTL)
MAXIMUM OUTPUT POWER (PBTL)
vs
vs
OUTPUT POWER
SUPPLY VOLTAGE
10
140
130
120
110
100
90
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 3Ω
Gain = 26dB
TA = 25°C
RL = 3Ω
1
80
0.1
70
60
50
40
0.01
30
20
f = 20Hz
f = 1kHz
f = 6kHz
THD+N = 1%
THD+N = 10%
10
0.001
0
0.01
0.1
1
10
100 200
4
6
8
10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Output Power (W)
G032
G034
Figure 25.
Figure 26.
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DEVICE INFORMATION
TYPICAL APPLICATION
PVCC DECOUPLING
PVCC
OUTPUT LC FILTER
EMI C-RC SNUBBER
1
2
PVCC
C57
10nF
L7
10uH
R15
3.3R
1
2
1
2
C20
1nF
C21
C22
GND
100nF
220uF
R10 3.3R
R13
C58 100nF
U1
C26
680nF
C30
1nF
GND
GND
PVCC
C34
10nF
100k
GND
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
+
MODSEL
SDZ
PVCC
PVCC
BSPR
OUTPR
GND
GND
4R
/SD_LR
C16 220nF
1 2
GND
GND
-
C11 1uF
1
3
FAULTZ
INPR
2
C37
10nF
C31
IN_P_RIGHT
IN_N_RIGHT
4
2
1
C27
680nF
5
1nF
INNR
PLIMIT
GVDD
GAIN/SLV
GND
C12 1uF
6
R16
3.3R
OUTNR
BSNR
GND
7
1
2
1
1
2
R11
100k
8
C17 220nF
C18 220nF
C15
1uF
L8
10uH
2
9
1
2
R12
20k
BSPL
10
11
12
13
14
15
16
L10
10uH
R17
3.3R
INPL
OUTPL
GND
C13 1uF
GND
INNL
2
1
1
C28
680nF
C32
1nF
IN_P_LEFT
IN_N_LEFT
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
2
C38
10nF
1
2
C14 1uF
C19 220nF
+
MUTE_LR
AM1
4R
1
2
GND
GND
C40
10nF
C33
1nF
AM0
PVCC
-
R14 100k
SYNC
C29
680nF
GND
C23
1nF
C24
100nF
C25
TPA3116D2
R18
3.3R
220uF
L9
10uH
1
2
GND
PVCC DECOUPLING
PVCC DECOUPLING
R73
10k
PVCC
C47
220uF
C45
1nF
C46
PVCC
100nF
GND
U2
R19
GND
100k
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MODSEL
SDZ
PVCC
PVCC
BSPR
OUTPR
GND
OUTPUT LC FILTER
EMI C-RC SNUBBER
/SD_SUB
1
2
C42 220nF
1 2
C35 1uF
1
3
FAULTZ
INPR
2
L15
10uH
R23
3.3R
IN_P_SUB
IN_N_SUB
4
2
1
5
C51
1uF
C53
1nF
INNR
PLIMIT
GVDD
GAIN/SLV
GND
C36 1uF
6
C55
10nF
OUTNR
BSNR
GND
7
1
2
R20
47k
+
8
C43 220nF
C43 220nF
C39
1uF
2R
9
1
2
R21
75k
GND
GND
-
BSPL
10
11
12
13
14
15
16
C56
10nF
C54
INPL
OUTPL
GND
C52
1uF
INNL
GND
1nF
MUTE_SUB
MUTE
AM2
OUTNL
BSNL
PVCC
PVCC
AVCC
R24
3.3R
1
2
1
2
R22
C44 220nF
100k
AM1
L16
10uH
AM0
PVCC
SYNC
GND
C41
1nF
C48
1nF
C49
100nF
C50
TPA3116D2
220uF
GND
GND
PVCC DECOUPLING
Figure 27. Schematic
A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in
Slave, PBTL mode gain of 20dB. Inputs are connected for differential inputs.
In the following sections the TPA3116D2, TPA3118D2, and TPA3130D2 are referred to as: TPA31xxD2 family.
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GAIN SETTING AND MASTER / SLAVE
The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or
Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four
stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets
the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while device is powered. Table 1 shows the recommended resistor values and the state
and gain:
Table 1. GAIN and MASTER/SLAVE
MASTER / SLAVE
GAIN
R1 (to GND)(1)
R2 (to GVDD)(1)
INPUT IMPEDANCE
MODE
Master
Master
Master
Master
Slave
20 dB
26 dB
32 dB
36 dB
20 dB
26 dB
32 dB
36 dB
5.6 kΩ
20 kΩ
39 kΩ
47 kΩ
51 kΩ
75 kΩ
100 kΩ
100 kΩ
OPEN
100 kΩ
100 kΩ
75 kΩ
51 kΩ
47 kΩ
39 kΩ
16 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
60 kΩ
30 kΩ
15 kΩ
9 kΩ
Slave
Slave
Slave
(1) Resistor tolerance should be 5% or better.
5
6
INNR
2
1
PLIMIT
GVDD
1
C5 1 µF
2
7
2
1
R2
8
51 k
GAIN/SLV
GND
9
R1 51 k
10
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
INPUT IMPEDANCE
The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the
gain setting from 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to
be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-
ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter
with the following cut-off frequency:
1
ƒ
=
2pZiCi
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10
times lower capacitors can used – for example, a 1 µF can be used.
Table 2. Recommended Input AC-Coupling Capacitors
GAIN
20 dB
26 dB
32 dB
36 dB
INPUT IMPEDANCE
INPUT CAPACITANCE
HIGH-PASS FILTER
1.8 Hz
60 kΩ
30 kΩ
15 kΩ
9 kΩ
1.5 µF
3.3 µF
5.6 µF
10 µF
1.6 Hz
2.3 Hz
1.8 Hz
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Z
f
C
i
Z
i
IN
Input
Signal
The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a
polarized type is used the positive connection should face the input pins which are biased to 3 Vdc.
START-UP/SHUTDOWN OPERATION
The TPA31xxD2 family employs a shutdown mode of operation designed to reduce supply current (Icc) to the
absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low
will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ
unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is
selected and cannot be changed until the next power-up.
PLIMIT OPERATION
The TPA31xxD2 family has a built-in voltage limiter that can be used to limit the output voltage level below the
supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the
output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external
reference may also be used if tighter tolerance is required. Add a 1 µF capacitor from pin PLIMIT to ground to
ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.
Figure 28. POWER LIMIT Example
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage
can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
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æ
ö2
æ
ç
è
ö
÷
ø
RL
´ V
ç
÷
P
ç
÷
RL + 2 ´ RS
è
ø
POUT
=
for unclipped power
2 ´ RL
(2)
Where:
RS is the total series resistance including RDS(on), and output filter resistance.
RL is the load resistance.
VP is the peak amplitude
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10%THD) = 1.25 × POUT (unclipped)
Table 3. POWER LIMIT Example
PVCC (V)
24 V
PLIMIT VOLTAGE (V)(1)
R to GND
Short
R to GVDD
Open
OUTPUT VOLTAGE (Vrms)
GVDD
3.3
17.90
12.67
9.00
24 V
45 kΩ
24 kΩ
Short
51 kΩ
24 V
2.25
GVDD
2.25
1.5
51 kΩ
12 V
Open
10.33
9.00
12 V
24 kΩ
18 kΩ
51 kΩ
12 V
68 kΩ
6.30
(1) PLIMIT measurements taken with EVM gain set to 26dB and input voltage set to 1Vrms
.
GVDD SUPPLY
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The
GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption
by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more.
BSPx AND BSNx CAPACITORS
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at
least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit
diagram in Figure 27.) The bootstrap capacitors connected between the BSxx pins and corresponding output
function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each
high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-
side MOSFETs turned on.
DIFFERENTIAL INPUTS
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA31xxD2 family with a differential source, connect the positive lead of the audio source to the RINP or
LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA31xxD2 family
with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor
on positive and apply the audio source to either input. In a single-ended input application, the unused input
should be ac grounded at the audio source instead of at the device input for best noise performance. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
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MONO MODE (PBTL)
The TPA31xxD2 family can be connected in MONO mode enabling up to 100W output power. This is done by:
•
•
•
Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during
power up.
Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for
the negative terminal
Analog input signal is applied to INPR and INNR
TPA3116D2
4.5 V–26 V
PSU
OUTPR
OUTNR
Right
LC Filter
OUTPL
OUTNL
PBTL
Detect
Left
DEVICE PROTECTION SYSTEM
The TPA31xxD2 family contains a complete set of protection circuits carefully designed to make system design
efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload,
over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to the fault
table below:
Table 4. Fault Reporting
TRIGGERING CONDITION
(typical value)
LATCHED/SELF-
CLEARING
FAULT
FAULTZ
ACTION
Over Current
Output short or short to PVCC or GND
Tj > 150°C
Low
Low
Low
Output high impedance
Output high impedance
Output high impedance
Latched
Latched
Latched
Over Temperature
Too High DC Offset
DC output voltage
Under Voltage on
PVCC
PVCC < 4.5V
PVCC > 27V
–
–
Output high impedance
Output high impedance
Self-clearing
Self-clearing
Over Voltage on
PVCC
DC DETECT PROTECTION
The TPA31xxD2 family has circuitry which will protect the speakers from DC current which might occur due to
defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be
reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by
changing the state of the outputs to Hi-Z.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect
protection latch.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than
420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection
threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or
AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-
up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and
negative inputs to avoid nuisance DC detect faults.
The minimum output offset voltages required to trigger the DC detect are show in Table 5. The outputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
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Table 5. DC Detect Threshold
PVCC (V)
VOS - OUTPUT OFFSET VOLTAGE (V)
4.5
6
0.96
1.30
2.60
3.90
12
18
SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE
The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage.
The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched
to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling
the SDZ pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the short-
circuit protection latch.
In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a
car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a high-
Z restart, like shown in the figure below:
> 1.4sec
SDZ
MUTE
mP
TPA3116D2
FAULTZ
SDZ
MUTE
FAULTZ
Figure 29. MUTE Driven by Inverted FAULTZ
THERMAL PROTECTION
Figure 30. Timing Requirement for SDZ
Thermal protection on the TPA31xxD2 family prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a
latched fault.
Thermal protection faults are reported on the FAULTZ terminal as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ
pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal
protection latch.
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TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
TPA3116/18/30D2 MODULATION SCHEME
The TPA31xxD2 family has the option of running in either BD modulation or 1SPW modulation; this is set by the
MODSEL pin.
MODSEL = GND: BD-modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
-
OUTP OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
OUTP-OUTN
-
PVCC
0A
Speaker
Current
Figure 31. BD Mode Modulation
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SLOS708B –APRIL 2012–REVISED MAY 2012
MODSEL = HIGH: 1SPW-modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate
at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will
increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place
through the rising output. The result is that only one output is switching during a majority of the audio cycle.
Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is
minimized by the high performance feedback loop. The resulting audio signal at each half output has a
discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless
care is taken in the selection of the filter components and type of filter used.
OUTP
OUTN
No Output
0V
OUTP-OUTN
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
0V
-PVCC
OUTP
-OUTN
0
A
Speaker
Current
Figure 32. 1SPW Mode Modulation
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TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
EFFICIENCY: LC FILTER REQUIRED WITH THE TRADITIONAL CLASS-D MODULATION
SCHEME
The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the
switching waveform results in maximum current flow. This causes more loss in the load, which causes lower
efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is
proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the
time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store
the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The
speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
FERRITE BEAD FILTER CONSIDERATIONS
Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a
high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite
bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz
range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer
electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation
in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good
antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a
value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best
performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM
user guide SLOU341.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND pins on the IC.
22
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TPA3118D2
TPA3130D2
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SLOS708B –APRIL 2012–REVISED MAY 2012
Figure 33.
WHEN TO USE AN OUTPUT FILTER FOR EMI SUPPRESSION
The TPA3116D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3116D2 EVM passes FCC class-B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
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TPA3116D2
TPA3118D2
TPA3130D2
SLOS708B –APRIL 2012–REVISED MAY 2012
www.ti.com
10 µH
L1
OUTP
C2
0.68 µF
4 W - 8 W
10 µH
L2
OUTN
C3
0.68 µF
Ferrite
Chip Bead
OUTP
OUTN
1 nF
1 nF
4 W - 8 W
Ferrite
Chip Bead
Figure 34.
AM AVOIDANCE EMI REDUCTION
To reduce interference in the AM radio band, the TPA3116D2 has the ability to change the switching frequency
via AM<2:0> pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its
second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the
switching frequency being demodulated by the AM radio.
Table 6. AM Frequencies
US
EUROPEAN
AM FREQUENCY (kHz)
522-540
AM FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
AM2
AM1
AM0
540-917
917-1125
1125-1375
1375-1547
540-914
500
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
1
914-1122
1122-1373
1373-1548
600 (or 400)
500
600 (or 400)
1547-1700
1548-1701
600 (or 500)
PRINTED-CIRCUIT BOARD (PCB LAYOUT)
The TPA3116D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
•
Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to
the PVCC connections at each end of the chip.
•
•
Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at
the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2.
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SLOS708B –APRIL 2012–REVISED MAY 2012
•
Output filter — The ferrite EMI filter (see Figure 34) should be placed as close to the output terminals as
possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded.
For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
HEAT SINK USED ON THE EVM
The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum
heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com.
50.00 0.38
[1.969 .015]
SINK LENGTH
MACHINE THESE
3 EDGES AFTER
0.00
ANODIZATION
25.00
–0.60
3.00
[.118]
+.000
–.024
SINK HEIGHT
.984
1.00
[.118]
6.35
[.250]
3.00
[.118]
13.90 0.38
[.547 .015]
BASE WIDTH
6.95
[.274]
5.00
[.197]
40.00
[1.575]
2X 4-40 x 6.5
Figure 35. EVM Heatsink
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having
airflow will lower the requirement for the heat sink size and smaller types can be used.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPA3116D2DAD
TPA3116D2DADR
TPA3118D2DAP
TPA3118D2DAPR
TPA3130D2DAP
TPA3130D2DAPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
HTSSOP
DAD
DAD
DAP
DAP
DAP
DAP
32
32
32
32
32
32
46
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
2000
46
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3116D2DADR
TPA3118D2DAPR
TPA3130D2DAPR
HTSSOP DAD
32
32
32
2000
2000
2000
330.0
330.0
330.0
24.4
24.4
24.4
8.6
8.6
8.6
11.5
11.5
11.5
1.6
1.6
1.6
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
HTSSOP
HTSSOP
DAP
DAP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPA3116D2DADR
TPA3118D2DAPR
TPA3130D2DAPR
HTSSOP
HTSSOP
HTSSOP
DAD
DAP
DAP
32
32
32
2000
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
41.0
Pack Materials-Page 2
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